diff --git a/.github/workflows/arty-a7-toy.yml b/.github/workflows/arty-a7-toy.yml index 84962fb..15b3058 100644 --- a/.github/workflows/arty-a7-toy.yml +++ b/.github/workflows/arty-a7-toy.yml @@ -26,12 +26,20 @@ jobs: working-directory: platforms/arty-a7-toy run: | python3 scripts/verify_target.py + python3 scripts/verify_pr10_evidence.py + python3 scripts/verify_rob_evidence.py + python3 scripts/verify_rob_pr10_full.py python3 scripts/verify_linux_gemmini_archive.py python3 scripts/verify_linux_gemmini.py --build-record evidence/2026-10-12/linux-gemmini/build/LINUX_GEMMINI_BUILD.json --hardware-result evidence/2026-10-12/linux-gemmini/hardware/RESULT.json python3 -m compileall -q scripts tests host software - bash -n scripts/elaborate.sh scripts/build_test_programs.sh software/build.sh + bash -n scripts/elaborate.sh scripts/elaborate_rob_candidate.sh scripts/build_test_programs.sh software/build.sh - name: Install interface simulator - run: sudo apt-get update && sudo apt-get install -y iverilog + run: sudo apt-get update && sudo apt-get install -y iverilog tcl - name: AXI, UART/SCU and DDR loader interface tests working-directory: platforms/arty-a7-toy - run: timeout --signal=TERM --kill-after=15s 180s python3 scripts/check_board.py + run: | + timeout --signal=TERM --kill-after=15s 180s python3 scripts/check_board.py + python3 scripts/check_programming_scripts.py + python3 scripts/check_flash_guards.py + python3 scripts/check_runner_status.py + python3 scripts/check_platform_mutations.py diff --git a/README.md b/README.md index db20565..8d2c936 100644 --- a/README.md +++ b/README.md @@ -14,6 +14,19 @@ The Arty A7 platforms have their own pinned Chisel build, serial loader, firmwar constraints and verification record. Follow its guide directly; the setup and demo below describe the existing Kintex-7 flow. +### Arty A7-100T 队友实板入口 + +Windows 克隆后进入 `platforms/arty-a7-toy`，安装 +`python -m pip install -r host/requirements-hardware.txt`，再执行： + +```powershell +.\run_hardware.ps1 -Port COM5 -Vivado 'D:\Xilinx\2025.1\Vivado\bin\vivado.bat' +``` + +入口自动下载固定 ROB/PR10 工程预发布、核验摘要，再复用原 Linux/Gemmini 验证器。 +无需重建位流或 Linux；没有接板可加 `-PrepareOnly`。 +请先阅读[中文准备与日志说明](platforms/arty-a7-toy/HARDWARE_TEST.md)。 + The Toy/Linux target passes complete board implementation, Linux RTL checks and a physical Arty A7-100T boot with full image readback and five Linux checks. Its PCB revision remains unconfirmed and physical Gemmini testing is pending; diff --git a/platforms/arty-a7-toy/HARDWARE_RELEASE.json b/platforms/arty-a7-toy/HARDWARE_RELEASE.json new file mode 100644 index 0000000..e581db4 --- /dev/null +++ b/platforms/arty-a7-toy/HARDWARE_RELEASE.json @@ -0,0 +1,17 @@ +{ + "tag": "arty-a7-rob-pr10-2026-10-13", + "url": "https://github.com/DangoSys/fpga/releases/download/arty-a7-rob-pr10-2026-10-13/arty-a7-rob-pr10-uart.zip", + "archive_bytes": 9666180, + "archive_sha256": "97ac0e4f624f77f40c60351279f80457c9ac21de95c81bf952ffbc2ca31dad92", + "manifest_sha256": "786d18edfa027a3e994792ee0d963ba99b3543f52eb9e71de7d175803e880d2d", + "source_commit": "9eaa67668a0db8b05653023722c3ec03f765e8d0", + "validation_input_commit": "5d20e94e6c85cce7f09424749cb9d0117023e000", + "flow": "ROB_PR10_UART", + "profile": "ROB_OPERAND_BRAM_WITH_PR10_FIXES", + "target": "xc7a100tcsg324-1", + "bitstream_sha256": "9f6f684361c049527fda09818cc8aa464f1067b75f3762305a27c5c738295942", + "payload_sha256": "e2282b5a7ddf1aa01579919aa92df483ed79e739bf5d39530e07532e164118b0", + "payload_bytes": 25797640, + "test_count": 15, + "timeout_seconds": 3600 +} diff --git a/platforms/arty-a7-toy/HARDWARE_TEST.md b/platforms/arty-a7-toy/HARDWARE_TEST.md new file mode 100644 index 0000000..35f4026 --- /dev/null +++ b/platforms/arty-a7-toy/HARDWARE_TEST.md @@ -0,0 +1,72 @@ +# 从仓库直接运行实板验证 + +目标：**Digilent Arty A7-100T / XC7A100T-CSG324-1**。入口固定到 +`HARDWARE_RELEASE.json` 中的 ROB/PR10 UART 工程预发布，自动下载约 9.7 MB 的运行包， +核对 ZIP、清单、位流和软件摘要，再复用原 `host/check_linux_gemmini.py` 与烧录 Tcl。 +无需重新编译硬件、构建 Linux、拉取子模块或登录研究服务器。 +该位流目前通过实现和 RTL 验证，尚未取得本版实板验收结果。 + +## 首次准备 + +使用 Windows、64 位 Python 3.10+、Vivado Hardware Manager 与 Digilent/FTDI 驱动。 +仅下载和烧录不要求安装 Artix-7 综合器件包。入口当前随 PR #10 提交；尚未合并时， +先在仓库根目录取得该 PR，然后进入平台目录： + +```powershell +git fetch origin pull/10/head +git switch --detach FETCH_HEAD +cd platforms/arty-a7-toy +python -m pip install -r host/requirements-hardware.txt +``` + +连接板卡 **PROG/UART USB**，保持 **SW0=0**，关闭其他串口工具。设备管理器中的 +USB Serial Port 对应 FT2232 的 **UART B**；请按实际端口修改 `COM5`。 +驱动应提供 `C:\Windows\System32\ftd2xx.dll`。默认速率为 1,000,000，8N1。 +PCB 修订号仍未确认，当前 DDR 使用官方 Rev E 参数；其他板卡不在这个入口的适用范围。 + +## 一条命令加载并验证 + +```powershell +.\run_hardware.ps1 -Port COM5 -Vivado 'D:\Xilinx\2025.1\Vivado\bin\vivado.bat' +``` + +Python 不在 PATH 时加 `-Python 'D:\python\python.exe'`。可以从任意工作目录以完整路径 +调用脚本，包含空格的路径需加引号。入口先检查驱动、串口和 Vivado 路径，再配置 FPGA、 +将约 25.8 MB 软件加载到 DDR 并完整读回、启动 Linux、执行 15 个程序。 +覆盖五项 Linux 系统检查、原 13 项 Gemmini 测试及 16 项 OS/WS 矩阵对照。 +DDR 传输与读回需要数分钟，进度直接显示，实板验证总超时一小时。 + +成功必须出现 `PASS_LINUX_AND_GEMMINI_HARDWARE`，15 个程序均返回 0，DDR 读回长度、 +位流与镜像摘要一致。失败或超时返回非零；不复用旧 PASS，不把离线准备标成实板通过。 + +## 离线准备 / GitHub 下载不通 + +没有接板时，只准备文件： + +```powershell +.\run_hardware.ps1 -PrepareOnly +``` + +它不访问串口、不调用 Vivado，结果为 `PREPARED_NOT_HARDWARE_TESTED`。 +若自动下载失败，从[固定 Release](https://github.com/DangoSys/fpga/releases/tag/arty-a7-rob-pr10-2026-10-13) +下载 `arty-a7-rob-pr10-uart.zip`，无需手动解压，再执行： + +```powershell +.\run_hardware.ps1 -PrepareOnly -BundleZip 'D:\Downloads\arty-a7-rob-pr10-uart.zip' +# 接板后仍可指定这个 ZIP，或者直接运行前面的一条命令，入口会复用已校验缓存。 +``` + +缓存位于 `build/hardware-release//`。每次复用均重新校验，摘要错误会终止， +请勿编辑缓存中的源码、清单或镜像；切换版本需更新固定发布信息并重新验证。 + +## 给队友检查的日志 + +每次入口记录独立写入 `build/hardware-entry/<时间-随机标识>/RUN.json`，包含发布版本、 +摘要、状态以及本次原验证器 `RESULT.json` 的路径。 +原始编程日志、Linux 串口输出和每个程序的退出码位于 +`build/hardware-release//bundle/build/hardware-gemmini-<日期-随机标识>/`。 +分享本轮目录及入口记录即可；历史测试日志不覆盖。 + +此流程临时修改 FPGA SRAM 与 DDR，**不擦写 Flash**。掉电后需要重跑；它与已发布的 +Flash 冷启动流程分别使用对应产物。完整能力和 MMIO 同步异常限制见 +[完整验证报告](evidence/2026-10-13/rob-pr10-full/REPORT.md)。 diff --git a/platforms/arty-a7-toy/README.md b/platforms/arty-a7-toy/README.md index 042cfd9..aff8429 100644 --- a/platforms/arty-a7-toy/README.md +++ b/platforms/arty-a7-toy/README.md @@ -1,5 +1,25 @@ # Toy/Linux on Arty A7-100T +## 队友直接跑实板验证 + +克隆后无需构建工具链或子模块，在 Windows 进入本目录： + +```powershell +python -m pip install -r host/requirements-hardware.txt +.\run_hardware.ps1 -Port COM5 -Vivado 'D:\Xilinx\2025.1\Vivado\bin\vivado.bat' +``` + +替换真实串口与 Vivado 路径。入口自动获取固定 ROB/PR10 发布包、核对摘要，并调用原 +Linux/Gemmini 实板验证器；没有接板可先运行 `.\run_hardware.ps1 -PrepareOnly`。 +详细准备、离线 ZIP、超时和日志位置见[中文实板验证指南](HARDWARE_TEST.md)。 + +## 当前源码修复的验收范围 + +PR #10 修正了平台 AXI 写错误响应与烧录脚本校验，评估、回归和复现命令见 +[修正说明](REVIEW_FIXES.md)。ROB 优化与本次修复已完成重新生成、整板实现及完整 RTL +回归，产物与原文报告见 [工程预发布下载](ROB_PR10_DOWNLOADS.md)。本轮没有连接板卡， +新位流尚无实物资格；下述历史实物记录仍属于其归档的旧源码/位流。 + A Chisel-generated Toy platform for `xc7a100tcsg324-1`, with CPU, Sv39, full FP16/32/64 support and Gemmini 8×8. Complete board implementation, timing, CDC checks and Linux RTL tests pass. On 2026-10-12 the connected board was programmed, @@ -15,6 +35,14 @@ it boots the original Linux image and passes all five system checks without reloading from the host. See [Flash evidence](evidence/2026-10-12/flash/README.md). Runtime DDR and changes to the initramfs remain volatile. +## 2026-10-12：可选 ROB 存储优化 + +新增 [ROB RAM 候选](ROB_RAM.md)，整板布线后减少 484 LUT、1,657 FF 和 +84 Slice，增加 2 BRAM tile。CPU/Gemmini/Linux RTL 回归周期数保持不变； +后续实物复测已通过完整镜像读回与两轮 Linux/Gemmini 回归，日志追加在 +[PR #9](https://github.com/DangoSys/fpga/pull/9)。默认构建与既有发布版本保留 +原寄存器路径；候选的 Flash 冷启动尚未验证。 + ## 2026-10-12：Linux/Gemmini 实物回归 按标准 rootfs/bbkernel 流程构建的新镜像已完成全部 DDR 读回和实物启动； diff --git a/platforms/arty-a7-toy/REVIEW_FIXES.md b/platforms/arty-a7-toy/REVIEW_FIXES.md new file mode 100644 index 0000000..afed7cb --- /dev/null +++ b/platforms/arty-a7-toy/REVIEW_FIXES.md @@ -0,0 +1,69 @@ +# PR #10 评估与修正 + +先评估原提交 `f20b504`，再修正。本次保持已有芯片配置和公开验收记录， +不重新编程板卡、不修改 Flash，也不把旧位流认定为已包含新的 RTL 修复。 + +## 与当前版本的关系 + +#10 基于 main `4bdd4e4`。逐文件比较发现，它涉及的五个文件在当前 ROB 工作分支 +`8f7bd63` 中仍与该基线逐字节相同，因此问题没有因 ROB 优化或新日志而消失。 +五文件局部补丁对当前分支执行 `git apply --check` 通过。修正没有复制旧 chip +配置、恢复旧 RTL 核心或覆盖 #9/#11 的新资料。 + +## 逐项结论 + +| 原改动 | 评估 | 最终处理 | +|---|---|---| +| `scu_bresp` 去掉归约 OR | 正确；`10` 被压成 `01`，SLVERR 误变 EXOKAY | 保留；增加真实 SCU 到 CPU 输入端口的测试 | +| 预打包镜像的 `assert` 改显式异常 | 正确；`python -O` 会删除 assert | 保留；对四项记录字段做普通/-O 篡改检查 | +| 三个 Tcl 入口用 `!命令返回值` | 缺乏统一布尔返回值依据；可拒绝合法成功 | 改用原生 Tcl 异常处理，增加配置状态检查 | + +本机 Vivado 2025.1 随附文档及 +[UG835 设备命令](https://docs.amd.com/r/2025.1-English/ug835-vivado-tcl-commands/program_hw_devices) +描述硬件对象/执行记录返回值； +[Flash 命令](https://docs.amd.com/r/2025.1-English/ug835-vivado-tcl-commands/program_hw_cfgmem) +描述成功返回记录、失败报错。没有支持“这三个命令统一失败返回 0、不抛错”的依据。 +离线按兼容返回值注入，原 #10 的三个脚本都在成功路径报布尔类型错误。 +本机实际 `vivado.bat -mode batch` 执行只含 `error` 的离线脚本，退出码为 1。 +这验证错误传播，不是一次真实编程失败实验。 + +最终 Tcl 通过 `catch` 的状态识别异常，保留原错误选项；JTAG/Flash bridge +编程后刷新并要求 DONE/EOS 为 1、CRC_ERROR 为 0。Flash 备份命令成功且完整 +16 MiB 后才允许擦写；编程/verify 报异常就停止，不打印成功标志。 + +## 对原 PR 其他观察的评估 + +- `axi_fullwidth` 的 `addr + len×bytes_per_beat` 表示最后一拍起点，配合已有 + 对齐和大小检查可以判定范围；不能直接改成 `len+1`。跨 4 KiB 拒绝符合 + [AXI 协议要求](https://docs.amd.com/r/en-US/pg101-axi-protocol-checker/AXI-Protocol-Checks-and-Descriptions)。 + 这部分 RTL 本次保留原值。 +- Flash observer 对瞬时断连可能报假失败的观察有合理性；改变它可能影响真实 + 冷启动的断连语义，本次不改。 +- 异步构建 worker 的退出码不足以表达任务最终状态，这个观察成立；现有 + `RUN.json`/位流检查契约保留，本次不扩展到构建调度器。 + +## 验证与资格 + +- 原 #10 Tcl 的成功路径错误已离线复现；修正后 20 个返回值、异常、DONE/EOS/CRC + 与短备份用例通过。fixture 不加载 Vivado，不连接硬件。 +- Python 普通/-O 两种模式，各覆盖有效记录及四项篡改，共 10 项通过；使用 + 替代 Observer 在编程边界停止，测试不会访问串口或执行 Vivado。 +- 接口回归四组通过：原 AXI fullwidth、SCU、DDR loader，加新增平台 B 响应。 + 新用例使用实际平台与 SCU，检查正常写、非法地址、非对齐和错误 burst， + 从 CPU 输入端检查响应、ID 及背压稳定性。仅使用 Chisel 端口 fixture，未模拟 CPU 行为。 +- 同一用例对当前旧平台反测，在 `0x60030000` 得到 `01` 而预期 `10`，按预期失败； + 修正版本通过。日志在 `evidence/2026-10-12/pr10-review/`。 + +SOURCE_LOCK 更新当前源码摘要；历史 Tcl/位流/实物日志保持原字节。 +历史验收校验绑定归档中的原脚本，当前脚本由新摘要与测试绑定，不继承原脚本实物资格。 +核心生成摘要仍保留原值。板级 RTL 已变，新位流还需重新综合、布线和实物验收； +2026-10-12 的 ROB 实板记录使用 #11 的旧接口版本，未包含本次 AXI 修复。 + +## 2026-10-13：新版自检 + +自检发现并修正两处验证问题：复跑失败可能遗留旧 PASS 结果；原平台测试未直接检查 +背压期间 BVALID 持续有效。新的离线入口启动即写 RUNNING，异常写 FAILED；平台用例 +同时检查 BVALID/响应/ID，并检查响应握手后有效信号撤销。 +原四组接口、20 项 Tcl 和 10 项镜像检查再次通过，新增实际入口失败注入和 RTL 错误 +注入证明两个缺口已堵住。测试源码、日志与精确边界见 +[自检报告](evidence/2026-10-13/pr10-selfcheck/REPORT.md)。原 10 月 12 日档案保持原字节。 diff --git a/platforms/arty-a7-toy/ROB_PR10_DOWNLOADS.md b/platforms/arty-a7-toy/ROB_PR10_DOWNLOADS.md new file mode 100644 index 0000000..257173e --- /dev/null +++ b/platforms/arty-a7-toy/ROB_PR10_DOWNLOADS.md @@ -0,0 +1,34 @@ +# ROB/PR10 工程预发布下载 + +目标为 **Digilent Arty A7-100T / XC7A100T-CSG324-1**。本版合并 ROB 操作数 BRAM 优化 +和 PR10 修复，保持 CPU、Sv39、FP16/32/64、Gemmini 8×8 及既有接口。 +通过完整实现和 RTL 回归；用户本轮无法连接板卡，**新位流尚未做实板验证**。 +资源、原文报告、测试与已知 MMIO 限制见 [完整报告](evidence/2026-10-13/rob-pr10-full/REPORT.md)。 + +[GitHub 工程预发布](https://github.com/DangoSys/fpga/releases/tag/arty-a7-rob-pr10-2026-10-13) +提供以下文件；旧 2026-10-12 的 UART/Flash 附件保持原值。 + +| 文件 | 用途 | +|---|---| +| [UART 完整包](https://github.com/DangoSys/fpga/releases/download/arty-a7-rob-pr10-2026-10-13/arty-a7-rob-pr10-uart.zip) | 位流、配套软件、Tcl、板级/生成 RTL、中文说明和一键加载/测试入口 | +| [源码包](https://github.com/DangoSys/fpga/releases/download/arty-a7-rob-pr10-2026-10-13/arty-a7-rob-pr10-sources.zip) | 仓库快照、实际生成 RTL、原 FPU 基线、软件依赖源码/配置、许可证和验证证据 | +| [位流](https://github.com/DangoSys/fpga/releases/download/arty-a7-rob-pr10-2026-10-13/toy_a7_rob_pr10_uart.bit) | 单独临时 JTAG 配置；仍需加载软件到 DDR | +| [烧录 Tcl](https://github.com/DangoSys/fpga/releases/download/arty-a7-rob-pr10-2026-10-13/program_arty.tcl) | 原生异常和 DONE/EOS/CRC 检查，可从任意目录调用 | +| [实现 Tcl](https://github.com/DangoSys/fpga/releases/download/arty-a7-rob-pr10-2026-10-13/build_board.tcl) | 配合完整包的 board/ 和生成 RTL 重建，不是单文件构建环境 | + +位流 SHA256 为 `9f6f684361c049527fda09818cc8aa464f1067b75f3762305a27c5c738295942`。 +下载后用 Release 的 SHA256SUMS.txt 检查附件，ZIP 内 verify_bundle.py 检查全部内容。 +RELEASE_MANIFEST.json 同时记录发布源码提交与实际验证输入提交，测试/文档追加不伪装成重新构建。 + +Windows 解压完整包后，按真实路径执行： + +已克隆仓库的队友可以直接使用仓库的 `run_hardware.ps1` 自动下载并验证这个固定版本， +无需手动解压；见[仓库实板入口](HARDWARE_TEST.md)。下面的 `run_uart.ps1` 仍适用于已解压包。 + +```powershell +.\run_uart.ps1 -Port COM5 -Vivado 'D:\Xilinx\2025.1\Vivado\bin\vivado.bat' +``` + +入口读取包内的新位流摘要，不沿用旧位流的默认值。临时 JTAG→软件完整 DDR 读回→Linux/ +Gemmini 测试，日志留在新 build/ 目录。仅用 Hardware Manager 即可烧录；重建需要 Artix-7 +器件支持。本包不是 Flash 固化包，掉电后须重载，不能替换旧 Flash 包的配套 MCS。 diff --git a/platforms/arty-a7-toy/ROB_RAM.md b/platforms/arty-a7-toy/ROB_RAM.md new file mode 100644 index 0000000..3c0c7d5 --- /dev/null +++ b/platforms/arty-a7-toy/ROB_RAM.md @@ -0,0 +1,84 @@ +# ROB 操作数存储优化 + +本轮保留 CPU、Sv39、完整 FPU、Gemmini 8×8、23 项 Ball 指令、16-entry ROB、 +bank/缓存容量和板级端口，将 ROB 的两份 64 位操作数移入同步 RAM。 +改动在 Chisel 覆盖层，生成的 RTL 不手工重写计算逻辑。 + +## 实现方式 + +`patches/framework/GlobalROB.scala` 的 `useOperandRam` 默认关闭，保留原发布路径。 +用 `sbt -Dfpga.robOperandRam=true` 显式启用；单元测试直接指定两条路径进行比较。 +新 RAM 为 16×128、1R1W，allocation +写入，选中 issue 指针时读取。既有指针级提供读取周期，背压期间重复读取该指针； +替换指针时，旧响应先进入既有 payload 级，新读取在下一个周期到达。 +控制标志、依赖状态、MSET 提交小字段仍用寄存器。 + +原完整寄存器观察用于 DPI trace/commit，不删调试语义；DPI disabled 的 FPGA +综合会消除仅被调试使用的数据位。禁止同址读写的断言有效，RAM 内容不复位， +有效位和发射状态仍复位。复位后不会把旧 RAM 数据当作新指令执行。 + +`prepare_fpga_memories.py --block-memory robOperands_ext` 显式选择 BRAM；浅层 +其他 RAM 的原映射策略不变。`prepare_rob_candidate.py` 核验全部架构 profile +字段与旧目标相同，并核对既有 memory 几何参数，之后只对新 RAM 指定 BRAM。 + +## 已完成的功能验证 + +- RAM/register 路径逐周期比较通过，共 8,029 周期，含满队列、绕回、背压和两次 + 中途复位；另以接受时保存的完整命令核验 issue 操作数，避免两条路径共同出错漏检。 +- 七类 memory 与实际原 Chisel RTL/独立 scoreboard 比较通过，覆盖全部深度、 + 写 mask、enable、双端口定义内行为及两拍之间输出稳定性。 +- 板级 AXI、SCU、CRC loader 检查通过；原测试二进制不改，四组周期数与基线完全相同： + +| 用例 | 基线周期 | 候选周期 | +|---|---:|---:| +| CPU/Sv39/FPU/AMO/cache/interrupt | 709,434 | 709,434 | +| 原 13 项 Gemmini | 251,063 | 251,063 | +| OS/WS 分块循环 | 684,219 | 684,219 | +| 非对齐/跨页 DMA | 1,914,839 | 1,914,839 | + +完整生成与绑定已通过；候选核心 SHA256 为 +`31e7e07f94d08208dbb564edf9546240df26ff834935bfb646b71b541d875fb9`。 +Linux RTL 启动、串口命令和五项用户态检查通过，273,506,752 周期与基线相同。 +25 MHz UART 整板实现通过并生成位流；完整报告见 +[本轮记录](evidence/2026-10-12/rob-ram/REPORT.md)。该初始档案保持实现阶段的历史状态。 +后续实物复测已通过完整镜像读回与两轮各 15 个 Linux/Gemmini 程序，新增记录在 +[PR #9](https://github.com/DangoSys/fpga/pull/9)，绑定同一份候选位流摘要。 + +| 布线后资源 | 同条件 UART 基线 | ROB RAM 候选 | 变化 | +|---|---:|---:|---:| +| 物理 LUT | 54,413 | 53,929 | −484 | +| FF | 35,600 | 33,943 | −1,657 | +| 占用 Slice | 15,663 | 15,579 | −84 | +| BRAM tile | 29 | 31 | +2 | +| DSP | 117 | 117 | 0 | + +空闲 Slice 从 187 增至 271，占用仍为 98.29%，不能据此判断足够恢复其他 Ball。 +WNS +1.276 ns、WHS +0.012 ns，无布线错误或 Critical DRC/CDC；普通警告保留。 +DSP 仍包含全部 64 个 PE。这里比较 UART 目标，未混用 Flash 目标的资源报告。 + +## 复现候选 + +在隔离 Linux 工具链目录执行，原基线 SRAM 清单从已验证旧版本的 +`build/serial-bound/MEMORY_MANIFEST.json` 取得；不能传入候选自身的清单。 +构建代理仍遵守 AGENTS 的 MCP 规则，本轮用户已明确授权隔离直接调用作为例外。 + +```bash +bash scripts/elaborate_rob_candidate.sh +python3 tests/check_fpga_memories.py --original build/serial-reference/ToyLinuxChip.sv --bound build/serial-bound +bash scripts/build_test_programs.sh +python3 scripts/run_board_regression.py +VIVADO=/path/to/vivado python3 scripts/start_rob_board_build.py +bash software/build.sh +python3 scripts/check_board_linux.py +python3 scripts/verify_rob_evidence.py +``` + +回归需按原流程准备 `cpu-smoke`、`gemmini-tests`、`loop-stress` 和 `dma-beat64` +测试二进制；本次从旧隔离目录只读复用并在结果里记录摘要。Linux 检查使用同一份 +原标准 payload，执行 `scripts/check_board_linux.py`，结果在 `build/board-linux-final/`。 + +候选 launcher 使用原整板 Tcl、原 25 MHz 约束和原策略，外层一小时 timeout。 +其结果不继承旧实物资格。默认 `elaborate.sh` 仍受旧 `verify_target.py --core` +摘要门限保护；候选走上述独立入口和 `verify_rob_evidence.py --core`。 +后续候选已临时上板并通过上述回归；其 Flash 启动版本仍未生成或验证， +现有发布包不替换。 diff --git a/platforms/arty-a7-toy/SOURCE_LOCK.json b/platforms/arty-a7-toy/SOURCE_LOCK.json index 49248f5..141fdd1 100644 --- a/platforms/arty-a7-toy/SOURCE_LOCK.json +++ b/platforms/arty-a7-toy/SOURCE_LOCK.json @@ -6,7 +6,12 @@ ".gitignore": "5eaf4f0d4cbefc5292732eb17cd984839a8fe4cfc65f39352c187fd73c95947a", ".jvmopts": "a66471d84e6e2ed0c3c40d5ebbc237d268ed9b04f3528ef22e967a2bd4e8aa44", "FLASH_BOOT.md": "471bcd9c9704bd2eedf11880c27c48d0505a56498e62e68ada84d5cd5ed70686", - "README.md": "d1a1326934b5f211f617b0528ca6d85fde5771d8ca32f0c85add7ffcb8310264", + "HARDWARE_RELEASE.json": "b4ab261966fbb266b9a778fd0972539a34506242ddbcd0206efd44db4679f0e5", + "HARDWARE_TEST.md": "9c39c55cf7982797a4044c5b328dd2c2cb4d8345a2bc8004c7a1f2160b22f3a0", + "README.md": "adbea71188260cb47f657cdbb0cb1c3d6fc4b085bb1b4787ec40e860c4029be0", + "REVIEW_FIXES.md": "baa81a32dbbc964f8c8a2dfe515f22ae9f3cb91d68e4190cd8c79cb1117441f8", + "ROB_PR10_DOWNLOADS.md": "645c7c809fca17d298a795cb9a374d3829996c0e47df3003515078df5bad919b", + "ROB_RAM.md": "2160a3dc8130464cf6d54aa03d64eadb13d4fc28c3a64cabfe54c3d5dfed86de", "SOFTWARE_BASELINE.json": "3a5c9f65771e6fd7f8172674baf22263ba7c2d9244993c9162ba526344a7b0aa", "THIRDPARTY.md": "02ed1d3ddd4fc26a8b1580eb4948ff6cf4f548c0434c89f1c6c2220bed3d4a42", "UPSTREAM_MANIFEST.json": "c4a96343e318c452420cf86b34d6008140560eeffa91cd85b4b87b229717c9be", @@ -16,16 +21,16 @@ "board/arty_a7.xdc": "f13869ba386038557084adabafeb5255943d0b67f1db4b88fd907e4f095d016f", "board/axi_fullwidth.sv": "bf07ae27724dbd0a361d732dfb57109f06beef207c47a066d400cb06d7f07d5a", "board/axi_scu.sv": "ee77bf641d61811b4c1faea845752850c22461a63b4cdfd3d6f9cd223e6c2fc2", - "board/backup_flash.tcl": "63d84e9055f00bd7ed97485912b0c8db83bee19b6950ba4c12fc3f9a639c3ea3", + "board/backup_flash.tcl": "fa9185afad3537bf15b4f2f0c952a4eebf9d6c5693619819ff5e57897ce6a86d", "board/build_board.tcl": "04f25ca8f6da06b37aec7156ec47def13da0bac88294466b08fb838bc462ba8d", "board/ddr_uart_loader.sv": "980f4cd2e3fa2a00b66143f879bc749ed952c2c1e54331460821bac0300c43d6", "board/flash_boot.xdc": "bbf9e250ae28dcc4f54d00effd918811f723a7563b4ceacb7b1d03a29151f4ea", "board/flash_spi_byte.sv": "4d1fac5238f31fb3a69a58d1aca9ccec722e833d788113b94d86c6a1b861045a", "board/loader_axi.sv": "05609b0870054ea675aedb406f6215cd456f18db6d6428b461cbae03d9a662f4", "board/make_flash_image.tcl": "69a70d18a519f8fa156981e9ab024dce5c7bc91733c5b6cf3b9045658415334b", - "board/program_arty.tcl": "fbb62bafb6df602b0f5f638fb05ae4ecc90494ac162b9a5f5ac314200f7a241c", - "board/program_flash.tcl": "a2cfa55d7f61f5cecd74e68e2bbede9c535399291eea274e76fe416bdc8d3626", - "board/toy_a7_platform.sv": "01fe1f8e2621a1a023ac3b8d91758868b190760f6e706ae1d34a67857b96d846", + "board/program_arty.tcl": "8af4c07627910536079eb4be647c6f0f447882950588c40588cdc571a72133ac", + "board/program_flash.tcl": "f9bf2b6fc6c9fdd268c308f417831c94707b464bbae75a5d2cc416f4c92bf424", + "board/toy_a7_platform.sv": "f9bc06535b7de19a6b1b501f06effe90519fd43a78e669ab7425d301662540b8", "board/toy_a7_top.sv": "c8af97f543b8ae5d6dc21a85ba13b16a28fe3ba5bf93f8051c9e38c99f3350bd", "board/uart_rx.sv": "0b35263884577324f146ff7fd516e5b561dcc8787e0d8ad599669bac1958406d", "board/uart_tx.sv": "c20d420fc20be4f6313bdde5abc45ef0b9f8e93bf75350dd9951bc8868b3b65c", @@ -40,9 +45,12 @@ "boot/flash_boot.c": "98d353e13a32fe3788a78a59da664aeb3b8ea7bc8b1d15951e377122bd8a593e", "boot/flash_start.S": "10a3c3dae05a2b3d99a58778a2815187e3fc34cd4200cfc8ff766602a022894c", "boot/requirements.txt": "f957a1197432942b8e01f3ba222639d0a341a93360a6bad23a99b6a9c3496a5f", - "build.sbt": "e41d7a540c61879ccf1adde9cb1dae2a203b0f619c625a51838c323cce24c966", + "build.sbt": "c4581ef9345fb3d3bd326c95b6f46a0ae8538ed6c0cc22ac675bd0c9a10fd407", "config/gemmini-8.toml": "7a34b166586b25e2bcb0849764a4f0d969b60493ba2d8d59f4e2176771c07195", "dependencies.json": "932815e2f03b3caf8a1ab4c17baa9bc1962633d1fe8a26168f97d60f0a6844c4", + "distribution-rob/README.md": "a3b102378a62b1c022de3fcb7807023a7e65f0d32a6092dbc344429260ffb907", + "distribution-rob/run_uart.ps1": "3843dcb6c9abadf610fdc971016242d524de357778933909aa2aa8f8327948e7", + "distribution-rob/verify_bundle.py": "e7e33932bb987a9c524c4b4fce42d18262ce31c89b2530e9345db5d488db901b", "evidence/2026-10-11/BOARD_REPORT.md": "a349e25ba696c037c54a7a44bcadda163dc43092f6dc5c573968db6b27908366", "evidence/2026-10-11/BOARD_RESULT.json": "ee1568766df33ee52a9a0a624b017939c499ef507cb074699d15959515297ab3", "evidence/2026-10-11/GEMMINI_CORRECT_REPORT.md": "f8147d1e0e242e5d6f4bd32f3195ab593c3245874bc67f2e61cd8c48dc07ac2d", @@ -243,14 +251,691 @@ "evidence/2026-10-12/linux-gemmini/sources/software/prepare_gemmini_linux.py": "358cee302a2a8ee6672cbf4c830776a6047dc33793a272a89f7343729ca0b3ec", "evidence/2026-10-12/linux-gemmini/watchdog/RESULT.json": "efc60f10a891ba2e224ee3130d4e776c00fc04eea5cc2e522690f85ddfb0475e", "evidence/2026-10-12/linux-gemmini/watchdog/check.log": "58de5f54346dfd805737aea528347a5fa9430a7a0962964a08b349ede52b6303", + "evidence/2026-10-12/pr10-review/MANIFEST.json": "e12ed1be093e9cf3d79726822e92c3ff95159365d9abc2f6366ec6966a2db29d", + "evidence/2026-10-12/pr10-review/README.md": "27339e474128e71804b6c1ed5de2d0c1fe1a81ccd197e992b398b2567aefcc5a", + "evidence/2026-10-12/pr10-review/RESULT.json": "92056e8748cdf031b4ce0a9db0cae2343b986da03dbca829dd2842c1da718704", + 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"eb3637a141d4ef30659eb8086d1d59ec159c710ee81d9f8e64fc38b811632799", "scripts/remote_linux_gemmini.py": "2221acd85bc1876d7730f15bb01f0b50629c2a9b9645b4d12cb74e566cf1e686", "scripts/resolve_config.py": "1c4fb7d8533e659c7f8cb9e0ef5eb93f06d29a51d6b3e2449efe648f8f74000d", "scripts/run_board_regression.py": "7302be4d5517eb315eb37b3ff8972bf17e2fe42990ae1fb6702c43c632515bfd", + "scripts/run_hardware.py": "f380d985bb33baa8b0a3c436cd31308309dc3a272da1b6b7a04b7083df897eec", "scripts/start_board_build.py": "04c5a521bcd7014774e6b476e8395bde134de9096bb22e6d6b6f200bf4311c83", + "scripts/start_rob_board_build.py": "0c99afafe707a51fba935a59076288a50b7179e01d330f8a1294c81ee1956cf9", "scripts/verify_flash_evidence.py": "6db7b0dcc7323ba07ec6f17d0a09f04b321f8bdd24582ca49184dd654c1ebd45", - "scripts/verify_hardware_evidence.py": "60f3555a6b6ac6a9f567cf1b22caca9755bd4179dcea1f6731a70f8bd26a1202", + "scripts/verify_hardware_evidence.py": "1c95ed937bc109361738f0ab7e9c80b1b9ab85707b0c087692e1d59651c948a8", "scripts/verify_linux_gemmini.py": "1413703dfa42a6be6ac60e0df6bf3eb95ce8b50671a3a803c7421302eace7b2b", "scripts/verify_linux_gemmini_archive.py": "cf8ab6737b2ad3525cf91e528aab64d78261146dec7473596d321812f3bad5e0", + "scripts/verify_pr10_evidence.py": "676df59b35d28e88cf8d90ee832be4000e5cb57587ac751088f30f3619cf017b", + "scripts/verify_rob_evidence.py": "584033d959522151572deb863c8213ef4ffc236e9ea60beb5dee1cb21fac0a1a", + "scripts/verify_rob_pr10_full.py": "0a2a978366abab63e0b7ffd3533564dc33047b8d3ec88fd716ea4df273d90c85", "scripts/verify_target.py": "39bdd529e55f2b36bed4ba6b10a4b0a400fcb685f6f3e5886d537e8c549932cd", "software/GEMMINI_LINUX.md": "31d991de14e315a1cf8ca24f5d3715a25a13d8601c8334687730a5b47959a963", "software/MODEL_COMPATIBILITY.md": "1e3a78574d019f4a3e1442b899cc654f2c5a3e41cf55a7650610eed75618a1cf", @@ -313,6 +1016,7 @@ "software/prepare_gemmini_linux.py": "358cee302a2a8ee6672cbf4c830776a6047dc33793a272a89f7343729ca0b3ec", "software/prepare_platform.py": "f053463897045e1929d65aa9614b7b871c1c6c342f1f15865793883c858f3d61", "src/main/scala/EmitFmaChecks.scala": "1d6eef40cefb36aaf0ce73838f2954cd89d09ad8c97244a2ac346da7137dccfd", + "src/main/scala/EmitGlobalRobCheck.scala": "5d366fce3e96278f60c648dc114896246b5c595c8ef783986524e6583c490a05", "src/main/scala/EmitGroupQueryCheck.scala": "ae3a7bb5a7d951109596bc3e481a9a275e14f04a7cf6ec28084d50f354122ee1", "src/main/scala/EmitPeChecks.scala": "38a88a8a59dcbdf1b4bf3b833679800c5e8505c18782f13719a7e7ec11fd100e", "src/main/scala/EmitRoundShiftChecks.scala": "964a7631e50fe9a7a6024fbcb3c4ae857ea49a6c77435ab1ec269e510a0af7b0", @@ -321,13 +1025,15 @@ "src/main/scala/ReferencePE.scala": "6afff2af2a328fc38fa28c8c20c62906a49e55753422b96edf9515241cec7f6c", "src/main/scala/ToyLinuxChip.scala": "d2c1bc12c9896f240ffb054f6d656076b0c367258fdd0764d58389de51c909e5", "src/main/scala/ToyLinuxConfig.scala": "6e4afd1fc5705996b7995faa5d94867ae80102f7ecf28a1ab8b0dbc1b4d44c14", + "tests/PLATFORM_PORTS_MANIFEST.json": "5456ad060837d30818d6084b194896714921617b11dcada5ac897bc1c655f1dc", "tests/REFERENCE_MANIFEST.json": "de4c11a8bca5bf8bb0fba0eada731177772756f307abd5523bbe5d60ffe3ff25", + "tests/ToyLinuxChipPorts.sv": "e4c06220cd7025972d432b06c452e85c62bd2cfccad618b2b993499b62e6621a", "tests/axi_smoke_memory.sv": "7d0d410549217e73d319b807488812da06d54404a50fce484e1b527ea0e6632d", "tests/board_loader_template.sv": "34be31c066ec317d5a1053d6e840145eb0af78766707915294a01cb96ec9b766", "tests/check_cpu_smoke.py": "4e4ddc8df87550ebef7d0faa333833753d78b1409b01b64401de4ae600ecf00c", "tests/check_dma_beat64.py": "c3f706adcf0bb8683825404b5342d56ac9587941678224106bb9c3d9289a01a2", "tests/check_fpga_memories.py": "23d30b55b8aa909c6b4cda56a7e40d6c0be9e7d9bbd06f5ef8e8abf33400df76", - "tests/check_fpu_shared.py": "4c4cda836f3763e7cd8858edaea06ee2bf6db66471d246078015839b815ba9c4", + "tests/check_fpu_shared.py": "8b49410d01211a96291143e78f05b8ac79be050f305d09a445b192110b45b50e", "tests/check_gemmini.py": "b34856c40f30e20efe1ba430555b10d6be4000b77d824751b92aa83af798cb71", "tests/check_loop_stress.py": "c803fa7003da1895f49fc0ab6c4f1cefe20c9a419820927763fc0c685b9c0b2b", "tests/check_pe.py": "47d167270b7890c1545bb7e6d325e8dd2d01b2b2821ddfba8064586518cd17d0", @@ -337,9 +1043,12 @@ "tests/cpu_smoke.S": "0e65a6c334d849e19668ada71f8a43b01a849523cd126e51c213078f77a5fa9f", "tests/cpu_smoke.ld": "5c8f545686abe877ec8cfd9b6a2ed6e06c284b800e2c95937bc588a92a53568f", "tests/dma_beat64.c": "ff3654f024836d346ffbb65a4c431a7e1dbf594b9e00e87443ca1f8583832d4d", + "tests/flash_guard_probe.py": "b4e59e6cfbe6c95e99b6f733a7597043f8f394d4c10b0919fd92ab7c5372ada4", "tests/fma_differential.cpp": "790313bbd9110230d78d11d4fd81dcb1c1b40aa2ab703faccc2788a414482168", "tests/gemmini_runtime.c": "1cf5e2ab3ca95a1941ba1e6db73fa81d2d21a7d7dd33dd0871fde6509661554f", "tests/gemmini_start.S": "f583cf6a4822511546b8eef0221ccca6b91e92025d663a247a8548d4b6230c32", + "tests/mmio_error.S": "2f85c4311d9132b62943b97e7cb0bfc71be9bb505272815f1789502bcd4c0615", + "tests/mock_programming.tcl": "fd25ee00f3af89a3ec0416bd68a54f6cf7b3dac99c4a44f0c532cc36228312f1", "tests/reference/bb-tests/workloads/lib/bbhw/isa/00_fence.c": "465a066c9f4b4dc7f75a8981983ea98ea29ca9838afc179f385dbfa569e45fb8", "tests/reference/bb-tests/workloads/lib/bbhw/isa/01_barrier.c": "5e3e8ac07f8a18eb771696e668e64754ce0dc5603a997dade467b26d8298b139", "tests/reference/bb-tests/workloads/lib/bbhw/isa/16_mvout.c": "d2dddcf237327aa65828ebf713466727544d08e41f93f0471fc3813169136e41", @@ -381,7 +1090,9 @@ "tests/tb_axi_fullwidth.sv": "1d3964fab0eaa76a6f864f07a7dedf01639ba12a9400a15d0839e707ab73c4ed", "tests/tb_axi_scu.sv": "5dfd1d6cac3201f0e5188e9b73e60ade27c4551570d4b00d387301713d9fbe97", "tests/tb_fpu_rf.sv": "6d2e61c50907fee0125a0be9acf35ff718fb8615554e6b5f064cfe1e88beaf25", + "tests/tb_globalrob.sv": "8ded6fc969a05ead874fd8771b86dadafe51f7ccec54fafd55a9d48a4e7361a6", "tests/tb_group_query.sv": "3461eda9a029ef0259daff3d5f58f43894e20893dbc489a3e64c8eda83c3f921", + "tests/tb_platform_bresp.sv": "289875c2e92800307aa0b7fc5186c946ba127835473b30f626aef7baa67b4fe8", "tests/tb_round_shift.sv": "d6cad7539f59f5dcb5c572cfb983828e35665586be79fea55fdb7471f895ae4f", "tests/tb_subrob.sv": "fdaa673650870895e823491e835f351372ec18a73cdd0a188107a956c3d336a4", "tests/ws_round_edges.c": "4ba46cd06447f1c5d8fdbebf16cc3ef4780c1b0d0b74f4d8d2dc7598410d3d10", diff --git a/platforms/arty-a7-toy/board/backup_flash.tcl b/platforms/arty-a7-toy/board/backup_flash.tcl index 7c44264..ad12561 100644 --- a/platforms/arty-a7-toy/board/backup_flash.tcl +++ b/platforms/arty-a7-toy/board/backup_flash.tcl @@ -21,9 +21,19 @@ if {[llength $choices]!=1} {error "Flash part is not uniquely compatible with th create_hw_cfgmem -hw_device $device [lindex $choices 0] set memory [get_property PROGRAM.HW_CFGMEM $device] create_hw_bitstream -hw_device $device [get_property PROGRAM.HW_CFGMEM_BITFILE $device] -program_hw_devices $device +if {[catch {program_hw_devices $device} message options]} { + return -options $options "SPI bridge programming failed: $message" +} +refresh_hw_device $device +if {[get_property REGISTER.CONFIG_STATUS.BIT14_DONE_PIN $device]!=1 || + [get_property REGISTER.CONFIG_STATUS.BIT04_END_OF_STARTUP_(EOS)_STATUS $device]!=1 || + [get_property REGISTER.CONFIG_STATUS.BIT00_CRC_ERROR $device]!=0} { + error "SPI bridge configuration status rejected" +} file mkdir [file dirname $backup] -readback_hw_cfgmem -all -file $backup -format bin $memory +if {[catch {readback_hw_cfgmem -all -file $backup -format bin $memory} message options]} { + return -options $options "Flash readback failed: $message" +} if {[file size $backup]!=16777216} {error "Incomplete Flash backup"} puts "PASS FLASH_BACKUP: $part $backup bytes=16777216" close_hw_target diff --git a/platforms/arty-a7-toy/board/program_arty.tcl b/platforms/arty-a7-toy/board/program_arty.tcl index f70f054..a328bd8 100644 --- a/platforms/arty-a7-toy/board/program_arty.tcl +++ b/platforms/arty-a7-toy/board/program_arty.tcl @@ -16,8 +16,15 @@ if {[llength $devices] != 1} { error "Expected one XC7A100T; inspect the connect set device [lindex $devices 0] current_hw_device $device set_property PROGRAM.FILE $bitfile $device -program_hw_devices $device +if {[catch {program_hw_devices $device} message options]} { + return -options $options "JTAG programming failed: $message" +} refresh_hw_device $device +if {[get_property REGISTER.CONFIG_STATUS.BIT14_DONE_PIN $device]!=1 || + [get_property REGISTER.CONFIG_STATUS.BIT04_END_OF_STARTUP_(EOS)_STATUS $device]!=1 || + [get_property REGISTER.CONFIG_STATUS.BIT00_CRC_ERROR $device]!=0} { + error "JTAG configuration status rejected: expected DONE/EOS high and CRC error clear" +} puts "ARTY_JTAG_PROGRAMMED: $bitfile" close_hw_target disconnect_hw_server diff --git a/platforms/arty-a7-toy/board/program_flash.tcl b/platforms/arty-a7-toy/board/program_flash.tcl index 82a6c4f..3b47630 100644 --- a/platforms/arty-a7-toy/board/program_flash.tcl +++ b/platforms/arty-a7-toy/board/program_flash.tcl @@ -22,9 +22,19 @@ if {[llength $choices]!=1} {error "Flash part is not uniquely compatible with th create_hw_cfgmem -hw_device $device [lindex $choices 0] set memory [get_property PROGRAM.HW_CFGMEM $device] create_hw_bitstream -hw_device $device [get_property PROGRAM.HW_CFGMEM_BITFILE $device] -program_hw_devices $device +if {[catch {program_hw_devices $device} message options]} { + return -options $options "SPI bridge programming failed: $message" +} +refresh_hw_device $device +if {[get_property REGISTER.CONFIG_STATUS.BIT14_DONE_PIN $device]!=1 || + [get_property REGISTER.CONFIG_STATUS.BIT04_END_OF_STARTUP_(EOS)_STATUS $device]!=1 || + [get_property REGISTER.CONFIG_STATUS.BIT00_CRC_ERROR $device]!=0} { + error "SPI bridge configuration status rejected; Flash programming cancelled" +} file mkdir [file dirname $backup] -readback_hw_cfgmem -all -file $backup -format bin $memory +if {[catch {readback_hw_cfgmem -all -file $backup -format bin $memory} message options]} { + return -options $options "Flash backup failed; programming cancelled: $message" +} if {[file size $backup]!=16777216} {error "Incomplete backup; programming cancelled"} puts "PASS FLASH_BACKUP: $backup bytes=16777216" set_property PROGRAM.ADDRESS_RANGE use_file $memory @@ -34,7 +44,9 @@ set_property PROGRAM.ERASE 1 $memory set_property PROGRAM.CFG_PROGRAM 1 $memory set_property PROGRAM.VERIFY 1 $memory set_property PROGRAM.CHECKSUM 0 $memory -program_hw_cfgmem $memory +if {[catch {program_hw_cfgmem $memory} message options]} { + return -options $options "Flash program/verify failed: $message" +} puts "PASS FLASH_PROGRAM_VERIFY: $part $image" # JP1 must be shorted; this reloads the FPGA from Flash without downloading .bit. boot_hw_device -timeout 60 $device diff --git a/platforms/arty-a7-toy/board/toy_a7_platform.sv b/platforms/arty-a7-toy/board/toy_a7_platform.sv index e26d6dc..ade0c4d 100644 --- a/platforms/arty-a7-toy/board/toy_a7_platform.sv +++ b/platforms/arty-a7-toy/board/toy_a7_platform.sv @@ -403,7 +403,7 @@ module toy_a7_platform #(parameter UART_DIVISOR=25, parameter FLASH_BOOT=0) ( assign l_rvalid=ddr_rvalid && !cpu_run; assign ddr_rready=cpu_run ? c_rready : l_rready; wire [1:0] scu_bresp; - assign peripherals_b_bits_resp=|scu_bresp; + assign peripherals_b_bits_resp=scu_bresp; axi_scu #(.FLASH_BOOT(FLASH_BOOT)) peripherals ( .clk(clk), .reset(cpu_reset), diff --git a/platforms/arty-a7-toy/build.sbt b/platforms/arty-a7-toy/build.sbt index c29b46e..79eb11f 100644 --- a/platforms/arty-a7-toy/build.sbt +++ b/platforms/arty-a7-toy/build.sbt @@ -57,7 +57,7 @@ lazy val root = project.in(file(".")).dependsOn(inclusive, gemmini).settings(chi val directories = Seq("balldomain", "builtin", "dpi", "frontend", "gpdomain", "memdomain", "top", "system/core/rocket", "system/core/accelerator", "system/tile") val shared = directories.flatMap(d => ((framework / d) ** "*.scala").get) - .filterNot(f => Set("WithBuckyballTiles.scala", "WithBoomTile.scala", "MemMidend.scala", "MemStorer.scala", "PrivateMemBackend.scala", "SubROB.scala", "MemFrontend.scala", "MemLoader.scala")(f.getName)) + .filterNot(f => Set("WithBuckyballTiles.scala", "WithBoomTile.scala", "MemMidend.scala", "MemStorer.scala", "PrivateMemBackend.scala", "SubROB.scala", "GlobalROB.scala", "MemFrontend.scala", "MemLoader.scala")(f.getName)) shared ++ ((baseDirectory.value / "patches/framework") ** "*.scala").get ++ ((baseDirectory.value / "patches/buckyball") ** "*.scala").get ++ ((upstream / "arch/src/main/scala/sims/hash") ** "*.scala").get ++ Seq("gemmini", "trace", "mxfp2int", "relu").flatMap { name => val ball = upstream / "examples/balls" / name diff --git a/platforms/arty-a7-toy/distribution-rob/README.md b/platforms/arty-a7-toy/distribution-rob/README.md new file mode 100644 index 0000000..12b78da --- /dev/null +++ b/platforms/arty-a7-toy/distribution-rob/README.md @@ -0,0 +1,54 @@ +# Arty A7-100T：ROB 优化与 PR10 修复下载包 + +本包是 UART/JTAG 工程预发布，目标 **XC7A100T-CSG324-1**，CPU 25 MHz、UART 1 Mbps。 +保留 RV64 CPU、Sv39、FP16/32/64、Gemmini 8×8，启用 ROB 操作数 BRAM，并包含 AXI +写错误响应修复。官方 E.0 MIG 参数保持原值；实际 PCB 修订号未知。 + +位流通过本轮综合、布局布线、时序、DRC/CDC 及 RTL 回归；软件采用此前已验证的 +标准 Linux/Gemmini 镜像。**本轮没有连接实物板卡，未取得新位流实板或冷启动资格。** +具体数值、测试范围、源码提交和文件摘要见 `VALIDATION_RESULT.json` 与 `MANIFEST.json`。 + +非法 MMIO 检查确认 SLVERR 完整传到 CPU 的 AXI 输入，但当前非阻塞缓存在该用例中 +未产生同步访问异常，不能把总线响应修复当作完整的物理总线错误保护。Linux 的虚拟内存 +页面保护属于独立路径。整模型、长期 DDR 压力与环境稳定性也不在本次验收范围。 + +## 一键加载并测试（Windows） + +安装 Python、`pip install pyserial==3.5`、Vivado Hardware Manager 及 Digilent/FTDI 驱动。 +连接板卡 PROG/UART USB，SW0=0；确认串口是 USB UART 通道 B，然后执行： + +```powershell +.\run_uart.ps1 -Port COM5 -Vivado 'D:\Xilinx\2025.1\Vivado\bin\vivado.bat' +``` + +请替换真实串口和 Vivado 路径。入口先核验包内摘要，再临时 JTAG 配置、完整 DDR 读回、 +启动 Linux，执行 15 个程序。含五项 Linux 检查、13 项 Gemmini 测试和 16 项矩阵对照。 +进度与日志写入本包 `build/`；软件传输及完整读回需要数分钟，测试设有超时。 +程序启动后可通过同一 USB 串口以 1,000,000 波特、8N1 与 Linux 交互。 + +## 只烧录位流 / Linux 下使用 + +```bash +python3 verify_bundle.py +vivado -mode batch -source board/program_arty.tcl -tclargs toy_a7_uart.bit +python3 host/load.py --port /dev/ttyUSB1 fw_payload.bin +``` + +Windows 单独调用 Vivado 时可用 `vivado.bat`。单独下载 `.bit` 只配置 FPGA 逻辑；还需 +将 `fw_payload.bin` 加载到 DDR 才会启动 Linux。此包不擦写 Flash；掉电后本次 SRAM +配置和 DDR 软件丢失，下一次需要重新执行上述流程。既有 Flash 发布包是另一个目标， +不能用本包 UART 位流直接替代其 MCS。 + +## 重新构建位流 + +本包带实际 Chisel 生成 RTL、板级源码、XDC、官方 MIG 输入及本轮构建 Tcl，可直接用 +带 Artix-7 支持的 Vivado 2024.1 重建： + +```bash +timeout --signal=TERM --kill-after=15s 3600s vivado -mode batch \ + -source board/build_board.tcl -tclargs build/rebuild +``` + +新生成位流需重新核验时序与 DRC，不能沿用本包摘要。更改 Chisel 时使用对应源码包的 +`scripts/elaborate_rob_candidate.sh` 重新生成；默认构建仍是原寄存器 ROB 路径。 +完整验证与软件依赖源码在配套 sources 包；许可证和声明在 `LICENSE`、`notices/`。 diff --git a/platforms/arty-a7-toy/distribution-rob/run_uart.ps1 b/platforms/arty-a7-toy/distribution-rob/run_uart.ps1 new file mode 100644 index 0000000..8652ea5 --- /dev/null +++ b/platforms/arty-a7-toy/distribution-rob/run_uart.ps1 @@ -0,0 +1,21 @@ +# 临时配置 ROB/PR10 位流，读回完整软件镜像并执行 Linux/Gemmini 回归。 +param( + [Parameter(Mandatory = $true)][string]$Port, + [Parameter(Mandatory = $true)][string]$Vivado, + [string]$Python = 'python' +) +$ErrorActionPreference = 'Stop' +$env:PYTHONUTF8 = '1' +Push-Location -LiteralPath $PSScriptRoot +try { + & $Python verify_bundle.py + if ($LASTEXITCODE -ne 0) { throw '下载包校验失败，取消烧录' } + $releaseManifest = Get-Content -LiteralPath MANIFEST.json -Raw -Encoding UTF8 | ConvertFrom-Json + $bitDigest = $releaseManifest.files.'toy_a7_uart.bit'.sha256 + & $Python host/check_linux_gemmini.py --payload fw_payload.bin ` + --build-result LINUX_GEMMINI_BUILD.json --bitstream toy_a7_uart.bit ` + --expected-bit-sha256 $bitDigest --vivado $Vivado --port $Port + if ($LASTEXITCODE -ne 0) { throw '加载或测试失败，请查看 build/ 中的记录' } +} finally { + Pop-Location +} diff --git a/platforms/arty-a7-toy/distribution-rob/verify_bundle.py b/platforms/arty-a7-toy/distribution-rob/verify_bundle.py new file mode 100644 index 0000000..61e2435 --- /dev/null +++ b/platforms/arty-a7-toy/distribution-rob/verify_bundle.py @@ -0,0 +1,39 @@ +"""烧录前离线核验下载包中的全部文件；本入口不连接硬件。""" + +import argparse +import hashlib +import json +from pathlib import Path + + +def digest(path): + result = hashlib.sha256() + with path.open("rb") as source: + for block in iter(lambda: source.read(1024 * 1024), b""): + result.update(block) + return result.hexdigest() + + +def verify(root): + root = root.resolve() + record = json.loads((root / "MANIFEST.json").read_text(encoding="utf-8")) + for name, expected in record["files"].items(): + path = (root / name).resolve() + if not path.is_relative_to(root) or not path.is_file(): + raise ValueError("下载包文件缺失或路径无效：" + name) + if path.stat().st_size != expected["bytes"] or digest(path) != expected["sha256"]: + raise ValueError("下载包摘要不匹配：" + name) + print(f"PASS BUNDLE {record['flow']} files={len(record['files'])}") + return record + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("directory", nargs="?", type=Path, + default=Path(__file__).resolve().parent) + args = parser.parse_args() + verify(args.directory) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/MANIFEST.json b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/MANIFEST.json new file mode 100644 index 0000000..7ef740a --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/MANIFEST.json @@ -0,0 +1,312 @@ +{ + "files": { + "board-unit/RESULT.json": { + "sha256": "829cf414eee5da97800e41b244b9088151e1913226a88029a73e06fc0b0f1b37", + "bytes": 1354 + }, + "board-unit/tb_axi_fullwidth-compile.log": { + "sha256": "e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855", + "bytes": 0 + }, + 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}, + "sources/tests/ToyLinuxChipPorts.sv": { + "sha256": "e4c06220cd7025972d432b06c452e85c62bd2cfccad618b2b993499b62e6621a", + "bytes": 5148 + } + } +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/README.md b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/README.md new file mode 100644 index 0000000..c425088 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/README.md @@ -0,0 +1,37 @@ +# PR #10 离线评估与回归记录 + +结论及旧基线比较见 [修正说明](../../../REVIEW_FIXES.md)。`RESULT.json` 记录原提交、 +当前 ROB 比较提交、五文件摘要、补丁兼容检查和本次测试边界；`MANIFEST.json` +绑定原始结果、日志与实际测试输入快照。历史实现/实物档案未改。 + +## 通过的检查 + +- `board-unit/`：Icarus 四组接口回归，包括真实 SCU→平台→CPU 输入端的 B 响应。 +- `programming-check/`：20 项 Tcl 返回值、原生异常、配置状态和完整备份检查。 +- `flash-guard-check/`：10 项普通/`python -O` 镜像记录校验。 +- `session.log`：隔离运行的原始汇总；总 timeout 为 600 秒。 + +`sources/` 是本次输入快照。CPU 仅使用端口 fixture；未模拟 CPU 行为、物理 MIG， +未访问板卡/串口，未生成或烧录位流。不能将这些结果作为新 RTL 的实物验收。 + +## 预期失败的反例 + +- `old-platform-negative.log`：相同平台测试运行旧平台源码，非法 MMIO 地址 + `0x60030000` 的响应为 `01`，预期 `10`；进程退出 1，证明用例能抓住原错误。 + 输入为 `old-platform.sv`，其摘要绑定在 `RESULT.json`。 +- `original-pr/`：原 #10 的三份 Tcl 原文及离线日志，合法对象/执行记录返回值 + 被当成布尔值导致失败。这是 API 契约反例，不是实际板卡编程失败。 + +## 复现 + +Linux 下安装 Python、Tcl 8.6 和 Icarus Verilog；在平台根目录执行： + +```bash +python3 scripts/check_board.py +python3 scripts/check_programming_scripts.py +python3 scripts/check_flash_guards.py +python3 scripts/verify_pr10_evidence.py +``` + +Windows 可用 `--tclsh` 指定原生 Tcl 解释器；避免使用不传播子进程退出码的包装脚本。 +这些测试自行限制单个子进程的运行时间，CI 另设接口测试 180 秒及任务 10 分钟上限。 diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/RESULT.json new file mode 100644 index 0000000..ea2e158 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/RESULT.json @@ -0,0 +1,79 @@ +{ + "result": "PASS_PR10_EVALUATION_AND_OFFLINE_REGRESSIONS", + "original_pr_head": "f20b504946ee0b12cd8a0c720fc3b6ceabac4e97", + "original_base": "4bdd4e446fd973b29a0b6318324031dfc7b57872", + "compared_current_rob_head": "8f7bd63c874609360058b8fe1f0aabe9fe3bc505", + "comparison": { + "board/backup_flash.tcl": { + "base_sha256": "63d84e9055f00bd7ed97485912b0c8db83bee19b6950ba4c12fc3f9a639c3ea3", + "current_sha256": "63d84e9055f00bd7ed97485912b0c8db83bee19b6950ba4c12fc3f9a639c3ea3", + "byte_identical": true + }, + "board/program_arty.tcl": { + "base_sha256": "fbb62bafb6df602b0f5f638fb05ae4ecc90494ac162b9a5f5ac314200f7a241c", + "current_sha256": "fbb62bafb6df602b0f5f638fb05ae4ecc90494ac162b9a5f5ac314200f7a241c", + "byte_identical": true + }, + "board/program_flash.tcl": { + "base_sha256": "a2cfa55d7f61f5cecd74e68e2bbede9c535399291eea274e76fe416bdc8d3626", + "current_sha256": "a2cfa55d7f61f5cecd74e68e2bbede9c535399291eea274e76fe416bdc8d3626", + "byte_identical": true + }, + "board/toy_a7_platform.sv": { + "base_sha256": "01fe1f8e2621a1a023ac3b8d91758868b190760f6e706ae1d34a67857b96d846", + "current_sha256": "01fe1f8e2621a1a023ac3b8d91758868b190760f6e706ae1d34a67857b96d846", + "byte_identical": true + }, + "host/flash.py": { + "base_sha256": "47ad35043c9a04e9f6730dd4d53cf84f0d7bb018a03f76754d549f7bebe936dc", + "current_sha256": "47ad35043c9a04e9f6730dd4d53cf84f0d7bb018a03f76754d549f7bebe936dc", + "byte_identical": true + } + }, + "focused_patch_apply_check_exit_code": 0, + "focused_patch_sha256": "7c0775aa1cc2c8e7e5f0c03a3901451e4aaa3460b4c0ae08202b0f23a0c90737", + "interface_test_groups": 4, + "tcl_contract_cases": 20, + "python_guard_cases": 10, + "old_platform_expected_negative": { + "exit_code": 1, + "address": "0x60030000", + "actual_bresp": "01", + "expected_bresp": "10", + "source_sha256": "01fe1f8e2621a1a023ac3b8d91758868b190760f6e706ae1d34a67857b96d846" + }, + "original_pr_tcl_expected_negatives": 3, + "physical_hardware_tested": false, + "new_bitstream_generated": false, + "cpu_behavior_simulated": false, + "physical_mig_simulated": false, + "timeout_seconds": 600, + "sources": { + "board/axi_fullwidth.sv": "bf07ae27724dbd0a361d732dfb57109f06beef207c47a066d400cb06d7f07d5a", + "board/axi_scu.sv": "ee77bf641d61811b4c1faea845752850c22461a63b4cdfd3d6f9cd223e6c2fc2", + "board/backup_flash.tcl": "fa9185afad3537bf15b4f2f0c952a4eebf9d6c5693619819ff5e57897ce6a86d", + "board/ddr_uart_loader.sv": "980f4cd2e3fa2a00b66143f879bc749ed952c2c1e54331460821bac0300c43d6", + "board/flash_spi_byte.sv": "4d1fac5238f31fb3a69a58d1aca9ccec722e833d788113b94d86c6a1b861045a", + "board/loader_axi.sv": "05609b0870054ea675aedb406f6215cd456f18db6d6428b461cbae03d9a662f4", + "board/program_arty.tcl": "8af4c07627910536079eb4be647c6f0f447882950588c40588cdc571a72133ac", + "board/program_flash.tcl": "f9bf2b6fc6c9fdd268c308f417831c94707b464bbae75a5d2cc416f4c92bf424", + "board/toy_a7_platform.sv": "f9bc06535b7de19a6b1b501f06effe90519fd43a78e669ab7425d301662540b8", + "board/toy_a7_top.sv": "c8af97f543b8ae5d6dc21a85ba13b16a28fe3ba5bf93f8051c9e38c99f3350bd", + "board/uart_rx.sv": "0b35263884577324f146ff7fd516e5b561dcc8787e0d8ad599669bac1958406d", + "board/uart_tx.sv": "c20d420fc20be4f6313bdde5abc45ef0b9f8e93bf75350dd9951bc8868b3b65c", + "host/flash.py": "83e366dab1dbf2c9cda3b3259a237bb970293742c13e3f7a5496d2478a1cbff1", + "scripts/check_board.py": "e3618121401bd811eac50c017a016d3a548cdc004f8a47b01ae74466f02a786c", + "scripts/check_flash_guards.py": "42129a0be9f1399fac294799294fea791a83004463f9391f77b18c3d828e2535", + "scripts/check_programming_scripts.py": "b91b146da58df41b8453a61fd8eaf87e7314d56a8e8fff327270cb3dbed10f10", + "tests/PLATFORM_PORTS_MANIFEST.json": "5456ad060837d30818d6084b194896714921617b11dcada5ac897bc1c655f1dc", + "tests/ToyLinuxChipPorts.sv": "e4c06220cd7025972d432b06c452e85c62bd2cfccad618b2b993499b62e6621a", + "tests/axi_smoke_memory.sv": "7d0d410549217e73d319b807488812da06d54404a50fce484e1b527ea0e6632d", + "tests/board_loader_template.sv": "34be31c066ec317d5a1053d6e840145eb0af78766707915294a01cb96ec9b766", + "tests/flash_guard_probe.py": "b4e59e6cfbe6c95e99b6f733a7597043f8f394d4c10b0919fd92ab7c5372ada4", + "tests/mock_programming.tcl": "fd25ee00f3af89a3ec0416bd68a54f6cf7b3dac99c4a44f0c532cc36228312f1", + "tests/tb_axi_fullwidth.sv": "1d3964fab0eaa76a6f864f07a7dedf01639ba12a9400a15d0839e707ab73c4ed", + "tests/tb_axi_scu.sv": "5dfd1d6cac3201f0e5188e9b73e60ade27c4551570d4b00d387301713d9fbe97", + "tests/tb_platform_bresp.sv": "e69671fb9a5ea6a77ccc0ec8d7a8ca0afa07e9e8b035d0e107530032beabe1a0" + }, + "interface_final_rerun_timeout_seconds": 180 +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/board-unit/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/board-unit/RESULT.json new file mode 100644 index 0000000..912f661 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/board-unit/RESULT.json @@ -0,0 +1,20 @@ +{ + "result": "PASS", + "tests": 4, + "physical_mig_simulated": false, + "sources": { + "board/loader_axi.sv": "05609b0870054ea675aedb406f6215cd456f18db6d6428b461cbae03d9a662f4", + "board/flash_spi_byte.sv": "4d1fac5238f31fb3a69a58d1aca9ccec722e833d788113b94d86c6a1b861045a", + "board/uart_rx.sv": "0b35263884577324f146ff7fd516e5b561dcc8787e0d8ad599669bac1958406d", + "board/toy_a7_top.sv": "c8af97f543b8ae5d6dc21a85ba13b16a28fe3ba5bf93f8051c9e38c99f3350bd", + "board/ddr_uart_loader.sv": "980f4cd2e3fa2a00b66143f879bc749ed952c2c1e54331460821bac0300c43d6", + "board/axi_scu.sv": "ee77bf641d61811b4c1faea845752850c22461a63b4cdfd3d6f9cd223e6c2fc2", + "board/toy_a7_platform.sv": "f9bc06535b7de19a6b1b501f06effe90519fd43a78e669ab7425d301662540b8", + "board/axi_fullwidth.sv": "bf07ae27724dbd0a361d732dfb57109f06beef207c47a066d400cb06d7f07d5a", + "board/uart_tx.sv": "c20d420fc20be4f6313bdde5abc45ef0b9f8e93bf75350dd9951bc8868b3b65c", + "tests/tb_axi_fullwidth.sv": "1d3964fab0eaa76a6f864f07a7dedf01639ba12a9400a15d0839e707ab73c4ed", + "tests/tb_axi_scu.sv": "5dfd1d6cac3201f0e5188e9b73e60ade27c4551570d4b00d387301713d9fbe97", + "tests/ToyLinuxChipPorts.sv": "e4c06220cd7025972d432b06c452e85c62bd2cfccad618b2b993499b62e6621a", + "tests/tb_platform_bresp.sv": "e69671fb9a5ea6a77ccc0ec8d7a8ca0afa07e9e8b035d0e107530032beabe1a0" + } +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/board-unit/tb_axi_fullwidth-compile.log b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/board-unit/tb_axi_fullwidth-compile.log new file mode 100644 index 0000000..e69de29 diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/board-unit/tb_axi_fullwidth.log b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/board-unit/tb_axi_fullwidth.log new file mode 100644 index 0000000..4c83752 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/board-unit/tb_axi_fullwidth.log @@ -0,0 +1,2 @@ +PASS fullwidth AXI: sizes 8..128 bits, INCR/FIXED, strobes, concurrent R/W, stalls, IDs, range/4KiB rejection; read beats=90 +/home/yys/codex-builds/arty-a7-pr10-review-20261012-6eae4386/tests/tb_axi_fullwidth.sv:107: $finish called at 9270000 (1ps) diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/board-unit/tb_axi_scu-compile.log b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/board-unit/tb_axi_scu-compile.log new file mode 100644 index 0000000..e69de29 diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/board-unit/tb_axi_scu.log b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/board-unit/tb_axi_scu.log new file mode 100644 index 0000000..36448b7 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/board-unit/tb_axi_scu.log @@ -0,0 +1,2 @@ +PASS SCU OpenSBI byte addresses, AXI lanes, RX pop/IRQ, TX backpressure, EXIT +/home/yys/codex-builds/arty-a7-pr10-review-20261012-6eae4386/tests/tb_axi_scu.sv:64: $finish called at 20580000 (1ps) diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/board-unit/tb_ddr_loader-compile.log b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/board-unit/tb_ddr_loader-compile.log new file mode 100644 index 0000000..e69de29 diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/board-unit/tb_ddr_loader.log b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/board-unit/tb_ddr_loader.log new file mode 100644 index 0000000..b9d373b --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/board-unit/tb_ddr_loader.log @@ -0,0 +1,2 @@ +PASS: DDR UART loader CRC, 256-byte unaligned RAM roundtrip, rejected writes/RUN, timeout and boot +/home/yys/codex-builds/arty-a7-pr10-review-20261012-6eae4386/build/board-unit/tb_ddr_loader.sv:116: $finish called at 78290000 (1ps) diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/board-unit/tb_platform_bresp-compile.log b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/board-unit/tb_platform_bresp-compile.log new file mode 100644 index 0000000..e69de29 diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/board-unit/tb_platform_bresp.log b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/board-unit/tb_platform_bresp.log new file mode 100644 index 0000000..59765bd --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/board-unit/tb_platform_bresp.log @@ -0,0 +1,2 @@ +PASS platform AXI B response: valid, invalid address, unaligned, burst, ID and backpressure +/home/yys/codex-builds/arty-a7-pr10-review-20261012-6eae4386/tests/tb_platform_bresp.sv:52: $finish called at 420000 (1ps) diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/flash-guard-check/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/flash-guard-check/RESULT.json new file mode 100644 index 0000000..f236658 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/flash-guard-check/RESULT.json @@ -0,0 +1,56 @@ +{ + "result": "PASS_FLASH_GUARDS_NORMAL_AND_OPTIMIZED", + "physical_hardware_tested": false, + "cases": [ + { + "optimized": false, + "field": "valid", + "result": "PASS" + }, + { + "optimized": false, + "field": "result", + "result": "PASS" + }, + { + "optimized": false, + "field": "bitstream_sha256", + "result": "PASS" + }, + { + "optimized": false, + "field": "packed_payload_sha256", + "result": "PASS" + }, + { + "optimized": false, + "field": "flash_image_sha256", + "result": "PASS" + }, + { + "optimized": true, + "field": "valid", + "result": "PASS" + }, + { + "optimized": true, + "field": "result", + "result": "PASS" + }, + { + "optimized": true, + "field": "bitstream_sha256", + "result": "PASS" + }, + { + "optimized": true, + "field": "packed_payload_sha256", + "result": "PASS" + }, + { + "optimized": true, + "field": "flash_image_sha256", + "result": "PASS" + } + ] +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/flash-guard-check/normal-bitstream_sha256.log b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/flash-guard-check/normal-bitstream_sha256.log new file mode 100644 index 0000000..743e348 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/flash-guard-check/normal-bitstream_sha256.log @@ -0,0 +1 @@ +PASS INVALID_IMAGE_BLOCKED Prepacked flash image bitstream hash mismatch diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/flash-guard-check/normal-flash_image_sha256.log b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/flash-guard-check/normal-flash_image_sha256.log new file mode 100644 index 0000000..ffaee7b --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/flash-guard-check/normal-flash_image_sha256.log @@ -0,0 +1 @@ +PASS INVALID_IMAGE_BLOCKED Prepacked flash image MCS hash mismatch diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/flash-guard-check/normal-packed_payload_sha256.log b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/flash-guard-check/normal-packed_payload_sha256.log new file mode 100644 index 0000000..7f5ad62 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/flash-guard-check/normal-packed_payload_sha256.log @@ -0,0 +1 @@ +PASS INVALID_IMAGE_BLOCKED Prepacked flash image payload hash mismatch diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/flash-guard-check/normal-result.log b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/flash-guard-check/normal-result.log new file mode 100644 index 0000000..c80dd16 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/flash-guard-check/normal-result.log @@ -0,0 +1 @@ +PASS INVALID_IMAGE_BLOCKED Prepacked flash image record did not pass packing diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/flash-guard-check/normal-valid.log b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/flash-guard-check/normal-valid.log new file mode 100644 index 0000000..664fff0 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/flash-guard-check/normal-valid.log @@ -0,0 +1,32 @@ +USING_PREPACKED_FLASH_IMAGE bb7752b500cc85074635eb43d325bb3d1fdb575a8b76a6f8b77248923ce55774 +{ + "status": "FAILED", + "timeout_seconds": 3600, + "bitstream_sha256": "7bf8e955913c442ddd945fafdcc42d2a593f2e19477288bd98cc008062369335", + "packed_payload_sha256": "57312732d5af9cb3785067f8032a41a0c3d023b8ebe0a6a8cde1c1dff99714ff", + "part": "mt25ql128-spi-x1_x2_x4", + "port": "OFFLINE_NO_DEVICE", + "started_at": "2026-10-12T21:58:21.821849+08:00", + "commands": [ + null, + [ + "OFFLINE_NO_VIVADO", + "-mode", + "batch", + "-source", + "/home/yys/codex-builds/arty-a7-pr10-review-20261012-6eae4386/board/program_flash.tcl", + "-log", + "/home/yys/codex-builds/arty-a7-pr10-review-20261012-6eae4386/build/flash-guard-check/tmp6bzjf0zb/run/program.log", + "-journal", + "/home/yys/codex-builds/arty-a7-pr10-review-20261012-6eae4386/build/flash-guard-check/tmp6bzjf0zb/run/program.jou", + "-tclargs", + "/home/yys/codex-builds/arty-a7-pr10-review-20261012-6eae4386/build/flash-guard-check/tmp6bzjf0zb/run/toy_flash.mcs", + "mt25ql128-spi-x1_x2_x4", + "/home/yys/codex-builds/arty-a7-pr10-review-20261012-6eae4386/build/flash-guard-check/tmp6bzjf0zb/run/flash-before.bin" + ] + ], + "error": "Guard accepted the valid image", + "elapsed_seconds": 0.0, + "finished_at": "2026-10-12T21:58:21.821964+08:00" +} +PASS VALID_IMAGE_REACHED_OFFLINE_BOUNDARY diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/flash-guard-check/optimized-bitstream_sha256.log b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/flash-guard-check/optimized-bitstream_sha256.log new file mode 100644 index 0000000..743e348 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/flash-guard-check/optimized-bitstream_sha256.log @@ -0,0 +1 @@ +PASS INVALID_IMAGE_BLOCKED Prepacked flash image bitstream hash mismatch diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/flash-guard-check/optimized-flash_image_sha256.log b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/flash-guard-check/optimized-flash_image_sha256.log new file mode 100644 index 0000000..ffaee7b --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/flash-guard-check/optimized-flash_image_sha256.log @@ -0,0 +1 @@ +PASS INVALID_IMAGE_BLOCKED Prepacked flash image MCS hash mismatch diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/flash-guard-check/optimized-packed_payload_sha256.log b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/flash-guard-check/optimized-packed_payload_sha256.log new file mode 100644 index 0000000..7f5ad62 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/flash-guard-check/optimized-packed_payload_sha256.log @@ -0,0 +1 @@ +PASS INVALID_IMAGE_BLOCKED Prepacked flash image payload hash mismatch diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/flash-guard-check/optimized-result.log b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/flash-guard-check/optimized-result.log new file mode 100644 index 0000000..c80dd16 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/flash-guard-check/optimized-result.log @@ -0,0 +1 @@ +PASS INVALID_IMAGE_BLOCKED Prepacked flash image record did not pass packing diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/flash-guard-check/optimized-valid.log b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/flash-guard-check/optimized-valid.log new file mode 100644 index 0000000..2e50faa --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/flash-guard-check/optimized-valid.log @@ -0,0 +1,32 @@ +USING_PREPACKED_FLASH_IMAGE bb7752b500cc85074635eb43d325bb3d1fdb575a8b76a6f8b77248923ce55774 +{ + "status": "FAILED", + "timeout_seconds": 3600, + "bitstream_sha256": "7bf8e955913c442ddd945fafdcc42d2a593f2e19477288bd98cc008062369335", + "packed_payload_sha256": "57312732d5af9cb3785067f8032a41a0c3d023b8ebe0a6a8cde1c1dff99714ff", + "part": "mt25ql128-spi-x1_x2_x4", + "port": "OFFLINE_NO_DEVICE", + "started_at": "2026-10-12T21:58:22.147992+08:00", + "commands": [ + null, + [ + "OFFLINE_NO_VIVADO", + "-mode", + "batch", + "-source", + "/home/yys/codex-builds/arty-a7-pr10-review-20261012-6eae4386/board/program_flash.tcl", + "-log", + "/home/yys/codex-builds/arty-a7-pr10-review-20261012-6eae4386/build/flash-guard-check/tmpurvb297x/run/program.log", + "-journal", + "/home/yys/codex-builds/arty-a7-pr10-review-20261012-6eae4386/build/flash-guard-check/tmpurvb297x/run/program.jou", + "-tclargs", + "/home/yys/codex-builds/arty-a7-pr10-review-20261012-6eae4386/build/flash-guard-check/tmpurvb297x/run/toy_flash.mcs", + "mt25ql128-spi-x1_x2_x4", + "/home/yys/codex-builds/arty-a7-pr10-review-20261012-6eae4386/build/flash-guard-check/tmpurvb297x/run/flash-before.bin" + ] + ], + "error": "Guard accepted the valid image", + "elapsed_seconds": 0.0, + "finished_at": "2026-10-12T21:58:22.148117+08:00" +} +PASS VALID_IMAGE_REACHED_OFFLINE_BOUNDARY diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/old-platform-negative.log b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/old-platform-negative.log new file mode 100644 index 0000000..b396228 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/old-platform-negative.log @@ -0,0 +1,2 @@ +FATAL: tests/tb_platform_bresp.sv:27: Platform B response addr=60030000 actual=01 expected=10 + Time: 170000 Scope: tb_platform_bresp.write_case diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/old-platform.sv b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/old-platform.sv new file mode 100644 index 0000000..e26d6dc --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/old-platform.sv @@ -0,0 +1,450 @@ +// Generated wiring; source CPU/accelerator RTL is byte-identical. +module toy_a7_platform #(parameter UART_DIVISOR=25, parameter FLASH_BOOT=0) ( + input wire clk, reset, uart_rx_in, + output wire uart_tx_out, cpu_run, exited, loader_error, + output wire [31:0] exit_code, + output wire [3:0] ddr_awid, + output wire [27:0] ddr_awaddr, + output wire [7:0] ddr_awlen, + output wire [2:0] ddr_awsize, + output wire [1:0] ddr_awburst, + output wire ddr_awvalid, + input wire ddr_awready, + output wire [127:0] ddr_wdata, + output wire [15:0] ddr_wstrb, + output wire ddr_wlast, + output wire ddr_wvalid, + input wire ddr_wready, + input wire [3:0] ddr_bid, + input wire [1:0] ddr_bresp, + input wire ddr_bvalid, + output wire ddr_bready, + output wire [3:0] ddr_arid, + output wire [27:0] ddr_araddr, + output wire [7:0] ddr_arlen, + output wire [2:0] ddr_arsize, + output wire [1:0] ddr_arburst, + output wire ddr_arvalid, + input wire ddr_arready, + input wire [3:0] ddr_rid, + input wire [127:0] ddr_rdata, + input wire [1:0] ddr_rresp, + input wire ddr_rlast, + input wire ddr_rvalid, + output wire ddr_rready, + input wire flash_miso, flash_recovery, + output wire flash_mosi, flash_sck, flash_cs_n +); + wire cpu_reset=reset || !cpu_run; + wire loader_cpu_run; + assign cpu_run=loader_cpu_run || (FLASH_BOOT && !flash_recovery); + wire irq; + wire rx_valid, rx_error, tx_ready, loader_tx_valid, mmio_tx_valid; + wire [7:0] rx_data, loader_tx_data, mmio_tx_data; + wire load_en, load_valid, load_error; wire [27:0] load_addr; + wire [127:0] load_data, load_result; wire [15:0] load_mask; + uart_rx #(.DIVISOR(UART_DIVISOR)) receiver (.clk(clk),.reset(reset),.rx(uart_rx_in), + .valid(rx_valid),.data(rx_data),.frame_error(rx_error)); + uart_tx #(.DIVISOR(UART_DIVISOR)) transmitter (.clk(clk),.reset(reset), + .valid(cpu_run ? mmio_tx_valid : loader_tx_valid),.data(cpu_run ? mmio_tx_data : loader_tx_data), + .ready(tx_ready),.tx(uart_tx_out)); + ddr_uart_loader loader (.clk(clk),.reset(reset),.rx_valid(rx_valid && !cpu_run),.rx_data(rx_data), + .rx_error(rx_error),.tx_valid(loader_tx_valid),.tx_data(loader_tx_data),.tx_ready(tx_ready), + .cpu_run(loader_cpu_run),.error_seen(loader_error),.load_en(load_en),.load_addr(load_addr), + .load_data(load_data),.load_mask(load_mask),.load_valid(load_valid),.load_error(load_error),.load_result(load_result)); + wire memory_aw_ready; + wire memory_aw_valid; + wire [3:0] memory_aw_bits_id; + wire [31:0] memory_aw_bits_addr; + wire [7:0] memory_aw_bits_len; + wire [2:0] memory_aw_bits_size; + wire [1:0] memory_aw_bits_burst; + wire memory_aw_bits_lock; + wire [3:0] memory_aw_bits_cache; + wire [2:0] memory_aw_bits_prot; + wire [3:0] memory_aw_bits_qos; + wire memory_w_ready; + wire memory_w_valid; + wire [127:0] memory_w_bits_data; + wire [15:0] memory_w_bits_strb; + wire memory_w_bits_last; + wire memory_b_ready; + wire memory_b_valid; + wire [3:0] memory_b_bits_id; + wire [1:0] memory_b_bits_resp; + wire memory_ar_ready; + wire memory_ar_valid; + wire [3:0] memory_ar_bits_id; + wire [31:0] memory_ar_bits_addr; + wire [7:0] memory_ar_bits_len; + wire [2:0] memory_ar_bits_size; + wire [1:0] memory_ar_bits_burst; + wire memory_ar_bits_lock; + wire [3:0] memory_ar_bits_cache; + wire [2:0] memory_ar_bits_prot; + wire [3:0] memory_ar_bits_qos; + wire memory_r_ready; + wire memory_r_valid; + wire [3:0] memory_r_bits_id; + wire [127:0] memory_r_bits_data; + wire [1:0] memory_r_bits_resp; + wire memory_r_bits_last; + wire peripherals_aw_ready; + wire peripherals_aw_valid; + wire [1:0] peripherals_aw_bits_id; + wire [30:0] peripherals_aw_bits_addr; + wire [7:0] peripherals_aw_bits_len; + wire [2:0] peripherals_aw_bits_size; + wire [1:0] peripherals_aw_bits_burst; + wire peripherals_aw_bits_lock; + wire [3:0] peripherals_aw_bits_cache; + wire [2:0] peripherals_aw_bits_prot; + wire [3:0] peripherals_aw_bits_qos; + wire peripherals_w_ready; + wire peripherals_w_valid; + wire [63:0] peripherals_w_bits_data; + wire [7:0] peripherals_w_bits_strb; + wire peripherals_w_bits_last; + wire peripherals_b_ready; + wire peripherals_b_valid; + wire [1:0] peripherals_b_bits_id; + wire [1:0] peripherals_b_bits_resp; + wire peripherals_ar_ready; + wire peripherals_ar_valid; + wire [1:0] peripherals_ar_bits_id; + wire [30:0] peripherals_ar_bits_addr; + wire [7:0] peripherals_ar_bits_len; + wire [2:0] peripherals_ar_bits_size; + wire [1:0] peripherals_ar_bits_burst; + wire peripherals_ar_bits_lock; + wire [3:0] peripherals_ar_bits_cache; + wire [2:0] peripherals_ar_bits_prot; + wire [3:0] peripherals_ar_bits_qos; + wire peripherals_r_ready; + wire peripherals_r_valid; + wire [1:0] peripherals_r_bits_id; + wire [63:0] peripherals_r_bits_data; + wire [1:0] peripherals_r_bits_resp; + wire peripherals_r_bits_last; + ToyLinuxChip chip ( + .clock(clk), + .reset(cpu_reset), + .interrupt(irq), + .memory_aw_ready(memory_aw_ready), + .memory_aw_valid(memory_aw_valid), + .memory_aw_bits_id(memory_aw_bits_id), + .memory_aw_bits_addr(memory_aw_bits_addr), + .memory_aw_bits_len(memory_aw_bits_len), + .memory_aw_bits_size(memory_aw_bits_size), + .memory_aw_bits_burst(memory_aw_bits_burst), + .memory_aw_bits_lock(memory_aw_bits_lock), + .memory_aw_bits_cache(memory_aw_bits_cache), + .memory_aw_bits_prot(memory_aw_bits_prot), + .memory_aw_bits_qos(memory_aw_bits_qos), + .memory_w_ready(memory_w_ready), + .memory_w_valid(memory_w_valid), + .memory_w_bits_data(memory_w_bits_data), + .memory_w_bits_strb(memory_w_bits_strb), + .memory_w_bits_last(memory_w_bits_last), + .memory_b_ready(memory_b_ready), + .memory_b_valid(memory_b_valid), + .memory_b_bits_id(memory_b_bits_id), + .memory_b_bits_resp(memory_b_bits_resp), + .memory_ar_ready(memory_ar_ready), + .memory_ar_valid(memory_ar_valid), + .memory_ar_bits_id(memory_ar_bits_id), + .memory_ar_bits_addr(memory_ar_bits_addr), + .memory_ar_bits_len(memory_ar_bits_len), + .memory_ar_bits_size(memory_ar_bits_size), + .memory_ar_bits_burst(memory_ar_bits_burst), + .memory_ar_bits_lock(memory_ar_bits_lock), + .memory_ar_bits_cache(memory_ar_bits_cache), + .memory_ar_bits_prot(memory_ar_bits_prot), + .memory_ar_bits_qos(memory_ar_bits_qos), + .memory_r_ready(memory_r_ready), + .memory_r_valid(memory_r_valid), + .memory_r_bits_id(memory_r_bits_id), + .memory_r_bits_data(memory_r_bits_data), + .memory_r_bits_resp(memory_r_bits_resp), + .memory_r_bits_last(memory_r_bits_last), + .peripherals_aw_ready(peripherals_aw_ready), + .peripherals_aw_valid(peripherals_aw_valid), + .peripherals_aw_bits_id(peripherals_aw_bits_id), + .peripherals_aw_bits_addr(peripherals_aw_bits_addr), + .peripherals_aw_bits_len(peripherals_aw_bits_len), + .peripherals_aw_bits_size(peripherals_aw_bits_size), + .peripherals_aw_bits_burst(peripherals_aw_bits_burst), + .peripherals_aw_bits_lock(peripherals_aw_bits_lock), + .peripherals_aw_bits_cache(peripherals_aw_bits_cache), + .peripherals_aw_bits_prot(peripherals_aw_bits_prot), + .peripherals_aw_bits_qos(peripherals_aw_bits_qos), + .peripherals_w_ready(peripherals_w_ready), + .peripherals_w_valid(peripherals_w_valid), + .peripherals_w_bits_data(peripherals_w_bits_data), + .peripherals_w_bits_strb(peripherals_w_bits_strb), + .peripherals_w_bits_last(peripherals_w_bits_last), + .peripherals_b_ready(peripherals_b_ready), + .peripherals_b_valid(peripherals_b_valid), + .peripherals_b_bits_id(peripherals_b_bits_id), + .peripherals_b_bits_resp(peripherals_b_bits_resp), + .peripherals_ar_ready(peripherals_ar_ready), + .peripherals_ar_valid(peripherals_ar_valid), + .peripherals_ar_bits_id(peripherals_ar_bits_id), + .peripherals_ar_bits_addr(peripherals_ar_bits_addr), + .peripherals_ar_bits_len(peripherals_ar_bits_len), + .peripherals_ar_bits_size(peripherals_ar_bits_size), + .peripherals_ar_bits_burst(peripherals_ar_bits_burst), + .peripherals_ar_bits_lock(peripherals_ar_bits_lock), + .peripherals_ar_bits_cache(peripherals_ar_bits_cache), + .peripherals_ar_bits_prot(peripherals_ar_bits_prot), + .peripherals_ar_bits_qos(peripherals_ar_bits_qos), + .peripherals_r_ready(peripherals_r_ready), + .peripherals_r_valid(peripherals_r_valid), + .peripherals_r_bits_id(peripherals_r_bits_id), + .peripherals_r_bits_data(peripherals_r_bits_data), + .peripherals_r_bits_resp(peripherals_r_bits_resp), + .peripherals_r_bits_last(peripherals_r_bits_last) + ); + wire [3:0] c_awid; + wire [27:0] c_awaddr; + wire [7:0] c_awlen; + wire [2:0] c_awsize; + wire [1:0] c_awburst; + wire c_awvalid; + wire c_awready; + wire [127:0] c_wdata; + wire [15:0] c_wstrb; + wire c_wlast; + wire c_wvalid; + wire c_wready; + wire [3:0] c_bid; + wire [1:0] c_bresp; + wire c_bvalid; + wire c_bready; + wire [3:0] c_arid; + wire [27:0] c_araddr; + wire [7:0] c_arlen; + wire [2:0] c_arsize; + wire [1:0] c_arburst; + wire c_arvalid; + wire c_arready; + wire [3:0] c_rid; + wire [127:0] c_rdata; + wire [1:0] c_rresp; + wire c_rlast; + wire c_rvalid; + wire c_rready; + wire [3:0] l_awid; + wire [27:0] l_awaddr; + wire [7:0] l_awlen; + wire [2:0] l_awsize; + wire [1:0] l_awburst; + wire l_awvalid; + wire l_awready; + wire [127:0] l_wdata; + wire [15:0] l_wstrb; + wire l_wlast; + wire l_wvalid; + wire l_wready; + wire [3:0] l_bid; + wire [1:0] l_bresp; + wire l_bvalid; + wire l_bready; + wire [3:0] l_arid; + wire [27:0] l_araddr; + wire [7:0] l_arlen; + wire [2:0] l_arsize; + wire [1:0] l_arburst; + wire l_arvalid; + wire l_arready; + wire [3:0] l_rid; + wire [127:0] l_rdata; + wire [1:0] l_rresp; + wire l_rlast; + wire l_rvalid; + wire l_rready; + axi_fullwidth normalizer ( + .clk(clk), + .reset(reset), + .s_awid(memory_aw_bits_id), + .m_awid(c_awid), + .s_awaddr(memory_aw_bits_addr), + .m_awaddr(c_awaddr), + .s_awlen(memory_aw_bits_len), + .m_awlen(c_awlen), + .s_awsize(memory_aw_bits_size), + .m_awsize(c_awsize), + .s_awburst(memory_aw_bits_burst), + .m_awburst(c_awburst), + .s_awvalid(memory_aw_valid), + .m_awvalid(c_awvalid), + .s_awready(memory_aw_ready), + .m_awready(c_awready), + .s_wdata(memory_w_bits_data), + .m_wdata(c_wdata), + .s_wstrb(memory_w_bits_strb), + .m_wstrb(c_wstrb), + .s_wlast(memory_w_bits_last), + .m_wlast(c_wlast), + .s_wvalid(memory_w_valid), + .m_wvalid(c_wvalid), + .s_wready(memory_w_ready), + .m_wready(c_wready), + .s_bid(memory_b_bits_id), + .m_bid(c_bid), + .s_bresp(memory_b_bits_resp), + .m_bresp(c_bresp), + .s_bvalid(memory_b_valid), + .m_bvalid(c_bvalid), + .s_bready(memory_b_ready), + .m_bready(c_bready), + .s_arid(memory_ar_bits_id), + .m_arid(c_arid), + .s_araddr(memory_ar_bits_addr), + .m_araddr(c_araddr), + .s_arlen(memory_ar_bits_len), + .m_arlen(c_arlen), + .s_arsize(memory_ar_bits_size), + .m_arsize(c_arsize), + .s_arburst(memory_ar_bits_burst), + .m_arburst(c_arburst), + .s_arvalid(memory_ar_valid), + .m_arvalid(c_arvalid), + .s_arready(memory_ar_ready), + .m_arready(c_arready), + .s_rid(memory_r_bits_id), + .m_rid(c_rid), + .s_rdata(memory_r_bits_data), + .m_rdata(c_rdata), + .s_rresp(memory_r_bits_resp), + .m_rresp(c_rresp), + .s_rlast(memory_r_bits_last), + .m_rlast(c_rlast), + .s_rvalid(memory_r_valid), + .m_rvalid(c_rvalid), + .s_rready(memory_r_ready), + .m_rready(c_rready) + ); + loader_axi load_bridge ( + .clk(clk), + .reset(reset), + .load_en(load_en), + .load_addr(load_addr), + .load_data(load_data), + .load_mask(load_mask), + .load_valid(load_valid), + .load_error(load_error), + .load_result(load_result), + .awaddr(l_awaddr), + .araddr(l_araddr), + .awvalid(l_awvalid), + .wvalid(l_wvalid), + .arvalid(l_arvalid), + .bready(l_bready), + .rready(l_rready), + .awready(l_awready), + .wready(l_wready), + .arready(l_arready), + .bvalid(l_bvalid), + .rvalid(l_rvalid), + .wdata(l_wdata), + .wstrb(l_wstrb), + .bresp(l_bresp), + .rresp(l_rresp), + .rdata(l_rdata) + ); + assign l_awid=0; + assign l_arid=0; + assign l_awlen=0; + assign l_arlen=0; + assign l_awsize=4; + assign l_arsize=4; + assign l_awburst=1; + assign l_arburst=1; + assign l_wlast=1; + assign ddr_awid=cpu_run ? c_awid : l_awid; + assign ddr_awaddr=cpu_run ? c_awaddr : l_awaddr; + assign ddr_awlen=cpu_run ? c_awlen : l_awlen; + assign ddr_awsize=cpu_run ? c_awsize : l_awsize; + assign ddr_awburst=cpu_run ? c_awburst : l_awburst; + assign ddr_awvalid=cpu_run ? c_awvalid : l_awvalid; + assign c_awready=ddr_awready && cpu_run; + assign l_awready=ddr_awready && !cpu_run; + assign ddr_wdata=cpu_run ? c_wdata : l_wdata; + assign ddr_wstrb=cpu_run ? c_wstrb : l_wstrb; + assign ddr_wlast=cpu_run ? c_wlast : l_wlast; + assign ddr_wvalid=cpu_run ? c_wvalid : l_wvalid; + assign c_wready=ddr_wready && cpu_run; + assign l_wready=ddr_wready && !cpu_run; + assign c_bid=ddr_bid; + assign l_bid=ddr_bid; + assign c_bresp=ddr_bresp; + assign l_bresp=ddr_bresp; + assign c_bvalid=ddr_bvalid && cpu_run; + assign l_bvalid=ddr_bvalid && !cpu_run; + assign ddr_bready=cpu_run ? c_bready : l_bready; + assign ddr_arid=cpu_run ? c_arid : l_arid; + assign ddr_araddr=cpu_run ? c_araddr : l_araddr; + assign ddr_arlen=cpu_run ? c_arlen : l_arlen; + assign ddr_arsize=cpu_run ? c_arsize : l_arsize; + assign ddr_arburst=cpu_run ? c_arburst : l_arburst; + assign ddr_arvalid=cpu_run ? c_arvalid : l_arvalid; + assign c_arready=ddr_arready && cpu_run; + assign l_arready=ddr_arready && !cpu_run; + assign c_rid=ddr_rid; + assign l_rid=ddr_rid; + assign c_rdata=ddr_rdata; + assign l_rdata=ddr_rdata; + assign c_rresp=ddr_rresp; + assign l_rresp=ddr_rresp; + assign c_rlast=ddr_rlast; + assign l_rlast=ddr_rlast; + assign c_rvalid=ddr_rvalid && cpu_run; + assign l_rvalid=ddr_rvalid && !cpu_run; + assign ddr_rready=cpu_run ? c_rready : l_rready; + wire [1:0] scu_bresp; + assign peripherals_b_bits_resp=|scu_bresp; + axi_scu #(.FLASH_BOOT(FLASH_BOOT)) peripherals ( + .clk(clk), + .reset(cpu_reset), + .awid(peripherals_aw_bits_id), + .awaddr(peripherals_aw_bits_addr), + .awlen(peripherals_aw_bits_len), + .awsize(peripherals_aw_bits_size), + .awburst(peripherals_aw_bits_burst), + .awvalid(peripherals_aw_valid), + .awready(peripherals_aw_ready), + .wdata(peripherals_w_bits_data), + .wstrb(peripherals_w_bits_strb), + .wlast(peripherals_w_bits_last), + .wvalid(peripherals_w_valid), + .wready(peripherals_w_ready), + .bid(peripherals_b_bits_id), + .bresp(scu_bresp), + .bvalid(peripherals_b_valid), + .bready(peripherals_b_ready), + .arid(peripherals_ar_bits_id), + .araddr(peripherals_ar_bits_addr), + .arlen(peripherals_ar_bits_len), + .arsize(peripherals_ar_bits_size), + .arburst(peripherals_ar_bits_burst), + .arvalid(peripherals_ar_valid), + .arready(peripherals_ar_ready), + .rid(peripherals_r_bits_id), + .rdata(peripherals_r_bits_data), + .rresp(peripherals_r_bits_resp), + .rlast(peripherals_r_bits_last), + .rvalid(peripherals_r_valid), + .rready(peripherals_r_ready), + .rx_valid(rx_valid && cpu_run), + .rx_data(rx_data), + .rx_error(rx_error), + .tx_valid(mmio_tx_valid), + .tx_data(mmio_tx_data), + .tx_ready(tx_ready), + .exited(exited), + .exit_code(exit_code), + .interrupt(irq),.flash_miso(flash_miso),.flash_recovery(flash_recovery), + .flash_mosi(flash_mosi),.flash_sck(flash_sck),.flash_cs_n(flash_cs_n) + ); +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/original-pr/backup_flash.tcl b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/original-pr/backup_flash.tcl new file mode 100644 index 0000000..ddffce7 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/original-pr/backup_flash.tcl @@ -0,0 +1,32 @@ +# Read all existing Flash before any erase. This temporarily replaces FPGA SRAM +# with Vivado's SPI bridge, but never requests a Flash write/erase. +if {$argc!=2} {error "Usage: backup_flash.tcl FLASH_PART output.bin"} +lassign $argv part backup +set backup [file normalize $backup] +if {[file exists $backup]} {error "Refusing to overwrite an existing backup"} +if {$part ni {s25fl128sxxxxxx0-spi-x1_x2_x4 s25fl128sxxxxxx1-spi-x1_x2_x4 mt25ql128-spi-x1_x2_x4}} { + error "Select the exact supported 128-Mbit Arty Flash model" +} +open_hw_manager +connect_hw_server -allow_non_jtag +set targets [get_hw_targets -quiet] +if {[llength $targets]!=1} {error "Expected one attached JTAG target"} +open_hw_target [lindex $targets 0] +set devices [get_hw_devices -quiet -filter {PART == xc7a100t}] +if {[llength $devices]!=1} {error "Expected one XC7A100T"} +set device [lindex $devices 0] +current_hw_device $device +set choices [get_cfgmem_parts -of_objects $device -filter "NAME == $part"] +if {[llength $choices]!=1} {error "Flash part is not uniquely compatible with this FPGA"} +create_hw_cfgmem -hw_device $device [lindex $choices 0] +set memory [get_property PROGRAM.HW_CFGMEM $device] +create_hw_bitstream -hw_device $device [get_property PROGRAM.HW_CFGMEM_BITFILE $device] +if {![program_hw_devices $device]} {error "SPI bridge programming failed"} +file mkdir [file dirname $backup] +if {![readback_hw_cfgmem -all -file $backup -format bin $memory]} {error "Flash readback failed"} +if {[file size $backup]!=16777216} {error "Incomplete Flash backup"} +puts "PASS FLASH_BACKUP: $part $backup bytes=16777216" +close_hw_target +disconnect_hw_server +close_hw_manager +exit diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/original-pr/backup_flash.tcl.log b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/original-pr/backup_flash.tcl.log new file mode 100644 index 0000000..eed5fa1 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/original-pr/backup_flash.tcl.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device +MOCK_FAILURE expected boolean value but got "xc7a100t_0" diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/original-pr/program_arty.tcl b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/original-pr/program_arty.tcl new file mode 100644 index 0000000..bafb16f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/original-pr/program_arty.tcl @@ -0,0 +1,25 @@ +# Volatile JTAG programming only. Usage: +# Confirm physical Rev E DDR compatibility before using this engineering image. +# vivado -mode batch -source board/program_arty.tcl -tclargs /path/to/toy_a7.bit +if {$argc != 1} { error "Supply the Arty A7-100T .bit file" } +set bitfile [file normalize [lindex $argv 0]] +if {![file isfile $bitfile]} { error "Bitstream not found: $bitfile" } +open_hw_manager +connect_hw_server -allow_non_jtag +set targets [get_hw_targets -quiet] +if {[llength $targets] != 1} { + error "Expected one connected JTAG target. Select the Arty manually in Hardware Manager if multiple boards are attached." +} +open_hw_target [lindex $targets 0] +set devices [get_hw_devices -quiet -filter {PART == xc7a100t}] +if {[llength $devices] != 1} { error "Expected one XC7A100T; inspect the connected board" } +set device [lindex $devices 0] +current_hw_device $device +set_property PROGRAM.FILE $bitfile $device +if {![program_hw_devices $device]} {error "JTAG programming failed; device did not configure"} +refresh_hw_device $device +puts "ARTY_JTAG_PROGRAMMED: $bitfile" +close_hw_target +disconnect_hw_server +close_hw_manager +exit diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/original-pr/program_arty.tcl.log b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/original-pr/program_arty.tcl.log new file mode 100644 index 0000000..eed5fa1 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/original-pr/program_arty.tcl.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device +MOCK_FAILURE expected boolean value but got "xc7a100t_0" diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/original-pr/program_flash.tcl b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/original-pr/program_flash.tcl new file mode 100644 index 0000000..af67f0f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/original-pr/program_flash.tcl @@ -0,0 +1,51 @@ +# Explicit nonvolatile programming: backs up Flash, then erases/programs/verifies. +if {$argc!=3} {error "Usage: program_flash.tcl image.mcs FLASH_PART fresh-backup.bin"} +lassign $argv image part backup +set image [file normalize $image] +set backup [file normalize $backup] +if {![file isfile $image]} {error "Missing Flash image"} +if {[file exists $backup]} {error "Refusing to overwrite an existing backup"} +if {$part ni {s25fl128sxxxxxx0-spi-x1_x2_x4 s25fl128sxxxxxx1-spi-x1_x2_x4 mt25ql128-spi-x1_x2_x4}} { + error "Select the exact supported 128-Mbit Arty Flash model" +} +open_hw_manager +connect_hw_server -allow_non_jtag +set targets [get_hw_targets -quiet] +if {[llength $targets]!=1} {error "Expected one attached JTAG target"} +open_hw_target [lindex $targets 0] +set devices [get_hw_devices -quiet -filter {PART == xc7a100t}] +if {[llength $devices]!=1} {error "Expected one XC7A100T"} +set device [lindex $devices 0] +current_hw_device $device +set choices [get_cfgmem_parts -of_objects $device -filter "NAME == $part"] +if {[llength $choices]!=1} {error "Flash part is not uniquely compatible with this FPGA"} +create_hw_cfgmem -hw_device $device [lindex $choices 0] +set memory [get_property PROGRAM.HW_CFGMEM $device] +create_hw_bitstream -hw_device $device [get_property PROGRAM.HW_CFGMEM_BITFILE $device] +program_hw_devices $device +file mkdir [file dirname $backup] +readback_hw_cfgmem -all -file $backup -format bin $memory +if {[file size $backup]!=16777216} {error "Incomplete backup; programming cancelled"} +puts "PASS FLASH_BACKUP: $backup bytes=16777216" +set_property PROGRAM.ADDRESS_RANGE use_file $memory +set_property PROGRAM.FILES [list $image] $memory +set_property PROGRAM.BLANK_CHECK 0 $memory +set_property PROGRAM.ERASE 1 $memory +set_property PROGRAM.CFG_PROGRAM 1 $memory +set_property PROGRAM.VERIFY 1 $memory +set_property PROGRAM.CHECKSUM 0 $memory +if {![program_hw_cfgmem $memory]} {error "Flash program/verify failed"} +puts "PASS FLASH_PROGRAM_VERIFY: $part $image" +# JP1 must be shorted; this reloads the FPGA from Flash without downloading .bit. +boot_hw_device -timeout 60 $device +refresh_hw_device $device +if {[get_property REGISTER.CONFIG_STATUS.BIT14_DONE_PIN $device]!=1 || + [get_property REGISTER.CONFIG_STATUS.BIT04_END_OF_STARTUP_(EOS)_STATUS $device]!=1 || + [get_property REGISTER.CONFIG_STATUS.BIT00_CRC_ERROR $device]!=0} { + error "FPGA did not successfully reconfigure from Flash" +} +puts "FLASH_BOOT_CONFIG_STATUS [get_property REGISTER.CONFIG_STATUS $device]" +close_hw_target +disconnect_hw_server +close_hw_manager +exit diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/original-pr/program_flash.tcl.log b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/original-pr/program_flash.tcl.log new file mode 100644 index 0000000..b4d8c99 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/original-pr/program_flash.tcl.log @@ -0,0 +1,3 @@ +PASS FLASH_BACKUP: D:/Verilog_Dev/fpga-arty-a7-pr10-review/platforms/arty-a7-toy/build/original-pr-evaluation/tmps2iklm9m/backup.bin bytes=16777216 +MOCK_EVENTS program_device readback program_flash +MOCK_FAILURE expected boolean value but got "Program and verification completed" diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/RESULT.json new file mode 100644 index 0000000..aeac5b4 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/RESULT.json @@ -0,0 +1,106 @@ +{ + "result": "PASS_OFFLINE_TCL_CONTRACTS", + "physical_hardware_tested": false, + "cases": [ + { + "script": "program_arty.tcl", + "fault": "none", + "result": "PASS" + }, + { + "script": "program_arty.tcl", + "fault": "device_error", + "result": "PASS" + }, + { + "script": "program_arty.tcl", + "fault": "done_low", + "result": "PASS" + }, + { + "script": "program_arty.tcl", + "fault": "eos_low", + "result": "PASS" + }, + { + "script": "program_arty.tcl", + "fault": "crc_error", + "result": "PASS" + }, + { + "script": "backup_flash.tcl", + "fault": "none", + "result": "PASS" + }, + { + "script": "backup_flash.tcl", + "fault": "device_error", + "result": "PASS" + }, + { + "script": "backup_flash.tcl", + "fault": "done_low", + "result": "PASS" + }, + { + "script": "backup_flash.tcl", + "fault": "eos_low", + "result": "PASS" + }, + { + "script": "backup_flash.tcl", + "fault": "crc_error", + "result": "PASS" + }, + { + "script": "backup_flash.tcl", + "fault": "readback_error", + "result": "PASS" + }, + { + "script": "backup_flash.tcl", + "fault": "short_backup", + "result": "PASS" + }, + { + "script": "program_flash.tcl", + "fault": "none", + "result": "PASS" + }, + { + "script": "program_flash.tcl", + "fault": "device_error", + "result": "PASS" + }, + { + "script": "program_flash.tcl", + "fault": "done_low", + "result": "PASS" + }, + { + "script": "program_flash.tcl", + "fault": "eos_low", + "result": "PASS" + }, + { + "script": "program_flash.tcl", + "fault": "crc_error", + "result": "PASS" + }, + { + "script": "program_flash.tcl", + "fault": "readback_error", + "result": "PASS" + }, + { + "script": "program_flash.tcl", + "fault": "short_backup", + "result": "PASS" + }, + { + "script": "program_flash.tcl", + "fault": "cfgmem_error", + "result": "PASS" + } + ] +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/backup_flash.tcl-crc_error.log b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/backup_flash.tcl-crc_error.log new file mode 100644 index 0000000..fca1bae --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/backup_flash.tcl-crc_error.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device +MOCK_FAILURE SPI bridge configuration status rejected diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/backup_flash.tcl-device_error.log b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/backup_flash.tcl-device_error.log new file mode 100644 index 0000000..30ac2d8 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/backup_flash.tcl-device_error.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device +MOCK_FAILURE SPI bridge programming failed: injected programming exception diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/backup_flash.tcl-done_low.log b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/backup_flash.tcl-done_low.log new file mode 100644 index 0000000..fca1bae --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/backup_flash.tcl-done_low.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device +MOCK_FAILURE SPI bridge configuration status rejected diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/backup_flash.tcl-eos_low.log b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/backup_flash.tcl-eos_low.log new file mode 100644 index 0000000..fca1bae --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/backup_flash.tcl-eos_low.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device +MOCK_FAILURE SPI bridge configuration status rejected diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/backup_flash.tcl-none.log b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/backup_flash.tcl-none.log new file mode 100644 index 0000000..9b4b889 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/backup_flash.tcl-none.log @@ -0,0 +1,3 @@ +PASS FLASH_BACKUP: mt25ql128-spi-x1_x2_x4 /home/yys/codex-builds/arty-a7-pr10-review-20261012-6eae4386/build/programming-check/tmpq84v9i8u/backup.bin bytes=16777216 +MOCK_EVENTS program_device readback +MOCK_SUCCESS diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/backup_flash.tcl-readback_error.log b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/backup_flash.tcl-readback_error.log new file mode 100644 index 0000000..450c391 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/backup_flash.tcl-readback_error.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device readback +MOCK_FAILURE Flash readback failed: injected readback exception diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/backup_flash.tcl-short_backup.log b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/backup_flash.tcl-short_backup.log new file mode 100644 index 0000000..20502f0 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/backup_flash.tcl-short_backup.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device readback +MOCK_FAILURE Incomplete Flash backup diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/program_arty.tcl-crc_error.log b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/program_arty.tcl-crc_error.log new file mode 100644 index 0000000..728e8ba --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/program_arty.tcl-crc_error.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device +MOCK_FAILURE JTAG configuration status rejected: expected DONE/EOS high and CRC error clear diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/program_arty.tcl-device_error.log b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/program_arty.tcl-device_error.log new file mode 100644 index 0000000..a98384b --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/program_arty.tcl-device_error.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device +MOCK_FAILURE JTAG programming failed: injected programming exception diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/program_arty.tcl-done_low.log b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/program_arty.tcl-done_low.log new file mode 100644 index 0000000..728e8ba --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/program_arty.tcl-done_low.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device +MOCK_FAILURE JTAG configuration status rejected: expected DONE/EOS high and CRC error clear diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/program_arty.tcl-eos_low.log b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/program_arty.tcl-eos_low.log new file mode 100644 index 0000000..728e8ba --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/program_arty.tcl-eos_low.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device +MOCK_FAILURE JTAG configuration status rejected: expected DONE/EOS high and CRC error clear diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/program_arty.tcl-none.log b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/program_arty.tcl-none.log new file mode 100644 index 0000000..2f251d9 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/program_arty.tcl-none.log @@ -0,0 +1,3 @@ +ARTY_JTAG_PROGRAMMED: /home/yys/codex-builds/arty-a7-pr10-review-20261012-6eae4386/build/programming-check/tmpugs87vr9/input.bit +MOCK_EVENTS program_device +MOCK_SUCCESS diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/program_flash.tcl-cfgmem_error.log b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/program_flash.tcl-cfgmem_error.log new file mode 100644 index 0000000..d4be261 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/program_flash.tcl-cfgmem_error.log @@ -0,0 +1,3 @@ +PASS FLASH_BACKUP: /home/yys/codex-builds/arty-a7-pr10-review-20261012-6eae4386/build/programming-check/tmphbmnyr8t/backup.bin bytes=16777216 +MOCK_EVENTS program_device readback program_flash +MOCK_FAILURE Flash program/verify failed: injected Flash verify exception diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/program_flash.tcl-crc_error.log b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/program_flash.tcl-crc_error.log new file mode 100644 index 0000000..e18af32 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/program_flash.tcl-crc_error.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device +MOCK_FAILURE SPI bridge configuration status rejected; Flash programming cancelled diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/program_flash.tcl-device_error.log b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/program_flash.tcl-device_error.log new file mode 100644 index 0000000..30ac2d8 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/program_flash.tcl-device_error.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device +MOCK_FAILURE SPI bridge programming failed: injected programming exception diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/program_flash.tcl-done_low.log b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/program_flash.tcl-done_low.log new file mode 100644 index 0000000..e18af32 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/program_flash.tcl-done_low.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device +MOCK_FAILURE SPI bridge configuration status rejected; Flash programming cancelled diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/program_flash.tcl-eos_low.log b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/program_flash.tcl-eos_low.log new file mode 100644 index 0000000..e18af32 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/program_flash.tcl-eos_low.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device +MOCK_FAILURE SPI bridge configuration status rejected; Flash programming cancelled diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/program_flash.tcl-none.log b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/program_flash.tcl-none.log new file mode 100644 index 0000000..376a147 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/program_flash.tcl-none.log @@ -0,0 +1,5 @@ +PASS FLASH_BACKUP: /home/yys/codex-builds/arty-a7-pr10-review-20261012-6eae4386/build/programming-check/tmp1d4t8t_b/backup.bin bytes=16777216 +PASS FLASH_PROGRAM_VERIFY: mt25ql128-spi-x1_x2_x4 /home/yys/codex-builds/arty-a7-pr10-review-20261012-6eae4386/build/programming-check/tmp1d4t8t_b/input.bit +FLASH_BOOT_CONFIG_STATUS DONE=1 EOS=1 CRC=0 +MOCK_EVENTS program_device readback program_flash boot +MOCK_SUCCESS diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/program_flash.tcl-readback_error.log b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/program_flash.tcl-readback_error.log new file mode 100644 index 0000000..8cc9ec4 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/program_flash.tcl-readback_error.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device readback +MOCK_FAILURE Flash backup failed; programming cancelled: injected readback exception diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/program_flash.tcl-short_backup.log b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/program_flash.tcl-short_backup.log new file mode 100644 index 0000000..2541aca --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/programming-check/program_flash.tcl-short_backup.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device readback +MOCK_FAILURE Incomplete backup; programming cancelled diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/session.log b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/session.log new file mode 100644 index 0000000..26cef58 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/session.log @@ -0,0 +1,10 @@ +PASS fullwidth AXI: sizes 8..128 bits, INCR/FIXED, strobes, concurrent R/W, stalls, IDs, range/4KiB rejection; read beats=90 +/home/yys/codex-builds/arty-a7-pr10-review-20261012-6eae4386/tests/tb_axi_fullwidth.sv:107: $finish called at 9270000 (1ps) +PASS SCU OpenSBI byte addresses, AXI lanes, RX pop/IRQ, TX backpressure, EXIT +/home/yys/codex-builds/arty-a7-pr10-review-20261012-6eae4386/tests/tb_axi_scu.sv:64: $finish called at 20580000 (1ps) +PASS platform AXI B response: valid, invalid address, unaligned, burst, ID and backpressure +/home/yys/codex-builds/arty-a7-pr10-review-20261012-6eae4386/tests/tb_platform_bresp.sv:52: $finish called at 420000 (1ps) +PASS: DDR UART loader CRC, 256-byte unaligned RAM roundtrip, rejected writes/RUN, timeout and boot +/home/yys/codex-builds/arty-a7-pr10-review-20261012-6eae4386/build/board-unit/tb_ddr_loader.sv:116: $finish called at 78290000 (1ps) +PASS programming scripts: 20 documented-return/status/error cases; no hardware +PASS Flash image guards: 10 normal/-O tamper/control cases; no hardware diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/board/axi_fullwidth.sv b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/board/axi_fullwidth.sv new file mode 100644 index 0000000..a17053c --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/board/axi_fullwidth.sv @@ -0,0 +1,115 @@ +// Serialize each INCR/FIXED AXI beat into an aligned 128-bit MIG transaction. +// Lane positions/strobes and IDs are preserved. Narrow reads may overfetch DDR +// bytes but never MMIO. One read and one write burst can progress independently. +module axi_fullwidth ( + input wire clk, reset, + input wire [3:0] s_awid, s_arid, + input wire [31:0] s_awaddr, s_araddr, + input wire [7:0] s_awlen, s_arlen, + input wire [2:0] s_awsize, s_arsize, + input wire [1:0] s_awburst, s_arburst, + input wire s_awvalid, s_arvalid, s_wvalid, s_wlast, s_bready, s_rready, + output wire s_awready, s_arready, s_wready, + input wire [127:0] s_wdata, input wire [15:0] s_wstrb, + output reg [3:0] s_bid, s_rid, + output reg [1:0] s_bresp, s_rresp, + output reg s_bvalid, s_rvalid, s_rlast, output reg [127:0] s_rdata, + output wire [3:0] m_awid, m_arid, + output wire [27:0] m_awaddr, m_araddr, + output wire [7:0] m_awlen, m_arlen, + output wire [2:0] m_awsize, m_arsize, + output wire [1:0] m_awburst, m_arburst, + output wire m_awvalid, m_arvalid, m_wvalid, m_wlast, m_bready, m_rready, + input wire m_awready, m_arready, m_wready, + output wire [127:0] m_wdata, output wire [15:0] m_wstrb, + input wire [3:0] m_bid, m_rid, + input wire [1:0] m_bresp, m_rresp, + input wire m_bvalid, m_rvalid, m_rlast, input wire [127:0] m_rdata +); + localparam W_IDLE=0, W_DATA=1, W_SEND=2, W_RESP=3; + localparam R_IDLE=0, R_SEND=1, R_RESP=2, R_RETURN=3; + reg [1:0] ws, rs; + reg [31:0] wa, ra; + reg [7:0] wl, rl; + reg [2:0] wz, rz; + reg wi, ri, wbad, rbad, aw_sent, w_sent; + reg [127:0] wd; + reg [15:0] wm; + wire [32:0] wend = {1'b0,s_awaddr} + ({25'd0,s_awlen} << s_awsize); + wire [32:0] rend = {1'b0,s_araddr} + ({25'd0,s_arlen} << s_arsize); + wire wlegal = s_awaddr[31:28]==4'h8 && s_awsize<=4 && s_awburst<=1 && + (s_awaddr & ((32'd1<3 || awburst>1 || + (awaddr & ((31'd1<3 || arburst>1 || (araddr & ((31'd1<=3) rdata[47:40]<={5'd0,framing,overflow,count!=0}; + end else rresp<=2; + end + if(push) begin fifo[wp]<=rx_data;wp<=wp+1'b1;end + if(pop) rp<=rp+1'b1; + case({push,pop}) + 2'b10:count<=count+1'b1; + 2'b01:count<=count-1'b1; + default:count<=count; + endcase + if(rx_valid && !push) overflow<=1; + if(rx_error) framing<=1; + end + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/board/backup_flash.tcl b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/board/backup_flash.tcl new file mode 100644 index 0000000..ad12561 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/board/backup_flash.tcl @@ -0,0 +1,42 @@ +# Read all existing Flash before any erase. This temporarily replaces FPGA SRAM +# with Vivado's SPI bridge, but never requests a Flash write/erase. +if {$argc!=2} {error "Usage: backup_flash.tcl FLASH_PART output.bin"} +lassign $argv part backup +set backup [file normalize $backup] +if {[file exists $backup]} {error "Refusing to overwrite an existing backup"} +if {$part ni {s25fl128sxxxxxx0-spi-x1_x2_x4 s25fl128sxxxxxx1-spi-x1_x2_x4 mt25ql128-spi-x1_x2_x4}} { + error "Select the exact supported 128-Mbit Arty Flash model" +} +open_hw_manager +connect_hw_server -allow_non_jtag +set targets [get_hw_targets -quiet] +if {[llength $targets]!=1} {error "Expected one attached JTAG target"} +open_hw_target [lindex $targets 0] +set devices [get_hw_devices -quiet -filter {PART == xc7a100t}] +if {[llength $devices]!=1} {error "Expected one XC7A100T"} +set device [lindex $devices 0] +current_hw_device $device +set choices [get_cfgmem_parts -of_objects $device -filter "NAME == $part"] +if {[llength $choices]!=1} {error "Flash part is not uniquely compatible with this FPGA"} +create_hw_cfgmem -hw_device $device [lindex $choices 0] +set memory [get_property PROGRAM.HW_CFGMEM $device] +create_hw_bitstream -hw_device $device [get_property PROGRAM.HW_CFGMEM_BITFILE $device] +if {[catch {program_hw_devices $device} message options]} { + return -options $options "SPI bridge programming failed: $message" +} +refresh_hw_device $device +if {[get_property REGISTER.CONFIG_STATUS.BIT14_DONE_PIN $device]!=1 || + [get_property REGISTER.CONFIG_STATUS.BIT04_END_OF_STARTUP_(EOS)_STATUS $device]!=1 || + [get_property REGISTER.CONFIG_STATUS.BIT00_CRC_ERROR $device]!=0} { + error "SPI bridge configuration status rejected" +} +file mkdir [file dirname $backup] +if {[catch {readback_hw_cfgmem -all -file $backup -format bin $memory} message options]} { + return -options $options "Flash readback failed: $message" +} +if {[file size $backup]!=16777216} {error "Incomplete Flash backup"} +puts "PASS FLASH_BACKUP: $part $backup bytes=16777216" +close_hw_target +disconnect_hw_server +close_hw_manager +exit diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/board/ddr_uart_loader.sv b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/board/ddr_uart_loader.sv new file mode 100644 index 0000000..9aa2dc9 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/board/ddr_uart_loader.sv @@ -0,0 +1,169 @@ +// Stop-and-wait serial boot protocol. Requests: A5 5A op seq addrLE32 lenLE16 +// [WRITE payload] crcLE16. CRC-16/CCITT-FALSE covers op through payload. +// Responses: 5A A5 (op|80) seq status lenLE16 [data] crcLE16. +// CRC is checked before any DDR write; CPU starts after the RUN reply drains. +module ddr_uart_loader #( + parameter integer RAM_BYTES = 268435456, + parameter integer CLOCK_HZ = 25000000, + parameter integer RX_TIMEOUT = CLOCK_HZ/10 +) ( + input wire clk, reset, + input wire rx_valid, input wire [7:0] rx_data, input wire rx_error, + output wire tx_valid, output reg [7:0] tx_data, input wire tx_ready, + output reg cpu_run, output reg error_seen, + output wire load_en, + output wire [$clog2(RAM_BYTES)-1:0] load_addr, + output reg [127:0] load_data, + output reg [15:0] load_mask, + input wire load_valid, load_error, input wire [127:0] load_result +); + localparam [3:0] SYNC0=0,SYNC1=1,HEADER=2,PAYLOAD=3,CRC0=4,CRC1=5, + EXECUTE=6,WRITE=7,READ_REQ=8,READ_WAIT=9,REPLY=10,DRAIN=11; + reg [3:0] state; + reg [7:0] operation, sequence_id, status; + reg [31:0] address; + reg [15:0] length, reply_length, crc, received_crc; + reg [8:0] cursor, reply_index; + reg [3:0] header_index; + (* ram_style="distributed" *) reg [7:0] payload [0:255]; + reg pending_run, image_loaded; + reg [$clog2(RX_TIMEOUT+1)-1:0] timeout_count; + wire receiving = state==SYNC1 || state==HEADER || state==PAYLOAD || state==CRC0 || state==CRC1; + wire [32:0] end_address = {1'b0,address}+length; + wire valid_range = length!=0 && length<=256 && address>=32'h80000000 && + end_address<=33'h080000000+RAM_BYTES; + wire [31:0] byte_address = address + cursor; + assign load_addr = byte_address[$clog2(RAM_BYTES)-1:0]; + assign load_en = !cpu_run && (state==WRITE || state==READ_REQ); + always @* begin + load_data=0;load_mask=0; + if(state==WRITE) begin + load_data[byte_address[3:0]*8 +: 8]=payload[cursor[7:0]]; + load_mask=16'b1<> ((reply_index-11)*8); + 15,16,17,18:tx_data=CLOCK_HZ >> ((reply_index-15)*8); + default:tx_data=0; + endcase + else tx_data=payload[(reply_index-7) & 255]; + end + else if(reply_index==7+reply_length) tx_data=crc[7:0]; + else tx_data=crc[15:8]; + end + endcase + end + always @(posedge clk) begin + if(reset) begin + state<=SYNC0;cpu_run<=0;error_seen<=0;image_loaded<=0;pending_run<=0; + operation<=0;sequence_id<=0;status<=0;address<=0;length<=0; + reply_length<=0;crc<=16'hffff;received_crc<=0;cursor<=0; + reply_index<=0;header_index<=0;timeout_count<=0; + end else if(!cpu_run) begin + if(!receiving || rx_valid) timeout_count<=0; + else timeout_count<=timeout_count+1'b1; + if((receiving && timeout_count==RX_TIMEOUT-1) || (receiving && rx_error)) begin + state<=SYNC0;error_seen<=1;timeout_count<=0; + end else case(state) + SYNC0: if(rx_valid && rx_data==8'ha5) state<=SYNC1; + SYNC1: if(rx_valid) begin + if(rx_data==8'h5a) begin + state<=HEADER;header_index<=0;crc<=16'hffff;length<=0;address<=0; + pending_run<=0;reply_index<=0;reply_length<=0;status<=0; + end else if(rx_data!=8'ha5) state<=SYNC0; + end + HEADER: if(rx_valid) begin + crc<=crc_next(crc,rx_data); + case(header_index) + 0:operation<=rx_data; + 1:sequence_id<=rx_data; + 2:address[7:0]<=rx_data; + 3:address[15:8]<=rx_data; + 4:address[23:16]<=rx_data; + 5:address[31:24]<=rx_data; + 6:length[7:0]<=rx_data; + 7:begin + length[15:8]<=rx_data;cursor<=0; + if({rx_data,length[7:0]}>256) begin state<=SYNC0;error_seen<=1;end + else if(operation==1 && {rx_data,length[7:0]}!=0) state<=PAYLOAD; + else state<=CRC0; + end + endcase + header_index<=header_index+1'b1; + end + PAYLOAD: if(rx_valid) begin + payload[cursor[7:0]]<=rx_data;crc<=crc_next(crc,rx_data); + cursor<=cursor+1'b1; + if(cursor+1==length) state<=CRC0; + end + CRC0: if(rx_valid) begin received_crc[7:0]<=rx_data;state<=CRC1;end + CRC1: if(rx_valid) begin + cursor<=0; + if({rx_data,received_crc[7:0]}!=crc) begin + status<=1;error_seen<=1;crc<=16'hffff;state<=REPLY; + end else state<=EXECUTE; + end + EXECUTE: begin + crc<=16'hffff; + if(operation==1 || operation==2) begin + if(!valid_range) begin status<=2;error_seen<=1;state<=REPLY;end + else if(operation==1) state<=WRITE; + else begin reply_length<=length;state<=READ_REQ;end + end else if(operation==3 && length==0 && address==32'h80000000) begin + if(!image_loaded) begin status<=5;error_seen<=1;end + else pending_run<=1; + state<=REPLY; + end else if(operation==4 && length==0 && address==0) begin + reply_length<=12;state<=REPLY; + end else begin status<=3;error_seen<=1;state<=REPLY;end + end + WRITE: if(load_valid) begin + if(load_error) begin status<=6;error_seen<=1;state<=REPLY;end + else if(cursor+1==length) begin image_loaded<=1;state<=REPLY;end + else cursor<=cursor+1'b1; + end + READ_REQ: state<=READ_WAIT; + READ_WAIT: if(load_valid) begin + if(load_error) begin status<=6;error_seen<=1;reply_length<=0;state<=REPLY;end + else begin + payload[cursor[7:0]]<=load_result[byte_address[3:0]*8 +: 8]; + if(cursor+1==length) state<=REPLY; + else begin cursor<=cursor+1'b1;state<=READ_REQ;end + end + end + REPLY: if(tx_ready) begin + if(reply_index>=2 && reply_index<7+reply_length) crc<=crc_next(crc,tx_data); + if(reply_index==8+reply_length) state<=DRAIN; + else reply_index<=reply_index+1'b1; + end + DRAIN: if(tx_ready) begin + if(pending_run) cpu_run<=1; + state<=SYNC0; + end + default:state<=SYNC0; + endcase + end + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/board/flash_spi_byte.sv b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/board/flash_spi_byte.sv new file mode 100644 index 0000000..1610a12 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/board/flash_spi_byte.sv @@ -0,0 +1,33 @@ +// Read-only boot software uses this mode-0 byte engine; no Flash writes in RTL. +// 25 MHz / (2 * 4) = 3.125 MHz. Two MISO synchronizers settle within a half bit. +module flash_spi_byte ( + input wire clk, reset, start, + input wire [7:0] tx_data, + input wire miso, + output reg busy, sck, + output wire mosi, + output reg [7:0] rx_data +); + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg miso_meta, miso_sync; + reg [7:0] shift_tx, shift_rx; + reg [2:0] bit_count; + reg [1:0] divider; + assign mosi=shift_tx[7]; + always @(posedge clk) begin + miso_meta<=miso;miso_sync<=miso_meta; + if(reset) begin + busy<=0;sck<=0;shift_tx<=0;shift_rx<=0;rx_data<=0;bit_count<=0;divider<=0; + end else if(!busy) begin + sck<=0; + if(start) begin busy<=1;shift_tx<=tx_data;shift_rx<=0;bit_count<=0;divider<=0;end + end else if(divider==3) begin + divider<=0;sck<=!sck; + if(!sck) shift_rx<={shift_rx[6:0],miso_sync}; + else begin + shift_tx<={shift_tx[6:0],1'b1}; + if(bit_count==7) begin busy<=0;rx_data<=shift_rx;end + else bit_count<=bit_count+1'b1; + end + end else divider<=divider+1'b1; + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/board/loader_axi.sv b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/board/loader_axi.sv new file mode 100644 index 0000000..096ddb0 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/board/loader_axi.sv @@ -0,0 +1,53 @@ +// Convert a held loader byte request into a completed AXI transaction. +// The loader advances only after B/R. A RELEASE cycle prevents resubmission +// while its synchronous state machine consumes the acknowledgement. +module loader_axi ( + input wire clk, reset, load_en, + input wire [27:0] load_addr, + input wire [127:0] load_data, input wire [15:0] load_mask, + output reg load_valid, load_error, output reg [127:0] load_result, + output wire [27:0] awaddr, araddr, + output wire awvalid, wvalid, arvalid, bready, rready, + input wire awready, wready, arready, bvalid, rvalid, + output wire [127:0] wdata, output wire [15:0] wstrb, + input wire [1:0] bresp, rresp, input wire [127:0] rdata +); + localparam IDLE=0, SEND_W=1, WAIT_B=2, SEND_R=3, WAIT_R=4, RELEASE=5; + reg [2:0] state; + reg [27:0] addr; + reg [127:0] data; + reg [15:0] mask; + reg sent_aw, sent_w; + assign awaddr=addr;assign araddr=addr; + assign wdata=data;assign wstrb=mask; + assign awvalid=!reset && state==SEND_W && !sent_aw; + assign wvalid=!reset && state==SEND_W && !sent_w; + assign arvalid=!reset && state==SEND_R; + assign bready=!reset && state==WAIT_B; + assign rready=!reset && state==WAIT_R; + always @(posedge clk) begin + load_valid<=0; + if(reset) begin + state<=IDLE;addr<=0;data<=0;mask<=0;sent_aw<=0;sent_w<=0; + load_valid<=0;load_error<=0;load_result<=0; + end else case(state) + IDLE:if(load_en) begin + addr<={load_addr[27:4],4'd0};data<=load_data;mask<=load_mask; + sent_aw<=0;sent_w<=0;load_error<=0; + state<=|load_mask ? SEND_W : SEND_R; + end + SEND_W:begin + if(awvalid && awready) sent_aw<=1; + if(wvalid && wready) sent_w<=1; + if((sent_aw || awready) && (sent_w || wready)) state<=WAIT_B; + end + WAIT_B:if(bvalid) begin load_valid<=1;load_error<=bresp!=0;state<=RELEASE;end + SEND_R:if(arready) state<=WAIT_R; + WAIT_R:if(rvalid) begin + load_valid<=1;load_error<=rresp!=0;load_result<=rdata;state<=RELEASE; + end + RELEASE:state<=IDLE; + default:state<=IDLE; + endcase + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/board/program_arty.tcl b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/board/program_arty.tcl new file mode 100644 index 0000000..a328bd8 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/board/program_arty.tcl @@ -0,0 +1,32 @@ +# Volatile JTAG programming only. Usage: +# Confirm physical Rev E DDR compatibility before using this engineering image. +# vivado -mode batch -source board/program_arty.tcl -tclargs /path/to/toy_a7.bit +if {$argc != 1} { error "Supply the Arty A7-100T .bit file" } +set bitfile [file normalize [lindex $argv 0]] +if {![file isfile $bitfile]} { error "Bitstream not found: $bitfile" } +open_hw_manager +connect_hw_server -allow_non_jtag +set targets [get_hw_targets -quiet] +if {[llength $targets] != 1} { + error "Expected one connected JTAG target. Select the Arty manually in Hardware Manager if multiple boards are attached." +} +open_hw_target [lindex $targets 0] +set devices [get_hw_devices -quiet -filter {PART == xc7a100t}] +if {[llength $devices] != 1} { error "Expected one XC7A100T; inspect the connected board" } +set device [lindex $devices 0] +current_hw_device $device +set_property PROGRAM.FILE $bitfile $device +if {[catch {program_hw_devices $device} message options]} { + return -options $options "JTAG programming failed: $message" +} +refresh_hw_device $device +if {[get_property REGISTER.CONFIG_STATUS.BIT14_DONE_PIN $device]!=1 || + [get_property REGISTER.CONFIG_STATUS.BIT04_END_OF_STARTUP_(EOS)_STATUS $device]!=1 || + [get_property REGISTER.CONFIG_STATUS.BIT00_CRC_ERROR $device]!=0} { + error "JTAG configuration status rejected: expected DONE/EOS high and CRC error clear" +} +puts "ARTY_JTAG_PROGRAMMED: $bitfile" +close_hw_target +disconnect_hw_server +close_hw_manager +exit diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/board/program_flash.tcl b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/board/program_flash.tcl new file mode 100644 index 0000000..3b47630 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/board/program_flash.tcl @@ -0,0 +1,63 @@ +# Explicit nonvolatile programming: backs up Flash, then erases/programs/verifies. +if {$argc!=3} {error "Usage: program_flash.tcl image.mcs FLASH_PART fresh-backup.bin"} +lassign $argv image part backup +set image [file normalize $image] +set backup [file normalize $backup] +if {![file isfile $image]} {error "Missing Flash image"} +if {[file exists $backup]} {error "Refusing to overwrite an existing backup"} +if {$part ni {s25fl128sxxxxxx0-spi-x1_x2_x4 s25fl128sxxxxxx1-spi-x1_x2_x4 mt25ql128-spi-x1_x2_x4}} { + error "Select the exact supported 128-Mbit Arty Flash model" +} +open_hw_manager +connect_hw_server -allow_non_jtag +set targets [get_hw_targets -quiet] +if {[llength $targets]!=1} {error "Expected one attached JTAG target"} +open_hw_target [lindex $targets 0] +set devices [get_hw_devices -quiet -filter {PART == xc7a100t}] +if {[llength $devices]!=1} {error "Expected one XC7A100T"} +set device [lindex $devices 0] +current_hw_device $device +set choices [get_cfgmem_parts -of_objects $device -filter "NAME == $part"] +if {[llength $choices]!=1} {error "Flash part is not uniquely compatible with this FPGA"} +create_hw_cfgmem -hw_device $device [lindex $choices 0] +set memory [get_property PROGRAM.HW_CFGMEM $device] +create_hw_bitstream -hw_device $device [get_property PROGRAM.HW_CFGMEM_BITFILE $device] +if {[catch {program_hw_devices $device} message options]} { + return -options $options "SPI bridge programming failed: $message" +} +refresh_hw_device $device +if {[get_property REGISTER.CONFIG_STATUS.BIT14_DONE_PIN $device]!=1 || + [get_property REGISTER.CONFIG_STATUS.BIT04_END_OF_STARTUP_(EOS)_STATUS $device]!=1 || + [get_property REGISTER.CONFIG_STATUS.BIT00_CRC_ERROR $device]!=0} { + error "SPI bridge configuration status rejected; Flash programming cancelled" +} +file mkdir [file dirname $backup] +if {[catch {readback_hw_cfgmem -all -file $backup -format bin $memory} message options]} { + return -options $options "Flash backup failed; programming cancelled: $message" +} +if {[file size $backup]!=16777216} {error "Incomplete backup; programming cancelled"} +puts "PASS FLASH_BACKUP: $backup bytes=16777216" +set_property PROGRAM.ADDRESS_RANGE use_file $memory +set_property PROGRAM.FILES [list $image] $memory +set_property PROGRAM.BLANK_CHECK 0 $memory +set_property PROGRAM.ERASE 1 $memory +set_property PROGRAM.CFG_PROGRAM 1 $memory +set_property PROGRAM.VERIFY 1 $memory +set_property PROGRAM.CHECKSUM 0 $memory +if {[catch {program_hw_cfgmem $memory} message options]} { + return -options $options "Flash program/verify failed: $message" +} +puts "PASS FLASH_PROGRAM_VERIFY: $part $image" +# JP1 must be shorted; this reloads the FPGA from Flash without downloading .bit. +boot_hw_device -timeout 60 $device +refresh_hw_device $device +if {[get_property REGISTER.CONFIG_STATUS.BIT14_DONE_PIN $device]!=1 || + [get_property REGISTER.CONFIG_STATUS.BIT04_END_OF_STARTUP_(EOS)_STATUS $device]!=1 || + [get_property REGISTER.CONFIG_STATUS.BIT00_CRC_ERROR $device]!=0} { + error "FPGA did not successfully reconfigure from Flash" +} +puts "FLASH_BOOT_CONFIG_STATUS [get_property REGISTER.CONFIG_STATUS $device]" +close_hw_target +disconnect_hw_server +close_hw_manager +exit diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/board/toy_a7_platform.sv b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/board/toy_a7_platform.sv new file mode 100644 index 0000000..ade0c4d --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/board/toy_a7_platform.sv @@ -0,0 +1,450 @@ +// Generated wiring; source CPU/accelerator RTL is byte-identical. +module toy_a7_platform #(parameter UART_DIVISOR=25, parameter FLASH_BOOT=0) ( + input wire clk, reset, uart_rx_in, + output wire uart_tx_out, cpu_run, exited, loader_error, + output wire [31:0] exit_code, + output wire [3:0] ddr_awid, + output wire [27:0] ddr_awaddr, + output wire [7:0] ddr_awlen, + output wire [2:0] ddr_awsize, + output wire [1:0] ddr_awburst, + output wire ddr_awvalid, + input wire ddr_awready, + output wire [127:0] ddr_wdata, + output wire [15:0] ddr_wstrb, + output wire ddr_wlast, + output wire ddr_wvalid, + input wire ddr_wready, + input wire [3:0] ddr_bid, + input wire [1:0] ddr_bresp, + input wire ddr_bvalid, + output wire ddr_bready, + output wire [3:0] ddr_arid, + output wire [27:0] ddr_araddr, + output wire [7:0] ddr_arlen, + output wire [2:0] ddr_arsize, + output wire [1:0] ddr_arburst, + output wire ddr_arvalid, + input wire ddr_arready, + input wire [3:0] ddr_rid, + input wire [127:0] ddr_rdata, + input wire [1:0] ddr_rresp, + input wire ddr_rlast, + input wire ddr_rvalid, + output wire ddr_rready, + input wire flash_miso, flash_recovery, + output wire flash_mosi, flash_sck, flash_cs_n +); + wire cpu_reset=reset || !cpu_run; + wire loader_cpu_run; + assign cpu_run=loader_cpu_run || (FLASH_BOOT && !flash_recovery); + wire irq; + wire rx_valid, rx_error, tx_ready, loader_tx_valid, mmio_tx_valid; + wire [7:0] rx_data, loader_tx_data, mmio_tx_data; + wire load_en, load_valid, load_error; wire [27:0] load_addr; + wire [127:0] load_data, load_result; wire [15:0] load_mask; + uart_rx #(.DIVISOR(UART_DIVISOR)) receiver (.clk(clk),.reset(reset),.rx(uart_rx_in), + .valid(rx_valid),.data(rx_data),.frame_error(rx_error)); + uart_tx #(.DIVISOR(UART_DIVISOR)) transmitter (.clk(clk),.reset(reset), + .valid(cpu_run ? mmio_tx_valid : loader_tx_valid),.data(cpu_run ? mmio_tx_data : loader_tx_data), + .ready(tx_ready),.tx(uart_tx_out)); + ddr_uart_loader loader (.clk(clk),.reset(reset),.rx_valid(rx_valid && !cpu_run),.rx_data(rx_data), + .rx_error(rx_error),.tx_valid(loader_tx_valid),.tx_data(loader_tx_data),.tx_ready(tx_ready), + .cpu_run(loader_cpu_run),.error_seen(loader_error),.load_en(load_en),.load_addr(load_addr), + .load_data(load_data),.load_mask(load_mask),.load_valid(load_valid),.load_error(load_error),.load_result(load_result)); + wire memory_aw_ready; + wire memory_aw_valid; + wire [3:0] memory_aw_bits_id; + wire [31:0] memory_aw_bits_addr; + wire [7:0] memory_aw_bits_len; + wire [2:0] memory_aw_bits_size; + wire [1:0] memory_aw_bits_burst; + wire memory_aw_bits_lock; + wire [3:0] memory_aw_bits_cache; + wire [2:0] memory_aw_bits_prot; + wire [3:0] memory_aw_bits_qos; + wire memory_w_ready; + wire memory_w_valid; + wire [127:0] memory_w_bits_data; + wire [15:0] memory_w_bits_strb; + wire memory_w_bits_last; + wire memory_b_ready; + wire memory_b_valid; + wire [3:0] memory_b_bits_id; + wire [1:0] memory_b_bits_resp; + wire memory_ar_ready; + wire memory_ar_valid; + wire [3:0] memory_ar_bits_id; + wire [31:0] memory_ar_bits_addr; + wire [7:0] memory_ar_bits_len; + wire [2:0] memory_ar_bits_size; + wire [1:0] memory_ar_bits_burst; + wire memory_ar_bits_lock; + wire [3:0] memory_ar_bits_cache; + wire [2:0] memory_ar_bits_prot; + wire [3:0] memory_ar_bits_qos; + wire memory_r_ready; + wire memory_r_valid; + wire [3:0] memory_r_bits_id; + wire [127:0] memory_r_bits_data; + wire [1:0] memory_r_bits_resp; + wire memory_r_bits_last; + wire peripherals_aw_ready; + wire peripherals_aw_valid; + wire [1:0] peripherals_aw_bits_id; + wire [30:0] peripherals_aw_bits_addr; + wire [7:0] peripherals_aw_bits_len; + wire [2:0] peripherals_aw_bits_size; + wire [1:0] peripherals_aw_bits_burst; + wire peripherals_aw_bits_lock; + wire [3:0] peripherals_aw_bits_cache; + wire [2:0] peripherals_aw_bits_prot; + wire [3:0] peripherals_aw_bits_qos; + wire peripherals_w_ready; + wire peripherals_w_valid; + wire [63:0] peripherals_w_bits_data; + wire [7:0] peripherals_w_bits_strb; + wire peripherals_w_bits_last; + wire peripherals_b_ready; + wire peripherals_b_valid; + wire [1:0] peripherals_b_bits_id; + wire [1:0] peripherals_b_bits_resp; + wire peripherals_ar_ready; + wire peripherals_ar_valid; + wire [1:0] peripherals_ar_bits_id; + wire [30:0] peripherals_ar_bits_addr; + wire [7:0] peripherals_ar_bits_len; + wire [2:0] peripherals_ar_bits_size; + wire [1:0] peripherals_ar_bits_burst; + wire peripherals_ar_bits_lock; + wire [3:0] peripherals_ar_bits_cache; + wire [2:0] peripherals_ar_bits_prot; + wire [3:0] peripherals_ar_bits_qos; + wire peripherals_r_ready; + wire peripherals_r_valid; + wire [1:0] peripherals_r_bits_id; + wire [63:0] peripherals_r_bits_data; + wire [1:0] peripherals_r_bits_resp; + wire peripherals_r_bits_last; + ToyLinuxChip chip ( + .clock(clk), + .reset(cpu_reset), + .interrupt(irq), + .memory_aw_ready(memory_aw_ready), + .memory_aw_valid(memory_aw_valid), + .memory_aw_bits_id(memory_aw_bits_id), + .memory_aw_bits_addr(memory_aw_bits_addr), + .memory_aw_bits_len(memory_aw_bits_len), + .memory_aw_bits_size(memory_aw_bits_size), + .memory_aw_bits_burst(memory_aw_bits_burst), + .memory_aw_bits_lock(memory_aw_bits_lock), + .memory_aw_bits_cache(memory_aw_bits_cache), + .memory_aw_bits_prot(memory_aw_bits_prot), + .memory_aw_bits_qos(memory_aw_bits_qos), + .memory_w_ready(memory_w_ready), + .memory_w_valid(memory_w_valid), + .memory_w_bits_data(memory_w_bits_data), + .memory_w_bits_strb(memory_w_bits_strb), + .memory_w_bits_last(memory_w_bits_last), + .memory_b_ready(memory_b_ready), + .memory_b_valid(memory_b_valid), + .memory_b_bits_id(memory_b_bits_id), + .memory_b_bits_resp(memory_b_bits_resp), + .memory_ar_ready(memory_ar_ready), + .memory_ar_valid(memory_ar_valid), + .memory_ar_bits_id(memory_ar_bits_id), + .memory_ar_bits_addr(memory_ar_bits_addr), + .memory_ar_bits_len(memory_ar_bits_len), + .memory_ar_bits_size(memory_ar_bits_size), + .memory_ar_bits_burst(memory_ar_bits_burst), + .memory_ar_bits_lock(memory_ar_bits_lock), + .memory_ar_bits_cache(memory_ar_bits_cache), + .memory_ar_bits_prot(memory_ar_bits_prot), + .memory_ar_bits_qos(memory_ar_bits_qos), + .memory_r_ready(memory_r_ready), + .memory_r_valid(memory_r_valid), + .memory_r_bits_id(memory_r_bits_id), + .memory_r_bits_data(memory_r_bits_data), + .memory_r_bits_resp(memory_r_bits_resp), + .memory_r_bits_last(memory_r_bits_last), + .peripherals_aw_ready(peripherals_aw_ready), + .peripherals_aw_valid(peripherals_aw_valid), + .peripherals_aw_bits_id(peripherals_aw_bits_id), + .peripherals_aw_bits_addr(peripherals_aw_bits_addr), + .peripherals_aw_bits_len(peripherals_aw_bits_len), + .peripherals_aw_bits_size(peripherals_aw_bits_size), + .peripherals_aw_bits_burst(peripherals_aw_bits_burst), + .peripherals_aw_bits_lock(peripherals_aw_bits_lock), + .peripherals_aw_bits_cache(peripherals_aw_bits_cache), + .peripherals_aw_bits_prot(peripherals_aw_bits_prot), + .peripherals_aw_bits_qos(peripherals_aw_bits_qos), + .peripherals_w_ready(peripherals_w_ready), + .peripherals_w_valid(peripherals_w_valid), + .peripherals_w_bits_data(peripherals_w_bits_data), + .peripherals_w_bits_strb(peripherals_w_bits_strb), + .peripherals_w_bits_last(peripherals_w_bits_last), + .peripherals_b_ready(peripherals_b_ready), + .peripherals_b_valid(peripherals_b_valid), + .peripherals_b_bits_id(peripherals_b_bits_id), + .peripherals_b_bits_resp(peripherals_b_bits_resp), + .peripherals_ar_ready(peripherals_ar_ready), + .peripherals_ar_valid(peripherals_ar_valid), + .peripherals_ar_bits_id(peripherals_ar_bits_id), + .peripherals_ar_bits_addr(peripherals_ar_bits_addr), + .peripherals_ar_bits_len(peripherals_ar_bits_len), + .peripherals_ar_bits_size(peripherals_ar_bits_size), + .peripherals_ar_bits_burst(peripherals_ar_bits_burst), + .peripherals_ar_bits_lock(peripherals_ar_bits_lock), + .peripherals_ar_bits_cache(peripherals_ar_bits_cache), + .peripherals_ar_bits_prot(peripherals_ar_bits_prot), + .peripherals_ar_bits_qos(peripherals_ar_bits_qos), + .peripherals_r_ready(peripherals_r_ready), + .peripherals_r_valid(peripherals_r_valid), + .peripherals_r_bits_id(peripherals_r_bits_id), + .peripherals_r_bits_data(peripherals_r_bits_data), + .peripherals_r_bits_resp(peripherals_r_bits_resp), + .peripherals_r_bits_last(peripherals_r_bits_last) + ); + wire [3:0] c_awid; + wire [27:0] c_awaddr; + wire [7:0] c_awlen; + wire [2:0] c_awsize; + wire [1:0] c_awburst; + wire c_awvalid; + wire c_awready; + wire [127:0] c_wdata; + wire [15:0] c_wstrb; + wire c_wlast; + wire c_wvalid; + wire c_wready; + wire [3:0] c_bid; + wire [1:0] c_bresp; + wire c_bvalid; + wire c_bready; + wire [3:0] c_arid; + wire [27:0] c_araddr; + wire [7:0] c_arlen; + wire [2:0] c_arsize; + wire [1:0] c_arburst; + wire c_arvalid; + wire c_arready; + wire [3:0] c_rid; + wire [127:0] c_rdata; + wire [1:0] c_rresp; + wire c_rlast; + wire c_rvalid; + wire c_rready; + wire [3:0] l_awid; + wire [27:0] l_awaddr; + wire [7:0] l_awlen; + wire [2:0] l_awsize; + wire [1:0] l_awburst; + wire l_awvalid; + wire l_awready; + wire [127:0] l_wdata; + wire [15:0] l_wstrb; + wire l_wlast; + wire l_wvalid; + wire l_wready; + wire [3:0] l_bid; + wire [1:0] l_bresp; + wire l_bvalid; + wire l_bready; + wire [3:0] l_arid; + wire [27:0] l_araddr; + wire [7:0] l_arlen; + wire [2:0] l_arsize; + wire [1:0] l_arburst; + wire l_arvalid; + wire l_arready; + wire [3:0] l_rid; + wire [127:0] l_rdata; + wire [1:0] l_rresp; + wire l_rlast; + wire l_rvalid; + wire l_rready; + axi_fullwidth normalizer ( + .clk(clk), + .reset(reset), + .s_awid(memory_aw_bits_id), + .m_awid(c_awid), + .s_awaddr(memory_aw_bits_addr), + .m_awaddr(c_awaddr), + .s_awlen(memory_aw_bits_len), + .m_awlen(c_awlen), + .s_awsize(memory_aw_bits_size), + .m_awsize(c_awsize), + .s_awburst(memory_aw_bits_burst), + .m_awburst(c_awburst), + .s_awvalid(memory_aw_valid), + .m_awvalid(c_awvalid), + .s_awready(memory_aw_ready), + .m_awready(c_awready), + .s_wdata(memory_w_bits_data), + .m_wdata(c_wdata), + .s_wstrb(memory_w_bits_strb), + .m_wstrb(c_wstrb), + .s_wlast(memory_w_bits_last), + .m_wlast(c_wlast), + .s_wvalid(memory_w_valid), + .m_wvalid(c_wvalid), + .s_wready(memory_w_ready), + .m_wready(c_wready), + .s_bid(memory_b_bits_id), + .m_bid(c_bid), + .s_bresp(memory_b_bits_resp), + .m_bresp(c_bresp), + .s_bvalid(memory_b_valid), + .m_bvalid(c_bvalid), + .s_bready(memory_b_ready), + .m_bready(c_bready), + .s_arid(memory_ar_bits_id), + .m_arid(c_arid), + .s_araddr(memory_ar_bits_addr), + .m_araddr(c_araddr), + .s_arlen(memory_ar_bits_len), + .m_arlen(c_arlen), + .s_arsize(memory_ar_bits_size), + .m_arsize(c_arsize), + .s_arburst(memory_ar_bits_burst), + .m_arburst(c_arburst), + .s_arvalid(memory_ar_valid), + .m_arvalid(c_arvalid), + .s_arready(memory_ar_ready), + .m_arready(c_arready), + .s_rid(memory_r_bits_id), + .m_rid(c_rid), + .s_rdata(memory_r_bits_data), + .m_rdata(c_rdata), + .s_rresp(memory_r_bits_resp), + .m_rresp(c_rresp), + .s_rlast(memory_r_bits_last), + .m_rlast(c_rlast), + .s_rvalid(memory_r_valid), + .m_rvalid(c_rvalid), + .s_rready(memory_r_ready), + .m_rready(c_rready) + ); + loader_axi load_bridge ( + .clk(clk), + .reset(reset), + .load_en(load_en), + .load_addr(load_addr), + .load_data(load_data), + .load_mask(load_mask), + .load_valid(load_valid), + .load_error(load_error), + .load_result(load_result), + .awaddr(l_awaddr), + .araddr(l_araddr), + .awvalid(l_awvalid), + .wvalid(l_wvalid), + .arvalid(l_arvalid), + .bready(l_bready), + .rready(l_rready), + .awready(l_awready), + .wready(l_wready), + .arready(l_arready), + .bvalid(l_bvalid), + .rvalid(l_rvalid), + .wdata(l_wdata), + .wstrb(l_wstrb), + .bresp(l_bresp), + .rresp(l_rresp), + .rdata(l_rdata) + ); + assign l_awid=0; + assign l_arid=0; + assign l_awlen=0; + assign l_arlen=0; + assign l_awsize=4; + assign l_arsize=4; + assign l_awburst=1; + assign l_arburst=1; + assign l_wlast=1; + assign ddr_awid=cpu_run ? c_awid : l_awid; + assign ddr_awaddr=cpu_run ? c_awaddr : l_awaddr; + assign ddr_awlen=cpu_run ? c_awlen : l_awlen; + assign ddr_awsize=cpu_run ? c_awsize : l_awsize; + assign ddr_awburst=cpu_run ? c_awburst : l_awburst; + assign ddr_awvalid=cpu_run ? c_awvalid : l_awvalid; + assign c_awready=ddr_awready && cpu_run; + assign l_awready=ddr_awready && !cpu_run; + assign ddr_wdata=cpu_run ? c_wdata : l_wdata; + assign ddr_wstrb=cpu_run ? c_wstrb : l_wstrb; + assign ddr_wlast=cpu_run ? c_wlast : l_wlast; + assign ddr_wvalid=cpu_run ? c_wvalid : l_wvalid; + assign c_wready=ddr_wready && cpu_run; + assign l_wready=ddr_wready && !cpu_run; + assign c_bid=ddr_bid; + assign l_bid=ddr_bid; + assign c_bresp=ddr_bresp; + assign l_bresp=ddr_bresp; + assign c_bvalid=ddr_bvalid && cpu_run; + assign l_bvalid=ddr_bvalid && !cpu_run; + assign ddr_bready=cpu_run ? c_bready : l_bready; + assign ddr_arid=cpu_run ? c_arid : l_arid; + assign ddr_araddr=cpu_run ? c_araddr : l_araddr; + assign ddr_arlen=cpu_run ? c_arlen : l_arlen; + assign ddr_arsize=cpu_run ? c_arsize : l_arsize; + assign ddr_arburst=cpu_run ? c_arburst : l_arburst; + assign ddr_arvalid=cpu_run ? c_arvalid : l_arvalid; + assign c_arready=ddr_arready && cpu_run; + assign l_arready=ddr_arready && !cpu_run; + assign c_rid=ddr_rid; + assign l_rid=ddr_rid; + assign c_rdata=ddr_rdata; + assign l_rdata=ddr_rdata; + assign c_rresp=ddr_rresp; + assign l_rresp=ddr_rresp; + assign c_rlast=ddr_rlast; + assign l_rlast=ddr_rlast; + assign c_rvalid=ddr_rvalid && cpu_run; + assign l_rvalid=ddr_rvalid && !cpu_run; + assign ddr_rready=cpu_run ? c_rready : l_rready; + wire [1:0] scu_bresp; + assign peripherals_b_bits_resp=scu_bresp; + axi_scu #(.FLASH_BOOT(FLASH_BOOT)) peripherals ( + .clk(clk), + .reset(cpu_reset), + .awid(peripherals_aw_bits_id), + .awaddr(peripherals_aw_bits_addr), + .awlen(peripherals_aw_bits_len), + .awsize(peripherals_aw_bits_size), + .awburst(peripherals_aw_bits_burst), + .awvalid(peripherals_aw_valid), + .awready(peripherals_aw_ready), + .wdata(peripherals_w_bits_data), + .wstrb(peripherals_w_bits_strb), + .wlast(peripherals_w_bits_last), + .wvalid(peripherals_w_valid), + .wready(peripherals_w_ready), + .bid(peripherals_b_bits_id), + .bresp(scu_bresp), + .bvalid(peripherals_b_valid), + .bready(peripherals_b_ready), + .arid(peripherals_ar_bits_id), + .araddr(peripherals_ar_bits_addr), + .arlen(peripherals_ar_bits_len), + .arsize(peripherals_ar_bits_size), + .arburst(peripherals_ar_bits_burst), + .arvalid(peripherals_ar_valid), + .arready(peripherals_ar_ready), + .rid(peripherals_r_bits_id), + .rdata(peripherals_r_bits_data), + .rresp(peripherals_r_bits_resp), + .rlast(peripherals_r_bits_last), + .rvalid(peripherals_r_valid), + .rready(peripherals_r_ready), + .rx_valid(rx_valid && cpu_run), + .rx_data(rx_data), + .rx_error(rx_error), + .tx_valid(mmio_tx_valid), + .tx_data(mmio_tx_data), + .tx_ready(tx_ready), + .exited(exited), + .exit_code(exit_code), + .interrupt(irq),.flash_miso(flash_miso),.flash_recovery(flash_recovery), + .flash_mosi(flash_mosi),.flash_sck(flash_sck),.flash_cs_n(flash_cs_n) + ); +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/board/toy_a7_top.sv b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/board/toy_a7_top.sv new file mode 100644 index 0000000..397a262 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/board/toy_a7_top.sv @@ -0,0 +1,305 @@ +module toy_a7_top #(parameter FLASH_BOOT=0) ( + input wire CLK100MHZ, btn0, uart_txd_in, output wire uart_rxd_out, output wire [3:0] led, + inout wire [15:0] ddr3_dq, inout wire [1:0] ddr3_dqs_n, ddr3_dqs_p, + output wire [13:0] ddr3_addr, output wire [2:0] ddr3_ba, + output wire ddr3_ras_n, ddr3_cas_n, ddr3_we_n, ddr3_reset_n, + output wire [0:0] ddr3_ck_p, ddr3_ck_n, ddr3_cke, ddr3_cs_n, ddr3_odt, output wire [1:0] ddr3_dm, + input wire sw0, flash_miso, + output wire flash_mosi, flash_cs_n, flash_wp_n, flash_hold_n +); + wire clk_in,fb,fb_buf,core_raw,sys_raw,ref_raw,clk,sys_clk,ref_clk,locked; + IBUF input_clock (.I(CLK100MHZ),.O(clk_in)); + MMCME2_BASE #(.CLKIN1_PERIOD(10.0),.DIVCLK_DIVIDE(1),.CLKFBOUT_MULT_F(10.0), + .CLKOUT0_DIVIDE_F(40.0),.CLKOUT1_DIVIDE(6),.CLKOUT2_DIVIDE(5)) clock_mmcm ( + .CLKIN1(clk_in),.CLKFBIN(fb_buf),.CLKFBOUT(fb),.CLKOUT0(core_raw), + .CLKOUT1(sys_raw),.CLKOUT2(ref_raw),.LOCKED(locked),.RST(1'b0),.PWRDWN(1'b0)); + BUFG fb_buffer (.I(fb),.O(fb_buf)); BUFG core_buffer (.I(core_raw),.O(clk)); + BUFG sys_buffer (.I(sys_raw),.O(sys_clk)); BUFG ref_buffer (.I(ref_raw),.O(ref_clk)); + wire ui_clk,ui_rst,mig_locked,calibrated; + wire flash_sck; + assign flash_wp_n=1;assign flash_hold_n=1; + generate if(FLASH_BOOT) begin : flash_clock + STARTUPE2 startup (.CLK(1'b0),.GSR(1'b0),.GTS(1'b0),.KEYCLEARB(1'b1),.PACK(1'b0), + .USRCCLKO(flash_sck),.USRCCLKTS(1'b0),.USRDONEO(1'b1),.USRDONETS(1'b1), + .CFGCLK(),.CFGMCLK(),.EOS(),.PREQ()); + end endgenerate + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg sw_meta=0,sw_sync=0; + reg flash_recovery=0; + always @(posedge clk) begin + sw_meta<=sw0;sw_sync<=sw_meta; + if(reset) flash_recovery<=sw_sync; + end + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg [2:0] lock_sync=7; + always @(posedge clk or negedge locked) if(!locked) lock_sync<=7;else lock_sync<={lock_sync[1:0],1'b0}; + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg btn_meta=0,btn_sync=0; + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg btn_ref_meta=0,btn_ref_sync=0; + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg [2:0] mig_resetn_pipe=0; + always @(posedge ref_clk) begin btn_ref_meta<=btn0;btn_ref_sync<=btn_ref_meta;end + always @(posedge ref_clk or negedge locked) if(!locked) mig_resetn_pipe<=0; + else mig_resetn_pipe<={mig_resetn_pipe[1:0],!btn_ref_sync}; + wire mig_resetn=mig_resetn_pipe[2]; + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg [1:0] calib_sync=0; + always @(posedge clk) begin btn_meta<=btn0;btn_sync<=btn_meta;calib_sync<={calib_sync[0],calibrated};end + reg [17:0] reset_count=0;wire reset=lock_sync[2] || btn_sync || !calib_sync[1] || !(&reset_count); + always @(posedge clk) if(lock_sync[2] || btn_sync || !calib_sync[1]) reset_count<=0; + else if(!(&reset_count)) reset_count<=reset_count+1'b1; + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg [2:0] ui_reset_pipe=7; + always @(posedge ui_clk or posedge ui_rst) if(ui_rst) ui_reset_pipe<=7; + else ui_reset_pipe<={ui_reset_pipe[1:0],1'b0}; + wire ui_aresetn=~ui_reset_pipe[2]; + wire cpu_run,exited,loader_error;wire [31:0] exit_code;reg [24:0] heartbeat=0; + always @(posedge clk) if(reset) heartbeat<=0;else heartbeat<=heartbeat+1'b1; + assign led={heartbeat[24],cpu_run && !reset,loader_error || (exited && exit_code!=0),calib_sync[1]}; + wire [3:0] ddr_awid; + wire [27:0] ddr_awaddr; + wire [7:0] ddr_awlen; + wire [2:0] ddr_awsize; + wire [1:0] ddr_awburst; + wire ddr_awvalid; + wire ddr_awready; + wire [127:0] ddr_wdata; + wire [15:0] ddr_wstrb; + wire ddr_wlast; + wire ddr_wvalid; + wire ddr_wready; + wire [3:0] ddr_bid; + wire [1:0] ddr_bresp; + wire ddr_bvalid; + wire ddr_bready; + wire [3:0] ddr_arid; + wire [27:0] ddr_araddr; + wire [7:0] ddr_arlen; + wire [2:0] ddr_arsize; + wire [1:0] ddr_arburst; + wire ddr_arvalid; + wire ddr_arready; + wire [3:0] ddr_rid; + wire [127:0] ddr_rdata; + wire [1:0] ddr_rresp; + wire ddr_rlast; + wire ddr_rvalid; + wire ddr_rready; + wire [3:0] ui_awid; + wire [27:0] ui_awaddr; + wire [7:0] ui_awlen; + wire [2:0] ui_awsize; + wire [1:0] ui_awburst; + wire ui_awvalid; + wire ui_awready; + wire [127:0] ui_wdata; + wire [15:0] ui_wstrb; + wire ui_wlast; + wire ui_wvalid; + wire ui_wready; + wire [3:0] ui_bid; + wire [1:0] ui_bresp; + wire ui_bvalid; + wire ui_bready; + wire [3:0] ui_arid; + wire [27:0] ui_araddr; + wire [7:0] ui_arlen; + wire [2:0] ui_arsize; + wire [1:0] ui_arburst; + wire ui_arvalid; + wire ui_arready; + wire [3:0] ui_rid; + wire [127:0] ui_rdata; + wire [1:0] ui_rresp; + wire ui_rlast; + wire ui_rvalid; + wire ui_rready; + toy_a7_platform #(.FLASH_BOOT(FLASH_BOOT)) platform ( + .clk(clk), + .reset(reset), + .uart_rx_in(uart_txd_in), + .uart_tx_out(uart_rxd_out), + .cpu_run(cpu_run), + .exited(exited), + .loader_error(loader_error), + .exit_code(exit_code), + .flash_miso(flash_miso),.flash_mosi(flash_mosi),.flash_sck(flash_sck), + .flash_cs_n(flash_cs_n),.flash_recovery(flash_recovery), + .ddr_awid(ddr_awid), + .ddr_awaddr(ddr_awaddr), + .ddr_awlen(ddr_awlen), + .ddr_awsize(ddr_awsize), + .ddr_awburst(ddr_awburst), + .ddr_awvalid(ddr_awvalid), + .ddr_awready(ddr_awready), + .ddr_wdata(ddr_wdata), + .ddr_wstrb(ddr_wstrb), + .ddr_wlast(ddr_wlast), + .ddr_wvalid(ddr_wvalid), + .ddr_wready(ddr_wready), + .ddr_bid(ddr_bid), + .ddr_bresp(ddr_bresp), + .ddr_bvalid(ddr_bvalid), + .ddr_bready(ddr_bready), + .ddr_arid(ddr_arid), + .ddr_araddr(ddr_araddr), + .ddr_arlen(ddr_arlen), + .ddr_arsize(ddr_arsize), + .ddr_arburst(ddr_arburst), + .ddr_arvalid(ddr_arvalid), + .ddr_arready(ddr_arready), + .ddr_rid(ddr_rid), + .ddr_rdata(ddr_rdata), + .ddr_rresp(ddr_rresp), + .ddr_rlast(ddr_rlast), + .ddr_rvalid(ddr_rvalid), + .ddr_rready(ddr_rready) + ); + toy_axi_cdc memory_cdc ( + .s_axi_aclk(clk), + .s_axi_aresetn(!reset), + .m_axi_aclk(ui_clk), + .m_axi_aresetn(ui_aresetn), + .s_axi_awid(ddr_awid), + .s_axi_awaddr(ddr_awaddr), + .s_axi_awlen(ddr_awlen), + .s_axi_awsize(ddr_awsize), + .s_axi_awburst(ddr_awburst), + .s_axi_awvalid(ddr_awvalid), + .s_axi_awready(ddr_awready), + .s_axi_wdata(ddr_wdata), + .s_axi_wstrb(ddr_wstrb), + .s_axi_wlast(ddr_wlast), + .s_axi_wvalid(ddr_wvalid), + .s_axi_wready(ddr_wready), + .s_axi_bid(ddr_bid), + .s_axi_bresp(ddr_bresp), + .s_axi_bvalid(ddr_bvalid), + .s_axi_bready(ddr_bready), + .s_axi_arid(ddr_arid), + .s_axi_araddr(ddr_araddr), + .s_axi_arlen(ddr_arlen), + .s_axi_arsize(ddr_arsize), + .s_axi_arburst(ddr_arburst), + .s_axi_arvalid(ddr_arvalid), + .s_axi_arready(ddr_arready), + .s_axi_rid(ddr_rid), + .s_axi_rdata(ddr_rdata), + .s_axi_rresp(ddr_rresp), + .s_axi_rlast(ddr_rlast), + .s_axi_rvalid(ddr_rvalid), + .s_axi_rready(ddr_rready), + .s_axi_awlock(1'b0), + .s_axi_arlock(1'b0), + .s_axi_awcache(4'b0011), + .s_axi_arcache(4'b0011), + .s_axi_awprot(3'd0), + .s_axi_arprot(3'd0), + .s_axi_awqos(4'd0), + .s_axi_arqos(4'd0), + .s_axi_awregion(4'd0), + .s_axi_arregion(4'd0), + .m_axi_awid(ui_awid), + .m_axi_awaddr(ui_awaddr), + .m_axi_awlen(ui_awlen), + .m_axi_awsize(ui_awsize), + .m_axi_awburst(ui_awburst), + .m_axi_awvalid(ui_awvalid), + .m_axi_awready(ui_awready), + .m_axi_wdata(ui_wdata), + .m_axi_wstrb(ui_wstrb), + .m_axi_wlast(ui_wlast), + .m_axi_wvalid(ui_wvalid), + .m_axi_wready(ui_wready), + .m_axi_bid(ui_bid), + .m_axi_bresp(ui_bresp), + .m_axi_bvalid(ui_bvalid), + .m_axi_bready(ui_bready), + .m_axi_arid(ui_arid), + .m_axi_araddr(ui_araddr), + .m_axi_arlen(ui_arlen), + .m_axi_arsize(ui_arsize), + .m_axi_arburst(ui_arburst), + .m_axi_arvalid(ui_arvalid), + .m_axi_arready(ui_arready), + .m_axi_rid(ui_rid), + .m_axi_rdata(ui_rdata), + .m_axi_rresp(ui_rresp), + .m_axi_rlast(ui_rlast), + .m_axi_rvalid(ui_rvalid), + .m_axi_rready(ui_rready), + .m_axi_awlock(), + .m_axi_arlock(), + .m_axi_awcache(), + .m_axi_arcache(), + .m_axi_awprot(), + .m_axi_arprot(), + .m_axi_awqos(), + .m_axi_arqos(), + .m_axi_awregion(), + .m_axi_arregion() + ); + arty_ddr3 ddr_controller ( + .ddr3_dq(ddr3_dq), + .ddr3_dqs_n(ddr3_dqs_n), + .ddr3_dqs_p(ddr3_dqs_p), + .ddr3_addr(ddr3_addr), + .ddr3_ba(ddr3_ba), + .ddr3_ras_n(ddr3_ras_n), + .ddr3_cas_n(ddr3_cas_n), + .ddr3_we_n(ddr3_we_n), + .ddr3_reset_n(ddr3_reset_n), + .ddr3_ck_p(ddr3_ck_p), + .ddr3_ck_n(ddr3_ck_n), + .ddr3_cke(ddr3_cke), + .ddr3_cs_n(ddr3_cs_n), + .ddr3_dm(ddr3_dm), + .ddr3_odt(ddr3_odt), + .sys_clk_i(sys_clk), + .clk_ref_i(ref_clk), + .sys_rst(mig_resetn), + .ui_clk(ui_clk), + .ui_clk_sync_rst(ui_rst), + .mmcm_locked(mig_locked), + .aresetn(ui_aresetn), + .init_calib_complete(calibrated), + .device_temp(), + .app_sr_req(1'b0), + .app_ref_req(1'b0), + .app_zq_req(1'b0), + .app_sr_active(), + .app_ref_ack(), + .app_zq_ack(), + .s_axi_awid(ui_awid), + .s_axi_awaddr(ui_awaddr), + .s_axi_awlen(ui_awlen), + .s_axi_awsize(ui_awsize), + .s_axi_awburst(ui_awburst), + .s_axi_awvalid(ui_awvalid), + .s_axi_awready(ui_awready), + .s_axi_wdata(ui_wdata), + .s_axi_wstrb(ui_wstrb), + .s_axi_wlast(ui_wlast), + .s_axi_wvalid(ui_wvalid), + .s_axi_wready(ui_wready), + .s_axi_bid(ui_bid), + .s_axi_bresp(ui_bresp), + .s_axi_bvalid(ui_bvalid), + .s_axi_bready(ui_bready), + .s_axi_arid(ui_arid), + .s_axi_araddr(ui_araddr), + .s_axi_arlen(ui_arlen), + .s_axi_arsize(ui_arsize), + .s_axi_arburst(ui_arburst), + .s_axi_arvalid(ui_arvalid), + .s_axi_arready(ui_arready), + .s_axi_rid(ui_rid), + .s_axi_rdata(ui_rdata), + .s_axi_rresp(ui_rresp), + .s_axi_rlast(ui_rlast), + .s_axi_rvalid(ui_rvalid), + .s_axi_rready(ui_rready), + .s_axi_awlock(1'b0), + .s_axi_arlock(1'b0), + .s_axi_awcache(4'b0011), + .s_axi_arcache(4'b0011), + .s_axi_awprot(3'd0), + .s_axi_arprot(3'd0), + .s_axi_awqos(4'd0), + .s_axi_arqos(4'd0) + ); +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/board/uart_rx.sv b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/board/uart_rx.sv new file mode 100644 index 0000000..567b8b4 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/board/uart_rx.sv @@ -0,0 +1,40 @@ +// 8-N-1 receiver. Data is sampled in the middle of each bit after a verified +// start bit. A held-low/broken line reports one framing error, then waits high. +module uart_rx #( + parameter integer DIVISOR = 434 +) ( + input wire clk, reset, rx, + output reg valid, + output reg [7:0] data, + output reg frame_error +); + (* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) reg rx_meta = 1, rx_sync = 1; + always @(posedge clk) begin rx_meta <= rx; rx_sync <= rx_meta; end + localparam integer WIDTH = $clog2(DIVISOR) < 1 ? 1 : $clog2(DIVISOR); + localparam [2:0] IDLE=0, START=1, DATA=2, STOP=3, WAIT_HIGH=4; + reg [2:0] state, bit_index; + reg [WIDTH-1:0] count; + reg [7:0] shift; + always @(posedge clk) begin + valid <= 0; frame_error <= 0; + if (reset) begin + state <= IDLE; bit_index <= 0; count <= 0; shift <= 0; data <= 0; + end else case (state) + IDLE: if (!rx_sync) begin state <= START; count <= DIVISOR/2 - 1; end + START: if (count != 0) count <= count - 1'b1; + else if (rx_sync) state <= IDLE; + else begin state <= DATA; bit_index <= 0; count <= DIVISOR - 1; end + DATA: if (count != 0) count <= count - 1'b1; + else begin + shift[bit_index] <= rx_sync; count <= DIVISOR - 1; + if (bit_index == 7) state <= STOP; + else bit_index <= bit_index + 1'b1; + end + STOP: if (count != 0) count <= count - 1'b1; + else if (rx_sync) begin data <= shift; valid <= 1; state <= IDLE; end + else begin frame_error <= 1; state <= WAIT_HIGH; end + WAIT_HIGH: if (rx_sync) state <= IDLE; + default: state <= IDLE; + endcase + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/board/uart_tx.sv b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/board/uart_tx.sv new file mode 100644 index 0000000..11f6e4a --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/board/uart_tx.sv @@ -0,0 +1,37 @@ +module uart_tx #( + parameter integer DIVISOR = 434 // 50 MHz / 115200, error < 0.01%. +) ( + input wire clk, + input wire reset, + input wire valid, + input wire [7:0] data, + output wire ready, + output wire tx +); + localparam integer COUNT_BITS = $clog2(DIVISOR) < 1 ? 1 : $clog2(DIVISOR); + reg [COUNT_BITS-1:0] count; + reg [9:0] shift; + reg [3:0] bits_left; + assign ready = bits_left == 0; + assign tx = shift[0]; + + always @(posedge clk) begin + if (reset) begin + count <= 0; + shift <= 10'h3ff; + bits_left <= 0; + end else if (ready) begin + if (valid) begin + shift <= {1'b1, data, 1'b0}; + bits_left <= 10; + count <= DIVISOR - 1; + end + end else if (count == 0) begin + shift <= {1'b1, shift[9:1]}; + bits_left <= bits_left - 1'b1; + count <= DIVISOR - 1; + end else begin + count <= count - 1'b1; + end + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/host/flash.py b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/host/flash.py new file mode 100644 index 0000000..6c518ab --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/host/flash.py @@ -0,0 +1,168 @@ +"""Back up/program/verify Flash and check automatic Linux startup, within 1 hour.""" + +import argparse +from datetime import datetime +import hashlib +import json +from pathlib import Path +import subprocess +import shutil +import time + +from observe_flash_boot import Observer + +ROOT = Path(__file__).resolve().parents[1] + + +def sha(path): + return hashlib.sha256(path.read_bytes()).hexdigest() + + +def main(): + p = argparse.ArgumentParser(description=__doc__) + p.add_argument("--vivado", default="vivado") + p.add_argument("--bitstream", type=Path, required=True) + p.add_argument( + "--payload", + type=Path, + required=True, + help="Packed TOYFLZ4 software, not the raw image", + ) + p.add_argument("--part", required=True) + p.add_argument( + "--mcs", + type=Path, + help="Existing Vivado-packed image if the programming host lacks Artix build support", + ) + p.add_argument("--port", required=True) + p.add_argument("--out", type=Path) + args = p.parse_args() + bit = args.bitstream.resolve() + payload = args.payload.resolve() + out = args.out or ROOT / "build" / ( + "flash-program-" + datetime.now().strftime("%Y%m%d-%H%M%S") + ) + out = out.resolve() + out.mkdir(parents=True, exist_ok=False) + image = out / "toy_flash.mcs" + backup = out / "flash-before.bin" + commands = [ + [ + args.vivado, + "-mode", + "batch", + "-source", + str(ROOT / "board/make_flash_image.tcl"), + "-log", + str(out / "image.log"), + "-journal", + str(out / "image.jou"), + "-tclargs", + str(bit), + str(payload), + str(image), + ], + [ + args.vivado, + "-mode", + "batch", + "-source", + str(ROOT / "board/program_flash.tcl"), + "-log", + str(out / "program.log"), + "-journal", + str(out / "program.jou"), + "-tclargs", + str(image), + args.part, + str(backup), + ], + ] + if args.mcs: + packed_record = json.loads( + args.mcs.with_suffix(args.mcs.suffix + ".json").read_text() + ) + if packed_record["result"] != "PASS_VIVADO_FLASH_PACK": + raise ValueError("Prepacked flash image record did not pass packing") + if packed_record["bitstream_sha256"] != sha(bit): + raise ValueError("Prepacked flash image bitstream hash mismatch") + if packed_record["packed_payload_sha256"] != sha(payload): + raise ValueError("Prepacked flash image payload hash mismatch") + if packed_record["flash_image_sha256"] != sha(args.mcs): + raise ValueError("Prepacked flash image MCS hash mismatch") + shutil.copy2(args.mcs.resolve(), image) + commands[0] = None + record = dict( + status="RUNNING", + timeout_seconds=3600, + bitstream_sha256=sha(bit), + packed_payload_sha256=sha(payload), + part=args.part, + port=args.port, + started_at=datetime.now().astimezone().isoformat(), + commands=commands, + ) + result = out / "RESULT.json" + result.write_text(json.dumps(record, indent=2) + "\n") + started = time.monotonic() + watcher = None + try: + for i, command in enumerate(commands): + if command is None: + print("USING_PREPACKED_FLASH_IMAGE", sha(image), flush=True) + continue + if i == 1: + watcher = Observer(args.port, out / "linux-console.log", timeout=3600) + watcher.start() + with (out / f"command-{i}.log").open("w") as log: + proc = subprocess.Popen( + command, cwd=ROOT, stdout=log, stderr=subprocess.STDOUT + ) + try: + code = proc.wait( + timeout=max(1, 3600 - (time.monotonic() - started)) + ) + except subprocess.TimeoutExpired: + if __import__("os").name == "nt": + subprocess.run( + ["taskkill", "/PID", str(proc.pid), "/T", "/F"], + capture_output=True, + ) + else: + proc.kill() + proc.wait() + raise + if code: + raise RuntimeError( + f"Vivado command {i} failed with {code}; inspect {out}" + ) + print("PASS FLASH_STAGE", i, flush=True) + # Program completion may precede CPU decompression; cap the remaining wait. + watcher.thread.join(timeout=max(1, 3600 - (time.monotonic() - started))) + if watcher.thread.is_alive(): + raise TimeoutError("One-hour Flash/Linux timeout") + hardware = watcher.finish() + record.update( + status="PASS", + hardware=hardware, + backup_sha256=sha(backup), + backup_bytes=backup.stat().st_size, + flash_image_sha256=sha(image), + ) + except Exception as error: + record.update(status="FAILED", error=str(error)) + raise + finally: + if watcher is not None: + watcher.stop.set() + watcher.thread.join(timeout=6) + record.update( + elapsed_seconds=round(time.monotonic() - started, 3), + finished_at=datetime.now().astimezone().isoformat(), + ) + result.write_text(json.dumps(record, indent=2) + "\n") + print(json.dumps(record, indent=2), flush=True) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/scripts/check_board.py b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/scripts/check_board.py new file mode 100644 index 0000000..e6ceeaf --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/scripts/check_board.py @@ -0,0 +1,76 @@ +"""Test the exact board loader, AXI normalizer and OpenSBI SCU with stalls.""" +import hashlib +import json +from pathlib import Path +import subprocess + +ROOT=Path(__file__).resolve().parents[1] +OUT=ROOT/"build/board-unit" + + +def run(name, files, marker): + executable=OUT/name + command=["iverilog","-g2012","-s",name,"-o",str(executable)]+[str(f) for f in files] + compiled=subprocess.run(command,capture_output=True,text=True,timeout=60) + (OUT/(name+"-compile.log")).write_text(compiled.stdout+compiled.stderr) + compiled.check_returncode() + result=subprocess.run(["vvp",str(executable)],capture_output=True,text=True,timeout=60) + (OUT/(name+".log")).write_text(result.stdout+result.stderr) + print(result.stdout,end="") + result.check_returncode() + assert marker in result.stdout + + +def main(): + fixture=json.loads((ROOT/"tests/PLATFORM_PORTS_MANIFEST.json").read_text()) + if hashlib.sha256((ROOT/"tests/ToyLinuxChipPorts.sv").read_bytes()).hexdigest()!=fixture["stub_sha256"]: + raise ValueError("CPU port fixture differs from its manifest") + OUT.mkdir(parents=True,exist_ok=True) + run("tb_axi_fullwidth",[ROOT/"board/axi_fullwidth.sv",ROOT/"tests/axi_smoke_memory.sv",ROOT/"tests/tb_axi_fullwidth.sv"],"PASS fullwidth AXI") + run("tb_axi_scu",[ROOT/"board/axi_scu.sv",ROOT/"tests/tb_axi_scu.sv"],"PASS SCU") + platform_files=[ROOT/"board"/name for name in + ("toy_a7_platform.sv","axi_fullwidth.sv","axi_scu.sv","ddr_uart_loader.sv", + "loader_axi.sv","uart_rx.sv","uart_tx.sv","flash_spi_byte.sv")] + run("tb_platform_bresp",platform_files+[ROOT/"tests/ToyLinuxChipPorts.sv",ROOT/"tests/tb_platform_bresp.sv"], + "PASS platform AXI B response") + # Retain the CRC/range/timeout/rejected RUN oracle from the earlier loader, + # but connect its new acknowledgement boundary to AXI, not zero-latency RAM. + template=(ROOT/"tests/board_loader_template.sv").read_text() + template=template.replace("module tb_uart_loader", "module tb_ddr_loader") + template=template.replace("uart_loader #", "ddr_uart_loader #") + template=template.replace("32'h01374150", "32'h02374154") + template=template.replace("axi_bram #(.WORDS(256)) memory(", "/* legacy memory removed\naxi_bram #(.WORDS(256)) memory(") + template=template.replace(" always @(posedge clk) begin\n", "*/\n"+LOADER_MEMORY+"\n always @(posedge clk) begin\n",1) + template=template.replace("wire cpu_run,error_seen,load_en,load_valid;", "wire cpu_run,error_seen,load_en,load_valid,load_error;") + template=template.replace("PASS: UART loader", "PASS: DDR UART loader") + (OUT/"tb_ddr_loader.sv").write_text(template) + run("tb_ddr_loader",[ROOT/"board/ddr_uart_loader.sv",ROOT/"board/loader_axi.sv",ROOT/"tests/axi_smoke_memory.sv",OUT/"tb_ddr_loader.sv"],"PASS: DDR UART loader") + files=[p for p in (ROOT/"board").glob("*.sv")]+[ROOT/"tests/tb_axi_fullwidth.sv",ROOT/"tests/tb_axi_scu.sv"] + files += [ROOT/"tests/ToyLinuxChipPorts.sv",ROOT/"tests/tb_platform_bresp.sv"] + record=dict(result="PASS",tests=4,physical_mig_simulated=False, + sources={str(p.relative_to(ROOT)):hashlib.sha256(p.read_bytes()).hexdigest() for p in files}) + (OUT/"RESULT.json").write_text(json.dumps(record,indent=2)+"\n") + + +LOADER_MEMORY=""" + wire [27:0] awaddr,araddr; + wire awvalid,wvalid,arvalid,bready,rready,awready,wready,arready,bvalid,rvalid; + wire [127:0] wdata,rdata; + wire [15:0] wstrb; + wire [1:0] bresp,rresp; + loader_axi bridge(.clk(clk),.reset(reset),.load_en(load_en),.load_addr({16'd0,load_addr}), + .load_data(load_data),.load_mask(load_mask),.load_valid(load_valid),.load_error(load_error),.load_result(load_result), + .awaddr(awaddr),.araddr(araddr),.awvalid(awvalid),.wvalid(wvalid),.arvalid(arvalid), + .bready(bready),.rready(rready),.awready(awready),.wready(wready),.arready(arready), + .bvalid(bvalid),.rvalid(rvalid),.wdata(wdata),.wstrb(wstrb),.bresp(bresp),.rresp(rresp),.rdata(rdata)); + axi_smoke_memory #(.ADDR_BITS(28),.BASE(0),.CAPACITY(4096)) memory ( + .clock(clk),.reset(reset),.aw_bits_id(4'd0),.aw_bits_addr(awaddr),.aw_bits_len(8'd0),.aw_bits_size(3'd4),.aw_bits_burst(2'd1), + .aw_valid(awvalid),.aw_ready(awready),.w_bits_data(wdata),.w_bits_strb(wstrb),.w_bits_last(1'b1),.w_valid(wvalid),.w_ready(wready), + .b_ready(bready),.b_valid(bvalid),.b_bits_id(),.b_bits_resp(bresp), + .ar_bits_id(4'd0),.ar_bits_addr(araddr),.ar_bits_len(8'd0),.ar_bits_size(3'd4),.ar_bits_burst(2'd1),.ar_valid(arvalid),.ar_ready(arready), + .r_ready(rready),.r_valid(rvalid),.r_bits_id(),.r_bits_data(rdata),.r_bits_resp(rresp),.r_bits_last()); +""" + + +if __name__=="__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/scripts/check_flash_guards.py b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/scripts/check_flash_guards.py new file mode 100644 index 0000000..6fcd597 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/scripts/check_flash_guards.py @@ -0,0 +1,47 @@ +"""验证普通模式与 python -O 下四项预打包镜像校验均有效。""" + +import hashlib +import json +from pathlib import Path +import subprocess +import sys +import tempfile + +ROOT = Path(__file__).resolve().parents[1] + + +def main(): + out = ROOT / "build/flash-guard-check" + out.mkdir(parents=True, exist_ok=True) + cases = [] + for optimized in [False, True]: + for field in [None, "result", "bitstream_sha256", "packed_payload_sha256", "flash_image_sha256"]: + with tempfile.TemporaryDirectory(dir=out) as directory: + work = Path(directory) + bit, payload, mcs = [work / name for name in ["chip.bit", "payload.bin", "image.mcs"]] + for path in [bit, payload, mcs]: + path.write_bytes(path.name.encode()) + sha = lambda path: hashlib.sha256(path.read_bytes()).hexdigest() + record = {"result": "PASS_VIVADO_FLASH_PACK", "bitstream_sha256": sha(bit), + "packed_payload_sha256": sha(payload), "flash_image_sha256": sha(mcs)} + if field: + record[field] = "FAILED" if field == "result" else "0" * 64 + mcs.with_suffix(".mcs.json").write_text(json.dumps(record)) + expected = "reject" if field else "accept" + command = [sys.executable] + (["-O"] if optimized else []) + command += [str(ROOT / "tests/flash_guard_probe.py"), str(ROOT / "host/flash.py"), + str(bit), str(payload), str(mcs), str(work / "run"), expected] + result = subprocess.run(command, capture_output=True, text=True, timeout=20) + name = f"{'optimized' if optimized else 'normal'}-{field or 'valid'}" + (out / f"{name}.log").write_text(result.stdout + result.stderr, encoding="utf-8") + result.check_returncode() + if ("PASS INVALID_IMAGE_BLOCKED" if field else "PASS VALID_IMAGE_REACHED_OFFLINE_BOUNDARY") not in result.stdout: + raise ValueError("Missing guard oracle") + cases.append({"optimized": optimized, "field": field or "valid", "result": "PASS"}) + (out / "RESULT.json").write_text(json.dumps({"result": "PASS_FLASH_GUARDS_NORMAL_AND_OPTIMIZED", + "physical_hardware_tested": False, "cases": cases}, indent=2) + "\n") + print(f"PASS Flash image guards: {len(cases)} normal/-O tamper/control cases; no hardware") + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/scripts/check_programming_scripts.py b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/scripts/check_programming_scripts.py new file mode 100644 index 0000000..b64d6f2 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/scripts/check_programming_scripts.py @@ -0,0 +1,56 @@ +"""离线注入 Vivado API 返回值、异常与配置状态，检查实际 Tcl 入口。""" + +import argparse +import json +from pathlib import Path +import shutil +import subprocess +import tempfile + +ROOT = Path(__file__).resolve().parents[1] + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--tclsh", default=shutil.which("tclsh")) + args = parser.parse_args() + if not args.tclsh: + raise RuntimeError("Install Tcl or supply --tclsh") + out = ROOT / "build/programming-check" + out.mkdir(parents=True, exist_ok=True) + cases = [] + for script in ["program_arty.tcl", "backup_flash.tcl", "program_flash.tcl"]: + faults = ["none", "device_error", "done_low", "eos_low", "crc_error"] + if script != "program_arty.tcl": + faults += ["readback_error", "short_backup"] + if script == "program_flash.tcl": + faults += ["cfgmem_error"] + for fault in faults: + with tempfile.TemporaryDirectory(dir=out) as directory: + work = Path(directory) + bit = work / "input.bit" + bit.write_bytes(b"offline fixture") + command = [args.tclsh, str(ROOT / "tests/mock_programming.tcl"), + str(ROOT / "board" / script), fault, str(bit), str(work / "backup.bin")] + result = subprocess.run(command, capture_output=True, text=True, timeout=20) + transcript = result.stdout + result.stderr + (out / f"{script}-{fault}.log").write_text(transcript, encoding="utf-8") + if fault == "none": + if result.returncode or "MOCK_SUCCESS" not in transcript: + raise ValueError(f"Documented success return rejected: {script}: {transcript}") + else: + if result.returncode == 0 or "MOCK_FAILURE" not in transcript: + raise ValueError(f"Injected failure accepted: {script}/{fault}") + if "PASS FLASH_PROGRAM_VERIFY" in transcript or "ARTY_JTAG_PROGRAMMED:" in transcript: + raise ValueError("False success marker") + if fault != "cfgmem_error" and "program_flash" in transcript.split("MOCK_EVENTS", 1)[1].splitlines()[0]: + raise ValueError("Flash programming reached after an earlier failure") + cases.append({"script": script, "fault": fault, "result": "PASS"}) + record = {"result": "PASS_OFFLINE_TCL_CONTRACTS", "physical_hardware_tested": False, + "cases": cases} + (out / "RESULT.json").write_text(json.dumps(record, indent=2) + "\n") + print(f"PASS programming scripts: {len(cases)} documented-return/status/error cases; no hardware") + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/tests/PLATFORM_PORTS_MANIFEST.json b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/tests/PLATFORM_PORTS_MANIFEST.json new file mode 100644 index 0000000..3c892d5 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/tests/PLATFORM_PORTS_MANIFEST.json @@ -0,0 +1,7 @@ +{ + "source_core_sha256": "31e7e07f94d08208dbb564edf9546240df26ff834935bfb646b71b541d875fb9", + "port_header_sha256": "3329804932f5a7632f78bbe56797f9bff35fb6f94910f0a474c59a9a0a90bf5d", + "stub_sha256": "e4c06220cd7025972d432b06c452e85c62bd2cfccad618b2b993499b62e6621a", + "cpu_behavior_included": false, + "port_header_hash_encoding": "UTF-8 with LF newlines" +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/tests/ToyLinuxChipPorts.sv b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/tests/ToyLinuxChipPorts.sv new file mode 100644 index 0000000..6e07c67 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/tests/ToyLinuxChipPorts.sv @@ -0,0 +1,134 @@ +// Port-only fixture from the Chisel-generated core; no CPU behavior. +// Outputs idle at zero. The testbench drives the real platform AXI port. +module ToyLinuxChip( + input clock, + reset, + interrupt, + memory_aw_ready, + output memory_aw_valid, + output [3:0] memory_aw_bits_id, + output [31:0] memory_aw_bits_addr, + output [7:0] memory_aw_bits_len, + output [2:0] memory_aw_bits_size, + output [1:0] memory_aw_bits_burst, + output memory_aw_bits_lock, + output [3:0] memory_aw_bits_cache, + output [2:0] memory_aw_bits_prot, + output [3:0] memory_aw_bits_qos, + input memory_w_ready, + output memory_w_valid, + output [127:0] memory_w_bits_data, + output [15:0] memory_w_bits_strb, + output memory_w_bits_last, + memory_b_ready, + input memory_b_valid, + input [3:0] memory_b_bits_id, + input [1:0] memory_b_bits_resp, + input memory_ar_ready, + output memory_ar_valid, + output [3:0] memory_ar_bits_id, + output [31:0] memory_ar_bits_addr, + output [7:0] memory_ar_bits_len, + output [2:0] memory_ar_bits_size, + output [1:0] memory_ar_bits_burst, + output memory_ar_bits_lock, + output [3:0] memory_ar_bits_cache, + output [2:0] memory_ar_bits_prot, + output [3:0] memory_ar_bits_qos, + output memory_r_ready, + input memory_r_valid, + input [3:0] memory_r_bits_id, + input [127:0] memory_r_bits_data, + input [1:0] memory_r_bits_resp, + input memory_r_bits_last, + peripherals_aw_ready, + output peripherals_aw_valid, + output [1:0] peripherals_aw_bits_id, + output [30:0] peripherals_aw_bits_addr, + output [7:0] peripherals_aw_bits_len, + output [2:0] peripherals_aw_bits_size, + output [1:0] peripherals_aw_bits_burst, + output peripherals_aw_bits_lock, + output [3:0] peripherals_aw_bits_cache, + output [2:0] peripherals_aw_bits_prot, + output [3:0] peripherals_aw_bits_qos, + input peripherals_w_ready, + output peripherals_w_valid, + output [63:0] peripherals_w_bits_data, + output [7:0] peripherals_w_bits_strb, + output peripherals_w_bits_last, + peripherals_b_ready, + input peripherals_b_valid, + input [1:0] peripherals_b_bits_id, + peripherals_b_bits_resp, + input peripherals_ar_ready, + output peripherals_ar_valid, + output [1:0] peripherals_ar_bits_id, + output [30:0] peripherals_ar_bits_addr, + output [7:0] peripherals_ar_bits_len, + output [2:0] peripherals_ar_bits_size, + output [1:0] peripherals_ar_bits_burst, + output peripherals_ar_bits_lock, + output [3:0] peripherals_ar_bits_cache, + output [2:0] peripherals_ar_bits_prot, + output [3:0] peripherals_ar_bits_qos, + output peripherals_r_ready, + input peripherals_r_valid, + input [1:0] peripherals_r_bits_id, + input [63:0] peripherals_r_bits_data, + input [1:0] peripherals_r_bits_resp, + input peripherals_r_bits_last +); + assign memory_aw_valid = '0; + assign memory_aw_bits_id = '0; + assign memory_aw_bits_addr = '0; + assign memory_aw_bits_len = '0; + assign memory_aw_bits_size = '0; + assign memory_aw_bits_burst = '0; + assign memory_aw_bits_lock = '0; + assign memory_aw_bits_cache = '0; + assign memory_aw_bits_prot = '0; + assign memory_aw_bits_qos = '0; + assign memory_w_valid = '0; + assign memory_w_bits_data = '0; + assign memory_w_bits_strb = '0; + assign memory_w_bits_last = '0; + assign memory_b_ready = '0; + assign memory_ar_valid = '0; + assign memory_ar_bits_id = '0; + assign memory_ar_bits_addr = '0; + assign memory_ar_bits_len = '0; + assign memory_ar_bits_size = '0; + assign memory_ar_bits_burst = '0; + assign memory_ar_bits_lock = '0; + assign memory_ar_bits_cache = '0; + assign memory_ar_bits_prot = '0; + assign memory_ar_bits_qos = '0; + assign memory_r_ready = '0; + assign peripherals_aw_valid = '0; + assign peripherals_aw_bits_id = '0; + assign peripherals_aw_bits_addr = '0; + assign peripherals_aw_bits_len = '0; + assign peripherals_aw_bits_size = '0; + assign peripherals_aw_bits_burst = '0; + assign peripherals_aw_bits_lock = '0; + assign peripherals_aw_bits_cache = '0; + assign peripherals_aw_bits_prot = '0; + assign peripherals_aw_bits_qos = '0; + assign peripherals_w_valid = '0; + assign peripherals_w_bits_data = '0; + assign peripherals_w_bits_strb = '0; + assign peripherals_w_bits_last = '0; + assign peripherals_b_ready = '0; + assign peripherals_ar_valid = '0; + assign peripherals_ar_bits_id = '0; + assign peripherals_ar_bits_addr = '0; + assign peripherals_ar_bits_len = '0; + assign peripherals_ar_bits_size = '0; + assign peripherals_ar_bits_burst = '0; + assign peripherals_ar_bits_lock = '0; + assign peripherals_ar_bits_cache = '0; + assign peripherals_ar_bits_prot = '0; + assign peripherals_ar_bits_qos = '0; + assign peripherals_r_ready = '0; +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/tests/axi_smoke_memory.sv b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/tests/axi_smoke_memory.sv new file mode 100644 index 0000000..f8e7dc6 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/tests/axi_smoke_memory.sv @@ -0,0 +1,115 @@ +// Single outstanding read and write, with independent AXI channels. +// Backpressure is legal: W is accepted after AW; R/B are held until accepted. +module axi_smoke_memory #( + parameter DATA_BITS=128, ID_BITS=4, ADDR_BITS=32, + parameter BASE=32'h80000000, CAPACITY=262144, + parameter IMAGE="", parameter MONITOR=0, + parameter TEST_LABEL="whole Toy CPU smoke" +) ( + input clock, reset, + output aw_ready, input aw_valid, + input [ID_BITS-1:0] aw_bits_id, + input [ADDR_BITS-1:0] aw_bits_addr, + input [7:0] aw_bits_len, input [2:0] aw_bits_size, + input [1:0] aw_bits_burst, + output w_ready, input w_valid, + input [DATA_BITS-1:0] w_bits_data, + input [DATA_BITS/8-1:0] w_bits_strb, input w_bits_last, + input b_ready, output reg b_valid, + output reg [ID_BITS-1:0] b_bits_id, output [1:0] b_bits_resp, + output ar_ready, input ar_valid, + input [ID_BITS-1:0] ar_bits_id, + input [ADDR_BITS-1:0] ar_bits_addr, + input [7:0] ar_bits_len, input [2:0] ar_bits_size, + input [1:0] ar_bits_burst, + input r_ready, output reg r_valid, + output reg [ID_BITS-1:0] r_bits_id, + output reg [DATA_BITS-1:0] r_bits_data, + output [1:0] r_bits_resp, output reg r_bits_last +); + localparam LANES=DATA_BITS/8; + reg [7:0] mem [0:CAPACITY-1]; + reg write_active; + reg [ADDR_BITS-1:0] write_addr, read_addr; + reg [7:0] write_remaining, read_remaining; + reg [2:0] write_size, read_size; + reg [3:0] stall_cycle; + integer read_bursts, write_bursts; + assign aw_ready = !write_active && !b_valid && stall_cycle[1:0]!=0; + assign w_ready = write_active && !b_valid && stall_cycle[2:0]!=0; + assign ar_ready = !r_valid && stall_cycle[1:0]!=1; + assign b_bits_resp = 0; + assign r_bits_resp = 0; + + initial begin + for (integer i=0; iCAPACITY) + $fatal(1,"AXI read out of range: %h",addr); + for (integer lane=0; laneCAPACITY) + $fatal(1,"AXI write out of range: %h",write_addr); + if (w_bits_last != (write_remaining==0)) $fatal(1,"WLAST mismatch"); + for (integer lane=0; lane=0;n=n-1) c=(c<<1)^((c[15]^value[n]) ? 16'h1021 : 16'd0); + crc_step=c; + end + endfunction + task automatic byte_send(input [7:0] value); + begin @(negedge clk);rx_data=value;rx_valid=1;@(negedge clk);rx_valid=0;end + endtask + task automatic request(input [7:0] op,input [31:0] address,input [15:0] length,input bit corrupt); + reg [15:0] crc; + reg [7:0] value; + begin + received=0;crc=16'hffff; + byte_send(8'ha5);byte_send(8'h5a); + byte_send(op);crc=crc_step(crc,op); + byte_send(8'h37);crc=crc_step(crc,8'h37); + for(integer n=0;n<4;n=n+1) begin + value=address>>(n*8);byte_send(value);crc=crc_step(crc,value); + end + byte_send(length[7:0]);crc=crc_step(crc,length[7:0]); + byte_send(length[15:8]);crc=crc_step(crc,length[15:8]); + if(op==1) for(integer n=0;n>(addr[2:0]*8) & 255)!==expected) + $fatal(1,"SCU read addr=%h data=%h resp=%h",addr,rdata,rresp); + @(negedge clk); + end + rready=1;@(negedge clk);rready=0; + end + endtask + initial begin + repeat(4) @(negedge clk);reset=0; + @(negedge clk);rx_data=8'h71;rx_valid=1;@(negedge clk);rx_valid=0; + read_byte(31'h60020005,1,0); + if(!interrupt) $fatal(1,"RX IRQ missing"); + read_byte(31'h60020004,8'h71,0); + if(interrupt) $fatal(1,"RX not popped exactly once"); + read_byte(31'h60020005,0,0); + // A whole pasted command must survive a long interval between SBI polls. + for(integer j=0;j<200;j=j+1) begin + @(negedge clk);rx_data=j;rx_valid=1;@(negedge clk);rx_valid=0; + end + if(dut.overflow) $fatal(1,"FIFO overflow on a 200-byte paste"); + for(integer j=0;j<200;j=j+1) read_byte(31'h60020004,j[7:0],0); + if(interrupt) $fatal(1,"FIFO not drained after paste"); + read_byte(31'h60030000,0,2); + @(negedge clk);awaddr=31'h60020000;awid=3;awvalid=1; + @(negedge clk);awvalid=0;wdata=64'h53;wstrb=1;wvalid=1; + repeat(10) begin @(negedge clk);if(wready || bvalid) $fatal(1,"SCU lost TX backpressure");end + tx_ready=1;@(negedge clk);wvalid=0; + repeat(4) @(negedge clk); + if(!bvalid || bid!==3 || bresp!==0 || tx_count!=1) $fatal(1,"SCU TX response/count"); + bready=1;@(negedge clk);bready=0; + awaddr=31'h60000000;awsize=2;awvalid=1;@(negedge clk);awvalid=0; + wdata=64'h12345678;wstrb=15;wvalid=1;@(negedge clk);wvalid=0; + if(!exited || exit_code!==32'h12345678) $fatal(1,"SCU EXIT decode"); + $display("PASS SCU OpenSBI byte addresses, AXI lanes, RX pop/IRQ, TX backpressure, EXIT");$finish; + end + initial begin #100000;$fatal(1,"SCU watchdog");end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/tests/tb_platform_bresp.sv b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/tests/tb_platform_bresp.sv new file mode 100644 index 0000000..d45f79d --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/pr10-review/sources/tests/tb_platform_bresp.sv @@ -0,0 +1,55 @@ +`timescale 1ns/1ps +module tb_platform_bresp; + reg clk=0; + always #5 clk=~clk; + reg reset=1; + reg [30:0] address=0; + reg [2:0] size=2; + reg [7:0] length=0; + reg awvalid=0,wvalid=0,last=1,bready=0; + toy_a7_platform dut(.clk(clk),.reset(reset),.uart_rx_in(1'b1), + .ddr_awready(1'b1),.ddr_wready(1'b1),.ddr_bid(4'd0),.ddr_bresp(2'd0),.ddr_bvalid(1'b0), + .ddr_arready(1'b1),.ddr_rid(4'd0),.ddr_rdata(128'd0),.ddr_rresp(2'd0),.ddr_rlast(1'b1),.ddr_rvalid(1'b0), + .flash_miso(1'b0),.flash_recovery(1'b0)); + task automatic write_case(input [30:0] addr,input [2:0] width,input [7:0] len,input [1:0] expected); + @(negedge clk);address=addr;size=width;length=len;awvalid=1; + do @(posedge clk);while(!dut.peripherals_aw_ready); + @(negedge clk);awvalid=0; + for(integer beat=0;beat<=len;beat=beat+1) begin + wvalid=1;last=beat==len; + do @(posedge clk);while(!dut.peripherals_w_ready); + @(negedge clk);wvalid=0; + end + while(!dut.peripherals_b_valid) @(negedge clk); + repeat(5) begin + // Observe the CPU input, through actual platform wiring and real SCU. + if(dut.chip.peripherals_b_bits_resp!==expected || dut.chip.peripherals_b_bits_id!==2) + $fatal(1,"Platform B response addr=%h actual=%b expected=%b",addr,dut.chip.peripherals_b_bits_resp,expected); + @(negedge clk); + end + bready=1;@(negedge clk);bready=0; + endtask + initial begin + force dut.cpu_run=1; + force dut.peripherals_aw_valid=awvalid; + force dut.peripherals_aw_bits_addr=address; + force dut.peripherals_aw_bits_size=size; + force dut.peripherals_aw_bits_len=length; + force dut.peripherals_aw_bits_id=2; + force dut.peripherals_aw_bits_burst=1; + force dut.peripherals_w_valid=wvalid; + force dut.peripherals_w_bits_last=last; + force dut.peripherals_w_bits_data=64'h13572468; + force dut.peripherals_w_bits_strb=8'h0f; + force dut.peripherals_b_ready=bready; + repeat(5) @(negedge clk);reset=0; + write_case(31'h60000000,2,0,0); + if(!dut.exited || dut.exit_code!==32'h13572468) $fatal(1,"Valid MMIO changed"); + write_case(31'h60030000,2,0,2); + write_case(31'h60000002,2,0,2); + write_case(31'h60000000,2,1,2); + $display("PASS platform AXI B response: valid, invalid address, unaligned, burst, ID and backpressure"); + $finish; + end + initial begin #100000;$fatal(1,"Platform response watchdog");end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/INPUT_MANIFEST.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/INPUT_MANIFEST.json new file mode 100644 index 0000000..f0d60a8 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/INPUT_MANIFEST.json @@ -0,0 +1,395 @@ +{ + "source_files": { + ".gitattributes": "8d9ebca04236fcd49c43562b5c6ca1d88ded1ff8c8d437fbdfe3822a5ec22d74", + ".gitignore": "5eaf4f0d4cbefc5292732eb17cd984839a8fe4cfc65f39352c187fd73c95947a", + ".jvmopts": "a66471d84e6e2ed0c3c40d5ebbc237d268ed9b04f3528ef22e967a2bd4e8aa44", + "FLASH_BOOT.md": "471bcd9c9704bd2eedf11880c27c48d0505a56498e62e68ada84d5cd5ed70686", + "README.md": "d1a1326934b5f211f617b0528ca6d85fde5771d8ca32f0c85add7ffcb8310264", + "SOFTWARE_BASELINE.json": "3a5c9f65771e6fd7f8172674baf22263ba7c2d9244993c9162ba526344a7b0aa", + "SOURCE_LOCK.json": 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"ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.accelerators_0.memDomain.backend.privateBackend.banks_1.mem.mem_ext", + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.accelerators_0.memDomain.backend.privateBackend.banks_0.mem.mem_ext" + ], + "ram_style": "block" + } + ], + "baseline_core_rtl_sha256": "03155e51ef07fec698c4c75f459478d065ed41fb324f00109d18a7426f330c05", + "additional_memory_adapters": [ + { + "module": "regfile_32x65", + "implementation": "two single-write LUTRAM banks and LVT", + "read_ports": 3, + "write_ports": 2, + "read_latency": 0, + "same_address_write_priority": "W1", + "added_cycles": 0, + "adapter_sha256": "bbc9ad168c94204a946b3e107115fae7f6042fd6c7f95807d7af367449e28950" + } + ] +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/OPTIN_RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/OPTIN_RESULT.json new file mode 100644 index 0000000..7a58cff --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/OPTIN_RESULT.json @@ -0,0 +1,14 @@ +{ + "rob-default-raw": { + "emitted_sha256": "05d53ac2a64ae89cfdb2861b3652b0e5b9a5bea401757c29a35f9a0654a3a2eb", + "core_rtl_sha256": "4c6aacf64660bbbf14b1114e8d5e4439d6a4e1427aaf1f681c6a4f618f2d2779", + "memory_rtl_sha256": "8307d252185ba71a4516d1932d235a5a188816f84a5ed237bb5f3c1281d4b580" + }, + "rob-optin-raw": { + "emitted_sha256": "9cf090b2ecdf1f59115c5f639151ef9c0037cf2531a619d3dab349f937ec5097", + "core_rtl_sha256": "31e7e07f94d08208dbb564edf9546240df26ff834935bfb646b71b541d875fb9", + "memory_rtl_sha256": "d5a37896aee19c8d4931c87dc9683861abf32f096a1c1441f4362370d3d7b054" + }, + "result": "PASS_DEFAULT_AND_CANDIDATE_BYTE_IDENTITY", + "source_switch": "sbt -Dfpga.robOperandRam=true" +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/REPORT.md b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/REPORT.md new file mode 100644 index 0000000..1d7531c --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/REPORT.md @@ -0,0 +1,73 @@ +# ROB 操作数 RAM 优化报告 + +本轮通过了 RTL 回归、Linux 启动与完整 FPGA 布线，尚未烧录实板。 +不减少架构功能或容量，不替换已有 UART/Flash 发布包。 + +## 改动与范围 + +从固定上游 `GlobalROB.scala` 增加可选路径：两份 64 位操作数在 allocation +写入 16×128、1R1W 同步 RAM，利用原 issue pointer 级隐藏读延迟。 +控制、依赖、提交顺序与 trace 保留；原指针、背压和有效位控制 RAM 使用。 +显式 BRAM 绑定消除了大量操作数 FF，代价是两块 RAMB36。 + +保留当前 FPGA profile 的 CPU、Sv39、FP16/32/64、Gemmini 8×8、23 项 Ball +指令、16-entry ROB、bank/缓存容量及板级接口。它不会恢复此前已裁剪的独立 Ball。 +这项内部存储优化不改变软件 ABI，也不代表整模型编译链已适配。 + +## 同条件面积与时序 + +器件 `xc7a100tcsg324-1`，Vivado 2024.1，UART 目标、25 MHz CPU； +沿用原 `board/build_board.tcl`、XDC 和综合/布局策略。基线为 +`evidence/2026-10-11/BOARD_RESULT.json`，没有用 Flash 目标作比较。 + +| 布线后测量 | 原寄存器 | 同步 RAM | 变化 | +|---|---:|---:|---:| +| 物理 LUT（已计入 LUT combining） | 54,413 | 53,929 | −484 | +| FF | 35,600 | 33,943 | −1,657 | +| 占用 Slice / 15,850 | 15,663 | 15,579 | −84 | +| 空闲 Slice | 187 | 271 | +84 | +| BRAM tile / 135 | 29 | 31 | +2 | +| DSP / 240 | 117 | 117 | 0 | +| WNS / WHS（ns） | +1.276 / +0.013 | +1.276 / +0.012 | 均通过 | + +候选 TNS、THS 为 0，全部可布线网络完成、布线错误为 0，位流已生成。 +运行 1,396 秒，在 3,600 秒期限内完成。DRC 无 Error/Critical，仍有 360 项 +普通警告（主要为 DSP 输入/输出流水建议）；CDC 保留 3 项时钟转换 IP 的 +CDC-15 Warning，无 Critical。未降低 DRC 严重级别。 + +全部 64 个 PE 仍各使用一个 DSP。综合阶段减少 429 LUT、1,655 FF；最终以 +布线后资源为准。Slice 占用仍为 98.29%，这点余量不能证明能加入另一套算子硬件。 + +RAM 子层级被 Vivado 归入部分 `bankCols_*` 配置控制，不能把该层级下的约 +1,721 LUT 全部解释成 RAM 本体开销。并行提交/配置更新网络仍是后续候选，未在 +本轮修改；未测量的优化不计入上述收益。 + +## 功能与性能核验 + +- ROB RAM 与原寄存器路径逐周期对照通过，8,029 周期，三个随机种子与两次 + 中途复位；接受时保存完整命令作独立对照。断言覆盖满队列、背压及排空。 +- 七类 memory 通过原 RTL/独立 scoreboard 对照，包括新增 RAM；AXI、SCU、 + UART/CRC loader 接口检查通过。 +- 不改测试二进制，CPU/Sv39/FPU/AMO/cache/IRQ、原 13 项 Gemmini、OS/WS + 分块循环、非对齐/跨页 DMA 分别为 709,434、251,063、684,219、1,914,839 + 周期，与原基线完全相同。这是已测用例结论，不是所有负载性能的证明。 +- 同一标准 payload 启动 OpenSBI/Linux，通过写时复制、页面保护、浮点进程 + 上下文、定时器与总检查；273,506,752 周期与基线相同。页面保护用例故意 + 触发子进程 SIGSEGV，之后 `PASS VM_PAGE_PROTECTION` 为预期成功行为。 +- Linux 检查使用 AXI 存储模型，串口 RX 输入真实波形；未模拟物理 DDR PHY。 + +## 复现与文件 + +从平台目录按 [ROB_RAM.md](../../../ROB_RAM.md) 执行。默认构建保持旧路径， +候选需显式 `sbt -Dfpga.robOperandRam=true`。后续两种配置均重新生成，默认 +核心/存储器与旧发布摘要一致，候选与本次已测字节一致，见 `OPTIN_RESULT.json`。 + +`sources/` 保存本次实际执行的覆盖层、测试入口和板级 Tcl/XDC；其中构造默认 +为 true 是首次实验快照，当前集成改为显式开启，生成字节一致性已单独核验。 +`INPUT_MANIFEST.json` 记录隔离目录初始输入，`MANIFEST.json` 核验本档案。 +`tests/` 保存通过的回归原文，`implementation/` 保存完整资源、时序、DRC/CDC +和 Vivado 日志。无关网络/启动命令错误不作为芯片测试失败写入档案。 + +生成核心、存储器、位流摘要记录在 `RESULT.json`。大体积 RTL、DCP、位流保留 +在构建目录，未当作已验收发布件提交。当前只有 UART 候选；Flash 版本和实板 +验收仍需独立执行。原发布资格与本轮记录分开保留。 diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/RESULT.json new file mode 100644 index 0000000..be1eac0 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/RESULT.json @@ -0,0 +1,51 @@ +{ + "result": "PASS_ROB_RAM_RTL_AND_BOARD_IMPLEMENTATION", + "part": "xc7a100tcsg324-1", + "mode": "UART", + "core_clock_hz": 25000000, + "baseline_record": "evidence/2026-10-11/BOARD_RESULT.json", + "core_rtl_sha256": "31e7e07f94d08208dbb564edf9546240df26ff834935bfb646b71b541d875fb9", + "memory_rtl_sha256": "d5a37896aee19c8d4931c87dc9683861abf32f096a1c1441f4362370d3d7b054", + "bitstream_sha256": "dec8dcaea14b56db49ef8166d1605034695658f55f02dce73d4455fbc078ee5c", + "routed_resources": { + "LUT": 53929, + "FF": 33943, + "Slice": 15579, + "BRAM_tiles": 31, + "DSP": 117 + }, + "resource_delta": { + "LUT": -484, + "FF": -1657, + "Slice": -84, + "BRAM_tiles": 2, + "DSP": 0 + }, + "free_slices": 271, + "gemmini_mesh_dsp": 64, + "timing": { + "wns_ns": 1.276, + "whs_ns": 0.012, + "tns_ns": 0, + "ths_ns": 0, + "wpws_ns": 0.187 + }, + "route_errors": 0, + "architectural_profile_unchanged": true, + "regression_cycles_unchanged": true, + "linux_rtl_cycles": 273506752, + "physical_board_tested": false, + "flash_boot_tested": false, + "replaces_published_artifacts": false, + "integration_sources": { + "build.sbt": "c4581ef9345fb3d3bd326c95b6f46a0ae8538ed6c0cc22ac675bd0c9a10fd407", + "patches/framework/GlobalROB.scala": "7998e486ffa0f6e4f1cdb3ee991ed5a7c8d389268da94e4fbbc9a9bd56573c7d", + "scripts/check_globalrob.py": "d9476b99ea8f68ea1b22fe62648433314c711fb40162349824f9fe89182517b4", + "scripts/prepare_fpga_memories.py": "9d40763492ebbf2bc5aa183e760ec349e31765a0e999af88f476d5e945ab74c4", + "scripts/prepare_rob_candidate.py": "321b4569d2638342a7c0002ba1db3eb72229c369397289a11ed49633b1f27823", + "scripts/start_rob_board_build.py": "0c99afafe707a51fba935a59076288a50b7179e01d330f8a1294c81ee1956cf9", + "scripts/elaborate_rob_candidate.sh": "ce65656a3ae6c9fd49d651b9cef434cf8cf3bcfb393180d210f233741c6ffa0f", + "src/main/scala/EmitGlobalRobCheck.scala": "5d366fce3e96278f60c648dc114896246b5c595c8ef783986524e6583c490a05", + "tests/tb_globalrob.sv": "8ded6fc969a05ead874fd8771b86dadafe51f7ccec54fafd55a9d48a4e7361a6" + } +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/ROB_RAM_PREPARED.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/ROB_RAM_PREPARED.json new file mode 100644 index 0000000..a49e085 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/ROB_RAM_PREPARED.json @@ -0,0 +1,21 @@ +{ + "result": "PREPARED_NOT_VALIDATED", + "architectural_profile_unchanged": true, + "existing_memory_geometry_unchanged": true, + "rob_operand_memory": { + "module_name": "robOperands_ext", + "depth": 16, + "width": 128, + "masked": false, + "read": 1, + "write": 1, + "readwrite": 0, + "extra_ports": [], + "hierarchy": [ + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.accelerators_0.frontend.scheduler.rob.robOperands.robOperands_ext" + ] + }, + "rob_operand_ram_style": "block", + "core_rtl_sha256": "31e7e07f94d08208dbb564edf9546240df26ff834935bfb646b71b541d875fb9", + "memory_rtl_sha256": "d5a37896aee19c8d4931c87dc9683861abf32f096a1c1441f4362370d3d7b054" +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/ToyLinuxChip.profile.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/ToyLinuxChip.profile.json new file mode 100644 index 0000000..8207768 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/ToyLinuxChip.profile.json @@ -0,0 +1,73 @@ +{ + "serial_fpga": true, + "gemmini_only_balls": true, + "ball_count": 1, + "ball_names": [ + "GemminiBall" + ], + "ball_ids": [ + 0 + ], + "ball_funct7": [ + 2, + 3, + 53, + 66, + 67, + 80, + 81, + 82, + 83, + 84, + 85, + 86, + 87, + 96, + 97, + 98, + 99, + 100, + 101, + 102, + 103, + 104, + 105 + ], + "ball_read_ports": 2, + "ball_write_ports": 4, + "accelerator_mmio_scale_pool": false, + "compact_caches": true, + "btb_enabled": false, + "icache_bytes": 8192, + "icache_ways": 2, + "dcache_bytes": 8192, + "dcache_mshrs": 1, + "l2_ways": 0, + "coherence_manager": "broadcast", + "rob_entries": 16, + "sub_rob_depth": 8, + "dma_n_xacts": 2, + "dma_max_in_flight": 4, + "tma_read_channels": 1, + "tma_write_channels": 1, + "cpu_mul_unroll": 8, + "gemmini_rows": 8, + "gemmini_columns": 8, + "virtual_bank_count": 16, + "trimmed_optional_peripherals": true, + "scratchpad_bytes": 0, + "cpu_use_debug": false, + "cpu_breakpoints": 0, + "extra_hpm_counters": 0, + "basic_counters": true, + "use_vm": true, + "fpu_shared_fma": true, + "fpu_sfma_latency": 6, + "fpu_dfma_latency": 6, + "fpu_min_flen": 16, + "fpu_flen": 64, + "bank_count": 8, + "bank_rows": 1024, + "bank_width": 64, + "bank_channels": 7 +} \ No newline at end of file diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/RUN.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/RUN.json new file mode 100644 index 0000000..aafc26b --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/RUN.json @@ -0,0 +1,71 @@ +{ + "status": "COMPLETED", + "optimization": "ROB_OPERAND_BRAM", + "timeout_seconds": 3600, + "termination_grace_seconds": 15, + "part": "xc7a100tcsg324-1", + "core_sha256": "31e7e07f94d08208dbb564edf9546240df26ff834935bfb646b71b541d875fb9", + "memory_sha256": "d5a37896aee19c8d4931c87dc9683861abf32f096a1c1441f4362370d3d7b054", + "board_sources": { + "board/make_flash_image.tcl": "69a70d18a519f8fa156981e9ab024dce5c7bc91733c5b6cf3b9045658415334b", + "board/SOURCE_MANIFEST.json": "03d99f1f43bbf68d92df61db52bdee0019723e2e194ee5f9c12a5ac6d4c5a105", + "board/loader_axi.sv": "05609b0870054ea675aedb406f6215cd456f18db6d6428b461cbae03d9a662f4", + "board/flash_spi_byte.sv": "4d1fac5238f31fb3a69a58d1aca9ccec722e833d788113b94d86c6a1b861045a", + "board/README.md": "5a7f01460107df0c5c40d2a2b18c68648ca2d7b20c914c788b880ec1b9f6f95b", + "board/uart_rx.sv": "0b35263884577324f146ff7fd516e5b561dcc8787e0d8ad599669bac1958406d", + "board/program_arty.tcl": "fbb62bafb6df602b0f5f638fb05ae4ecc90494ac162b9a5f5ac314200f7a241c", + "board/arty_a7.xdc": "f13869ba386038557084adabafeb5255943d0b67f1db4b88fd907e4f095d016f", + "board/toy_a7_top.sv": "c8af97f543b8ae5d6dc21a85ba13b16a28fe3ba5bf93f8051c9e38c99f3350bd", + "board/backup_flash.tcl": "63d84e9055f00bd7ed97485912b0c8db83bee19b6950ba4c12fc3f9a639c3ea3", + "board/ddr_uart_loader.sv": "980f4cd2e3fa2a00b66143f879bc749ed952c2c1e54331460821bac0300c43d6", + "board/program_flash.tcl": "a2cfa55d7f61f5cecd74e68e2bbede9c535399291eea274e76fe416bdc8d3626", + "board/axi_scu.sv": "ee77bf641d61811b4c1faea845752850c22461a63b4cdfd3d6f9cd223e6c2fc2", + "board/build_board.tcl": "04f25ca8f6da06b37aec7156ec47def13da0bac88294466b08fb838bc462ba8d", + "board/toy_a7_platform.sv": "01fe1f8e2621a1a023ac3b8d91758868b190760f6e706ae1d34a67857b96d846", + "board/axi_fullwidth.sv": "bf07ae27724dbd0a361d732dfb57109f06beef207c47a066d400cb06d7f07d5a", + "board/flash_boot.xdc": "bbf9e250ae28dcc4f54d00effd918811f723a7563b4ceacb7b1d03a29151f4ea", + "board/uart_tx.sv": "c20d420fc20be4f6313bdde5abc45ef0b9f8e93bf75350dd9951bc8868b3b65c", + "board/vendor/License.txt": "28a42137bb9c77a6aa931c5ca670134620f448051dbd708a05921280a7b277ba", + "board/vendor/mig.prj": "914a9e4bb1b3002837592944cdf49f8dfbaf4d112552dd8b5be48602ff1ac329", + "board/vendor/preset.xml": "ff95b9b976323fefa588873588dfa2bdce1673759c0a9e91c12ee9f2a2955bce", + "board/vendor/part0_pins.xml": "50aa844aa9c78af6342de68ae3c980f7618716447b28282878d5a106f86fed31", + "board/vendor/board.xml": "5bd9a7ca97ccb2fef617515a14401166464b45a06684d663c0be1a06b02a86df", + "board/vendor/MANIFEST.json": "3fbfac2499bc99a23356873a5d81e0f87d32f02ec1b7929ead51a15f33d9af85" + }, + "execution_script": "/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/build_board.tcl", + "execution_script_sha256": "04f25ca8f6da06b37aec7156ec47def13da0bac88294466b08fb838bc462ba8d", + "core_clock_hz": 25000000, + "uart_baud": 1000000, + "architectural_profile_unchanged": true, + "flash_boot": false, + "physical_boot_tested": false, + "inherits_baseline_hardware_qualification": false, + "started_at": "2026-10-12T20:13:52.282668+08:00", + "deadline": "2026-10-12T21:13:52.282668+08:00", + "command": [ + "timeout", + "--signal=TERM", + "--kill-after=15s", + "3600s", + "/home/yys/bin/vivado", + "-mode", + "batch", + "-source", + "/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/build_board.tcl", + "-log", + "/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/vivado.log", + "-journal", + "/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/vivado.jou", + "-tclargs", + "/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352" + ], + "worker_pid": 19876, + "timeout_process_pid": 19881, + "exit_code": 0, + "elapsed_seconds": 1396.3394632509999, + "finished_at": "2026-10-12T20:37:08.622201+08:00", + "core_unchanged": false, + "bitstream_generated": true, + "candidate_core_unchanged": true, + "candidate_memory_unchanged": true +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/bus-skew.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/bus-skew.rpt new file mode 100644 index 0000000..cfa9204 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/bus-skew.rpt @@ -0,0 +1,1380 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Mon Oct 12 20:36:27 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_bus_skew -return_string +| Design : toy_a7_top +| Device : 7a100t-csg324 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +| Design State : Routed +--------------------------------------------------------------------------------------------------------------------------------------------- + +Bus Skew Report + +Table of Contents +----------------- +1. Bus Skew Report Summary +2. Bus Skew Report Per Constraint + +1. Bus Skew Report Summary +-------------------------- + +Id Position From To Corner Requirement(ns) Actual(ns) Slack(ns) +-- -------- ------------------------------ ------------------------------ ------ --------------- ---------- --------- +1 31 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 0.873 11.127 +2 33 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 0.653 11.347 +3 35 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 0.929 11.071 +4 37 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 0.779 11.221 +5 39 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 0.489 11.511 +6 41 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 0.698 11.302 +7 43 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 1.078 10.922 +8 45 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 0.985 11.015 +9 47 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 0.763 11.237 +10 49 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 0.781 11.219 + + +2. Bus Skew Report Per Constraint +--------------------------------- + +Id: 1 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +core_raw clk_pll_i memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + Slow 0.873 11.127 + + +Slack (MET) : 11.127ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: -0.562ns + Reference Relative Delay: -1.878ns + Relative CRPR: 0.444ns + Actual Bus Skew: 0.873ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.613 -0.927 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X53Y80 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X53Y80 FDRE (Prop_fdre_C_Q) 0.419 -0.508 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.747 0.239 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[1] + SLICE_X49Y78 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.498 0.671 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X49Y78 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C + clock pessimism 0.395 1.066 + SLICE_X49Y78 FDRE (Setup_fdre_C_D) -0.265 0.801 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + ------------------------------------------------------------------- + data arrival 0.239 + clock arrival 0.801 + ------------------------------------------------------------------- + relative delay -0.562 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=35517, routed) 1.489 -1.531 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X55Y76 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X55Y76 FDRE (Prop_fdre_C_Q) 0.367 -1.164 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.489 -0.675 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[2] + SLICE_X57Y76 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.606 1.428 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X57Y76 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C + clock pessimism -0.395 1.033 + SLICE_X57Y76 FDRE (Hold_fdre_C_D) 0.170 1.203 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2] + ------------------------------------------------------------------- + data arrival -0.675 + clock arrival 1.203 + ------------------------------------------------------------------- + relative delay -1.878 + + + +Id: 2 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +core_raw clk_pll_i memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + Slow 0.653 11.347 + + +Slack (MET) : 11.347ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: -0.897ns + Reference Relative Delay: -2.108ns + Relative CRPR: 0.558ns + Actual Bus Skew: 0.653ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.633 -0.907 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X68Y94 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X68Y94 FDRE (Prop_fdre_C_Q) 0.456 -0.451 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.535 0.085 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[0] + SLICE_X69Y94 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.509 0.682 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X69Y94 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C + clock pessimism 0.395 1.077 + SLICE_X69Y94 FDRE (Setup_fdre_C_D) -0.095 0.982 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + ------------------------------------------------------------------- + data arrival 0.085 + clock arrival 0.982 + ------------------------------------------------------------------- + relative delay -0.897 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=35517, routed) 1.512 -1.508 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X68Y94 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X68Y94 FDRE (Prop_fdre_C_Q) 0.367 -1.141 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.260 -0.882 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[2] + SLICE_X68Y92 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.630 1.452 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X68Y92 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C + clock pessimism -0.395 1.057 + SLICE_X68Y92 FDRE (Hold_fdre_C_D) 0.169 1.226 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2] + ------------------------------------------------------------------- + data arrival -0.882 + clock arrival 1.226 + ------------------------------------------------------------------- + relative delay -2.108 + + + +Id: 3 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +clk_pll_i core_raw memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + Slow 0.929 11.071 + + +Slack (MET) : 11.071ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: 3.868ns + Reference Relative Delay: 2.440ns + Relative CRPR: 0.499ns + Actual Bus Skew: 0.929ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.630 1.452 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X67Y92 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y92 FDRE (Prop_fdre_C_Q) 0.456 1.908 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.752 2.660 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[0] + SLICE_X64Y93 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=35517, routed) 1.512 -1.508 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X64Y93 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C + clock pessimism 0.395 -1.113 + SLICE_X64Y93 FDRE (Setup_fdre_C_D) -0.095 -1.208 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + ------------------------------------------------------------------- + data arrival 2.660 + clock arrival -1.208 + ------------------------------------------------------------------- + relative delay 3.868 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.508 0.681 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X68Y92 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X68Y92 FDRE (Prop_fdre_C_Q) 0.367 1.048 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.260 1.307 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[3] + SLICE_X68Y94 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.633 -0.907 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X68Y94 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C + clock pessimism -0.395 -1.302 + SLICE_X68Y94 FDRE (Hold_fdre_C_D) 0.169 -1.133 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3] + ------------------------------------------------------------------- + data arrival 1.307 + clock arrival -1.133 + ------------------------------------------------------------------- + relative delay 2.440 + + + +Id: 4 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +core_raw clk_pll_i memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + Slow 0.779 11.221 + + +Slack (MET) : 11.221ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: -0.747ns + Reference Relative Delay: -2.080ns + Relative CRPR: 0.554ns + Actual Bus Skew: 0.779ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.714 -0.826 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X87Y109 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X87Y109 FDRE (Prop_fdre_C_Q) 0.419 -0.407 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.607 0.199 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[3] + SLICE_X88Y109 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.597 0.769 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X88Y109 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C + clock pessimism 0.395 1.164 + SLICE_X88Y109 FDRE (Setup_fdre_C_D) -0.218 0.946 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3] + ------------------------------------------------------------------- + data arrival 0.199 + clock arrival 0.946 + ------------------------------------------------------------------- + relative delay -0.747 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=35517, routed) 1.594 -1.427 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X87Y109 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X87Y109 FDRE (Prop_fdre_C_Q) 0.367 -1.060 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.293 -0.767 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[2] + SLICE_X86Y109 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.716 1.538 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X86Y109 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C + clock pessimism -0.395 1.143 + SLICE_X86Y109 FDRE (Hold_fdre_C_D) 0.170 1.313 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2] + ------------------------------------------------------------------- + data arrival -0.767 + clock arrival 1.313 + ------------------------------------------------------------------- + relative delay -2.080 + + + +Id: 5 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +clk_pll_i core_raw memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + Slow 0.489 11.511 + + +Slack (MET) : 11.511ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: 3.567ns + Reference Relative Delay: 2.548ns + Relative CRPR: 0.529ns + Actual Bus Skew: 0.489ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.717 1.539 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X89Y108 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X89Y108 FDRE (Prop_fdre_C_Q) 0.456 1.995 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.445 2.440 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[0] + SLICE_X87Y109 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=35517, routed) 1.594 -1.427 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X87Y109 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C + clock pessimism 0.395 -1.032 + SLICE_X87Y109 FDRE (Setup_fdre_C_D) -0.095 -1.127 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + ------------------------------------------------------------------- + data arrival 2.440 + clock arrival -1.127 + ------------------------------------------------------------------- + relative delay 3.567 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.594 0.766 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X89Y114 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X89Y114 FDRE (Prop_fdre_C_Q) 0.367 1.133 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.360 1.493 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[3] + SLICE_X87Y114 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.711 -0.829 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X87Y114 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C + clock pessimism -0.395 -1.224 + SLICE_X87Y114 FDRE (Hold_fdre_C_D) 0.169 -1.055 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3] + ------------------------------------------------------------------- + data arrival 1.493 + clock arrival -1.055 + ------------------------------------------------------------------- + relative delay 2.548 + + + +Id: 6 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +clk_pll_i core_raw memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + Slow 0.698 11.302 + + +Slack (MET) : 11.302ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: 3.743ns + Reference Relative Delay: 2.489ns + Relative CRPR: 0.556ns + Actual Bus Skew: 0.698ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.715 1.537 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X76Y94 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X76Y94 FDRE (Prop_fdre_C_Q) 0.478 2.015 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.432 2.448 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[1] + SLICE_X75Y94 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=35517, routed) 1.597 -1.423 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X75Y94 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C + clock pessimism 0.395 -1.028 + SLICE_X75Y94 FDRE (Setup_fdre_C_D) -0.267 -1.295 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + ------------------------------------------------------------------- + data arrival 2.448 + clock arrival -1.295 + ------------------------------------------------------------------- + relative delay 3.743 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.594 0.767 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X76Y94 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X76Y94 FDRE (Prop_fdre_C_Q) 0.418 1.185 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.255 1.440 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[2] + SLICE_X77Y93 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.717 -0.823 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X77Y93 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C + clock pessimism -0.395 -1.218 + SLICE_X77Y93 FDRE (Hold_fdre_C_D) 0.169 -1.049 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2] + ------------------------------------------------------------------- + data arrival 1.440 + clock arrival -1.049 + ------------------------------------------------------------------- + relative delay 2.489 + + + +Id: 7 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +core_raw clk_pll_i memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + Slow 1.078 10.922 + + +Slack (MET) : 10.922ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: -0.584ns + Reference Relative Delay: -2.177ns + Relative CRPR: 0.515ns + Actual Bus Skew: 1.078ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.717 -0.823 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X76Y93 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X76Y93 FDRE (Prop_fdre_C_Q) 0.518 -0.305 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.813 0.509 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[2] + SLICE_X73Y93 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.592 0.765 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X73Y93 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C + clock pessimism 0.395 1.160 + SLICE_X73Y93 FDRE (Setup_fdre_C_D) -0.067 1.093 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2] + ------------------------------------------------------------------- + data arrival 0.509 + clock arrival 1.093 + ------------------------------------------------------------------- + relative delay -0.584 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=35517, routed) 1.597 -1.423 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X75Y94 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X75Y94 FDRE (Prop_fdre_C_Q) 0.367 -1.056 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.254 -0.802 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[3] + SLICE_X74Y93 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.715 1.537 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X74Y93 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C + clock pessimism -0.395 1.142 + SLICE_X74Y93 FDRE (Hold_fdre_C_D) 0.233 1.375 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3] + ------------------------------------------------------------------- + data arrival -0.802 + clock arrival 1.375 + ------------------------------------------------------------------- + relative delay -2.177 + + + +Id: 8 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +core_raw clk_pll_i memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + Slow 0.985 11.015 + + +Slack (MET) : 11.015ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: -0.551ns + Reference Relative Delay: -2.003ns + Relative CRPR: 0.468ns + Actual Bus Skew: 0.985ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.613 -0.927 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X53Y80 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X53Y80 FDRE (Prop_fdre_C_Q) 0.419 -0.508 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.746 0.238 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[1] + SLICE_X48Y80 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.499 0.672 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X48Y80 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C + clock pessimism 0.395 1.067 + SLICE_X48Y80 FDRE (Setup_fdre_C_D) -0.278 0.789 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + ------------------------------------------------------------------- + data arrival 0.238 + clock arrival 0.789 + ------------------------------------------------------------------- + relative delay -0.551 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=35517, routed) 1.493 -1.527 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X53Y80 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X53Y80 FDRE (Prop_fdre_C_Q) 0.367 -1.160 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.366 -0.794 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[0] + SLICE_X57Y80 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.612 1.434 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X57Y80 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C + clock pessimism -0.395 1.039 + SLICE_X57Y80 FDRE (Hold_fdre_C_D) 0.170 1.209 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + ------------------------------------------------------------------- + data arrival -0.794 + clock arrival 1.209 + ------------------------------------------------------------------- + relative delay -2.003 + + + +Id: 9 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +clk_pll_i core_raw memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + Slow 0.763 11.237 + + +Slack (MET) : 11.237ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: 3.721ns + Reference Relative Delay: 2.442ns + Relative CRPR: 0.516ns + Actual Bus Skew: 0.763ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.612 1.434 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X57Y80 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X57Y80 FDRE (Prop_fdre_C_Q) 0.456 1.890 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.606 2.496 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[0] + SLICE_X57Y81 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=35517, routed) 1.495 -1.525 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X57Y81 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C + clock pessimism 0.395 -1.130 + SLICE_X57Y81 FDRE (Setup_fdre_C_D) -0.095 -1.225 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + ------------------------------------------------------------------- + data arrival 2.496 + clock arrival -1.225 + ------------------------------------------------------------------- + relative delay 3.721 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.487 0.660 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X57Y76 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X57Y76 FDRE (Prop_fdre_C_Q) 0.367 1.027 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.257 1.284 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[2] + SLICE_X55Y76 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.607 -0.933 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X55Y76 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C + clock pessimism -0.395 -1.328 + SLICE_X55Y76 FDRE (Hold_fdre_C_D) 0.169 -1.159 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2] + ------------------------------------------------------------------- + data arrival 1.284 + clock arrival -1.159 + ------------------------------------------------------------------- + relative delay 2.442 + + + +Id: 10 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +clk_pll_i core_raw memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + Slow 0.781 11.219 + + +Slack (MET) : 11.219ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: 3.898ns + Reference Relative Delay: 2.579ns + Relative CRPR: 0.539ns + Actual Bus Skew: 0.781ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.614 1.436 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X59Y78 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X59Y78 FDRE (Prop_fdre_C_Q) 0.419 1.855 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.646 2.501 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[1] + SLICE_X59Y79 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=35517, routed) 1.498 -1.522 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X59Y79 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C + clock pessimism 0.395 -1.127 + SLICE_X59Y79 FDRE (Setup_fdre_C_D) -0.270 -1.397 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + ------------------------------------------------------------------- + data arrival 2.501 + clock arrival -1.397 + ------------------------------------------------------------------- + relative delay 3.898 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.494 0.667 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X59Y78 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X59Y78 FDRE (Prop_fdre_C_Q) 0.367 1.034 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.391 1.425 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[0] + SLICE_X55Y78 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.611 -0.929 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X55Y78 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C + clock pessimism -0.395 -1.324 + SLICE_X55Y78 FDRE (Hold_fdre_C_D) 0.170 -1.154 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + ------------------------------------------------------------------- + data arrival 1.425 + clock arrival -1.154 + ------------------------------------------------------------------- + relative delay 2.579 + + + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/cdc.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/cdc.rpt new file mode 100644 index 0000000..0772732 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/cdc.rpt @@ -0,0 +1,93 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Mon Oct 12 20:36:23 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_cdc -details -return_string +| Design : toy_a7_top +| Device : 7a100t-csg324 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +| Design State : Routed +--------------------------------------------------------------------------------------------------------------------------------------------- + +CDC Report + +ID Severity Count Description +------ -------- ----- ------------------------------------------------------- +CDC-3 Info 17 1-bit synchronized with ASYNC_REG property +CDC-9 Info 10 Asynchronous reset synchronized with ASYNC_REG property +CDC-15 Warning 3 Clock enable controlled CDC structure detected + +Source Clock: core_raw +Destination Clock: clk_pll_i +CDC Type: Safely Timed + +Row ID Severity Description Depth Exception Source (From) Destination (To) +--- ------ -------- ------------------------------------------------------- ----- ---------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + 1 CDC-15 Warning Clock enable controlled CDC structure detected 0 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_60_60/DP/CLK memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[60]/D + 2 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path reset_count_reg[9]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + 3 CDC-3 Info 1-bit synchronized with ASYNC_REG property 7 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd/syncstages_ff_reg[0]/D + 4 CDC-3 Info 1-bit synchronized with ASYNC_REG property 6 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr/syncstages_ff_reg[0]/D + 5 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path reset_count_reg[9]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + 6 CDC-15 Warning Clock enable controlled CDC structure detected 0 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_60_60/DP/CLK memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[60]/D + 7 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path reset_count_reg[9]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + 8 CDC-3 Info 1-bit synchronized with ASYNC_REG property 7 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd/syncstages_ff_reg[0]/D + 9 CDC-15 Warning Clock enable controlled CDC structure detected 0 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_144_144/DP/CLK memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[144]/D + 10 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path reset_count_reg[9]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + 11 CDC-3 Info 1-bit synchronized with ASYNC_REG property 7 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd/syncstages_ff_reg[0]/D + 12 CDC-3 Info 1-bit synchronized with ASYNC_REG property 6 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr/syncstages_ff_reg[0]/D + 13 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path reset_count_reg[9]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + +Source Clock: mem_refclk +Destination Clock: clk_pll_i +CDC Type: User Ignored + +Row ID Severity Description Depth Exception Source (From) Destination (To) +--- ----- -------- ------------------------------------------ ----- ---------- -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------------------------------- + 1 CDC-3 Info 1-bit synchronized with ASYNC_REG property 3 False Path ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/MEMREFCLK ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[2]/D + 2 CDC-3 Info 1-bit synchronized with ASYNC_REG property 3 False Path ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/MEMREFCLK ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[3]/D + +Source Clock: clk_pll_i +Destination Clock: core_raw +CDC Type: Safely Timed + +Row ID Severity Description Depth Exception Source (From) Destination (To) +--- ----- -------- ------------------------------------------------------- ----- ---------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + 1 CDC-3 Info 1-bit synchronized with ASYNC_REG property 2 False Path ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/init_calib_complete_reg/C calib_sync_reg[0]/D + 2 CDC-3 Info 1-bit synchronized with ASYNC_REG property 6 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr/syncstages_ff_reg[0]/D + 3 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path ui_reset_pipe_reg[2]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + 4 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path ui_reset_pipe_reg[2]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + 5 CDC-3 Info 1-bit synchronized with ASYNC_REG property 7 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd/syncstages_ff_reg[0]/D + 6 CDC-3 Info 1-bit synchronized with ASYNC_REG property 6 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr/syncstages_ff_reg[0]/D + 7 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path ui_reset_pipe_reg[2]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + 8 CDC-3 Info 1-bit synchronized with ASYNC_REG property 6 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr/syncstages_ff_reg[0]/D + 9 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path ui_reset_pipe_reg[2]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + 10 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path ui_reset_pipe_reg[2]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + 11 CDC-3 Info 1-bit synchronized with ASYNC_REG property 7 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd/syncstages_ff_reg[0]/D + +Source Clock: input port clock +Destination Clock: core_raw +CDC Type: No Common Primary Clock + +Row ID Severity Description Depth Exception Source (From) Destination (To) +--- ----- -------- ------------------------------------------ ----- ---------- ------------- ------------------------------- + 1 CDC-3 Info 1-bit synchronized with ASYNC_REG property 2 False Path btn0 btn_meta_reg/D + 2 CDC-3 Info 1-bit synchronized with ASYNC_REG property 2 False Path uart_txd_in platform/receiver/rx_meta_reg/D + +Source Clock: clk_pll_i +Destination Clock: ref_raw +CDC Type: Safely Timed + +Row ID Severity Description Depth Exception Source (From) Destination (To) +--- ----- -------- ------------------------------------------ ----- ----------------------- ------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------ + 1 CDC-3 Info 1-bit synchronized with ASYNC_REG property 2 Max Delay Datapath Only ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg/D + +Source Clock: input port clock +Destination Clock: ref_raw +CDC Type: No Common Primary Clock + +Row ID Severity Description Depth Exception Source (From) Destination (To) +--- ----- -------- ------------------------------------------ ----- ---------- ------------- ------------------ + 1 CDC-3 Info 1-bit synchronized with ASYNC_REG property 2 False Path btn0 btn_ref_meta_reg/D + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/check-timing.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/check-timing.rpt new file mode 100644 index 0000000..a2f2d10 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/check-timing.rpt @@ -0,0 +1,108 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Mon Oct 12 20:36:40 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : check_timing -verbose -file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/check-timing.rpt +| Design : toy_a7_top +| Device : 7a100t-csg324 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +| Design State : Routed +---------------------------------------------------------------------------------------------------------------------------------------------------------- + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock (0) +2. checking constant_clock (0) +3. checking pulse_width_clock (0) +4. checking unconstrained_internal_endpoints (0) +5. checking no_input_delay (2) +6. checking no_output_delay (6) +7. checking multiple_clock (0) +8. checking generated_clocks (0) +9. checking loops (0) +10. checking partial_input_delay (0) +11. checking partial_output_delay (0) +12. checking latch_loops (0) + +1. checking no_clock (0) +------------------------ + There are 0 register/latch pins with no clock. + + +2. checking constant_clock (0) +------------------------------ + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock (0) +--------------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints (0) +------------------------------------------------ + There are 0 pins that are not constrained for maximum delay. + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay (2) +------------------------------ + There are 0 input ports with no input delay specified. + + There are 2 input ports with no input delay but user has a false path constraint. (MEDIUM) + +btn0 +uart_txd_in + + +6. checking no_output_delay (6) +------------------------------- + There are 0 ports with no output delay specified. + + There are 6 ports with no output delay but user has a false path constraint (MEDIUM) + +ddr3_reset_n +led[0] +led[1] +led[2] +led[3] +uart_rxd_out + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock (0) +------------------------------ + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks (0) +-------------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops (0) +--------------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay (0) +------------------------------------ + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay (0) +------------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops (0) +---------------------------- + There are 0 combinational latch loops in the design through latch input + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/clocks.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/clocks.rpt new file mode 100644 index 0000000..b5f4351 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/clocks.rpt @@ -0,0 +1,203 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Mon Oct 12 20:36:39 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_clocks -file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/clocks.rpt +| Design : toy_a7_top +| Device : 7a100t-csg324 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +| Design State : Routed +--------------------------------------------------------------------------------------------------------------------------------------------- + +Clock Report + + +Attributes + P: Propagated + G: Generated + A: Auto-derived + R: Renamed + V: Virtual + I: Inverted + S: Pin phase-shifted with Latency mode + +Clock Period(ns) Waveform(ns) Attributes Sources +board_clk 10.000 {0.000 5.000} P {CLK100MHZ} +clk_pll_i 12.000 {0.000 6.000} P,G,A {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT} +core_raw 40.000 {0.000 20.000} P,G,A {clock_mmcm/CLKOUT0} +fb 10.000 {0.000 5.000} P,G,A {clock_mmcm/CLKFBOUT} +freq_refclk 1.500 {0.000 0.750} P,G,A {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0} +iserdes_clkdiv 12.000 {0.000 6.000} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV} +iserdes_clkdiv_1 12.000 {0.000 6.000} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV} +mem_refclk 3.000 {0.000 1.500} P,G,A {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1} +oserdes_clk 3.000 {0.000 1.500} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK} +oserdes_clk_1 3.000 {0.000 1.500} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK} +oserdes_clk_2 3.000 {0.000 1.500} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK} +oserdes_clk_3 3.000 {0.000 1.500} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK} +oserdes_clkdiv 12.000 {0.000 6.000} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV} +oserdes_clkdiv_1 12.000 {0.000 6.000} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV} +oserdes_clkdiv_2 6.000 {0.000 3.000} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV} +oserdes_clkdiv_3 6.000 {0.000 3.000} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV} +pll_clk3_out 12.000 {0.000 6.000} P,G,A {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3} +pll_clkfbout 6.000 {0.000 3.000} P,G,A {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT} +ref_raw 5.000 {0.000 2.500} P,G,A {clock_mmcm/CLKOUT2} +sync_pulse 48.000 {1.312 4.312} P,G,A {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2} +sys_raw 6.000 {0.000 3.000} P,G,A {clock_mmcm/CLKOUT1} +u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk 3.000 {0.000 1.500} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK} +u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk 3.000 {0.000 1.500} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK} + + +==================================================== +Generated Clocks +==================================================== + +Generated Clock : clk_pll_i +Master Source : ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKIN1 +Master Clock : pll_clk3_out +Multiply By : 1 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT} + +Generated Clock : core_raw +Master Source : clock_mmcm/CLKIN1 +Master Clock : board_clk +Edges : {1 2 3} +Edge Shifts(ns) : {0.000 15.000 30.000} +Generated Sources : {clock_mmcm/CLKOUT0} + +Generated Clock : fb +Master Source : clock_mmcm/CLKIN1 +Master Clock : board_clk +Multiply By : 1 +Generated Sources : {clock_mmcm/CLKFBOUT} + +Generated Clock : freq_refclk +Master Source : ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 +Master Clock : sys_raw +Multiply By : 4 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0} + +Generated Clock : iserdes_clkdiv +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK +Master Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk +Divide By : 4 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV} + +Generated Clock : iserdes_clkdiv_1 +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK +Master Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk +Divide By : 4 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV} + +Generated Clock : mem_refclk +Master Source : ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 +Master Clock : sys_raw +Multiply By : 2 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1} + +Generated Clock : oserdes_clk +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/MEMREFCLK +Master Clock : mem_refclk +Divide By : 1 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK} + +Generated Clock : oserdes_clk_1 +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/MEMREFCLK +Master Clock : mem_refclk +Divide By : 1 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK} + +Generated Clock : oserdes_clk_2 +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/MEMREFCLK +Master Clock : mem_refclk +Divide By : 1 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK} + +Generated Clock : oserdes_clk_3 +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/MEMREFCLK +Master Clock : mem_refclk +Divide By : 1 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK} + +Generated Clock : oserdes_clkdiv +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK +Master Clock : oserdes_clk +Divide By : 4 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV} + +Generated Clock : oserdes_clkdiv_1 +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK +Master Clock : oserdes_clk_1 +Divide By : 4 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV} + +Generated Clock : oserdes_clkdiv_2 +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK +Master Clock : oserdes_clk_2 +Divide By : 2 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV} + +Generated Clock : oserdes_clkdiv_3 +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK +Master Clock : oserdes_clk_3 +Divide By : 2 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV} + +Generated Clock : pll_clk3_out +Master Source : ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 +Master Clock : sys_raw +Edges : {1 2 3} +Edge Shifts(ns) : {0.000 3.000 6.000} +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3} + +Generated Clock : pll_clkfbout +Master Source : ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 +Master Clock : sys_raw +Multiply By : 1 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT} + +Generated Clock : ref_raw +Master Source : clock_mmcm/CLKIN1 +Master Clock : board_clk +Multiply By : 2 +Generated Sources : {clock_mmcm/CLKOUT2} + +Generated Clock : sync_pulse +Master Source : ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 +Master Clock : sys_raw +Edges : {1 2 3} +Edge Shifts(ns) : {1.312 1.313 43.312} +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2} + +Generated Clock : sys_raw +Master Source : clock_mmcm/CLKIN1 +Master Clock : board_clk +Edges : {1 2 3} +Edge Shifts(ns) : {0.000 -2.000 -4.000} +Generated Sources : {clock_mmcm/CLKOUT1} + +Generated Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/FREQREFCLK +Master Clock : freq_refclk +Divide By : 2 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK} + +Generated Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/FREQREFCLK +Master Clock : freq_refclk +Divide By : 2 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK} + + + +==================================================== +User Uncertainty +==================================================== + + + +==================================================== +User Jitter +==================================================== + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/console.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/console.log new file mode 100644 index 0000000..87f2d59 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/console.log @@ -0,0 +1,5789 @@ + +****** Vivado v2024.1 (64-bit) + **** SW Build 5076996 on Wed May 22 18:36:09 MDT 2024 + **** IP Build 5075265 on Wed May 22 21:45:21 MDT 2024 + **** SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024 + **** Start of session at: Mon Oct 12 20:13:53 2026 + ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. + ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. + +source /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/build_board.tcl +# set root [file dirname [file dirname [file normalize [info script]]]] +# cd $root +# if {[llength $argv]<1 || [llength $argv]>2} {error "Usage: build_board.tcl OUTPUT_DIRECTORY ?flash?"} +# set flash 0 +# if {[llength $argv]==2} { +# if {[lindex $argv 1] ne "flash"} {error "Second argument must be flash"} +# set flash 1 +# } +# set out [file normalize [lindex $argv 0]] +# file mkdir $out +# file mkdir $out/ip +# proc phase {name} { +# global out +# set f [open $out/phase.txt w];puts $f $name;close $f +# puts "BOARD_PHASE $name" +# } +# set_param general.maxThreads 8 +# phase CREATE_IP +BOARD_PHASE CREATE_IP +# create_project -in_memory -part xc7a100tcsg324-1 +# set_property target_language Verilog [current_project] +# create_ip -name mig_7series -vendor xilinx.com -library ip -version 4.2 -module_name arty_ddr3 -dir $out/ip +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data0/tools/Xilinx/Vivado/2024.1/data/ip'. +# set_property CONFIG.XML_INPUT_FILE $root/board/vendor/mig.prj [get_ips arty_ddr3] +INFO: [IP_Flow 19-3484] Absolute path of file '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/vendor/mig.prj' provided. It will be converted relative to IP Instance files '../../../../board/vendor/mig.prj' +INFO: [Device 21-403] Loading part xc7a100tcsg324-1 +INFO: [Device 21-9227] Part: xc7a100tcsg324-1 does not have CEAM library. +# create_ip -name axi_clock_converter -vendor xilinx.com -library ip -version 2.1 -module_name toy_axi_cdc -dir $out/ip +# set_property -dict {CONFIG.PROTOCOL AXI4 CONFIG.ADDR_WIDTH 28 CONFIG.DATA_WIDTH 128 CONFIG.ID_WIDTH 4 CONFIG.ACLK_ASYNC 1 CONFIG.SYNCHRONIZATION_STAGES 3} [get_ips toy_axi_cdc] +# generate_target all [get_ips] +INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'arty_ddr3'... +INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'arty_ddr3'... +INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'arty_ddr3'... +INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'arty_ddr3'... +INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'arty_ddr3'... +INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'toy_axi_cdc'... +INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'toy_axi_cdc'... +WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_ooc.xdc' +INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'toy_axi_cdc'... +INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'toy_axi_cdc'... +INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'toy_axi_cdc'... +generate_target: Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 2222.848 ; gain = 275.328 ; free physical = 491940 ; free virtual = 628327 +# report_ip_status -file $out/ip-status.rpt +# phase SYNTH_IP +BOARD_PHASE SYNTH_IP +# synth_ip [get_ips] +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data0/tools/Xilinx/Vivado/2024.1/data/ip'. +WARNING: [Vivado 12-13650] The IP file '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3.xci' has been moved from its original location, as a result the outputs for this IP will now be generated in '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3'. Alternatively a copy of the IP can be imported into the project using one of the 'import_ip' or 'import_files' commands. +Command: synth_design -top arty_ddr3 -part xc7a100tcsg324-1 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. +INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes +INFO: [Synth 8-7075] Helper process launched with PID 20494 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2658.477 ; gain = 417.715 ; free physical = 491599 ; free virtual = 627992 +--------------------------------------------------------------------------------- +WARNING: [Synth 8-10515] begin/end is required for generate-for in this mode of Verilog [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v:253] +INFO: [Synth 8-11241] undeclared symbol 'dbg_sel_po_incdec', assumed default net type 'wire' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:1223] +INFO: [Synth 8-11241] undeclared symbol 'dbg_po_f_inc', assumed default net type 'wire' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:1227] +INFO: [Synth 8-11241] undeclared symbol 'dbg_po_f_stg23_sel', assumed default net type 'wire' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:1228] +INFO: [Synth 8-11241] undeclared symbol 'dbg_po_f_dec', assumed default net type 'wire' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:1229] +INFO: [Synth 8-6157] synthesizing module 'arty_ddr3' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3.v:70] +INFO: [Synth 8-6157] synthesizing module 'arty_ddr3_mig' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:75] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_tempmon' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v:69] + Parameter TCQ bound to: 100 - type: integer + Parameter TEMP_MON_CONTROL bound to: INTERNAL - type: string + Parameter XADC_CLK_PERIOD bound to: 5000 - type: integer + Parameter tTEMPSAMPLE bound to: 10000000 - type: integer +INFO: [Synth 8-6157] synthesizing module 'XADC' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:143027] + Parameter INIT_40 bound to: 16'b0001000000000000 + Parameter INIT_41 bound to: 16'b0010111111111111 + Parameter INIT_42 bound to: 16'b0000100000000000 + Parameter INIT_48 bound to: 16'b0000000100000001 + Parameter INIT_49 bound to: 16'b0000000000000000 + Parameter INIT_4A bound to: 16'b0000000100000000 + Parameter INIT_4B bound to: 16'b0000000000000000 + Parameter INIT_4C bound to: 16'b0000000000000000 + Parameter INIT_4D bound to: 16'b0000000000000000 + Parameter INIT_4E bound to: 16'b0000000000000000 + Parameter INIT_4F bound to: 16'b0000000000000000 + Parameter INIT_50 bound to: 16'b1011010111101101 + Parameter INIT_51 bound to: 16'b0101011111100100 + Parameter INIT_52 bound to: 16'b1010000101000111 + Parameter INIT_53 bound to: 16'b1100101000110011 + Parameter INIT_54 bound to: 16'b1010100100111010 + Parameter INIT_55 bound to: 16'b0101001011000110 + Parameter INIT_56 bound to: 16'b1001010101010101 + Parameter INIT_57 bound to: 16'b1010111001001110 + Parameter INIT_58 bound to: 16'b0101100110011001 + Parameter INIT_5C bound to: 16'b0101000100010001 + Parameter SIM_DEVICE bound to: 7SERIES - type: string +INFO: [Synth 8-6155] done synthesizing module 'XADC' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:143027] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_tempmon' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v:69] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_iodelay_ctrl' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_iodelay_ctrl.v:80] + Parameter TCQ bound to: 100 - type: integer + Parameter IODELAY_GRP0 bound to: ARTY_DDR3_IODELAY_MIG0 - type: string + Parameter IODELAY_GRP1 bound to: ARTY_DDR3_IODELAY_MIG1 - type: string + Parameter REFCLK_TYPE bound to: NO_BUFFER - type: string + Parameter SYSCLK_TYPE bound to: NO_BUFFER - type: string + Parameter SYS_RST_PORT bound to: FALSE - type: string + Parameter RST_ACT_LOW bound to: 1 - type: integer + Parameter DIFF_TERM_REFCLK bound to: TRUE - type: string + Parameter FPGA_SPEED_GRADE bound to: 1 - type: integer + Parameter REF_CLK_MMCM_IODELAY_CTRL bound to: FALSE - type: string +INFO: [Synth 8-6157] synthesizing module 'IDELAYCTRL' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:75739] +INFO: [Synth 8-6155] done synthesizing module 'IDELAYCTRL' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:75739] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_iodelay_ctrl' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_iodelay_ctrl.v:80] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_clk_ibuf' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_clk_ibuf.v:68] + Parameter SYSCLK_TYPE bound to: NO_BUFFER - type: string + Parameter DIFF_TERM_SYSCLK bound to: TRUE - type: string +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_clk_ibuf' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_clk_ibuf.v:68] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_infrastructure' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:78] + Parameter TCQ bound to: 100 - type: integer + Parameter CLKIN_PERIOD bound to: 6000 - type: integer + Parameter nCK_PER_CLK bound to: 4 - type: integer + Parameter SYSCLK_TYPE bound to: NO_BUFFER - type: string + Parameter CLKFBOUT_MULT bound to: 8 - type: integer + Parameter DIVCLK_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT0_DIVIDE bound to: 2 - type: integer + Parameter CLKOUT1_DIVIDE bound to: 4 - type: integer + Parameter CLKOUT2_DIVIDE bound to: 64 - type: integer + Parameter CLKOUT3_DIVIDE bound to: 16 - type: integer + Parameter MMCM_VCO bound to: 666 - type: integer + Parameter MMCM_MULT_F bound to: 8 - type: integer + Parameter MMCM_DIVCLK_DIVIDE bound to: 1 - type: integer + Parameter RST_ACT_LOW bound to: 1 - type: integer + Parameter tCK bound to: 3000 - type: integer + Parameter MEM_TYPE bound to: DDR3 - type: string +INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82388] + Parameter BANDWIDTH bound to: HIGH - type: string + Parameter CLKFBOUT_MULT_F bound to: 8.000000 - type: double + Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double + Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKIN1_PERIOD bound to: 12.000000 - type: double + Parameter CLKOUT0_DIVIDE_F bound to: 16.000000 - type: double + Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT0_USE_FINE_PS bound to: TRUE - type: string + Parameter CLKOUT1_DIVIDE bound to: 4 - type: integer + Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT4_CASCADE bound to: FALSE - type: string + Parameter COMPENSATION bound to: BUF_IN - type: string + Parameter DIVCLK_DIVIDE bound to: 1 - type: integer + Parameter REF_JITTER1 bound to: 0.000000 - type: double + Parameter STARTUP_WAIT bound to: FALSE - type: string +INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82388] +INFO: [Synth 8-6157] synthesizing module 'BUFG' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951] +INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951] +INFO: [Synth 8-6157] synthesizing module 'PLLE2_ADV' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114750] + Parameter BANDWIDTH bound to: OPTIMIZED - type: string + Parameter CLKFBOUT_MULT bound to: 8 - type: integer + Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double + Parameter CLKIN1_PERIOD bound to: 6.000000 - type: double + Parameter CLKOUT0_DIVIDE bound to: 2 - type: integer + Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT1_DIVIDE bound to: 4 - type: integer + Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT2_DIVIDE bound to: 64 - type: integer + Parameter CLKOUT2_DUTY_CYCLE bound to: 0.062500 - type: double + Parameter CLKOUT2_PHASE bound to: 9.843750 - type: double + Parameter CLKOUT3_DIVIDE bound to: 16 - type: integer + Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT3_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT4_DIVIDE bound to: 8 - type: integer + Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT4_PHASE bound to: 168.750000 - type: double + Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT5_PHASE bound to: 0.000000 - type: double + Parameter COMPENSATION bound to: INTERNAL - type: string + Parameter DIVCLK_DIVIDE bound to: 1 - type: integer + Parameter REF_JITTER1 bound to: 0.010000 - type: double + Parameter REF_JITTER2 bound to: 0.010000 - type: double + Parameter STARTUP_WAIT bound to: FALSE - type: string +INFO: [Synth 8-6155] done synthesizing module 'PLLE2_ADV' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114750] +INFO: [Synth 8-6157] synthesizing module 'BUFH' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:2199] +INFO: [Synth 8-6155] done synthesizing module 'BUFH' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:2199] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_infrastructure' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:78] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_memc_ui_top_axi' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_memc_ui_top_axi.v:71] + Parameter TCQ bound to: 100 - type: integer + Parameter DDR3_VDD_OP_VOLT bound to: 135 - type: string + Parameter PAYLOAD_WIDTH bound to: 16 - type: integer + Parameter ADDR_CMD_MODE bound to: 1T - type: string + Parameter AL bound to: 0 - type: string + Parameter BANK_WIDTH bound to: 3 - type: integer + Parameter BM_CNT_WIDTH bound to: 2 - type: integer + Parameter BURST_MODE bound to: 8 - type: string + Parameter BURST_TYPE bound to: SEQ - type: string + Parameter CA_MIRROR bound to: OFF - type: string + Parameter CK_WIDTH bound to: 1 - type: integer + Parameter CL bound to: 5 - type: integer + Parameter COL_WIDTH bound to: 10 - type: integer + Parameter CMD_PIPE_PLUS1 bound to: ON - type: string + Parameter CS_WIDTH bound to: 1 - type: integer + Parameter CKE_WIDTH bound to: 1 - type: integer + Parameter CWL bound to: 5 - type: integer + Parameter DATA_WIDTH bound to: 16 - type: integer + Parameter DATA_BUF_ADDR_WIDTH bound to: 5 - type: integer + Parameter DM_WIDTH bound to: 2 - type: integer + Parameter DQ_CNT_WIDTH bound to: 4 - type: integer + Parameter DQ_WIDTH bound to: 16 - type: integer + Parameter DQS_CNT_WIDTH bound to: 1 - type: integer + Parameter DQS_WIDTH bound to: 2 - type: integer + Parameter DRAM_TYPE bound to: DDR3 - type: string + Parameter DRAM_WIDTH bound to: 8 - type: integer + Parameter ECC bound to: OFF - type: string + Parameter ECC_WIDTH bound to: 0 - type: integer + Parameter ECC_TEST bound to: OFF - type: string + Parameter MC_ERR_ADDR_WIDTH bound to: 28 - type: integer + Parameter MASTER_PHY_CTL bound to: 0 - type: integer + Parameter nAL bound to: 0 - type: integer + Parameter nBANK_MACHS bound to: 4 - type: integer + Parameter nCK_PER_CLK bound to: 4 - type: integer + Parameter nCS_PER_RANK bound to: 1 - type: integer + Parameter ORDERING bound to: NORM - type: string + Parameter IBUF_LPWR_MODE bound to: OFF - type: string + Parameter BANK_TYPE bound to: HR_IO - type: string + Parameter DATA_IO_PRIM_TYPE bound to: HR_LP - type: string + Parameter DATA_IO_IDLE_PWRDWN bound to: ON - type: string + Parameter IODELAY_GRP0 bound to: ARTY_DDR3_IODELAY_MIG0 - type: string + Parameter IODELAY_GRP1 bound to: ARTY_DDR3_IODELAY_MIG1 - type: string + Parameter FPGA_SPEED_GRADE bound to: 1 - type: integer + Parameter OUTPUT_DRV bound to: LOW - type: string + Parameter REG_CTRL bound to: OFF - type: string + Parameter RTT_NOM bound to: 40 - type: string + Parameter RTT_WR bound to: OFF - type: string + Parameter STARVE_LIMIT bound to: 2 - type: integer + Parameter tCK bound to: 3000 - type: integer + Parameter tCKE bound to: 5625 - type: integer + Parameter tFAW bound to: 45000 - type: integer + Parameter tPRDI bound to: 1000000 - type: integer + Parameter tRAS bound to: 36000 - type: integer + Parameter tRCD bound to: 13500 - type: integer + Parameter tREFI bound to: 7800000 - type: integer + Parameter tRFC bound to: 160000 - type: integer + Parameter tRP bound to: 13500 - type: integer + Parameter tRRD bound to: 7500 - type: integer + Parameter tRTP bound to: 7500 - type: integer + Parameter tWTR bound to: 7500 - type: integer + Parameter tZQI bound to: 128000000 - type: integer + Parameter tZQCS bound to: 64 - type: integer + Parameter USER_REFRESH bound to: OFF - type: string + Parameter TEMP_MON_EN bound to: ON - type: string + Parameter WRLVL bound to: ON - type: string + Parameter DEBUG_PORT bound to: OFF - type: string + Parameter CAL_WIDTH bound to: HALF - type: string + Parameter RANK_WIDTH bound to: 1 - type: integer + Parameter RANKS bound to: 1 - type: integer + Parameter ODT_WIDTH bound to: 1 - type: integer + Parameter ROW_WIDTH bound to: 14 - type: integer + Parameter ADDR_WIDTH bound to: 28 - type: integer + Parameter APP_MASK_WIDTH bound to: 16 - type: integer + Parameter APP_DATA_WIDTH bound to: 128 - type: integer + Parameter BYTE_LANES_B0 bound to: 4'b1111 + Parameter BYTE_LANES_B1 bound to: 4'b0000 + Parameter BYTE_LANES_B2 bound to: 4'b0000 + Parameter BYTE_LANES_B3 bound to: 4'b0000 + Parameter BYTE_LANES_B4 bound to: 4'b0000 + Parameter DATA_CTL_B0 bound to: 4'b1100 + Parameter DATA_CTL_B1 bound to: 4'b0000 + Parameter DATA_CTL_B2 bound to: 4'b0000 + Parameter DATA_CTL_B3 bound to: 4'b0000 + Parameter DATA_CTL_B4 bound to: 4'b0000 + Parameter PHY_0_BITLANES bound to: 48'b001111111110001111111110111111111111101111111111 + Parameter PHY_1_BITLANES bound to: 48'b000000000000000000000000000000000000000000000000 + Parameter PHY_2_BITLANES bound to: 48'b000000000000000000000000000000000000000000000000 + Parameter CK_BYTE_MAP bound to: 144'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter ADDR_MAP bound to: 192'b000000000000000000000000000000000000000000000010000000000100000000001001000000000111000000000001000000000101000000000110000000000011000000010000000000010010000000010100000000010001000000011010 + Parameter BANK_MAP bound to: 36'b000000011011000000010111000000010011 + Parameter CAS_MAP bound to: 12'b000000010101 + Parameter CKE_ODT_BYTE_MAP bound to: 8'b00000000 + Parameter CKE_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011001 + Parameter ODT_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000 + Parameter CKE_ODT_AUX bound to: FALSE - type: string + Parameter CS_MAP bound to: 120'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001011 + Parameter PARITY_MAP bound to: 12'b000000000000 + Parameter RAS_MAP bound to: 12'b000000010110 + Parameter WE_MAP bound to: 12'b000000011000 + Parameter DQS_BYTE_MAP bound to: 144'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000011 + Parameter DATA0_MAP bound to: 96'b000000110100000000110010000000111000000000110101000000110001000000110111000000110110000000110011 + Parameter DATA1_MAP bound to: 96'b000000100011000000100110000000100010000000101000000000100101000000100111000000100001000000100100 + Parameter DATA2_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA3_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA4_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA5_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA6_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA7_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA8_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA9_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA10_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA11_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA12_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA13_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA14_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA15_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA16_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA17_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter MASK0_MAP bound to: 108'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101001000000111001 + Parameter MASK1_MAP bound to: 108'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter SLOT_0_CONFIG bound to: 8'b00000001 + Parameter SLOT_1_CONFIG bound to: 8'b00000000 + Parameter MEM_ADDR_ORDER bound to: BANK_ROW_COLUMN - type: string + Parameter CALIB_ROW_ADD bound to: 16'b0000000000000000 + Parameter CALIB_COL_ADD bound to: 12'b000000000000 + Parameter CALIB_BA_ADD bound to: 3'b000 + Parameter SIM_BYPASS_INIT_CAL bound to: OFF - type: string + Parameter REFCLK_FREQ bound to: 200.000000 - type: double + Parameter USE_CS_PORT bound to: 1 - type: integer + Parameter USE_DM_PORT bound to: 1 - type: integer + Parameter USE_ODT_PORT bound to: 1 - type: integer + Parameter IDELAY_ADJ bound to: OFF - type: string + Parameter FINE_PER_BIT bound to: OFF - type: string + Parameter CENTER_COMP_MODE bound to: OFF - type: string + Parameter PI_VAL_ADJ bound to: OFF - type: string + Parameter SKIP_CALIB bound to: FALSE - type: string + Parameter TAPSPERKCLK bound to: 112 - type: integer + Parameter C_S_AXI_ID_WIDTH bound to: 4 - type: integer + Parameter C_S_AXI_ADDR_WIDTH bound to: 28 - type: integer + Parameter C_S_AXI_DATA_WIDTH bound to: 128 - type: integer + Parameter C_S_AXI_SUPPORTS_NARROW_BURST bound to: 0 - type: integer + Parameter C_RD_WR_ARB_ALGORITHM bound to: RD_PRI_REG - type: string + Parameter C_S_AXI_REG_EN0 bound to: 20'b00000000000000000000 + Parameter C_S_AXI_REG_EN1 bound to: 20'b00000000000000000000 + Parameter C_S_AXI_CTRL_ADDR_WIDTH bound to: 32 - type: integer + Parameter C_S_AXI_CTRL_DATA_WIDTH bound to: 32 - type: integer + Parameter C_S_AXI_BASEADDR bound to: 0 - type: integer + Parameter C_ECC_ONOFF_RESET_VALUE bound to: 1 - type: integer + Parameter C_ECC_CE_COUNTER_WIDTH bound to: 8 - type: integer + Parameter FPGA_VOLT_TYPE bound to: N - type: string +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_mem_intfc' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_mem_intfc.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_mc' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v:73] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_rank_mach' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_mach.v:71] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_rank_cntrl' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v:79] +INFO: [Synth 8-6157] synthesizing module 'SRLC32E' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:137412] +INFO: [Synth 8-6155] done synthesizing module 'SRLC32E' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:137412] +WARNING: [Synth 8-567] referenced signal 'periodic_rd_generation.periodic_rd_timer_one' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v:509] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_rank_cntrl' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v:79] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_rank_common' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_common.v:72] +WARNING: [Synth 8-567] referenced signal 'zq_cntrl.zq_tick' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_common.v:172] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_round_robin_arb' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_round_robin_arb' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_round_robin_arb__parameterized0' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_round_robin_arb__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_rank_common' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_common.v:72] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_rank_mach' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_mach.v:71] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_mach' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_mach.v:72] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_compare' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v:74] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_compare' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v:74] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_state' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_queue' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_cntrl' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized0' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state__parameterized0' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_state__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue__parameterized0' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_queue__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state__parameterized1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_state__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue__parameterized1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_queue__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized2' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state__parameterized2' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_state__parameterized2' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue__parameterized2' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_queue__parameterized2' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized2' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_common' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_common.v:73] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_common' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_common.v:73] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_arb_mux' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_mux.v:69] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_arb_row_col' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v:83] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_round_robin_arb__parameterized1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_round_robin_arb__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_arb_row_col' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v:83] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_arb_select' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:75] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_arb_select' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:75] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_arb_mux' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_mux.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_mach' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_mach.v:72] +WARNING: [Synth 8-7071] port 'idle' of module 'mig_7series_v4_2_bank_mach' is unconnected for instance 'bank_mach0' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v:670] +WARNING: [Synth 8-7023] instance 'bank_mach0' of module 'mig_7series_v4_2_bank_mach' has 74 connections declared, but only 73 given [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v:670] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_col_mach' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_col_mach.v:88] +INFO: [Synth 8-6157] synthesizing module 'RAM32M' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:129077] +INFO: [Synth 8-6155] done synthesizing module 'RAM32M' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:129077] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_col_mach' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_col_mach.v:88] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_mc' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v:73] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_top' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_top.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_mc_phy_wrapper' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:71] +INFO: [Synth 8-6157] synthesizing module 'OBUF' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96458] +INFO: [Synth 8-6155] done synthesizing module 'OBUF' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96458] +INFO: [Synth 8-6157] synthesizing module 'OBUFT' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96846] +INFO: [Synth 8-6155] done synthesizing module 'OBUFT' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96846] +INFO: [Synth 8-6157] synthesizing module 'IOBUF_INTERMDISABLE' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:79002] +INFO: [Synth 8-6155] done synthesizing module 'IOBUF_INTERMDISABLE' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:79002] +INFO: [Synth 8-6157] synthesizing module 'IOBUFDS_INTERMDISABLE' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:78516] +INFO: [Synth 8-6155] done synthesizing module 'IOBUFDS_INTERMDISABLE' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:78516] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +WARNING: [Synth 8-7071] port 'afull' of module 'mig_7series_v4_2_ddr_of_pre_fifo' is unconnected for instance 'phy_ctl_pre_fifo_0' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1428] +WARNING: [Synth 8-7023] instance 'phy_ctl_pre_fifo_0' of module 'mig_7series_v4_2_ddr_of_pre_fifo' has 8 connections declared, but only 7 given [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1428] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo__parameterized0' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +WARNING: [Synth 8-7071] port 'afull' of module 'mig_7series_v4_2_ddr_of_pre_fifo' is unconnected for instance 'phy_ctl_pre_fifo_1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1445] +WARNING: [Synth 8-7023] instance 'phy_ctl_pre_fifo_1' of module 'mig_7series_v4_2_ddr_of_pre_fifo' has 8 connections declared, but only 7 given [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1445] +WARNING: [Synth 8-7071] port 'afull' of module 'mig_7series_v4_2_ddr_of_pre_fifo' is unconnected for instance 'phy_ctl_pre_fifo_2' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1462] +WARNING: [Synth 8-7023] instance 'phy_ctl_pre_fifo_2' of module 'mig_7series_v4_2_ddr_of_pre_fifo' has 8 connections declared, but only 7 given [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1462] +WARNING: [Synth 8-5974] attribute "use_dsp48" has been deprecated, please use "use_dsp" instead +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_mc_phy' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_4lanes' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:72] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo__parameterized1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +INFO: [Synth 8-6157] synthesizing module 'ODDR' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100102] +INFO: [Synth 8-6155] done synthesizing module 'ODDR' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100102] +INFO: [Synth 8-6157] synthesizing module 'OBUFDS' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96472] +INFO: [Synth 8-6155] done synthesizing module 'OBUFDS' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96472] +INFO: [Synth 8-6157] synthesizing module 'PHASER_OUT_PHY' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114573] +INFO: [Synth 8-6155] done synthesizing module 'PHASER_OUT_PHY' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114573] +INFO: [Synth 8-6157] synthesizing module 'OUT_FIFO' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100824] +INFO: [Synth 8-6155] done synthesizing module 'OUT_FIFO' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100824] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_group_io' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6157] synthesizing module 'OSERDESE2' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6155] done synthesizing module 'OSERDESE2' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_group_io' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized0' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized0' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_if_post_fifo' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v:68] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v:110] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_if_post_fifo' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v:68] +INFO: [Synth 8-6157] synthesizing module 'PHASER_IN_PHY' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114436] +INFO: [Synth 8-6155] done synthesizing module 'PHASER_IN_PHY' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114436] +INFO: [Synth 8-6157] synthesizing module 'IN_FIFO' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:78141] +INFO: [Synth 8-6155] done synthesizing module 'IN_FIFO' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:78141] +INFO: [Synth 8-6157] synthesizing module 'PHASER_OUT_PHY__parameterized0' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114573] +INFO: [Synth 8-6155] done synthesizing module 'PHASER_OUT_PHY__parameterized0' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114573] +INFO: [Synth 8-6157] synthesizing module 'OUT_FIFO__parameterized0' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100824] +INFO: [Synth 8-6155] done synthesizing module 'OUT_FIFO__parameterized0' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100824] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6157] synthesizing module 'IDELAYE2' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:75752] +INFO: [Synth 8-6155] done synthesizing module 'IDELAYE2' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:75752] +INFO: [Synth 8-6157] synthesizing module 'ISERDESE2' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:80773] +INFO: [Synth 8-6155] done synthesizing module 'ISERDESE2' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:80773] +INFO: [Synth 8-6157] synthesizing module 'OSERDESE2__parameterized0' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6155] done synthesizing module 'OSERDESE2__parameterized0' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6157] synthesizing module 'OSERDESE2__parameterized1' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6155] done synthesizing module 'OSERDESE2__parameterized1' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized2' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized2' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'BUFIO' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:2224] +INFO: [Synth 8-6155] done synthesizing module 'BUFIO' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:2224] +INFO: [Synth 8-6157] synthesizing module 'PHY_CONTROL' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114664] +INFO: [Synth 8-6155] done synthesizing module 'PHY_CONTROL' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114664] +INFO: [Synth 8-226] default block is never used [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:1557] +INFO: [Synth 8-6157] synthesizing module 'PHASER_REF' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114648] +INFO: [Synth 8-6155] done synthesizing module 'PHASER_REF' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114648] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_4lanes' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:72] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_mc_phy' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy.v:70] +WARNING: [Synth 8-689] width (12) of port connection 'pi_dqs_found_lanes' does not match port width (4) of module 'mig_7series_v4_2_ddr_mc_phy' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1671] +WARNING: [Synth 8-689] width (12) of port connection 'pi_phase_locked_lanes' does not match port width (4) of module 'mig_7series_v4_2_ddr_mc_phy' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1679] +WARNING: [Synth 8-7071] port 'of_data_a_full' of module 'mig_7series_v4_2_ddr_mc_phy' is unconnected for instance 'u_ddr_mc_phy' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1579] +WARNING: [Synth 8-7023] instance 'u_ddr_mc_phy' of module 'mig_7series_v4_2_ddr_mc_phy' has 89 connections declared, but only 88 given [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1579] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_mc_phy_wrapper' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:71] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_calib_top' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:82] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_wrlvl' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:90] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:797] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_wrlvl' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:90] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v:68] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v:68] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_dqs_found_cal_hr' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:79] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_dqs_found_cal_hr' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:79] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_rdlvl' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:79] +WARNING: [Synth 8-5974] attribute "use_dsp48" has been deprecated, please use "use_dsp" instead +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2746] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_rdlvl' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:79] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_prbs_gen' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:92] +WARNING: [Synth 8-7186] Applying attribute ram_style = "distributed" is ignored, object 'rd_addr' is not inferred as ram due to incorrect usage [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:203] +WARNING: [Synth 8-7186] Applying attribute ram_style = "distributed" is ignored, object 'mem_out' is not inferred as ram due to incorrect usage [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:205] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_prbs_gen' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:92] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_init' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:89] +INFO: [Synth 8-226] default block is never used [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:5273] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_init' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:89] +WARNING: [Synth 8-7071] port 'complex_oclk_prech_req' of module 'mig_7series_v4_2_ddr_phy_init' is unconnected for instance 'u_ddr_phy_init' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:1367] +WARNING: [Synth 8-7023] instance 'u_ddr_phy_init' of module 'mig_7series_v4_2_ddr_phy_init' has 131 connections declared, but only 130 given [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:1367] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_wrcal' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:77] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:1130] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_wrcal' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:77] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_tempmon' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_tempmon' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_calib_top' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:82] +WARNING: [Synth 8-689] width (12) of port connection 'pi_dqs_found_lanes' does not match port width (4) of module 'mig_7series_v4_2_ddr_calib_top' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_top.v:1340] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_top' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_top.v:70] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_mem_intfc' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_mem_intfc.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ui_top' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_top.v:71] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ui_cmd' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_cmd.v:70] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ui_cmd' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_cmd.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ui_wr_data' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v:131] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v:342] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v:380] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ui_wr_data' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v:131] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ui_rd_data' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:140] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:406] +WARNING: [Synth 8-567] referenced signal 'not_strict_mode.occ_cnt_r' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403] +WARNING: [Synth 8-567] referenced signal 'not_strict_mode.free_rd_buf' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403] +WARNING: [Synth 8-567] referenced signal 'not_strict_mode.occ_minus_one' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403] +WARNING: [Synth 8-567] referenced signal 'not_strict_mode.occ_plus_one' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403] +WARNING: [Synth 8-567] referenced signal 'not_strict_mode.rd_data_buf_addr_r_lcl' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:432] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ui_rd_data' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:140] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ui_top' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_top.v:71] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_axi_mc' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc.v:90] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_axi_register_slice' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axi_register_slice.v:63] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized0' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized2' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized2' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_axi_register_slice' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axi_register_slice.v:63] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_axi_mc_aw_channel' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_aw_channel.v:57] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_axi_mc_cmd_translator' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_cmd_translator.v:62] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_axi_mc_incr_cmd' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_incr_cmd.v:64] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_incr_cmd' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_incr_cmd.v:64] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_axi_mc_wrap_cmd' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wrap_cmd.v:97] +INFO: [Common 17-14] Message 'Synth 8-6157' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_wrap_cmd' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wrap_cmd.v:97] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_cmd_translator' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_cmd_translator.v:62] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_wr_cmd_fsm' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wr_cmd_fsm.v:76] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_aw_channel' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_aw_channel.v:57] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_w_channel' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_w_channel.v:64] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_fifo' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_fifo.v:70] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_b_channel' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_b_channel.v:83] +INFO: [Common 17-14] Message 'Synth 8-6155' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [Synth 8-589] replacing case/wildcard equality operator === with logical equality operator == [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_r_channel.v:189] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_r_channel.v:315] +WARNING: [Synth 8-3848] Net ui_addn_clk_0 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:140] +WARNING: [Synth 8-3848] Net ui_addn_clk_1 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:141] +WARNING: [Synth 8-3848] Net ui_addn_clk_2 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:142] +WARNING: [Synth 8-3848] Net ui_addn_clk_3 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:143] +WARNING: [Synth 8-3848] Net ui_addn_clk_4 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:144] +WARNING: [Synth 8-6014] Unused sequential element periodic_rd_generation.read_this_rank_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v:487] +WARNING: [Synth 8-3936] Found unconnected internal register 'dbl_req_reg' and it is trimmed from '6' to '5' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:145] +WARNING: [Synth 8-3936] Found unconnected internal register 'dbl_last_master_ns_reg' and it is trimmed from '6' to '4' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:143] +WARNING: [Synth 8-6014] Unused sequential element last_master_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:181] +WARNING: [Synth 8-3848] Net channel[0].inh_group in module/entity mig_7series_v4_2_round_robin_arb__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:153] +WARNING: [Synth 8-3936] Found unconnected internal register 'col_addr_template_reg' and it is trimmed from '16' to '14' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v:251] +WARNING: [Synth 8-3936] Found unconnected internal register 'dbl_req_reg' and it is trimmed from '8' to '7' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:145] +WARNING: [Synth 8-3936] Found unconnected internal register 'dbl_last_master_ns_reg' and it is trimmed from '8' to '6' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:143] +WARNING: [Synth 8-6014] Unused sequential element sent_row_or_maint_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v:357] +WARNING: [Synth 8-6014] Unused sequential element mc_aux_out_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:680] +WARNING: [Synth 8-6014] Unused sequential element mc_aux_out_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:681] +WARNING: [Synth 8-3848] Net col_mux.col_row_r in module/entity mig_7series_v4_2_arb_select does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:390] +WARNING: [Synth 8-3936] Found unconnected internal register 'read_fifo.fifo_out_data_r_reg' and it is trimmed from '12' to '8' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_col_mach.v:396] +WARNING: [Synth 8-3848] Net oserdes_dqts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:143] +WARNING: [Synth 8-3848] Net oserdes_dqs_buf in module/entity mig_7series_v4_2_ddr_byte_group_io does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:144] +WARNING: [Synth 8-3848] Net oserdes_dqsts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:145] +WARNING: [Synth 8-3848] Net iserdes_dout in module/entity mig_7series_v4_2_ddr_byte_group_io does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:92] +WARNING: [Synth 8-6014] Unused sequential element ififo_rst_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:307] +WARNING: [Synth 8-3848] Net rclk in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:147] +WARNING: [Synth 8-3848] Net pi_iserdes_rst in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:193] +WARNING: [Synth 8-3848] Net pi_fine_overflow in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:195] +WARNING: [Synth 8-3848] Net pi_counter_read_val_w in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:431] +WARNING: [Synth 8-3848] Net dqs_out_of_range in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:198] +WARNING: [Synth 8-3848] Net iserdes_clk in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:275] +WARNING: [Synth 8-3848] Net iserdes_clkdiv in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:276] +WARNING: [Synth 8-3848] Net oserdes_dqts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:143] +WARNING: [Synth 8-3848] Net oserdes_dqs_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:144] +WARNING: [Synth 8-3848] Net oserdes_dqsts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:145] +WARNING: [Synth 8-3848] Net iserdes_dout in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:92] +WARNING: [Synth 8-6014] Unused sequential element ififo_rst_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:307] +WARNING: [Synth 8-3848] Net rclk in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:147] +WARNING: [Synth 8-3848] Net pi_iserdes_rst in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:193] +WARNING: [Synth 8-3848] Net pi_fine_overflow in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:195] +WARNING: [Synth 8-3848] Net pi_counter_read_val_w in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:431] +WARNING: [Synth 8-3848] Net dqs_out_of_range in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:198] +WARNING: [Synth 8-3848] Net iserdes_clk in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:275] +WARNING: [Synth 8-3848] Net iserdes_clkdiv in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:276] +WARNING: [Synth 8-6014] Unused sequential element fine_delay_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:185] +WARNING: [Synth 8-3848] Net dummy_i5 in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized1 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:269] +WARNING: [Synth 8-3848] Net dummy_i6 in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized1 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:270] +WARNING: [Synth 8-3848] Net dummy_i5 in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized2 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:269] +WARNING: [Synth 8-3848] Net dummy_i6 in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized2 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:270] +WARNING: [Synth 8-6014] Unused sequential element B_rst_primitives_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:737] +WARNING: [Synth 8-6014] Unused sequential element C_rst_primitives_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:738] +WARNING: [Synth 8-6014] Unused sequential element D_rst_primitives_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:739] +WARNING: [Synth 8-3936] Found unconnected internal register 'byte_sel_data_map_reg' and it is trimmed from '96' to '88' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:731] +WARNING: [Synth 8-3848] Net phy_data_full in module/entity mig_7series_v4_2_ddr_mc_phy_wrapper does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:227] +WARNING: [Synth 8-6014] Unused sequential element fast_cal_fine_cnt_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:790] +WARNING: [Synth 8-6014] Unused sequential element fast_cal_coarse_cnt_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:791] +WARNING: [Synth 8-6014] Unused sequential element final_corse_dec_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:792] +WARNING: [Synth 8-6014] Unused sequential element add_smallest_reg[1] was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:516] +WARNING: [Synth 8-6014] Unused sequential element add_largest_reg[0] was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:517] +WARNING: [Synth 8-6014] Unused sequential element add_largest_reg[1] was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:517] +WARNING: [Synth 8-6014] Unused sequential element dqs_wl_po_en_stg2_c_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:628] +WARNING: [Synth 8-6014] Unused sequential element po_en_stg2_c_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v:162] +WARNING: [Synth 8-6014] Unused sequential element rank_final_loop[0].final_do_max_reg[0] was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:1116] +WARNING: [Synth 8-6014] Unused sequential element rank_final_loop[0].final_do_index_reg[0] was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:1146] +WARNING: [Synth 8-6014] Unused sequential element dqsfound_retry_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:690] +WARNING: [Synth 8-3848] Net dqsfound_retry_done in module/entity mig_7series_v4_2_ddr_phy_dqs_found_cal_hr does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:131] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[0].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[1].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[2].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[3].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[4].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[5].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[6].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[7].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_stg1_done_int_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:686] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_stg1_done_int_r2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:687] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_stg1_done_int_r3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:688] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_last_byte_done_int_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:689] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_last_byte_done_int_r2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:690] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_last_byte_done_int_r3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:691] +WARNING: [Synth 8-6014] Unused sequential element fine_dly_dec_done_r3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:940] +WARNING: [Synth 8-6014] Unused sequential element fine_dly_dec_done_r4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:941] +WARNING: [Synth 8-6014] Unused sequential element regl_rank_done_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:1044] +WARNING: [Synth 8-6014] Unused sequential element cal1_state_r2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2696] +WARNING: [Synth 8-6014] Unused sequential element cal1_state_r3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2697] +WARNING: [Synth 8-6014] Unused sequential element cal1_cnt_cpt_timing_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:610] +WARNING: [Synth 8-6014] Unused sequential element sample_cnt_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:156] +WARNING: [Synth 8-6014] Unused sequential element reseed_prbs_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:157] +WARNING: [Synth 8-6014] Unused sequential element lfsr_q_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:174] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.phy_tmp_cs1_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4271] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.phy_tmp_odt_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4273] +WARNING: [Synth 8-6014] Unused sequential element wrlvl_final_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1421] +WARNING: [Synth 8-6014] Unused sequential element wrlvl_rank_cntr_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1539] +WARNING: [Synth 8-6014] Unused sequential element cnt_pwron_cke_done_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1781] +WARNING: [Synth 8-6014] Unused sequential element cnt_init_pre_wait_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1814] +WARNING: [Synth 8-6014] Unused sequential element cnt_init_pre_wait_done_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1815] +WARNING: [Synth 8-6014] Unused sequential element rnk_ref_cnt_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1941] +WARNING: [Synth 8-6014] Unused sequential element read_calib_int_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:2720] +WARNING: [Synth 8-6014] Unused sequential element read_calib_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:2727] +WARNING: [Synth 8-6014] Unused sequential element pi_dqs_found_rank_done_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:2778] +WARNING: [Synth 8-6014] Unused sequential element pi_dqs_found_all_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:2783] +WARNING: [Synth 8-6014] Unused sequential element complex_row0_rd_done_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:3339] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_wr_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:3632] +WARNING: [Synth 8-6014] Unused sequential element extend_cal_pat_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:3638] +WARNING: [Synth 8-6014] Unused sequential element cnt_init_data_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:3714] +WARNING: [Synth 8-6014] Unused sequential element victim_byte_cnt_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:818] +WARNING: [Synth 8-3936] Found unconnected internal register 'rdlvl_start_dly0_r_reg' and it is trimmed from '16' to '15' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1228] +WARNING: [Synth 8-3936] Found unconnected internal register 'wrcal_start_dly_r_reg' and it is trimmed from '16' to '15' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1230] +WARNING: [Synth 8-3936] Found unconnected internal register 'oclkdelay_start_dly_r_reg' and it is trimmed from '16' to '15' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1232] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr2_r_reg[1] was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4265] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr2_r_reg[2] was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4265] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr2_r_reg[3] was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4265] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr1_r_reg[1] was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4268] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr1_r_reg[2] was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4268] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr1_r_reg[3] was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4268] +WARNING: [Synth 8-6014] Unused sequential element prech_done_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1303] +WARNING: [Synth 8-6014] Unused sequential element calib_cmd_wren_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4229] +WARNING: [Synth 8-3848] Net calib_aux_out in module/entity mig_7series_v4_2_ddr_phy_init does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:276] +WARNING: [Synth 8-6014] Unused sequential element rd_active_r4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:534] +WARNING: [Synth 8-6014] Unused sequential element rd_active_r5_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:535] +WARNING: [Synth 8-6014] Unused sequential element pat1_detect_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:1124] +WARNING: [Synth 8-6014] Unused sequential element early1_detect_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:1125] +WARNING: [Synth 8-6014] Unused sequential element rd_mux_sel_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:438] +WARNING: [Synth 8-3848] Net i in module/entity mig_7series_v4_2_ddr_phy_wrcal does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:155] +WARNING: [Synth 8-6014] Unused sequential element calib_complete_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v:182] +WARNING: [Synth 8-6014] Unused sequential element sample_en_cnt_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v:188] +WARNING: [Synth 8-6014] Unused sequential element device_temp_capture_102_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v:290] +WARNING: [Synth 8-6014] Unused sequential element tempmon_sel_pi_incdec_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:883] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:898] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:899] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:900] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:901] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r5_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:902] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r6_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:903] +WARNING: [Synth 8-6014] Unused sequential element skip_calib_tap_off.skip_cal_tempmon_samp_en_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:2262] +WARNING: [Synth 8-6014] Unused sequential element wrlvl_final_mux_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:834] +WARNING: [Synth 8-3848] Net dbg_skip_cal in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:673] +WARNING: [Synth 8-3848] Net coarse_dec_err in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:662] +WARNING: [Synth 8-3848] Net dbg_poc in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:335] +WARNING: [Synth 8-3848] Net fine_delay_incdec_pb in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:341] +WARNING: [Synth 8-3848] Net fine_delay_sel in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:342] +WARNING: [Synth 8-3848] Net lim_done in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:620] +WARNING: [Synth 8-3848] Net lim2init_write_request in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:619] +WARNING: [Synth 8-3848] Net complex_ocal_num_samples_done_r in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:533] +WARNING: [Synth 8-3848] Net complex_ocal_rd_victim_sel in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:534] +WARNING: [Synth 8-3848] Net complex_victim_inc in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:592] +WARNING: [Synth 8-3848] Net rd_victim_sel in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:588] +WARNING: [Synth 8-3848] Net oclkdelay_center_calib_start in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:597] +WARNING: [Synth 8-3848] Net oclk_center_write_resume in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:615] +WARNING: [Synth 8-3848] Net oclkdelay_center_calib_done in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:616] +WARNING: [Synth 8-6014] Unused sequential element app_wdf_rdy_r_copy4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v:268] +WARNING: [Synth 8-6014] Unused sequential element int_next_pending_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_incr_cmd.v:191] +WARNING: [Synth 8-6014] Unused sequential element sel_first_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_incr_cmd.v:220] +WARNING: [Synth 8-6014] Unused sequential element int_next_pending_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wrap_cmd.v:221] +WARNING: [Synth 8-6014] Unused sequential element sel_first_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wrap_cmd.v:239] +WARNING: [Synth 8-3848] Net cmd_wr_bytes in module/entity mig_7series_v4_2_axi_mc_w_channel does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_w_channel.v:96] +WARNING: [Synth 8-6014] Unused sequential element rd_last_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_r_channel.v:216] +WARNING: [Synth 8-3848] Net error in module/entity mig_7series_v4_2_memc_ui_top_axi does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_memc_ui_top_axi.v:555] +WARNING: [Synth 8-3848] Net app_correct_en_i in module/entity mig_7series_v4_2_memc_ui_top_axi does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_memc_ui_top_axi.v:500] +WARNING: [Synth 8-3848] Net s_axi_ctrl_awvalid in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:754] +WARNING: [Synth 8-3848] Net s_axi_ctrl_awaddr in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:756] +WARNING: [Synth 8-3848] Net s_axi_ctrl_wvalid in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:758] +WARNING: [Synth 8-3848] Net s_axi_ctrl_wdata in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:760] +WARNING: [Synth 8-3848] Net s_axi_ctrl_bready in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:763] +WARNING: [Synth 8-3848] Net s_axi_ctrl_arvalid in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:766] +WARNING: [Synth 8-3848] Net s_axi_ctrl_araddr in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:768] +WARNING: [Synth 8-3848] Net s_axi_ctrl_rready in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:771] +WARNING: [Synth 8-3848] Net device_temp_i in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:784] +WARNING: [Synth 8-7129] Port mc_app_rd_last in module mig_7series_v4_2_axi_mc_r_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port axlen[7] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axlen[6] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axlen[5] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axlen[4] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[2] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[1] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[0] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[2] in module mig_7series_v4_2_axi_mc_incr_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[1] in module mig_7series_v4_2_axi_mc_incr_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[0] in module mig_7series_v4_2_axi_mc_incr_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axburst[0] in module mig_7series_v4_2_axi_mc_cmd_translator is either unconnected or has no load +WARNING: [Synth 8-7129] Port arlock[1] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arlock[0] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arcache[3] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arcache[2] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arcache[1] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arcache[0] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arprot[2] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arprot[1] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arprot[0] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port b_resp_rdy in module mig_7series_v4_2_axi_mc_b_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port cmd_wr_bytes in module mig_7series_v4_2_axi_mc_w_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awvalid in module mig_7series_v4_2_axi_mc_w_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port w_ignore_begin in module mig_7series_v4_2_axi_mc_w_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port w_ignore_end in module mig_7series_v4_2_axi_mc_w_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awlock[1] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awlock[0] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awcache[3] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awcache[2] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awcache[1] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awcache[0] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awprot[2] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awprot[1] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awprot[0] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port cmd_wr_bytes in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice__parameterized1 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice__parameterized1 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice__parameterized0 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice__parameterized0 is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_AWUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_WUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_ARUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port M_AXI_BUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port M_AXI_RUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[7] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[6] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[5] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[4] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[3] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[2] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[1] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[0] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[7] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[6] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[5] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[4] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[3] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[2] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[1] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[0] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[7] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[6] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[5] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[4] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[3] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[2] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[1] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[0] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port wr_data_addr[4] in module mig_7series_v4_2_ui_top is either unconnected or has no load +WARNING: [Synth 8-7129] Port accept in module mig_7series_v4_2_ui_top is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[11] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[10] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[9] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[8] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[7] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[6] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[5] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[4] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[3] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[2] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[1] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[0] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[99] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[98] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[97] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[96] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[95] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[94] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[93] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[16] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[15] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[14] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[12] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[11] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[10] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2909.984 ; gain = 669.223 ; free physical = 491527 ; free virtual = 627929 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2909.984 ; gain = 669.223 ; free physical = 491535 ; free virtual = 627937 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2909.984 ; gain = 669.223 ; free physical = 491535 ; free virtual = 627937 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.2 . Memory (MB): peak = 2909.984 ; gain = 0.000 ; free physical = 491540 ; free virtual = 627942 +INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3_ooc.xdc] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3_ooc.xdc] +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] +WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc:346] +WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc:353] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/arty_ddr3_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/arty_ddr3_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +INFO: [Timing 38-2] Deriving generated clocks +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.828 ; gain = 0.000 ; free physical = 491553 ; free virtual = 627970 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 70 instances were transformed. + IOBUFDS_INTERMDISABLE => IOBUFDS_INTERMDISABLE (IBUFDS_INTERMDISABLE_INT(x2), INV, OBUFTDS(x2)): 2 instances + IOBUF_INTERMDISABLE => IOBUF_INTERMDISABLE (IBUF_INTERMDISABLE, OBUFT): 16 instances + OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 1 instance + RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 51 instances + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3019.828 ; gain = 0.000 ; free physical = 491557 ; free virtual = 627975 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 3019.828 ; gain = 779.066 ; free physical = 491702 ; free virtual = 628120 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a100tcsg324-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 3027.832 ; gain = 787.070 ; free physical = 491702 ; free virtual = 628120 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_ck_n[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc, line 27). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_ck_p[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc, line 28). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 3027.832 ; gain = 787.070 ; free physical = 491707 ; free virtual = 628125 +--------------------------------------------------------------------------------- +INFO: [Synth 8-802] inferred FSM for state register 'xadc_supplied_temperature.tempmon_state_reg' in module 'mig_7series_v4_2_tempmon' +INFO: [Synth 8-802] inferred FSM for state register 'wl_state_r_reg' in module 'mig_7series_v4_2_ddr_phy_wrlvl' +INFO: [Synth 8-802] inferred FSM for state register 'fine_adj_state_r_reg' in module 'mig_7series_v4_2_ddr_phy_dqs_found_cal_hr' +INFO: [Synth 8-802] inferred FSM for state register 'cal1_state_r_reg' in module 'mig_7series_v4_2_ddr_phy_rdlvl' +INFO: [Synth 8-802] inferred FSM for state register 'tempmon_state_reg' in module 'mig_7series_v4_2_ddr_phy_tempmon' +INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'mig_7series_v4_2_axi_mc_r_channel' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + INIT_IDLE | 0001 | 000 + REQUEST_READ_TEMP | 1000 | 001 + WAIT_FOR_READ | 0100 | 010 + READ | 0010 | 011 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'xadc_supplied_temperature.tempmon_state_reg' using encoding 'one-hot' in module 'mig_7series_v4_2_tempmon' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + WL_IDLE | 01110 | 00000 + WL_INIT | 10010 | 00001 + WL_INIT_FINE_INC | 01100 | 00010 + WL_INIT_FINE_INC_WAIT1 | 01000 | 00011 + WL_INIT_FINE_INC_WAIT | 01001 | 00100 + WL_INIT_FINE_DEC | 11001 | 00101 + WL_INIT_FINE_DEC_WAIT1 | 10111 | 11001 + WL_INIT_FINE_DEC_WAIT | 11000 | 00110 + WL_WAIT | 00110 | 01000 + WL_EDGE_CHECK | 11011 | 01001 + WL_DQS_CNT | 10100 | 01011 + WL_FINE_DEC | 00000 | 01110 + WL_FINE_DEC_WAIT1 | 00001 | 11010 + WL_FINE_DEC_WAIT | 10001 | 01111 + WL_CORSE_DEC | 10110 | 10100 + WL_CORSE_DEC_WAIT | 11010 | 10101 + WL_CORSE_DEC_WAIT1 | 10101 | 10110 + WL_2RANK_DQS_CNT | 00010 | 01101 + WL_DQS_CHECK | 00011 | 01010 + WL_FINE_INC | 01101 | 00111 + WL_FINE_INC_WAIT | 10011 | 10111 + WL_2RANK_FINAL_TAP | 01111 | 11000 + WL_CORSE_INC | 01011 | 10000 + WL_CORSE_INC_WAIT_TMP | 10000 | 11011 + WL_CORSE_INC_WAIT | 01010 | 10001 + WL_CORSE_INC_WAIT1 | 00111 | 10010 + WL_CORSE_INC_WAIT2 | 00101 | 10011 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'wl_state_r_reg' using encoding 'sequential' in module 'mig_7series_v4_2_ddr_phy_wrlvl' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + FINE_ADJ_IDLE | 0000 | 0000 + RST_WAIT | 0001 | 0011 + FINE_ADJ_DONE | 0010 | 1111 + RST_POSTWAIT | 0011 | 0001 + RST_POSTWAIT1 | 0100 | 0010 + FINE_ADJ_INIT | 0101 | 0100 + FINE_INC | 0110 | 0101 + FINE_INC_WAIT | 0111 | 0110 + FINE_INC_PREWAIT | 1000 | 0111 + DETECT_PREWAIT | 1001 | 1000 + DETECT_DQSFOUND | 1010 | 1001 + FINE_DEC | 1011 | 1011 + FINE_DEC_WAIT | 1100 | 1100 + FINE_DEC_PREWAIT | 1101 | 1101 + FINAL_WAIT | 1110 | 1110 + PRECH_WAIT | 1111 | 1010 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'fine_adj_state_r_reg' using encoding 'sequential' in module 'mig_7series_v4_2_ddr_phy_dqs_found_cal_hr' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + CAL1_IDLE | 00000000000000000000000000010000000 | 000000 + CAL1_NEW_DQS_WAIT | 00000000000000000000010000000000000 | 000001 + CAL1_STORE_FIRST_WAIT | 00000000000000000010000000000000000 | 000010 + CAL1_PAT_DETECT | 00000000000000100000000000000000000 | 000011 + CAL1_DQ_IDEL_TAP_INC | 00000000000000000000000000000000100 | 000100 +CAL1_DQ_IDEL_TAP_INC_WAIT | 00000000000000000000000000000001000 | 000101 + CAL1_MPR_PAT_DETECT | 00000000000000000000000010000000000 | 011111 + CAL1_VALID_WAIT | 10000000000000000000000000000000000 | 011110 + CAL1_DETECT_EDGE | 00000000000001000000000000000000000 | 001000 + CAL1_CALC_IDEL | 00000100000000000000000000000000000 | 001011 + CAL1_CENTER_WAIT | 00000000000000000000000000000000001 | 100010 + CAL1_IDEL_DEC_CPT | 00000000000000000000000000000000010 | 001100 + CAL1_DQ_IDEL_TAP_DEC | 00000000000000000001000000000000000 | 000110 +CAL1_DQ_IDEL_TAP_DEC_WAIT | 00100000000000000000000000000000000 | 000111 + CAL1_NEXT_DQS | 00000000000000000000000000000010000 | 001110 + CAL1_REGL_LOAD | 00000000000000000000000000001000000 | 011011 + CAL1_DONE | 00000000000000000000000000000100000 | 001111 + CAL1_NEW_DQS_PREWAIT | 00000000000000000000000000100000000 | 100000 + CAL1_MPR_NEW_DQS_WAIT | 00000000000000000000000001000000000 | 011101 + CAL1_IDEL_DEC_CPT_WAIT | 00000000000000000000100000000000000 | 001101 + CAL1_RD_STOP_FOR_PI_INC | 00000000000000000000000100000000000 | 100001 + CAL1_IDEL_INC_CPT | 00000000000000000000001000000000000 | 001001 + CAL1_IDEL_INC_CPT_WAIT | 00010000000000000000000000000000000 | 001010 + CAL1_RDLVL_ERR | 00000000000010000000000000000000000 | 011100 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'cal1_state_r_reg' using encoding 'one-hot' in module 'mig_7series_v4_2_ddr_phy_rdlvl' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 00000000001 | 00000000001 + INIT | 00000000010 | 00000000010 + NEUTRAL | 00001000000 | 00001000000 + ONE_DEC | 00010000000 | 00010000000 + TWO_DEC | 00100000000 | 00100000000 + THREE_DEC | 01000000000 | 01000000000 + FOUR_DEC | 10000000000 | 10000000000 + ONE_INC | 00000100000 | 00000100000 + TWO_INC | 00000010000 | 00000010000 + THREE_INC | 00000001000 | 00000001000 + FOUR_INC | 00000000100 | 00000000100 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'tempmon_state_reg' in module 'mig_7series_v4_2_ddr_phy_tempmon' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + ZERO | 11 | 10 + ONE | 01 | 11 + TWO | 00 | 01 + iSTATE | 10 | 00 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'mig_7series_v4_2_axi_mc_r_channel' +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 3027.832 ; gain = 787.070 ; free physical = 491753 ; free virtual = 628175 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 4 Input 32 Bit Adders := 2 + 3 Input 32 Bit Adders := 1 + 2 Input 28 Bit Adders := 2 + 2 Input 13 Bit Adders := 1 + 2 Input 12 Bit Adders := 15 + 2 Input 11 Bit Adders := 1 + 2 Input 10 Bit Adders := 6 + 2 Input 9 Bit Adders := 4 + 2 Input 8 Bit Adders := 8 + 3 Input 7 Bit Adders := 2 + 2 Input 7 Bit Adders := 1 + 2 Input 6 Bit Adders := 30 + 3 Input 6 Bit Adders := 3 + 2 Input 5 Bit Adders := 37 + 2 Input 4 Bit Adders := 34 + 2 Input 3 Bit Adders := 20 + 3 Input 3 Bit Adders := 1 + 2 Input 2 Bit Adders := 51 + 3 Input 2 Bit Adders := 3 + 4 Input 2 Bit Adders := 5 + 5 Input 2 Bit Adders := 1 + 8 Input 2 Bit Adders := 1 + 2 Input 1 Bit Adders := 5 + 3 Input 1 Bit Adders := 1 + 4 Input 1 Bit Adders := 1 + 5 Input 1 Bit Adders := 1 + 6 Input 1 Bit Adders := 1 + 7 Input 1 Bit Adders := 1 + 8 Input 1 Bit Adders := 1 + 9 Input 1 Bit Adders := 1 ++---XORs : + 2 Input 1 Bit XORs := 1 ++---Registers : + 144 Bit Registers := 1 + 128 Bit Registers := 5 + 88 Bit Registers := 1 + 80 Bit Registers := 3 + 56 Bit Registers := 1 + 32 Bit Registers := 3 + 30 Bit Registers := 1 + 28 Bit Registers := 6 + 16 Bit Registers := 13 + 15 Bit Registers := 4 + 14 Bit Registers := 6 + 13 Bit Registers := 1 + 12 Bit Registers := 33 + 11 Bit Registers := 1 + 10 Bit Registers := 4 + 9 Bit Registers := 12 + 8 Bit Registers := 15 + 7 Bit Registers := 5 + 6 Bit Registers := 59 + 5 Bit Registers := 46 + 4 Bit Registers := 82 + 3 Bit Registers := 47 + 2 Bit Registers := 66 + 1 Bit Registers := 1542 ++---Muxes : + 2 Input 128 Bit Muxes := 10 + 4 Input 128 Bit Muxes := 1 + 2 Input 127 Bit Muxes := 1 + 2 Input 80 Bit Muxes := 6 + 2 Input 56 Bit Muxes := 1 + 24 Input 35 Bit Muxes := 1 + 2 Input 35 Bit Muxes := 22 + 2 Input 32 Bit Muxes := 1 + 2 Input 30 Bit Muxes := 12 + 4 Input 30 Bit Muxes := 4 + 2 Input 28 Bit Muxes := 11 + 2 Input 21 Bit Muxes := 8 + 2 Input 16 Bit Muxes := 8 + 3 Input 16 Bit Muxes := 1 + 3 Input 14 Bit Muxes := 1 + 2 Input 14 Bit Muxes := 8 + 4 Input 14 Bit Muxes := 1 + 2 Input 12 Bit Muxes := 5 + 12 Input 11 Bit Muxes := 1 + 2 Input 11 Bit Muxes := 1 + 2 Input 10 Bit Muxes := 7 + 4 Input 9 Bit Muxes := 6 + 2 Input 9 Bit Muxes := 18 + 2 Input 8 Bit Muxes := 61 + 5 Input 8 Bit Muxes := 1 + 2 Input 7 Bit Muxes := 64 + 3 Input 7 Bit Muxes := 1 + 4 Input 7 Bit Muxes := 1 + 5 Input 7 Bit Muxes := 2 + 2 Input 6 Bit Muxes := 81 + 4 Input 6 Bit Muxes := 8 + 27 Input 6 Bit Muxes := 4 + 5 Input 6 Bit Muxes := 2 + 16 Input 6 Bit Muxes := 1 + 24 Input 6 Bit Muxes := 5 + 3 Input 6 Bit Muxes := 2 + 2 Input 5 Bit Muxes := 35 + 8 Input 5 Bit Muxes := 2 + 27 Input 5 Bit Muxes := 1 + 58 Input 5 Bit Muxes := 1 + 24 Input 5 Bit Muxes := 1 + 4 Input 5 Bit Muxes := 2 + 3 Input 5 Bit Muxes := 4 + 2 Input 4 Bit Muxes := 67 + 32 Input 4 Bit Muxes := 1 + 8 Input 4 Bit Muxes := 1 + 7 Input 4 Bit Muxes := 1 + 2 Input 3 Bit Muxes := 69 + 27 Input 3 Bit Muxes := 6 + 3 Input 3 Bit Muxes := 1 + 4 Input 3 Bit Muxes := 3 + 8 Input 3 Bit Muxes := 1 + 2 Input 2 Bit Muxes := 101 + 4 Input 2 Bit Muxes := 7 + 3 Input 2 Bit Muxes := 9 + 8 Input 2 Bit Muxes := 4 + 27 Input 2 Bit Muxes := 1 + 24 Input 2 Bit Muxes := 2 + 5 Input 2 Bit Muxes := 1 + 10 Input 2 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 491 + 3 Input 1 Bit Muxes := 12 + 8 Input 1 Bit Muxes := 4 + 4 Input 1 Bit Muxes := 204 + 27 Input 1 Bit Muxes := 27 + 5 Input 1 Bit Muxes := 1 + 16 Input 1 Bit Muxes := 21 + 24 Input 1 Bit Muxes := 30 + 10 Input 1 Bit Muxes := 17 + 12 Input 1 Bit Muxes := 4 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 240 (col length:80) +BRAMs: 270 (col length: RAMB18 80 RAMB36 40) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +WARNING: [Synth 8-7080] Parallel synthesis criteria is not met +WARNING: [Synth 8-3936] Found unconnected internal register 'byte_sel_data_map_reg' and it is trimmed from '88' to '4' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:731] +WARNING: [Synth 8-3936] Found unconnected internal register 'oclkdelay_start_dly_r_reg' and it is trimmed from '15' to '14' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1232] +WARNING: [Synth 8-3936] Found unconnected internal register 'wrcal_start_dly_r_reg' and it is trimmed from '15' to '14' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1230] +WARNING: [Synth 8-3332] Sequential element (FSM_onehot_cal1_state_r_reg[33]) is unused and will be removed from module mig_7series_v4_2_ddr_phy_rdlvl. +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:15 ; elapsed = 00:01:15 . Memory (MB): peak = 3300.871 ; gain = 1060.109 ; free physical = 492131 ; free virtual = 628560 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +ROM: Preliminary Mapping Report ++------------------------------+------------+---------------+----------------+ +|Module Name | RTL Object | Depth x Width | Implemented As | ++------------------------------+------------+---------------+----------------+ +|mig_7series_v4_2_ddr_prbs_gen | mem_out | 256x18 | LUT | +|mig_7series_v4_2_ddr_prbs_gen | mem_out | 256x18 | LUT | ++------------------------------+------------+---------------+----------------+ + + +Distributed RAM: Preliminary Mapping Report (see note below) ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ +|arty_ddr3 | of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ + +Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +WARNING: [Synth 8-3321] set_false_path : Empty through list for constraint at line 359 of /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc:359] +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:19 ; elapsed = 00:01:19 . Memory (MB): peak = 3300.871 ; gain = 1060.109 ; free physical = 491922 ; free virtual = 628371 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:01:19 ; elapsed = 00:01:19 . Memory (MB): peak = 3300.871 ; gain = 1060.109 ; free physical = 491872 ; free virtual = 628347 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Distributed RAM: Final Mapping Report ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ +|arty_ddr3 | of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:01:21 ; elapsed = 00:01:22 . Memory (MB): peak = 3300.871 ; gain = 1060.109 ; free physical = 491502 ; free virtual = 628069 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:01:24 ; elapsed = 00:01:25 . Memory (MB): peak = 3300.871 ; gain = 1060.109 ; free physical = 491390 ; free virtual = 628027 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:01:24 ; elapsed = 00:01:25 . Memory (MB): peak = 3300.871 ; gain = 1060.109 ; free physical = 491389 ; free virtual = 628027 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:25 ; elapsed = 00:01:25 . Memory (MB): peak = 3300.871 ; gain = 1060.109 ; free physical = 491437 ; free virtual = 628074 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:01:25 ; elapsed = 00:01:25 . Memory (MB): peak = 3300.871 ; gain = 1060.109 ; free physical = 491436 ; free virtual = 628073 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:01:25 ; elapsed = 00:01:25 . Memory (MB): peak = 3300.871 ; gain = 1060.109 ; free physical = 491436 ; free virtual = 628073 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:01:25 ; elapsed = 00:01:25 . Memory (MB): peak = 3300.871 ; gain = 1060.109 ; free physical = 491435 ; free virtual = 628073 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Static Shift Register Report: ++------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ +|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | ++------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/rclk_delay_reg[11] | 12 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/rst_r4_reg | 4 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/phy_ctl_ready_r5_reg | 5 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay/delay_done_r4_reg | 4 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/init_dqsfound_done_r5_reg | 3 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrlvl_rank_done_r7_reg | 6 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prech_done_reg | 17 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_start_dly_r_reg[5] | 6 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg[14] | 15 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_pat_match_div4.pat_data_match_valid_r_reg | 3 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] | 3 | 4 | NO | NO | YES | 4 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/wrcal_pat_resume_reg | 3 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/reset_if_r9_reg | 9 | 1 | NO | NO | YES | 1 | 0 | ++------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ + + +Dynamic Shift Register Report: ++------------+----------------+--------+------------+--------+---------+--------+--------+--------+ +|Module Name | RTL Name | Length | Data Width | SRL16E | SRLC32E | Mux F7 | Mux F8 | Mux F9 | ++------------+----------------+--------+------------+--------+---------+--------+--------+--------+ +|dsrl | memory_reg[7] | 4 | 4 | 4 | 0 | 0 | 0 | 0 | +|dsrl__1 | memory_reg[31] | 129 | 129 | 0 | 129 | 0 | 0 | 0 | +|dsrl__2 | memory_reg[29] | 7 | 7 | 0 | 7 | 0 | 0 | 0 | ++------------+----------------+--------+------------+--------+---------+--------+--------+--------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+----------------------+------+ +| |Cell |Count | ++------+----------------------+------+ +|1 |BUFG | 3| +|2 |BUFH | 1| +|3 |BUFIO | 1| +|4 |CARRY4 | 124| +|5 |IDELAYCTRL | 1| +|6 |IDELAYE2 | 16| +|7 |IN_FIFO | 2| +|8 |ISERDESE2 | 16| +|9 |LUT1 | 375| +|10 |LUT2 | 438| +|11 |LUT3 | 1023| +|12 |LUT4 | 905| +|13 |LUT5 | 1361| +|14 |LUT6 | 1262| +|15 |MMCME2_ADV | 1| +|16 |MUXF7 | 28| +|17 |ODDR | 5| +|18 |OSERDESE2 | 43| +|21 |OUT_FIFO | 4| +|23 |PHASER_IN_PHY | 2| +|24 |PHASER_OUT_PHY | 4| +|26 |PHASER_REF | 1| +|27 |PHY_CONTROL | 1| +|28 |PLLE2_ADV | 1| +|29 |RAM32M | 112| +|30 |RAM32X1D | 2| +|31 |SRL16E | 20| +|32 |SRLC32E | 134| +|33 |XADC | 1| +|34 |FDCE | 2| +|35 |FDPE | 73| +|36 |FDRE | 3995| +|37 |FDSE | 123| +|38 |IOBUFDS_INTERMDISABLE | 2| +|39 |IOBUF_INTERMDISABLE | 16| +|40 |OBUF | 24| +|41 |OBUFDS | 1| +|42 |OBUFT | 2| ++------+----------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:01:25 ; elapsed = 00:01:25 . Memory (MB): peak = 3300.871 ; gain = 1060.109 ; free physical = 491435 ; free virtual = 628072 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 6 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:01:21 ; elapsed = 00:01:23 . Memory (MB): peak = 3300.871 ; gain = 950.266 ; free physical = 491411 ; free virtual = 628048 +Synthesis Optimization Complete : Time (s): cpu = 00:01:25 ; elapsed = 00:01:26 . Memory (MB): peak = 3300.879 ; gain = 1060.109 ; free physical = 491410 ; free virtual = 628047 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.14 . Memory (MB): peak = 3300.879 ; gain = 0.000 ; free physical = 491722 ; free virtual = 628364 +INFO: [Netlist 29-17] Analyzing 325 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3_ooc.xdc] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3_ooc.xdc] +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] +INFO: [Opt 31-138] Pushed 2 inverter(s) to 16 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3356.898 ; gain = 0.000 ; free physical = 491719 ; free virtual = 628364 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 133 instances were transformed. + IOBUFDS_INTERMDISABLE => IOBUFDS_INTERMDISABLE (IBUFDS_INTERMDISABLE_INT(x2), INV, OBUFTDS(x2)): 2 instances + IOBUF_INTERMDISABLE => IOBUF_INTERMDISABLE (IBUF_INTERMDISABLE, OBUFT): 16 instances + OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 1 instance + RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 112 instances + RAM32X1D => RAM32X1D (RAMD32(x2)): 2 instances + +Synth Design complete | Checksum: cc6d6f52 +INFO: [Common 17-83] Releasing license: Synthesis +249 Infos, 303 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:01:30 ; elapsed = 00:01:28 . Memory (MB): peak = 3356.898 ; gain = 1120.105 ; free physical = 491719 ; free virtual = 628364 +INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 3059.030; main = 2758.349; forked = 445.011 +INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 4342.461; main = 3356.902; forked = 1041.586 +INFO: [Coretcl 2-1174] Renamed 88 cell refs. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-2] Deriving generated clocks +INFO: [Timing 38-480] Writing timing data to binary archive. +Write ShapeDB Complete: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3404.914 ; gain = 0.000 ; free physical = 491865 ; free virtual = 628527 +Wrote PlaceDB: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3404.914 ; gain = 0.000 ; free physical = 491865 ; free virtual = 628527 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3404.914 ; gain = 0.000 ; free physical = 491865 ; free virtual = 628527 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3404.914 ; gain = 0.000 ; free physical = 491869 ; free virtual = 628532 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3404.914 ; gain = 0.000 ; free physical = 491869 ; free virtual = 628532 +Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3404.914 ; gain = 0.000 ; free physical = 491869 ; free virtual = 628532 +Write Physdb Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3404.914 ; gain = 0.000 ; free physical = 491869 ; free virtual = 628532 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3.dcp' has been generated. +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data0/tools/Xilinx/Vivado/2024.1/data/ip'. +WARNING: [Vivado 12-13650] The IP file '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc.xci' has been moved from its original location, as a result the outputs for this IP will now be generated in '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc'. Alternatively a copy of the IP can be imported into the project using one of the 'import_ip' or 'import_files' commands. +Command: synth_design -top toy_axi_cdc -part xc7a100tcsg324-1 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 3404.914 ; gain = 0.000 ; free physical = 491808 ; free virtual = 628479 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'toy_axi_cdc' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/synth/toy_axi_cdc.v:53] +INFO: [Synth 8-6157] synthesizing module 'axi_clock_converter_v2_1_30_axi_clock_converter' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/hdl/axi_clock_converter_v2_1_vl_rfs.v:650] +INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_single' [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:152] +INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_single' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:152] +INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_async_rst' [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1175] +INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_async_rst' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1175] +INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_single__parameterized1' [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:152] +INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_single__parameterized1' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:152] +INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray' [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:283] +INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:283] +INFO: [Synth 8-6155] done synthesizing module 'axi_clock_converter_v2_1_30_axi_clock_converter' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/hdl/axi_clock_converter_v2_1_vl_rfs.v:650] +INFO: [Synth 8-6155] done synthesizing module 'toy_axi_cdc' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/synth/toy_axi_cdc.v:53] +WARNING: [Synth 8-7129] Port ALMOST_FULL_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ALMOST_EMPTY_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_ACK_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port VALID_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port OVERFLOW_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port UNDERFLOW_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DATA_COUNT_I[4] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DATA_COUNT_I[3] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DATA_COUNT_I[2] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DATA_COUNT_I[1] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DATA_COUNT_I[0] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[4] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[3] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[2] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[1] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[0] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[4] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[3] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[2] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[1] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[0] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port SBITERR_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DBITERR_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_RST in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port SAFETY_CKT_WR_RST in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[3] in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[2] in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[1] in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[0] in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module wr_bin_cntr is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_EN_INTO_LOGIC in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_RST_INTO_LOGIC in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_EN in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST_FULL_FF in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_RST_BUSY in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port EMPTY in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RAM_RD_EN in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port ALMOST_EMPTY in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[3] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[2] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[1] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[0] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[3] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[2] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[1] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[0] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_NEGATE[3] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_NEGATE[2] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_NEGATE[1] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_NEGATE[0] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module rd_fwft is either unconnected or has no load +WARNING: [Synth 8-7129] Port SAFETY_CKT_RD_RST in module rd_fwft is either unconnected or has no load +WARNING: [Synth 8-7129] Port RAM_ALMOST_EMPTY in module rd_fwft is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port SAFETY_CKT_RD_RST in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_PNTR_PLUS2[3] in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_PNTR_PLUS2[2] in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_PNTR_PLUS2[1] in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_PNTR_PLUS2[0] in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module rd_bin_cntr is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_EN_INTO_LOGIC in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_RST_INTO_LOGIC in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_RST_BUSY in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RAM_WR_EN in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RST_FULL_FF in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port ALMOST_FULL_FB in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port FULL in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS1_RD[3] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS1_RD[2] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS1_RD[1] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS1_RD[0] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[3] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[2] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[1] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[0] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_ASSERT[3] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_ASSERT[2] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_ASSERT[1] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_ASSERT[0] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_NEGATE[3] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_NEGATE[2] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_NEGATE[1] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_NEGATE[0] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_RST in module clk_x_pntrs is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_RST in module clk_x_pntrs is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module dmem__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FAB_REGOUT_EN in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port SFT_RST in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port SAFETY_CKT_RD_RST in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port SLEEP in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port INJECTDBITERR in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port INJECTSBITERR in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port CLK in module input_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port INT_CLK in module input_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[3] in module input_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[2] in module input_blk__parameterized2 is either unconnected or has no load +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 3416.914 ; gain = 12.000 ; free physical = 491891 ; free virtual = 628560 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 3416.914 ; gain = 12.000 ; free physical = 491891 ; free virtual = 628560 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 3416.914 ; gain = 12.000 ; free physical = 491891 ; free virtual = 628560 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3416.914 ; gain = 0.000 ; free physical = 491893 ; free virtual = 628563 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_ooc.xdc] for cell 'inst' +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_ooc.xdc] for cell 'inst' +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/toy_axi_cdc_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/toy_axi_cdc_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/toy_axi_cdc_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/toy_axi_cdc_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +INFO: [Project 1-1714] 33 XPM XDC files have been applied to the design. +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3462.727 ; gain = 0.000 ; free physical = 491923 ; free virtual = 628592 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3462.727 ; gain = 0.000 ; free physical = 491923 ; free virtual = 628592 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 491974 ; free virtual = 628643 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a100tcsg324-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 491974 ; free virtual = 628643 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property KEEP_HIERARCHY = SOFT for inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.cdc_wr_rst_busy_ic_3.xpm_cdc_single_inst3 . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.cdc_wr_rst_busy_ic_1.xpm_cdc_single_inst1 . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.cdc_wr_rst_busy_ic_2.xpm_cdc_single_inst2 . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 491979 ; free virtual = 628648 +--------------------------------------------------------------------------------- +INFO: [Synth 8-802] inferred FSM for state register 'gpregsm1.curr_fwft_state_reg' in module 'rd_fwft' +INFO: [Synth 8-6159] Found Keep on FSM register 'gpregsm1.curr_fwft_state_reg' in module 'rd_fwft', re-encoding will not be performed +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + invalid | 00 | 00 + stage1_valid | 10 | 10 + both_stages_valid | 11 | 11 + stage2_valid | 01 | 01 +--------------------------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 491969 ; free virtual = 628639 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 10 ++---XORs : + 2 Input 4 Bit XORs := 10 + 2 Input 1 Bit XORs := 110 ++---Registers : + 145 Bit Registers := 2 + 135 Bit Registers := 2 + 61 Bit Registers := 4 + 6 Bit Registers := 2 + 5 Bit Registers := 10 + 4 Bit Registers := 83 + 2 Bit Registers := 15 + 1 Bit Registers := 88 ++---Muxes : + 4 Input 2 Bit Muxes := 5 + 2 Input 2 Bit Muxes := 50 + 5 Input 2 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 5 + 2 Input 1 Bit Muxes := 15 + 4 Input 1 Bit Muxes := 10 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 240 (col length:80) +BRAMs: 270 (col length: RAMB18 80 RAMB36 40) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +WARNING: [Synth 8-7080] Parallel synthesis criteria is not met +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 491967 ; free virtual = 628638 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Distributed RAM: Preliminary Mapping Report (see note below) ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 61 | RAM32M x 11 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 145 | RAM32M x 25 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 6 | RAM32M x 1 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 61 | RAM32M x 11 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 135 | RAM32M x 23 | ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ + +Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 492037 ; free virtual = 628707 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 492041 ; free virtual = 628712 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Distributed RAM: Final Mapping Report ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 61 | RAM32M x 11 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 145 | RAM32M x 25 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 6 | RAM32M x 1 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 61 | RAM32M x 11 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 135 | RAM32M x 23 | ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 492048 ; free virtual = 628719 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 492084 ; free virtual = 628755 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 492084 ; free virtual = 628755 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 492084 ; free virtual = 628755 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 492084 ; free virtual = 628755 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 492084 ; free virtual = 628755 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 492084 ; free virtual = 628755 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+---------+------+ +| |Cell |Count | ++------+---------+------+ +|1 |LUT1 | 76| +|2 |LUT2 | 66| +|3 |LUT3 | 35| +|4 |LUT4 | 65| +|5 |LUT5 | 10| +|6 |LUT6 | 25| +|7 |RAM32M | 68| +|8 |RAM32X1D | 3| +|9 |FDCE | 130| +|10 |FDPE | 115| +|11 |FDRE | 1081| ++------+---------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 492084 ; free virtual = 628755 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 206 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 3462.727 ; gain = 12.000 ; free physical = 492086 ; free virtual = 628757 +Synthesis Optimization Complete : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3462.734 ; gain = 57.812 ; free physical = 492086 ; free virtual = 628757 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3462.734 ; gain = 0.000 ; free physical = 492379 ; free virtual = 629050 +INFO: [Netlist 29-17] Analyzing 71 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_ooc.xdc] for cell 'inst' +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_ooc.xdc] for cell 'inst' +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc] for cell 'inst' +INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:16] +WARNING: [Vivado_Tcl 4-2057] Waiver ID 'LUTAR-1' object list specifies likely unusable hierarchical instance 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:30] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:35] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:35] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:35] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:39] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:39] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:42] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:42] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:45] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:45] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:45] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:49] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:49] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:52] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:52] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:52] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:56] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:56] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:56] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:60] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:60] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:63] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:63] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:66] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:66] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:66] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:70] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:70] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc] for cell 'inst' +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3462.734 ; gain = 0.000 ; free physical = 492413 ; free virtual = 629084 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 71 instances were transformed. + RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 68 instances + RAM32X1D => RAM32X1D (RAMD32(x2)): 3 instances + +Synth Design complete | Checksum: ed94db3a +INFO: [Common 17-83] Releasing license: Synthesis +33 Infos, 130 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 3462.734 ; gain = 57.820 ; free physical = 492415 ; free virtual = 629086 +INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 3101.122; main = 2799.306; forked = 445.645 +INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 4504.316; main = 3462.730; forked = 1041.586 +INFO: [Coretcl 2-1174] Renamed 101 cell refs. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-480] Writing timing data to binary archive. +Write ShapeDB Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00 . Memory (MB): peak = 3470.730 ; gain = 0.000 ; free physical = 492418 ; free virtual = 629089 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc.dcp' has been generated. +INFO: [Vivado 12-3441] generate_netlist_ip - operation complete +synth_ip: Time (s): cpu = 00:02:04 ; elapsed = 00:02:00 . Memory (MB): peak = 3470.730 ; gain = 1247.883 ; free physical = 492416 ; free virtual = 629088 +INFO: [Common 17-2834] synth_ip peak Physical Memory [PSS] (MB): overall = 3101.122; main = 2799.306; forked = 445.645 +INFO: [Common 17-2834] synth_ip peak Virtual Memory [VSS] (MB): overall = 4504.316; main = 3470.734; forked = 1041.586 +# phase SYNTH_BOARD +BOARD_PHASE SYNTH_BOARD +# if {$flash} {read_verilog -sv $root/build/flash-boot/ToyLinuxChip.sv} else { +# read_verilog -sv $root/build/serial-bound/ToyLinuxChip.sv +# } +# read_verilog -sv $root/build/serial-bound/FpgaMemories.sv +# foreach f [glob $root/board/*.sv] {read_verilog -sv $f} +# set_property verilog_define {SYNTHESIS BUCKYBALL_DISABLE_DPI} [current_fileset] +# read_xdc $root/board/arty_a7.xdc +# read_xdc $root/board/flash_boot.xdc +# synth_design -top toy_a7_top -part xc7a100tcsg324-1 -flatten_hierarchy rebuilt -directive AreaOptimized_high -resource_sharing on -generic FLASH_BOOT=$flash +Command: synth_design -top toy_a7_top -part xc7a100tcsg324-1 -flatten_hierarchy rebuilt -directive AreaOptimized_high -resource_sharing on -generic FLASH_BOOT=0 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 3470.852 ; gain = 0.000 ; free physical = 492075 ; free virtual = 628755 +--------------------------------------------------------------------------------- +WARNING: [Synth 8-6901] identifier 'reset' is used before its declaration [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:30] +INFO: [Synth 8-6157] synthesizing module 'toy_a7_top' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:1] + Parameter FLASH_BOOT bound to: 0 - type: integer +INFO: [Synth 8-6157] synthesizing module 'IBUF' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:73643] +INFO: [Synth 8-6155] done synthesizing module 'IBUF' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:73643] +INFO: [Synth 8-6157] synthesizing module 'MMCME2_BASE' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82508] + Parameter CLKFBOUT_MULT_F bound to: 10.000000 - type: double + Parameter CLKIN1_PERIOD bound to: 10.000000 - type: double + Parameter CLKOUT0_DIVIDE_F bound to: 40.000000 - type: double + Parameter CLKOUT1_DIVIDE bound to: 6 - type: integer + Parameter CLKOUT2_DIVIDE bound to: 5 - type: integer + Parameter DIVCLK_DIVIDE bound to: 1 - type: integer +INFO: [Synth 8-6155] done synthesizing module 'MMCME2_BASE' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82508] +WARNING: [Synth 8-7071] port 'CLKFBOUTB' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT0B' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT1B' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT2B' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT3' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT3B' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT4' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT5' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT6' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7023] instance 'clock_mmcm' of module 'MMCME2_BASE' has 18 connections declared, but only 9 given [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:13] +INFO: [Synth 8-6157] synthesizing module 'BUFG' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951] +INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951] +INFO: [Synth 8-6157] synthesizing module 'toy_a7_platform' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_platform.sv:2] + Parameter FLASH_BOOT bound to: 0 - type: integer +INFO: [Synth 8-6157] synthesizing module 'uart_rx' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_rx.sv:3] + Parameter DIVISOR bound to: 25 - type: integer +INFO: [Synth 8-6155] done synthesizing module 'uart_rx' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_rx.sv:3] +INFO: [Synth 8-6157] synthesizing module 'uart_tx' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_tx.sv:1] + Parameter DIVISOR bound to: 25 - type: integer +INFO: [Synth 8-6155] done synthesizing module 'uart_tx' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_tx.sv:1] +INFO: [Synth 8-6157] synthesizing module 'ddr_uart_loader' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:5] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:99] +INFO: [Synth 8-6155] done synthesizing module 'ddr_uart_loader' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:5] +INFO: [Synth 8-6157] synthesizing module 'ToyLinuxChip' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:103817] +INFO: [Synth 8-6157] synthesizing module 'ToyLinuxSystem' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:102569] +INFO: [Synth 8-6157] synthesizing module 'IntSyncAsyncCrossingSink_n1x1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:61] +INFO: [Synth 8-6157] synthesizing module 'SynchronizerShiftReg_w1_d3' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:48] +INFO: [Synth 8-6157] synthesizing module 'NonSyncResetSynchronizerPrimitiveShiftReg_d3' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:31] +INFO: [Synth 8-6155] done synthesizing module 'NonSyncResetSynchronizerPrimitiveShiftReg_d3' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:31] +INFO: [Synth 8-6155] done synthesizing module 'SynchronizerShiftReg_w1_d3' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:48] +INFO: [Synth 8-6155] done synthesizing module 'IntSyncAsyncCrossingSink_n1x1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:61] +INFO: [Synth 8-6157] synthesizing module 'IntSyncCrossingSource_n1x1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:103] +INFO: [Synth 8-6157] synthesizing module 'AsyncResetRegVec_w1_i0' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:74] +INFO: [Synth 8-6155] done synthesizing module 'AsyncResetRegVec_w1_i0' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:74] +INFO: [Synth 8-6155] done synthesizing module 'IntSyncCrossingSource_n1x1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:103] +INFO: [Synth 8-6157] synthesizing module 'SystemBus' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:9400] +INFO: [Synth 8-6157] synthesizing module 'FixedClockBroadcast_3' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:118] +INFO: [Synth 8-6155] done synthesizing module 'FixedClockBroadcast_3' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:118] +INFO: [Synth 8-6157] synthesizing module 'TLXbar_sbus_i2_o3_a32d128s3k1z4c' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:2434] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:3011] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:139] +INFO: [Synth 8-6157] synthesizing module 'plusarg_reader' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104301] + Parameter FORMAT bound to: tilelink_timeout=%d - type: string + Parameter WIDTH bound to: 32 - type: integer + Parameter DEFAULT bound to: 32'b00000000000000000000000000000000 +INFO: [Synth 8-6155] done synthesizing module 'plusarg_reader' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104301] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:139] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:3033] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:987] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:987] +INFO: [Synth 8-6155] done synthesizing module 'TLXbar_sbus_i2_o3_a32d128s3k1z4c' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:2434] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_sbus_to_bus_named_cbus' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4386] +INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget16' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4218] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4310] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_2' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:3195] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_2' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:3195] +INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a28d128s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4151] +INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a28d128s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4151] +INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget16' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4218] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_sbus_to_bus_named_cbus' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4386] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8623] +INFO: [Synth 8-6157] synthesizing module 'AXI4Buffer' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4891] +INFO: [Synth 8-6157] synthesizing module 'Queue2_AXI4BundleAW' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4497] +INFO: [Synth 8-6157] synthesizing module 'ram_2x58' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4478] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x58' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4478] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_AXI4BundleAW' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4497] +INFO: [Synth 8-6157] synthesizing module 'Queue2_AXI4BundleW' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4600] +INFO: [Synth 8-6157] synthesizing module 'ram_2x73' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4581] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x73' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4581] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_AXI4BundleW' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4600] +INFO: [Synth 8-6157] synthesizing module 'Queue2_AXI4BundleB' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4676] +INFO: [Synth 8-6157] synthesizing module 'ram_2x4' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4657] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x4' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4657] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_AXI4BundleB' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4676] +INFO: [Synth 8-6157] synthesizing module 'Queue2_AXI4BundleAR' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4729] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_AXI4BundleAR' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4729] +INFO: [Synth 8-6157] synthesizing module 'Queue2_AXI4BundleR' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4832] +INFO: [Synth 8-6157] synthesizing module 'ram_2x69' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4813] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x69' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4813] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_AXI4BundleR' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4832] +INFO: [Synth 8-6155] done synthesizing module 'AXI4Buffer' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4891] +INFO: [Synth 8-6157] synthesizing module 'AXI4UserYanker' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5178] +INFO: [Synth 8-6157] synthesizing module 'Queue2_BundleMap' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5086] +INFO: [Synth 8-6157] synthesizing module 'ram_2x8' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5067] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x8' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5067] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_BundleMap' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5086] +INFO: [Synth 8-6157] synthesizing module 'Queue1_BundleMap' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5143] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_BundleMap' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5143] +INFO: [Synth 8-6155] done synthesizing module 'AXI4UserYanker' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5178] +INFO: [Synth 8-6157] synthesizing module 'AXI4Deinterleaver' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5631] +INFO: [Synth 8-6157] synthesizing module 'Queue8_AXI4BundleR' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5559] +INFO: [Synth 8-6157] synthesizing module 'ram_8x77' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5540] +INFO: [Synth 8-6155] done synthesizing module 'ram_8x77' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5540] +INFO: [Synth 8-6155] done synthesizing module 'Queue8_AXI4BundleR' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5559] +INFO: [Synth 8-6155] done synthesizing module 'AXI4Deinterleaver' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5631] +INFO: [Synth 8-6157] synthesizing module 'AXI4IdIndexer' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:6073] +INFO: [Synth 8-6155] done synthesizing module 'AXI4IdIndexer' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:6073] +INFO: [Synth 8-6157] synthesizing module 'TLToAXI4' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7148] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7423] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_3' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:6219] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_3' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:6219] +INFO: [Synth 8-6157] synthesizing module 'Queue1_AXI4BundleW' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7048] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_AXI4BundleW' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7048] +INFO: [Synth 8-6157] synthesizing module 'Queue1_AXI4BundleARW' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7082] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_AXI4BundleARW' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7082] +INFO: [Synth 8-6155] done synthesizing module 'TLToAXI4' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7148] +INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget16_2' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8463] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8551] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_4' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7529] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_4' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7529] +INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a31d128s3k1z3u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8396] +INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a31d128s3k1z3u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8396] +INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget16_2' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8463] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8623] +INFO: [Synth 8-6155] done synthesizing module 'SystemBus' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:9400] +INFO: [Synth 8-6157] synthesizing module 'PeripheryBus_cbus' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19330] +INFO: [Synth 8-6157] synthesizing module 'FixedClockBroadcast_4' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10050] +INFO: [Synth 8-6155] done synthesizing module 'FixedClockBroadcast_4' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10050] +INFO: [Synth 8-6157] synthesizing module 'TLXbar_cbus_out_i1_o4_a28d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10975] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:11207] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_5' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10073] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_5' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10073] +INFO: [Synth 8-6155] done synthesizing module 'TLXbar_cbus_out_i1_o4_a28d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10975] +INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a28d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12399] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12453] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_6' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:11288] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_6' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:11288] +INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleA_a28d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12221] +INFO: [Synth 8-6157] synthesizing module 'ram_2x114' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12202] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x114' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12202] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleA_a28d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12221] +INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleD_a28d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12320] +INFO: [Synth 8-6157] synthesizing module 'ram_2x79' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12301] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x79' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12301] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleD_a28d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12320] +INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a28d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12399] +INFO: [Synth 8-6157] synthesizing module 'TLAtomicAutomata_cbus' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:13449] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:13829] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_7' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12534] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_7' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12534] +INFO: [Synth 8-6155] done synthesizing module 'TLAtomicAutomata_cbus' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:13449] +INFO: [Synth 8-6157] synthesizing module 'ErrorDeviceWrapper' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16155] +INFO: [Synth 8-6157] synthesizing module 'TLError' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14846] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14907] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_8' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:13973] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_8' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:13973] +INFO: [Synth 8-6157] synthesizing module 'Queue1_TLBundleA_a14d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14799] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_TLBundleA_a14d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14799] +INFO: [Synth 8-6155] done synthesizing module 'TLError' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14846] +INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a14d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16028] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16078] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_9' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14953] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_9' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14953] +INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleA_a14d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15876] +INFO: [Synth 8-6157] synthesizing module 'ram_2x100' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15857] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x100' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15857] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleA_a14d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15876] +INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleD_a14d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15955] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleD_a14d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15955] +INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a14d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16028] +INFO: [Synth 8-6155] done synthesizing module 'ErrorDeviceWrapper' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16155] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_clint' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17261] +INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_CLINT' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17081] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17199] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_10' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16258] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_10' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16258] +INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a26d64s3k1z3u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17017] +INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a26d64s3k1z3u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17017] +INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_CLINT' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17081] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_clint' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17261] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_plic' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18350] +INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_PLIC' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18170] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18288] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_11' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17336] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_11' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17336] +INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a28d64s3k1z3u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18106] +INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a28d64s3k1z3u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18106] +INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_PLIC' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18170] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_plic' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18350] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_bootrom' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19263] +INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_bootrom' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19104] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19205] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_12' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18425] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19035] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_12' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18425] +INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a17d64s3k1z3u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19040] +INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a17d64s3k1z3u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19040] +INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_bootrom' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19104] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_bootrom' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19263] +INFO: [Synth 8-6155] done synthesizing module 'PeripheryBus_cbus' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19330] +INFO: [Synth 8-6157] synthesizing module 'MemoryBus' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:24031] +INFO: [Synth 8-6157] synthesizing module 'ProbePicker' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20610] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20649] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_13' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19882] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_13' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19882] +INFO: [Synth 8-6155] done synthesizing module 'ProbePicker' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20610] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:23555] +INFO: [Synth 8-6157] synthesizing module 'AXI4UserYanker_1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20764] +INFO: [Synth 8-6157] synthesizing module 'Queue2_BundleMap_6' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20707] +INFO: [Synth 8-6157] synthesizing module 'ram_2x10' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20688] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x10' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20688] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_BundleMap_6' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20707] +INFO: [Synth 8-6155] done synthesizing module 'AXI4UserYanker_1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20764] +INFO: [Synth 8-6157] synthesizing module 'AXI4IdIndexer_1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:21713] +INFO: [Synth 8-6155] done synthesizing module 'AXI4IdIndexer_1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:21713] +INFO: [Synth 8-6157] synthesizing module 'TLToAXI4_1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22687] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:23450] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_14' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:21859] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_14' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:21859] +INFO: [Synth 8-6157] synthesizing module 'Queue1_AXI4BundleW_1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22587] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_AXI4BundleW_1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22587] +INFO: [Synth 8-6157] synthesizing module 'Queue1_AXI4BundleARW_1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22621] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_AXI4BundleARW_1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22621] +INFO: [Synth 8-6155] done synthesizing module 'TLToAXI4_1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22687] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:23555] +INFO: [Synth 8-6155] done synthesizing module 'MemoryBus' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:24031] +INFO: [Synth 8-6157] synthesizing module 'CoherenceManagerWrapper' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:27491] +INFO: [Synth 8-6157] synthesizing module 'TLBroadcast' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:26100] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:26482] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_15' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:24349] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_15' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:24349] +INFO: [Synth 8-6157] synthesizing module 'BroadcastFilter' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25732] +INFO: [Common 17-14] Message 'Synth 8-6157' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-6155] done synthesizing module 'BroadcastFilter' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25732] +INFO: [Synth 8-6155] done synthesizing module 'ram_4x144' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25756] +INFO: [Synth 8-6155] done synthesizing module 'Queue4_TLBroadcastData' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25775] +INFO: [Synth 8-6155] done synthesizing module 'TLBroadcastTracker' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25828] +INFO: [Synth 8-6155] done synthesizing module 'TLBroadcastTracker_1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25964] +INFO: [Synth 8-6155] done synthesizing module 'TLBroadcast' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:26100] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:27453] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_16' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:26686] +INFO: [Common 17-14] Message 'Synth 8-6155' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29794] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29834] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43249] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43271] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44089] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44825] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:45961] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47133] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68592] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68606] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68620] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:82885] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:82084] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86970] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85223] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85231] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:90541] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:90573] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:90605] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:90637] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:90669] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:90701] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:90733] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98928] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98950] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99569] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99575] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99581] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100308] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101303] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:102505] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101968] + Parameter FLASH_BOOT bound to: 0 - type: integer +WARNING: [Synth 8-6014] Unused sequential element rmPost_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52403] +WARNING: [Synth 8-6014] Unused sequential element rmPost_pipe_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52405] +WARNING: [Synth 8-6014] Unused sequential element rm_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52416] +WARNING: [Synth 8-6014] Unused sequential element rm_pipe_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52418] +WARNING: [Synth 8-6014] Unused sequential element rm_pipe_pipe_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52420] +WARNING: [Synth 8-6014] Unused sequential element tag_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52422] +WARNING: [Synth 8-6014] Unused sequential element tag_pipe_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52424] +WARNING: [Synth 8-6014] Unused sequential element tag_pipe_pipe_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52426] +WARNING: [Synth 8-6014] Unused sequential element ex_ctrl_rxs1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:61288] +WARNING: [Synth 8-6014] Unused sequential element ex_ctrl_rfs1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62163] +WARNING: [Synth 8-6014] Unused sequential element ex_ctrl_rfs2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62183] +WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rxs2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62375] +WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rxs1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62376] +WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rfs1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62378] +WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rfs2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62379] +WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rxs2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62390] +WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rxs1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62391] +WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rfs1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62393] +WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rfs2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62394] +WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd0val_REG_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62497] +WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd0val_REG_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62498] +WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd1val_REG_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62499] +WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd1val_REG_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62500] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63220] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63221] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63222] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63223] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63224] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_5_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63225] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_6_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63226] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_7_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63227] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_8_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63228] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_9_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63229] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_10_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63230] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_11_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63231] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_12_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63232] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_13_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63233] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_14_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63234] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_15_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63235] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_2_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76912] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_2_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76914] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76916] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76919] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76922] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76926] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76930] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76935] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76940] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76946] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76952] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76959] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_2_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76968] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76970] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76973] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76977] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76982] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76988] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_84_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77024] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_85_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77026] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_87_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77029] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_90_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77033] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_94_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77038] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_99_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77044] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_105_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77052] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_106_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77054] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_108_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77057] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_111_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77061] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_115_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77066] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_120_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77072] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_dataflow_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76917] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_propagate_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76920] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_dataflow_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76923] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_dataflow_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76924] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_propagate_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76927] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_propagate_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76928] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_dataflow_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76931] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_dataflow_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76932] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_dataflow_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76933] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_propagate_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76936] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_propagate_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76937] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_propagate_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76938] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_dataflow_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76941] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_dataflow_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76942] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_dataflow_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76943] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_dataflow_r_4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76944] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_propagate_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76947] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_propagate_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76948] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_propagate_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76949] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_propagate_r_4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76950] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76953] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76954] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76955] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76956] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_5_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76957] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76960] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76961] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76962] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76963] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_5_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76964] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_shift_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76971] +INFO: [Common 17-14] Message 'Synth 8-6014' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [Synth 8-3936] Found unconnected internal register 's2_req_tag_reg' and it is trimmed from '8' to '6' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93740] +WARNING: [Synth 8-3917] design toy_a7_top has port flash_wp_n driven by constant 1 +WARNING: [Synth 8-3917] design toy_a7_top has port flash_hold_n driven by constant 1 +WARNING: [Synth 8-7129] Port wdata[63] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[62] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[61] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[60] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[59] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[58] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[57] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[56] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[55] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[54] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[53] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[52] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[51] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[50] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[49] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[48] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[47] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[46] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[45] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[44] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[43] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[42] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[41] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[40] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[39] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[38] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[37] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[36] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[35] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[34] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[33] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[32] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wstrb[7] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wstrb[6] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wstrb[5] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wstrb[4] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port flash_miso in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port flash_recovery in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port load_addr[3] in module loader_axi is either unconnected or has no load +WARNING: [Synth 8-7129] Port load_addr[2] in module loader_axi is either unconnected or has no load +WARNING: [Synth 8-7129] Port load_addr[1] in module loader_axi is either unconnected or has no load +WARNING: [Synth 8-7129] Port load_addr[0] in module loader_axi is either unconnected or has no load +WARNING: [Synth 8-7129] Port clock in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port reset in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_ready in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_valid in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_opcode[2] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_opcode[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_opcode[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_param[2] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_param[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_param[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_size[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_size[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[6] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[5] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[4] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[3] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[2] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[16] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[15] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[14] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[13] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[12] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[11] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[10] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[9] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[8] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[7] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[6] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[5] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[4] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[3] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[2] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[7] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[6] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[5] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[4] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[3] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[2] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_corrupt in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_ready in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_valid in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_size[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_size[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_source[6] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_source[5] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_source[4] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_source[3] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_source[2] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_source[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_source[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port clock in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port reset in module TLMonitor_28 is either unconnected or has no load +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 3813.723 ; gain = 342.871 ; free physical = 491660 ; free virtual = 628352 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 3828.566 ; gain = 357.715 ; free physical = 491683 ; free virtual = 628374 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 3828.566 ; gain = 357.715 ; free physical = 491683 ; free virtual = 628374 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 3828.566 ; gain = 0.000 ; free physical = 491693 ; free virtual = 628384 +INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc] for cell 'ddr_controller' +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc] for cell 'ddr_controller' +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc/toy_axi_cdc_in_context.xdc] for cell 'memory_cdc' +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc/toy_axi_cdc_in_context.xdc] for cell 'memory_cdc' +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/arty_a7.xdc] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/arty_a7.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/arty_a7.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/toy_a7_top_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/toy_a7_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/flash_boot.xdc] +CRITICAL WARNING: [Designutils 20-1307] Command 'if' is not supported in the xdc constraint file. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/flash_boot.xdc:11] +CRITICAL WARNING: [Designutils 20-1307] Command 'if' is not supported in the xdc constraint file. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/flash_boot.xdc:15] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/flash_boot.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/flash_boot.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/toy_a7_top_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/toy_a7_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +INFO: [Timing 38-2] Deriving generated clocks +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3996.254 ; gain = 0.000 ; free physical = 491625 ; free virtual = 628316 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 1 instances were transformed. + MMCME2_BASE => MMCME2_ADV: 1 instance + +INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'uart_rx' +WARNING: [Synth 8-3936] Found unconnected internal register 'cam_a_0_bits_opcode_reg' and it is trimmed from '3' to '1' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:13813] +WARNING: [Synth 8-3936] Found unconnected internal register 'ram_reg' and it is trimmed from '100' to '13' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14825] +WARNING: [Synth 8-3936] Found unconnected internal register 'req_addr_reg' and it is trimmed from '40' to '32' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30468] +WARNING: [Synth 8-3936] Found unconnected internal register 'r_raddr_reg' and it is trimmed from '11' to '4' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36089] +WARNING: [Synth 8-3936] Found unconnected internal register 'in_fmt_reg' and it is trimmed from '2' to '1' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50199] +WARNING: [Synth 8-3936] Found unconnected internal register 'mem_reg_inst_reg' and it is trimmed from '32' to '12' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:54509] +WARNING: [Synth 8-3936] Found unconnected internal register 'ex_reg_inst_reg' and it is trimmed from '32' to '28' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:54256] +WARNING: [Synth 8-3936] Found unconnected internal register 'reg_mcounteren_reg' and it is trimmed from '32' to '3' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:55509] +WARNING: [Synth 8-3936] Found unconnected internal register 'reg_scounteren_reg' and it is trimmed from '32' to '3' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:55511] +WARNING: [Synth 8-3936] Found unconnected internal register 'reg_mideleg_reg' and it is trimmed from '64' to '14' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:55493] +WARNING: [Synth 8-3936] Found unconnected internal register 'reg_medeleg_reg' and it is trimmed from '64' to '16' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:55497] +WARNING: [Synth 8-3936] Found unconnected internal register 'wb_reg_raw_inst_reg' and it is trimmed from '32' to '16' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62407] +WARNING: [Synth 8-3936] Found unconnected internal register 'mem_reg_raw_inst_reg' and it is trimmed from '32' to '16' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62407] +WARNING: [Synth 8-3936] Found unconnected internal register 'ex_reg_raw_inst_reg' and it is trimmed from '32' to '16' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62438] +WARNING: [Synth 8-3936] Found unconnected internal register 'iter_reg_reg' and it is trimmed from '34' to '29' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84823] +WARNING: [Synth 8-3936] Found unconnected internal register 'iter_cmd_reg' and it is trimmed from '34' to '29' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84821] +WARNING: [Synth 8-3936] Found unconnected internal register 'reqReg_vaddr_reg' and it is trimmed from '64' to '39' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86206] +INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'MemConfiger' +INFO: [Synth 8-802] inferred FSM for state register 'ws_reg' in module 'axi_fullwidth' +INFO: [Synth 8-802] inferred FSM for state register 'rs_reg' in module 'axi_fullwidth' +INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'loader_axi' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + IDLE | 000 | 000 + START | 001 | 001 + DATA | 010 | 010 + STOP | 011 | 011 + WAIT_HIGH | 100 | 100 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'uart_rx' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + iSTATE3 | 00000001 | 000 + iSTATE2 | 00000010 | 001 + iSTATE6 | 00000100 | 010 + iSTATE4 | 00010000 | 011 + iSTATE1 | 00100000 | 100 + iSTATE5 | 00001000 | 101 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'MemConfiger' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + P_D965DF20 | 00 | 00 + P_D965DC20 | 01 | 01 + P_D965E030 | 10 | 10 + P_D9611170 | 11 | 11 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'ws_reg' using encoding 'sequential' in module 'axi_fullwidth' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + R_IDLE | 00 | 00 + R_SEND | 01 | 01 + R_RESP | 10 | 10 + R_RETURN | 11 | 11 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'rs_reg' using encoding 'sequential' in module 'axi_fullwidth' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + IDLE | 000001 | 000 + SEND_W | 100000 | 001 + WAIT_B | 010000 | 010 + SEND_R | 001000 | 011 + WAIT_R | 000100 | 100 + RELEASE | 000010 | 101 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'loader_axi' +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:46 ; elapsed = 00:00:42 . Memory (MB): peak = 4000.172 ; gain = 529.320 ; free physical = 486720 ; free virtual = 623434 +--------------------------------------------------------------------------------- +INFO: [Synth 8-223] decloning instance 'platform/chip/system/sbus/system_bus_xbar/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/sbus/system_bus_xbar/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/sbus/system_bus_xbar/monitor_1/plusarg_reader' (plusarg_reader) to 'platform/chip/system/sbus/system_bus_xbar/monitor_1/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/sbus/coupler_to_bus_named_cbus/widget/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/sbus/coupler_to_bus_named_cbus/widget/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/sbus/coupler_to_port_named_mmio_port_axi4/tl2axi4/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/sbus/coupler_to_port_named_mmio_port_axi4/tl2axi4/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/sbus/coupler_to_port_named_mmio_port_axi4/widget/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/sbus/coupler_to_port_named_mmio_port_axi4/widget/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/out_xbar/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/out_xbar/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/buffer/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/buffer/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/atomics/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/atomics/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/wrapped_error_device/error/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/wrapped_error_device/error/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/wrapped_error_device/buffer/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/wrapped_error_device/buffer/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/coupler_to_clint/fragmenter/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/coupler_to_clint/fragmenter/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/coupler_to_plic/fragmenter/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/coupler_to_plic/fragmenter/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/coupler_to_bootrom/fragmenter/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/coupler_to_bootrom/fragmenter/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/mbus/picker/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/mbus/picker/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/mbus/coupler_to_memory_controller_port_named_axi4/tl2axi4/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/mbus/coupler_to_memory_controller_port_named_axi4/tl2axi4/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/coh_wrapper/broadcast_1/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/coh_wrapper/broadcast_1/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/coh_wrapper/binder/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/coh_wrapper/binder/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/tlMasterXbar/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/tlMasterXbar/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/tlMasterXbar/monitor_1/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/tlMasterXbar/monitor_1/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/dtlb/mpu_ppn_barrier' (OptimizationBarrier_TLBEntryData) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/dtlb/entries_barrier_12' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/tlb/mpu_ppn_barrier' (OptimizationBarrier_TLBEntryData) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/tlb/entries_barrier_12' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/xbar/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/xbar/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/xbar/monitor_1/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/xbar/monitor_1/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer_1/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer_1/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/widget_3/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/widget_3/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer_2/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer_2/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/buffer/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/buffer/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/buffer/monitor_1/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/buffer/monitor_1/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/intsource' (IntSyncCrossingSource_n1x1) to 'platform/chip/system/tile_prci_domain/intsource_2' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/clint_domain/clint/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/clint_domain/clint/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/plic_domain/plic/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/plic_domain/plic/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/bootrom_domain/bootrom/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/bootrom_domain/bootrom/monitor/plusarg_reader_1' +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 109 Bit Adders := 1 + 2 Input 107 Bit Adders := 1 + 2 Input 73 Bit Adders := 1 + 3 Input 65 Bit Adders := 1 + 2 Input 64 Bit Adders := 21 + 3 Input 64 Bit Adders := 2 + 3 Input 58 Bit Adders := 1 + 2 Input 58 Bit Adders := 2 + 2 Input 55 Bit Adders := 4 + 2 Input 48 Bit Adders := 1 + 2 Input 40 Bit Adders := 3 + 3 Input 39 Bit Adders := 5 + 2 Input 39 Bit Adders := 3 + 2 Input 37 Bit Adders := 1 + 2 Input 34 Bit Adders := 1 + 2 Input 33 Bit Adders := 3 + 2 Input 32 Bit Adders := 18 + 3 Input 32 Bit Adders := 1 + 2 Input 30 Bit Adders := 8 + 3 Input 29 Bit Adders := 1 + 2 Input 28 Bit Adders := 1 + 2 Input 26 Bit Adders := 4 + 2 Input 20 Bit Adders := 64 + 2 Input 19 Bit Adders := 2 + 2 Input 17 Bit Adders := 2 + 3 Input 16 Bit Adders := 1 + 2 Input 16 Bit Adders := 12 + 2 Input 15 Bit Adders := 4 + 2 Input 14 Bit Adders := 7 + 4 Input 14 Bit Adders := 1 + 2 Input 13 Bit Adders := 6 + 3 Input 13 Bit Adders := 2 + 2 Input 12 Bit Adders := 12 + 3 Input 12 Bit Adders := 1 + 2 Input 11 Bit Adders := 4 + 2 Input 10 Bit Adders := 7 + 4 Input 10 Bit Adders := 1 + 3 Input 10 Bit Adders := 1 + 2 Input 9 Bit Adders := 14 + 3 Input 9 Bit Adders := 4 + 2 Input 8 Bit Adders := 16 + 3 Input 8 Bit Adders := 8 + 2 Input 7 Bit Adders := 6 + 3 Input 7 Bit Adders := 1 + 2 Input 6 Bit Adders := 13 + 3 Input 6 Bit Adders := 2 + 2 Input 5 Bit Adders := 9 + 2 Input 4 Bit Adders := 60 + 5 Input 4 Bit Adders := 1 + 4 Input 4 Bit Adders := 4 + 2 Input 3 Bit Adders := 65 + 3 Input 3 Bit Adders := 7 + 2 Input 2 Bit Adders := 70 + 3 Input 2 Bit Adders := 5 + 4 Input 2 Bit Adders := 1 + 3 Input 1 Bit Adders := 3 + 2 Input 1 Bit Adders := 126 + 4 Input 1 Bit Adders := 39 ++---XORs : + 2 Input 65 Bit XORs := 1 + 2 Input 64 Bit XORs := 5 + 2 Input 32 Bit XORs := 8 + 2 Input 29 Bit XORs := 8 + 2 Input 27 Bit XORs := 6 + 2 Input 25 Bit XORs := 16 + 2 Input 20 Bit XORs := 8 + 2 Input 18 Bit XORs := 8 + 2 Input 16 Bit XORs := 18 + 2 Input 11 Bit XORs := 8 + 2 Input 10 Bit XORs := 3 + 2 Input 4 Bit XORs := 3 + 2 Input 3 Bit XORs := 11 + 2 Input 2 Bit XORs := 8 + 2 Input 1 Bit XORs := 14 + 3 Input 1 Bit XORs := 2 + 4 Input 1 Bit XORs := 2 ++---Registers : + 1269 Bit Registers := 1 + 145 Bit Registers := 1 + 130 Bit Registers := 1 + 128 Bit Registers := 9 + 107 Bit Registers := 1 + 106 Bit Registers := 3 + 105 Bit Registers := 1 + 73 Bit Registers := 1 + 72 Bit Registers := 1 + 67 Bit Registers := 1 + 65 Bit Registers := 14 + 64 Bit Registers := 184 + 62 Bit Registers := 2 + 58 Bit Registers := 2 + 56 Bit Registers := 1 + 55 Bit Registers := 5 + 53 Bit Registers := 3 + 44 Bit Registers := 5 + 42 Bit Registers := 74 + 40 Bit Registers := 21 + 39 Bit Registers := 19 + 34 Bit Registers := 2 + 32 Bit Registers := 115 + 31 Bit Registers := 2 + 30 Bit Registers := 8 + 29 Bit Registers := 2 + 28 Bit Registers := 5 + 27 Bit Registers := 34 + 26 Bit Registers := 4 + 24 Bit Registers := 1 + 23 Bit Registers := 4 + 21 Bit Registers := 8 + 20 Bit Registers := 293 + 19 Bit Registers := 2 + 17 Bit Registers := 2 + 16 Bit Registers := 54 + 14 Bit Registers := 1 + 13 Bit Registers := 8 + 12 Bit Registers := 1 + 11 Bit Registers := 1 + 10 Bit Registers := 140 + 9 Bit Registers := 12 + 8 Bit Registers := 434 + 7 Bit Registers := 27 + 6 Bit Registers := 11 + 5 Bit Registers := 113 + 4 Bit Registers := 193 + 3 Bit Registers := 234 + 2 Bit Registers := 127 + 1 Bit Registers := 1664 ++---Multipliers : + 53x53 Multipliers := 1 + 73x73 Multipliers := 1 + 16x32 Multipliers := 6 + 16x39 Multipliers := 2 + 16x37 Multipliers := 1 ++---RAMs : + 64K Bit (1024 X 64 bit) RAMs := 8 + 8K Bit (256 X 32 bit) RAMs := 8 + 8K Bit (128 X 64 bit) RAMs := 8 + 2K Bit (16 X 128 bit) RAMs := 1 ++---Muxes : + 2 Input 130 Bit Muxes := 4 + 2 Input 128 Bit Muxes := 34 + 4 Input 128 Bit Muxes := 1 + 2 Input 109 Bit Muxes := 1 + 2 Input 108 Bit Muxes := 1 + 2 Input 65 Bit Muxes := 33 + 4 Input 65 Bit Muxes := 4 + 2 Input 64 Bit Muxes := 303 + 3 Input 64 Bit Muxes := 2 + 4 Input 64 Bit Muxes := 26 + 8 Input 64 Bit Muxes := 3 + 2 Input 62 Bit Muxes := 1 + 2 Input 61 Bit Muxes := 2 + 2 Input 58 Bit Muxes := 2 + 2 Input 56 Bit Muxes := 9 + 2 Input 55 Bit Muxes := 11 + 2 Input 54 Bit Muxes := 3 + 2 Input 53 Bit Muxes := 2 + 2 Input 52 Bit Muxes := 10 + 2 Input 51 Bit Muxes := 2 + 2 Input 48 Bit Muxes := 2 + 4 Input 44 Bit Muxes := 1 + 2 Input 44 Bit Muxes := 6 + 4 Input 42 Bit Muxes := 16 + 2 Input 40 Bit Muxes := 25 + 2 Input 39 Bit Muxes := 19 + 5 Input 39 Bit Muxes := 1 + 3 Input 39 Bit Muxes := 1 + 2 Input 38 Bit Muxes := 1 + 2 Input 34 Bit Muxes := 57 + 2 Input 33 Bit Muxes := 1 + 2 Input 32 Bit Muxes := 129 + 3 Input 32 Bit Muxes := 2 + 4 Input 32 Bit Muxes := 4 + 13 Input 32 Bit Muxes := 2 + 10 Input 32 Bit Muxes := 1 + 8 Input 32 Bit Muxes := 1 + 2 Input 31 Bit Muxes := 4 + 2 Input 30 Bit Muxes := 8 + 2 Input 29 Bit Muxes := 5 + 2 Input 28 Bit Muxes := 13 + 2 Input 27 Bit Muxes := 5 + 2 Input 26 Bit Muxes := 15 + 2 Input 25 Bit Muxes := 6 + 2 Input 24 Bit Muxes := 2 + 2 Input 23 Bit Muxes := 11 + 2 Input 22 Bit Muxes := 388 + 2 Input 21 Bit Muxes := 6 + 2 Input 20 Bit Muxes := 621 + 2 Input 19 Bit Muxes := 11 + 4 Input 18 Bit Muxes := 1 + 2 Input 17 Bit Muxes := 1 + 4 Input 16 Bit Muxes := 1 + 2 Input 16 Bit Muxes := 134 + 13 Input 16 Bit Muxes := 3 + 10 Input 16 Bit Muxes := 1 + 8 Input 16 Bit Muxes := 1 + 2 Input 14 Bit Muxes := 12 + 2 Input 13 Bit Muxes := 23 + 2 Input 12 Bit Muxes := 21 + 5 Input 12 Bit Muxes := 1 + 2 Input 11 Bit Muxes := 8 + 2 Input 10 Bit Muxes := 53 + 2 Input 9 Bit Muxes := 41 + 4 Input 9 Bit Muxes := 1 + 13 Input 9 Bit Muxes := 2 + 2 Input 8 Bit Muxes := 370 + 6 Input 8 Bit Muxes := 1 + 3 Input 8 Bit Muxes := 1 + 5 Input 8 Bit Muxes := 1 + 13 Input 8 Bit Muxes := 3 + 4 Input 8 Bit Muxes := 2 + 2 Input 7 Bit Muxes := 28 + 4 Input 7 Bit Muxes := 1 + 7 Input 7 Bit Muxes := 2 + 6 Input 7 Bit Muxes := 1 + 2 Input 6 Bit Muxes := 32 + 4 Input 6 Bit Muxes := 1 + 5 Input 6 Bit Muxes := 1 + 6 Input 6 Bit Muxes := 1 + 2 Input 5 Bit Muxes := 103 + 4 Input 5 Bit Muxes := 1 + 5 Input 5 Bit Muxes := 1 + 3 Input 5 Bit Muxes := 1 + 4 Input 4 Bit Muxes := 10 + 2 Input 4 Bit Muxes := 198 + 3 Input 4 Bit Muxes := 5 + 5 Input 4 Bit Muxes := 1 + 8 Input 4 Bit Muxes := 4 + 6 Input 4 Bit Muxes := 1 + 13 Input 4 Bit Muxes := 1 + 2 Input 3 Bit Muxes := 225 + 8 Input 3 Bit Muxes := 6 + 3 Input 3 Bit Muxes := 7 + 4 Input 3 Bit Muxes := 11 + 5 Input 3 Bit Muxes := 5 + 6 Input 3 Bit Muxes := 2 + 2 Input 2 Bit Muxes := 257 + 4 Input 2 Bit Muxes := 16 + 3 Input 2 Bit Muxes := 9 + 5 Input 2 Bit Muxes := 2 + 16 Input 2 Bit Muxes := 5 + 2 Input 1 Bit Muxes := 1279 + 8 Input 1 Bit Muxes := 6 + 6 Input 1 Bit Muxes := 12 + 4 Input 1 Bit Muxes := 33 + 3 Input 1 Bit Muxes := 2 + 5 Input 1 Bit Muxes := 6 + 13 Input 1 Bit Muxes := 10 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 240 (col length:80) +BRAMs: 270 (col length: RAMB18 80 RAMB36 40) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +WARNING: [Synth 8-3936] Found unconnected internal register 'subRob/sram/sram_ext/lanes[0].R0_data_reg' and it is trimmed from '1269' to '1262' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:103] +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +WARNING: [Synth 8-3917] design toy_a7_top has port flash_wp_n driven by constant 1 +WARNING: [Synth 8-3917] design toy_a7_top has port flash_hold_n driven by constant 1 +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 10 [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52365] +DSP Report: Generating DSP product_pipe_b0, operation Mode is: A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b0, operation Mode is: PCIN+A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b_reg, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +DSP Report: Generating DSP product_pipe_b0, operation Mode is: A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b0, operation Mode is: PCIN+A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b_reg, operation Mode is: (PCIN+A2*B2)'. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +DSP Report: Generating DSP product_pipe_b0, operation Mode is: A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b0, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b_reg, operation Mode is: (PCIN+A2*B2)'. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +INFO: [Synth 8-4471] merging register 'cfg_max_j_reg[15:0]' into 'cfg_max_j_reg[15:0]' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79428] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79511] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79576] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79605] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79627] +DSP Report: Generating DSP _GEN_363, operation Mode is: A2*B2. +DSP Report: register cfg_max_j_reg is absorbed into DSP _GEN_363. +DSP Report: register cfg_max_i_reg is absorbed into DSP _GEN_363. +DSP Report: operator _GEN_363 is absorbed into DSP _GEN_363. +DSP Report: Generating DSP _GEN_362, operation Mode is: A*B2. +DSP Report: register _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: operator _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: operator _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: Generating DSP _GEN_362, operation Mode is: (PCIN>>17)+A2*B. +DSP Report: register _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: operator _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: operator _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: Generating DSP io_cmd_bits_slots_0_bits_dram_addr5, operation Mode is: A2*B2. +DSP Report: register io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: register io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: operator io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: operator io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: Generating DSP io_cmd_bits_slots_0_bits_dram_addr5, operation Mode is: (PCIN>>17)+A2*B. +DSP Report: register io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: operator io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: operator io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: Generating DSP io_cmd_bits_slots_1_bits_dram_addr4, operation Mode is: A2*B. +DSP Report: register io_cmd_bits_slots_1_bits_dram_addr4 is absorbed into DSP io_cmd_bits_slots_1_bits_dram_addr4. +DSP Report: operator io_cmd_bits_slots_1_bits_dram_addr4 is absorbed into DSP io_cmd_bits_slots_1_bits_dram_addr4. +DSP Report: operator io_cmd_bits_slots_1_bits_dram_addr4 is absorbed into DSP io_cmd_bits_slots_1_bits_dram_addr4. +DSP Report: Generating DSP io_cmd_bits_slots_1_bits_dram_addr4, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_cmd_bits_slots_1_bits_dram_addr4 is absorbed into DSP io_cmd_bits_slots_1_bits_dram_addr4. +DSP Report: operator io_cmd_bits_slots_1_bits_dram_addr4 is absorbed into DSP io_cmd_bits_slots_1_bits_dram_addr4. +DSP Report: Generating DSP io_cmd_bits_slots_2_bits_dram_addr2, operation Mode is: A2*B. +DSP Report: register io_cmd_bits_slots_2_bits_dram_addr2 is absorbed into DSP io_cmd_bits_slots_2_bits_dram_addr2. +DSP Report: operator io_cmd_bits_slots_2_bits_dram_addr2 is absorbed into DSP io_cmd_bits_slots_2_bits_dram_addr2. +DSP Report: operator io_cmd_bits_slots_2_bits_dram_addr2 is absorbed into DSP io_cmd_bits_slots_2_bits_dram_addr2. +DSP Report: Generating DSP io_cmd_bits_slots_2_bits_dram_addr2, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_cmd_bits_slots_2_bits_dram_addr2 is absorbed into DSP io_cmd_bits_slots_2_bits_dram_addr2. +DSP Report: operator io_cmd_bits_slots_2_bits_dram_addr2 is absorbed into DSP io_cmd_bits_slots_2_bits_dram_addr2. +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79673] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79673] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79677] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79681] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79681] +DSP Report: Generating DSP _irow_T_7, operation Mode is: C+A*B. +DSP Report: operator _irow_T_7 is absorbed into DSP _irow_T_7. +DSP Report: operator _irow_T_71 is absorbed into DSP _irow_T_7. +DSP Report: Generating DSP io_inputAddr4, operation Mode is: A*B. +DSP Report: operator io_inputAddr4 is absorbed into DSP io_inputAddr4. +DSP Report: Generating DSP io_inputAddr5, operation Mode is: A*B. +DSP Report: operator io_inputAddr5 is absorbed into DSP io_inputAddr5. +DSP Report: Generating DSP io_inputAddr4, operation Mode is: A*B. +DSP Report: operator io_inputAddr4 is absorbed into DSP io_inputAddr4. +DSP Report: operator io_inputAddr4 is absorbed into DSP io_inputAddr4. +DSP Report: Generating DSP io_inputAddr4, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_inputAddr4 is absorbed into DSP io_inputAddr4. +DSP Report: operator io_inputAddr4 is absorbed into DSP io_inputAddr4. +DSP Report: Generating DSP _icol_T_7, operation Mode is: C+A*B. +DSP Report: operator _icol_T_7 is absorbed into DSP _icol_T_7. +DSP Report: operator _icol_T_71 is absorbed into DSP _icol_T_7. +DSP Report: Generating DSP io_inputAddr2, operation Mode is: PCIN+A:B+C. +DSP Report: operator io_inputAddr2 is absorbed into DSP io_inputAddr2. +DSP Report: Generating DSP io_inputAddr1, operation Mode is: A*B. +DSP Report: operator io_inputAddr1 is absorbed into DSP io_inputAddr1. +DSP Report: operator io_inputAddr1 is absorbed into DSP io_inputAddr1. +DSP Report: Generating DSP io_inputAddr1, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_inputAddr1 is absorbed into DSP io_inputAddr1. +DSP Report: operator io_inputAddr1 is absorbed into DSP io_inputAddr1. +DSP Report: Generating DSP io_weightAddr4, operation Mode is: C+A*B. +DSP Report: operator io_weightAddr4 is absorbed into DSP io_weightAddr4. +DSP Report: operator io_weightAddr5 is absorbed into DSP io_weightAddr4. +DSP Report: Generating DSP io_weightAddr2, operation Mode is: C+A*B. +DSP Report: operator io_weightAddr2 is absorbed into DSP io_weightAddr2. +DSP Report: operator io_weightAddr3 is absorbed into DSP io_weightAddr2. +DSP Report: Generating DSP io_weightAddr1, operation Mode is: A*B. +DSP Report: operator io_weightAddr1 is absorbed into DSP io_weightAddr1. +DSP Report: operator io_weightAddr1 is absorbed into DSP io_weightAddr1. +DSP Report: Generating DSP io_weightAddr1, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_weightAddr1 is absorbed into DSP io_weightAddr1. +DSP Report: operator io_weightAddr1 is absorbed into DSP io_weightAddr1. +DSP Report: Generating DSP io_outputAddr4, operation Mode is: A*B. +DSP Report: operator io_outputAddr4 is absorbed into DSP io_outputAddr4. +DSP Report: Generating DSP io_outputAddr5, operation Mode is: A*B. +DSP Report: operator io_outputAddr5 is absorbed into DSP io_outputAddr5. +DSP Report: Generating DSP io_outputAddr4, operation Mode is: A*B. +DSP Report: operator io_outputAddr4 is absorbed into DSP io_outputAddr4. +DSP Report: operator io_outputAddr4 is absorbed into DSP io_outputAddr4. +DSP Report: Generating DSP io_outputAddr4, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_outputAddr4 is absorbed into DSP io_outputAddr4. +DSP Report: operator io_outputAddr4 is absorbed into DSP io_outputAddr4. +DSP Report: Generating DSP io_outputAddr2, operation Mode is: PCIN+(A:0x0):B+C. +DSP Report: operator io_outputAddr2 is absorbed into DSP io_outputAddr2. +DSP Report: Generating DSP io_outputAddr1, operation Mode is: A*B. +DSP Report: operator io_outputAddr1 is absorbed into DSP io_outputAddr1. +DSP Report: operator io_outputAddr1 is absorbed into DSP io_outputAddr1. +DSP Report: Generating DSP io_outputAddr1, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_outputAddr1 is absorbed into DSP io_outputAddr1. +DSP Report: operator io_outputAddr1 is absorbed into DSP io_outputAddr1. +WARNING: [Synth 8-3936] Found unconnected internal register 'cfg_input_stride_reg' and it is trimmed from '32' to '22' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79776] +WARNING: [Synth 8-3936] Found unconnected internal register 'cfg_output_stride_reg' and it is trimmed from '32' to '24' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79780] +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_domain_id[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_domain_id[2] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_funct[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[63] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[62] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[61] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[60] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[59] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[58] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_domain_id[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_domain_id[2] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_funct[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[63] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[62] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[61] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[60] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[59] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[58] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_domain_id[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_domain_id[2] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_funct[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[63] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[62] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[61] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[60] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[59] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[58] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[4] driven by constant 0 +INFO: [Synth 8-4471] merging register 'reqReg_pixel_bytes_reg[9:0]' into 'reqReg_pixel_bytes_reg[9:0]' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86013] +DSP Report: Generating DSP rowSkip_reg, operation Mode is: (A*B)'. +DSP Report: register rowSkip_reg is absorbed into DSP rowSkip_reg. +DSP Report: operator rowSkip0 is absorbed into DSP rowSkip_reg. +DSP Report: Generating DSP readVaddr1, operation Mode is: A*B2. +DSP Report: register reqReg_pixel_bytes_reg is absorbed into DSP readVaddr1. +DSP Report: operator readVaddr1 is absorbed into DSP readVaddr1. +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 17 [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:58083] +DSP Report: Generating DSP remainder1, operation Mode is: A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [Synth 8-6430] The Block RAM "dcache/mshrs/sdq_ext/Memory_reg" may get memory collision error if read and write address collide. Use attribute (* rw_addr_collision= "yes" *) to avoid collision +WARNING: [Synth 8-3917] design BBTile__GCB2 has port io_requestor_1_resp_bits_tag[7] driven by constant 0 +WARNING: [Synth 8-3917] design BBTile__GCB2 has port io_requestor_1_resp_bits_tag[6] driven by constant 0 +WARNING: [Synth 8-3917] design BBTile__GCB2 has port io_requestor_2_resp_bits_tag[7] driven by constant 0 +WARNING: [Synth 8-3917] design BBTile__GCB2 has port io_requestor_2_resp_bits_tag[6] driven by constant 0 +WARNING: [Synth 8-3917] design BBTile__GCB2 has port auto_buffer_out_1_c_bits_source[1] driven by constant 0 +RAM Pipeline Warning: Read Address Register Found For RAM sdq_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance. +RAM Pipeline Warning: Read Address Register Found For RAM sdq_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance. +RAM Pipeline Warning: Read Address Register Found For RAM sdq_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance. +WARNING: [Synth 8-6430] The Block RAM "dcache/mshrs/sdq_ext/Memory_reg" may get memory collision error if read and write address collide. Use attribute (* rw_addr_collision= "yes" *) to avoid collision +RAM Pipeline Warning: Read Address Register Found For RAM sdq_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance. +--------------------------------------------------------------------------------- +Start Pre Area Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Iterative Area Optimization +--------------------------------------------------------------------------------- +INFO: [Synth 8-3333] propagating constant 0 across sequential element (fpmu/\io_out_pipe_b_exc_reg[3] ) +INFO: [Synth 8-3886] merging instance 'wb_toint_exc_reg[1]' (FDE) to 'wb_toint_exc_reg[3]' +INFO: [Synth 8-3886] merging instance 'wb_toint_exc_reg[2]' (FDE) to 'wb_toint_exc_reg[3]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\wb_toint_exc_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (sharedFma/\io_out_pipe_b_exc_reg[3] ) +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[47]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[46]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[45]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[44]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[43]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[42]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[41]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[40]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[39]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[38]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[37]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[36]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[35]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[34]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[33]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[32]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[31]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[30]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[29]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[28]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[27]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[26]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[25]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[24]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[23]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[22]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[21]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[47]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[46]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[45]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[44]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[43]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[42]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[41]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[40]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[39]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[38]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[37]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[36]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[35]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[34]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[33]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[32]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[31]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[30]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[29]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[28]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[27]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[26]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[25]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[24]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[23]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[22]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[21]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[20]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[19]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[18]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[17]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[47]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[46]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[45]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[44]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[43]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[42]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[41]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[40]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[39]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[38]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[37]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[36]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[35]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[34]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[33]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[32]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[31]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[30]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[29]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[28]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[27]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[26]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[25]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[24]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[23]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[22]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[21]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[20]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[19]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[18]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[17]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_15_reg[9]' (FDRE) to 'bat/entNewAlias_15_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_15_reg[6]' (FDRE) to 'bat/entNewAlias_15_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_15_reg[7]' (FDRE) to 'bat/entNewAlias_15_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_15_reg[8]' (FDRE) to 'bat/entNewAlias_15_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_15_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_14_reg[9]' (FDRE) to 'bat/entNewAlias_14_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_14_reg[6]' (FDRE) to 'bat/entNewAlias_14_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_14_reg[7]' (FDRE) to 'bat/entNewAlias_14_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_14_reg[8]' (FDRE) to 'bat/entNewAlias_14_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_14_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_13_reg[9]' (FDRE) to 'bat/entNewAlias_13_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_13_reg[6]' (FDRE) to 'bat/entNewAlias_13_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_13_reg[7]' (FDRE) to 'bat/entNewAlias_13_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_13_reg[8]' (FDRE) to 'bat/entNewAlias_13_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_13_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_12_reg[9]' (FDRE) to 'bat/entNewAlias_12_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_12_reg[6]' (FDRE) to 'bat/entNewAlias_12_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_12_reg[7]' (FDRE) to 'bat/entNewAlias_12_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_12_reg[8]' (FDRE) to 'bat/entNewAlias_12_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_12_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_11_reg[9]' (FDRE) to 'bat/entNewAlias_11_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_11_reg[6]' (FDRE) to 'bat/entNewAlias_11_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_11_reg[7]' (FDRE) to 'bat/entNewAlias_11_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_11_reg[8]' (FDRE) to 'bat/entNewAlias_11_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_11_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_10_reg[9]' (FDRE) to 'bat/entNewAlias_10_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_10_reg[6]' (FDRE) to 'bat/entNewAlias_10_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_10_reg[7]' (FDRE) to 'bat/entNewAlias_10_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_10_reg[8]' (FDRE) to 'bat/entNewAlias_10_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_10_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_9_reg[9]' (FDRE) to 'bat/entNewAlias_9_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_9_reg[6]' (FDRE) to 'bat/entNewAlias_9_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_9_reg[7]' (FDRE) to 'bat/entNewAlias_9_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_9_reg[8]' (FDRE) to 'bat/entNewAlias_9_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_9_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_8_reg[9]' (FDRE) to 'bat/entNewAlias_8_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_8_reg[6]' (FDRE) to 'bat/entNewAlias_8_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_8_reg[7]' (FDRE) to 'bat/entNewAlias_8_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_8_reg[8]' (FDRE) to 'bat/entNewAlias_8_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_8_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_7_reg[9]' (FDRE) to 'bat/entNewAlias_7_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_7_reg[6]' (FDRE) to 'bat/entNewAlias_7_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_7_reg[7]' (FDRE) to 'bat/entNewAlias_7_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_7_reg[8]' (FDRE) to 'bat/entNewAlias_7_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_7_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_6_reg[9]' (FDRE) to 'bat/entNewAlias_6_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_6_reg[6]' (FDRE) to 'bat/entNewAlias_6_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_6_reg[7]' (FDRE) to 'bat/entNewAlias_6_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_6_reg[8]' (FDRE) to 'bat/entNewAlias_6_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_6_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_5_reg[9]' (FDRE) to 'bat/entNewAlias_5_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_5_reg[6]' (FDRE) to 'bat/entNewAlias_5_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_5_reg[7]' (FDRE) to 'bat/entNewAlias_5_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_5_reg[8]' (FDRE) to 'bat/entNewAlias_5_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_5_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_4_reg[9]' (FDRE) to 'bat/entNewAlias_4_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_4_reg[6]' (FDRE) to 'bat/entNewAlias_4_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_4_reg[7]' (FDRE) to 'bat/entNewAlias_4_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_4_reg[8]' (FDRE) to 'bat/entNewAlias_4_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_4_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_3_reg[9]' (FDRE) to 'bat/entNewAlias_3_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_3_reg[6]' (FDRE) to 'bat/entNewAlias_3_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_3_reg[7]' (FDRE) to 'bat/entNewAlias_3_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_3_reg[8]' (FDRE) to 'bat/entNewAlias_3_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_3_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_2_reg[9]' (FDRE) to 'bat/entNewAlias_2_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_2_reg[6]' (FDRE) to 'bat/entNewAlias_2_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_2_reg[7]' (FDRE) to 'bat/entNewAlias_2_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_2_reg[8]' (FDRE) to 'bat/entNewAlias_2_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_2_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_1_reg[9]' (FDRE) to 'bat/entNewAlias_1_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_1_reg[6]' (FDRE) to 'bat/entNewAlias_1_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_1_reg[7]' (FDRE) to 'bat/entNewAlias_1_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_1_reg[8]' (FDRE) to 'bat/entNewAlias_1_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_1_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_0_reg[9]' (FDRE) to 'bat/entNewAlias_0_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_0_reg[6]' (FDRE) to 'bat/entNewAlias_0_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_0_reg[7]' (FDRE) to 'bat/entNewAlias_0_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_0_reg[8]' (FDRE) to 'bat/entNewAlias_0_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_0_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/v2a_15_reg[9]' (FDRE) to 'bat/v2a_15_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_14_reg[9]' (FDRE) to 'bat/v2a_14_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_13_reg[9]' (FDRE) to 'bat/v2a_13_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_12_reg[9]' (FDRE) to 'bat/v2a_12_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_11_reg[9]' (FDRE) to 'bat/v2a_11_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_10_reg[9]' (FDRE) to 'bat/v2a_10_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_9_reg[9]' (FDRE) to 'bat/v2a_9_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_8_reg[9]' (FDRE) to 'bat/v2a_8_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_7_reg[9]' (FDRE) to 'bat/v2a_7_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_6_reg[9]' (FDRE) to 'bat/v2a_6_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_5_reg[9]' (FDRE) to 'bat/v2a_5_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_4_reg[9]' (FDRE) to 'bat/v2a_4_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_3_reg[9]' (FDRE) to 'bat/v2a_3_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_2_reg[9]' (FDRE) to 'bat/v2a_2_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_1_reg[9]' (FDRE) to 'bat/v2a_1_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_0_reg[9]' (FDRE) to 'bat/v2a_0_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_15_reg[6]' (FDRE) to 'bat/v2a_15_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_14_reg[6]' (FDRE) to 'bat/v2a_14_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_13_reg[6]' (FDRE) to 'bat/v2a_13_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_12_reg[6]' (FDRE) to 'bat/v2a_12_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_11_reg[6]' (FDRE) to 'bat/v2a_11_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_10_reg[6]' (FDRE) to 'bat/v2a_10_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_9_reg[6]' (FDRE) to 'bat/v2a_9_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_8_reg[6]' (FDRE) to 'bat/v2a_8_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_7_reg[6]' (FDRE) to 'bat/v2a_7_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_6_reg[6]' (FDRE) to 'bat/v2a_6_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_5_reg[6]' (FDRE) to 'bat/v2a_5_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_4_reg[6]' (FDRE) to 'bat/v2a_4_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_3_reg[6]' (FDRE) to 'bat/v2a_3_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_2_reg[6]' (FDRE) to 'bat/v2a_2_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_1_reg[6]' (FDRE) to 'bat/v2a_1_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_0_reg[6]' (FDRE) to 'bat/v2a_0_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_15_reg[7]' (FDRE) to 'bat/v2a_15_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_14_reg[7]' (FDRE) to 'bat/v2a_14_reg[8]' +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_15_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_14_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_13_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_12_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_11_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_10_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_9_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_8_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_7_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_6_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_5_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_4_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_3_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_2_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_1_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_0_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_15_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_14_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_13_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_12_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_11_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_10_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_9_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_8_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_7_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_6_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_5_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_4_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_3_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_2_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_1_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_0_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_15_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_0_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_1_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_2_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_3_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_4_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_5_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_6_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_7_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_8_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_9_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_10_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_11_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_12_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_13_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_14_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [Synth 8-3332] Sequential element (FSM_onehot_state_reg[7]) is unused and will be removed from module MemConfiger. +WARNING: [Synth 8-3332] Sequential element (FSM_onehot_state_reg[6]) is unused and will be removed from module MemConfiger. +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\roccMemIF/s1_req_tag_reg[0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/\ex_reg_cause_reg[7] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_mie_reg[38] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_mcountinhibit_reg[1] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\roccMemIF/io_cache_s1_data_r_data_reg[63] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/reg_singleStepped_reg) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_satp_mode_reg[2] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[40] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[41] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[42] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[43] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[44] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[45] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[46] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[47] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[48] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[49] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[50] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[51] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[52] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[53] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[54] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[55] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[56] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[57] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[58] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[59] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[60] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[61] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[62] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (cores_0/csr/\reg_misa_reg[63] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[7] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[10] ) +INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_114_115 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_108_113 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_102_107 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_96_101 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_90_95 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_84_89 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_78_83 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_72_77 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_66_71 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_60_65 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_54_59 from module BBTile__GCB1 due to constant propagation +INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_114_115 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_72_77 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_66_71 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_60_65 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_54_59 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_48_53 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_42_47 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_36_41 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_30_35 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_24_29 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_18_23 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_72_77 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_10/buffer_1/nodeOut_a_q/ram_ext/Memory_reg_0_1_6_11 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_4/coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_r_deq_q/ram_ext/Memory_reg_0_1_60_65 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_4/coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_r_deq_q/ram_ext/Memory_reg_0_1_54_59 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_4/coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_r_deq_q/ram_ext/Memory_reg_0_1_48_53 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_11/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_0/ram_ext/Memory_reg_0_7_60_65 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_12/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_1/ram_ext/Memory_reg_0_7_60_65 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_13/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_2/ram_ext/Memory_reg_0_7_60_65 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_14/i_0/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_3/ram_ext/Memory_reg_0_7_60_65 from module extram__61 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_11/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_0/ram_ext/Memory_reg_0_7_54_59 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_12/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_1/ram_ext/Memory_reg_0_7_60_65 from module SystemBus due to constant propagation +--------------------------------------------------------------------------------- +Start Post Area Optimization : Time (s): cpu = 00:12:02 ; elapsed = 00:12:36 . Memory (MB): peak = 6506.113 ; gain = 3035.262 ; free physical = 468157 ; free virtual = 608469 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:12:08 ; elapsed = 00:12:42 . Memory (MB): peak = 6506.113 ; gain = 3035.262 ; free physical = 467930 ; free virtual = 608253 +--------------------------------------------------------------------------------- + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_0 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_0 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_10 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_10 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_11 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_12 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_13 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_14 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_15 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_16 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_17 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_18 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_19 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1a : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1b : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1c : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1d : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1e : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1f : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_2 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_20 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_21 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_22 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_23 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_24 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_25 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_26 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_27 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_28 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_29 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2a : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2b : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2c : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2d : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2e : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2f : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_3 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_3 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_30 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_4 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_4 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_5 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_5 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_6 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_6 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_7 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_7 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_8 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_8 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_9 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_9 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_a : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_a : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_b : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_b : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_c : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_c : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_d : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_d : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_e : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_e : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_f : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_f : 0 0 : 519 519 : Used 1 time 100 + Sort Area is BBTile__GCB0 remainder1_8 : 0 0 : 3475 13938 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_8 : 0 1 : 3494 13938 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_8 : 0 2 : 3475 13938 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_8 : 0 3 : 3494 13938 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_6 : 0 0 : 3137 13243 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_6 : 0 1 : 3475 13243 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_6 : 0 2 : 3494 13243 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_6 : 0 3 : 3137 13243 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_4 : 0 0 : 3137 12905 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_4 : 0 1 : 3137 12905 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_4 : 0 2 : 3494 12905 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_4 : 0 3 : 3137 12905 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_0 : 0 0 : 3137 12586 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_0 : 0 1 : 3156 12586 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_0 : 0 2 : 3137 12586 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_0 : 0 3 : 3156 12586 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_8 : 0 0 : 3274 9889 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_8 : 0 1 : 3274 9889 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_8 : 0 2 : 3341 9889 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_4 : 0 0 : 3274 9733 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_4 : 0 1 : 3137 9733 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_4 : 0 2 : 3322 9733 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_0 : 0 0 : 3137 9478 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_0 : 0 1 : 3156 9478 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_0 : 0 2 : 3185 9478 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr1_15 : 0 0 : 2588 5929 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr1_15 : 0 1 : 3341 5929 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_weightAddr1_1b : 0 0 : 2588 5929 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_weightAddr1_1b : 0 1 : 3341 5929 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr1_20 : 0 0 : 2588 5807 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr1_20 : 0 1 : 3219 5807 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_0_bits_dram_addr5_5 : 0 0 : 3052 5790 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_0_bits_dram_addr5_5 : 0 1 : 2738 5790 : Used 1 time 0 + Sort Area is GemminiBall__GC0 _GEN_362_2 : 0 0 : 3034 5772 : Used 1 time 0 + Sort Area is GemminiBall__GC0 _GEN_362_2 : 0 1 : 2738 5772 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_1_bits_dram_addr4_7 : 0 0 : 3035 5756 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_1_bits_dram_addr4_7 : 0 1 : 2721 5756 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_2_bits_dram_addr2_a : 0 0 : 3035 5756 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_2_bits_dram_addr2_a : 0 1 : 2721 5756 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr4_f : 0 0 : 2588 5309 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr4_f : 0 1 : 2721 5309 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr4_1d : 0 0 : 2588 5309 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr4_1d : 0 1 : 2721 5309 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr4_12 : 0 0 : 2722 2987 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr4_12 : 0 1 : 265 2987 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_weightAddr2_19 : 0 0 : 2838 2838 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr4_1e : 0 0 : 1946 2168 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr4_1e : 0 1 : 222 2168 : Used 1 time 0 + Sort Area is GemminiBall__GC0 _GEN_363_0 : 0 0 : 1978 1978 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr5_d : 0 0 : 1946 1946 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr5_1c : 0 0 : 1946 1946 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_a : 0 0 : 1207 1207 : Used 1 time 0 + Sort Area is GemminiBall__GC0 _icol_T_7_b : 0 0 : 949 949 : Used 1 time 0 + Sort Area is GemminiBall__GC0 _irow_T_7_11 : 0 0 : 949 949 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_weightAddr4_17 : 0 0 : 949 949 : Used 1 time 0 + Sort Area is MemFrontend rowSkip_reg_0 : 0 0 : 768 768 : Used 1 time 0 + Sort Area is MemFrontend readVaddr1_2 : 0 0 : 733 733 : Used 1 time 0 +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Block RAM: Preliminary Mapping Report (see note below) ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|GlobalROB__GB1 | robOperands/robOperands_ext/lanes[0].ram_reg | 16 x 128(READ_FIRST) | W | | 16 x 128(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_0 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_1 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_2 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_3 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_4 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_5 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_6 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_7 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|dcache/mshrs | sdq_ext/Memory_reg | 17 x 64(READ_FIRST) | W | | 17 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_0/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_0/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_1/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_1/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_0/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_0/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_1/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_1/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ + +Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once. + +Distributed RAM: Preliminary Mapping Report (see note below) ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ +|regfile_ext | bank0_reg | User Attribute | 32 x 65 | RAM32M x 33 | +|regfile_ext | bank1_reg | User Attribute | 32 x 65 | RAM32M x 33 | +|toy_a7_top | completeQueue/ram_ext/Memory_reg | Implied | 16 x 4 | RAM32M x 1 | +|toy_a7_top | subRob/sram/sram_ext/lanes[0].ram_reg | User Attribute | 8 x 1262 | RAM32M x 211 | +|toy_a7_top | total_rows_q/ram_ext/Memory_reg | Implied | 8 x 7 | RAM32M x 2 | +|GemminiExCtrl__GC0 | rdQueue0/ram_data_ext/Memory_reg | Implied | 8 x 64 | RAM32M x 11 | +|GemminiExCtrl__GC0 | rdQueue1/ram_data_ext/Memory_reg | Implied | 8 x 64 | RAM32M x 11 | +|toy_a7_top | ballRs/fifo/ram_ext/Memory_reg | Implied | 4 x 281 | RAM32M x 47 | +|memRs | fifo/ram_ext/Memory_reg | Implied | 4 x 158 | RAM32M x 27 | +|toy_a7_top | bankReadReqQ_q/ram_ext/Memory_reg | Implied | 8 x 21 | RAM32M x 4 | +|toy_a7_top | bankReadReqQ_q_1/ram_ext/Memory_reg | Implied | 8 x 21 | RAM32M x 4 | +|cores_0 | rf_ext/Memory_reg | Implied | 32 x 64 | RAM32M x 22 | +|BBTile__GCB0 | buffer_2/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 117 | RAM32M x 20 | +|BBTile__GCB0 | buffer_2/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 78 | RAM32M x 13 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_tag_array/bbtile_icache_tag_array_ext/lanes[0].ram_reg | User Attribute | 64 x 21 | RAM64X1S x 21 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_tag_array/bbtile_icache_tag_array_ext/lanes[1].ram_reg | User Attribute | 64 x 21 | RAM64X1S x 21 | +|BBTile__GCB1 | buffer_1/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 116 | RAM32M x 20 | +|BBTile__GCB1 | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 116 | RAM32M x 20 | +|BBTile__GCB1 | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 76 | RAM32M x 13 | +|dcache/mshrs | mshrs_0/rpq/ram_ext/Memory_reg | Implied | 16 x 64 | RAM32M x 11 | +|dcache/meta | tag_array/tag_array_ext/lanes[0].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[1].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[2].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[3].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|toy_a7_top | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 189 | RAM32M x 32 | +|toy_a7_top | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 142 | RAM32M x 24 | +|toy_a7_top | buffer/nodeOut_a_q_1/ram_ext/Memory_reg | Implied | 2 x 188 | RAM32M x 32 | +|toy_a7_top | buffer/nodeIn_d_q_1/ram_ext/Memory_reg | Implied | 2 x 142 | RAM32M x 24 | +|toy_a7_top | buffer/nodeIn_b_q/ram_ext/Memory_reg | Implied | 2 x 60 | RAM32M x 10 | +|toy_a7_top | buffer/nodeOut_c_q/ram_ext/Memory_reg | Implied | 2 x 172 | RAM32M x 29 | +|toy_a7_top | buffer/nodeOut_e_q/ram_sink_ext/Memory_reg | Implied | 2 x 1 | RAM16X1D x 1 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_aw_deq_q/ram_ext/Memory_reg | Implied | 2 x 58 | RAM32M x 10 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_w_deq_q/ram_ext/Memory_reg | Implied | 2 x 73 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_b_deq_q/ram_ext/Memory_reg | Implied | 2 x 4 | RAM32M x 1 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_ar_deq_q/ram_ext/Memory_reg | Implied | 2 x 58 | RAM32M x 10 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_r_deq_q/ram_ext/Memory_reg | Implied | 2 x 69 | RAM32M x 12 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_1/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_2/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_3/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_4/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_5/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_0/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_1/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_2/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_3/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|cbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 114 | RAM32M x 19 | +|cbus | wrapped_error_device/buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 100 | RAM32M x 17 | +|cbus | wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 79 | RAM32M x 14 | +|cbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 79 | RAM32M x 14 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_1/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_2/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_3/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_4/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_5/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_6/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_7/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_8/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_9/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_10/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_11/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_12/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_13/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_14/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_15/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_16/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_17/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_18/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_19/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_20/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_21/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_22/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_23/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_24/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_25/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_26/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_27/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_28/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_29/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_30/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_31/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|coh_wrapper | broadcast_1/TLBroadcastTracker/o_data_q/ram_ext/Memory_reg | Implied | 4 x 144 | RAM32M x 24 | +|coh_wrapper | broadcast_1/TLBroadcastTracker_1/o_data_q/ram_ext/Memory_reg | Implied | 4 x 144 | RAM32M x 24 | +|platformi_21/loader | payload_reg | User Attribute | 256 x 8 | RAM128X1D x 16 | +|platformi_21/peripherals | fifo_reg | User Attribute | 256 x 8 | RAM64M x 12 | ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ + +Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. + +DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set) ++----------------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ +|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | ++----------------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | A2*B2 | 20 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | PCIN+A2*B2 | 20 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN>>17)+A2*B2 | 20 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 1 | +|SharedMulAddRecFNPipe | A2*B2 | 20 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN+A2*B2)' | 20 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 1 | +|SharedMulAddRecFNPipe | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN>>17)+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN+A2*B2)' | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 1 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopMatmulUnroller | A2*B2 | 16 | 16 | - | - | 32 | 1 | 1 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A*B2 | 18 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | (PCIN>>17)+A2*B | 17 | 16 | - | - | 48 | 1 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A2*B2 | 18 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | (PCIN>>17)+A2*B | 17 | 16 | - | - | 48 | 1 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A2*B | 18 | 17 | - | - | 48 | 1 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | (PCIN>>17)+A*B | 17 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A2*B | 18 | 17 | - | - | 48 | 1 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | (PCIN>>17)+A*B | 17 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | C+A*B | 16 | 8 | 24 | - | 24 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 24 | 16 | - | - | 40 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 16 | 16 | - | - | 32 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 18 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | (PCIN>>17)+A*B | 17 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | C+A*B | 16 | 8 | 24 | - | 24 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN+A:B+C | 6 | 18 | 39 | - | -1 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 18 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | (PCIN>>17)+A*B | 23 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | C+A*B | 16 | 8 | 16 | - | 24 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | C+A*B | 24 | 16 | 16 | - | 39 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 18 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | (PCIN>>17)+A*B | 23 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 16 | 16 | - | - | 32 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 16 | 16 | - | - | 32 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 18 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | (PCIN>>17)+A*B | 17 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN+(A:0x0):B+C | 30 | 16 | 37 | - | -1 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 18 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | (PCIN>>17)+A*B | 21 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|StreamReader | (A*B)' | 19 | 6 | - | - | 25 | 0 | 0 | - | - | - | 1 | 0 | +|StreamReader | A*B2 | 10 | 10 | - | - | 20 | 0 | 1 | - | - | - | 0 | 0 | +|MulDiv | A2*B2 | 23 | 6 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | ++----------------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ + +Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once. +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:12:14 ; elapsed = 00:12:49 . Memory (MB): peak = 6506.113 ; gain = 3035.262 ; free physical = 466997 ; free virtual = 607433 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:12:27 ; elapsed = 00:13:02 . Memory (MB): peak = 6506.113 ; gain = 3035.262 ; free physical = 466864 ; free virtual = 607304 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Block RAM: Final Mapping Report ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|GlobalROB__GB1 | robOperands/robOperands_ext/lanes[0].ram_reg | 16 x 128(READ_FIRST) | W | | 16 x 128(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_0 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_1 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_2 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_3 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_4 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_5 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_6 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_7 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|dcache/mshrs | sdq_ext/Memory_reg | 17 x 64(READ_FIRST) | W | | 17 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_0/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_0/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_1/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_1/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_0/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_0/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_1/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_1/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ + + +Distributed RAM: Final Mapping Report ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ +|regfile_ext | bank0_reg | User Attribute | 32 x 65 | RAM32M x 33 | +|regfile_ext | bank1_reg | User Attribute | 32 x 65 | RAM32M x 33 | +|toy_a7_top | total_rows_q/ram_ext/Memory_reg | Implied | 8 x 7 | RAM32M x 2 | +|GemminiExCtrl__GC0 | rdQueue0/ram_data_ext/Memory_reg | Implied | 8 x 64 | RAM32M x 11 | +|GemminiExCtrl__GC0 | rdQueue1/ram_data_ext/Memory_reg | Implied | 8 x 64 | RAM32M x 11 | +|toy_a7_top | ballRs/fifo/ram_ext/Memory_reg | Implied | 4 x 281 | RAM32M x 47 | +|memRs | fifo/ram_ext/Memory_reg | Implied | 4 x 158 | RAM32M x 27 | +|toy_a7_top | bankReadReqQ_q/ram_ext/Memory_reg | Implied | 8 x 21 | RAM32M x 4 | +|toy_a7_top | bankReadReqQ_q_1/ram_ext/Memory_reg | Implied | 8 x 21 | RAM32M x 4 | +|toy_a7_top | completeQueue/ram_ext/Memory_reg | Implied | 16 x 4 | RAM32M x 1 | +|toy_a7_top | subRob/sram/sram_ext/lanes[0].ram_reg | User Attribute | 8 x 1262 | RAM32M x 211 | +|cores_0 | rf_ext/Memory_reg | Implied | 32 x 64 | RAM32M x 22 | +|BBTile__GCB0 | buffer_2/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 117 | RAM32M x 20 | +|BBTile__GCB0 | buffer_2/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 78 | RAM32M x 13 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_tag_array/bbtile_icache_tag_array_ext/lanes[0].ram_reg | User Attribute | 64 x 21 | RAM64X1S x 21 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_tag_array/bbtile_icache_tag_array_ext/lanes[1].ram_reg | User Attribute | 64 x 21 | RAM64X1S x 21 | +|BBTile__GCB1 | buffer_1/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 116 | RAM32M x 20 | +|BBTile__GCB1 | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 116 | RAM32M x 20 | +|BBTile__GCB1 | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 76 | RAM32M x 13 | +|dcache/mshrs | mshrs_0/rpq/ram_ext/Memory_reg | Implied | 16 x 64 | RAM32M x 11 | +|dcache/meta | tag_array/tag_array_ext/lanes[0].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[1].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[2].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[3].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|toy_a7_top | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 189 | RAM32M x 32 | +|toy_a7_top | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 142 | RAM32M x 24 | +|toy_a7_top | buffer/nodeOut_a_q_1/ram_ext/Memory_reg | Implied | 2 x 188 | RAM32M x 32 | +|toy_a7_top | buffer/nodeIn_d_q_1/ram_ext/Memory_reg | Implied | 2 x 142 | RAM32M x 24 | +|toy_a7_top | buffer/nodeIn_b_q/ram_ext/Memory_reg | Implied | 2 x 60 | RAM32M x 10 | +|toy_a7_top | buffer/nodeOut_c_q/ram_ext/Memory_reg | Implied | 2 x 172 | RAM32M x 29 | +|toy_a7_top | buffer/nodeOut_e_q/ram_sink_ext/Memory_reg | Implied | 2 x 1 | RAM16X1D x 1 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_aw_deq_q/ram_ext/Memory_reg | Implied | 2 x 58 | RAM32M x 10 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_w_deq_q/ram_ext/Memory_reg | Implied | 2 x 73 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_b_deq_q/ram_ext/Memory_reg | Implied | 2 x 4 | RAM32M x 1 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_ar_deq_q/ram_ext/Memory_reg | Implied | 2 x 58 | RAM32M x 10 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_r_deq_q/ram_ext/Memory_reg | Implied | 2 x 69 | RAM32M x 12 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_1/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_2/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_3/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_4/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_5/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_0/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_1/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_2/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_3/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|cbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 114 | RAM32M x 19 | +|cbus | wrapped_error_device/buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 100 | RAM32M x 17 | +|cbus | wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 79 | RAM32M x 14 | +|cbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 79 | RAM32M x 14 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_1/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_2/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_3/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_4/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_5/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_6/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_7/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_8/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_9/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_10/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_11/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_12/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_13/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_14/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_15/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_16/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_17/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_18/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_19/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_20/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_21/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_22/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_23/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_24/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_25/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_26/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_27/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_28/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_29/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_30/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_31/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|coh_wrapper | broadcast_1/TLBroadcastTracker/o_data_q/ram_ext/Memory_reg | Implied | 4 x 144 | RAM32M x 24 | +|coh_wrapper | broadcast_1/TLBroadcastTracker_1/o_data_q/ram_ext/Memory_reg | Implied | 4 x 144 | RAM32M x 24 | +|platformi_21/loader | payload_reg | User Attribute | 256 x 8 | RAM128X1D x 16 | +|platformi_21/peripherals | fifo_reg | User Attribute | 256 x 8 | RAM64M x 12 | ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_0/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_0/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_1/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_1/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_2/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_2/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_3/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_3/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_4/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_4/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_5/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_5/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_6/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_6/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_7/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_7/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/mshrs/sdq_ext/Memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_0/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_0/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_1/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_1/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_0/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_0/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_1/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_1/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:12:46 ; elapsed = 00:13:20 . Memory (MB): peak = 6518.039 ; gain = 3047.188 ; free physical = 466890 ; free virtual = 607336 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_0/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_0/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_1/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_1/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_2/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_2/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_3/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_3/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_4/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_4/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_5/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_5/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_6/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_6/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_7/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_7/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/mshrs/sdq_ext/Memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_0/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_0/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_1/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_1/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_0/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_0/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_1/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_1/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/frontend/scheduler/rob/itraceComp of module ITraceDPI__1 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/frontend/scheduler/rob/itraceIssue of module ITraceDPI__2 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/frontend/scheduler/rob/itraceAlloc of module ITraceDPI having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/pmc/pmcTraces_0 of module PMCTraceDPI having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/pmc/ldPmcTrace of module MemPMCTraceDPI__1 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/pmc/stPmcTrace of module MemPMCTraceDPI having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_0 of module MTraceDPI__1 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_1 of module MTraceDPI__2 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_2 of module MTraceDPI__3 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_3 of module MTraceDPI__4 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_4 of module MTraceDPI__5 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_5 of module MTraceDPI__6 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_6 of module MTraceDPI having unconnected or no output ports +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:12:55 ; elapsed = 00:13:30 . Memory (MB): peak = 6518.039 ; gain = 3047.188 ; free physical = 466689 ; free virtual = 607217 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:12:55 ; elapsed = 00:13:30 . Memory (MB): peak = 6518.039 ; gain = 3047.188 ; free physical = 466688 ; free virtual = 607216 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:13:08 ; elapsed = 00:13:43 . Memory (MB): peak = 6518.039 ; gain = 3047.188 ; free physical = 466720 ; free virtual = 607249 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:13:08 ; elapsed = 00:13:43 . Memory (MB): peak = 6518.039 ; gain = 3047.188 ; free physical = 466720 ; free virtual = 607249 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:13:10 ; elapsed = 00:13:45 . Memory (MB): peak = 6518.039 ; gain = 3047.188 ; free physical = 466713 ; free virtual = 607242 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:13:10 ; elapsed = 00:13:45 . Memory (MB): peak = 6518.039 ; gain = 3047.188 ; free physical = 466706 ; free virtual = 607235 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Static Shift Register Report: ++------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ +|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | ++------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/out_matmul_id_RegShifted_0_0_reg[2] | 16 | 3 | NO | NO | YES | 3 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_0_0_reg[19] | 7 | 20 | NO | NO | YES | 20 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_1_6_0_reg[19] | 6 | 20 | NO | NO | YES | 20 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_2_6_0_reg[19] | 5 | 20 | NO | NO | YES | 20 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_3_6_0_reg[19] | 4 | 20 | NO | NO | YES | 20 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_4_6_0_reg[19] | 3 | 20 | NO | NO | YES | 20 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/out_last_RegShifted_0_0_reg | 16 | 1 | NO | NO | YES | 1 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_3_0_reg[7] | 3 | 8 | NO | NO | YES | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_4_0_reg[7] | 4 | 8 | NO | NO | YES | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_5_0_reg[7] | 5 | 8 | NO | NO | YES | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_6_0_reg[7] | 6 | 8 | NO | NO | YES | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_7_0_reg[7] | 7 | 8 | NO | NO | YES | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_3_1_0_reg[7] | 3 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_4_1_0_reg[7] | 4 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_5_1_0_reg[7] | 5 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_6_1_0_reg[7] | 6 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_7_1_0_reg[7] | 7 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_3_2_0_reg[7] | 3 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_4_2_0_reg[7] | 4 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_5_2_0_reg[7] | 5 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_6_2_0_reg[7] | 6 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_7_2_0_reg[7] | 7 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/ibus_intsink/chain/output_chain/sync_0_reg | 3 | 1 | NO | NO | YES | 1 | 0 | ++------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +DSP Final Report (the ' indicates corresponding REG is set) ++----------------------+--------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ +|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | ++----------------------+--------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ +|LoopConvAddrGen | C'+A'*B'' | 16 | 8 | 24 | - | 24 | 1 | 2 | 2 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 24 | 16 | - | - | 40 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A'*B'' | 16 | 16 | - | - | 32 | 1 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN>>17+A''*B | 16 | 15 | - | - | 48 | 2 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | C'+A'*B'' | 16 | 8 | 24 | - | 24 | 1 | 2 | 2 | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN+A:B+C | 6 | 18 | - | - | 39 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN>>17+A*B'' | 22 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | C'+A'*B'' | 16 | 8 | 16 | - | 24 | 1 | 2 | 2 | - | - | 0 | 0 | +|LoopConvAddrGen | C'+A*B'' | 24 | 16 | 16 | - | 39 | 0 | 2 | 2 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN>>17+A*B'' | 22 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A'*B'' | 16 | 16 | - | - | 32 | 1 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A'*B'' | 16 | 16 | - | - | 32 | 1 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN>>17+A''*B | 16 | 15 | - | - | 48 | 2 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN+A:B'+C | 0 | 16 | - | - | 37 | 0 | 1 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN>>17+A*B'' | 20 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|FpgaDspMac | C+A'*B | 30 | 18 | 48 | - | 20 | 1 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|LoopMatmulUnroller | A''*B'' | 16 | 16 | - | - | 32 | 2 | 2 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | PCIN>>17+A''*B | 16 | 15 | - | - | 48 | 2 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A''*B' | 17 | 16 | - | - | 48 | 2 | 1 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | PCIN>>17+A'*B'' | 16 | 15 | - | - | 48 | 1 | 2 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A''*B | 17 | 16 | - | - | 48 | 2 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | PCIN>>17+A*B'' | 16 | 15 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A''*B | 17 | 16 | - | - | 48 | 2 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | PCIN>>17+A*B'' | 16 | 15 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|StreamReader | (A*B')' | 19 | 4 | - | - | 25 | 0 | 1 | - | - | - | 0 | 1 | +|StreamReader | A*B' | 10 | 10 | - | - | 20 | 0 | 1 | - | - | - | 0 | 0 | +|MulDiv | A'*B' | 22 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A'*B' | 17 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A'*B' | 22 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN>>17+A'*B' | 22 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A'*B' | 17 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN>>17+A'*B' | 22 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN>>17+A'*B' | 17 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN>>17+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | A'*B' | 19 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | PCIN+A'*B'' | 19 | 17 | - | - | 48 | 1 | 2 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN>>17+A'*B'')' | 19 | 17 | - | - | 48 | 1 | 2 | - | - | - | 0 | 1 | +|SharedMulAddRecFNPipe | A'*B' | 19 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | PCIN+A'*B'' | 17 | 17 | - | - | 0 | 1 | 2 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN+A'*B'')' | 19 | 17 | - | - | 48 | 1 | 2 | - | - | - | 0 | 1 | +|SharedMulAddRecFNPipe | A'*B'' | 17 | 17 | - | - | 48 | 1 | 2 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | PCIN>>17+A'*B'' | 17 | 17 | - | - | 0 | 1 | 2 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN+A'*B'')' | 17 | 17 | - | - | 48 | 1 | 2 | - | - | - | 0 | 1 | ++----------------------+--------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ + + +Report BlackBoxes: ++------+--------------+----------+ +| |BlackBox name |Instances | ++------+--------------+----------+ +|1 |toy_axi_cdc | 1| +|2 |arty_ddr3 | 1| ++------+--------------+----------+ + +Report Cell Usage: ++------+------------+------+ +| |Cell |Count | ++------+------------+------+ +|1 |arty_ddr3 | 1| +|2 |toy_axi_cdc | 1| +|3 |BUFG | 4| +|4 |CARRY4 | 1950| +|5 |DSP48E1 | 117| +|18 |LUT1 | 817| +|19 |LUT2 | 4360| +|20 |LUT3 | 12197| +|21 |LUT4 | 10130| +|22 |LUT5 | 12422| +|23 |LUT6 | 18450| +|24 |MMCME2_BASE | 1| +|25 |MUXF7 | 629| +|26 |MUXF8 | 112| +|27 |RAM128X1D | 16| +|28 |RAM16X1D | 1| +|29 |RAM32M | 665| +|30 |RAM32X1D | 21| +|31 |RAM32X1S | 92| +|32 |RAM64M | 12| +|33 |RAM64X1S | 42| +|34 |RAMB18E1 | 8| +|35 |RAMB36E1 | 27| +|38 |SRL16E | 225| +|39 |FDCE | 8| +|40 |FDPE | 6| +|41 |FDRE | 28184| +|42 |FDSE | 457| +|43 |IBUF | 4| +|44 |OBUF | 9| ++------+------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:13:10 ; elapsed = 00:13:45 . Memory (MB): peak = 6518.039 ; gain = 3047.188 ; free physical = 466706 ; free virtual = 607235 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 571 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:12:56 ; elapsed = 00:13:37 . Memory (MB): peak = 6518.039 ; gain = 2875.582 ; free physical = 474549 ; free virtual = 615080 +Synthesis Optimization Complete : Time (s): cpu = 00:13:13 ; elapsed = 00:13:48 . Memory (MB): peak = 6518.039 ; gain = 3047.188 ; free physical = 474565 ; free virtual = 615078 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Project 1-454] Reading design checkpoint '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc.dcp' for cell 'memory_cdc' +INFO: [Project 1-454] Reading design checkpoint '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3.dcp' for cell 'ddr_controller' +Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 6518.039 ; gain = 0.000 ; free physical = 474568 ; free virtual = 615080 +INFO: [Netlist 29-17] Analyzing 4089 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2024.1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] for cell 'ddr_controller' +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] for cell 'ddr_controller' +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/arty_a7.xdc] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/arty_a7.xdc] +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/flash_boot.xdc] +CRITICAL WARNING: [Designutils 20-1307] Command 'if' is not supported in the xdc constraint file. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/flash_boot.xdc:11] +CRITICAL WARNING: [Designutils 20-1307] Command 'if' is not supported in the xdc constraint file. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/flash_boot.xdc:15] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/flash_boot.xdc] +INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3.dcp' +INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc.dcp' +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc] for cell 'memory_cdc/inst' +INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:16] +INFO: [Timing 38-2] Deriving generated clocks [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:16] +all_fanout: Time (s): cpu = 00:00:14 ; elapsed = 00:00:06 . Memory (MB): peak = 6518.039 ; gain = 0.000 ; free physical = 474581 ; free virtual = 615093 +WARNING: [Vivado_Tcl 4-2057] Waiver ID 'LUTAR-1' object list specifies likely unusable hierarchical instance 'memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:30] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:35] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:39] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:42] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:45] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:49] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:52] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:56] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:60] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:63] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:66] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:70] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc] for cell 'memory_cdc/inst' +INFO: [Project 1-1714] 33 XPM XDC files have been applied to the design. +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-1687] 16 scoped IP constraints or related sub-commands were skipped due to synthesis logic optimizations usually triggered by constant connectivity or unconnected output pins. To review the skipped constraints and messages, run the command 'set_param netlist.IPMsgFiltering false' before opening the design. +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 6518.039 ; gain = 0.000 ; free physical = 474560 ; free virtual = 615073 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 1054 instances were transformed. + IOBUFDS_INTERMDISABLE => IOBUFDS_INTERMDISABLE (IBUFDS_INTERMDISABLE_INT(x2), INV, OBUFTDS(x2)): 2 instances + IOBUF_INTERMDISABLE => IOBUF_INTERMDISABLE (IBUF_INTERMDISABLE, OBUFT): 16 instances + MMCME2_BASE => MMCME2_ADV: 1 instance + OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 1 instance + RAM128X1D => RAM128X1D (MUXF7(x2), RAMD64E(x4)): 16 instances + RAM16X1D => RAM32X1D (RAMD32(x2)): 1 instance + RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 845 instances + RAM32X1D => RAM32X1D (RAMD32(x2)): 26 instances + RAM32X1S => RAM32X1S (RAMS32): 92 instances + RAM64M => RAM64M (RAMD64E(x4)): 12 instances + RAM64X1S => RAM64X1S (RAMS64E): 42 instances + +Synth Design complete | Checksum: 2dfdb574 +INFO: [Common 17-83] Releasing license: Synthesis +608 Infos, 466 Warnings, 4 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:13:44 ; elapsed = 00:14:10 . Memory (MB): peak = 6518.039 ; gain = 3047.309 ; free physical = 474561 ; free virtual = 615074 +INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 13700.579; main = 5845.433; forked = 8252.530 +INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 19180.555; main = 6514.125; forked = 12666.434 +# write_checkpoint -force $out/synthesized.dcp +INFO: [Timing 38-480] Writing timing data to binary archive. +Wrote PlaceDB: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6538.129 ; gain = 0.000 ; free physical = 474561 ; free virtual = 615074 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6538.129 ; gain = 0.000 ; free physical = 474561 ; free virtual = 615074 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.02 . Memory (MB): peak = 6538.129 ; gain = 0.000 ; free physical = 474561 ; free virtual = 615074 +Wrote Netlist Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 6538.129 ; gain = 0.000 ; free physical = 474561 ; free virtual = 615074 +Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 6538.129 ; gain = 0.000 ; free physical = 474560 ; free virtual = 615074 +Write Physdb Complete: Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.03 . Memory (MB): peak = 6538.129 ; gain = 0.000 ; free physical = 474560 ; free virtual = 615074 +Write ShapeDB Complete: Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.09 . Memory (MB): peak = 6538.129 ; gain = 0.000 ; free physical = 474553 ; free virtual = 615074 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/synthesized.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 6538.129 ; gain = 20.090 ; free physical = 474489 ; free virtual = 615068 +# report_utilization -file $out/synth-utilization.rpt +# report_utilization -hierarchical -file $out/synth-hierarchy.rpt +# report_timing_summary -delay_type min_max -file $out/synth-timing.rpt +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. +report_timing_summary: Time (s): cpu = 00:00:20 ; elapsed = 00:00:06 . Memory (MB): peak = 6538.129 ; gain = 0.000 ; free physical = 474378 ; free virtual = 614957 +# set unresolved [get_cells -hier -quiet -filter {IS_BLACKBOX == 1}] +# if {[llength $unresolved]} {error "Unresolved black boxes: $unresolved"} +# phase OPTIMIZE +BOARD_PHASE OPTIMIZE +# opt_design -directive ExploreArea +Command: opt_design -directive ExploreArea +INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: ExploreArea +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 8 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.74 . Memory (MB): peak = 6570.145 ; gain = 32.016 ; free physical = 474363 ; free virtual = 614942 + +Starting Logic Optimization Task + +Phase 1 Initialization + +Phase 1.1 Core Generation And Design Setup +Phase 1.1 Core Generation And Design Setup | Checksum: 24b21dee2 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 474154 ; free virtual = 614733 + +Phase 1.2 Setup Constraints And Sort Netlist +Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 24b21dee2 + +Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 474146 ; free virtual = 614725 +Phase 1 Initialization | Checksum: 24b21dee2 + +Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.05 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 474146 ; free virtual = 614725 + +Phase 2 Timer Update And Timing Data Collection + +Phase 2.1 Timer Update +Phase 2.1 Timer Update | Checksum: 24b21dee2 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 473991 ; free virtual = 614570 + +Phase 2.2 Timing Data Collection +Phase 2.2 Timing Data Collection | Checksum: 24b21dee2 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 473983 ; free virtual = 614562 +Phase 2 Timer Update And Timing Data Collection | Checksum: 24b21dee2 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 473983 ; free virtual = 614562 + +Phase 3 Retarget +INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0 +INFO: [Opt 31-1566] Pulled 311 inverters resulting in an inversion of 2868 pins +INFO: [Opt 31-138] Pushed 8 inverter(s) to 9 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 3 Retarget | Checksum: 21a22d777 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 473922 ; free virtual = 614502 +Retarget | Checksum: 21a22d777 +INFO: [Opt 31-389] Phase Retarget created 97 cells and removed 603 cells +INFO: [Opt 31-1021] In phase Retarget, 52 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 4 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 4 Constant propagation | Checksum: 2d2bd90bb + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 473896 ; free virtual = 614496 +Constant propagation | Checksum: 2d2bd90bb +INFO: [Opt 31-389] Phase Constant propagation created 12 cells and removed 19 cells +INFO: [Opt 31-1021] In phase Constant propagation, 30 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 5 Sweep +Phase 5 Sweep | Checksum: 2d6232e06 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 473899 ; free virtual = 614500 +Sweep | Checksum: 2d6232e06 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 333 cells +INFO: [Opt 31-1021] In phase Sweep, 150 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 6 BUFG optimization +Phase 6 BUFG optimization | Checksum: 264ce99c3 + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 473900 ; free virtual = 614501 +BUFG optimization | Checksum: 264ce99c3 +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. + +Phase 7 Shift Register Optimization +INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs +Phase 7 Shift Register Optimization | Checksum: 264ce99c3 + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 473900 ; free virtual = 614500 +Shift Register Optimization | Checksum: 264ce99c3 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells +INFO: [Opt 31-1555] control_set_opt supports Versal devices only, and device 7a100t is unsupported + +Phase 8 Resynthesis +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Opt 31-74] Optimized 105 modules. +INFO: [Opt 31-75] Optimized module 'AccPipe'. +INFO: [Opt 31-75] Optimized module 'AccPipe_11'. +INFO: [Opt 31-75] Optimized module 'AccPipe_12'. +INFO: [Opt 31-75] Optimized module 'AccPipe_13'. +INFO: [Opt 31-75] Optimized module 'AccPipe_14'. +INFO: [Opt 31-75] Optimized module 'AccPipe_15'. +INFO: [Opt 31-75] Optimized module 'AccPipe_16'. +INFO: [Opt 31-75] Optimized module 'BankScoreboard'. +INFO: [Opt 31-75] Optimized module 'DTLB'. +INFO: [Opt 31-75] Optimized module 'DivSqrtRawFN_small_e8_s24'. +INFO: [Opt 31-75] Optimized module 'FPToInt'. +INFO: [Opt 31-75] Optimized module 'GemminiExCtrl'. +INFO: [Opt 31-75] Optimized module 'IBuf'. +INFO: [Opt 31-75] Optimized module 'ICache'. +INFO: [Opt 31-75] Optimized module 'ITLB'. +INFO: [Opt 31-75] Optimized module 'LoopConvUnroller'. +INFO: [Opt 31-75] Optimized module 'MaxPeriodFibonacciLFSR_3'. +INFO: [Opt 31-75] Optimized module 'MemConfiger'. +INFO: [Opt 31-75] Optimized module 'MemMidend'. +INFO: [Opt 31-75] Optimized module 'MeshWithDelays'. +INFO: [Opt 31-75] Optimized module 'NonBlockingDCache'. +INFO: [Opt 31-75] Optimized module 'PE_64_186'. +INFO: [Opt 31-75] Optimized module 'PE_64_189'. +INFO: [Opt 31-75] Optimized module 'PE_64_192'. +INFO: [Opt 31-75] Optimized module 'PE_64_195'. +INFO: [Opt 31-75] Optimized module 'PE_64_198'. +INFO: [Opt 31-75] Optimized module 'PE_64_201'. +INFO: [Opt 31-75] Optimized module 'PE_64_204'. +INFO: [Opt 31-75] Optimized module 'PE_64_207'. +INFO: [Opt 31-75] Optimized module 'PE_64_210'. +INFO: [Opt 31-75] Optimized module 'PE_64_213'. +INFO: [Opt 31-75] Optimized module 'PE_64_216'. +INFO: [Opt 31-75] Optimized module 'PE_64_219'. +INFO: [Opt 31-75] Optimized module 'PE_64_222'. +INFO: [Opt 31-75] Optimized module 'PE_64_225'. +INFO: [Opt 31-75] Optimized module 'PE_64_228'. +INFO: [Opt 31-75] Optimized module 'PE_64_231'. +INFO: [Opt 31-75] Optimized module 'PE_64_234'. +INFO: [Opt 31-75] Optimized module 'PE_64_237'. +INFO: [Opt 31-75] Optimized module 'PE_64_240'. +INFO: [Opt 31-75] Optimized module 'PE_64_243'. +INFO: [Opt 31-75] Optimized module 'PE_64_246'. +INFO: [Opt 31-75] Optimized module 'PE_64_249'. +INFO: [Opt 31-75] Optimized module 'PE_64_252'. +INFO: [Opt 31-75] Optimized module 'PE_64_255'. +INFO: [Opt 31-75] Optimized module 'PE_64_258'. +INFO: [Opt 31-75] Optimized module 'PE_64_261'. +INFO: [Opt 31-75] Optimized module 'PE_64_264'. +INFO: [Opt 31-75] Optimized module 'PE_64_267'. +INFO: [Opt 31-75] Optimized module 'PE_64_270'. +INFO: [Opt 31-75] Optimized module 'PE_64_273'. +INFO: [Opt 31-75] Optimized module 'PE_64_276'. +INFO: [Opt 31-75] Optimized module 'PE_64_279'. +INFO: [Opt 31-75] Optimized module 'PE_64_282'. +INFO: [Opt 31-75] Optimized module 'PE_64_285'. +INFO: [Opt 31-75] Optimized module 'PE_64_288'. +INFO: [Opt 31-75] Optimized module 'PE_64_291'. +INFO: [Opt 31-75] Optimized module 'PE_64_294'. +INFO: [Opt 31-75] Optimized module 'PE_64_297'. +INFO: [Opt 31-75] Optimized module 'PE_64_300'. +INFO: [Opt 31-75] Optimized module 'PE_64_303'. +INFO: [Opt 31-75] Optimized module 'PE_64_306'. +INFO: [Opt 31-75] Optimized module 'PE_64_309'. +INFO: [Opt 31-75] Optimized module 'PE_64_312'. +INFO: [Opt 31-75] Optimized module 'PE_64_315'. +INFO: [Opt 31-75] Optimized module 'PE_64_318'. +INFO: [Opt 31-75] Optimized module 'PE_64_321'. +INFO: [Opt 31-75] Optimized module 'PE_64_324'. +INFO: [Opt 31-75] Optimized module 'PE_64_327'. +INFO: [Opt 31-75] Optimized module 'PE_64_330'. +INFO: [Opt 31-75] Optimized module 'PE_64_333'. +INFO: [Opt 31-75] Optimized module 'PE_64_336'. +INFO: [Opt 31-75] Optimized module 'PE_64_339'. +INFO: [Opt 31-75] Optimized module 'PE_64_342'. +INFO: [Opt 31-75] Optimized module 'PE_64_345'. +INFO: [Opt 31-75] Optimized module 'PE_64_348'. +INFO: [Opt 31-75] Optimized module 'PE_64_351'. +INFO: [Opt 31-75] Optimized module 'PE_64_354'. +INFO: [Opt 31-75] Optimized module 'Queue16_ReplayInternal'. +INFO: [Opt 31-75] Optimized module 'Queue1_RegMapperInput_i23_m8'. +INFO: [Opt 31-75] Optimized module 'Queue4_TLBroadcastData'. +INFO: [Opt 31-75] Optimized module 'Queue8_SramReadResp_39'. +INFO: [Opt 31-75] Optimized module 'Repeater_TLBundleA_a17d64s3k1z3u'. +INFO: [Opt 31-75] Optimized module 'ShiftQueue'. +INFO: [Opt 31-75] Optimized module 'SubROB'. +INFO: [Opt 31-75] Optimized module 'TLB'. +INFO: [Opt 31-75] Optimized module 'TLXbar_sbus_i2_o3_a32d128s3k1z4c'. +INFO: [Opt 31-75] Optimized module 'TagQueue'. +INFO: [Opt 31-75] Optimized module 'WritebackUnit'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_axi_mc_wr_cmd_fsm'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_bank_state__parameterized2'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_ddr_if_post_fifo'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_ddr_phy_rdlvl'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_ddr_phy_wrcal'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_rank_common'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_round_robin_arb'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_tempmon'. +INFO: [Opt 31-75] Optimized module 'axi_fullwidth'. +INFO: [Opt 31-75] Optimized module 'ram_2x58'. +INFO: [Opt 31-75] Optimized module 'ram_2x58_376'. +INFO: [Common 17-14] Message 'Opt 31-75' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Opt 31-1566] Pulled 2280 inverters resulting in an inversion of 7908 pins +INFO: [Opt 31-138] Pushed 4 inverter(s) to 19 load pin(s). +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 8 Resynthesis | Checksum: 23ff3679c + +Time (s): cpu = 00:02:41 ; elapsed = 00:00:53 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 472072 ; free virtual = 612675 +Resynthesis | Checksum: 23ff3679c +INFO: [Opt 31-389] Phase Resynthesis created 19062 cells and removed 19811 cells +INFO: [Opt 31-1021] In phase Resynthesis, 151 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 9 Post Processing Netlist +Phase 9 Post Processing Netlist | Checksum: 23ff3679c + +Time (s): cpu = 00:02:41 ; elapsed = 00:00:53 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 472074 ; free virtual = 612678 +Post Processing Netlist | Checksum: 23ff3679c +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells +INFO: [Opt 31-1021] In phase Post Processing Netlist, 45 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 10 Finalization + +Phase 10.1 Finalizing Design Cores and Updating Shapes +Phase 10.1 Finalizing Design Cores and Updating Shapes | Checksum: 1a072e151 + +Time (s): cpu = 00:02:42 ; elapsed = 00:00:54 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 472083 ; free virtual = 612686 + +Phase 10.2 Verifying Netlist Connectivity + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.12 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 471942 ; free virtual = 612545 +Phase 10.2 Verifying Netlist Connectivity | Checksum: 1a072e151 + +Time (s): cpu = 00:02:42 ; elapsed = 00:00:54 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 471934 ; free virtual = 612537 +Phase 10 Finalization | Checksum: 1a072e151 + +Time (s): cpu = 00:02:42 ; elapsed = 00:00:54 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 471926 ; free virtual = 612529 +Opt_design Change Summary +========================= + + +------------------------------------------------------------------------------------------------------------------------- +| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | +------------------------------------------------------------------------------------------------------------------------- +| Retarget | 97 | 603 | 52 | +| Constant propagation | 12 | 19 | 30 | +| Sweep | 0 | 333 | 150 | +| BUFG optimization | 0 | 0 | 0 | +| Shift Register Optimization | 0 | 0 | 0 | +| Resynthesis | 19062 | 19811 | 151 | +| Post Processing Netlist | 0 | 0 | 45 | +------------------------------------------------------------------------------------------------------------------------- + + +Ending Logic Optimization Task | Checksum: 1a072e151 + +Time (s): cpu = 00:02:42 ; elapsed = 00:00:54 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 471926 ; free virtual = 612529 + +Starting Netlist Obfuscation Task +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 471723 ; free virtual = 612326 +Ending Netlist Obfuscation Task | Checksum: 1a072e151 + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 471715 ; free virtual = 612318 +INFO: [Common 17-83] Releasing license: Implementation +131 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:02:46 ; elapsed = 00:00:56 . Memory (MB): peak = 6570.145 ; gain = 32.016 ; free physical = 471661 ; free virtual = 612265 +# write_checkpoint -force $out/optimized.dcp +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-480] Writing timing data to binary archive. +Wrote PlaceDB: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470083 ; free virtual = 610686 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470083 ; free virtual = 610686 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.02 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470082 ; free virtual = 610686 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470082 ; free virtual = 610686 +Wrote Device Cache: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470082 ; free virtual = 610687 +Write Physdb Complete: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.03 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470081 ; free virtual = 610686 +Write ShapeDB Complete: Time (s): cpu = 00:00:00.43 ; elapsed = 00:00:00.11 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470074 ; free virtual = 610689 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/optimized.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:19 ; elapsed = 00:00:12 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470006 ; free virtual = 610681 +# report_utilization -file $out/opt-utilization.rpt +# phase PLACE +BOARD_PHASE PLACE +# place_design -directive Explore +Command: place_design -directive Explore +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-83] Releasing license: Implementation +INFO: [DRC 23-27] Running DRC with 8 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +INFO: [Vivado_Tcl 4-2302] The placer was invoked with the 'Explore' directive. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 8 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs + +Starting Placer Task + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470014 ; free virtual = 610691 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 14f5d1a2b + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470014 ; free virtual = 610691 +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470013 ; free virtual = 610690 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 17dfc4ae4 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470042 ; free virtual = 610722 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 189c2ca53 + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:12 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 470095 ; free virtual = 610790 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 189c2ca53 + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:12 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 470095 ; free virtual = 610790 +Phase 1 Placer Initialization | Checksum: 189c2ca53 + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:12 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 470095 ; free virtual = 610791 + +Phase 2 Global Placement + +Phase 2.1 Floorplanning +Phase 2.1 Floorplanning | Checksum: 20bb1dab5 + +Time (s): cpu = 00:00:34 ; elapsed = 00:00:14 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 470120 ; free virtual = 610816 + +Phase 2.2 Update Timing before SLR Path Opt +Phase 2.2 Update Timing before SLR Path Opt | Checksum: 2286fe973 + +Time (s): cpu = 00:00:40 ; elapsed = 00:00:17 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 470140 ; free virtual = 610839 + +Phase 2.3 Post-Processing in Floorplanning +Phase 2.3 Post-Processing in Floorplanning | Checksum: 2286fe973 + +Time (s): cpu = 00:00:41 ; elapsed = 00:00:17 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 470127 ; free virtual = 610826 + +Phase 2.4 Global Placement Core + +Phase 2.4.1 UpdateTiming Before Physical Synthesis +Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 1a630b68c + +Time (s): cpu = 00:02:11 ; elapsed = 00:00:50 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 470167 ; free virtual = 610887 + +Phase 2.4.2 Physical Synthesis In Placer +INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 5152 LUT instances to create LUTNM shape +INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0 +INFO: [Physopt 32-1138] End 1 Pass. Optimized 2204 nets or LUTs. Breaked 0 LUT, combined 2204 existing LUTs and moved 0 existing LUT +INFO: [Physopt 32-65] No nets found for high-fanout optimization. +INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. +INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed. +INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. +INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. +INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed. +INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 470052 ; free virtual = 610865 + +Summary of Physical Synthesis Optimizations +============================================ + + +----------------------------------------------------------------------------------------------------------------------------------------------------------- +| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | +----------------------------------------------------------------------------------------------------------------------------------------------------------- +| LUT Combining | 0 | 2204 | 2204 | 0 | 1 | 00:00:02 | +| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Total | 0 | 2204 | 2204 | 0 | 4 | 00:00:02 | +----------------------------------------------------------------------------------------------------------------------------------------------------------- + + +Phase 2.4.2 Physical Synthesis In Placer | Checksum: 2a3298b58 + +Time (s): cpu = 00:02:21 ; elapsed = 00:00:55 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 469384 ; free virtual = 610551 +Phase 2.4 Global Placement Core | Checksum: 28e960a12 + +Time (s): cpu = 00:02:34 ; elapsed = 00:01:00 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 469678 ; free virtual = 610874 +Phase 2 Global Placement | Checksum: 28e960a12 + +Time (s): cpu = 00:02:34 ; elapsed = 00:01:01 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 469678 ; free virtual = 610874 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 2ba6ea6d8 + +Time (s): cpu = 00:02:41 ; elapsed = 00:01:03 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 469681 ; free virtual = 610876 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 2733bb972 + +Time (s): cpu = 00:02:53 ; elapsed = 00:01:07 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 469671 ; free virtual = 610867 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 27d09f09c + +Time (s): cpu = 00:02:54 ; elapsed = 00:01:08 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 469668 ; free virtual = 610864 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 280076c81 + +Time (s): cpu = 00:02:54 ; elapsed = 00:01:08 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 469675 ; free virtual = 610871 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 274e2b06e + +Time (s): cpu = 00:03:15 ; elapsed = 00:01:28 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 465571 ; free virtual = 607195 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 2462932d4 + +Time (s): cpu = 00:03:17 ; elapsed = 00:01:30 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 465456 ; free virtual = 607080 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 3265b2010 + +Time (s): cpu = 00:03:17 ; elapsed = 00:01:30 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 465404 ; free virtual = 607046 +Phase 3 Detail Placement | Checksum: 3265b2010 + +Time (s): cpu = 00:03:18 ; elapsed = 00:01:31 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 465246 ; free virtual = 606904 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Phase 4.1.1 Post Placement Optimization +Post Placement Optimization Initialization | Checksum: 260892d3c + +Phase 4.1.1.1 BUFG Insertion + +Starting Physical Synthesis Task + +Phase 1 Physical Synthesis Initialization +INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=1.277 | TNS=0.000 | +Phase 1 Physical Synthesis Initialization | Checksum: 1113813e2 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 459558 ; free virtual = 602864 +INFO: [Place 46-33] Processed net platform/loader/SR[0], BUFG insertion was skipped due to placement/routing conflicts. +INFO: [Place 46-56] BUFG insertion identified 1 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 1, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. +Ending Physical Synthesis Task | Checksum: 1f7ac6828 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 455937 ; free virtual = 600446 +Phase 4.1.1.1 BUFG Insertion | Checksum: 260892d3c + +Time (s): cpu = 00:03:51 ; elapsed = 00:01:43 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 454364 ; free virtual = 599397 + +Phase 4.1.1.2 Post Placement Timing Optimization +INFO: [Place 30-746] Post Placement Timing Summary WNS=1.277. For the most accurate timing information please run report_timing. +Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 29d6b1f6b + +Time (s): cpu = 00:03:53 ; elapsed = 00:01:44 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 452011 ; free virtual = 597821 + +Time (s): cpu = 00:03:53 ; elapsed = 00:01:44 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 452010 ; free virtual = 597821 +Phase 4.1 Post Commit Optimization | Checksum: 29d6b1f6b + +Time (s): cpu = 00:03:53 ; elapsed = 00:01:44 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 450421 ; free virtual = 596761 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 29d6b1f6b + +Time (s): cpu = 00:03:54 ; elapsed = 00:01:45 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 448028 ; free virtual = 595156 + +Phase 4.3 Placer Reporting + +Phase 4.3.1 Print Estimated Congestion +INFO: [Place 30-612] Post-Placement Estimated Congestion + ____________________________________________________ +| | Global Congestion | Short Congestion | +| Direction | Region Size | Region Size | +|___________|___________________|___________________| +| North| 1x1| 8x8| +|___________|___________________|___________________| +| South| 2x2| 8x8| +|___________|___________________|___________________| +| East| 2x2| 8x8| +|___________|___________________|___________________| +| West| 1x1| 2x2| +|___________|___________________|___________________| + +Phase 4.3.1 Print Estimated Congestion | Checksum: 29d6b1f6b + +Time (s): cpu = 00:03:55 ; elapsed = 00:01:45 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 446097 ; free virtual = 593864 +Phase 4.3 Placer Reporting | Checksum: 29d6b1f6b + +Time (s): cpu = 00:03:55 ; elapsed = 00:01:46 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 444507 ; free virtual = 592800 + +Phase 4.4 Final Placement Cleanup +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 444337 ; free virtual = 592687 + +Time (s): cpu = 00:03:55 ; elapsed = 00:01:46 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 444336 ; free virtual = 592686 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 2e4b25a14 + +Time (s): cpu = 00:03:55 ; elapsed = 00:01:46 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 442564 ; free virtual = 591473 +Ending Placer Task | Checksum: 1eddddbab + +Time (s): cpu = 00:03:56 ; elapsed = 00:01:46 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 441290 ; free virtual = 590627 +30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +place_design: Time (s): cpu = 00:04:00 ; elapsed = 00:01:48 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 440996 ; free virtual = 590428 +# write_checkpoint -force $out/placed.dcp +INFO: [Timing 38-480] Writing timing data to binary archive. +Write ShapeDB Complete: Time (s): cpu = 00:00:00.75 ; elapsed = 00:00:00.16 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 440814 ; free virtual = 590264 +Wrote PlaceDB: Time (s): cpu = 00:00:09 ; elapsed = 00:00:03 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 451981 ; free virtual = 601581 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 451981 ; free virtual = 601581 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 452075 ; free virtual = 601675 +Wrote Netlist Cache: Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.1 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 452552 ; free virtual = 602161 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 452552 ; free virtual = 602161 +Write Physdb Complete: Time (s): cpu = 00:00:09 ; elapsed = 00:00:03 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 452552 ; free virtual = 602161 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/placed.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:16 ; elapsed = 00:00:11 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 453042 ; free virtual = 603197 +# phase PHYS_OPT +BOARD_PHASE PHYS_OPT +# phys_opt_design -directive Explore +Command: phys_opt_design -directive Explore +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: Explore + +Starting Initial Update Timing Task + +Time (s): cpu = 00:00:19 ; elapsed = 00:00:06 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 441326 ; free virtual = 602523 +INFO: [Vivado_Tcl 4-2279] Estimated Timing Summary | WNS= 1.277 | TNS= 0.000 | +INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. All physical synthesis setup optimizations will be skipped. +INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified. +INFO: [Common 17-83] Releasing license: Implementation +6 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +phys_opt_design completed successfully +phys_opt_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:06 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 441326 ; free virtual = 602523 +# phase ROUTE +BOARD_PHASE ROUTE +# route_design -directive Explore +Command: route_design -directive Explore +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 8 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-270] Using Router directive 'Explore'. +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs + +Phase 1 Build RT Design +Checksum: PlaceDB: ee9480ea ConstDB: 0 ShapeSum: 4d76fb2b RouteDB: b1d25f96 +Post Restoration Checksum: NetGraph: 3122703f | NumContArr: 80923bb4 | Constraints: c2a8fa9d | Timing: c2a8fa9d +Phase 1 Build RT Design | Checksum: 23706a12d + +Time (s): cpu = 00:00:33 ; elapsed = 00:00:14 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 434318 ; free virtual = 603900 + +Phase 2 Router Initialization + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 23706a12d + +Time (s): cpu = 00:00:34 ; elapsed = 00:00:15 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 434125 ; free virtual = 603900 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 23706a12d + +Time (s): cpu = 00:00:35 ; elapsed = 00:00:15 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 434083 ; free virtual = 603902 + Number of Nodes with overlaps = 0 + +Phase 2.3 Update Timing +Phase 2.3 Update Timing | Checksum: 2919fd49e + +Time (s): cpu = 00:01:07 ; elapsed = 00:00:24 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 429576 ; free virtual = 603961 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.274 | TNS=0.000 | WHS=-1.411 | THS=-707.945| + + +Phase 2.4 Update Timing for Bus Skew + +Phase 2.4.1 Update Timing +Phase 2.4.1 Update Timing | Checksum: 24d0d505a + +Time (s): cpu = 00:01:30 ; elapsed = 00:00:30 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 426124 ; free virtual = 603406 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.274 | TNS=0.000 | WHS=-2.372 | THS=-68.356| + +Phase 2.4 Update Timing for Bus Skew | Checksum: 25d8558af + +Time (s): cpu = 00:01:30 ; elapsed = 00:00:30 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 426009 ; free virtual = 603350 + +Router Utilization Summary + Global Vertical Routing Utilization = 0 % + Global Horizontal Routing Utilization = 0 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 93600 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 93600 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Phase 2 Router Initialization | Checksum: 30f73531b + +Time (s): cpu = 00:01:32 ; elapsed = 00:00:31 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 425562 ; free virtual = 603128 + +Phase 3 Global Routing +Phase 3 Global Routing | Checksum: 30f73531b + +Time (s): cpu = 00:01:32 ; elapsed = 00:00:31 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 425546 ; free virtual = 603120 + +Phase 4 Initial Routing + +Phase 4.1 Initial Net Routing Pass +Phase 4.1 Initial Net Routing Pass | Checksum: 373819a83 + +Time (s): cpu = 00:01:47 ; elapsed = 00:00:34 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424373 ; free virtual = 603481 +Phase 4 Initial Routing | Checksum: 373819a83 + +Time (s): cpu = 00:01:48 ; elapsed = 00:00:34 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424370 ; free virtual = 603478 + +Phase 5 Rip-up And Reroute + +Phase 5.1 Global Iteration 0 + Number of Nodes with overlaps = 14547 + Number of Nodes with overlaps = 1474 + Number of Nodes with overlaps = 372 + Number of Nodes with overlaps = 120 + Number of Nodes with overlaps = 28 + Number of Nodes with overlaps = 9 + Number of Nodes with overlaps = 4 + Number of Nodes with overlaps = 2 + Number of Nodes with overlaps = 4 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 0 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.274 | TNS=0.000 | WHS=N/A | THS=N/A | + +Phase 5.1 Global Iteration 0 | Checksum: 22ddfe875 + +Time (s): cpu = 00:03:05 ; elapsed = 00:01:18 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424370 ; free virtual = 603561 + +Phase 5.2 Global Iteration 1 + Number of Nodes with overlaps = 6 + Number of Nodes with overlaps = 18 + Number of Nodes with overlaps = 35 + Number of Nodes with overlaps = 9 + Number of Nodes with overlaps = 4 + Number of Nodes with overlaps = 3 + Number of Nodes with overlaps = 2 + Number of Nodes with overlaps = 0 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.274 | TNS=0.000 | WHS=N/A | THS=N/A | + +Phase 5.2 Global Iteration 1 | Checksum: 2caa5e21c + +Time (s): cpu = 00:03:21 ; elapsed = 00:01:25 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424320 ; free virtual = 603539 +Phase 5 Rip-up And Reroute | Checksum: 2caa5e21c + +Time (s): cpu = 00:03:21 ; elapsed = 00:01:26 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424320 ; free virtual = 603539 + +Phase 6 Delay and Skew Optimization + +Phase 6.1 Delay CleanUp + +Phase 6.1.1 Update Timing +Phase 6.1.1 Update Timing | Checksum: 23ffe80c8 + +Time (s): cpu = 00:03:30 ; elapsed = 00:01:28 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424280 ; free virtual = 603499 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.274 | TNS=0.000 | WHS=N/A | THS=N/A | + +Phase 6.1 Delay CleanUp | Checksum: 2c7712393 + +Time (s): cpu = 00:03:30 ; elapsed = 00:01:28 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424280 ; free virtual = 603499 + +Phase 6.2 Clock Skew Optimization +Phase 6.2 Clock Skew Optimization | Checksum: 2c7712393 + +Time (s): cpu = 00:03:31 ; elapsed = 00:01:28 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424280 ; free virtual = 603499 +Phase 6 Delay and Skew Optimization | Checksum: 2c7712393 + +Time (s): cpu = 00:03:31 ; elapsed = 00:01:28 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424280 ; free virtual = 603500 + +Phase 7 Post Hold Fix + +Phase 7.1 Hold Fix Iter +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.274 | TNS=0.000 | WHS=0.010 | THS=0.000 | + +Phase 7.1 Hold Fix Iter | Checksum: 3069ea4f8 + +Time (s): cpu = 00:03:41 ; elapsed = 00:01:30 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424301 ; free virtual = 603520 +Phase 7 Post Hold Fix | Checksum: 3069ea4f8 + +Time (s): cpu = 00:03:41 ; elapsed = 00:01:30 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424301 ; free virtual = 603520 + +Phase 8 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 21.9621 % + Global Horizontal Routing Utilization = 26.5401 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Phase 8 Route finalize | Checksum: 3069ea4f8 + +Time (s): cpu = 00:03:42 ; elapsed = 00:01:30 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424309 ; free virtual = 603528 + +Phase 9 Verifying routed nets + + Verification completed successfully +Phase 9 Verifying routed nets | Checksum: 3069ea4f8 + +Time (s): cpu = 00:03:42 ; elapsed = 00:01:31 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424309 ; free virtual = 603528 + +Phase 10 Depositing Routes +Phase 10 Depositing Routes | Checksum: 29fc7be2a + +Time (s): cpu = 00:03:49 ; elapsed = 00:01:34 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424316 ; free virtual = 603535 + +Phase 11 Post Process Routing +Phase 11 Post Process Routing | Checksum: 29fc7be2a + +Time (s): cpu = 00:03:49 ; elapsed = 00:01:34 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424316 ; free virtual = 603535 + +Phase 12 Post Router Timing +INFO: [Route 35-20] Post Routing Timing Summary | WNS=1.276 | TNS=0.000 | WHS=0.012 | THS=0.000 | + +Phase 12 Post Router Timing | Checksum: 1f006e4a8 + +Time (s): cpu = 00:04:17 ; elapsed = 00:01:40 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424343 ; free virtual = 603562 +INFO: [Route 35-61] The design met the timing requirement. +Total Elapsed time in route_design: 100.15 secs + +Phase 13 Post-Route Event Processing +Phase 13 Post-Route Event Processing | Checksum: fa658e56 + +Time (s): cpu = 00:04:17 ; elapsed = 00:01:41 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424343 ; free virtual = 603562 +INFO: [Route 35-16] Router Completed Successfully +Ending Routing Task | Checksum: fa658e56 + +Time (s): cpu = 00:04:18 ; elapsed = 00:01:41 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424351 ; free virtual = 603571 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +16 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:04:24 ; elapsed = 00:01:45 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424352 ; free virtual = 603571 +# write_checkpoint -force $out/routed.dcp +INFO: [Timing 38-480] Writing timing data to binary archive. +Write ShapeDB Complete: Time (s): cpu = 00:00:00.79 ; elapsed = 00:00:00.16 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424337 ; free virtual = 603574 +Wrote PlaceDB: Time (s): cpu = 00:00:08 ; elapsed = 00:00:03 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424235 ; free virtual = 603557 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424235 ; free virtual = 603557 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00.92 ; elapsed = 00:00:00.54 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424229 ; free virtual = 603567 +Wrote Netlist Cache: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424222 ; free virtual = 603569 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424214 ; free virtual = 603561 +Write Physdb Complete: Time (s): cpu = 00:00:09 ; elapsed = 00:00:04 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424214 ; free virtual = 603561 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/routed.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:24 ; elapsed = 00:00:14 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424299 ; free virtual = 603605 +# phase REPORT +BOARD_PHASE REPORT +# report_utilization -file $out/routed-utilization.rpt +# report_utilization -hierarchical -file $out/routed-hierarchy.rpt +# report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -file $out/routed-timing.rpt +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. +report_timing_summary: Time (s): cpu = 00:00:25 ; elapsed = 00:00:07 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424242 ; free virtual = 603549 +# report_route_status -file $out/route-status.rpt +# report_drc -file $out/drc.rpt +Command: report_drc -file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/drc.rpt +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 8 threads +INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/drc.rpt. +report_drc completed successfully +INFO: [Timing 38-91] UpdateTimingParams: No interconnect No Cell Dly, Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +INFO: [Timing 38-314] The report_cdc command only analyzes and reports clock domain crossing paths where clocks have been defined on both source and destination sides. Ports with no input delay constraint are skipped. Please run check_timing to verify there are no missing clock definitions in your design, nor any unconstrained input port. +# set cdc [report_cdc -details -return_string] +# set f [open $out/cdc.rpt w] +# puts $f $cdc +# close $f +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +# set skew [report_bus_skew -return_string] +# set f [open $out/bus-skew.rpt w] +# puts $f $skew +# close $f +# report_methodology -file $out/methodology.rpt +Command: report_methodology -file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/methodology.rpt +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 8 threads +INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/methodology.rpt. +report_methodology completed successfully +report_methodology: Time (s): cpu = 00:00:30 ; elapsed = 00:00:10 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424266 ; free virtual = 603608 +# report_io -file $out/io.rpt +report_io: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.18 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424268 ; free virtual = 603610 +# report_clocks -file $out/clocks.rpt +INFO: [Timing 38-35] Done setting XDC timing constraints. +# check_timing -verbose -file $out/check-timing.rpt +# if {[regexp {CDC-[0-9]+\s+Critical} $cdc]} {error "Critical CDC findings; see cdc.rpt"} +# if {[string match *VIOLATED* $skew]} {error "Bus skew failed; see bus-skew.rpt"} +# foreach kind {max min} { +# set paths [get_timing_paths -delay_type $kind -max_paths 1] +# if {[llength $paths]==0} {error "Missing $kind timing paths"} +# if {[get_property SLACK [lindex $paths 0]]<0} {error "$kind timing failed"} +# } +# if {![report_route_status -boolean_check ROUTED_FULLY]} {error "Routing incomplete"} +# if {[report_route_status -boolean_check ERRORS_IN_ROUTES]} {error "Routing errors"} +# set errors [get_drc_violations -quiet -filter {SEVERITY == Error || SEVERITY == {Critical Warning}}] +# if {[llength $errors]} {error "DRC errors/critical warnings: $errors"} +# phase BITSTREAM +BOARD_PHASE BITSTREAM +# set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +# write_bitstream -force $out/toy_a7.bit +Command: write_bitstream -force /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/toy_a7.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +Running DRC as a precondition to command write_bitstream +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 8 threads +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +INFO: [Common 17-14] Message 'DRC DPIP-1' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +INFO: [Common 17-14] Message 'DRC DPOP-1' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/rowSkip_reg multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/rowSkip_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +INFO: [Common 17-14] Message 'DRC DPOP-2' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [DRC REQP-1709] Clock output buffering: PLLE2_ADV connectivity violation. The signal ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out on the ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 pin of ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i does not drive the same kind of BUFFER load as the other CLKOUT pins. Routing from the different buffer types will not be phase aligned. +WARNING: [DRC RTSTAT-10] No routable loads: 45 net(s) have no routable loads. The problem bus(es) and/or net(s) are memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0]... and (the first 15 of 25 listed). +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 360 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Bitstream compression saved 7428160 bits. +Writing bitstream /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/toy_a7.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-83] Releasing license: Implementation +12 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:45 ; elapsed = 00:00:24 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424219 ; free virtual = 603708 +# phase COMPLETE +BOARD_PHASE COMPLETE +# puts "PASS BOARD_PLACE_ROUTE_TIMING_BITSTREAM: engineering Rev E target; flash=$flash; this build does not validate physical boot" +PASS BOARD_PLACE_ROUTE_TIMING_BITSTREAM: engineering Rev E target; flash=0; this build does not validate physical boot +INFO: [Common 17-206] Exiting Vivado at Mon Oct 12 20:37:08 2026... diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/drc.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/drc.rpt new file mode 100644 index 0000000..38a39cd --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/drc.rpt @@ -0,0 +1,1855 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Mon Oct 12 20:36:22 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_drc -file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/drc.rpt +| Design : toy_a7_top +| Device : xc7a100tcsg324-1 +| Speed File : -1 +| Design State : Fully Routed +--------------------------------------------------------------------------------------------------------------------------------------------- + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: toy_a7_top + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 360 ++-----------+----------+------------------------+------------+ +| Rule | Severity | Description | Violations | ++-----------+----------+------------------------+------------+ +| DPIP-1 | Warning | Input pipelining | 152 | +| DPOP-1 | Warning | PREG Output pipelining | 102 | +| DPOP-2 | Warning | MREG Output pipelining | 104 | +| REQP-1709 | Warning | Clock output buffering | 1 | +| RTSTAT-10 | Warning | No routable loads | 1 | ++-----------+----------+------------------------+------------+ + +2. REPORT DETAILS +----------------- +DPIP-1#1 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#2 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#3 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#4 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#5 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#6 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#7 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#8 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#9 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#10 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#11 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#12 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#13 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#14 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#15 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#16 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#17 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#18 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#19 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#20 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#21 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#22 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#23 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#24 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#25 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#26 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#27 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#28 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#29 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#30 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#31 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#32 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#33 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#34 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#35 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#36 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#37 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#38 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#39 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#40 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#41 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#42 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#43 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#44 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#45 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#46 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#47 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#48 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#49 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#50 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#51 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#52 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#53 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#54 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#55 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#56 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#57 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#58 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#59 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#60 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#61 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#62 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#63 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#64 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#65 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#66 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#67 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#68 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#69 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#70 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#71 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#72 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#73 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#74 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#75 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#76 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#77 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#78 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#79 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#80 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#81 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#82 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#83 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#84 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#85 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#86 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#87 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#88 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#89 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#90 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#91 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#92 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#93 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#94 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#95 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#96 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#97 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#98 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#99 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#100 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#101 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#102 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#103 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#104 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#105 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#106 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#107 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#108 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#109 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#110 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#111 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#112 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#113 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#114 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#115 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#116 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#117 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#118 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#119 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#120 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#121 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#122 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#123 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#124 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#125 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#126 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#127 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#128 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#129 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#130 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#131 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#132 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#133 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#134 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#135 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#136 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#137 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#138 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#139 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#140 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#141 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#142 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#143 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#144 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#145 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#146 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#147 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#148 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#149 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#150 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#151 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#152 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/rowSkip_reg input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/rowSkip_reg/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPOP-1#1 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#2 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#3 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#4 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#5 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#6 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#7 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#8 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#9 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#10 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#11 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#12 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#13 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#14 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#15 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#16 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#17 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#18 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#19 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#20 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#21 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#22 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#23 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#24 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#25 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#26 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#27 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#28 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#29 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#30 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#31 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#32 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#33 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#34 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#35 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#36 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#37 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#38 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#39 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#40 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#41 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#42 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#43 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#44 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#45 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#46 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#47 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#48 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#49 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#50 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#51 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#52 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#53 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#54 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#55 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#56 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#57 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#58 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#59 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#60 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#61 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#62 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#63 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#64 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#65 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#66 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#67 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#68 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#69 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#70 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#71 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#72 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#73 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#74 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#75 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#76 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#77 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#78 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#79 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#80 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#81 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#82 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#83 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#84 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#85 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#86 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#87 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#88 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#89 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#90 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#91 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#92 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#93 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#94 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#95 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#96 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#97 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#98 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#99 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#100 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#101 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#102 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__3 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__3/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-2#1 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#2 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#3 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#4 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#5 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#6 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#7 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#8 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#9 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#10 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#11 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#12 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#13 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#14 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#15 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#16 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#17 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#18 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#19 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#20 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#21 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#22 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#23 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#24 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#25 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#26 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#27 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#28 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#29 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#30 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#31 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#32 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#33 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#34 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#35 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#36 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#37 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#38 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#39 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#40 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#41 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#42 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#43 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#44 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#45 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#46 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#47 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#48 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#49 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#50 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#51 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#52 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#53 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#54 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#55 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#56 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#57 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#58 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#59 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#60 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#61 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#62 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#63 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#64 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#65 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#66 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#67 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#68 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#69 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#70 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#71 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#72 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#73 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#74 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#75 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#76 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#77 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#78 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#79 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#80 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#81 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#82 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#83 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#84 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#85 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#86 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#87 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#88 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#89 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#90 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#91 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/rowSkip_reg multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/rowSkip_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#92 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#93 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#94 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#95 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#96 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#97 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#98 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#99 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#100 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#101 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__3 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__3/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#102 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#103 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#104 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +REQP-1709#1 Warning +Clock output buffering +PLLE2_ADV connectivity violation. The signal ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out on the ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 pin of ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i does not drive the same kind of BUFFER load as the other CLKOUT pins. Routing from the different buffer types will not be phase aligned. +Related violations: + +RTSTAT-10#1 Warning +No routable loads +45 net(s) have no routable loads. The problem bus(es) and/or net(s) are memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0] + (the first 15 of 25 listed). +Related violations: + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/io.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/io.rpt new file mode 100644 index 0000000..67518e6 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/io.rpt @@ -0,0 +1,366 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Mon Oct 12 20:36:37 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_io -file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/io.rpt +| Design : toy_a7_top +| Device : xc7a100t +| Speed File : -1 +| Package : csg324 +| Package Version : FINAL 2012-07-17 +| Package Pin Delay Version : VERS. 2.0 2012-07-17 +---------------------------------------------------------------------------------------------------------------------------------------------------------- + +IO Information + +Table of Contents +----------------- +1. Summary +2. IO Assignments by Package Pin + +1. Summary +---------- + ++---------------+ +| Total User IO | ++---------------+ +| 62 | ++---------------+ + + +2. IO Assignments by Package Pin +-------------------------------- + ++------------+---------------+------------+------------------------------+-------------+--------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+----------+------------------+--------------+-------------------+--------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization | ++------------+---------------+------------+------------------------------+-------------+--------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+----------+------------------+--------------+-------------------+--------------+ +| A1 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A3 | | High Range | IO_L8N_T1_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A4 | | High Range | IO_L8P_T1_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | | +| A5 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A6 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | | +| A7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| A8 | sw0 | High Range | IO_L12N_T1_MRCC_16 | INPUT | LVCMOS33 | 16 | | | | NONE | | FIXED | | | | NONE | | | | +| A9 | uart_txd_in | High Range | IO_L14N_T2_SRCC_16 | INPUT | LVCMOS33 | 16 | | | | NONE | | FIXED | | | | NONE | | | | +| A10 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A11 | | High Range | IO_L4N_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A13 | | High Range | IO_L9P_T1_DQS_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | | +| A14 | | High Range | IO_L9N_T1_DQS_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A15 | | High Range | IO_L8P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | | +| A16 | | High Range | IO_L8N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| A18 | | High Range | IO_L10N_T1_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B1 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B2 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B3 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B4 | | High Range | IO_L7N_T1_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B6 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B7 | | High Range | IO_L2P_T0_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B8 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B9 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B10 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | | +| B11 | | High Range | IO_L4P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| B12 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B13 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B14 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B16 | | High Range | IO_L7P_T1_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B17 | | High Range | IO_L7N_T1_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B18 | | High Range | IO_L10P_T1_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C1 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| C2 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| C3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| C4 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | | +| C5 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | | +| C6 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | | +| C7 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| C8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C9 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C10 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C11 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C12 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C13 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| C14 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | | +| C15 | | High Range | IO_L12N_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| C16 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | | +| C17 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | | +| C18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D2 | | High Range | IO_L14N_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D3 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D4 | | High Range | IO_L11N_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D5 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D6 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| D7 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| D8 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| D9 | btn0 | High Range | IO_L6N_T0_VREF_16 | INPUT | LVCMOS33 | 16 | | | | NONE | | FIXED | | | | NONE | | | | +| D10 | uart_rxd_out | High Range | IO_L19N_T3_VREF_16 | OUTPUT | LVCMOS33 | 16 | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| D11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D12 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| D13 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| D14 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | | +| D15 | | High Range | IO_L12P_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| D16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| D17 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | | +| D18 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | | +| E1 | | High Range | IO_L18N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| E2 | | High Range | IO_L14P_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| E3 | CLK100MHZ | High Range | IO_L12P_T1_MRCC_35 | INPUT | LVCMOS33 | 35 | | | | NONE | | FIXED | | | | NONE | | | | +| E4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E5 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | | +| E6 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | | +| E7 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| E8 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | | +| E9 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | | +| E10 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | | +| E11 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | | +| E12 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | | +| E13 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | | +| E14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E15 | | High Range | IO_L11P_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| E16 | | High Range | IO_L11N_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| E17 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | | +| E18 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| F1 | | High Range | IO_L18P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| F2 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| F3 | | High Range | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| F4 | | High Range | IO_L13P_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| F5 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | | +| F6 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| F9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F10 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| F11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| F13 | | High Range | IO_L5P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | | +| F14 | | High Range | IO_L5N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | | +| F15 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| F16 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| F17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F18 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | | +| G1 | | High Range | IO_L17N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| G2 | | High Range | IO_L15N_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| G3 | | High Range | IO_L20N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| G4 | | High Range | IO_L20P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| G5 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| G6 | | High Range | IO_L19P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| G7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G13 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | | +| G14 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| G15 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| G16 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| G17 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | | +| G18 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | | +| H1 | | High Range | IO_L17P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| H2 | | High Range | IO_L15P_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| H3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H4 | | High Range | IO_L21N_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| H5 | led[0] | High Range | IO_L24N_T3_35 | OUTPUT | LVCMOS33 | 35 | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| H6 | | High Range | IO_L24P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| H9 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| H10 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| H13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H14 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| H15 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| H16 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| H17 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | | +| H18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| J1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| J2 | | High Range | IO_L22N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| J3 | | High Range | IO_L22P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| J4 | | High Range | IO_L21P_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| J5 | led[1] | High Range | IO_25_35 | OUTPUT | LVCMOS33 | 35 | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| J6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J9 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | | +| J10 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | | +| J11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J13 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | | +| J14 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | | | | | +| J15 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | | +| J16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J17 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| J18 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| K1 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| K2 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| K3 | ddr3_dq[2] | High Range | IO_L2P_T0_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| K4 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.35 | | | | | | | | | +| K5 | ddr3_dq[0] | High Range | IO_L5P_T0_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| K6 | ddr3_reset_n | High Range | IO_0_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| K9 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | | +| K10 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | | +| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| K13 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | | +| K14 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| K15 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | | +| K16 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | | +| K17 | flash_mosi | High Range | IO_L1P_T0_D00_MOSI_14 | OUTPUT | LVCMOS33 | 14 | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| K18 | flash_miso | High Range | IO_L1N_T0_D01_DIN_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| L1 | ddr3_dm[0] | High Range | IO_L1P_T0_34 | TRISTATE | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| L2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L3 | ddr3_dq[1] | High Range | IO_L2N_T0_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| L4 | ddr3_dq[6] | High Range | IO_L5N_T0_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| L5 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| L6 | ddr3_dq[3] | High Range | IO_L6P_T0_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| L7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L9 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| L10 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| L11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L13 | flash_cs_n | High Range | IO_L6P_T0_FCS_B_14 | OUTPUT | LVCMOS33 | 14 | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| L14 | flash_wp_n | High Range | IO_L2P_T0_D02_14 | OUTPUT | LVCMOS33 | 14 | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| L15 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| L16 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | | +| L17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| L18 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | | +| M1 | ddr3_dq[5] | High Range | IO_L1N_T0_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| M2 | ddr3_dq[7] | High Range | IO_L4N_T0_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| M3 | ddr3_dq[4] | High Range | IO_L4P_T0_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| M4 | ddr3_cas_n | High Range | IO_L16P_T2_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| M5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M6 | ddr3_addr[1] | High Range | IO_L18P_T2_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| M13 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| M14 | flash_hold_n | High Range | IO_L2N_T0_D03_14 | OUTPUT | LVCMOS33 | 14 | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| M15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M16 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | | +| M17 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | | +| M18 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | | +| N1 | ddr3_dqs_n[0] | High Range | IO_L3N_T0_DQS_34 | BIDIR | DIFF_SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| N2 | ddr3_dqs_p[0] | High Range | IO_L3P_T0_DQS_34 | BIDIR | DIFF_SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| N3 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.35 | | | | | | | | | +| N4 | ddr3_addr[2] | High Range | IO_L16N_T2_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| N5 | ddr3_cke[0] | High Range | IO_L13P_T2_MRCC_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| N6 | ddr3_addr[4] | High Range | IO_L18N_T2_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| N7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| N14 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | | +| N15 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N16 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N17 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| N18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P2 | ddr3_ba[2] | High Range | IO_L15P_T2_DQS_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| P3 | ddr3_ras_n | High Range | IO_L14N_T2_SRCC_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| P4 | ddr3_ba[1] | High Range | IO_L14P_T2_SRCC_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| P5 | ddr3_we_n | High Range | IO_L13N_T2_MRCC_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| P6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.35 | | | | | | | | | +| P7 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | | +| P8 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | 3.30 | | | | | | | | | +| P9 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | | +| P10 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | | +| P11 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | | +| P12 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | | +| P13 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | | +| P14 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | | +| P15 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| P16 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| P17 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| P18 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | | +| R1 | ddr3_ba[0] | High Range | IO_L17P_T2_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| R2 | ddr3_addr[0] | High Range | IO_L15N_T2_DQS_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| R3 | ddr3_dq[15] | High Range | IO_L11P_T1_SRCC_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| R4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R5 | ddr3_odt[0] | High Range | IO_L19N_T3_VREF_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| R6 | ddr3_addr[10] | High Range | IO_L19P_T3_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| R7 | ddr3_addr[5] | High Range | IO_L23P_T3_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| R8 | ddr3_addr[8] | High Range | IO_L24P_T3_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| R9 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | 3.30 | | | | | | | | | +| R10 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | | +| R11 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | | +| R12 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | | +| R13 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | | +| R14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R15 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| R16 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| R17 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| R18 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | | +| T1 | ddr3_addr[3] | High Range | IO_L17N_T2_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| T2 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.35 | | | | | | | | | +| T3 | ddr3_dq[13] | High Range | IO_L11N_T1_SRCC_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| T4 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T5 | ddr3_dq[9] | High Range | IO_L12P_T1_MRCC_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| T6 | ddr3_addr[12] | High Range | IO_L23N_T3_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T8 | ddr3_addr[13] | High Range | IO_L24N_T3_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| T9 | led[2] | High Range | IO_L24P_T3_A01_D17_14 | OUTPUT | LVCMOS33 | 14 | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| T10 | led[3] | High Range | IO_L24N_T3_A00_D16_14 | OUTPUT | LVCMOS33 | 14 | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| T11 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | | +| T12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| T13 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | | +| T14 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| T15 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| T16 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T18 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | | +| U1 | ddr3_dm[1] | High Range | IO_L7P_T1_34 | TRISTATE | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U2 | ddr3_dqs_p[1] | High Range | IO_L9P_T1_DQS_34 | BIDIR | DIFF_SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U3 | ddr3_dq[14] | High Range | IO_L8N_T1_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| U4 | ddr3_dq[10] | High Range | IO_L8P_T1_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| U5 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.35 | | | | | | | | | +| U6 | ddr3_addr[11] | High Range | IO_L22N_T3_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U7 | ddr3_addr[7] | High Range | IO_L22P_T3_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U8 | ddr3_cs_n[0] | High Range | IO_25_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U9 | ddr3_ck_p[0] | High Range | IO_L21P_T3_DQS_34 | OUTPUT | DIFF_SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U11 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| U12 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | | +| U13 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | | +| U14 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | | +| U15 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| U16 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | | +| U17 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | | +| U18 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | | +| V1 | ddr3_dq[12] | High Range | IO_L7N_T1_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| V2 | ddr3_dqs_n[1] | High Range | IO_L9N_T1_DQS_34 | BIDIR | DIFF_SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| V3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V4 | ddr3_dq[8] | High Range | IO_L10N_T1_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| V5 | ddr3_dq[11] | High Range | IO_L10P_T1_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| V6 | ddr3_addr[6] | High Range | IO_L20N_T3_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| V7 | ddr3_addr[9] | High Range | IO_L20P_T3_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| V8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.35 | | | | | | | | | +| V9 | ddr3_ck_n[0] | High Range | IO_L21N_T3_DQS_34 | OUTPUT | DIFF_SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| V10 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| V11 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | | +| V12 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | | +| V13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V14 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | | +| V15 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| V16 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | | +| V17 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | | +| V18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | ++------------+---------------+------------+------------------------------+-------------+--------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+----------+------------------+--------------+-------------------+--------------+ +* Default value +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/ip-status.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/ip-status.rpt new file mode 100644 index 0000000..0b91f38 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/ip-status.rpt @@ -0,0 +1,33 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Mon Oct 12 20:14:28 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_ip_status +--------------------------------------------------------------------------------------------------------------------------------------------- + +IP Status Summary + +1. Project IP Status +-------------------- +Your project uses 2 IP. Some of these IP may have undergone changes in this release of the software. Please review the recommended actions. + +More information on the Xilinx versioning policy is available at www.xilinx.com. + +Project IP Instances ++---------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| Instance Name | Status | Recommendation | Change | IP Name | IP | New Version | New | Original Part | +| | | | Log | | Version | | License | | ++---------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| arty_ddr3 | Up-to-date | No changes required | *(1) | Memory Interface | 4.2 | 4.2 (Rev. 1) | Included | xc7a100tcsg324-1 | +| | | | | Generator (MIG 7 | (Rev. | | | | +| | | | | Series) | 1) | | | | ++---------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| toy_axi_cdc | Up-to-date | No changes required | *(2) | AXI Clock | 2.1 | 2.1 (Rev. 30) | Included | xc7a100tcsg324-1 | +| | | | | Converter | (Rev. | | | | +| | | | | | 30) | | | | ++---------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +*(1) /data0/tools/Xilinx/Vivado/2024.1/data/ip/xilinx/mig_7series_v4_2/doc/mig_7series_v4_2_changelog.txt +*(2) /data0/tools/Xilinx/Vivado/2024.1/data/ip/xilinx/axi_clock_converter_v2_1/doc/axi_clock_converter_v2_1_changelog.txt + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/launcher.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/launcher.log new file mode 100644 index 0000000..e69de29 diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/methodology.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/methodology.rpt new file mode 100644 index 0000000..7d07e7e --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/methodology.rpt @@ -0,0 +1,389 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Mon Oct 12 20:36:37 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_methodology -file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/methodology.rpt +| Design : toy_a7_top +| Device : xc7a100tcsg324-1 +| Speed File : -1 +| Design State : Fully Routed +------------------------------------------------------------------------------------------------------------------------------------------------------ + +Report Methodology + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: toy_a7_top + Floorplan: design_1 + Design limits: + Max violations: + Violations found: 65 ++-----------+----------+-----------------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++-----------+----------+-----------------------------------------------------------+------------+ +| LUTAR-1 | Warning | LUT drives async reset alert | 2 | +| SYNTH-5 | Warning | Mapped onto distributed RAM because of timing constraints | 16 | +| SYNTH-9 | Warning | Small multiplier | 5 | +| SYNTH-10 | Warning | Wide multiplier | 21 | +| SYNTH-16 | Warning | Address collision | 1 | +| TIMING-10 | Warning | Missing property on synchronizer | 1 | +| ULMTCS-1 | Warning | Control Sets use limits recommend reduction | 1 | +| XDCB-5 | Warning | Runtime inefficient way to find pin objects | 2 | +| REQP-1959 | Advisory | connects_SERDES_RST_driver_not_FF | 16 | ++-----------+----------+-----------------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +LUTAR-1#1 Warning +LUT drives async reset alert +LUT cell ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rstdiv2_sync_r[11]_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__7/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__8/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__9/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[0]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[10]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[11]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[1]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[2]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[3]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[4]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[5]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[6]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[7]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[8]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[9]/PRE + (the first 15 of 32 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#2 Warning +LUT drives async reset alert +LUT cell platform/loader/in_pipe_v_i_1__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) platform/chip/system/clint_domain/intsource/reg_0/reg_0_reg[0]/CLR, +platform/chip/system/clint_domain/intsource/reg_0/reg_0_reg[1]/CLR, +platform/chip/system/ibus_intsource/reg_0__0/reg_0_reg/CLR, +platform/chip/system/plic_domain/intsource/reg_0/reg_0_reg/CLR +platform/chip/system/plic_domain/intsource_1/reg_0/reg_0_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +SYNTH-5#1 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_0_127_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#2 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_0_127_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#3 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_0_127_2_2 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#4 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_0_127_3_3 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#5 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_0_127_4_4 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#6 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_0_127_5_5 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#7 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_0_127_6_6 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#8 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_0_127_7_7 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#9 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_128_255_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#10 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_128_255_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#11 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_128_255_2_2 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#12 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_128_255_3_3 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#13 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_128_255_4_4 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#14 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_128_255_5_5 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#15 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_128_255_6_6 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#16 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_128_255_7_7 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-9#1 Warning +Small multiplier +Detected multiplier at sharedFma/fma/product_pipe_b_reg[11]_i_1 of size 20x3, it is implemented as LUTs due to its small size. To force the multiplier onto a DSP block, use the USE_DSP48 attribute. +Related violations: + +SYNTH-9#2 Warning +Small multiplier +Detected multiplier at sharedFma/fma/product_pipe_b_reg[15]_i_1 of size 20x3, it is implemented as LUTs due to its small size. To force the multiplier onto a DSP block, use the USE_DSP48 attribute. +Related violations: + +SYNTH-9#3 Warning +Small multiplier +Detected multiplier at sharedFma/fma/product_pipe_b_reg[19]_i_1 of size 20x3, it is implemented as LUTs due to its small size. To force the multiplier onto a DSP block, use the USE_DSP48 attribute. +Related violations: + +SYNTH-9#4 Warning +Small multiplier +Detected multiplier at sharedFma/fma/product_pipe_b_reg[3]_i_1 of size 20x3, it is implemented as LUTs due to its small size. To force the multiplier onto a DSP block, use the USE_DSP48 attribute. +Related violations: + +SYNTH-9#5 Warning +Small multiplier +Detected multiplier at sharedFma/fma/product_pipe_b_reg[7]_i_1 of size 20x3, it is implemented as LUTs due to its small size. To force the multiplier onto a DSP block, use the USE_DSP48 attribute. +Related violations: + +SYNTH-10#1 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1 of size 23x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#2 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__0 of size 18x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#3 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1 of size 23x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#4 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10 of size 18x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#5 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11 of size 18x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#6 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__2 of size 18x23, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#7 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3 of size 18x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#8 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__4 of size 18x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#9 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5 of size 18x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#10 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__6 of size 18x23, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#11 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7 of size 18x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#12 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8 of size 18x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#13 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__9 of size 18x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#14 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0 of size 18x20, it is decomposed from a wide multipler into 10 DSP blocks. +Related violations: + +SYNTH-10#15 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__0 of size 20x18, it is decomposed from a wide multipler into 10 DSP blocks. +Related violations: + +SYNTH-10#16 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__1 of size 18x20, it is decomposed from a wide multipler into 10 DSP blocks. +Related violations: + +SYNTH-10#17 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__2 of size 18x18, it is decomposed from a wide multipler into 10 DSP blocks. +Related violations: + +SYNTH-10#18 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__3 of size 18x18, it is decomposed from a wide multipler into 10 DSP blocks. +Related violations: + +SYNTH-10#19 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__4 of size 18x18, it is decomposed from a wide multipler into 10 DSP blocks. +Related violations: + +SYNTH-10#20 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg__0 of size 20x18, it is decomposed from a wide multipler into 10 DSP blocks. +Related violations: + +SYNTH-10#21 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg__1 of size 18x18, it is decomposed from a wide multipler into 10 DSP blocks. +Related violations: + +SYNTH-16#1 Warning +Address collision +Block RAM platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/mshrs/sdq_ext/Memory_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended. +Related violations: + +TIMING-10#1 Warning +Missing property on synchronizer +One or more logic synchronizer has been detected between 2 clock domains but the synchronizer does not have the property ASYNC_REG defined on one or both registers. It is recommended to run report_cdc for a complete and detailed CDC coverage +Related violations: + +ULMTCS-1#1 Warning +Control Sets use limits recommend reduction +This design uses 1256 control sets (vs. available limit of 15850, determined by 1 control set per CLB). This exceeds the control set use guideline of 7.5 percent. This is at a level where reduction is RECOMMENDED (see UG949). Use report_control_sets to get more details. +Related violations: + +XDCB-5#1 Warning +Runtime inefficient way to find pin objects +The option '-to : [get_pins -hier -filter {NAME =~ *rx_meta_reg/D}]' of constraint 'set_false_path' uses inefficient query to find pin objects (see constraint position '12' in the Timing Constraint window in Vivado IDE). To reduce runtime, it is recommended to get the pins through the cell objects. Please refer to Using Constraints Guide (Constraints Efficiency). An example of optimal query is: get_pins -filter {REF_PIN_NAME=~yy*} -of_objects [get_cells -hierarchical xx*]. +Current XDC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/arty_a7.xdc (Line: 18) +Related violations: + +XDCB-5#2 Warning +Runtime inefficient way to find pin objects +The option '-to : [get_pins -hier -include_replicated_objects -filter {NAME =~ *temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[*]/D}]' of constraint 'set_max_delay' uses inefficient query to find pin objects (see constraint position '6' in the Timing Constraint window in Vivado IDE). To reduce runtime, it is recommended to get the pins through the cell objects. Please refer to Using Constraints Guide (Constraints Efficiency). An example of optimal query is: get_pins -filter {REF_PIN_NAME=~yy*} -of_objects [get_cells -hierarchical xx*]. +Current XDC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc (Line: 356) +Related violations: + +REQP-1959#1 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#2 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#3 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[3].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#4 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[4].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#5 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[5].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#6 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[6].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#7 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[7].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#8 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#9 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#10 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#11 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[3].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#12 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[4].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#13 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[5].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#14 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[6].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#15 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[7].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#16 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/opt-utilization.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/opt-utilization.rpt new file mode 100644 index 0000000..88ddb17 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/opt-utilization.rpt @@ -0,0 +1,233 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Mon Oct 12 20:32:03 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_utilization -file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/opt-utilization.rpt +| Design : toy_a7_top +| Device : xc7a100tcsg324-1 +| Speed File : -1 +| Design State : Optimized +---------------------------------------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++----------------------------+-------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++----------------------------+-------+-------+------------+-----------+-------+ +| Slice LUTs* | 56386 | 0 | 0 | 63400 | 88.94 | +| LUT as Logic | 52343 | 0 | 0 | 63400 | 82.56 | +| LUT as Memory | 4043 | 0 | 0 | 19000 | 21.28 | +| LUT as Distributed RAM | 3664 | 0 | | | | +| LUT as Shift Register | 379 | 0 | | | | +| Slice Registers | 33943 | 0 | 0 | 126800 | 26.77 | +| Register as Flip Flop | 33943 | 0 | 0 | 126800 | 26.77 | +| Register as Latch | 0 | 0 | 0 | 126800 | 0.00 | +| F7 Muxes | 689 | 0 | 0 | 31700 | 2.17 | +| F8 Muxes | 112 | 0 | 0 | 15850 | 0.71 | ++----------------------------+-------+-------+------------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. +Warning! LUT value is adjusted to account for LUT combining. +Warning! For any ECO changes, please run place_design if there are unplaced instances + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 163 | Yes | - | Set | +| 140 | Yes | - | Reset | +| 562 | Yes | Set | - | +| 33078 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++-------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------------+------+-------+------------+-----------+-------+ +| Block RAM Tile | 31 | 0 | 0 | 135 | 22.96 | +| RAMB36/FIFO* | 27 | 0 | 0 | 135 | 20.00 | +| RAMB36E1 only | 27 | | | | | +| RAMB18 | 8 | 0 | 0 | 270 | 2.96 | +| RAMB18E1 only | 8 | | | | | ++-------------------+------+-------+------------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++----------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++----------------+------+-------+------------+-----------+-------+ +| DSPs | 117 | 0 | 0 | 240 | 48.75 | +| DSP48E1 only | 117 | | | | | ++----------------+------+-------+------------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-----------------------------+------+-------+------------+-----------+-------+ +| Bonded IOB | 60 | 60 | 0 | 210 | 28.57 | +| IOB Master Pads | 29 | | | | | +| IOB Slave Pads | 28 | | | | | +| Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 | +| PHY_CONTROL | 1 | 1 | 0 | 6 | 16.67 | +| PHASER_REF | 1 | 1 | 0 | 6 | 16.67 | +| OUT_FIFO | 4 | 4 | 0 | 24 | 16.67 | +| IN_FIFO | 2 | 2 | 0 | 24 | 8.33 | +| IDELAYCTRL | 1 | 0 | 0 | 6 | 16.67 | +| IBUFDS | 0 | 0 | 0 | 202 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 4 | 4 | 0 | 24 | 16.67 | +| PHASER_OUT_PHY only | 4 | 4 | | | | +| PHASER_IN/PHASER_IN_PHY | 2 | 2 | 0 | 24 | 8.33 | +| PHASER_IN_PHY only | 2 | 2 | | | | +| IDELAYE2/IDELAYE2_FINEDELAY | 16 | 16 | 0 | 300 | 5.33 | +| IDELAYE2 only | 16 | 16 | | | | +| ILOGIC | 16 | 16 | 0 | 210 | 7.62 | +| ISERDES | 16 | 16 | 0 | 210 | | +| OLOGIC | 46 | 46 | 0 | 210 | 21.90 | +| OUTFF_ODDR_Register | 3 | 3 | | | | +| TFF_ODDR_Register | 2 | 2 | | | | +| OSERDES | 43 | 43 | 0 | 210 | | ++-----------------------------+------+-------+------------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++------------+------+-------+------------+-----------+-------+ +| BUFGCTRL | 5 | 0 | 0 | 32 | 15.63 | +| BUFIO | 0 | 0 | 0 | 24 | 0.00 | +| MMCME2_ADV | 2 | 1 | 0 | 6 | 33.33 | +| PLLE2_ADV | 1 | 1 | 0 | 6 | 16.67 | +| BUFMRCE | 0 | 0 | 0 | 12 | 0.00 | +| BUFHCE | 1 | 0 | 0 | 96 | 1.04 | +| BUFR | 0 | 0 | 0 | 24 | 0.00 | ++------------+------+-------+------------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+------------+-----------+--------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------+------+-------+------------+-----------+--------+ +| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 | +| XADC | 1 | 0 | 0 | 1 | 100.00 | ++-------------+------+-------+------------+-----------+--------+ + + +7. Primitives +------------- + ++--------------------------+-------+---------------------+ +| Ref Name | Used | Functional Category | ++--------------------------+-------+---------------------+ +| FDRE | 33078 | Flop & Latch | +| LUT6 | 20391 | LUT | +| LUT3 | 13504 | LUT | +| LUT5 | 12689 | LUT | +| LUT4 | 10385 | LUT | +| RAMD32 | 5100 | Distributed Memory | +| LUT2 | 4885 | LUT | +| CARRY4 | 2073 | CarryLogic | +| RAMS32 | 1774 | Distributed Memory | +| LUT1 | 811 | LUT | +| MUXF7 | 689 | MuxFx | +| FDSE | 562 | Flop & Latch | +| SRL16E | 246 | Distributed Memory | +| FDPE | 163 | Flop & Latch | +| FDCE | 140 | Flop & Latch | +| SRLC32E | 133 | Distributed Memory | +| DSP48E1 | 117 | Block Arithmetic | +| RAMD64E | 112 | Distributed Memory | +| MUXF8 | 112 | MuxFx | +| OSERDESE2 | 43 | IO | +| RAMS64E | 42 | Distributed Memory | +| OBUF | 33 | IO | +| RAMB36E1 | 27 | Block Memory | +| OBUFT | 18 | IO | +| ISERDESE2 | 16 | IO | +| IDELAYE2 | 16 | IO | +| IBUF_INTERMDISABLE | 16 | IO | +| RAMB18E1 | 8 | Block Memory | +| ODDR | 5 | IO | +| BUFG | 5 | Clock | +| PHASER_OUT_PHY | 4 | IO | +| OUT_FIFO | 4 | IO | +| OBUFTDS | 4 | IO | +| IBUFDS_INTERMDISABLE_INT | 4 | IO | +| INV | 3 | LUT | +| IBUF | 3 | IO | +| PHASER_IN_PHY | 2 | IO | +| OBUFDS | 2 | IO | +| MMCME2_ADV | 2 | Clock | +| IN_FIFO | 2 | IO | +| XADC | 1 | Others | +| PLLE2_ADV | 1 | Clock | +| PHY_CONTROL | 1 | IO | +| PHASER_REF | 1 | IO | +| IDELAYCTRL | 1 | IO | +| BUFH | 1 | Clock | ++--------------------------+-------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++-------------+------+ +| Ref Name | Used | ++-------------+------+ +| toy_axi_cdc | 1 | +| arty_ddr3 | 1 | ++-------------+------+ + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/phase.txt b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/phase.txt new file mode 100644 index 0000000..569f0b3 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/phase.txt @@ -0,0 +1 @@ +COMPLETE diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/route-status.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/route-status.rpt new file mode 100644 index 0000000..d85abf0 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/route-status.rpt @@ -0,0 +1,12 @@ +Design Route Status + : # nets : + ------------------------------------------- : ----------- : + # of logical nets.......................... : 119398 : + # of nets not needing routing.......... : 25764 : + # of internally routed nets........ : 23639 : + # of nets with no loads............ : 2125 : + # of routable nets..................... : 93634 : + # of fully routed nets............. : 93634 : + # of nets with routing errors.......... : 0 : + ------------------------------------------- : ----------- : + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/routed-hierarchy.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/routed-hierarchy.rpt new file mode 100644 index 0000000..36d5e6d --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/routed-hierarchy.rpt @@ -0,0 +1,1150 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Mon Oct 12 20:36:10 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_utilization -hierarchical -file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/routed-hierarchy.rpt +| Design : toy_a7_top +| Device : xc7a100tcsg324-1 +| Speed File : -1 +| Design State : Routed +------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Utilization by Hierarchy + +1. Utilization by Hierarchy +--------------------------- + ++----------------------------------------------------------------------------------------+-----------------------------------------------------------------+------------+------------+---------+------+-------+--------+--------+------------+ +| Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP Blocks | ++----------------------------------------------------------------------------------------+-----------------------------------------------------------------+------------+------------+---------+------+-------+--------+--------+------------+ +| toy_a7_top | (top) | 53929 | 50007 | 3644 | 278 | 33943 | 27 | 8 | 117 | +| (toy_a7_top) | (top) | 5 | 5 | 0 | 0 | 63 | 0 | 0 | 0 | +| ddr_controller | arty_ddr3 | 4569 | 3965 | 450 | 154 | 4081 | 0 | 0 | 0 | +| (ddr_controller) | arty_ddr3 | 216 | 0 | 216 | 0 | 0 | 0 | 0 | 0 | +| u_arty_ddr3_mig | arty_ddr3_mig | 4353 | 3965 | 234 | 154 | 4081 | 0 | 0 | 0 | +| temp_mon_enabled.u_tempmon | arty_ddr3mig_7series_v4_2_tempmon | 38 | 38 | 0 | 0 | 122 | 0 | 0 | 0 | +| u_ddr3_clk_ibuf | arty_ddr3mig_7series_v4_2_clk_ibuf | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| u_ddr3_infrastructure | arty_ddr3mig_7series_v4_2_infrastructure | 6 | 6 | 0 | 0 | 32 | 0 | 0 | 0 | +| u_iodelay_ctrl | arty_ddr3mig_7series_v4_2_iodelay_ctrl | 1 | 1 | 0 | 0 | 15 | 0 | 0 | 0 | +| u_memc_ui_top_axi | arty_ddr3mig_7series_v4_2_memc_ui_top_axi | 4310 | 3922 | 234 | 154 | 3912 | 0 | 0 | 0 | +| (u_memc_ui_top_axi) | arty_ddr3mig_7series_v4_2_memc_ui_top_axi | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem_intfc0 | arty_ddr3mig_7series_v4_2_mem_intfc | 3342 | 3287 | 38 | 17 | 2828 | 0 | 0 | 0 | +| ddr_phy_top0 | arty_ddr3mig_7series_v4_2_ddr_phy_top | 2738 | 2692 | 30 | 16 | 2301 | 0 | 0 | 0 | +| (ddr_phy_top0) | arty_ddr3mig_7series_v4_2_ddr_phy_top | 3 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | +| u_ddr_calib_top | arty_ddr3mig_7series_v4_2_ddr_calib_top | 2242 | 2228 | 0 | 14 | 1980 | 0 | 0 | 0 | +| (u_ddr_calib_top) | arty_ddr3mig_7series_v4_2_ddr_calib_top | 95 | 94 | 0 | 1 | 29 | 0 | 0 | 0 | +| ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl | arty_ddr3mig_7series_v4_2_ddr_phy_rdlvl | 527 | 527 | 0 | 0 | 872 | 0 | 0 | 0 | +| ddr_phy_tempmon_0 | arty_ddr3mig_7series_v4_2_ddr_phy_tempmon | 257 | 257 | 0 | 0 | 229 | 0 | 0 | 0 | +| dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr | arty_ddr3mig_7series_v4_2_ddr_phy_dqs_found_cal_hr | 146 | 145 | 0 | 1 | 91 | 0 | 0 | 0 | +| mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay | arty_ddr3mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay | 17 | 16 | 0 | 1 | 16 | 0 | 0 | 0 | +| mb_wrlvl_inst.u_ddr_phy_wrlvl | arty_ddr3mig_7series_v4_2_ddr_phy_wrlvl | 264 | 263 | 0 | 1 | 160 | 0 | 0 | 0 | +| u_ddr_phy_init | arty_ddr3mig_7series_v4_2_ddr_phy_init | 794 | 790 | 0 | 4 | 279 | 0 | 0 | 0 | +| u_ddr_phy_wrcal | arty_ddr3mig_7series_v4_2_ddr_phy_wrcal | 159 | 153 | 0 | 6 | 304 | 0 | 0 | 0 | +| u_ddr_mc_phy_wrapper | arty_ddr3mig_7series_v4_2_ddr_mc_phy_wrapper | 496 | 464 | 30 | 2 | 321 | 0 | 0 | 0 | +| (u_ddr_mc_phy_wrapper) | arty_ddr3mig_7series_v4_2_ddr_mc_phy_wrapper | 0 | 0 | 0 | 0 | 24 | 0 | 0 | 0 | +| u_ddr_mc_phy | arty_ddr3mig_7series_v4_2_ddr_mc_phy | 496 | 464 | 30 | 2 | 297 | 0 | 0 | 0 | +| (u_ddr_mc_phy) | arty_ddr3mig_7series_v4_2_ddr_mc_phy | 0 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | +| ddr_phy_4lanes_0.u_ddr_phy_4lanes | arty_ddr3mig_7series_v4_2_ddr_phy_4lanes | 496 | 464 | 30 | 2 | 281 | 0 | 0 | 0 | +| (ddr_phy_4lanes_0.u_ddr_phy_4lanes) | arty_ddr3mig_7series_v4_2_ddr_phy_4lanes | 6 | 5 | 0 | 1 | 20 | 0 | 0 | 0 | +| ddr_byte_lane_A.ddr_byte_lane_A | arty_ddr3mig_7series_v4_2_ddr_byte_lane | 51 | 21 | 30 | 0 | 20 | 0 | 0 | 0 | +| (ddr_byte_lane_A.ddr_byte_lane_A) | arty_ddr3mig_7series_v4_2_ddr_byte_lane | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | +| ddr_byte_group_io | arty_ddr3mig_7series_v4_2_ddr_byte_group_io | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| of_pre_fifo_gen.u_ddr_of_pre_fifo | arty_ddr3mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_14 | 50 | 20 | 30 | 0 | 19 | 0 | 0 | 0 | +| ddr_byte_lane_B.ddr_byte_lane_B | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized0 | 24 | 24 | 0 | 0 | 19 | 0 | 0 | 0 | +| (ddr_byte_lane_B.ddr_byte_lane_B) | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized0 | 9 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | +| ddr_byte_group_io | arty_ddr3mig_7series_v4_2_ddr_byte_group_io__parameterized0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| of_pre_fifo_gen.u_ddr_of_pre_fifo | arty_ddr3mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_13 | 15 | 15 | 0 | 0 | 19 | 0 | 0 | 0 | +| ddr_byte_lane_C.ddr_byte_lane_C | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized1 | 210 | 210 | 0 | 0 | 111 | 0 | 0 | 0 | +| (ddr_byte_lane_C.ddr_byte_lane_C) | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized1 | 7 | 7 | 0 | 0 | 69 | 0 | 0 | 0 | +| ddr_byte_group_io | arty_ddr3mig_7series_v4_2_ddr_byte_group_io__parameterized1_10 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo | arty_ddr3mig_7series_v4_2_ddr_if_post_fifo_11 | 181 | 181 | 0 | 0 | 17 | 0 | 0 | 0 | +| of_pre_fifo_gen.u_ddr_of_pre_fifo | arty_ddr3mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_12 | 22 | 22 | 0 | 0 | 24 | 0 | 0 | 0 | +| ddr_byte_lane_D.ddr_byte_lane_D | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized2 | 206 | 205 | 0 | 1 | 111 | 0 | 0 | 0 | +| (ddr_byte_lane_D.ddr_byte_lane_D) | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized2 | 0 | 0 | 0 | 0 | 69 | 0 | 0 | 0 | +| ddr_byte_group_io | arty_ddr3mig_7series_v4_2_ddr_byte_group_io__parameterized1 | 2 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | +| dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo | arty_ddr3mig_7series_v4_2_ddr_if_post_fifo | 183 | 183 | 0 | 0 | 17 | 0 | 0 | 0 | +| of_pre_fifo_gen.u_ddr_of_pre_fifo | arty_ddr3mig_7series_v4_2_ddr_of_pre_fifo__parameterized1 | 21 | 21 | 0 | 0 | 24 | 0 | 0 | 0 | +| mc0 | arty_ddr3mig_7series_v4_2_mc | 608 | 599 | 8 | 1 | 527 | 0 | 0 | 0 | +| (mc0) | arty_ddr3mig_7series_v4_2_mc | 6 | 6 | 0 | 0 | 73 | 0 | 0 | 0 | +| bank_mach0 | arty_ddr3mig_7series_v4_2_bank_mach | 495 | 495 | 0 | 0 | 362 | 0 | 0 | 0 | +| arb_mux0 | arty_ddr3mig_7series_v4_2_arb_mux | 195 | 195 | 0 | 0 | 45 | 0 | 0 | 0 | +| arb_row_col0 | arty_ddr3mig_7series_v4_2_arb_row_col | 195 | 195 | 0 | 0 | 40 | 0 | 0 | 0 | +| (arb_row_col0) | arty_ddr3mig_7series_v4_2_arb_row_col | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | +| col_arb0 | arty_ddr3mig_7series_v4_2_round_robin_arb__parameterized1 | 65 | 65 | 0 | 0 | 8 | 0 | 0 | 0 | +| config_arb0 | arty_ddr3mig_7series_v4_2_round_robin_arb__parameterized1_6 | 17 | 17 | 0 | 0 | 8 | 0 | 0 | 0 | +| pre_4_1_1T_arb.pre_arb0 | arty_ddr3mig_7series_v4_2_round_robin_arb__parameterized1_7 | 47 | 47 | 0 | 0 | 8 | 0 | 0 | 0 | +| row_arb0 | arty_ddr3mig_7series_v4_2_round_robin_arb__parameterized1_8 | 65 | 65 | 0 | 0 | 8 | 0 | 0 | 0 | +| arb_select0 | arty_ddr3mig_7series_v4_2_arb_select | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| bank_cntrl[0].bank0 | arty_ddr3mig_7series_v4_2_bank_cntrl | 71 | 71 | 0 | 0 | 75 | 0 | 0 | 0 | +| bank_compare0 | arty_ddr3mig_7series_v4_2_bank_compare_5 | 8 | 8 | 0 | 0 | 35 | 0 | 0 | 0 | +| bank_queue0 | arty_ddr3mig_7series_v4_2_bank_queue | 41 | 41 | 0 | 0 | 18 | 0 | 0 | 0 | +| bank_state0 | arty_ddr3mig_7series_v4_2_bank_state | 23 | 23 | 0 | 0 | 22 | 0 | 0 | 0 | +| bank_cntrl[1].bank0 | arty_ddr3mig_7series_v4_2_bank_cntrl__parameterized0 | 69 | 69 | 0 | 0 | 73 | 0 | 0 | 0 | +| bank_compare0 | arty_ddr3mig_7series_v4_2_bank_compare_4 | 13 | 13 | 0 | 0 | 35 | 0 | 0 | 0 | +| bank_queue0 | arty_ddr3mig_7series_v4_2_bank_queue__parameterized0 | 36 | 36 | 0 | 0 | 18 | 0 | 0 | 0 | +| bank_state0 | arty_ddr3mig_7series_v4_2_bank_state__parameterized0 | 21 | 21 | 0 | 0 | 20 | 0 | 0 | 0 | +| bank_cntrl[2].bank0 | arty_ddr3mig_7series_v4_2_bank_cntrl__parameterized1 | 71 | 71 | 0 | 0 | 74 | 0 | 0 | 0 | +| bank_compare0 | arty_ddr3mig_7series_v4_2_bank_compare_3 | 10 | 10 | 0 | 0 | 35 | 0 | 0 | 0 | +| bank_queue0 | arty_ddr3mig_7series_v4_2_bank_queue__parameterized1 | 33 | 33 | 0 | 0 | 18 | 0 | 0 | 0 | +| bank_state0 | arty_ddr3mig_7series_v4_2_bank_state__parameterized1 | 28 | 28 | 0 | 0 | 21 | 0 | 0 | 0 | +| bank_cntrl[3].bank0 | arty_ddr3mig_7series_v4_2_bank_cntrl__parameterized2 | 71 | 71 | 0 | 0 | 73 | 0 | 0 | 0 | +| bank_compare0 | arty_ddr3mig_7series_v4_2_bank_compare | 14 | 14 | 0 | 0 | 35 | 0 | 0 | 0 | +| bank_queue0 | arty_ddr3mig_7series_v4_2_bank_queue__parameterized2 | 33 | 33 | 0 | 0 | 18 | 0 | 0 | 0 | +| bank_state0 | arty_ddr3mig_7series_v4_2_bank_state__parameterized2 | 25 | 25 | 0 | 0 | 20 | 0 | 0 | 0 | +| bank_common0 | arty_ddr3mig_7series_v4_2_bank_common | 26 | 26 | 0 | 0 | 22 | 0 | 0 | 0 | +| col_mach0 | arty_ddr3mig_7series_v4_2_col_mach | 26 | 18 | 8 | 0 | 26 | 0 | 0 | 0 | +| rank_mach0 | arty_ddr3mig_7series_v4_2_rank_mach | 81 | 80 | 0 | 1 | 66 | 0 | 0 | 0 | +| rank_cntrl[0].rank_cntrl0 | arty_ddr3mig_7series_v4_2_rank_cntrl | 10 | 9 | 0 | 1 | 13 | 0 | 0 | 0 | +| rank_common0 | arty_ddr3mig_7series_v4_2_rank_common | 71 | 71 | 0 | 0 | 53 | 0 | 0 | 0 | +| (rank_common0) | arty_ddr3mig_7series_v4_2_rank_common | 59 | 59 | 0 | 0 | 47 | 0 | 0 | 0 | +| maintenance_request.maint_arb0 | arty_ddr3mig_7series_v4_2_round_robin_arb | 12 | 12 | 0 | 0 | 6 | 0 | 0 | 0 | +| u_axi_mc | arty_ddr3mig_7series_v4_2_axi_mc | 599 | 462 | 0 | 137 | 532 | 0 | 0 | 0 | +| (u_axi_mc) | arty_ddr3mig_7series_v4_2_axi_mc | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| axi_mc_ar_channel_0 | arty_ddr3mig_7series_v4_2_axi_mc_ar_channel | 122 | 122 | 0 | 0 | 87 | 0 | 0 | 0 | +| (axi_mc_ar_channel_0) | arty_ddr3mig_7series_v4_2_axi_mc_ar_channel | 1 | 1 | 0 | 0 | 45 | 0 | 0 | 0 | +| ar_cmd_fsm_0 | arty_ddr3mig_7series_v4_2_axi_mc_cmd_fsm | 80 | 80 | 0 | 0 | 1 | 0 | 0 | 0 | +| axi_mc_cmd_translator_0 | arty_ddr3mig_7series_v4_2_axi_mc_cmd_translator_0 | 43 | 43 | 0 | 0 | 41 | 0 | 0 | 0 | +| axi_mc_incr_cmd_0 | arty_ddr3mig_7series_v4_2_axi_mc_incr_cmd_1 | 35 | 35 | 0 | 0 | 33 | 0 | 0 | 0 | +| axi_mc_wrap_cmd_0 | arty_ddr3mig_7series_v4_2_axi_mc_wrap_cmd_2 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| axi_mc_aw_channel_0 | arty_ddr3mig_7series_v4_2_axi_mc_aw_channel | 125 | 125 | 0 | 0 | 85 | 0 | 0 | 0 | +| (axi_mc_aw_channel_0) | arty_ddr3mig_7series_v4_2_axi_mc_aw_channel | 0 | 0 | 0 | 0 | 43 | 0 | 0 | 0 | +| aw_cmd_fsm_0 | arty_ddr3mig_7series_v4_2_axi_mc_wr_cmd_fsm | 79 | 79 | 0 | 0 | 1 | 0 | 0 | 0 | +| axi_mc_cmd_translator_0 | arty_ddr3mig_7series_v4_2_axi_mc_cmd_translator | 47 | 47 | 0 | 0 | 41 | 0 | 0 | 0 | +| axi_mc_incr_cmd_0 | arty_ddr3mig_7series_v4_2_axi_mc_incr_cmd | 39 | 39 | 0 | 0 | 33 | 0 | 0 | 0 | +| axi_mc_wrap_cmd_0 | arty_ddr3mig_7series_v4_2_axi_mc_wrap_cmd | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| axi_mc_b_channel_0 | arty_ddr3mig_7series_v4_2_axi_mc_b_channel | 11 | 7 | 0 | 4 | 9 | 0 | 0 | 0 | +| (axi_mc_b_channel_0) | arty_ddr3mig_7series_v4_2_axi_mc_b_channel | 1 | 1 | 0 | 0 | 5 | 0 | 0 | 0 | +| bid_fifo_0 | arty_ddr3mig_7series_v4_2_axi_mc_fifo | 11 | 7 | 0 | 4 | 4 | 0 | 0 | 0 | +| axi_mc_cmd_arbiter_0 | arty_ddr3mig_7series_v4_2_axi_mc_cmd_arbiter | 33 | 33 | 0 | 0 | 31 | 0 | 0 | 0 | +| axi_mc_r_channel_0 | arty_ddr3mig_7series_v4_2_axi_mc_r_channel | 160 | 27 | 0 | 133 | 24 | 0 | 0 | 0 | +| (axi_mc_r_channel_0) | arty_ddr3mig_7series_v4_2_axi_mc_r_channel | 0 | 0 | 0 | 0 | 12 | 0 | 0 | 0 | +| rd_data_fifo_0 | arty_ddr3mig_7series_v4_2_axi_mc_fifo__parameterized0 | 141 | 13 | 0 | 128 | 6 | 0 | 0 | 0 | +| transaction_fifo_0 | arty_ddr3mig_7series_v4_2_axi_mc_fifo__parameterized1 | 19 | 14 | 0 | 5 | 6 | 0 | 0 | 0 | +| axi_mc_w_channel_0 | arty_ddr3mig_7series_v4_2_axi_mc_w_channel | 147 | 147 | 0 | 0 | 294 | 0 | 0 | 0 | +| u_ui_top | arty_ddr3mig_7series_v4_2_ui_top | 391 | 195 | 196 | 0 | 550 | 0 | 0 | 0 | +| ui_cmd0 | arty_ddr3mig_7series_v4_2_ui_cmd | 38 | 38 | 0 | 0 | 54 | 0 | 0 | 0 | +| ui_rd_data0 | arty_ddr3mig_7series_v4_2_ui_rd_data | 118 | 26 | 92 | 0 | 163 | 0 | 0 | 0 | +| ui_wr_data0 | arty_ddr3mig_7series_v4_2_ui_wr_data | 235 | 131 | 104 | 0 | 333 | 0 | 0 | 0 | +| memory_cdc | toy_axi_cdc | 452 | 190 | 262 | 0 | 1212 | 0 | 0 | 0 | +| inst | toy_axi_cdcaxi_clock_converter_v2_1_30_axi_clock_converter | 452 | 190 | 262 | 0 | 1212 | 0 | 0 | 0 | +| (inst) | toy_axi_cdcaxi_clock_converter_v2_1_30_axi_clock_converter | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | +| gen_clock_conv.gen_async_conv.asyncfifo_axi | toy_axi_cdcfifo_generator_v13_2_10 | 451 | 189 | 262 | 0 | 1212 | 0 | 0 | 0 | +| inst_fifo_gen | toy_axi_cdcfifo_generator_v13_2_10_synth | 451 | 189 | 262 | 0 | 1212 | 0 | 0 | 0 | +| gaxi_full_lite.gread_ch.grach2.axi_rach | toy_axi_cdcfifo_generator_top | 73 | 39 | 34 | 0 | 174 | 0 | 0 | 0 | +| grf.rf | toy_axi_cdcfifo_generator_ramfifo | 73 | 39 | 34 | 0 | 174 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gcx.clkx | toy_axi_cdcclk_x_pntrs__xdcDup__4 | 12 | 12 | 0 | 0 | 40 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.gcx.clkx) | toy_axi_cdcclk_x_pntrs__xdcDup__4 | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | +| rd_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__17 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| wr_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__16 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.rd | toy_axi_cdcrd_logic_21 | 13 | 13 | 0 | 0 | 18 | 0 | 0 | 0 | +| gr1.gr1_int.rfwft | toy_axi_cdcrd_fwft_27 | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| gras.rsts | toy_axi_cdcrd_status_flags_as_28 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpntr | toy_axi_cdcrd_bin_cntr_29 | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.wr | toy_axi_cdcwr_logic_22 | 7 | 7 | 0 | 0 | 14 | 0 | 0 | 0 | +| gwas.wsts | toy_axi_cdcwr_status_flags_as_25 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| wpntr | toy_axi_cdcwr_bin_cntr_26 | 5 | 5 | 0 | 0 | 12 | 0 | 0 | 0 | +| gntv_or_sync_fifo.mem | toy_axi_cdcmemory_23 | 34 | 0 | 34 | 0 | 76 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.mem) | toy_axi_cdcmemory_23 | 0 | 0 | 0 | 0 | 38 | 0 | 0 | 0 | +| gdm.dm_gen.dm | toy_axi_cdcdmem_24 | 34 | 0 | 34 | 0 | 38 | 0 | 0 | 0 | +| rstblk | toy_axi_cdcreset_blk_ramfifo__xdcDup__4 | 7 | 7 | 0 | 0 | 26 | 0 | 0 | 0 | +| (rstblk) | toy_axi_cdcreset_blk_ramfifo__xdcDup__4 | 7 | 7 | 0 | 0 | 12 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__12 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | toy_axi_cdcxpm_cdc_single__parameterized1__17 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | toy_axi_cdcxpm_cdc_single__parameterized1__16 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__11 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gaxi_full_lite.gread_ch.grdch2.axi_rdch | toy_axi_cdcfifo_generator_top__parameterized2 | 131 | 39 | 92 | 0 | 368 | 0 | 0 | 0 | +| grf.rf | toy_axi_cdcfifo_generator_ramfifo__parameterized2 | 131 | 39 | 92 | 0 | 368 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gcx.clkx | toy_axi_cdcclk_x_pntrs | 12 | 12 | 0 | 0 | 40 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.gcx.clkx) | toy_axi_cdcclk_x_pntrs | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | +| rd_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| wr_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__18 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.rd | toy_axi_cdcrd_logic_14 | 13 | 13 | 0 | 0 | 18 | 0 | 0 | 0 | +| gr1.gr1_int.rfwft | toy_axi_cdcrd_fwft_18 | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| gras.rsts | toy_axi_cdcrd_status_flags_as_19 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpntr | toy_axi_cdcrd_bin_cntr_20 | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.wr | toy_axi_cdcwr_logic_15 | 7 | 7 | 0 | 0 | 14 | 0 | 0 | 0 | +| gwas.wsts | toy_axi_cdcwr_status_flags_as_16 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| wpntr | toy_axi_cdcwr_bin_cntr_17 | 5 | 5 | 0 | 0 | 12 | 0 | 0 | 0 | +| gntv_or_sync_fifo.mem | toy_axi_cdcmemory__parameterized2 | 92 | 0 | 92 | 0 | 270 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.mem) | toy_axi_cdcmemory__parameterized2 | 0 | 0 | 0 | 0 | 135 | 0 | 0 | 0 | +| gdm.dm_gen.dm | toy_axi_cdcdmem__parameterized2 | 92 | 0 | 92 | 0 | 135 | 0 | 0 | 0 | +| rstblk | toy_axi_cdcreset_blk_ramfifo | 7 | 7 | 0 | 0 | 26 | 0 | 0 | 0 | +| (rstblk) | toy_axi_cdcreset_blk_ramfifo | 7 | 7 | 0 | 0 | 12 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | toy_axi_cdcxpm_cdc_async_rst | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | toy_axi_cdcxpm_cdc_single__parameterized1 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | toy_axi_cdcxpm_cdc_single__parameterized1__18 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__13 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gaxi_full_lite.gwrite_ch.gwach2.axi_wach | toy_axi_cdcfifo_generator_top__xdcDup__1 | 71 | 37 | 34 | 0 | 174 | 0 | 0 | 0 | +| grf.rf | toy_axi_cdcfifo_generator_ramfifo__xdcDup__1 | 71 | 37 | 34 | 0 | 174 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gcx.clkx | toy_axi_cdcclk_x_pntrs__xdcDup__1 | 10 | 10 | 0 | 0 | 40 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.gcx.clkx) | toy_axi_cdcclk_x_pntrs__xdcDup__1 | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | +| rd_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__11 | 4 | 4 | 0 | 0 | 20 | 0 | 0 | 0 | +| wr_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__10 | 4 | 4 | 0 | 0 | 20 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.rd | toy_axi_cdcrd_logic_7 | 13 | 13 | 0 | 0 | 18 | 0 | 0 | 0 | +| gr1.gr1_int.rfwft | toy_axi_cdcrd_fwft_11 | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| gras.rsts | toy_axi_cdcrd_status_flags_as_12 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpntr | toy_axi_cdcrd_bin_cntr_13 | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.wr | toy_axi_cdcwr_logic_8 | 7 | 7 | 0 | 0 | 14 | 0 | 0 | 0 | +| gwas.wsts | toy_axi_cdcwr_status_flags_as_9 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| wpntr | toy_axi_cdcwr_bin_cntr_10 | 5 | 5 | 0 | 0 | 12 | 0 | 0 | 0 | +| gntv_or_sync_fifo.mem | toy_axi_cdcmemory | 34 | 0 | 34 | 0 | 76 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.mem) | toy_axi_cdcmemory | 0 | 0 | 0 | 0 | 38 | 0 | 0 | 0 | +| gdm.dm_gen.dm | toy_axi_cdcdmem | 34 | 0 | 34 | 0 | 38 | 0 | 0 | 0 | +| rstblk | toy_axi_cdcreset_blk_ramfifo__xdcDup__1 | 7 | 7 | 0 | 0 | 26 | 0 | 0 | 0 | +| (rstblk) | toy_axi_cdcreset_blk_ramfifo__xdcDup__1 | 7 | 7 | 0 | 0 | 12 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__6 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | toy_axi_cdcxpm_cdc_single__parameterized1__11 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | toy_axi_cdcxpm_cdc_single__parameterized1__10 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__5 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch | toy_axi_cdcfifo_generator_top__parameterized0 | 136 | 38 | 98 | 0 | 386 | 0 | 0 | 0 | +| grf.rf | toy_axi_cdcfifo_generator_ramfifo__parameterized0 | 136 | 38 | 98 | 0 | 386 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gcx.clkx | toy_axi_cdcclk_x_pntrs__xdcDup__2 | 11 | 11 | 0 | 0 | 40 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.gcx.clkx) | toy_axi_cdcclk_x_pntrs__xdcDup__2 | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | +| rd_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__13 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| wr_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__12 | 4 | 4 | 0 | 0 | 20 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.rd | toy_axi_cdcrd_logic_0 | 13 | 13 | 0 | 0 | 18 | 0 | 0 | 0 | +| gr1.gr1_int.rfwft | toy_axi_cdcrd_fwft_4 | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| gras.rsts | toy_axi_cdcrd_status_flags_as_5 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpntr | toy_axi_cdcrd_bin_cntr_6 | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.wr | toy_axi_cdcwr_logic_1 | 7 | 7 | 0 | 0 | 14 | 0 | 0 | 0 | +| gwas.wsts | toy_axi_cdcwr_status_flags_as_2 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| wpntr | toy_axi_cdcwr_bin_cntr_3 | 5 | 5 | 0 | 0 | 12 | 0 | 0 | 0 | +| gntv_or_sync_fifo.mem | toy_axi_cdcmemory__parameterized0 | 98 | 0 | 98 | 0 | 288 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.mem) | toy_axi_cdcmemory__parameterized0 | 0 | 0 | 0 | 0 | 144 | 0 | 0 | 0 | +| gdm.dm_gen.dm | toy_axi_cdcdmem__parameterized0 | 98 | 0 | 98 | 0 | 144 | 0 | 0 | 0 | +| rstblk | toy_axi_cdcreset_blk_ramfifo__xdcDup__2 | 7 | 7 | 0 | 0 | 26 | 0 | 0 | 0 | +| (rstblk) | toy_axi_cdcreset_blk_ramfifo__xdcDup__2 | 7 | 7 | 0 | 0 | 12 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__8 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | toy_axi_cdcxpm_cdc_single__parameterized1__13 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | toy_axi_cdcxpm_cdc_single__parameterized1__12 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__7 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch | toy_axi_cdcfifo_generator_top__parameterized1 | 41 | 37 | 4 | 0 | 110 | 0 | 0 | 0 | +| grf.rf | toy_axi_cdcfifo_generator_ramfifo__parameterized1 | 41 | 37 | 4 | 0 | 110 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gcx.clkx | toy_axi_cdcclk_x_pntrs__xdcDup__3 | 10 | 10 | 0 | 0 | 40 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.gcx.clkx) | toy_axi_cdcclk_x_pntrs__xdcDup__3 | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | +| rd_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__15 | 4 | 4 | 0 | 0 | 20 | 0 | 0 | 0 | +| wr_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__14 | 4 | 4 | 0 | 0 | 20 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.rd | toy_axi_cdcrd_logic | 13 | 13 | 0 | 0 | 18 | 0 | 0 | 0 | +| gr1.gr1_int.rfwft | toy_axi_cdcrd_fwft | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| gras.rsts | toy_axi_cdcrd_status_flags_as | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpntr | toy_axi_cdcrd_bin_cntr | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.wr | toy_axi_cdcwr_logic | 7 | 7 | 0 | 0 | 14 | 0 | 0 | 0 | +| gwas.wsts | toy_axi_cdcwr_status_flags_as | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| wpntr | toy_axi_cdcwr_bin_cntr | 5 | 5 | 0 | 0 | 12 | 0 | 0 | 0 | +| gntv_or_sync_fifo.mem | toy_axi_cdcmemory__parameterized1 | 4 | 0 | 4 | 0 | 12 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.mem) | toy_axi_cdcmemory__parameterized1 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | +| gdm.dm_gen.dm | toy_axi_cdcdmem__parameterized1 | 4 | 0 | 4 | 0 | 6 | 0 | 0 | 0 | +| rstblk | toy_axi_cdcreset_blk_ramfifo__xdcDup__3 | 7 | 7 | 0 | 0 | 26 | 0 | 0 | 0 | +| (rstblk) | toy_axi_cdcreset_blk_ramfifo__xdcDup__3 | 7 | 7 | 0 | 0 | 12 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__10 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | toy_axi_cdcxpm_cdc_single__parameterized1__15 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | toy_axi_cdcxpm_cdc_single__parameterized1__14 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__9 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| platform | toy_a7_platform | 48907 | 45851 | 2932 | 124 | 28587 | 27 | 8 | 117 | +| chip | ToyLinuxChip | 47912 | 44968 | 2820 | 124 | 27535 | 27 | 8 | 117 | +| system | ToyLinuxSystem | 47912 | 44968 | 2820 | 124 | 27535 | 27 | 8 | 117 | +| (system) | ToyLinuxSystem | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | +| bootrom_domain | bootromClockSinkDomain | 462 | 462 | 0 | 0 | 0 | 0 | 0 | 0 | +| bootrom | TLROM | 462 | 462 | 0 | 0 | 0 | 0 | 0 | 0 | +| cbus | PeripheryBus_cbus | 969 | 815 | 154 | 0 | 364 | 0 | 0 | 0 | +| atomics | TLAtomicAutomata_cbus | 377 | 377 | 0 | 0 | 203 | 0 | 0 | 0 | +| buffer | TLBuffer_a28d64s3k1z4u | 263 | 133 | 130 | 0 | 6 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a28d64s3k1z4u | 111 | 57 | 54 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q) | Queue2_TLBundleD_a28d64s3k1z4u | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x79_445 | 107 | 53 | 54 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a28d64s3k1z4u | 152 | 76 | 76 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a28d64s3k1z4u | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x114 | 151 | 75 | 76 | 0 | 0 | 0 | 0 | 0 | +| coupler_to_bootrom | TLInterconnectCoupler_cbus_to_bootrom | 74 | 74 | 0 | 0 | 29 | 0 | 0 | 0 | +| fragmenter | TLFragmenter_bootrom | 74 | 74 | 0 | 0 | 29 | 0 | 0 | 0 | +| (fragmenter) | TLFragmenter_bootrom | 1 | 1 | 0 | 0 | 9 | 0 | 0 | 0 | +| repeater | Repeater_TLBundleA_a17d64s3k1z3u | 73 | 73 | 0 | 0 | 20 | 0 | 0 | 0 | +| coupler_to_clint | TLInterconnectCoupler_cbus_to_clint | 79 | 79 | 0 | 0 | 32 | 0 | 0 | 0 | +| fragmenter | TLFragmenter_CLINT | 79 | 79 | 0 | 0 | 32 | 0 | 0 | 0 | +| (fragmenter) | TLFragmenter_CLINT | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | +| repeater | Repeater_TLBundleA_a26d64s3k1z3u | 79 | 79 | 0 | 0 | 23 | 0 | 0 | 0 | +| coupler_to_plic | TLInterconnectCoupler_cbus_to_plic | 24 | 24 | 0 | 0 | 42 | 0 | 0 | 0 | +| fragmenter | TLFragmenter_PLIC | 24 | 24 | 0 | 0 | 42 | 0 | 0 | 0 | +| (fragmenter) | TLFragmenter_PLIC | 3 | 3 | 0 | 0 | 9 | 0 | 0 | 0 | +| repeater | Repeater_TLBundleA_a28d64s3k1z3u | 21 | 21 | 0 | 0 | 33 | 0 | 0 | 0 | +| out_xbar | TLXbar_cbus_out_i1_o4_a28d64s3k1z4u | 81 | 81 | 0 | 0 | 17 | 0 | 0 | 0 | +| wrapped_error_device | ErrorDeviceWrapper | 77 | 53 | 24 | 0 | 35 | 0 | 0 | 0 | +| buffer | TLBuffer_a14d64s3k1z4u | 40 | 16 | 24 | 0 | 6 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a14d64s3k1z4u | 25 | 13 | 12 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q) | Queue2_TLBundleD_a14d64s3k1z4u | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x79 | 21 | 9 | 12 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a14d64s3k1z4u | 15 | 3 | 12 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a14d64s3k1z4u | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x100 | 13 | 1 | 12 | 0 | 0 | 0 | 0 | 0 | +| error | TLError | 37 | 37 | 0 | 0 | 29 | 0 | 0 | 0 | +| (error) | TLError | 7 | 7 | 0 | 0 | 18 | 0 | 0 | 0 | +| a_q | Queue1_TLBundleA_a14d64s3k1z4u | 30 | 30 | 0 | 0 | 11 | 0 | 0 | 0 | +| clint_domain | CLINTClockSinkDomain | 70 | 70 | 0 | 0 | 131 | 0 | 0 | 0 | +| clint | CLINT | 70 | 70 | 0 | 0 | 129 | 0 | 0 | 0 | +| intsource | IntSyncCrossingSource_n1x2 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| reg_0 | AsyncResetRegVec_w2_i0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| coh_wrapper | CoherenceManagerWrapper | 539 | 347 | 192 | 0 | 142 | 0 | 0 | 0 | +| broadcast_1 | TLBroadcast | 539 | 347 | 192 | 0 | 142 | 0 | 0 | 0 | +| (broadcast_1) | TLBroadcast | 16 | 16 | 0 | 0 | 44 | 0 | 0 | 0 | +| TLBroadcastTracker | TLBroadcastTracker | 379 | 283 | 96 | 0 | 49 | 0 | 0 | 0 | +| (TLBroadcastTracker) | TLBroadcastTracker | 20 | 20 | 0 | 0 | 44 | 0 | 0 | 0 | +| o_data_q | Queue4_TLBroadcastData_443 | 360 | 264 | 96 | 0 | 5 | 0 | 0 | 0 | +| (o_data_q) | Queue4_TLBroadcastData_443 | 99 | 99 | 0 | 0 | 5 | 0 | 0 | 0 | +| ram_ext | ram_4x144_444 | 261 | 165 | 96 | 0 | 0 | 0 | 0 | 0 | +| TLBroadcastTracker_1 | TLBroadcastTracker_1 | 147 | 51 | 96 | 0 | 49 | 0 | 0 | 0 | +| (TLBroadcastTracker_1) | TLBroadcastTracker_1 | 32 | 32 | 0 | 0 | 44 | 0 | 0 | 0 | +| o_data_q | Queue4_TLBroadcastData | 115 | 19 | 96 | 0 | 5 | 0 | 0 | 0 | +| (o_data_q) | Queue4_TLBroadcastData | 14 | 14 | 0 | 0 | 5 | 0 | 0 | 0 | +| ram_ext | ram_4x144 | 101 | 5 | 96 | 0 | 0 | 0 | 0 | 0 | +| ibus_intsink | IntSyncAsyncCrossingSink_n1x1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | +| chain | SynchronizerShiftReg_w1_d3 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | +| output_chain | NonSyncResetSynchronizerPrimitiveShiftReg_d3 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | +| ibus_intsource | IntSyncCrossingSource_n1x1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| reg_0__0 | AsyncResetRegVec_w1_i0_442 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| mbus | MemoryBus | 719 | 463 | 256 | 0 | 330 | 0 | 0 | 0 | +| coupler_to_memory_controller_port_named_axi4 | TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4 | 719 | 463 | 256 | 0 | 330 | 0 | 0 | 0 | +| axi4yank | AXI4UserYanker_1 | 439 | 183 | 256 | 0 | 96 | 0 | 0 | 0 | +| Queue2_BundleMap | Queue2_BundleMap_6 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap) | Queue2_BundleMap_6 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_441 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_1 | Queue2_BundleMap_6_380 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_1) | Queue2_BundleMap_6_380 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_440 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_10 | Queue2_BundleMap_6_381 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_10) | Queue2_BundleMap_6_381 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_439 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_11 | Queue2_BundleMap_6_382 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_11) | Queue2_BundleMap_6_382 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_438 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_12 | Queue2_BundleMap_6_383 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_12) | Queue2_BundleMap_6_383 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_437 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_13 | Queue2_BundleMap_6_384 | 9 | 1 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_13) | Queue2_BundleMap_6_384 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_436 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_14 | Queue2_BundleMap_6_385 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_14) | Queue2_BundleMap_6_385 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_435 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_15 | Queue2_BundleMap_6_386 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_15) | Queue2_BundleMap_6_386 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_434 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_16 | Queue2_BundleMap_6_387 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_16) | Queue2_BundleMap_6_387 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_433 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_17 | Queue2_BundleMap_6_388 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_17) | Queue2_BundleMap_6_388 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_432 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_18 | Queue2_BundleMap_6_389 | 14 | 6 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_18) | Queue2_BundleMap_6_389 | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_431 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_19 | Queue2_BundleMap_6_390 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_19) | Queue2_BundleMap_6_390 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_430 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_2 | Queue2_BundleMap_6_391 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_2) | Queue2_BundleMap_6_391 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_429 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_20 | Queue2_BundleMap_6_392 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_20) | Queue2_BundleMap_6_392 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_428 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_21 | Queue2_BundleMap_6_393 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_21) | Queue2_BundleMap_6_393 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_427 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_22 | Queue2_BundleMap_6_394 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_22) | Queue2_BundleMap_6_394 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_426 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_23 | Queue2_BundleMap_6_395 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_23) | Queue2_BundleMap_6_395 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_425 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_24 | Queue2_BundleMap_6_396 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_24) | Queue2_BundleMap_6_396 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_424 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_25 | Queue2_BundleMap_6_397 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_25) | Queue2_BundleMap_6_397 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_423 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_26 | Queue2_BundleMap_6_398 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_26) | Queue2_BundleMap_6_398 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_422 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_27 | Queue2_BundleMap_6_399 | 43 | 35 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_27) | Queue2_BundleMap_6_399 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_421 | 42 | 34 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_28 | Queue2_BundleMap_6_400 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_28) | Queue2_BundleMap_6_400 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_420 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_29 | Queue2_BundleMap_6_401 | 9 | 1 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_29) | Queue2_BundleMap_6_401 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_419 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_3 | Queue2_BundleMap_6_402 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_3) | Queue2_BundleMap_6_402 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_418 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_30 | Queue2_BundleMap_6_403 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_30) | Queue2_BundleMap_6_403 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_417 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_31 | Queue2_BundleMap_6_404 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_31) | Queue2_BundleMap_6_404 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_416 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_4 | Queue2_BundleMap_6_405 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_4) | Queue2_BundleMap_6_405 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_415 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_5 | Queue2_BundleMap_6_406 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_5) | Queue2_BundleMap_6_406 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_414 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_6 | Queue2_BundleMap_6_407 | 13 | 5 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_6) | Queue2_BundleMap_6_407 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_413 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_7 | Queue2_BundleMap_6_408 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_7) | Queue2_BundleMap_6_408 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_412 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_8 | Queue2_BundleMap_6_409 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_8) | Queue2_BundleMap_6_409 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_411 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_9 | Queue2_BundleMap_6_410 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_9) | Queue2_BundleMap_6_410 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| tl2axi4 | TLToAXI4_1 | 293 | 293 | 0 | 0 | 234 | 0 | 0 | 0 | +| (tl2axi4) | TLToAXI4_1 | 3 | 3 | 0 | 0 | 41 | 0 | 0 | 0 | +| nodeOut_w_deq_q | Queue1_AXI4BundleW_1 | 83 | 83 | 0 | 0 | 146 | 0 | 0 | 0 | +| queue_arw_deq_q | Queue1_AXI4BundleARW_1 | 208 | 208 | 0 | 0 | 47 | 0 | 0 | 0 | +| plic_domain | PLICClockSinkDomain | 33 | 33 | 0 | 0 | 52 | 0 | 0 | 0 | +| intsource | IntSyncCrossingSource_n1x1_377 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| reg_0 | AsyncResetRegVec_w1_i0_379 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| intsource_1 | IntSyncCrossingSource_n1x1_378 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| reg_0 | AsyncResetRegVec_w1_i0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| plic | TLPLIC | 33 | 33 | 0 | 0 | 50 | 0 | 0 | 0 | +| (plic) | TLPLIC | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | +| gateways_gateway | LevelGateway | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| out_back_front_q | Queue1_RegMapperInput_i23_m8 | 28 | 28 | 0 | 0 | 41 | 0 | 0 | 0 | +| sbus | SystemBus | 1370 | 1036 | 334 | 0 | 608 | 0 | 0 | 0 | +| coupler_to_bus_named_cbus | TLInterconnectCoupler_sbus_to_bus_named_cbus | 143 | 143 | 0 | 0 | 191 | 0 | 0 | 0 | +| widget | TLWidthWidget16 | 143 | 143 | 0 | 0 | 191 | 0 | 0 | 0 | +| (widget) | TLWidthWidget16 | 64 | 64 | 0 | 0 | 68 | 0 | 0 | 0 | +| repeated_repeater | Repeater_TLBundleA_a28d128s3k1z4u | 79 | 79 | 0 | 0 | 123 | 0 | 0 | 0 | +| coupler_to_port_named_mmio_port_axi4 | TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4 | 740 | 406 | 334 | 0 | 353 | 0 | 0 | 0 | +| axi4buf | AXI4Buffer | 204 | 66 | 138 | 0 | 15 | 0 | 0 | 0 | +| nodeIn_b_deq_q | Queue2_AXI4BundleB | 18 | 14 | 4 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_b_deq_q) | Queue2_AXI4BundleB | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x4 | 13 | 9 | 4 | 0 | 0 | 0 | 0 | 0 | +| nodeIn_r_deq_q | Queue2_AXI4BundleR | 42 | 6 | 36 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_r_deq_q) | Queue2_AXI4BundleR | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x69 | 39 | 3 | 36 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_ar_deq_q | Queue2_AXI4BundleAR | 59 | 27 | 32 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_ar_deq_q) | Queue2_AXI4BundleAR | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x58_376 | 55 | 23 | 32 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_aw_deq_q | Queue2_AXI4BundleAW | 47 | 15 | 32 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_aw_deq_q) | Queue2_AXI4BundleAW | 6 | 6 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x58 | 41 | 9 | 32 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_w_deq_q | Queue2_AXI4BundleW | 38 | 4 | 34 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_w_deq_q) | Queue2_AXI4BundleW | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x73 | 36 | 2 | 34 | 0 | 0 | 0 | 0 | 0 | +| axi4deint | AXI4Deinterleaver | 276 | 116 | 160 | 0 | 47 | 0 | 0 | 0 | +| (axi4deint) | AXI4Deinterleaver | 0 | 0 | 0 | 0 | 19 | 0 | 0 | 0 | +| qs_queue_0 | Queue8_AXI4BundleR | 51 | 11 | 40 | 0 | 7 | 0 | 0 | 0 | +| (qs_queue_0) | Queue8_AXI4BundleR | 8 | 8 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x77_375 | 43 | 3 | 40 | 0 | 0 | 0 | 0 | 0 | +| qs_queue_1 | Queue8_AXI4BundleR_370 | 73 | 33 | 40 | 0 | 7 | 0 | 0 | 0 | +| (qs_queue_1) | Queue8_AXI4BundleR_370 | 6 | 6 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x77_374 | 67 | 27 | 40 | 0 | 0 | 0 | 0 | 0 | +| qs_queue_2 | Queue8_AXI4BundleR_371 | 49 | 9 | 40 | 0 | 7 | 0 | 0 | 0 | +| (qs_queue_2) | Queue8_AXI4BundleR_371 | 6 | 6 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x77_373 | 43 | 3 | 40 | 0 | 0 | 0 | 0 | 0 | +| qs_queue_3 | Queue8_AXI4BundleR_372 | 104 | 64 | 40 | 0 | 7 | 0 | 0 | 0 | +| (qs_queue_3) | Queue8_AXI4BundleR_372 | 6 | 6 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x77 | 98 | 58 | 40 | 0 | 0 | 0 | 0 | 0 | +| axi4yank | AXI4UserYanker | 76 | 40 | 36 | 0 | 34 | 0 | 0 | 0 | +| Queue1_BundleMap | Queue1_BundleMap | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| Queue1_BundleMap_1 | Queue1_BundleMap_359 | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| Queue2_BundleMap | Queue2_BundleMap | 12 | 6 | 6 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap) | Queue2_BundleMap | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8_369 | 8 | 2 | 6 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_1 | Queue2_BundleMap_360 | 11 | 5 | 6 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_1) | Queue2_BundleMap_360 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8_368 | 8 | 2 | 6 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_2 | Queue2_BundleMap_361 | 12 | 6 | 6 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_2) | Queue2_BundleMap_361 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8_367 | 9 | 3 | 6 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_3 | Queue2_BundleMap_362 | 12 | 6 | 6 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_3) | Queue2_BundleMap_362 | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8_366 | 8 | 2 | 6 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_4 | Queue2_BundleMap_363 | 9 | 3 | 6 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_4) | Queue2_BundleMap_363 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8_365 | 8 | 2 | 6 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_5 | Queue2_BundleMap_364 | 9 | 3 | 6 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_5) | Queue2_BundleMap_364 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8 | 8 | 2 | 6 | 0 | 0 | 0 | 0 | 0 | +| tl2axi4 | TLToAXI4 | 86 | 86 | 0 | 0 | 114 | 0 | 0 | 0 | +| (tl2axi4) | TLToAXI4 | 22 | 22 | 0 | 0 | 17 | 0 | 0 | 0 | +| nodeOut_w_deq_q | Queue1_AXI4BundleW | 33 | 33 | 0 | 0 | 50 | 0 | 0 | 0 | +| queue_arw_deq_q | Queue1_AXI4BundleARW | 31 | 31 | 0 | 0 | 47 | 0 | 0 | 0 | +| widget | TLWidthWidget16_2 | 101 | 101 | 0 | 0 | 143 | 0 | 0 | 0 | +| (widget) | TLWidthWidget16_2 | 45 | 45 | 0 | 0 | 48 | 0 | 0 | 0 | +| repeated_repeater | Repeater_TLBundleA_a31d128s3k1z3u | 56 | 56 | 0 | 0 | 95 | 0 | 0 | 0 | +| system_bus_xbar | TLXbar_sbus_i2_o3_a32d128s3k1z4c | 490 | 490 | 0 | 0 | 64 | 0 | 0 | 0 | +| tile_prci_domain | TilePRCIDomain | 43756 | 41749 | 1884 | 123 | 25900 | 27 | 8 | 117 | +| buffer | TLBuffer_a32d128s2k1z4u_1 | 1208 | 624 | 584 | 0 | 21 | 0 | 0 | 0 | +| nodeIn_b_q | Queue2_TLBundleB_a32d128s2k1z4c | 28 | 4 | 24 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_b_q) | Queue2_TLBundleB_a32d128s2k1z4c | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x60 | 25 | 1 | 24 | 0 | 0 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a32d128s2k1z4u | 101 | 5 | 96 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q) | Queue2_TLBundleD_a32d128s2k1z4u | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x142_358 | 97 | 1 | 96 | 0 | 0 | 0 | 0 | 0 | +| nodeIn_d_q_1 | Queue2_TLBundleD_a32d128s2k1z4c | 158 | 62 | 96 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q_1) | Queue2_TLBundleD_a32d128s2k1z4c | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x142 | 156 | 60 | 96 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a32d128s2k1z4u | 144 | 16 | 128 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a32d128s2k1z4u | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x189_357 | 142 | 14 | 128 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q_1 | Queue2_TLBundleA_a32d128s2k1z4c | 644 | 518 | 126 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q_1) | Queue2_TLBundleA_a32d128s2k1z4c | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x189 | 641 | 515 | 126 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_c_q | Queue2_TLBundleC_a32d128s2k1z4c | 127 | 15 | 112 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_c_q) | Queue2_TLBundleC_a32d128s2k1z4c | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x173 | 125 | 13 | 112 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_e_q | Queue2_TLBundleE_a32d128s2k1z4c | 6 | 4 | 2 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_e_q) | Queue2_TLBundleE_a32d128s2k1z4c | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_sink_ext | ram_sink_2x1 | 3 | 1 | 2 | 0 | 0 | 0 | 0 | 0 | +| element_reset_domain_bbtile | BBTile | 42551 | 41128 | 1300 | 123 | 25879 | 27 | 8 | 117 | +| (element_reset_domain_bbtile) | BBTile | 24 | 0 | 24 | 0 | 0 | 0 | 0 | 0 | +| accelerators_0 | BuckyballAccelerator | 22610 | 21977 | 510 | 123 | 15033 | 18 | 0 | 95 | +| ballDomain | BallDomain | 13143 | 12830 | 190 | 123 | 10879 | 0 | 0 | 93 | +| ballRs | BallReservationStation | 144 | 48 | 96 | 0 | 5 | 0 | 0 | 0 | +| fifo | Queue4_BallReservationStation_Anon | 144 | 48 | 96 | 0 | 5 | 0 | 0 | 0 | +| (fifo) | Queue4_BallReservationStation_Anon | 3 | 3 | 0 | 0 | 5 | 0 | 0 | 0 | +| ram_ext | ram_4x281 | 141 | 45 | 96 | 0 | 0 | 0 | 0 | 0 | +| bbus | BBus | 13000 | 12783 | 94 | 123 | 10874 | 0 | 0 | 93 | +| (bbus) | BBus | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | +| balls_0 | GemminiBall | 13000 | 12783 | 94 | 123 | 10864 | 0 | 0 | 93 | +| (balls_0) | GemminiBall | 1 | 1 | 0 | 0 | 470 | 0 | 0 | 0 | +| convUnroller | LoopConvUnroller | 476 | 476 | 0 | 0 | 375 | 0 | 0 | 20 | +| (convUnroller) | LoopConvUnroller | 33 | 33 | 0 | 0 | 375 | 0 | 0 | 0 | +| addrGen | LoopConvAddrGen | 446 | 446 | 0 | 0 | 0 | 0 | 0 | 20 | +| exCtrl | GemminiExCtrl | 11897 | 11680 | 94 | 123 | 9717 | 0 | 0 | 64 | +| (exCtrl) | GemminiExCtrl | 1310 | 1310 | 0 | 0 | 2444 | 0 | 0 | 0 | +| mesh | MeshWithDelays | 10211 | 10082 | 6 | 123 | 7259 | 0 | 0 | 64 | +| (mesh) | MeshWithDelays | 530 | 407 | 0 | 123 | 557 | 0 | 0 | 0 | +| mesh | Mesh | 9035 | 9035 | 0 | 0 | 6098 | 0 | 0 | 64 | +| (mesh) | Mesh | 225 | 225 | 0 | 0 | 3530 | 0 | 0 | 0 | +| mesh_0_0 | Tile | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_354 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_354 | 92 | 92 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_355 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_356 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_1 | Tile_104 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_351 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_351 | 92 | 92 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_352 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_353 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_2 | Tile_105 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_348 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_348 | 92 | 92 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_349 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_350 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_3 | Tile_106 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_345 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_345 | 92 | 92 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_346 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_347 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_4 | Tile_107 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_342 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_342 | 92 | 92 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_343 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_344 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_5 | Tile_108 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_339 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_339 | 92 | 92 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_340 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_341 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_6 | Tile_109 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_336 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_336 | 92 | 92 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_337 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_338 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_7 | Tile_110 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_333 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_333 | 92 | 92 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_334 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_335 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_0 | Tile_111 | 137 | 137 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_330 | 137 | 137 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_330 | 88 | 88 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_331 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_332 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_1 | Tile_112 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_327 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_327 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_328 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_329 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_2 | Tile_113 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_324 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_324 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_325 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_326 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_3 | Tile_114 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_321 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_321 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_322 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_323 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_4 | Tile_115 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_318 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_318 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_319 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_320 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_5 | Tile_116 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_315 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_315 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_316 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_317 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_6 | Tile_117 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_312 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_312 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_313 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_314 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_7 | Tile_118 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_309 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_309 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_310 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_311 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_0 | Tile_119 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_306 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_306 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_307 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_308 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_1 | Tile_120 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_303 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_303 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_304 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_305 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_2 | Tile_121 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_300 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_300 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_301 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_302 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_3 | Tile_122 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_297 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_297 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_298 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_299 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_4 | Tile_123 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_294 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_294 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_295 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_296 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_5 | Tile_124 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_291 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_291 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_292 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_293 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_6 | Tile_125 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_288 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_288 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_289 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_290 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_7 | Tile_126 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_285 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_285 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_286 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_287 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_0 | Tile_127 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_282 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_282 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_283 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_284 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_1 | Tile_128 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_279 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_279 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_280 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_281 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_2 | Tile_129 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_276 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_276 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_277 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_278 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_3 | Tile_130 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_273 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_273 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_274 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_275 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_4 | Tile_131 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_270 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_270 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_271 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_272 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_5 | Tile_132 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_267 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_267 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_268 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_269 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_6 | Tile_133 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_264 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_264 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_265 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_266 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_7 | Tile_134 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_261 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_261 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_262 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_263 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_0 | Tile_135 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_258 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_258 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_259 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_260 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_1 | Tile_136 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_255 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_255 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_256 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_257 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_2 | Tile_137 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_252 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_252 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_253 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_254 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_3 | Tile_138 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_249 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_249 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_250 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_251 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_4 | Tile_139 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_246 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_246 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_247 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_248 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_5 | Tile_140 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_243 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_243 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_244 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_245 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_6 | Tile_141 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_240 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_240 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_241 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_242 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_7 | Tile_142 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_237 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_237 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_238 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_239 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_0 | Tile_143 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_234 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_234 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_235 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_236 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_1 | Tile_144 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_231 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_231 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_232 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_233 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_2 | Tile_145 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_228 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_228 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_229 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_230 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_3 | Tile_146 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_225 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_225 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_226 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_227 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_4 | Tile_147 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_222 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_222 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_223 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_224 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_5 | Tile_148 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_219 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_219 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_220 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_221 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_6 | Tile_149 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_216 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_216 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_217 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_218 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_7 | Tile_150 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_213 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_213 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_214 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_215 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_0 | Tile_151 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_210 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_210 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_211 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_212 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_1 | Tile_152 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_207 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_207 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_208 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_209 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_2 | Tile_153 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_204 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_204 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_205 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_206 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_3 | Tile_154 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_201 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_201 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_202 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_203 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_4 | Tile_155 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_198 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_198 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_199 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_200 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_5 | Tile_156 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_195 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_195 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_196 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_197 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_6 | Tile_157 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_192 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_192 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_193 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_194 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_7 | Tile_158 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_189 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_189 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_190 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_191 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_0 | Tile_159 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_186 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_186 | 95 | 95 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_187 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_188 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_1 | Tile_160 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_183 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_183 | 96 | 96 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_184 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_185 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_2 | Tile_161 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_180 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_180 | 96 | 96 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_181 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_182 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_3 | Tile_162 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_177 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_177 | 96 | 96 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_178 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_179 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_4 | Tile_163 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_174 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_174 | 96 | 96 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_175 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_176 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_5 | Tile_164 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_171 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_171 | 96 | 96 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_172 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_173 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_6 | Tile_165 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_168 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_168 | 96 | 96 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_169 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_170 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_7 | Tile_166 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_167 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_167 | 96 | 96 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| tagq | TagQueue | 106 | 106 | 0 | 0 | 75 | 0 | 0 | 0 | +| total_rows_q | Queue6_TagWithIdAndTotalRows | 30 | 24 | 6 | 0 | 7 | 0 | 0 | 0 | +| (total_rows_q) | Queue6_TagWithIdAndTotalRows | 5 | 5 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_6x7 | 25 | 19 | 6 | 0 | 0 | 0 | 0 | 0 | +| transposer | AlwaysOutTransposer | 511 | 511 | 0 | 0 | 522 | 0 | 0 | 0 | +| (transposer) | AlwaysOutTransposer | 5 | 5 | 0 | 0 | 10 | 0 | 0 | 0 | +| pes_0_0 | PE | 17 | 17 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_1 | PE_41 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_2 | PE_42 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_3 | PE_43 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_4 | PE_44 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_5 | PE_45 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_6 | PE_46 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_7 | PE_47 | 32 | 32 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_0 | PE_48 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_1 | PE_49 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_2 | PE_50 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_3 | PE_51 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_4 | PE_52 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_5 | PE_53 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_6 | PE_54 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_7 | PE_55 | 13 | 13 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_0 | PE_56 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_1 | PE_57 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_2 | PE_58 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_3 | PE_59 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_4 | PE_60 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_5 | PE_61 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_6 | PE_62 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_7 | PE_63 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_0 | PE_64 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_1 | PE_65 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_2 | PE_66 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_3 | PE_67 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_4 | PE_68 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_5 | PE_69 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_6 | PE_70 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_7 | PE_71 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_0 | PE_72 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_1 | PE_73 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_2 | PE_74 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_3 | PE_75 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_4 | PE_76 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_5 | PE_77 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_6 | PE_78 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_7 | PE_79 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_0 | PE_80 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_1 | PE_81 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_2 | PE_82 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_3 | PE_83 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_4 | PE_84 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_5 | PE_85 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_6 | PE_86 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_7 | PE_87 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_0 | PE_88 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_1 | PE_89 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_2 | PE_90 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_3 | PE_91 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_4 | PE_92 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_5 | PE_93 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_6 | PE_94 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_7 | PE_95 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_0 | PE_96 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_1 | PE_97 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_2 | PE_98 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_3 | PE_99 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_4 | PE_100 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_5 | PE_101 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_6 | PE_102 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_7 | PE_103 | 16 | 16 | 0 | 0 | 8 | 0 | 0 | 0 | +| rdQueue0 | Queue8_SramReadResp | 305 | 261 | 44 | 0 | 7 | 0 | 0 | 0 | +| (rdQueue0) | Queue8_SramReadResp | 100 | 100 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_data_ext | ram_data_8x64_40 | 206 | 162 | 44 | 0 | 0 | 0 | 0 | 0 | +| rdQueue1 | Queue8_SramReadResp_39 | 83 | 39 | 44 | 0 | 7 | 0 | 0 | 0 | +| (rdQueue1) | Queue8_SramReadResp_39 | 38 | 38 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_data_ext | ram_data_8x64 | 46 | 2 | 44 | 0 | 0 | 0 | 0 | 0 | +| matmulUnroller | LoopMatmulUnroller | 626 | 626 | 0 | 0 | 302 | 0 | 0 | 9 | +| cmdRouter | CmdRouter | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| bankReadReqQ_q | Queue8_BuckyballAccelerator_Anon | 32 | 16 | 16 | 0 | 7 | 0 | 0 | 0 | +| (bankReadReqQ_q) | Queue8_BuckyballAccelerator_Anon | 6 | 6 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x21_38 | 26 | 10 | 16 | 0 | 0 | 0 | 0 | 0 | +| bankReadReqQ_q_1 | Queue8_BuckyballAccelerator_Anon_10 | 34 | 18 | 16 | 0 | 7 | 0 | 0 | 0 | +| (bankReadReqQ_q_1) | Queue8_BuckyballAccelerator_Anon_10 | 5 | 5 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x21 | 29 | 13 | 16 | 0 | 0 | 0 | 0 | 0 | +| frontend | Frontend_1 | 5105 | 4909 | 196 | 0 | 2205 | 2 | 0 | 0 | +| boot | BootRom | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 | +| scheduler | GlobalScheduler | 5096 | 4900 | 196 | 0 | 2199 | 2 | 0 | 0 | +| (scheduler) | GlobalScheduler | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | +| completeQueue | Queue16_UInt4 | 34 | 30 | 4 | 0 | 9 | 0 | 0 | 0 | +| (completeQueue) | Queue16_UInt4 | 10 | 10 | 0 | 0 | 9 | 0 | 0 | 0 | +| ram_ext | ram_16x4 | 24 | 20 | 4 | 0 | 0 | 0 | 0 | 0 | +| rob | GlobalROB | 4572 | 4572 | 0 | 0 | 1668 | 2 | 0 | 0 | +| (rob) | GlobalROB | 1439 | 1439 | 0 | 0 | 1476 | 0 | 0 | 0 | +| bat | BankAliasTable | 1006 | 1006 | 0 | 0 | 176 | 0 | 0 | 0 | +| robOperands | robOperands | 1721 | 1721 | 0 | 0 | 0 | 2 | 0 | 0 | +| robOperands_ext | robOperands_ext | 1721 | 1721 | 0 | 0 | 0 | 2 | 0 | 0 | +| scoreboard | BankScoreboard | 421 | 421 | 0 | 0 | 16 | 0 | 0 | 0 | +| subRob | SubROB | 492 | 300 | 192 | 0 | 519 | 0 | 0 | 0 | +| (subRob) | SubROB | 299 | 299 | 0 | 0 | 273 | 0 | 0 | 0 | +| sram | sram | 195 | 3 | 192 | 0 | 246 | 0 | 0 | 0 | +| sram_ext | sram_ext | 195 | 3 | 192 | 0 | 246 | 0 | 0 | 0 | +| gpDomain | GpDomain | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | +| completeQ | Queue1_GlobalSchedComplete | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | +| memDomain | MemDomain | 4300 | 4208 | 92 | 0 | 1928 | 16 | 0 | 2 | +| backend | MemBackend | 2149 | 2149 | 0 | 0 | 472 | 16 | 0 | 0 | +| privateBackend | PrivateMemBackend | 2149 | 2149 | 0 | 0 | 472 | 16 | 0 | 0 | +| (privateBackend) | PrivateMemBackend | 200 | 200 | 0 | 0 | 243 | 0 | 0 | 0 | +| accPipes_0 | AccPipe | 285 | 285 | 0 | 0 | 67 | 0 | 0 | 0 | +| accPipes_1 | AccPipe_11 | 265 | 265 | 0 | 0 | 67 | 0 | 0 | 0 | +| accPipes_2 | AccPipe_12 | 57 | 57 | 0 | 0 | 3 | 0 | 0 | 0 | +| accPipes_3 | AccPipe_13 | 282 | 282 | 0 | 0 | 3 | 0 | 0 | 0 | +| accPipes_4 | AccPipe_14 | 325 | 325 | 0 | 0 | 3 | 0 | 0 | 0 | +| accPipes_5 | AccPipe_15 | 508 | 508 | 0 | 0 | 3 | 0 | 0 | 0 | +| accPipes_6 | AccPipe_16 | 227 | 227 | 0 | 0 | 67 | 0 | 0 | 0 | +| banks_0 | SramBank | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_0) | SramBank | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_36 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_37 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_1 | SramBank_17 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_1) | SramBank_17 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_34 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_35 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_2 | SramBank_18 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_2) | SramBank_18 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_32 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_33 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_3 | SramBank_19 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_3) | SramBank_19 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_30 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_31 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_4 | SramBank_20 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_4) | SramBank_20 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_28 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_29 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_5 | SramBank_21 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_5) | SramBank_21 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_26 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_27 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_6 | SramBank_22 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_6) | SramBank_22 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_24 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_25 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_7 | SramBank_23 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_7) | SramBank_23 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| frontend | MemFrontend | 2117 | 2025 | 92 | 0 | 1446 | 0 | 0 | 2 | +| (frontend) | MemFrontend | 574 | 574 | 0 | 0 | 2 | 0 | 0 | 0 | +| configer | MemConfiger | 133 | 133 | 0 | 0 | 63 | 0 | 0 | 0 | +| (configer) | MemConfiger | 95 | 95 | 0 | 0 | 29 | 0 | 0 | 0 | +| zeroLines | ZeroLineGenerator | 39 | 39 | 0 | 0 | 34 | 0 | 0 | 0 | +| groupQuery | MemGroupQueryArbiter | 7 | 7 | 0 | 0 | 12 | 0 | 0 | 0 | +| (groupQuery) | MemGroupQueryArbiter | 7 | 7 | 0 | 0 | 11 | 0 | 0 | 0 | +| arbiter | RRArbiter_2 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| memLoader | MemLoader | 240 | 240 | 0 | 0 | 242 | 0 | 0 | 0 | +| memRs | MemReservationStation | 164 | 72 | 92 | 0 | 5 | 0 | 0 | 0 | +| fifo | Queue4_MemReservationStation_Anon | 164 | 72 | 92 | 0 | 5 | 0 | 0 | 0 | +| (fifo) | Queue4_MemReservationStation_Anon | 3 | 3 | 0 | 0 | 5 | 0 | 0 | 0 | +| ram_ext | ram_4x158 | 161 | 69 | 92 | 0 | 0 | 0 | 0 | 0 | +| memStorer | MemStorer | 380 | 380 | 0 | 0 | 447 | 0 | 0 | 0 | +| reader | StreamReader | 542 | 542 | 0 | 0 | 304 | 0 | 0 | 2 | +| tlbCluster | BBTLBCluster | 142 | 142 | 0 | 0 | 261 | 0 | 0 | 0 | +| (tlbCluster) | BBTLBCluster | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| tlb | TLB | 142 | 142 | 0 | 0 | 259 | 0 | 0 | 0 | +| tlbArb | RRArbiter_1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| writer | StreamWriter | 5 | 5 | 0 | 0 | 110 | 0 | 0 | 0 | +| midend | MemMidend | 38 | 38 | 0 | 0 | 10 | 0 | 0 | 0 | +| barrierUnit | BarrierUnit | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | +| buffer | TLBuffer_a32d64s1k1z4u | 127 | 49 | 78 | 0 | 6 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a32d64s1k1z4u_7 | 93 | 41 | 52 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q) | Queue2_TLBundleD_a32d64s1k1z4u_7 | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x77 | 90 | 38 | 52 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a32d64s1k1z4u_8 | 34 | 8 | 26 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a32d64s1k1z4u_8 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x116_9 | 31 | 5 | 26 | 0 | 0 | 0 | 0 | 0 | +| buffer_1 | TLBuffer_a32d64s1k1z4u_1 | 111 | 41 | 70 | 0 | 6 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a32d64s1k1z4u | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a32d64s1k1z4u | 107 | 37 | 70 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a32d64s1k1z4u | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x116 | 104 | 34 | 70 | 0 | 0 | 0 | 0 | 0 | +| buffer_2 | TLBuffer_a32d64s2k1z4u | 237 | 105 | 132 | 0 | 6 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a32d64s2k1z4u | 56 | 4 | 52 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q) | Queue2_TLBundleD_a32d64s2k1z4u | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x78 | 53 | 1 | 52 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a32d64s2k1z4u | 181 | 101 | 80 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a32d64s2k1z4u | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x117 | 180 | 100 | 80 | 0 | 0 | 0 | 0 | 0 | +| cores_0 | RocketBB | 5905 | 5817 | 88 | 0 | 1895 | 0 | 0 | 13 | +| (cores_0) | RocketBB | 2332 | 2332 | 0 | 0 | 753 | 0 | 0 | 0 | +| csr | CSRFile | 1828 | 1828 | 0 | 0 | 869 | 0 | 0 | 0 | +| div | MulDiv | 1530 | 1530 | 0 | 0 | 214 | 0 | 0 | 13 | +| ibuf | IBuf | 101 | 101 | 0 | 0 | 59 | 0 | 0 | 0 | +| rf_ext | rf_31x64 | 119 | 31 | 88 | 0 | 0 | 0 | 0 | 0 | +| dcache | NonBlockingDCache | 2954 | 2862 | 92 | 0 | 3330 | 9 | 0 | 0 | +| (dcache) | NonBlockingDCache | 514 | 514 | 0 | 0 | 1150 | 0 | 0 | 0 | +| data | DataArray | 192 | 192 | 0 | 0 | 2 | 8 | 0 | 0 | +| (data) | DataArray | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| array_0_0 | array_0_0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_0_0_ext | array_0_0_ext_6 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_0_1 | array_0_1 | 64 | 64 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_0_0_ext | array_0_0_ext_5 | 64 | 64 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_2_0 | array_2_0 | 64 | 64 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_0_0_ext | array_0_0_ext_4 | 64 | 64 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_2_1 | array_2_1 | 128 | 128 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_0_0_ext | array_0_0_ext | 128 | 128 | 0 | 0 | 0 | 2 | 0 | 0 | +| dtlb | DTLB | 1147 | 1147 | 0 | 0 | 1692 | 0 | 0 | 0 | +| lfsr_prng | MaxPeriodFibonacciLFSR_3 | 12 | 12 | 0 | 0 | 16 | 0 | 0 | 0 | +| meta | L1MetadataArray | 129 | 37 | 92 | 0 | 98 | 0 | 0 | 0 | +| (meta) | L1MetadataArray | 3 | 3 | 0 | 0 | 6 | 0 | 0 | 0 | +| tag_array | tag_array | 126 | 34 | 92 | 0 | 92 | 0 | 0 | 0 | +| tag_array_ext | tag_array_ext | 126 | 34 | 92 | 0 | 92 | 0 | 0 | 0 | +| mshrs | MSHRFile | 632 | 632 | 0 | 0 | 292 | 1 | 0 | 0 | +| (mshrs) | MSHRFile | 2 | 2 | 0 | 0 | 26 | 0 | 0 | 0 | +| mmios_0 | IOMSHR | 261 | 261 | 0 | 0 | 180 | 0 | 0 | 0 | +| mshrs_0 | MSHR | 297 | 297 | 0 | 0 | 86 | 0 | 0 | 0 | +| (mshrs_0) | MSHR | 117 | 117 | 0 | 0 | 75 | 0 | 0 | 0 | +| grantackq | Queue1_TLBundleE_a32d128s1k1z4c | 72 | 72 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpq | Queue16_ReplayInternal | 109 | 109 | 0 | 0 | 9 | 0 | 0 | 0 | +| sdq_ext | sdq_17x64 | 77 | 77 | 0 | 0 | 0 | 1 | 0 | 0 | +| prober | ProbeUnit | 78 | 78 | 0 | 0 | 40 | 0 | 0 | 0 | +| wb | WritebackUnit | 256 | 256 | 0 | 0 | 40 | 0 | 0 | 0 | +| dcacheArb | HellaCacheArbiter | 15 | 15 | 0 | 0 | 4 | 0 | 0 | 0 | +| fpuOpts_0 | FPU | 7790 | 7526 | 264 | 0 | 2618 | 0 | 0 | 9 | +| (fpuOpts_0) | FPU | 26 | 26 | 0 | 0 | 193 | 0 | 0 | 0 | +| divSqrt | DivSqrtRecFM_small_e5_s11 | 150 | 150 | 0 | 0 | 60 | 0 | 0 | 0 | +| divSqrtRecFNToRaw | DivSqrtRecFMToRaw_small_e5_s11 | 150 | 150 | 0 | 0 | 60 | 0 | 0 | 0 | +| divSqrtRawFN | DivSqrtRawFN_small_e5_s11 | 150 | 150 | 0 | 0 | 60 | 0 | 0 | 0 | +| roundRawFNToRecFN | RoundRawFNToRecFN_e5_s11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie5_is13_oe5_os11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| divSqrt_1 | DivSqrtRecFM_small_e8_s24 | 316 | 316 | 0 | 0 | 103 | 0 | 0 | 0 | +| divSqrtRecFNToRaw | DivSqrtRecFMToRaw_small_e8_s24 | 312 | 312 | 0 | 0 | 103 | 0 | 0 | 0 | +| divSqrtRawFN | DivSqrtRawFN_small_e8_s24 | 312 | 312 | 0 | 0 | 103 | 0 | 0 | 0 | +| roundRawFNToRecFN | RoundRawFNToRecFN_e8_s24 | 5 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie8_is26_oe8_os24 | 5 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | +| divSqrt_2 | DivSqrtRecFM_small_e11_s53 | 844 | 844 | 0 | 0 | 195 | 0 | 0 | 0 | +| divSqrtRecFNToRaw | DivSqrtRecFMToRaw_small_e11_s53 | 835 | 835 | 0 | 0 | 195 | 0 | 0 | 0 | +| divSqrtRawFN | DivSqrtRawFN_small_e11_s53 | 835 | 835 | 0 | 0 | 195 | 0 | 0 | 0 | +| roundRawFNToRecFN | RoundRawFNToRecFN_e11_s53 | 9 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie11_is55_oe11_os53 | 9 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | +| fpiu | FPToInt | 1020 | 1020 | 0 | 0 | 140 | 0 | 0 | 0 | +| (fpiu) | FPToInt | 970 | 970 | 0 | 0 | 140 | 0 | 0 | 0 | +| dcmp | CompareRecFN | 51 | 51 | 0 | 0 | 0 | 0 | 0 | 0 | +| fpmu | FPToFP | 418 | 418 | 0 | 0 | 208 | 0 | 0 | 0 | +| (fpmu) | FPToFP | 83 | 83 | 0 | 0 | 208 | 0 | 0 | 0 | +| narrower | RecFNToRecFN | 125 | 125 | 0 | 0 | 0 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie11_is53_oe5_os11 | 125 | 125 | 0 | 0 | 0 | 0 | 0 | 0 | +| narrower_1 | RecFNToRecFN_1 | 215 | 215 | 0 | 0 | 0 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie11_is53_oe8_os24 | 215 | 215 | 0 | 0 | 0 | 0 | 0 | 0 | +| ifpu | IntToFP | 1520 | 1520 | 0 | 0 | 695 | 0 | 0 | 0 | +| (ifpu) | IntToFP | 61 | 61 | 0 | 0 | 140 | 0 | 0 | 0 | +| i2f_0 | PipelinedINToRecFN | 779 | 779 | 0 | 0 | 281 | 0 | 0 | 0 | +| (i2f_0) | PipelinedINToRecFN | 753 | 753 | 0 | 0 | 281 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie7_is64_oe5_os11 | 27 | 27 | 0 | 0 | 0 | 0 | 0 | 0 | +| i2f_1 | PipelinedINToRecFN_1 | 344 | 344 | 0 | 0 | 137 | 0 | 0 | 0 | +| (i2f_1) | PipelinedINToRecFN_1 | 316 | 316 | 0 | 0 | 137 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie7_is64_oe8_os24 | 28 | 28 | 0 | 0 | 0 | 0 | 0 | 0 | +| i2f_2 | PipelinedINToRecFN_2 | 342 | 342 | 0 | 0 | 137 | 0 | 0 | 0 | +| (i2f_2) | PipelinedINToRecFN_2 | 301 | 301 | 0 | 0 | 137 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie7_is64_oe11_os53 | 41 | 41 | 0 | 0 | 0 | 0 | 0 | 0 | +| regfile_ext | regfile_32x65 | 1066 | 802 | 264 | 0 | 32 | 0 | 0 | 0 | +| sharedFma | FPUSharedFMAPipe | 2442 | 2442 | 0 | 0 | 992 | 0 | 0 | 9 | +| (sharedFma) | FPUSharedFMAPipe | 15 | 15 | 0 | 0 | 238 | 0 | 0 | 0 | +| fma | SharedMulAddRecFNPipe | 2428 | 2428 | 0 | 0 | 754 | 0 | 0 | 9 | +| frontend | Frontend | 2041 | 1999 | 42 | 0 | 2221 | 0 | 8 | 0 | +| (frontend) | Frontend | 3 | 3 | 0 | 0 | 90 | 0 | 0 | 0 | +| fq | ShiftQueue | 746 | 746 | 0 | 0 | 375 | 0 | 0 | 0 | +| icache | ICache | 545 | 503 | 42 | 0 | 294 | 0 | 8 | 0 | +| (icache) | ICache | 264 | 264 | 0 | 0 | 236 | 0 | 0 | 0 | +| bbtile_icache_data_arrays_0 | bbtile_icache_data_arrays_0 | 2 | 2 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_0_ext | bbtile_icache_data_arrays_0_ext_2 | 2 | 2 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_1 | bbtile_icache_data_arrays_1 | 43 | 43 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_0_ext | bbtile_icache_data_arrays_0_ext_1 | 43 | 43 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_2 | bbtile_icache_data_arrays_2 | 2 | 2 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_0_ext | bbtile_icache_data_arrays_0_ext_0 | 2 | 2 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_3 | bbtile_icache_data_arrays_3 | 45 | 45 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_0_ext | bbtile_icache_data_arrays_0_ext | 45 | 45 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_tag_array | bbtile_icache_tag_array | 63 | 21 | 42 | 0 | 42 | 0 | 0 | 0 | +| bbtile_icache_tag_array_ext | bbtile_icache_tag_array_ext | 63 | 21 | 42 | 0 | 42 | 0 | 0 | 0 | +| repl_way_v0_prng | MaxPeriodFibonacciLFSR | 129 | 129 | 0 | 0 | 16 | 0 | 0 | 0 | +| tlb | ITLB | 750 | 750 | 0 | 0 | 1462 | 0 | 0 | 0 | +| ptw | PTW | 678 | 678 | 0 | 0 | 567 | 0 | 0 | 0 | +| roccMemIF | SimpleHellaCacheIF | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| (roccMemIF) | SimpleHellaCacheIF | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| replayq | SimpleHellaCacheIFReplayQueue | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 | +| (replayq) | SimpleHellaCacheIFReplayQueue | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| nackq | Queue3_UInt2 | 8 | 8 | 0 | 0 | 5 | 0 | 0 | 0 | +| tlMasterXbar | TLXbar_MasterXbar_BBTile_i2_o1_a32d128s2k1z4c | 42 | 42 | 0 | 0 | 11 | 0 | 0 | 0 | +| widget_3 | TLWidthWidget8_4 | 78 | 78 | 0 | 0 | 160 | 0 | 0 | 0 | +| (widget_3) | TLWidthWidget8_4 | 1 | 1 | 0 | 0 | 81 | 0 | 0 | 0 | +| repeated_repeater | Repeater_TLBundleD_a32d128s2k1z4u | 77 | 77 | 0 | 0 | 79 | 0 | 0 | 0 | +| xbar | TLXbar_i2_o1_a32d64s2k1z4u | 60 | 60 | 0 | 0 | 13 | 0 | 0 | 0 | +| load_bridge | loader_axi | 41 | 41 | 0 | 0 | 306 | 0 | 0 | 0 | +| loader | ddr_uart_loader | 435 | 371 | 64 | 0 | 159 | 0 | 0 | 0 | +| normalizer | axi_fullwidth | 330 | 330 | 0 | 0 | 376 | 0 | 0 | 0 | +| peripherals | axi_scu | 147 | 99 | 48 | 0 | 162 | 0 | 0 | 0 | +| receiver | uart_rx | 37 | 37 | 0 | 0 | 31 | 0 | 0 | 0 | +| transmitter | uart_tx | 13 | 13 | 0 | 0 | 18 | 0 | 0 | 0 | ++----------------------------------------------------------------------------------------+-----------------------------------------------------------------+------------+------------+---------+------+-------+--------+--------+------------+ +* Note: The sum of lower-level cells may be larger than their parent cells total, due to cross-hierarchy LUT combining + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/routed-timing.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/routed-timing.rpt new file mode 100644 index 0000000..71fe54f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/routed-timing.rpt @@ -0,0 +1,6691 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Mon Oct 12 20:36:17 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/routed-timing.rpt +| Design : toy_a7_top +| Device : 7a100t-csg324 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +| Design State : Routed +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : No + Borrow Time for Max Delay Exceptions : Yes + Merge Timing Exceptions : Yes + Inter-SLR Compensation : Conservative + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + +------------------------------------------------------------------------------------------------ +| Report Methodology +| ------------------ +------------------------------------------------------------------------------------------------ + +No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations. + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock (0) +2. checking constant_clock (0) +3. checking pulse_width_clock (0) +4. checking unconstrained_internal_endpoints (0) +5. checking no_input_delay (2) +6. checking no_output_delay (6) +7. checking multiple_clock (0) +8. checking generated_clocks (0) +9. checking loops (0) +10. checking partial_input_delay (0) +11. checking partial_output_delay (0) +12. checking latch_loops (0) + +1. checking no_clock (0) +------------------------ + There are 0 register/latch pins with no clock. + + +2. checking constant_clock (0) +------------------------------ + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock (0) +--------------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints (0) +------------------------------------------------ + There are 0 pins that are not constrained for maximum delay. + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay (2) +------------------------------ + There are 0 input ports with no input delay specified. + + There are 2 input ports with no input delay but user has a false path constraint. (MEDIUM) + +btn0 +uart_txd_in + + +6. checking no_output_delay (6) +------------------------------- + There are 0 ports with no output delay specified. + + There are 6 ports with no output delay but user has a false path constraint (MEDIUM) + +ddr3_reset_n +led[0] +led[1] +led[2] +led[3] +uart_rxd_out + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock (0) +------------------------------ + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks (0) +-------------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops (0) +--------------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay (0) +------------------------------------ + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay (0) +------------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops (0) +---------------------------- + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + 1.276 0.000 0 107738 0.012 0.000 0 107696 0.187 0.000 0 41738 + + +All user specified timing constraints are met. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + +Clock Waveform(ns) Period(ns) Frequency(MHz) +----- ------------ ---------- -------------- +board_clk {0.000 5.000} 10.000 100.000 + core_raw {0.000 20.000} 40.000 25.000 + fb {0.000 5.000} 10.000 100.000 + ref_raw {0.000 2.500} 5.000 200.000 + sys_raw {0.000 3.000} 6.000 166.667 + freq_refclk {0.000 0.750} 1.500 666.667 + u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk {0.000 1.500} 3.000 333.333 + iserdes_clkdiv {0.000 6.000} 12.000 83.333 + u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk {0.000 1.500} 3.000 333.333 + iserdes_clkdiv_1 {0.000 6.000} 12.000 83.333 + mem_refclk {0.000 1.500} 3.000 333.333 + oserdes_clk {0.000 1.500} 3.000 333.333 + oserdes_clkdiv {0.000 6.000} 12.000 83.333 + oserdes_clk_1 {0.000 1.500} 3.000 333.333 + oserdes_clkdiv_1 {0.000 6.000} 12.000 83.333 + oserdes_clk_2 {0.000 1.500} 3.000 333.333 + oserdes_clkdiv_2 {0.000 3.000} 6.000 166.667 + oserdes_clk_3 {0.000 1.500} 3.000 333.333 + oserdes_clkdiv_3 {0.000 3.000} 6.000 166.667 + pll_clk3_out {0.000 6.000} 12.000 83.333 + clk_pll_i {0.000 6.000} 12.000 83.333 + pll_clkfbout {0.000 3.000} 6.000 166.667 + sync_pulse {1.312 4.313} 48.000 20.833 + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- +board_clk 3.000 0.000 0 1 + core_raw 8.550 0.000 0 92342 0.012 0.000 0 92342 18.750 0.000 0 35501 + fb 7.845 0.000 0 3 + ref_raw 1.756 0.000 0 130 0.122 0.000 0 130 0.264 0.000 0 69 + sys_raw 1.500 0.000 0 3 + freq_refclk 0.187 0.000 0 8 + u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk 1.333 0.000 0 16 + iserdes_clkdiv 9.974 0.000 0 33 0.071 0.000 0 33 3.850 0.000 0 9 + u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk 1.333 0.000 0 16 + iserdes_clkdiv_1 9.843 0.000 0 33 0.071 0.000 0 33 3.850 0.000 0 9 + mem_refclk 1.842 0.000 0 1 0.336 0.000 0 1 0.875 0.000 0 8 + oserdes_clk 1.333 0.000 0 12 + oserdes_clkdiv 10.051 0.000 0 44 0.090 0.000 0 44 3.850 0.000 0 12 + oserdes_clk_1 1.333 0.000 0 12 + oserdes_clkdiv_1 10.574 0.000 0 48 0.094 0.000 0 48 3.850 0.000 0 13 + oserdes_clk_2 1.423 0.000 0 4 0.413 0.000 0 4 1.333 0.000 0 12 + oserdes_clkdiv_2 4.245 0.000 0 36 0.092 0.000 0 36 0.850 0.000 0 11 + oserdes_clk_3 1.439 0.000 0 4 0.408 0.000 0 4 1.333 0.000 0 12 + oserdes_clkdiv_3 4.597 0.000 0 36 0.086 0.000 0 36 0.850 0.000 0 11 + pll_clk3_out 3.000 0.000 0 3 + clk_pll_i 2.912 0.000 0 14674 0.027 0.000 0 14674 3.850 0.000 0 5987 + pll_clkfbout 4.751 0.000 0 2 + sync_pulse 1.750 0.000 0 8 + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- +clk_pll_i core_raw 10.665 0.000 0 20 +clk_pll_i ref_raw 16.907 0.000 0 1 +clk_pll_i u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk 10.088 0.000 0 8 45.348 0.000 0 8 +clk_pll_i u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk 8.404 0.000 0 8 46.023 0.000 0 8 +sync_pulse mem_refclk 1.276 0.000 0 1 0.909 0.000 0 1 +oserdes_clk oserdes_clkdiv 2.105 0.000 0 12 0.095 0.000 0 12 +oserdes_clk_1 oserdes_clkdiv_1 2.105 0.000 0 13 0.095 0.000 0 13 +oserdes_clk_2 oserdes_clkdiv_2 2.105 0.000 0 15 0.095 0.000 0 15 +oserdes_clk_3 oserdes_clkdiv_3 2.105 0.000 0 15 0.095 0.000 0 15 +core_raw clk_pll_i 38.557 0.000 0 20 +ref_raw clk_pll_i 16.759 0.000 0 12 0.112 0.000 0 12 + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- +**async_default** clk_pll_i clk_pll_i 8.947 0.000 0 111 0.176 0.000 0 111 +**async_default** core_raw core_raw 20.362 0.000 0 116 0.154 0.000 0 116 +**default** clk_pll_i 1.977 0.000 0 1 + + +------------------------------------------------------------------------------------------------ +| User Ignored Path Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock +---------- ---------- -------- +(none) clk_pll_i +(none) core_raw +(none) clk_pll_i clk_pll_i +(none) core_raw clk_pll_i +(none) mem_refclk clk_pll_i +(none) ref_raw clk_pll_i +(none) core_raw +(none) clk_pll_i core_raw +(none) core_raw core_raw +(none) ref_raw +(none) clk_pll_i ref_raw +(none) ref_raw ref_raw + + +------------------------------------------------------------------------------------------------ +| Unconstrained Path Table +| ------------------------ +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock +---------- ---------- -------- +(none) clk_pll_i +(none) fb +(none) freq_refclk +(none) pll_clkfbout +(none) ref_raw +(none) clk_pll_i + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + +--------------------------------------------------------------------------------------------------- +From Clock: board_clk + To Clock: board_clk + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 3.000ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: board_clk +Waveform(ns): { 0.000 5.000 } +Period(ns): 10.000 +Sources: { CLK100MHZ } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a MMCME2_ADV/CLKIN1 n/a 1.249 10.000 8.751 MMCME2_ADV_X1Y2 clock_mmcm/CLKIN1 +Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 10.000 90.000 MMCME2_ADV_X1Y2 clock_mmcm/CLKIN1 +Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y2 clock_mmcm/CLKIN1 +High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y2 clock_mmcm/CLKIN1 + + + +--------------------------------------------------------------------------------------------------- +From Clock: core_raw + To Clock: core_raw + +Setup : 0 Failing Endpoints, Worst Slack 8.550ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.012ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 18.750ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 8.550ns (required time - arrival time) + Source: platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/regs_1_0_reg[63]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[6]/D + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: core_raw + Path Type: Setup (Max at Slow Process Corner) + Requirement: 40.000ns (core_raw rise@40.000ns - core_raw rise@0.000ns) + Data Path Delay: 31.373ns (logic 7.987ns (25.458%) route 23.386ns (74.542%)) + Logic Levels: 35 (CARRY4=3 LUT2=6 LUT3=4 LUT4=8 LUT5=7 LUT6=7) + Clock Path Skew: -0.015ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.360ns = ( 38.640 - 40.000 ) + Source Clock Delay (SCD): -0.857ns + Clock Pessimism Removal (CPR): 0.488ns + Clock Uncertainty: 0.091ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.683 -0.857 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/clk + SLICE_X74Y126 FDRE r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/regs_1_0_reg[63]/C + ------------------------------------------------------------------- ------------------- + SLICE_X74Y126 FDRE (Prop_fdre_C_Q) 0.478 -0.379 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/regs_1_0_reg[63]/Q + net (fo=2, routed) 1.253 0.874 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/regs_1_0[63] + SLICE_X82Y128 LUT6 (Prop_lut6_I4_O) 0.296 1.170 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/NonBlockingDCac_LUT6_24/O + net (fo=1, routed) 0.513 1.683 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/NonBlockingDCac_net_49 + SLICE_X81Y128 LUT5 (Prop_lut5_I4_O) 0.124 1.807 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/NonBlockingDCac_LUT5_49/O + net (fo=8, routed) 1.224 3.031 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/NonBlockingDCac_net_114 + SLICE_X68Y129 LUT5 (Prop_lut5_I4_O) 0.124 3.155 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/load_wb_data[31]_i_3/O + net (fo=5, routed) 0.910 4.065 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/_dcacheArb_io_requestor_1_resp_bits_data_word_bypass[31] + SLICE_X59Y137 LUT4 (Prop_lut4_I3_O) 0.124 4.189 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/NonBlockingDCac_LUT4_25/O + net (fo=33, routed) 0.999 5.188 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/NonBlockingDCac_net_232 + SLICE_X56Y134 LUT4 (Prop_lut4_I3_O) 0.150 5.338 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/in_pipe_b_in1[47]_i_3/O + net (fo=2, routed) 1.169 6.507 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/_dcacheArb_io_requestor_1_resp_bits_data_word_bypass[47] + SLICE_X48Y156 LUT6 (Prop_lut6_I0_O) 0.348 6.855 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/in_pipe_b_in1[47]_i_2/O + net (fo=1, routed) 1.171 8.026 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/in_pipe_b_in1[47]_i_2_n_0 + SLICE_X44Y161 LUT3 (Prop_lut3_I0_O) 0.124 8.150 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/in_pipe_b_in1[47]_i_1/O + net (fo=7, routed) 1.244 9.394 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/_cores_0_io_fpu_fromint_data[47] + SLICE_X39Y179 LUT4 (Prop_lut4_I3_O) 0.118 9.512 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[49]_i_9/O + net (fo=2, routed) 0.611 10.123 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[49]_i_9_n_0 + SLICE_X39Y178 LUT3 (Prop_lut3_I1_O) 0.320 10.443 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[50]_i_10/O + net (fo=1, routed) 0.569 11.011 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[50]_i_10_n_0 + SLICE_X41Y178 LUT6 (Prop_lut6_I2_O) 0.326 11.337 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[50]_i_7/O + net (fo=11, routed) 0.982 12.319 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[50]_i_7_n_0 + SLICE_X45Y174 LUT4 (Prop_lut4_I3_O) 0.150 12.469 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_217/O + net (fo=3, routed) 0.591 13.060 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_217_n_0 + SLICE_X45Y178 LUT2 (Prop_lut2_I1_O) 0.332 13.392 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_213/O + net (fo=5, routed) 0.590 13.982 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_213_n_0 + SLICE_X43Y178 LUT3 (Prop_lut3_I0_O) 0.124 14.106 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_227/O + net (fo=3, routed) 0.815 14.921 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_227_n_0 + SLICE_X45Y178 LUT2 (Prop_lut2_I0_O) 0.150 15.071 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_223/O + net (fo=3, routed) 0.564 15.635 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_223_n_0 + SLICE_X41Y177 LUT2 (Prop_lut2_I0_O) 0.332 15.967 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_229/O + net (fo=2, routed) 0.277 16.244 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_229_n_0 + SLICE_X41Y177 LUT2 (Prop_lut2_I0_O) 0.124 16.368 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_220/O + net (fo=5, routed) 0.666 17.034 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_220_n_0 + SLICE_X46Y180 LUT3 (Prop_lut3_I0_O) 0.124 17.158 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_262/O + net (fo=3, routed) 0.602 17.759 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_262_n_0 + SLICE_X45Y180 LUT2 (Prop_lut2_I0_O) 0.149 17.908 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_259/O + net (fo=3, routed) 0.668 18.576 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_259_n_0 + SLICE_X45Y180 LUT2 (Prop_lut2_I0_O) 0.332 18.908 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_257/O + net (fo=4, routed) 0.579 19.487 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_257_n_0 + SLICE_X45Y177 LUT5 (Prop_lut5_I3_O) 0.124 19.611 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_264/O + net (fo=4, routed) 0.604 20.215 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_264_n_0 + SLICE_X45Y181 LUT6 (Prop_lut6_I0_O) 0.124 20.339 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_251/O + net (fo=1, routed) 0.626 20.965 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_251_n_0 + SLICE_X44Y181 CARRY4 (Prop_carry4_DI[0]_O[1]) + 0.407 21.372 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[2]_i_185/O[1] + net (fo=1, routed) 0.424 21.797 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/alu/_popc_in_T_1370[62] + SLICE_X42Y181 LUT4 (Prop_lut4_I0_O) 0.303 22.100 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_135/O + net (fo=3, routed) 0.824 22.924 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_135_n_0 + SLICE_X41Y181 LUT4 (Prop_lut4_I0_O) 0.152 23.076 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_100/O + net (fo=2, routed) 0.584 23.660 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_100_n_0 + SLICE_X41Y180 LUT4 (Prop_lut4_I3_O) 0.326 23.986 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_97/O + net (fo=2, routed) 0.583 24.569 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_97_n_0 + SLICE_X40Y179 LUT6 (Prop_lut6_I5_O) 0.124 24.693 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_60/O + net (fo=2, routed) 0.837 25.530 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_60_n_0 + SLICE_X41Y171 LUT5 (Prop_lut5_I4_O) 0.118 25.648 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_56/O + net (fo=2, routed) 0.451 26.099 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_56_n_0 + SLICE_X41Y171 LUT5 (Prop_lut5_I3_O) 0.326 26.425 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_39/O + net (fo=2, routed) 0.507 26.932 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_39_n_0 + SLICE_X40Y171 LUT6 (Prop_lut6_I5_O) 0.124 27.056 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_30/O + net (fo=1, routed) 0.000 27.056 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_30_n_0 + SLICE_X40Y171 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.401 27.457 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[2]_i_13/CO[3] + net (fo=1, routed) 0.000 27.457 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[2]_i_13_n_0 + SLICE_X40Y172 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 27.685 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[4]_i_14/CO[2] + net (fo=2, routed) 0.583 28.268 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/alu/data5[6] + SLICE_X43Y170 LUT4 (Prop_lut4_I3_O) 0.307 28.575 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[6]_i_13/O + net (fo=1, routed) 0.452 29.026 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[6]_i_13_n_0 + SLICE_X46Y170 LUT6 (Prop_lut6_I3_O) 0.326 29.352 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[6]_i_5/O + net (fo=1, routed) 0.423 29.775 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[6]_i_5_n_0 + SLICE_X48Y169 LUT5 (Prop_lut5_I0_O) 0.124 29.899 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[6]_i_2/O + net (fo=1, routed) 0.493 30.392 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[6]_i_2_n_0 + SLICE_X48Y169 LUT5 (Prop_lut5_I0_O) 0.124 30.516 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[6]_i_1/O + net (fo=1, routed) 0.000 30.516 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/_alu_io_out[6] + SLICE_X48Y169 FDRE r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[6]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 40.000 40.000 r + E3 0.000 40.000 r CLK100MHZ (IN) + net (fo=0) 0.000 40.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r input_clock/O + net (fo=1, routed) 1.162 42.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 35.249 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 36.888 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 36.979 r core_buffer/O + net (fo=35517, routed) 1.660 38.640 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/clk + SLICE_X48Y169 FDRE r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[6]/C + clock pessimism 0.488 39.128 + clock uncertainty -0.091 39.037 + SLICE_X48Y169 FDRE (Setup_fdre_C_D) 0.029 39.066 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[6] + ------------------------------------------------------------------- + required time 39.066 + arrival time -30.516 + ------------------------------------------------------------------- + slack 8.550 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.012ns (arrival time - required time) + Source: platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/memStorer/dma_data_reg[56]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/writer/reqReg_data_reg[56]/D + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: core_raw + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (core_raw rise@0.000ns - core_raw rise@0.000ns) + Data Path Delay: 0.285ns (logic 0.128ns (44.914%) route 0.157ns (55.086%)) + Logic Levels: 0 + Clock Path Skew: 0.261ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.847ns + Source Clock Delay (SCD): -0.604ns + Clock Pessimism Removal (CPR): -0.504ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.379 -1.689 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.499 -1.190 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.164 r core_buffer/O + net (fo=35517, routed) 0.560 -0.604 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/memStorer/clk + SLICE_X51Y66 FDRE r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/memStorer/dma_data_reg[56]/C + ------------------------------------------------------------------- ------------------- + SLICE_X51Y66 FDRE (Prop_fdre_C_Q) 0.128 -0.476 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/memStorer/dma_data_reg[56]/Q + net (fo=1, routed) 0.157 -0.319 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/writer/reqReg_data_reg[63]_1[56] + SLICE_X52Y67 FDRE r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/writer/reqReg_data_reg[56]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.163 -2.245 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.544 -1.702 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.673 r core_buffer/O + net (fo=35517, routed) 0.826 -0.847 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/writer/clk + SLICE_X52Y67 FDRE r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/writer/reqReg_data_reg[56]/C + clock pessimism 0.504 -0.343 + SLICE_X52Y67 FDRE (Hold_fdre_C_D) 0.012 -0.331 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/writer/reqReg_data_reg[56] + ------------------------------------------------------------------- + required time 0.331 + arrival time -0.319 + ------------------------------------------------------------------- + slack 0.012 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: core_raw +Waveform(ns): { 0.000 20.000 } +Period(ns): 40.000 +Sources: { clock_mmcm/CLKOUT0 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a DSP48E1/CLK n/a 3.884 40.000 36.116 DSP48_X0Y69 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg/CLK +Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 40.000 173.360 MMCME2_ADV_X1Y2 clock_mmcm/CLKOUT0 +Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X58Y81 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_12_17/RAMA/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X58Y81 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_12_17/RAMA/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: fb + To Clock: fb + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 7.845ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: fb +Waveform(ns): { 0.000 5.000 } +Period(ns): 10.000 +Sources: { clock_mmcm/CLKFBOUT } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFG/I n/a 2.155 10.000 7.845 BUFGCTRL_X0Y19 fb_buffer/I +Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 10.000 90.000 MMCME2_ADV_X1Y2 clock_mmcm/CLKFBIN + + + +--------------------------------------------------------------------------------------------------- +From Clock: ref_raw + To Clock: ref_raw + +Setup : 0 Failing Endpoints, Worst Slack 1.756ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.122ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 0.264ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.756ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r2_reg/C + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.sample_timer_reg[1]/R + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: ref_raw + Path Type: Setup (Max at Slow Process Corner) + Requirement: 5.000ns (ref_raw rise@5.000ns - ref_raw rise@0.000ns) + Data Path Delay: 2.724ns (logic 0.716ns (26.281%) route 2.008ns (73.719%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: -0.024ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.519ns = ( 3.481 - 5.000 ) + Source Clock Delay (SCD): -0.935ns + Clock Pessimism Removal (CPR): 0.560ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.070 -4.355 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.719 -2.636 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r ref_buffer/O + net (fo=67, routed) 1.605 -0.935 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/clk_ref_i + SLICE_X32Y125 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r2_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X32Y125 FDRE (Prop_fdre_C_Q) 0.419 -0.516 r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r2_reg/Q + net (fo=32, routed) 0.876 0.360 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r2 + SLICE_X32Y131 LUT2 (Prop_lut2_I0_O) 0.297 0.657 r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/arty_ddr3mig_7s_LUT2_2/O + net (fo=11, routed) 1.132 1.789 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.sample_timer0__20 + SLICE_X28Y138 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.sample_timer_reg[1]/R + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 5.000 5.000 r + E3 0.000 5.000 r CLK100MHZ (IN) + net (fo=0) 0.000 5.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 6.411 r input_clock/O + net (fo=1, routed) 1.162 7.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.324 0.249 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.639 1.888 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 1.979 r ref_buffer/O + net (fo=67, routed) 1.502 3.481 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/clk_ref_i + SLICE_X28Y138 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.sample_timer_reg[1]/C + clock pessimism 0.560 4.041 + clock uncertainty -0.067 3.974 + SLICE_X28Y138 FDRE (Setup_fdre_C_R) -0.429 3.545 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.sample_timer_reg[1] + ------------------------------------------------------------------- + required time 3.545 + arrival time -1.789 + ------------------------------------------------------------------- + slack 1.756 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.122ns (arrival time - required time) + Source: btn_ref_meta_reg/C + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: btn_ref_sync_reg/D + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: ref_raw + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (ref_raw rise@0.000ns - ref_raw rise@0.000ns) + Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.849ns + Source Clock Delay (SCD): -0.609ns + Clock Pessimism Removal (CPR): -0.240ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -2.379 -1.689 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.499 -1.190 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r ref_buffer/O + net (fo=67, routed) 0.555 -0.609 ref_clk + SLICE_X67Y74 FDRE r btn_ref_meta_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y74 FDRE (Prop_fdre_C_Q) 0.141 -0.468 r btn_ref_meta_reg/Q + net (fo=1, routed) 0.056 -0.412 btn_ref_meta + SLICE_X67Y74 FDRE r btn_ref_sync_reg/D + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -3.163 -2.245 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.544 -1.702 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r ref_buffer/O + net (fo=67, routed) 0.824 -0.849 ref_clk + SLICE_X67Y74 FDRE r btn_ref_sync_reg/C + clock pessimism 0.240 -0.609 + SLICE_X67Y74 FDRE (Hold_fdre_C_D) 0.075 -0.534 btn_ref_sync_reg + ------------------------------------------------------------------- + required time 0.534 + arrival time -0.412 + ------------------------------------------------------------------- + slack 0.122 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: ref_raw +Waveform(ns): { 0.000 2.500 } +Period(ns): 5.000 +Sources: { clock_mmcm/CLKOUT2 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a XADC/DCLK n/a 4.000 5.000 1.000 XADC_X0Y0 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.XADC_inst/DCLK +Max Period n/a IDELAYCTRL/REFCLK n/a 5.264 5.000 0.264 IDELAYCTRL_X1Y1 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/u_idelayctrl_200/REFCLK +Low Pulse Width Slow FDRE/C n/a 0.500 2.500 2.000 SLICE_X67Y74 btn_ref_meta_reg/C +High Pulse Width Slow FDRE/C n/a 0.500 2.500 2.000 SLICE_X67Y74 btn_ref_meta_reg/C + + + +--------------------------------------------------------------------------------------------------- +From Clock: sys_raw + To Clock: sys_raw + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.500ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: sys_raw +Waveform(ns): { 0.000 3.000 } +Period(ns): 6.000 +Sources: { clock_mmcm/CLKOUT1 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFG/I n/a 2.155 6.000 3.845 BUFGCTRL_X0Y17 sys_buffer/I +Max Period n/a PLLE2_ADV/CLKIN1 n/a 52.633 6.000 46.633 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 +Low Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 1.500 3.000 1.500 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 +High Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 1.500 3.000 1.500 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 + + + +--------------------------------------------------------------------------------------------------- +From Clock: freq_refclk + To Clock: freq_refclk + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 0.187ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: freq_refclk +Waveform(ns): { 0.000 0.750 } +Period(ns): 1.500 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a PHASER_OUT_PHY/FREQREFCLK n/a 1.250 1.500 0.250 PHASER_OUT_PHY_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/FREQREFCLK +Max Period n/a PHASER_OUT_PHY/FREQREFCLK n/a 2.500 1.500 1.000 PHASER_OUT_PHY_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/FREQREFCLK +Low Pulse Width Slow PHASER_REF/CLKIN n/a 0.562 0.750 0.188 PHASER_REF_X1Y1 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i/CLKIN +High Pulse Width Slow PHASER_OUT_PHY/FREQREFCLK n/a 0.563 0.750 0.187 PHASER_OUT_PHY_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/FREQREFCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk + To Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a ISERDESE2/CLK n/a 1.667 3.000 1.333 ILOGIC_X1Y76 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: iserdes_clkdiv + To Clock: iserdes_clkdiv + +Setup : 0 Failing Endpoints, Worst Slack 9.974ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.071ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 3.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 9.974ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLKDIVP + (rising edge-triggered cell ISERDESE2 clocked by iserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/D1[3] + (rising edge-triggered cell IN_FIFO clocked by iserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: iserdes_clkdiv + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (iserdes_clkdiv rise@12.000ns - iserdes_clkdiv rise@0.000ns) + Data Path Delay: 0.954ns (logic 0.425ns (44.547%) route 0.529ns (55.453%)) + Logic Levels: 0 + Clock Path Skew: -0.450ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.970ns = ( 12.970 - 12.000 ) + Source Clock Delay (SCD): 2.107ns + Clock Pessimism Removal (CPR): 0.686ns + Clock Uncertainty: 0.051ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.073ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock iserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.607 -0.179 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.662 1.484 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.173 1.657 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, routed) 0.450 2.107 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/iserdes_clkdiv + ILOGIC_X1Y76 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLKDIVP + ------------------------------------------------------------------- ------------------- + ILOGIC_X1Y76 ISERDESE2 (Prop_iserdese2_CLKDIVP_Q1) + 0.425 2.532 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/Q1 + net (fo=1, routed) 0.529 3.061 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/if_d1[3] + IN_FIFO_X1Y6 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/D1[3] + ------------------------------------------------------------------- ------------------- + + (clock iserdes_clkdiv rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.576 11.183 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.624 12.807 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.163 12.970 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, routed) 0.000 12.970 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clkdiv + IN_FIFO_X1Y6 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK + clock pessimism 0.686 13.657 + clock uncertainty -0.051 13.606 + IN_FIFO_X1Y6 IN_FIFO (Setup_in_fifo_WRCLK_D1[3]) + -0.571 13.035 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo + ------------------------------------------------------------------- + required time 13.035 + arrival time -3.061 + ------------------------------------------------------------------- + slack 9.974 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.071ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV + (rising edge-triggered cell PHASER_IN_PHY clocked by iserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WREN + (rising edge-triggered cell IN_FIFO clocked by iserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: iserdes_clkdiv + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (iserdes_clkdiv rise@0.000ns - iserdes_clkdiv rise@0.000ns) + Data Path Delay: 0.058ns (logic 0.058ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.908ns + Source Clock Delay (SCD): 1.095ns + Clock Pessimism Removal (CPR): -0.187ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock iserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.197 -0.351 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.357 1.005 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.090 1.095 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV + ------------------------------------------------------------------- ------------------- + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_ICLKDIV_WRENABLE) + 0.058 1.153 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/WRENABLE + net (fo=1, routed) 0.000 1.153 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ififo_wr_enable + IN_FIFO_X1Y6 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WREN + ------------------------------------------------------------------- ------------------- + + (clock iserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.217 -0.568 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.381 0.812 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.096 0.908 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, routed) 0.000 0.908 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clkdiv + IN_FIFO_X1Y6 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK + clock pessimism 0.187 1.095 + IN_FIFO_X1Y6 IN_FIFO (Hold_in_fifo_WRCLK_WREN) + -0.013 1.082 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo + ------------------------------------------------------------------- + required time -1.082 + arrival time 1.153 + ------------------------------------------------------------------- + slack 0.071 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: iserdes_clkdiv +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a IN_FIFO/WRCLK n/a 5.000 12.000 7.000 IN_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK +Low Pulse Width Slow IN_FIFO/WRCLK n/a 2.150 6.000 3.850 IN_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK +High Pulse Width Slow IN_FIFO/WRCLK n/a 2.150 6.000 3.850 IN_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk + To Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a ISERDESE2/CLK n/a 1.667 3.000 1.333 ILOGIC_X1Y88 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: iserdes_clkdiv_1 + To Clock: iserdes_clkdiv_1 + +Setup : 0 Failing Endpoints, Worst Slack 9.843ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.071ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 3.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 9.843ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq/CLKDIVP + (rising edge-triggered cell ISERDESE2 clocked by iserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/D2[0] + (rising edge-triggered cell IN_FIFO clocked by iserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: iserdes_clkdiv_1 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (iserdes_clkdiv_1 rise@12.000ns - iserdes_clkdiv_1 rise@0.000ns) + Data Path Delay: 1.117ns (logic 0.425ns (38.045%) route 0.692ns (61.955%)) + Logic Levels: 0 + Clock Path Skew: -0.465ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.960ns = ( 12.960 - 12.000 ) + Source Clock Delay (SCD): 2.112ns + Clock Pessimism Removal (CPR): 0.686ns + Clock Uncertainty: 0.051ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.073ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock iserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.597 -0.189 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.662 1.474 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.173 1.647 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, routed) 0.465 2.112 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/iserdes_clkdiv + ILOGIC_X1Y89 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq/CLKDIVP + ------------------------------------------------------------------- ------------------- + ILOGIC_X1Y89 ISERDESE2 (Prop_iserdese2_CLKDIVP_Q4) + 0.425 2.537 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq/Q4 + net (fo=1, routed) 0.692 3.229 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/if_d2[0] + IN_FIFO_X1Y7 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/D2[0] + ------------------------------------------------------------------- ------------------- + + (clock iserdes_clkdiv_1 rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.566 11.173 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.624 12.797 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.163 12.960 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, routed) 0.000 12.960 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clkdiv + IN_FIFO_X1Y7 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK + clock pessimism 0.686 13.647 + clock uncertainty -0.051 13.596 + IN_FIFO_X1Y7 IN_FIFO (Setup_in_fifo_WRCLK_D2[0]) + -0.524 13.072 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo + ------------------------------------------------------------------- + required time 13.072 + arrival time -3.229 + ------------------------------------------------------------------- + slack 9.843 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.071ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV + (rising edge-triggered cell PHASER_IN_PHY clocked by iserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WREN + (rising edge-triggered cell IN_FIFO clocked by iserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: iserdes_clkdiv_1 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (iserdes_clkdiv_1 rise@0.000ns - iserdes_clkdiv_1 rise@0.000ns) + Data Path Delay: 0.058ns (logic 0.058ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.902ns + Source Clock Delay (SCD): 1.089ns + Clock Pessimism Removal (CPR): -0.187ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock iserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.191 -0.357 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.357 0.999 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.090 1.089 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV + ------------------------------------------------------------------- ------------------- + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_ICLKDIV_WRENABLE) + 0.058 1.147 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/WRENABLE + net (fo=1, routed) 0.000 1.147 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ififo_wr_enable + IN_FIFO_X1Y7 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WREN + ------------------------------------------------------------------- ------------------- + + (clock iserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.211 -0.574 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.381 0.806 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.096 0.902 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, routed) 0.000 0.902 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clkdiv + IN_FIFO_X1Y7 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK + clock pessimism 0.187 1.089 + IN_FIFO_X1Y7 IN_FIFO (Hold_in_fifo_WRCLK_WREN) + -0.013 1.076 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo + ------------------------------------------------------------------- + required time -1.076 + arrival time 1.147 + ------------------------------------------------------------------- + slack 0.071 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: iserdes_clkdiv_1 +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a IN_FIFO/WRCLK n/a 5.000 12.000 7.000 IN_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK +Low Pulse Width Slow IN_FIFO/WRCLK n/a 2.150 6.000 3.850 IN_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK +High Pulse Width Slow IN_FIFO/WRCLK n/a 2.150 6.000 3.850 IN_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: mem_refclk + To Clock: mem_refclk + +Setup : 0 Failing Endpoints, Worst Slack 1.842ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.336ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 0.875ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.842ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLMSTREMPTY + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: mem_refclk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (mem_refclk rise@3.000ns - mem_refclk rise@0.000ns) + Data Path Delay: 1.093ns (logic 0.622ns (56.908%) route 0.471ns (43.092%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.804ns = ( 2.196 - 3.000 ) + Source Clock Delay (SCD): -0.165ns + Clock Pessimism Removal (CPR): 0.639ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.621 -0.165 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + ------------------------------------------------------------------- ------------------- + PHY_CONTROL_X1Y1 PHY_CONTROL (Prop_phy_control_MEMREFCLK_PHYCTLEMPTY) + 0.622 0.457 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLEMPTY + net (fo=1, routed) 0.471 0.928 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i_n_1 + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLMSTREMPTY + ------------------------------------------------------------------- ------------------- + + (clock mem_refclk rise edge) + 3.000 3.000 r + E3 0.000 3.000 r CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 4.411 r input_clock/O + net (fo=1, routed) 1.162 5.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -1.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -0.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -0.021 r sys_buffer/O + net (fo=1, routed) 1.544 1.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 1.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.589 2.196 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + clock pessimism 0.639 2.835 + clock uncertainty -0.054 2.781 + PHY_CONTROL_X1Y1 PHY_CONTROL (Setup_phy_control_MEMREFCLK_PHYCTLMSTREMPTY) + -0.011 2.770 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i + ------------------------------------------------------------------- + required time 2.770 + arrival time -0.928 + ------------------------------------------------------------------- + slack 1.842 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.336ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLMSTREMPTY + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: mem_refclk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mem_refclk rise@0.000ns - mem_refclk rise@0.000ns) + Data Path Delay: 0.459ns (logic 0.313ns (68.192%) route 0.146ns (31.808%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.570ns + Source Clock Delay (SCD): -0.353ns + Clock Pessimism Removal (CPR): -0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.195 -0.353 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + ------------------------------------------------------------------- ------------------- + PHY_CONTROL_X1Y1 PHY_CONTROL (Prop_phy_control_MEMREFCLK_PHYCTLEMPTY) + 0.313 -0.040 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLEMPTY + net (fo=1, routed) 0.146 0.106 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i_n_1 + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLMSTREMPTY + ------------------------------------------------------------------- ------------------- + + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.215 -0.570 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + clock pessimism 0.217 -0.353 + PHY_CONTROL_X1Y1 PHY_CONTROL (Hold_phy_control_MEMREFCLK_PHYCTLMSTREMPTY) + 0.123 -0.230 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i + ------------------------------------------------------------------- + required time 0.230 + arrival time 0.106 + ------------------------------------------------------------------- + slack 0.336 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: mem_refclk +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a PHY_CONTROL/MEMREFCLK n/a 1.475 3.000 1.525 PHY_CONTROL_X1Y1 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK +Max Period n/a PLLE2_ADV/CLKOUT1 n/a 160.000 3.000 157.000 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 +Low Pulse Width Slow PHY_CONTROL/MEMREFCLK n/a 0.625 1.500 0.875 PHY_CONTROL_X1Y1 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK +High Pulse Width Slow PHY_CONTROL/MEMREFCLK n/a 0.625 1.500 0.875 PHY_CONTROL_X1Y1 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk + To Clock: oserdes_clk + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clk +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OSERDESE2/CLK n/a 1.667 3.000 1.333 OLOGIC_X1Y51 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[0].oserdes_dq_.sdr.oserdes_dq_i/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clkdiv + To Clock: oserdes_clkdiv + +Setup : 0 Failing Endpoints, Worst Slack 10.051ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.090ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 3.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 10.051ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[11].oserdes_dq_.sdr.oserdes_dq_i/D4 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (oserdes_clkdiv rise@12.000ns - oserdes_clkdiv rise@0.000ns) + Data Path Delay: 1.681ns (logic 0.674ns (40.087%) route 1.007ns (59.913%)) + Logic Levels: 0 + Clock Path Skew: 0.412ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.119ns = ( 14.119 - 12.000 ) + Source Clock Delay (SCD): 2.419ns + Clock Pessimism Removal (CPR): 0.712ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.614 -0.172 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 2.262 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.157 2.419 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, routed) 0.000 2.419 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/oserdes_clkdiv + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y4 OUT_FIFO (Prop_out_fifo_RDCLK_Q6[7]) + 0.674 3.093 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/Q6[7] + net (fo=1, routed) 1.007 4.101 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/oserdes_dq[43] + OLOGIC_X1Y50 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[11].oserdes_dq_.sdr.oserdes_dq_i/D4 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.582 11.189 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 13.559 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 13.707 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, routed) 0.412 14.119 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y50 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[11].oserdes_dq_.sdr.oserdes_dq_i/CLKDIV + clock pessimism 0.712 14.831 + clock uncertainty -0.054 14.777 + OLOGIC_X1Y50 OSERDESE2 (Setup_oserdese2_CLKDIV_D4) + -0.625 14.152 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[11].oserdes_dq_.sdr.oserdes_dq_i + ------------------------------------------------------------------- + required time 14.152 + arrival time -4.101 + ------------------------------------------------------------------- + slack 10.051 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.090ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/D2 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv rise@0.000ns - oserdes_clkdiv rise@0.000ns) + Data Path Delay: 0.288ns (logic 0.138ns (47.866%) route 0.150ns (52.134%)) + Logic Levels: 0 + Clock Path Skew: 0.179ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.840ns + Source Clock Delay (SCD): 1.824ns + Clock Pessimism Removal (CPR): -0.163ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.197 -0.351 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.741 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.083 1.824 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, routed) 0.000 1.824 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/oserdes_clkdiv + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y4 OUT_FIFO (Prop_out_fifo_RDCLK_Q2[1]) + 0.138 1.962 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/Q2[1] + net (fo=1, routed) 0.150 2.112 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/oserdes_dq[9] + OLOGIC_X1Y53 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/D2 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.218 -0.567 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.573 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.661 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, routed) 0.179 1.840 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y53 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/CLKDIV + clock pessimism 0.163 2.003 + OLOGIC_X1Y53 OSERDESE2 (Hold_oserdese2_CLKDIV_D2) + 0.019 2.022 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i + ------------------------------------------------------------------- + required time -2.022 + arrival time 2.112 + ------------------------------------------------------------------- + slack 0.090 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clkdiv +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OUT_FIFO/RDCLK n/a 5.000 12.000 7.000 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK +Low Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK +High Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_1 + To Clock: oserdes_clk_1 + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clk_1 +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OSERDESE2/CLK n/a 1.667 3.000 1.333 OLOGIC_X1Y63 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[0].oserdes_dq_.sdr.oserdes_dq_i/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clkdiv_1 + To Clock: oserdes_clkdiv_1 + +Setup : 0 Failing Endpoints, Worst Slack 10.574ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.094ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 3.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 10.574ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[10].oserdes_dq_.sdr.oserdes_dq_i/D1 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv_1 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (oserdes_clkdiv_1 rise@12.000ns - oserdes_clkdiv_1 rise@0.000ns) + Data Path Delay: 1.142ns (logic 0.674ns (59.004%) route 0.468ns (40.996%)) + Logic Levels: 0 + Clock Path Skew: 0.396ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.093ns = ( 14.093 - 12.000 ) + Source Clock Delay (SCD): 2.408ns + Clock Pessimism Removal (CPR): 0.711ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.603 -0.183 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 2.251 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.157 2.408 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, routed) 0.000 2.408 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/oserdes_clkdiv + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y5 OUT_FIFO (Prop_out_fifo_RDCLK_Q5[4]) + 0.674 3.082 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/Q5[4] + net (fo=1, routed) 0.468 3.551 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/oserdes_dq[40] + OLOGIC_X1Y69 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[10].oserdes_dq_.sdr.oserdes_dq_i/D1 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_1 rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.572 11.179 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 13.549 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 13.697 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, routed) 0.396 14.093 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y69 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[10].oserdes_dq_.sdr.oserdes_dq_i/CLKDIV + clock pessimism 0.711 14.804 + clock uncertainty -0.054 14.750 + OLOGIC_X1Y69 OSERDESE2 (Setup_oserdese2_CLKDIV_D1) + -0.625 14.125 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[10].oserdes_dq_.sdr.oserdes_dq_i + ------------------------------------------------------------------- + required time 14.125 + arrival time -3.551 + ------------------------------------------------------------------- + slack 10.574 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.094ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/D2 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv_1 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_1 rise@0.000ns - oserdes_clkdiv_1 rise@0.000ns) + Data Path Delay: 0.288ns (logic 0.138ns (47.866%) route 0.150ns (52.134%)) + Logic Levels: 0 + Clock Path Skew: 0.175ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.827ns + Source Clock Delay (SCD): 1.817ns + Clock Pessimism Removal (CPR): -0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.190 -0.358 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.734 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.083 1.817 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, routed) 0.000 1.817 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/oserdes_clkdiv + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y5 OUT_FIFO (Prop_out_fifo_RDCLK_Q2[1]) + 0.138 1.955 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/Q2[1] + net (fo=1, routed) 0.150 2.105 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/oserdes_dq[9] + OLOGIC_X1Y65 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/D2 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.209 -0.576 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.564 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.652 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, routed) 0.175 1.827 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y65 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/CLKDIV + clock pessimism 0.165 1.992 + OLOGIC_X1Y65 OSERDESE2 (Hold_oserdese2_CLKDIV_D2) + 0.019 2.011 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i + ------------------------------------------------------------------- + required time -2.011 + arrival time 2.105 + ------------------------------------------------------------------- + slack 0.094 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clkdiv_1 +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OUT_FIFO/RDCLK n/a 5.000 12.000 7.000 OUT_FIFO_X1Y5 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK +Low Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y5 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK +High Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y5 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_2 + To Clock: oserdes_clk_2 + +Setup : 0 Failing Endpoints, Worst Slack 1.423ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.413ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.423ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqsts/D1 + (rising edge-triggered cell ODDR clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: oserdes_clk_2 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clk_2 rise@3.000ns - oserdes_clk_2 rise@0.000ns) + Data Path Delay: 1.037ns (logic 0.562ns (54.177%) route 0.475ns (45.823%)) + Logic Levels: 0 + Clock Path Skew: 0.400ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.698ns = ( 5.698 - 3.000 ) + Source Clock Delay (SCD): 3.046ns + Clock Pessimism Removal (CPR): 0.748ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.614 -0.172 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 2.262 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.784 3.046 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLKDELAYED_CTSBUS[0]) + 0.562 3.608 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/CTSBUS[0] + net (fo=2, routed) 0.475 4.084 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/CTSBUS[0] + OLOGIC_X1Y82 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqsts/D1 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clk_2 rise edge) + 3.000 3.000 r + E3 0.000 3.000 r CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 4.411 r input_clock/O + net (fo=1, routed) 1.162 5.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -1.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -0.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -0.021 r sys_buffer/O + net (fo=1, routed) 1.544 1.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 1.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.582 2.189 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 4.559 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.739 5.298 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + net (fo=2, routed) 0.400 5.698 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/oserdes_clk_delayed + OLOGIC_X1Y82 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqsts/C + clock pessimism 0.748 6.446 + clock uncertainty -0.054 6.392 + OLOGIC_X1Y82 ODDR (Setup_oddr_C_D1) -0.885 5.507 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqsts + ------------------------------------------------------------------- + required time 5.507 + arrival time -4.084 + ------------------------------------------------------------------- + slack 1.423 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.413ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqs/D2 + (rising edge-triggered cell ODDR clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: oserdes_clk_2 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clk_2 rise@0.000ns - oserdes_clk_2 rise@0.000ns) + Data Path Delay: 0.496ns (logic 0.346ns (69.715%) route 0.150ns (30.285%)) + Logic Levels: 0 + Clock Path Skew: 0.176ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 2.419ns + Source Clock Delay (SCD): 2.371ns + Clock Pessimism Removal (CPR): -0.128ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.197 -0.351 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.741 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.630 2.371 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLKDELAYED_DQSBUS[1]) + 0.346 2.717 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/DQSBUS[1] + net (fo=1, routed) 0.150 2.868 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/DQSBUS[1] + OLOGIC_X1Y82 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqs/D2 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clk_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.218 -0.567 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.573 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.670 2.243 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + net (fo=2, routed) 0.176 2.419 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/oserdes_clk_delayed + OLOGIC_X1Y82 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqs/C + clock pessimism 0.128 2.547 + OLOGIC_X1Y82 ODDR (Hold_oddr_C_D2) -0.093 2.454 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqs + ------------------------------------------------------------------- + required time -2.454 + arrival time 2.868 + ------------------------------------------------------------------- + slack 0.413 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clk_2 +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OSERDESE2/CLK n/a 1.667 3.000 1.333 OLOGIC_X1Y76 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[1].oserdes_dq_.ddr.oserdes_dq_i/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clkdiv_2 + To Clock: oserdes_clkdiv_2 + +Setup : 0 Failing Endpoints, Worst Slack 4.245ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.092ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 0.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 4.245ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D2 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_2 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 6.000ns (oserdes_clkdiv_2 rise@6.000ns - oserdes_clkdiv_2 rise@0.000ns) + Data Path Delay: 1.483ns (logic 0.674ns (45.456%) route 0.809ns (54.544%)) + Logic Levels: 0 + Clock Path Skew: 0.407ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.114ns = ( 8.114 - 6.000 ) + Source Clock Delay (SCD): 2.419ns + Clock Pessimism Removal (CPR): 0.712ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.614 -0.172 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 2.262 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.157 2.419 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, routed) 0.000 2.419 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/oserdes_clkdiv + OUT_FIFO_X1Y6 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y6 OUT_FIFO (Prop_out_fifo_RDCLK_Q2[1]) + 0.674 3.093 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/Q2[1] + net (fo=1, routed) 0.809 3.902 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/of_dqbus[5] + OLOGIC_X1Y77 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D2 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_2 rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, routed) 1.162 8.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 1.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 2.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 2.979 r sys_buffer/O + net (fo=1, routed) 1.544 4.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 4.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.582 5.189 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 7.559 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 7.707 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, routed) 0.407 8.114 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y77 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV + clock pessimism 0.712 8.826 + clock uncertainty -0.054 8.772 + OLOGIC_X1Y77 OSERDESE2 (Setup_oserdese2_CLKDIV_D2) + -0.625 8.147 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i + ------------------------------------------------------------------- + required time 8.147 + arrival time -3.902 + ------------------------------------------------------------------- + slack 4.245 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.092ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D3 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_2 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_2 rise@0.000ns - oserdes_clkdiv_2 rise@0.000ns) + Data Path Delay: 0.288ns (logic 0.138ns (47.866%) route 0.150ns (52.134%)) + Logic Levels: 0 + Clock Path Skew: 0.177ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.838ns + Source Clock Delay (SCD): 1.824ns + Clock Pessimism Removal (CPR): -0.163ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.197 -0.351 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.741 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.083 1.824 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, routed) 0.000 1.824 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/oserdes_clkdiv + OUT_FIFO_X1Y6 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y6 OUT_FIFO (Prop_out_fifo_RDCLK_Q2[2]) + 0.138 1.962 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/Q2[2] + net (fo=1, routed) 0.150 2.112 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/of_dqbus[6] + OLOGIC_X1Y77 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D3 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.218 -0.567 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.573 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.661 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, routed) 0.177 1.838 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y77 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV + clock pessimism 0.163 2.001 + OLOGIC_X1Y77 OSERDESE2 (Hold_oserdese2_CLKDIV_D3) + 0.019 2.020 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i + ------------------------------------------------------------------- + required time -2.020 + arrival time 2.112 + ------------------------------------------------------------------- + slack 0.092 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clkdiv_2 +Waveform(ns): { 0.000 3.000 } +Period(ns): 6.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OUT_FIFO/RDCLK n/a 5.000 6.000 1.000 OUT_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK +Low Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 3.000 0.850 OUT_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK +High Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 3.000 0.850 OUT_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_3 + To Clock: oserdes_clk_3 + +Setup : 0 Failing Endpoints, Worst Slack 1.439ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.408ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.439ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqsts/D1 + (rising edge-triggered cell ODDR clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: oserdes_clk_3 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clk_3 rise@3.000ns - oserdes_clk_3 rise@0.000ns) + Data Path Delay: 1.037ns (logic 0.562ns (54.177%) route 0.475ns (45.823%)) + Logic Levels: 0 + Clock Path Skew: 0.416ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.704ns = ( 5.704 - 3.000 ) + Source Clock Delay (SCD): 3.035ns + Clock Pessimism Removal (CPR): 0.747ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.603 -0.183 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 2.251 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.784 3.035 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLKDELAYED_CTSBUS[0]) + 0.562 3.597 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/CTSBUS[0] + net (fo=2, routed) 0.475 4.073 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/CTSBUS[0] + OLOGIC_X1Y94 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqsts/D1 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clk_3 rise edge) + 3.000 3.000 r + E3 0.000 3.000 r CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 4.411 r input_clock/O + net (fo=1, routed) 1.162 5.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -1.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -0.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -0.021 r sys_buffer/O + net (fo=1, routed) 1.544 1.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 1.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.572 2.179 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 4.549 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.739 5.288 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + net (fo=2, routed) 0.416 5.704 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/oserdes_clk_delayed + OLOGIC_X1Y94 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqsts/C + clock pessimism 0.747 6.451 + clock uncertainty -0.054 6.397 + OLOGIC_X1Y94 ODDR (Setup_oddr_C_D1) -0.885 5.512 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqsts + ------------------------------------------------------------------- + required time 5.512 + arrival time -4.073 + ------------------------------------------------------------------- + slack 1.439 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.408ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqs/D2 + (rising edge-triggered cell ODDR clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: oserdes_clk_3 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clk_3 rise@0.000ns - oserdes_clk_3 rise@0.000ns) + Data Path Delay: 0.496ns (logic 0.346ns (69.715%) route 0.150ns (30.285%)) + Logic Levels: 0 + Clock Path Skew: 0.181ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 2.415ns + Source Clock Delay (SCD): 2.364ns + Clock Pessimism Removal (CPR): -0.130ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.190 -0.358 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.734 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.630 2.364 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLKDELAYED_DQSBUS[1]) + 0.346 2.710 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/DQSBUS[1] + net (fo=1, routed) 0.150 2.861 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/DQSBUS[1] + OLOGIC_X1Y94 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqs/D2 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clk_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.209 -0.576 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.564 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.670 2.234 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + net (fo=2, routed) 0.181 2.415 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/oserdes_clk_delayed + OLOGIC_X1Y94 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqs/C + clock pessimism 0.130 2.545 + OLOGIC_X1Y94 ODDR (Hold_oddr_C_D2) -0.093 2.452 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqs + ------------------------------------------------------------------- + required time -2.452 + arrival time 2.861 + ------------------------------------------------------------------- + slack 0.408 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clk_3 +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OSERDESE2/CLK n/a 1.667 3.000 1.333 OLOGIC_X1Y88 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[1].oserdes_dq_.ddr.oserdes_dq_i/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clkdiv_3 + To Clock: oserdes_clkdiv_3 + +Setup : 0 Failing Endpoints, Worst Slack 4.597ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.086ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 0.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 4.597ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/D1 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_3 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 6.000ns (oserdes_clkdiv_3 rise@6.000ns - oserdes_clkdiv_3 rise@0.000ns) + Data Path Delay: 1.142ns (logic 0.674ns (59.004%) route 0.468ns (40.996%)) + Logic Levels: 0 + Clock Path Skew: 0.419ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.116ns = ( 8.116 - 6.000 ) + Source Clock Delay (SCD): 2.408ns + Clock Pessimism Removal (CPR): 0.711ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.603 -0.183 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 2.251 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.157 2.408 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, routed) 0.000 2.408 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/oserdes_clkdiv + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y7 OUT_FIFO (Prop_out_fifo_RDCLK_Q6[0]) + 0.674 3.082 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/Q6[0] + net (fo=1, routed) 0.468 3.551 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/of_dqbus[20] + OLOGIC_X1Y95 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/D1 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_3 rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, routed) 1.162 8.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 1.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 2.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 2.979 r sys_buffer/O + net (fo=1, routed) 1.544 4.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 4.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.572 5.179 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 7.549 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 7.697 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, routed) 0.419 8.116 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y95 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV + clock pessimism 0.711 8.827 + clock uncertainty -0.054 8.773 + OLOGIC_X1Y95 OSERDESE2 (Setup_oserdese2_CLKDIV_D1) + -0.625 8.148 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i + ------------------------------------------------------------------- + required time 8.148 + arrival time -3.551 + ------------------------------------------------------------------- + slack 4.597 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.086ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D2 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_3 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_3 rise@0.000ns - oserdes_clkdiv_3 rise@0.000ns) + Data Path Delay: 0.288ns (logic 0.138ns (47.866%) route 0.150ns (52.134%)) + Logic Levels: 0 + Clock Path Skew: 0.183ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.835ns + Source Clock Delay (SCD): 1.817ns + Clock Pessimism Removal (CPR): -0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.190 -0.358 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.734 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.083 1.817 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, routed) 0.000 1.817 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/oserdes_clkdiv + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y7 OUT_FIFO (Prop_out_fifo_RDCLK_Q2[1]) + 0.138 1.955 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/Q2[1] + net (fo=1, routed) 0.150 2.105 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/of_dqbus[5] + OLOGIC_X1Y89 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D2 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.209 -0.576 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.564 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.652 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, routed) 0.183 1.835 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y89 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV + clock pessimism 0.165 2.000 + OLOGIC_X1Y89 OSERDESE2 (Hold_oserdese2_CLKDIV_D2) + 0.019 2.019 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i + ------------------------------------------------------------------- + required time -2.019 + arrival time 2.105 + ------------------------------------------------------------------- + slack 0.086 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clkdiv_3 +Waveform(ns): { 0.000 3.000 } +Period(ns): 6.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OUT_FIFO/RDCLK n/a 5.000 6.000 1.000 OUT_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK +Low Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 3.000 0.850 OUT_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK +High Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 3.000 0.850 OUT_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: pll_clk3_out + To Clock: pll_clk3_out + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 3.000ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: pll_clk3_out +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFH/I n/a 2.155 12.000 9.845 BUFHCE_X1Y12 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/I +Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 12.000 88.000 MMCME2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKIN1 +Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 3.000 6.000 3.000 MMCME2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKIN1 +High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 3.000 6.000 3.000 MMCME2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKIN1 + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_pll_i + To Clock: clk_pll_i + +Setup : 0 Failing Endpoints, Worst Slack 2.912ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.027ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 3.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 2.912ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_w_channel_0/wready_reg/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[18]/CE + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: clk_pll_i + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (clk_pll_i rise@12.000ns - clk_pll_i rise@0.000ns) + Data Path Delay: 8.395ns (logic 0.743ns (8.850%) route 7.652ns (91.150%)) + Logic Levels: 1 (LUT4=1) + Clock Path Skew: -0.213ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.672ns = ( 12.672 - 12.000 ) + Source Clock Delay (SCD): 1.534ns + Clock Pessimism Removal (CPR): 0.649ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.712 1.534 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_w_channel_0/wready_reg_rep__0_0 + SLICE_X77Y88 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_w_channel_0/wready_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X77Y88 FDRE (Prop_fdre_C_Q) 0.419 1.953 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_w_channel_0/wready_reg/Q + net (fo=145, routed) 4.268 6.221 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/m_axi_wready + SLICE_X89Y110 LUT4 (Prop_lut4_I3_O) 0.324 6.545 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/goreg_dm.dout_i[144]_i_1/O + net (fo=144, routed) 3.384 9.929 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[144]_1[0] + SLICE_X71Y100 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[18]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 11.812 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 11.893 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 12.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 9.442 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 11.081 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 11.172 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.500 12.672 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/m_aclk + SLICE_X71Y100 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[18]/C + clock pessimism 0.649 13.322 + clock uncertainty -0.067 13.255 + SLICE_X71Y100 FDRE (Setup_fdre_C_CE) -0.413 12.842 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[18] + ------------------------------------------------------------------- + required time 12.842 + arrival time -9.929 + ------------------------------------------------------------------- + slack 2.912 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.027ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/smallest_reg[0][4]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/gen_final_tap[0].final_val_reg[0][4]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: clk_pll_i + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_pll_i rise@0.000ns - clk_pll_i rise@0.000ns) + Data Path Delay: 0.302ns (logic 0.128ns (42.423%) route 0.174ns (57.577%)) + Logic Levels: 0 + Clock Path Skew: 0.266ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.192ns + Source Clock Delay (SCD): 0.136ns + Clock Pessimism Removal (CPR): -0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 -0.154 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 -0.134 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 -0.949 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 -0.450 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.424 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.560 0.136 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/dqs_count_r_reg[0]_rep_0 + SLICE_X53Y60 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/smallest_reg[0][4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X53Y60 FDRE (Prop_fdre_C_Q) 0.128 0.264 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/smallest_reg[0][4]/Q + net (fo=2, routed) 0.174 0.437 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/smallest_reg[0]_4[4] + SLICE_X50Y61 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/gen_final_tap[0].final_val_reg[0][4]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.437 -0.348 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.043 -0.305 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.494 0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.400 -1.211 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.544 -0.668 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -0.639 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.831 0.192 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/dqs_count_r_reg[0]_rep_0 + SLICE_X50Y61 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/gen_final_tap[0].final_val_reg[0][4]/C + clock pessimism 0.210 0.402 + SLICE_X50Y61 FDRE (Hold_fdre_C_D) 0.009 0.411 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/gen_final_tap[0].final_val_reg[0][4] + ------------------------------------------------------------------- + required time -0.411 + arrival time 0.437 + ------------------------------------------------------------------- + slack 0.027 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: clk_pll_i +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OUT_FIFO/WRCLK n/a 5.000 12.000 7.000 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/WRCLK +Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 12.000 88.000 MMCME2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBIN +Low Pulse Width Slow OUT_FIFO/WRCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/WRCLK +High Pulse Width Slow OUT_FIFO/WRCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/WRCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: pll_clkfbout + To Clock: pll_clkfbout + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 4.751ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: pll_clkfbout +Waveform(ns): { 0.000 3.000 } +Period(ns): 6.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a PLLE2_ADV/CLKFBOUT n/a 1.249 6.000 4.751 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT +Max Period n/a PLLE2_ADV/CLKFBIN n/a 52.633 6.000 46.633 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBIN + + + +--------------------------------------------------------------------------------------------------- +From Clock: sync_pulse + To Clock: sync_pulse + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.750ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: sync_pulse +Waveform(ns): { 1.312 4.312 } +Period(ns): 48.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a PLLE2_ADV/CLKOUT2 n/a 1.249 48.000 46.751 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 +Max Period n/a PLLE2_ADV/CLKOUT2 n/a 160.000 48.000 112.000 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 +High Pulse Width Slow PHASER_OUT_PHY/SYNCIN n/a 1.250 3.000 1.750 PHASER_OUT_PHY_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/SYNCIN + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_pll_i + To Clock: core_raw + +Setup : 0 Failing Endpoints, Worst Slack 10.665ns, Total Violation 0.000ns +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 10.665ns (required time - arrival time) + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: core_raw + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (MaxDelay Path 12.000ns) + Data Path Delay: 1.065ns (logic 0.419ns (39.345%) route 0.646ns (60.655%)) + Logic Levels: 0 + Timing Exception: MaxDelay Path 12.000ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + SLICE_X59Y78 0.000 0.000 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + SLICE_X59Y78 FDRE (Prop_fdre_C_Q) 0.419 0.419 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.646 1.065 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[1] + SLICE_X59Y79 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + max delay 12.000 12.000 + SLICE_X59Y79 FDRE (Setup_fdre_C_D) -0.270 11.730 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + ------------------------------------------------------------------- + required time 11.730 + arrival time -1.065 + ------------------------------------------------------------------- + slack 10.665 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_pll_i + To Clock: ref_raw + +Setup : 0 Failing Endpoints, Worst Slack 16.907ns, Total Violation 0.000ns +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 16.907ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg/D + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: ref_raw + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (MaxDelay Path 20.000ns) + Data Path Delay: 3.012ns (logic 0.456ns (15.138%) route 2.556ns (84.862%)) + Logic Levels: 0 + Timing Exception: MaxDelay Path 20.000ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + SLICE_X69Y117 0.000 0.000 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + SLICE_X69Y117 FDPE (Prop_fdpe_C_Q) 0.456 0.456 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/Q + net (fo=50, routed) 2.556 3.012 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg_0 + SLICE_X32Y125 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg/D + ------------------------------------------------------------------- ------------------- + + max delay 20.000 20.000 + SLICE_X32Y125 FDRE (Setup_fdre_C_D) -0.081 19.919 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg + ------------------------------------------------------------------- + required time 19.919 + arrival time -3.012 + ------------------------------------------------------------------- + slack 16.907 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_pll_i + To Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk + +Setup : 0 Failing Endpoints, Worst Slack 10.088ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 45.348ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 10.088ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq/DDLY + (falling edge-triggered cell ISERDESE2 clocked by u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 16.500ns (u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk fall@16.500ns - clk_pll_i rise@0.000ns) + Data Path Delay: 6.328ns (logic 3.867ns (61.105%) route 2.461ns (38.895%)) + Logic Levels: 2 (IBUF_INTERMDISABLE=1 IDELAYE2=1) + Clock Path Skew: 0.301ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.219ns = ( 2.719 - 1.500 ) + Source Clock Delay (SCD): 1.525ns + Clock Pessimism Removal (CPR): 0.607ns + Clock Uncertainty: 0.220ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.154ns + Timing Exception: MultiCycle Path Setup -end 6 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.703 1.525 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/last_master_r_reg[2] + SLICE_X75Y69 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X75Y69 FDRE (Prop_fdre_C_Q) 0.456 1.981 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/Q + net (fo=40, routed) 2.461 4.443 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[12].u_iobuf_dq/IBUFDISABLE + V1 IBUF_INTERMDISABLE (Prop_ibuf_intermdisable_IBUFDISABLE_O) + 2.596 7.039 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[12].u_iobuf_dq/IBUF/O + net (fo=2, routed) 0.000 7.039 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/mem_dq_in[7] + IDELAY_X1Y85 IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT) + 0.815 7.854 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.idelay_dq.idelaye2/DATAOUT + net (fo=1, routed) 0.000 7.854 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/data_in_dly_8 + ILOGIC_X1Y85 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq/DDLY + ------------------------------------------------------------------- ------------------- + + (clock u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk fall edge) + 16.500 16.500 f + E3 0.000 16.500 f CLK100MHZ (IN) + net (fo=0) 0.000 16.500 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 17.911 f input_clock/O + net (fo=1, routed) 1.162 19.073 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 11.749 f clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 13.388 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 13.479 f sys_buffer/O + net (fo=1, routed) 1.544 15.024 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.083 15.107 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.576 15.683 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.624 17.307 f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + net (fo=16, routed) 0.412 17.719 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/CLKB0 + ILOGIC_X1Y85 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq/CLKB (IS_INVERTED) + clock pessimism 0.607 18.327 + clock uncertainty -0.220 18.107 + ILOGIC_X1Y85 ISERDESE2 (Setup_iserdese2_CLKB_DDLY) + -0.165 17.942 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq + ------------------------------------------------------------------- + required time 17.942 + arrival time -7.854 + ------------------------------------------------------------------- + slack 10.088 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 45.348ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq/DDLY + (rising edge-triggered cell ISERDESE2 clocked by u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: -45.000ns (u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk rise@15.000ns - clk_pll_i rise@60.000ns) + Data Path Delay: 1.688ns (logic 1.068ns (63.257%) route 0.620ns (36.743%)) + Logic Levels: 2 (IBUF_INTERMDISABLE=1 IDELAYE2=1) + Clock Path Skew: 1.065ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.990ns + Source Clock Delay (SCD): 0.163ns + Clock Pessimism Removal (CPR): -0.237ns + Clock Uncertainty: 0.220ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.154ns + Timing Exception: MultiCycle Path Setup -end 6 Hold -start 5 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 60.000 60.000 r + E3 0.000 60.000 r CLK100MHZ (IN) + net (fo=0) 0.000 60.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 60.250 r input_clock/O + net (fo=1, routed) 0.440 60.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 58.311 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 58.810 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 58.836 r sys_buffer/O + net (fo=1, routed) 0.566 59.402 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 59.452 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 59.846 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 59.866 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 60.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 59.051 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 59.550 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 59.576 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.587 60.163 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/last_master_r_reg[2] + SLICE_X75Y69 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X75Y69 FDRE (Prop_fdre_C_Q) 0.141 60.304 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/Q + net (fo=40, routed) 0.620 60.924 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[13].u_iobuf_dq/IBUFDISABLE + T3 IBUF_INTERMDISABLE (Prop_ibuf_intermdisable_IBUFDISABLE_O) + 0.684 61.608 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[13].u_iobuf_dq/IBUF/O + net (fo=2, routed) 0.000 61.608 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/mem_dq_in[1] + IDELAY_X1Y77 IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT) + 0.243 61.851 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[2].iserdes_dq_.idelay_dq.idelaye2/DATAOUT + net (fo=1, routed) 0.000 61.851 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/data_in_dly_2 + ILOGIC_X1Y77 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq/DDLY + ------------------------------------------------------------------- ------------------- + + (clock u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk rise edge) + 15.000 15.000 r + E3 0.000 15.000 r CLK100MHZ (IN) + net (fo=0) 0.000 15.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 15.438 r input_clock/O + net (fo=1, routed) 0.480 15.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 12.755 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 13.298 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 13.327 r sys_buffer/O + net (fo=1, routed) 0.835 14.162 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.053 14.215 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.217 14.432 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.381 15.812 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + net (fo=16, routed) 0.178 15.990 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq_0 + ILOGIC_X1Y77 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq/CLK + clock pessimism 0.237 16.227 + clock uncertainty 0.220 16.447 + ILOGIC_X1Y77 ISERDESE2 (Hold_iserdese2_CLK_DDLY) + 0.056 16.503 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq + ------------------------------------------------------------------- + required time -16.503 + arrival time 61.851 + ------------------------------------------------------------------- + slack 45.348 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_pll_i + To Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk + +Setup : 0 Failing Endpoints, Worst Slack 8.404ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 46.023ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 8.404ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq/DDLY + (falling edge-triggered cell ISERDESE2 clocked by u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 16.500ns (u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk fall@16.500ns - clk_pll_i rise@0.000ns) + Data Path Delay: 8.019ns (logic 3.867ns (48.222%) route 4.152ns (51.778%)) + Logic Levels: 2 (IBUF_INTERMDISABLE=1 IDELAYE2=1) + Clock Path Skew: 0.308ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.226ns = ( 2.726 - 1.500 ) + Source Clock Delay (SCD): 1.525ns + Clock Pessimism Removal (CPR): 0.607ns + Clock Uncertainty: 0.220ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.154ns + Timing Exception: MultiCycle Path Setup -end 6 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.703 1.525 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/last_master_r_reg[2] + SLICE_X75Y69 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X75Y69 FDRE (Prop_fdre_C_Q) 0.456 1.981 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/Q + net (fo=40, routed) 4.152 6.133 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[5].u_iobuf_dq/IBUFDISABLE + M1 IBUF_INTERMDISABLE (Prop_ibuf_intermdisable_IBUFDISABLE_O) + 2.596 8.729 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[5].u_iobuf_dq/IBUF/O + net (fo=2, routed) 0.000 8.729 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/mem_dq_in[7] + IDELAY_X1Y97 IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT) + 0.815 9.544 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.idelay_dq.idelaye2/DATAOUT + net (fo=1, routed) 0.000 9.544 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/data_in_dly_8 + ILOGIC_X1Y97 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq/DDLY + ------------------------------------------------------------------- ------------------- + + (clock u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk fall edge) + 16.500 16.500 f + E3 0.000 16.500 f CLK100MHZ (IN) + net (fo=0) 0.000 16.500 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 17.911 f input_clock/O + net (fo=1, routed) 1.162 19.073 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 11.749 f clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 13.388 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 13.479 f sys_buffer/O + net (fo=1, routed) 1.544 15.024 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.083 15.107 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.566 15.673 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.624 17.297 f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + net (fo=16, routed) 0.429 17.726 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/CLKB0_4 + ILOGIC_X1Y97 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq/CLKB (IS_INVERTED) + clock pessimism 0.607 18.334 + clock uncertainty -0.220 18.114 + ILOGIC_X1Y97 ISERDESE2 (Setup_iserdese2_CLKB_DDLY) + -0.165 17.949 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq + ------------------------------------------------------------------- + required time 17.949 + arrival time -9.544 + ------------------------------------------------------------------- + slack 8.404 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 46.023ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/DDLY + (rising edge-triggered cell ISERDESE2 clocked by u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: -45.000ns (u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk rise@15.000ns - clk_pll_i rise@60.000ns) + Data Path Delay: 2.362ns (logic 1.068ns (45.210%) route 1.294ns (54.790%)) + Logic Levels: 2 (IBUF_INTERMDISABLE=1 IDELAYE2=1) + Clock Path Skew: 1.064ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.989ns + Source Clock Delay (SCD): 0.163ns + Clock Pessimism Removal (CPR): -0.237ns + Clock Uncertainty: 0.220ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.154ns + Timing Exception: MultiCycle Path Setup -end 6 Hold -start 5 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 60.000 60.000 r + E3 0.000 60.000 r CLK100MHZ (IN) + net (fo=0) 0.000 60.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 60.250 r input_clock/O + net (fo=1, routed) 0.440 60.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 58.311 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 58.810 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 58.836 r sys_buffer/O + net (fo=1, routed) 0.566 59.402 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 59.452 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 59.846 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 59.866 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 60.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 59.051 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 59.550 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 59.576 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.587 60.163 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/last_master_r_reg[2] + SLICE_X75Y69 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X75Y69 FDRE (Prop_fdre_C_Q) 0.141 60.304 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/Q + net (fo=40, routed) 1.294 61.598 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[3].u_iobuf_dq/IBUFDISABLE + L6 IBUF_INTERMDISABLE (Prop_ibuf_intermdisable_IBUFDISABLE_O) + 0.684 62.282 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[3].u_iobuf_dq/IBUF/O + net (fo=2, routed) 0.000 62.282 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/mem_dq_in[0] + IDELAY_X1Y88 IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT) + 0.243 62.525 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.idelay_dq.idelaye2/DATAOUT + net (fo=1, routed) 0.000 62.525 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/data_in_dly_1 + ILOGIC_X1Y88 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/DDLY + ------------------------------------------------------------------- ------------------- + + (clock u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk rise edge) + 15.000 15.000 r + E3 0.000 15.000 r CLK100MHZ (IN) + net (fo=0) 0.000 15.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 15.438 r input_clock/O + net (fo=1, routed) 0.480 15.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 12.755 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 13.298 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 13.327 r sys_buffer/O + net (fo=1, routed) 0.835 14.162 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.053 14.215 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.211 14.426 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.381 15.806 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + net (fo=16, routed) 0.183 15.989 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq_0 + ILOGIC_X1Y88 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLK + clock pessimism 0.237 16.226 + clock uncertainty 0.220 16.446 + ILOGIC_X1Y88 ISERDESE2 (Hold_iserdese2_CLK_DDLY) + 0.056 16.502 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq + ------------------------------------------------------------------- + required time -16.502 + arrival time 62.525 + ------------------------------------------------------------------- + slack 46.023 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: sync_pulse + To Clock: mem_refclk + +Setup : 0 Failing Endpoints, Worst Slack 1.276ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.909ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.276ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 + (clock source 'sync_pulse' {rise@1.312ns fall@4.312ns period=48.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/SYNCIN + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: mem_refclk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 1.687ns (mem_refclk rise@6.000ns - sync_pulse fall@4.312ns) + Data Path Delay: 0.621ns (logic 0.000ns (0.000%) route 0.621ns (100.000%)) + Logic Levels: 0 + Clock Path Skew: 0.589ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.804ns = ( 5.196 - 6.000 ) + Source Clock Delay (SCD): -0.786ns = ( 3.527 - 4.312 ) + Clock Pessimism Removal (CPR): 0.607ns + Clock Uncertainty: 0.198ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.139ns + Phase Error (PE): 0.120ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sync_pulse fall edge) + 4.312 4.312 f + E3 0.000 4.312 f CLK100MHZ (IN) + net (fo=0) 0.000 4.312 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 5.794 f input_clock/O + net (fo=1, routed) 1.233 7.027 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -0.043 f clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 1.676 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 1.772 f sys_buffer/O + net (fo=1, routed) 1.666 3.439 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + 0.088 3.527 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 + net (fo=7, routed) 0.621 4.148 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/sync_pulse + PHY_CONTROL_X1Y1 PHY_CONTROL f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/SYNCIN + ------------------------------------------------------------------- ------------------- + + (clock mem_refclk rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, routed) 1.162 8.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 1.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 2.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 2.979 r sys_buffer/O + net (fo=1, routed) 1.544 4.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 4.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.589 5.196 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + clock pessimism 0.607 5.803 + clock uncertainty -0.198 5.605 + PHY_CONTROL_X1Y1 PHY_CONTROL (Setup_phy_control_MEMREFCLK_SYNCIN) + -0.182 5.423 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i + ------------------------------------------------------------------- + required time 5.423 + arrival time -4.148 + ------------------------------------------------------------------- + slack 1.276 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.909ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 + (clock source 'sync_pulse' {rise@1.312ns fall@4.312ns period=48.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/SYNCIN + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: mem_refclk + Path Type: Hold (Min at Slow Process Corner) + Requirement: -1.312ns (mem_refclk rise@0.000ns - sync_pulse rise@1.312ns) + Data Path Delay: 0.589ns (logic 0.000ns (0.000%) route 0.589ns (100.000%)) + Logic Levels: 0 + Clock Path Skew: 0.621ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.165ns + Source Clock Delay (SCD): -1.393ns = ( -0.081 - 1.312 ) + Clock Pessimism Removal (CPR): 0.607ns + Clock Uncertainty: 0.198ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.139ns + Phase Error (PE): 0.120ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sync_pulse rise edge) + 1.312 1.312 r + E3 0.000 1.312 r CLK100MHZ (IN) + net (fo=0) 0.000 1.312 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 2.724 r input_clock/O + net (fo=1, routed) 1.162 3.886 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -3.438 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -1.799 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -1.708 r sys_buffer/O + net (fo=1, routed) 1.544 -0.164 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + 0.083 -0.081 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 + net (fo=7, routed) 0.589 0.508 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/sync_pulse + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/SYNCIN + ------------------------------------------------------------------- ------------------- + + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.621 -0.165 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + clock pessimism -0.607 -0.772 + clock uncertainty 0.198 -0.574 + PHY_CONTROL_X1Y1 PHY_CONTROL (Hold_phy_control_MEMREFCLK_SYNCIN) + 0.174 -0.400 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i + ------------------------------------------------------------------- + required time 0.400 + arrival time 0.508 + ------------------------------------------------------------------- + slack 0.909 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk + To Clock: oserdes_clkdiv + +Setup : 0 Failing Endpoints, Worst Slack 2.105ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.095ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 2.105ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clkdiv rise@12.000ns - oserdes_clk rise@9.000ns) + Data Path Delay: 0.338ns (logic 0.338ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.148ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.707ns = ( 13.707 - 12.000 ) + Source Clock Delay (SCD): 2.262ns = ( 11.262 - 9.000 ) + Clock Pessimism Removal (CPR): 0.703ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.081ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk rise edge) + 9.000 9.000 r + E3 0.000 9.000 r CLK100MHZ (IN) + net (fo=0) 0.000 9.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 10.482 r input_clock/O + net (fo=1, routed) 1.233 11.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 4.645 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 6.364 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 6.460 r sys_buffer/O + net (fo=1, routed) 1.666 8.126 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 8.214 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.614 8.828 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 11.262 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.338 11.600 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/RDENABLE + net (fo=1, routed) 0.000 11.600 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/po_rd_enable + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.582 11.189 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 13.559 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 13.707 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, routed) 0.000 13.707 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/oserdes_clkdiv + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + clock pessimism 0.703 14.410 + clock uncertainty -0.054 14.356 + OUT_FIFO_X1Y4 OUT_FIFO (Setup_out_fifo_RDCLK_RDEN) + -0.651 13.705 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo + ------------------------------------------------------------------- + required time 13.705 + arrival time -11.600 + ------------------------------------------------------------------- + slack 2.105 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.095ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv rise@0.000ns - oserdes_clk rise@0.000ns) + Data Path Delay: 0.172ns (logic 0.172ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.088ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.661ns + Source Clock Delay (SCD): 1.741ns + Clock Pessimism Removal (CPR): -0.168ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.197 -0.351 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.741 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.172 1.913 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/RDENABLE + net (fo=1, routed) 0.000 1.913 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/po_rd_enable + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.218 -0.567 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.573 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.661 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, routed) 0.000 1.661 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/oserdes_clkdiv + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + clock pessimism 0.168 1.829 + OUT_FIFO_X1Y4 OUT_FIFO (Hold_out_fifo_RDCLK_RDEN) + -0.011 1.818 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo + ------------------------------------------------------------------- + required time -1.818 + arrival time 1.913 + ------------------------------------------------------------------- + slack 0.095 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_1 + To Clock: oserdes_clkdiv_1 + +Setup : 0 Failing Endpoints, Worst Slack 2.105ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.095ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 2.105ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_1 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv_1 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clkdiv_1 rise@12.000ns - oserdes_clk_1 rise@9.000ns) + Data Path Delay: 0.338ns (logic 0.338ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.148ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.697ns = ( 13.697 - 12.000 ) + Source Clock Delay (SCD): 2.251ns = ( 11.251 - 9.000 ) + Clock Pessimism Removal (CPR): 0.702ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.081ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_1 rise edge) + 9.000 9.000 r + E3 0.000 9.000 r CLK100MHZ (IN) + net (fo=0) 0.000 9.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 10.482 r input_clock/O + net (fo=1, routed) 1.233 11.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 4.645 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 6.364 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 6.460 r sys_buffer/O + net (fo=1, routed) 1.666 8.126 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 8.214 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.603 8.817 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 11.251 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.338 11.589 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/RDENABLE + net (fo=1, routed) 0.000 11.589 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/po_rd_enable + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_1 rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.572 11.179 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 13.549 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 13.697 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, routed) 0.000 13.697 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/oserdes_clkdiv + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + clock pessimism 0.702 14.399 + clock uncertainty -0.054 14.345 + OUT_FIFO_X1Y5 OUT_FIFO (Setup_out_fifo_RDCLK_RDEN) + -0.651 13.694 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo + ------------------------------------------------------------------- + required time 13.694 + arrival time -11.589 + ------------------------------------------------------------------- + slack 2.105 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.095ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_1 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv_1 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_1 rise@0.000ns - oserdes_clk_1 rise@0.000ns) + Data Path Delay: 0.172ns (logic 0.172ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.088ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.652ns + Source Clock Delay (SCD): 1.734ns + Clock Pessimism Removal (CPR): -0.170ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.190 -0.358 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.734 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.172 1.906 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/RDENABLE + net (fo=1, routed) 0.000 1.906 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/po_rd_enable + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.209 -0.576 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.564 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.652 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, routed) 0.000 1.652 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/oserdes_clkdiv + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + clock pessimism 0.170 1.822 + OUT_FIFO_X1Y5 OUT_FIFO (Hold_out_fifo_RDCLK_RDEN) + -0.011 1.811 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo + ------------------------------------------------------------------- + required time -1.811 + arrival time 1.906 + ------------------------------------------------------------------- + slack 0.095 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_2 + To Clock: oserdes_clkdiv_2 + +Setup : 0 Failing Endpoints, Worst Slack 2.105ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.095ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 2.105ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_2 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clkdiv_2 rise@6.000ns - oserdes_clk_2 rise@3.000ns) + Data Path Delay: 0.338ns (logic 0.338ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.148ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.707ns = ( 7.707 - 6.000 ) + Source Clock Delay (SCD): 2.262ns = ( 5.262 - 3.000 ) + Clock Pessimism Removal (CPR): 0.703ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.081ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_2 rise edge) + 3.000 3.000 r + E3 0.000 3.000 r CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 4.482 r input_clock/O + net (fo=1, routed) 1.233 5.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -1.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 0.364 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 0.460 r sys_buffer/O + net (fo=1, routed) 1.666 2.126 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 2.214 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.614 2.828 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 5.262 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.338 5.600 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/RDENABLE + net (fo=1, routed) 0.000 5.600 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/po_rd_enable + OUT_FIFO_X1Y6 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_2 rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, routed) 1.162 8.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 1.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 2.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 2.979 r sys_buffer/O + net (fo=1, routed) 1.544 4.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 4.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.582 5.189 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 7.559 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 7.707 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, routed) 0.000 7.707 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/oserdes_clkdiv + OUT_FIFO_X1Y6 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + clock pessimism 0.703 8.410 + clock uncertainty -0.054 8.356 + OUT_FIFO_X1Y6 OUT_FIFO (Setup_out_fifo_RDCLK_RDEN) + -0.651 7.705 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo + ------------------------------------------------------------------- + required time 7.705 + arrival time -5.600 + ------------------------------------------------------------------- + slack 2.105 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.095ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_2 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_2 rise@0.000ns - oserdes_clk_2 rise@0.000ns) + Data Path Delay: 0.172ns (logic 0.172ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.088ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.661ns + Source Clock Delay (SCD): 1.741ns + Clock Pessimism Removal (CPR): -0.168ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.197 -0.351 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.741 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.172 1.913 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/RDENABLE + net (fo=1, routed) 0.000 1.913 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/po_rd_enable + OUT_FIFO_X1Y6 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.218 -0.567 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.573 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.661 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, routed) 0.000 1.661 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/oserdes_clkdiv + OUT_FIFO_X1Y6 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + clock pessimism 0.168 1.829 + OUT_FIFO_X1Y6 OUT_FIFO (Hold_out_fifo_RDCLK_RDEN) + -0.011 1.818 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo + ------------------------------------------------------------------- + required time -1.818 + arrival time 1.913 + ------------------------------------------------------------------- + slack 0.095 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_3 + To Clock: oserdes_clkdiv_3 + +Setup : 0 Failing Endpoints, Worst Slack 2.105ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.095ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 2.105ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_3 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clkdiv_3 rise@6.000ns - oserdes_clk_3 rise@3.000ns) + Data Path Delay: 0.338ns (logic 0.338ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.148ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.697ns = ( 7.697 - 6.000 ) + Source Clock Delay (SCD): 2.251ns = ( 5.251 - 3.000 ) + Clock Pessimism Removal (CPR): 0.702ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.081ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_3 rise edge) + 3.000 3.000 r + E3 0.000 3.000 r CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 4.482 r input_clock/O + net (fo=1, routed) 1.233 5.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -1.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 0.364 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 0.460 r sys_buffer/O + net (fo=1, routed) 1.666 2.126 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 2.214 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.603 2.817 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 5.251 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.338 5.589 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/RDENABLE + net (fo=1, routed) 0.000 5.589 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/po_rd_enable + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_3 rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, routed) 1.162 8.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 1.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 2.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 2.979 r sys_buffer/O + net (fo=1, routed) 1.544 4.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 4.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.572 5.179 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 7.549 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 7.697 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, routed) 0.000 7.697 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/oserdes_clkdiv + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + clock pessimism 0.702 8.399 + clock uncertainty -0.054 8.345 + OUT_FIFO_X1Y7 OUT_FIFO (Setup_out_fifo_RDCLK_RDEN) + -0.651 7.694 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo + ------------------------------------------------------------------- + required time 7.694 + arrival time -5.589 + ------------------------------------------------------------------- + slack 2.105 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.095ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_3 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_3 rise@0.000ns - oserdes_clk_3 rise@0.000ns) + Data Path Delay: 0.172ns (logic 0.172ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.088ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.652ns + Source Clock Delay (SCD): 1.734ns + Clock Pessimism Removal (CPR): -0.170ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.190 -0.358 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.734 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.172 1.906 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/RDENABLE + net (fo=1, routed) 0.000 1.906 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/po_rd_enable + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.209 -0.576 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.564 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.652 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, routed) 0.000 1.652 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/oserdes_clkdiv + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + clock pessimism 0.170 1.822 + OUT_FIFO_X1Y7 OUT_FIFO (Hold_out_fifo_RDCLK_RDEN) + -0.011 1.811 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo + ------------------------------------------------------------------- + required time -1.811 + arrival time 1.906 + ------------------------------------------------------------------- + slack 0.095 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: core_raw + To Clock: clk_pll_i + +Setup : 0 Failing Endpoints, Worst Slack 38.557ns, Total Violation 0.000ns +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 38.557ns (required time - arrival time) + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: clk_pll_i + Path Type: Setup (Max at Slow Process Corner) + Requirement: 40.000ns (MaxDelay Path 40.000ns) + Data Path Delay: 1.165ns (logic 0.419ns (35.978%) route 0.746ns (64.022%)) + Logic Levels: 0 + Timing Exception: MaxDelay Path 40.000ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + SLICE_X53Y80 0.000 0.000 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + SLICE_X53Y80 FDRE (Prop_fdre_C_Q) 0.419 0.419 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.746 1.165 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[1] + SLICE_X48Y80 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + max delay 40.000 40.000 + SLICE_X48Y80 FDRE (Setup_fdre_C_D) -0.278 39.722 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + ------------------------------------------------------------------- + required time 39.722 + arrival time -1.165 + ------------------------------------------------------------------- + slack 38.557 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: ref_raw + To Clock: clk_pll_i + +Setup : 0 Failing Endpoints, Worst Slack 16.759ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.112ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 16.759ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[7]/C + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[7]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: clk_pll_i + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (MaxDelay Path 20.000ns) + Data Path Delay: 4.944ns (logic 0.456ns (9.223%) route 4.488ns (90.777%)) + Logic Levels: 0 + Clock Path Skew: 1.995ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.667ns + Source Clock Delay (SCD): -0.933ns + Clock Pessimism Removal (CPR): 0.395ns + Clock Uncertainty: 0.245ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.178ns + Timing Exception: MaxDelay Path 20.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.070 -4.355 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.719 -2.636 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r ref_buffer/O + net (fo=67, routed) 1.607 -0.933 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/clk_ref_i + SLICE_X32Y126 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[7]/C + ------------------------------------------------------------------- ------------------- + SLICE_X32Y126 FDRE (Prop_fdre_C_Q) 0.456 -0.477 r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[7]/Q + net (fo=1, routed) 4.488 4.011 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_lcl[7] + SLICE_X35Y129 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[7]/D + ------------------------------------------------------------------- ------------------- + + max delay 20.000 20.000 + E3 0.000 20.000 r CLK100MHZ (IN) + net (fo=0) 0.000 20.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 21.411 r input_clock/O + net (fo=1, routed) 1.162 22.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 15.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 16.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 16.979 r sys_buffer/O + net (fo=1, routed) 1.544 18.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 18.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 19.812 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 19.893 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 20.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 17.442 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 19.081 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 19.172 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.495 20.667 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r5_reg[11]_0 + SLICE_X35Y129 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[7]/C + clock pessimism 0.395 21.062 + clock uncertainty -0.245 20.817 + SLICE_X35Y129 FDRE (Setup_fdre_C_D) -0.047 20.770 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[7] + ------------------------------------------------------------------- + required time 20.770 + arrival time -4.011 + ------------------------------------------------------------------- + slack 16.759 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.112ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[4]/C + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[4]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: clk_pll_i + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_pll_i rise@0.000ns - ref_raw rise@0.000ns) + Data Path Delay: 1.784ns (logic 0.141ns (7.901%) route 1.643ns (92.099%)) + Logic Levels: 0 + Clock Path Skew: 1.352ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.185ns + Source Clock Delay (SCD): -0.611ns + Clock Pessimism Removal (CPR): -0.557ns + Clock Uncertainty: 0.245ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.178ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -2.379 -1.689 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.499 -1.190 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r ref_buffer/O + net (fo=67, routed) 0.553 -0.611 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/clk_ref_i + SLICE_X33Y126 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X33Y126 FDRE (Prop_fdre_C_Q) 0.141 -0.470 r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[4]/Q + net (fo=1, routed) 1.643 1.173 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_lcl[4] + SLICE_X35Y127 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[4]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.437 -0.348 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.043 -0.305 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.494 0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.400 -1.211 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.544 -0.668 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -0.639 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.823 0.185 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r5_reg[11]_0 + SLICE_X35Y127 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[4]/C + clock pessimism 0.557 0.741 + clock uncertainty 0.245 0.986 + SLICE_X35Y127 FDRE (Hold_fdre_C_D) 0.075 1.061 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[4] + ------------------------------------------------------------------- + required time -1.061 + arrival time 1.173 + ------------------------------------------------------------------- + slack 0.112 + + + + + +--------------------------------------------------------------------------------------------------- +Path Group: **async_default** +From Clock: clk_pll_i + To Clock: clk_pll_i + +Setup : 0 Failing Endpoints, Worst Slack 8.947ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.176ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 8.947ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__8/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n_reg/CLR + (recovery check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 12.000ns (clk_pll_i rise@12.000ns - clk_pll_i rise@0.000ns) + Data Path Delay: 2.717ns (logic 0.518ns (19.068%) route 2.199ns (80.932%)) + Logic Levels: 0 + Clock Path Skew: 0.050ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.763ns = ( 12.763 - 12.000 ) + Source Clock Delay (SCD): 1.442ns + Clock Pessimism Removal (CPR): 0.729ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.620 1.442 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + SLICE_X58Y66 FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__8/C + ------------------------------------------------------------------- ------------------- + SLICE_X58Y66 FDPE (Prop_fdpe_C_Q) 0.518 1.960 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__8/Q + net (fo=47, routed) 2.199 4.159 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/calib_ctl_wren_reg_7 + SLICE_X78Y66 FDCE f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 11.812 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 11.893 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 12.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 9.442 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 11.081 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 11.172 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.590 12.763 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg[14]_0 + SLICE_X78Y66 FDCE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n_reg/C + clock pessimism 0.729 13.492 + clock uncertainty -0.067 13.425 + SLICE_X78Y66 FDCE (Recov_fdce_C_CLR) -0.319 13.106 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n_reg + ------------------------------------------------------------------- + required time 13.106 + arrival time -4.159 + ------------------------------------------------------------------- + slack 8.947 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.176ns (arrival time - required time) + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]/CLR + (removal check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (clk_pll_i rise@0.000ns - clk_pll_i rise@0.000ns) + Data Path Delay: 0.291ns (logic 0.128ns (43.969%) route 0.163ns (56.031%)) + Logic Levels: 0 + Clock Path Skew: 0.261ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.180ns + Source Clock Delay (SCD): 0.129ns + Clock Pessimism Removal (CPR): -0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 -0.154 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 -0.134 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 -0.949 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 -0.450 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.424 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.553 0.129 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/dest_clk + SLICE_X51Y77 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X51Y77 FDPE (Prop_fdpe_C_Q) 0.128 0.257 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/Q + net (fo=3, routed) 0.163 0.420 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.rst_rd_reg2 + SLICE_X53Y77 FDCE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.437 -0.348 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.043 -0.305 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.494 0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.400 -1.211 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.544 -0.668 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -0.639 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.819 0.180 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/m_aclk + SLICE_X53Y77 FDCE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]/C + clock pessimism 0.210 0.390 + SLICE_X53Y77 FDCE (Remov_fdce_C_CLR) -0.146 0.244 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0] + ------------------------------------------------------------------- + required time -0.244 + arrival time 0.420 + ------------------------------------------------------------------- + slack 0.176 + + + + + +--------------------------------------------------------------------------------------------------- +Path Group: **async_default** +From Clock: core_raw + To Clock: core_raw + +Setup : 0 Failing Endpoints, Worst Slack 20.362ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.154ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 20.362ns (required time - arrival time) + Source: reset_count_reg[2]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: platform/chip/system/clint_domain/intsource/reg_0/reg_0_reg[1]/CLR + (recovery check against rising-edge clock core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 40.000ns (core_raw rise@40.000ns - core_raw rise@0.000ns) + Data Path Delay: 19.149ns (logic 1.308ns (6.831%) route 17.841ns (93.169%)) + Logic Levels: 5 (LUT2=1 LUT4=2 LUT5=1 LUT6=1) + Clock Path Skew: -0.079ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.493ns = ( 38.507 - 40.000 ) + Source Clock Delay (SCD): -0.927ns + Clock Pessimism Removal (CPR): 0.487ns + Clock Uncertainty: 0.091ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.613 -0.927 clk + SLICE_X68Y74 FDRE r reset_count_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X68Y74 FDRE (Prop_fdre_C_Q) 0.456 -0.471 r reset_count_reg[2]/Q + net (fo=2, routed) 0.843 0.372 platform/normalizer/reset_count_reg[2] + SLICE_X69Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.496 r platform/normalizer/axi_fullwidth_LUT6_1/O + net (fo=1, routed) 0.292 0.789 platform/normalizer/axi_fullwidth_net_1 + SLICE_X69Y77 LUT5 (Prop_lut5_I4_O) 0.124 0.913 r platform/normalizer/axi_fullwidth_LUT5_1/O + net (fo=1, routed) 0.433 1.346 platform/normalizer/axi_fullwidth_net_3 + SLICE_X69Y77 LUT4 (Prop_lut4_I3_O) 0.124 1.470 f platform/normalizer/axi_fullwidth_LUT4_9/O + net (fo=21, routed) 0.825 2.294 platform/normalizer/sel + SLICE_X69Y78 LUT4 (Prop_lut4_I3_O) 0.153 2.447 f platform/normalizer/axi_fullwidth_LUT4_10/O + net (fo=899, routed) 3.798 6.246 platform/loader/cpu_run_reg_inv_20 + SLICE_X85Y102 LUT2 (Prop_lut2_I0_O) 0.327 6.573 f platform/loader/in_pipe_v_i_1__0/O + net (fo=3764, routed) 11.649 18.222 platform/chip/system/clint_domain/intsource/reg_0/cpu_reset + SLICE_X10Y93 FDCE f platform/chip/system/clint_domain/intsource/reg_0/reg_0_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 40.000 40.000 r + E3 0.000 40.000 r CLK100MHZ (IN) + net (fo=0) 0.000 40.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r input_clock/O + net (fo=1, routed) 1.162 42.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 35.249 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 36.888 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 36.979 r core_buffer/O + net (fo=35517, routed) 1.527 38.507 platform/chip/system/clint_domain/intsource/reg_0/clk + SLICE_X10Y93 FDCE r platform/chip/system/clint_domain/intsource/reg_0/reg_0_reg[1]/C + clock pessimism 0.487 38.994 + clock uncertainty -0.091 38.903 + SLICE_X10Y93 FDCE (Recov_fdce_C_CLR) -0.319 38.584 platform/chip/system/clint_domain/intsource/reg_0/reg_0_reg[1] + ------------------------------------------------------------------- + required time 38.584 + arrival time -18.222 + ------------------------------------------------------------------- + slack 20.362 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.154ns (arrival time - required time) + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + (rising edge-triggered cell FDPE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1]/CLR + (removal check against rising-edge clock core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (core_raw rise@0.000ns - core_raw rise@0.000ns) + Data Path Delay: 0.349ns (logic 0.141ns (40.345%) route 0.208ns (59.655%)) + Logic Levels: 0 + Clock Path Skew: 0.262ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.849ns + Source Clock Delay (SCD): -0.607ns + Clock Pessimism Removal (CPR): -0.504ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.379 -1.689 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.499 -1.190 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.164 r core_buffer/O + net (fo=35517, routed) 0.557 -0.607 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/s_aclk + SLICE_X51Y80 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X51Y80 FDPE (Prop_fdpe_C_Q) 0.141 -0.466 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q + net (fo=15, routed) 0.208 -0.258 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] + SLICE_X54Y80 FDCE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.163 -2.245 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.544 -1.702 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.673 r core_buffer/O + net (fo=35517, routed) 0.824 -0.849 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/s_aclk + SLICE_X54Y80 FDCE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1]/C + clock pessimism 0.504 -0.345 + SLICE_X54Y80 FDCE (Remov_fdce_C_CLR) -0.067 -0.412 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1] + ------------------------------------------------------------------- + required time 0.412 + arrival time -0.258 + ------------------------------------------------------------------- + slack 0.154 + + + + + +--------------------------------------------------------------------------------------------------- +Path Group: **default** +From Clock: clk_pll_i + To Clock: + +Setup : 0 Failing Endpoints, Worst Slack 1.977ns, Total Violation 0.000ns +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.977ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/RESET + Path Group: **default** + Path Type: Max at Slow Process Corner + Requirement: 5.000ns (MaxDelay Path 5.000ns) + Data Path Delay: 3.023ns (logic 0.456ns (15.083%) route 2.567ns (84.917%)) + Logic Levels: 0 + Output Delay: 0.000ns + Timing Exception: MaxDelay Path 5.000ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + SLICE_X69Y117 0.000 0.000 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + SLICE_X69Y117 FDPE (Prop_fdpe_C_Q) 0.456 0.456 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/Q + net (fo=50, routed) 2.567 3.023 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i_0 + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/RESET + ------------------------------------------------------------------- ------------------- + + max delay 5.000 5.000 + PHY_CONTROL_X1Y1 PHY_CONTROL 0.000 5.000 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i + output delay -0.000 5.000 + ------------------------------------------------------------------- + required time 5.000 + arrival time -3.023 + ------------------------------------------------------------------- + slack 1.977 + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: clk_pll_i + To Clock: + +Max Delay 1 Endpoint +Min Delay 2 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n_reg/C + (rising edge-triggered cell FDCE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr3_reset_n + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 5.748ns (logic 2.163ns (37.622%) route 3.586ns (62.378%)) + Logic Levels: 2 (LUT2=1 OBUF=1) + Clock Uncertainty: 0.193ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.132ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.711 1.533 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg[14]_0 + SLICE_X78Y66 FDCE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X78Y66 FDCE (Prop_fdce_C_Q) 0.518 2.051 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n_reg/Q + net (fo=1, routed) 0.961 3.012 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n + SLICE_X87Y66 LUT2 (Prop_lut2_I1_O) 0.124 3.136 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/gen_reset_obuf.u_reset_obuf_i_1/O + net (fo=1, routed) 2.625 5.761 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/mux_reset_n + K6 OBUF (Prop_obuf_I_O) 1.521 7.282 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_reset_obuf.u_reset_obuf/O + net (fo=0) 0.000 7.282 ddr3_reset_n + K6 r ddr3_reset_n (OUT) + ------------------------------------------------------------------- ------------------- + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/RESET + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 1.376ns (logic 0.141ns (10.246%) route 1.235ns (89.754%)) + Logic Levels: 0 + Clock Uncertainty: 0.193ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.132ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 -0.154 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 -0.134 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 -0.949 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 -0.450 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.424 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.558 0.134 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + SLICE_X69Y117 FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X69Y117 FDPE (Prop_fdpe_C_Q) 0.141 0.275 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/Q + net (fo=50, routed) 1.235 1.510 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i_0 + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/RESET + ------------------------------------------------------------------- ------------------- + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: core_raw + To Clock: + +Max Delay 5 Endpoints +Min Delay 5 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: platform/loader/cpu_run_reg_inv/C + (rising edge-triggered cell FDSE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: led[2] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 12.328ns (logic 4.784ns (38.808%) route 7.544ns (61.192%)) + Logic Levels: 2 (LUT5=1 OBUF=1) + Clock Uncertainty: 0.186ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.099ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.721 -0.819 platform/loader/clk + SLICE_X78Y96 FDSE r platform/loader/cpu_run_reg_inv/C + ------------------------------------------------------------------- ------------------- + SLICE_X78Y96 FDSE (Prop_fdse_C_Q) 0.478 -0.341 f platform/loader/cpu_run_reg_inv/Q + net (fo=264, routed) 3.176 2.835 platform/loader/rx_valid1 + SLICE_X69Y78 LUT5 (Prop_lut5_I4_O) 0.295 3.130 r platform/loader/led_OBUF[2]_inst_i_1/O + net (fo=1, routed) 4.368 7.498 led_OBUF[2] + T9 OBUF (Prop_obuf_I_O) 4.011 11.509 r led_OBUF[2]_inst/O + net (fo=0) 0.000 11.509 led[2] + T9 r led[2] (OUT) + ------------------------------------------------------------------- ------------------- + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: platform/peripherals/exit_code_reg[19]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: led[1] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.331ns (logic 2.205ns (66.189%) route 1.126ns (33.811%)) + Logic Levels: 3 (LUT5=1 LUT6=1 OBUF=1) + Clock Uncertainty: 0.186ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.099ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.379 -1.689 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.499 -1.190 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.164 r core_buffer/O + net (fo=35517, routed) 0.559 -0.605 platform/peripherals/clk + SLICE_X54Y101 FDRE r platform/peripherals/exit_code_reg[19]/C + ------------------------------------------------------------------- ------------------- + SLICE_X54Y101 FDRE (Prop_fdre_C_Q) 0.164 -0.441 r platform/peripherals/exit_code_reg[19]/Q + net (fo=2, routed) 0.094 -0.347 platform/peripherals/exit_code[19] + SLICE_X55Y101 LUT6 (Prop_lut6_I3_O) 0.045 -0.302 r platform/peripherals/led_OBUF[1]_inst_i_4/O + net (fo=1, routed) 0.082 -0.220 platform/peripherals/led_OBUF[1]_inst_i_4_n_0 + SLICE_X55Y101 LUT5 (Prop_lut5_I2_O) 0.045 -0.175 r platform/peripherals/led_OBUF[1]_inst_i_1/O + net (fo=1, routed) 0.950 0.775 led_OBUF[1] + J5 OBUF (Prop_obuf_I_O) 1.951 2.726 r led_OBUF[1]_inst/O + net (fo=0) 0.000 2.726 led[1] + J5 r led[1] (OUT) + ------------------------------------------------------------------- ------------------- + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: clk_pll_i + To Clock: clk_pll_i + +Max Delay 13 Endpoints +Min Delay 13 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ui_reset_pipe_reg[2]/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + (recovery check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 4.076ns (logic 0.711ns (17.445%) route 3.365ns (82.555%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: -0.670ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.766ns + Source Clock Delay (SCD): 1.436ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.614 1.436 ui_clk + SLICE_X65Y77 FDPE r ui_reset_pipe_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y77 FDPE (Prop_fdpe_C_Q) 0.419 1.855 f ui_reset_pipe_reg[2]/Q + net (fo=2, routed) 0.267 2.122 memory_cdc/inst/m_axi_aresetn + SLICE_X65Y77 LUT2 (Prop_lut2_I1_O) 0.292 2.414 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi_i_1/O + net (fo=20, routed) 3.098 5.512 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/src_arst + SLICE_X89Y113 FDPE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.594 0.766 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/dest_clk + SLICE_X89Y113 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ui_reset_pipe_reg[2]/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + (removal check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Removal (Min at Fast Process Corner) + Data Path Delay: 0.744ns (logic 0.232ns (31.172%) route 0.512ns (68.828%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: 0.049ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.181ns + Source Clock Delay (SCD): 0.132ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 -0.154 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 -0.134 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 -0.949 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 -0.450 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.424 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.556 0.132 ui_clk + SLICE_X65Y77 FDPE r ui_reset_pipe_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y77 FDPE (Prop_fdpe_C_Q) 0.128 0.260 f ui_reset_pipe_reg[2]/Q + net (fo=2, routed) 0.086 0.345 memory_cdc/inst/m_axi_aresetn + SLICE_X65Y77 LUT2 (Prop_lut2_I1_O) 0.104 0.449 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi_i_1/O + net (fo=20, routed) 0.427 0.876 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/src_arst + SLICE_X51Y77 FDPE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.437 -0.348 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.043 -0.305 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.494 0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.400 -1.211 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.544 -0.668 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -0.639 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.820 0.181 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/dest_clk + SLICE_X51Y77 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: core_raw + To Clock: clk_pll_i + +Max Delay 235 Endpoints +Min Delay 255 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: reset_count_reg[2]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + (recovery check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 7.211ns (logic 1.308ns (18.138%) route 5.903ns (81.862%)) + Logic Levels: 5 (LUT2=1 LUT4=2 LUT5=1 LUT6=1) + Clock Path Skew: 1.693ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.766ns + Source Clock Delay (SCD): -0.927ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.247ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.117ns + Phase Error (PE): 0.178ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.613 -0.927 clk + SLICE_X68Y74 FDRE r reset_count_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X68Y74 FDRE (Prop_fdre_C_Q) 0.456 -0.471 r reset_count_reg[2]/Q + net (fo=2, routed) 0.843 0.372 platform/normalizer/reset_count_reg[2] + SLICE_X69Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.496 r platform/normalizer/axi_fullwidth_LUT6_1/O + net (fo=1, routed) 0.292 0.789 platform/normalizer/axi_fullwidth_net_1 + SLICE_X69Y77 LUT5 (Prop_lut5_I4_O) 0.124 0.913 r platform/normalizer/axi_fullwidth_LUT5_1/O + net (fo=1, routed) 0.433 1.346 platform/normalizer/axi_fullwidth_net_3 + SLICE_X69Y77 LUT4 (Prop_lut4_I3_O) 0.124 1.470 f platform/normalizer/axi_fullwidth_LUT4_9/O + net (fo=21, routed) 0.440 1.910 sel + SLICE_X69Y78 LUT4 (Prop_lut4_I3_O) 0.119 2.029 r memory_cdc_i_1/O + net (fo=1, routed) 0.797 2.826 memory_cdc/inst/s_axi_aresetn + SLICE_X65Y77 LUT2 (Prop_lut2_I0_O) 0.361 3.187 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi_i_1/O + net (fo=20, routed) 3.098 6.285 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/src_arst + SLICE_X89Y113 FDPE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.594 0.766 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/dest_clk + SLICE_X89Y113 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.586ns (logic 0.337ns (57.552%) route 0.249ns (42.448%)) + Logic Levels: 0 + Clock Path Skew: 2.961ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.453ns + Source Clock Delay (SCD): -1.508ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.247ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.117ns + Phase Error (PE): 0.178ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=35517, routed) 1.512 -1.508 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X68Y94 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X68Y94 FDRE (Prop_fdre_C_Q) 0.337 -1.171 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.249 -0.923 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[1] + SLICE_X69Y94 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.631 1.453 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X69Y94 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: mem_refclk + To Clock: clk_pll_i + +Max Delay 2 Endpoints +Min Delay 2 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/MEMREFCLK + (rising edge-triggered cell PHASER_IN_PHY clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[3]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 1.754ns (logic 0.402ns (22.913%) route 1.352ns (77.087%)) + Logic Levels: 0 + Clock Path Skew: 0.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.758ns + Source Clock Delay (SCD): -0.189ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.245ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.178ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.597 -0.189 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/MEMREFCLK + ------------------------------------------------------------------- ------------------- + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_MEMREFCLK_DQSFOUND) + 0.402 0.213 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/DQSFOUND + net (fo=1, routed) 1.352 1.566 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes[1] + SLICE_X81Y73 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.585 0.758 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/init_dqsfound_done_r5_reg_0 + SLICE_X81Y73 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[3]/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/MEMREFCLK + (rising edge-triggered cell PHASER_IN_PHY clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[2]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 0.546ns (logic 0.204ns (37.365%) route 0.342ns (62.635%)) + Logic Levels: 0 + Clock Path Skew: 0.574ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.223ns + Source Clock Delay (SCD): -0.351ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.245ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.178ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.197 -0.351 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/MEMREFCLK + ------------------------------------------------------------------- ------------------- + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_MEMREFCLK_DQSFOUND) + 0.204 -0.147 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/DQSFOUND + net (fo=1, routed) 0.342 0.195 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes[0] + SLICE_X89Y73 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.437 -0.348 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.043 -0.305 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.494 0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.400 -1.211 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.544 -0.668 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -0.639 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.862 0.223 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/init_dqsfound_done_r5_reg_0 + SLICE_X89Y73 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[2]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: ref_raw + To Clock: clk_pll_i + +Max Delay 32 Endpoints +Min Delay 32 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: mig_resetn_pipe_reg[2]/C + (rising edge-triggered cell FDCE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__11/PRE + (recovery check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 6.619ns (logic 0.779ns (11.769%) route 5.840ns (88.231%)) + Logic Levels: 1 (LUT4=1) + Clock Path Skew: 1.586ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.659ns + Source Clock Delay (SCD): -0.927ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.245ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.178ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.070 -4.355 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.719 -2.636 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r ref_buffer/O + net (fo=67, routed) 1.613 -0.927 ref_clk + SLICE_X70Y75 FDCE r mig_resetn_pipe_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X70Y75 FDCE (Prop_fdce_C_Q) 0.478 -0.449 r mig_resetn_pipe_reg[2]/Q + net (fo=2, routed) 1.326 0.877 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/sys_rst_i + SLICE_X89Y75 LUT4 (Prop_lut4_I2_O) 0.301 1.178 f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rstdiv2_sync_r[11]_i_1/O + net (fo=32, routed) 4.514 5.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_tmp + SLICE_X51Y119 FDPE f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__11/PRE + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.487 0.659 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + SLICE_X51Y119 FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__11/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: mig_resetn_pipe_reg[2]/C + (rising edge-triggered cell FDCE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[9]/PRE + (removal check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Removal (Min at Fast Process Corner) + Data Path Delay: 1.567ns (logic 0.247ns (15.765%) route 1.320ns (84.235%)) + Logic Levels: 1 (LUT4=1) + Clock Path Skew: 0.847ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.238ns + Source Clock Delay (SCD): -0.609ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.245ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.178ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -2.379 -1.689 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.499 -1.190 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r ref_buffer/O + net (fo=67, routed) 0.555 -0.609 ref_clk + SLICE_X70Y75 FDCE r mig_resetn_pipe_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X70Y75 FDCE (Prop_fdce_C_Q) 0.148 -0.461 r mig_resetn_pipe_reg[2]/Q + net (fo=2, routed) 0.601 0.140 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/sys_rst_i + SLICE_X89Y75 LUT4 (Prop_lut4_I2_O) 0.099 0.239 f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rstdiv2_sync_r[11]_i_1/O + net (fo=32, routed) 0.719 0.957 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_tmp + SLICE_X83Y97 FDPE f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[9]/PRE + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.437 -0.348 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.043 -0.305 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.494 0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.400 -1.211 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.544 -0.668 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -0.639 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.877 0.238 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + SLICE_X83Y97 FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[9]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: + To Clock: core_raw + +Max Delay 2 Endpoints +Min Delay 2 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: btn0 + (input port) + Destination: btn_meta_reg/D + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 7.988ns (logic 1.487ns (18.620%) route 6.501ns (81.380%)) + Logic Levels: 1 (IBUF=1) + Clock Path Skew: -1.522ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.522ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.186ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.099ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + D9 0.000 0.000 r btn0 (IN) + net (fo=0) 0.000 0.000 btn0 + D9 IBUF (Prop_ibuf_I_O) 1.487 1.487 r btn0_IBUF_inst/O + net (fo=2, routed) 6.501 7.988 btn0_IBUF + SLICE_X67Y77 FDRE r btn_meta_reg/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=35517, routed) 1.498 -1.522 clk + SLICE_X67Y77 FDRE r btn_meta_reg/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: uart_txd_in + (input port) + Destination: platform/receiver/rx_meta_reg/D + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.930ns (logic 0.294ns (15.218%) route 1.637ns (84.782%)) + Logic Levels: 1 (IBUF=1) + Clock Path Skew: -0.838ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.838ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + A9 0.000 0.000 r uart_txd_in (IN) + net (fo=0) 0.000 0.000 uart_txd_in + A9 IBUF (Prop_ibuf_I_O) 0.294 0.294 r uart_txd_in_IBUF_inst/O + net (fo=1, routed) 1.637 1.930 platform/receiver/rx + SLICE_X39Y102 FDRE r platform/receiver/rx_meta_reg/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.163 -2.245 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.544 -1.702 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.673 r core_buffer/O + net (fo=35517, routed) 0.835 -0.838 platform/receiver/clk + SLICE_X39Y102 FDRE r platform/receiver/rx_meta_reg/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: clk_pll_i + To Clock: core_raw + +Max Delay 157 Endpoints +Min Delay 177 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ui_reset_pipe_reg[2]/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + (recovery check against rising-edge clock core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 3.789ns (logic 0.711ns (18.764%) route 3.078ns (81.236%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: -2.866ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.430ns + Source Clock Delay (SCD): 1.436ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.255ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.164ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.614 1.436 ui_clk + SLICE_X65Y77 FDPE r ui_reset_pipe_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y77 FDPE (Prop_fdpe_C_Q) 0.419 1.855 f ui_reset_pipe_reg[2]/Q + net (fo=2, routed) 0.267 2.122 memory_cdc/inst/m_axi_aresetn + SLICE_X65Y77 LUT2 (Prop_lut2_I1_O) 0.292 2.414 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi_i_1/O + net (fo=20, routed) 2.812 5.225 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst + SLICE_X87Y113 FDPE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=35517, routed) 1.591 -1.430 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk + SLICE_X87Y113 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 0.238ns (logic 0.128ns (53.830%) route 0.110ns (46.170%)) + Logic Levels: 0 + Clock Path Skew: -0.978ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.847ns + Source Clock Delay (SCD): 0.131ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.255ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.164ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 -0.154 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 -0.134 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 -0.949 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 -0.450 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.424 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.555 0.131 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X57Y80 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X57Y80 FDRE (Prop_fdre_C_Q) 0.128 0.259 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.110 0.369 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[1] + SLICE_X57Y81 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.163 -2.245 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.544 -1.702 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.673 r core_buffer/O + net (fo=35517, routed) 0.826 -0.847 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X57Y81 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: core_raw + To Clock: core_raw + +Max Delay 10 Endpoints +Min Delay 10 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: reset_count_reg[2]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + (recovery check against rising-edge clock core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 6.925ns (logic 1.308ns (18.888%) route 5.617ns (81.112%)) + Logic Levels: 5 (LUT2=1 LUT4=2 LUT5=1 LUT6=1) + Clock Path Skew: -0.503ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.430ns + Source Clock Delay (SCD): -0.927ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.091ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.613 -0.927 clk + SLICE_X68Y74 FDRE r reset_count_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X68Y74 FDRE (Prop_fdre_C_Q) 0.456 -0.471 r reset_count_reg[2]/Q + net (fo=2, routed) 0.843 0.372 platform/normalizer/reset_count_reg[2] + SLICE_X69Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.496 r platform/normalizer/axi_fullwidth_LUT6_1/O + net (fo=1, routed) 0.292 0.789 platform/normalizer/axi_fullwidth_net_1 + SLICE_X69Y77 LUT5 (Prop_lut5_I4_O) 0.124 0.913 r platform/normalizer/axi_fullwidth_LUT5_1/O + net (fo=1, routed) 0.433 1.346 platform/normalizer/axi_fullwidth_net_3 + SLICE_X69Y77 LUT4 (Prop_lut4_I3_O) 0.124 1.470 f platform/normalizer/axi_fullwidth_LUT4_9/O + net (fo=21, routed) 0.440 1.910 sel + SLICE_X69Y78 LUT4 (Prop_lut4_I3_O) 0.119 2.029 r memory_cdc_i_1/O + net (fo=1, routed) 0.797 2.826 memory_cdc/inst/s_axi_aresetn + SLICE_X65Y77 LUT2 (Prop_lut2_I0_O) 0.361 3.187 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi_i_1/O + net (fo=20, routed) 2.812 5.998 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst + SLICE_X87Y113 FDPE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=35517, routed) 1.591 -1.430 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk + SLICE_X87Y113 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: lock_sync_reg[2]/C + (rising edge-triggered cell FDPE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + (removal check against rising-edge clock core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: (none) + Path Type: Removal (Min at Fast Process Corner) + Data Path Delay: 1.285ns (logic 0.293ns (22.796%) route 0.992ns (77.204%)) + Logic Levels: 2 (LUT2=1 LUT4=1) + Clock Path Skew: -0.245ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.851ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.091ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.379 -1.689 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.499 -1.190 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.164 r core_buffer/O + net (fo=35517, routed) 0.558 -0.606 clk + SLICE_X63Y78 FDPE r lock_sync_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X63Y78 FDPE (Prop_fdpe_C_Q) 0.141 -0.465 f lock_sync_reg[2]/Q + net (fo=4, routed) 0.287 -0.179 lock_sync[2] + SLICE_X69Y78 LUT4 (Prop_lut4_I1_O) 0.043 -0.136 r memory_cdc_i_1/O + net (fo=1, routed) 0.279 0.143 memory_cdc/inst/s_axi_aresetn + SLICE_X65Y77 LUT2 (Prop_lut2_I0_O) 0.109 0.252 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi_i_1/O + net (fo=20, routed) 0.427 0.679 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst + SLICE_X50Y77 FDPE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.163 -2.245 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.544 -1.702 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.673 r core_buffer/O + net (fo=35517, routed) 0.822 -0.851 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk + SLICE_X50Y77 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: + To Clock: ref_raw + +Max Delay 1 Endpoint +Min Delay 1 Endpoint +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: btn0 + (input port) + Destination: btn_ref_meta_reg/D + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 8.119ns (logic 1.487ns (18.320%) route 6.632ns (81.680%)) + Logic Levels: 1 (IBUF=1) + Clock Path Skew: -1.525ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.525ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.099ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + D9 0.000 0.000 r btn0 (IN) + net (fo=0) 0.000 0.000 btn0 + D9 IBUF (Prop_ibuf_I_O) 1.487 1.487 r btn0_IBUF_inst/O + net (fo=2, routed) 6.632 8.119 btn0_IBUF + SLICE_X67Y74 FDRE r btn_ref_meta_reg/D + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.324 -4.751 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.639 -3.112 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.021 r ref_buffer/O + net (fo=67, routed) 1.495 -1.525 ref_clk + SLICE_X67Y74 FDRE r btn_ref_meta_reg/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: btn0 + (input port) + Destination: btn_ref_meta_reg/D + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.179ns (logic 0.255ns (8.026%) route 2.924ns (91.974%)) + Logic Levels: 1 (IBUF=1) + Clock Path Skew: -0.849ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.849ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + D9 0.000 0.000 r btn0 (IN) + net (fo=0) 0.000 0.000 btn0 + D9 IBUF (Prop_ibuf_I_O) 0.255 0.255 r btn0_IBUF_inst/O + net (fo=2, routed) 2.924 3.179 btn0_IBUF + SLICE_X67Y74 FDRE r btn_ref_meta_reg/D + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -3.163 -2.245 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.544 -1.702 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r ref_buffer/O + net (fo=67, routed) 0.824 -0.849 ref_clk + SLICE_X67Y74 FDRE r btn_ref_meta_reg/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: clk_pll_i + To Clock: ref_raw + +Max Delay 0 Endpoints +Min Delay 1 Endpoint +-------------------------------------------------------------------------------------- + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg/D + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.213ns (logic 0.141ns (11.621%) route 1.072ns (88.379%)) + Logic Levels: 0 + Clock Path Skew: -0.987ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.853ns + Source Clock Delay (SCD): 0.134ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.231ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.164ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 -0.154 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 -0.134 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 -0.949 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 -0.450 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.424 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.558 0.134 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + SLICE_X69Y117 FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X69Y117 FDPE (Prop_fdpe_C_Q) 0.141 0.275 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/Q + net (fo=50, routed) 1.072 1.347 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg_0 + SLICE_X32Y125 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg/D + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -3.163 -2.245 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.544 -1.702 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r ref_buffer/O + net (fo=67, routed) 0.820 -0.853 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/clk_ref_i + SLICE_X32Y125 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: ref_raw + To Clock: ref_raw + +Max Delay 15 Endpoints +Min Delay 15 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: mig_resetn_pipe_reg[2]/C + (rising edge-triggered cell FDCE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rst_ref_sync_r_reg[0][11]/PRE + (recovery check against rising-edge clock ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 4.125ns (logic 0.808ns (19.586%) route 3.317ns (80.414%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.481ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.408ns + Source Clock Delay (SCD): -0.927ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.070 -4.355 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.719 -2.636 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r ref_buffer/O + net (fo=67, routed) 1.613 -0.927 ref_clk + SLICE_X70Y75 FDCE r mig_resetn_pipe_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X70Y75 FDCE (Prop_fdce_C_Q) 0.478 -0.449 r mig_resetn_pipe_reg[2]/Q + net (fo=2, routed) 1.326 0.877 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/sys_rst_i + SLICE_X89Y75 LUT1 (Prop_lut1_I0_O) 0.330 1.207 f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/plle2_i_i_1/O + net (fo=16, routed) 1.992 3.199 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/AS[0] + SLICE_X89Y53 FDPE f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rst_ref_sync_r_reg[0][11]/PRE + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.324 -4.751 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.639 -3.112 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.021 r ref_buffer/O + net (fo=67, routed) 1.612 -1.408 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/clk_ref_i + SLICE_X89Y53 FDPE r ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rst_ref_sync_r_reg[0][11]/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: mig_resetn_pipe_reg[2]/C + (rising edge-triggered cell FDCE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rst_ref_sync_r_reg[0][0]/PRE + (removal check against rising-edge clock ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: (none) + Path Type: Removal (Min at Fast Process Corner) + Data Path Delay: 1.482ns (logic 0.244ns (16.461%) route 1.238ns (83.539%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.184ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.793ns + Source Clock Delay (SCD): -0.609ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -2.379 -1.689 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.499 -1.190 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r ref_buffer/O + net (fo=67, routed) 0.555 -0.609 ref_clk + SLICE_X70Y75 FDCE r mig_resetn_pipe_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X70Y75 FDCE (Prop_fdce_C_Q) 0.148 -0.461 r mig_resetn_pipe_reg[2]/Q + net (fo=2, routed) 0.601 0.140 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/sys_rst_i + SLICE_X89Y75 LUT1 (Prop_lut1_I0_O) 0.096 0.236 f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/plle2_i_i_1/O + net (fo=16, routed) 0.637 0.873 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/AS[0] + SLICE_X89Y50 FDPE f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rst_ref_sync_r_reg[0][0]/PRE + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -3.163 -2.245 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.544 -1.702 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r ref_buffer/O + net (fo=67, routed) 0.880 -0.793 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/clk_ref_i + SLICE_X89Y50 FDPE r ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rst_ref_sync_r_reg[0][0]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: clk_pll_i + To Clock: + +Max Delay 1 Endpoint +Min Delay 1 Endpoint +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + (clock source 'clk_pll_i' {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBIN + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 3.457ns (logic 0.096ns (2.777%) route 3.361ns (97.223%)) + Logic Levels: 1 (BUFG=1) + Clock Uncertainty: 0.193ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.132ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i fall edge) + 6.000 6.000 f + E3 0.000 6.000 f CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 7.482 f input_clock/O + net (fo=1, routed) 1.233 8.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 1.645 f clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 3.364 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 3.460 f sys_buffer/O + net (fo=1, routed) 1.666 5.126 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 5.214 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 6.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 6.622 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 7.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + ------------------------------------------------------------------- ------------------- + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 4.007 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 5.726 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 5.822 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.641 7.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + MMCME2_ADV_X1Y1 MMCME2_ADV f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBIN + ------------------------------------------------------------------- ------------------- + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + (clock source 'clk_pll_i' {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBIN + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 1.084ns (logic 0.026ns (2.400%) route 1.058ns (97.600%)) + Logic Levels: 1 (BUFG=1) + Clock Uncertainty: 0.193ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.132ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 -0.154 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 -0.134 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + ------------------------------------------------------------------- ------------------- + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 -0.949 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 -0.450 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.424 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.559 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + MMCME2_ADV_X1Y1 MMCME2_ADV r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBIN + ------------------------------------------------------------------- ------------------- + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: fb + To Clock: + +Max Delay 1 Endpoint +Min Delay 1 Endpoint +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: clock_mmcm/CLKFBOUT + (clock source 'fb' {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: clock_mmcm/CLKFBIN + Path Group: (none) + Path Type: Max at Fast Process Corner + Data Path Delay: 1.396ns (logic 0.029ns (2.077%) route 1.367ns (97.923%)) + Logic Levels: 1 (BUFG=1) + Clock Uncertainty: 0.147ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.099ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock fb fall edge) 5.000 5.000 f + E3 0.000 5.000 f CLK100MHZ (IN) + net (fo=0) 0.000 5.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 5.438 f input_clock/O + net (fo=1, routed) 0.480 5.918 clk_in + ------------------------------------------------------------------- ------------------- + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.163 2.755 f clock_mmcm/CLKFBOUT + net (fo=1, routed) 0.544 3.298 fb + BUFGCTRL_X0Y19 BUFG (Prop_bufg_I_O) 0.029 3.327 f fb_buffer/O + net (fo=1, routed) 0.824 4.151 fb_buf + MMCME2_ADV_X1Y2 MMCME2_ADV f clock_mmcm/CLKFBIN + ------------------------------------------------------------------- ------------------- + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: clock_mmcm/CLKFBOUT + (clock source 'fb' {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: clock_mmcm/CLKFBIN + Path Group: (none) + Path Type: Min at Slow Process Corner + Data Path Delay: 3.236ns (logic 0.091ns (2.812%) route 3.145ns (97.188%)) + Logic Levels: 1 (BUFG=1) + Clock Uncertainty: 0.147ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.099ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock fb rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + ------------------------------------------------------------------- ------------------- + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -7.324 -4.751 r clock_mmcm/CLKFBOUT + net (fo=1, routed) 1.639 -3.112 fb + BUFGCTRL_X0Y19 BUFG (Prop_bufg_I_O) 0.091 -3.021 r fb_buffer/O + net (fo=1, routed) 1.506 -1.515 fb_buf + MMCME2_ADV_X1Y2 MMCME2_ADV r clock_mmcm/CLKFBIN + ------------------------------------------------------------------- ------------------- + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: freq_refclk + To Clock: + +Max Delay 5 Endpoints +Min Delay 5 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + (clock source 'freq_refclk' {rise@0.000ns fall@0.750ns period=1.500ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i/CLKIN + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 0.647ns (logic 0.000ns (0.000%) route 0.647ns (100.000%)) + Logic Levels: 0 + Clock Uncertainty: 0.123ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.071ns + Phase Error (PE): 0.080ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock freq_refclk fall edge) + 0.750 0.750 f + E3 0.000 0.750 f CLK100MHZ (IN) + net (fo=0) 0.000 0.750 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 2.232 f input_clock/O + net (fo=1, routed) 1.233 3.465 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -3.605 f clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -1.886 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -1.790 f sys_buffer/O + net (fo=1, routed) 1.666 -0.124 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.088 -0.036 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.647 0.611 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/freq_refclk + PHASER_REF_X1Y1 PHASER_REF f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i/CLKIN + ------------------------------------------------------------------- ------------------- + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + (clock source 'freq_refclk' {rise@0.000ns fall@0.750ns period=1.500ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/FREQREFCLK + Path Group: (none) + Path Type: Min at Slow Process Corner + Data Path Delay: 0.572ns (logic 0.000ns (0.000%) route 0.572ns (100.000%)) + Logic Levels: 0 + Clock Uncertainty: 0.123ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.071ns + Phase Error (PE): 0.080ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock freq_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.572 -0.821 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/FREQREFCLK + ------------------------------------------------------------------- ------------------- + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: pll_clkfbout + To Clock: + +Max Delay 1 Endpoint +Min Delay 1 Endpoint +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT + (clock source 'pll_clkfbout' {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBIN + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 0.014ns (logic 0.000ns (0.000%) route 0.014ns (100.001%)) + Logic Levels: 0 + Clock Uncertainty: 0.120ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.062ns + Phase Error (PE): 0.080ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock pll_clkfbout fall edge) + 3.000 3.000 f + E3 0.000 3.000 f CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 4.482 f input_clock/O + net (fo=1, routed) 1.233 5.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -1.355 f clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 0.364 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 0.460 f sys_buffer/O + net (fo=1, routed) 1.666 2.126 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) + 0.088 2.214 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT + net (fo=1, routed) 0.014 2.228 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clkfbout + PLLE2_ADV_X1Y1 PLLE2_ADV f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBIN + ------------------------------------------------------------------- ------------------- + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT + (clock source 'pll_clkfbout' {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBIN + Path Group: (none) + Path Type: Min at Slow Process Corner + Data Path Delay: 0.013ns (logic 0.000ns (0.000%) route 0.013ns (100.000%)) + Logic Levels: 0 + Clock Uncertainty: 0.120ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.062ns + Phase Error (PE): 0.080ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock pll_clkfbout rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT + net (fo=1, routed) 0.013 -1.380 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clkfbout + PLLE2_ADV_X1Y1 PLLE2_ADV r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBIN + ------------------------------------------------------------------- ------------------- + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: ref_raw + To Clock: + +Max Delay 1 Endpoint +Min Delay 1 Endpoint +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: clock_mmcm/CLKOUT2 + (clock source 'ref_raw' {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/u_idelayctrl_200/REFCLK + Path Group: (none) + Path Type: Max at Fast Process Corner + Data Path Delay: 1.340ns (logic 0.029ns (2.164%) route 1.311ns (97.836%)) + Logic Levels: 1 (BUFG=1) + Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.099ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw fall edge) 2.500 2.500 f + E3 0.000 2.500 f CLK100MHZ (IN) + net (fo=0) 0.000 2.500 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 2.938 f input_clock/O + net (fo=1, routed) 0.480 3.418 clk_in + ------------------------------------------------------------------- ------------------- + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -3.163 0.255 f clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.544 0.798 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.827 f ref_buffer/O + net (fo=67, routed) 0.768 1.595 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/clk_ref_i + IDELAYCTRL_X1Y1 IDELAYCTRL f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/u_idelayctrl_200/REFCLK + ------------------------------------------------------------------- ------------------- + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: clock_mmcm/CLKOUT2 + (clock source 'ref_raw' {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/u_idelayctrl_200/REFCLK + Path Group: (none) + Path Type: Min at Slow Process Corner + Data Path Delay: 3.031ns (logic 0.091ns (3.003%) route 2.940ns (96.997%)) + Logic Levels: 1 (BUFG=1) + Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.099ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + ------------------------------------------------------------------- ------------------- + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.324 -4.751 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.639 -3.112 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.021 r ref_buffer/O + net (fo=67, routed) 1.300 -1.720 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/clk_ref_i + IDELAYCTRL_X1Y1 IDELAYCTRL r ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/u_idelayctrl_200/REFCLK + ------------------------------------------------------------------- ------------------- + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: + To Clock: clk_pll_i + +Max Delay 33 Endpoints +Min Delay 33 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/LOCKED + (internal pin) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__11/PRE + (recovery check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 6.581ns (logic 0.124ns (1.884%) route 6.457ns (98.116%)) + Logic Levels: 1 (LUT4=1) + Clock Uncertainty: 0.193ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.132ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + MMCME2_ADV_X1Y1 MMCME2_ADV 0.000 0.000 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/LOCKED + net (fo=3, routed) 1.943 1.943 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rstdiv2_sync_r_reg[11] + SLICE_X89Y75 LUT4 (Prop_lut4_I0_O) 0.124 2.067 f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rstdiv2_sync_r[11]_i_1/O + net (fo=32, routed) 4.514 6.581 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_tmp + SLICE_X51Y119 FDPE f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__11/PRE + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.487 0.659 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + SLICE_X51Y119 FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__11/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/PHASELOCKED + (internal pin) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/pi_phase_locked_all_r1_reg/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 0.723ns (logic 0.045ns (6.224%) route 0.678ns (93.776%)) + Logic Levels: 1 (LUT2=1) + Clock Uncertainty: 0.193ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.132ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY 0.000 0.000 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/PHASELOCKED + net (fo=1, routed) 0.317 0.317 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in_n_6 + SLICE_X89Y75 LUT2 (Prop_lut2_I0_O) 0.045 0.362 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/pi_phase_locked_all_inferred_i_1/O + net (fo=1, routed) 0.361 0.723 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/in0 + SLICE_X81Y69 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/pi_phase_locked_all_r1_reg/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.437 -0.348 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.043 -0.305 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.494 0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.400 -1.211 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.544 -0.668 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -0.639 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.862 0.223 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg[14]_0 + SLICE_X81Y69 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/pi_phase_locked_all_r1_reg/C + + + + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/routed-utilization.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/routed-utilization.rpt new file mode 100644 index 0000000..a543491 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/routed-utilization.rpt @@ -0,0 +1,264 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Mon Oct 12 20:36:07 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_utilization -file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/routed-utilization.rpt +| Design : toy_a7_top +| Device : xc7a100tcsg324-1 +| Speed File : -1 +| Design State : Routed +------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++----------------------------+-------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++----------------------------+-------+-------+------------+-----------+-------+ +| Slice LUTs | 53929 | 0 | 0 | 63400 | 85.06 | +| LUT as Logic | 50007 | 0 | 0 | 63400 | 78.88 | +| LUT as Memory | 3922 | 0 | 0 | 19000 | 20.64 | +| LUT as Distributed RAM | 3644 | 0 | | | | +| LUT as Shift Register | 278 | 0 | | | | +| Slice Registers | 33943 | 0 | 0 | 126800 | 26.77 | +| Register as Flip Flop | 33943 | 0 | 0 | 126800 | 26.77 | +| Register as Latch | 0 | 0 | 0 | 126800 | 0.00 | +| F7 Muxes | 689 | 0 | 0 | 31700 | 2.17 | +| F8 Muxes | 112 | 0 | 0 | 15850 | 0.71 | ++----------------------------+-------+-------+------------+-----------+-------+ +* Warning! LUT value is adjusted to account for LUT combining. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 163 | Yes | - | Set | +| 140 | Yes | - | Reset | +| 562 | Yes | Set | - | +| 33078 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++--------------------------------------------+-------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++--------------------------------------------+-------+-------+------------+-----------+-------+ +| Slice | 15579 | 0 | 0 | 15850 | 98.29 | +| SLICEL | 10888 | 0 | | | | +| SLICEM | 4691 | 0 | | | | +| LUT as Logic | 50007 | 0 | 0 | 63400 | 78.88 | +| using O5 output only | 31 | | | | | +| using O6 output only | 37318 | | | | | +| using O5 and O6 | 12658 | | | | | +| LUT as Memory | 3922 | 0 | 0 | 19000 | 20.64 | +| LUT as Distributed RAM | 3644 | 0 | | | | +| using O5 output only | 0 | | | | | +| using O6 output only | 260 | | | | | +| using O5 and O6 | 3384 | | | | | +| LUT as Shift Register | 278 | 0 | | | | +| using O5 output only | 17 | | | | | +| using O6 output only | 160 | | | | | +| using O5 and O6 | 101 | | | | | +| Slice Registers | 33943 | 0 | 0 | 126800 | 26.77 | +| Register driven from within the Slice | 15009 | | | | | +| Register driven from outside the Slice | 18934 | | | | | +| LUT in front of the register is unused | 4958 | | | | | +| LUT in front of the register is used | 13976 | | | | | +| Unique Control Sets | 1256 | | 0 | 15850 | 7.92 | ++--------------------------------------------+-------+-------+------------+-----------+-------+ +* * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++-------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------------+------+-------+------------+-----------+-------+ +| Block RAM Tile | 31 | 0 | 0 | 135 | 22.96 | +| RAMB36/FIFO* | 27 | 0 | 0 | 135 | 20.00 | +| RAMB36E1 only | 27 | | | | | +| RAMB18 | 8 | 0 | 0 | 270 | 2.96 | +| RAMB18E1 only | 8 | | | | | ++-------------------+------+-------+------------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++----------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++----------------+------+-------+------------+-----------+-------+ +| DSPs | 117 | 0 | 0 | 240 | 48.75 | +| DSP48E1 only | 117 | | | | | ++----------------+------+-------+------------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-----------------------------+------+-------+------------+-----------+-------+ +| Bonded IOB | 60 | 60 | 0 | 210 | 28.57 | +| IOB Master Pads | 29 | | | | | +| IOB Slave Pads | 28 | | | | | +| Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 | +| PHY_CONTROL | 1 | 1 | 0 | 6 | 16.67 | +| PHASER_REF | 1 | 1 | 0 | 6 | 16.67 | +| OUT_FIFO | 4 | 4 | 0 | 24 | 16.67 | +| IN_FIFO | 2 | 2 | 0 | 24 | 8.33 | +| IDELAYCTRL | 1 | 0 | 0 | 6 | 16.67 | +| IBUFDS | 0 | 0 | 0 | 202 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 4 | 4 | 0 | 24 | 16.67 | +| PHASER_OUT_PHY only | 4 | 4 | | | | +| PHASER_IN/PHASER_IN_PHY | 2 | 2 | 0 | 24 | 8.33 | +| PHASER_IN_PHY only | 2 | 2 | | | | +| IDELAYE2/IDELAYE2_FINEDELAY | 16 | 16 | 0 | 300 | 5.33 | +| IDELAYE2 only | 16 | 16 | | | | +| ILOGIC | 16 | 16 | 0 | 210 | 7.62 | +| ISERDES | 16 | 16 | 0 | 210 | | +| OLOGIC | 46 | 46 | 0 | 210 | 21.90 | +| OUTFF_ODDR_Register | 3 | 3 | | | | +| TFF_ODDR_Register | 2 | 2 | | | | +| OSERDES | 43 | 43 | 0 | 210 | | ++-----------------------------+------+-------+------------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++------------+------+-------+------------+-----------+-------+ +| BUFGCTRL | 5 | 0 | 0 | 32 | 15.63 | +| BUFIO | 0 | 0 | 0 | 24 | 0.00 | +| MMCME2_ADV | 2 | 1 | 0 | 6 | 33.33 | +| PLLE2_ADV | 1 | 1 | 0 | 6 | 16.67 | +| BUFMRCE | 0 | 0 | 0 | 12 | 0.00 | +| BUFHCE | 1 | 0 | 0 | 96 | 1.04 | +| BUFR | 0 | 0 | 0 | 24 | 0.00 | ++------------+------+-------+------------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+------------+-----------+--------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------+------+-------+------------+-----------+--------+ +| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 | +| XADC | 1 | 0 | 0 | 1 | 100.00 | ++-------------+------+-------+------------+-----------+--------+ + + +8. Primitives +------------- + ++--------------------------+-------+---------------------+ +| Ref Name | Used | Functional Category | ++--------------------------+-------+---------------------+ +| FDRE | 33078 | Flop & Latch | +| LUT6 | 20391 | LUT | +| LUT3 | 13504 | LUT | +| LUT5 | 12689 | LUT | +| LUT4 | 10385 | LUT | +| RAMD32 | 5100 | Distributed Memory | +| LUT2 | 4885 | LUT | +| CARRY4 | 2073 | CarryLogic | +| RAMS32 | 1774 | Distributed Memory | +| LUT1 | 811 | LUT | +| MUXF7 | 689 | MuxFx | +| FDSE | 562 | Flop & Latch | +| SRL16E | 246 | Distributed Memory | +| FDPE | 163 | Flop & Latch | +| FDCE | 140 | Flop & Latch | +| SRLC32E | 133 | Distributed Memory | +| DSP48E1 | 117 | Block Arithmetic | +| RAMD64E | 112 | Distributed Memory | +| MUXF8 | 112 | MuxFx | +| OSERDESE2 | 43 | IO | +| RAMS64E | 42 | Distributed Memory | +| OBUF | 33 | IO | +| RAMB36E1 | 27 | Block Memory | +| OBUFT | 18 | IO | +| ISERDESE2 | 16 | IO | +| IDELAYE2 | 16 | IO | +| IBUF_INTERMDISABLE | 16 | IO | +| RAMB18E1 | 8 | Block Memory | +| ODDR | 5 | IO | +| BUFG | 5 | Clock | +| PHASER_OUT_PHY | 4 | IO | +| OUT_FIFO | 4 | IO | +| OBUFTDS | 4 | IO | +| IBUFDS_INTERMDISABLE_INT | 4 | IO | +| INV | 3 | LUT | +| IBUF | 3 | IO | +| PHASER_IN_PHY | 2 | IO | +| OBUFDS | 2 | IO | +| MMCME2_ADV | 2 | Clock | +| IN_FIFO | 2 | IO | +| XADC | 1 | Others | +| PLLE2_ADV | 1 | Clock | +| PHY_CONTROL | 1 | IO | +| PHASER_REF | 1 | IO | +| IDELAYCTRL | 1 | IO | +| BUFH | 1 | Clock | ++--------------------------+-------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++-------------+------+ +| Ref Name | Used | ++-------------+------+ +| toy_axi_cdc | 1 | +| arty_ddr3 | 1 | ++-------------+------+ + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/synth-hierarchy.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/synth-hierarchy.rpt new file mode 100644 index 0000000..84b4c82 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/synth-hierarchy.rpt @@ -0,0 +1,1157 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Mon Oct 12 20:30:49 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_utilization -hierarchical -file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/synth-hierarchy.rpt +| Design : toy_a7_top +| Device : xc7a100tcsg324-1 +| Speed File : -1 +| Design State : Synthesized +------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + +Utilization Design Information + +Table of Contents +----------------- +1. Utilization by Hierarchy + +1. Utilization by Hierarchy +--------------------------- + ++----------------------------------------------------------------------------------------+-----------------------------------------------------------------+------------+------------+---------+------+-------+--------+--------+------------+ +| Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP Blocks | ++----------------------------------------------------------------------------------------+-----------------------------------------------------------------+------------+------------+---------+------+-------+--------+--------+------------+ +| toy_a7_top | (top) | 57555 | 53496 | 3680 | 379 | 34174 | 27 | 8 | 117 | +| (toy_a7_top) | (top) | 7 | 7 | 0 | 0 | 65 | 0 | 0 | 0 | +| ddr_controller | arty_ddr3 | 5052 | 4446 | 452 | 154 | 4193 | 0 | 0 | 0 | +| (ddr_controller) | arty_ddr3 | 216 | 0 | 216 | 0 | 0 | 0 | 0 | 0 | +| u_arty_ddr3_mig | arty_ddr3_mig | 4836 | 4446 | 236 | 154 | 4193 | 0 | 0 | 0 | +| temp_mon_enabled.u_tempmon | arty_ddr3mig_7series_v4_2_tempmon | 39 | 39 | 0 | 0 | 122 | 0 | 0 | 0 | +| u_ddr3_clk_ibuf | arty_ddr3mig_7series_v4_2_clk_ibuf | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| u_ddr3_infrastructure | arty_ddr3mig_7series_v4_2_infrastructure | 27 | 27 | 0 | 0 | 58 | 0 | 0 | 0 | +| u_iodelay_ctrl | arty_ddr3mig_7series_v4_2_iodelay_ctrl | 2 | 2 | 0 | 0 | 15 | 0 | 0 | 0 | +| u_memc_ui_top_axi | arty_ddr3mig_7series_v4_2_memc_ui_top_axi | 4768 | 4378 | 236 | 154 | 3998 | 0 | 0 | 0 | +| (u_memc_ui_top_axi) | arty_ddr3mig_7series_v4_2_memc_ui_top_axi | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem_intfc0 | arty_ddr3mig_7series_v4_2_mem_intfc | 3681 | 3624 | 40 | 17 | 2902 | 0 | 0 | 0 | +| ddr_phy_top0 | arty_ddr3mig_7series_v4_2_ddr_phy_top | 3047 | 2999 | 32 | 16 | 2370 | 0 | 0 | 0 | +| (ddr_phy_top0) | arty_ddr3mig_7series_v4_2_ddr_phy_top | 3 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | +| u_ddr_calib_top | arty_ddr3mig_7series_v4_2_ddr_calib_top | 2376 | 2362 | 0 | 14 | 1986 | 0 | 0 | 0 | +| (u_ddr_calib_top) | arty_ddr3mig_7series_v4_2_ddr_calib_top | 107 | 106 | 0 | 1 | 29 | 0 | 0 | 0 | +| ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl | arty_ddr3mig_7series_v4_2_ddr_phy_rdlvl | 543 | 543 | 0 | 0 | 872 | 0 | 0 | 0 | +| ddr_phy_tempmon_0 | arty_ddr3mig_7series_v4_2_ddr_phy_tempmon | 258 | 258 | 0 | 0 | 229 | 0 | 0 | 0 | +| dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr | arty_ddr3mig_7series_v4_2_ddr_phy_dqs_found_cal_hr | 150 | 149 | 0 | 1 | 97 | 0 | 0 | 0 | +| mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay | arty_ddr3mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay | 17 | 16 | 0 | 1 | 16 | 0 | 0 | 0 | +| mb_wrlvl_inst.u_ddr_phy_wrlvl | arty_ddr3mig_7series_v4_2_ddr_phy_wrlvl | 266 | 265 | 0 | 1 | 160 | 0 | 0 | 0 | +| u_ddr_phy_init | arty_ddr3mig_7series_v4_2_ddr_phy_init | 872 | 868 | 0 | 4 | 279 | 0 | 0 | 0 | +| u_ddr_phy_wrcal | arty_ddr3mig_7series_v4_2_ddr_phy_wrcal | 163 | 157 | 0 | 6 | 304 | 0 | 0 | 0 | +| u_ddr_mc_phy_wrapper | arty_ddr3mig_7series_v4_2_ddr_mc_phy_wrapper | 668 | 634 | 32 | 2 | 384 | 0 | 0 | 0 | +| (u_ddr_mc_phy_wrapper) | arty_ddr3mig_7series_v4_2_ddr_mc_phy_wrapper | 0 | 0 | 0 | 0 | 24 | 0 | 0 | 0 | +| genblk24.phy_ctl_pre_fifo_0 | arty_ddr3mig_7series_v4_2_ddr_of_pre_fifo | 33 | 33 | 0 | 0 | 21 | 0 | 0 | 0 | +| genblk24.phy_ctl_pre_fifo_1 | arty_ddr3mig_7series_v4_2_ddr_of_pre_fifo__parameterized0 | 33 | 33 | 0 | 0 | 21 | 0 | 0 | 0 | +| genblk24.phy_ctl_pre_fifo_2 | arty_ddr3mig_7series_v4_2_ddr_of_pre_fifo__parameterized0_9 | 33 | 33 | 0 | 0 | 21 | 0 | 0 | 0 | +| u_ddr_mc_phy | arty_ddr3mig_7series_v4_2_ddr_mc_phy | 569 | 535 | 32 | 2 | 297 | 0 | 0 | 0 | +| (u_ddr_mc_phy) | arty_ddr3mig_7series_v4_2_ddr_mc_phy | 0 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | +| ddr_phy_4lanes_0.u_ddr_phy_4lanes | arty_ddr3mig_7series_v4_2_ddr_phy_4lanes | 569 | 535 | 32 | 2 | 281 | 0 | 0 | 0 | +| (ddr_phy_4lanes_0.u_ddr_phy_4lanes) | arty_ddr3mig_7series_v4_2_ddr_phy_4lanes | 10 | 9 | 0 | 1 | 20 | 0 | 0 | 0 | +| ddr_byte_lane_A.ddr_byte_lane_A | arty_ddr3mig_7series_v4_2_ddr_byte_lane | 55 | 23 | 32 | 0 | 20 | 0 | 0 | 0 | +| (ddr_byte_lane_A.ddr_byte_lane_A) | arty_ddr3mig_7series_v4_2_ddr_byte_lane | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | +| ddr_byte_group_io | arty_ddr3mig_7series_v4_2_ddr_byte_group_io | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| of_pre_fifo_gen.u_ddr_of_pre_fifo | arty_ddr3mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_14 | 54 | 22 | 32 | 0 | 19 | 0 | 0 | 0 | +| ddr_byte_lane_B.ddr_byte_lane_B | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized0 | 25 | 25 | 0 | 0 | 19 | 0 | 0 | 0 | +| (ddr_byte_lane_B.ddr_byte_lane_B) | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized0 | 9 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | +| ddr_byte_group_io | arty_ddr3mig_7series_v4_2_ddr_byte_group_io__parameterized0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| of_pre_fifo_gen.u_ddr_of_pre_fifo | arty_ddr3mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_13 | 16 | 16 | 0 | 0 | 19 | 0 | 0 | 0 | +| ddr_byte_lane_C.ddr_byte_lane_C | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized1 | 241 | 241 | 0 | 0 | 111 | 0 | 0 | 0 | +| (ddr_byte_lane_C.ddr_byte_lane_C) | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized1 | 7 | 7 | 0 | 0 | 69 | 0 | 0 | 0 | +| ddr_byte_group_io | arty_ddr3mig_7series_v4_2_ddr_byte_group_io__parameterized1_10 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo | arty_ddr3mig_7series_v4_2_ddr_if_post_fifo_11 | 212 | 212 | 0 | 0 | 17 | 0 | 0 | 0 | +| of_pre_fifo_gen.u_ddr_of_pre_fifo | arty_ddr3mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_12 | 22 | 22 | 0 | 0 | 24 | 0 | 0 | 0 | +| ddr_byte_lane_D.ddr_byte_lane_D | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized2 | 238 | 237 | 0 | 1 | 111 | 0 | 0 | 0 | +| (ddr_byte_lane_D.ddr_byte_lane_D) | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized2 | 0 | 0 | 0 | 0 | 69 | 0 | 0 | 0 | +| ddr_byte_group_io | arty_ddr3mig_7series_v4_2_ddr_byte_group_io__parameterized1 | 2 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | +| dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo | arty_ddr3mig_7series_v4_2_ddr_if_post_fifo | 215 | 215 | 0 | 0 | 17 | 0 | 0 | 0 | +| of_pre_fifo_gen.u_ddr_of_pre_fifo | arty_ddr3mig_7series_v4_2_ddr_of_pre_fifo__parameterized1 | 21 | 21 | 0 | 0 | 24 | 0 | 0 | 0 | +| mc0 | arty_ddr3mig_7series_v4_2_mc | 634 | 625 | 8 | 1 | 532 | 0 | 0 | 0 | +| (mc0) | arty_ddr3mig_7series_v4_2_mc | 8 | 8 | 0 | 0 | 73 | 0 | 0 | 0 | +| bank_mach0 | arty_ddr3mig_7series_v4_2_bank_mach | 508 | 508 | 0 | 0 | 362 | 0 | 0 | 0 | +| arb_mux0 | arty_ddr3mig_7series_v4_2_arb_mux | 197 | 197 | 0 | 0 | 45 | 0 | 0 | 0 | +| arb_row_col0 | arty_ddr3mig_7series_v4_2_arb_row_col | 197 | 197 | 0 | 0 | 40 | 0 | 0 | 0 | +| (arb_row_col0) | arty_ddr3mig_7series_v4_2_arb_row_col | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | +| col_arb0 | arty_ddr3mig_7series_v4_2_round_robin_arb__parameterized1 | 66 | 66 | 0 | 0 | 8 | 0 | 0 | 0 | +| config_arb0 | arty_ddr3mig_7series_v4_2_round_robin_arb__parameterized1_6 | 17 | 17 | 0 | 0 | 8 | 0 | 0 | 0 | +| pre_4_1_1T_arb.pre_arb0 | arty_ddr3mig_7series_v4_2_round_robin_arb__parameterized1_7 | 47 | 47 | 0 | 0 | 8 | 0 | 0 | 0 | +| row_arb0 | arty_ddr3mig_7series_v4_2_round_robin_arb__parameterized1_8 | 65 | 65 | 0 | 0 | 8 | 0 | 0 | 0 | +| arb_select0 | arty_ddr3mig_7series_v4_2_arb_select | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| bank_cntrl[0].bank0 | arty_ddr3mig_7series_v4_2_bank_cntrl | 72 | 72 | 0 | 0 | 75 | 0 | 0 | 0 | +| bank_compare0 | arty_ddr3mig_7series_v4_2_bank_compare_5 | 8 | 8 | 0 | 0 | 35 | 0 | 0 | 0 | +| bank_queue0 | arty_ddr3mig_7series_v4_2_bank_queue | 41 | 41 | 0 | 0 | 18 | 0 | 0 | 0 | +| bank_state0 | arty_ddr3mig_7series_v4_2_bank_state | 23 | 23 | 0 | 0 | 22 | 0 | 0 | 0 | +| bank_cntrl[1].bank0 | arty_ddr3mig_7series_v4_2_bank_cntrl__parameterized0 | 70 | 70 | 0 | 0 | 73 | 0 | 0 | 0 | +| bank_compare0 | arty_ddr3mig_7series_v4_2_bank_compare_4 | 13 | 13 | 0 | 0 | 35 | 0 | 0 | 0 | +| bank_queue0 | arty_ddr3mig_7series_v4_2_bank_queue__parameterized0 | 36 | 36 | 0 | 0 | 18 | 0 | 0 | 0 | +| bank_state0 | arty_ddr3mig_7series_v4_2_bank_state__parameterized0 | 21 | 21 | 0 | 0 | 20 | 0 | 0 | 0 | +| bank_cntrl[2].bank0 | arty_ddr3mig_7series_v4_2_bank_cntrl__parameterized1 | 71 | 71 | 0 | 0 | 74 | 0 | 0 | 0 | +| bank_compare0 | arty_ddr3mig_7series_v4_2_bank_compare_3 | 10 | 10 | 0 | 0 | 35 | 0 | 0 | 0 | +| bank_queue0 | arty_ddr3mig_7series_v4_2_bank_queue__parameterized1 | 33 | 33 | 0 | 0 | 18 | 0 | 0 | 0 | +| bank_state0 | arty_ddr3mig_7series_v4_2_bank_state__parameterized1 | 28 | 28 | 0 | 0 | 21 | 0 | 0 | 0 | +| bank_cntrl[3].bank0 | arty_ddr3mig_7series_v4_2_bank_cntrl__parameterized2 | 72 | 72 | 0 | 0 | 73 | 0 | 0 | 0 | +| bank_compare0 | arty_ddr3mig_7series_v4_2_bank_compare | 14 | 14 | 0 | 0 | 35 | 0 | 0 | 0 | +| bank_queue0 | arty_ddr3mig_7series_v4_2_bank_queue__parameterized2 | 33 | 33 | 0 | 0 | 18 | 0 | 0 | 0 | +| bank_state0 | arty_ddr3mig_7series_v4_2_bank_state__parameterized2 | 25 | 25 | 0 | 0 | 20 | 0 | 0 | 0 | +| bank_common0 | arty_ddr3mig_7series_v4_2_bank_common | 26 | 26 | 0 | 0 | 22 | 0 | 0 | 0 | +| col_mach0 | arty_ddr3mig_7series_v4_2_col_mach | 27 | 19 | 8 | 0 | 26 | 0 | 0 | 0 | +| rank_mach0 | arty_ddr3mig_7series_v4_2_rank_mach | 91 | 90 | 0 | 1 | 71 | 0 | 0 | 0 | +| rank_cntrl[0].rank_cntrl0 | arty_ddr3mig_7series_v4_2_rank_cntrl | 11 | 10 | 0 | 1 | 13 | 0 | 0 | 0 | +| rank_common0 | arty_ddr3mig_7series_v4_2_rank_common | 80 | 80 | 0 | 0 | 58 | 0 | 0 | 0 | +| (rank_common0) | arty_ddr3mig_7series_v4_2_rank_common | 67 | 67 | 0 | 0 | 52 | 0 | 0 | 0 | +| maintenance_request.maint_arb0 | arty_ddr3mig_7series_v4_2_round_robin_arb | 13 | 13 | 0 | 0 | 6 | 0 | 0 | 0 | +| u_axi_mc | arty_ddr3mig_7series_v4_2_axi_mc | 615 | 478 | 0 | 137 | 544 | 0 | 0 | 0 | +| (u_axi_mc) | arty_ddr3mig_7series_v4_2_axi_mc | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| axi_mc_ar_channel_0 | arty_ddr3mig_7series_v4_2_axi_mc_ar_channel | 129 | 129 | 0 | 0 | 93 | 0 | 0 | 0 | +| (axi_mc_ar_channel_0) | arty_ddr3mig_7series_v4_2_axi_mc_ar_channel | 1 | 1 | 0 | 0 | 48 | 0 | 0 | 0 | +| ar_cmd_fsm_0 | arty_ddr3mig_7series_v4_2_axi_mc_cmd_fsm | 83 | 83 | 0 | 0 | 1 | 0 | 0 | 0 | +| axi_mc_cmd_translator_0 | arty_ddr3mig_7series_v4_2_axi_mc_cmd_translator_0 | 46 | 46 | 0 | 0 | 44 | 0 | 0 | 0 | +| axi_mc_incr_cmd_0 | arty_ddr3mig_7series_v4_2_axi_mc_incr_cmd_1 | 38 | 38 | 0 | 0 | 36 | 0 | 0 | 0 | +| axi_mc_wrap_cmd_0 | arty_ddr3mig_7series_v4_2_axi_mc_wrap_cmd_2 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| axi_mc_aw_channel_0 | arty_ddr3mig_7series_v4_2_axi_mc_aw_channel | 132 | 132 | 0 | 0 | 91 | 0 | 0 | 0 | +| (axi_mc_aw_channel_0) | arty_ddr3mig_7series_v4_2_axi_mc_aw_channel | 0 | 0 | 0 | 0 | 46 | 0 | 0 | 0 | +| aw_cmd_fsm_0 | arty_ddr3mig_7series_v4_2_axi_mc_wr_cmd_fsm | 82 | 82 | 0 | 0 | 1 | 0 | 0 | 0 | +| axi_mc_cmd_translator_0 | arty_ddr3mig_7series_v4_2_axi_mc_cmd_translator | 51 | 51 | 0 | 0 | 44 | 0 | 0 | 0 | +| axi_mc_incr_cmd_0 | arty_ddr3mig_7series_v4_2_axi_mc_incr_cmd | 43 | 43 | 0 | 0 | 36 | 0 | 0 | 0 | +| axi_mc_wrap_cmd_0 | arty_ddr3mig_7series_v4_2_axi_mc_wrap_cmd | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| axi_mc_b_channel_0 | arty_ddr3mig_7series_v4_2_axi_mc_b_channel | 12 | 8 | 0 | 4 | 9 | 0 | 0 | 0 | +| (axi_mc_b_channel_0) | arty_ddr3mig_7series_v4_2_axi_mc_b_channel | 1 | 1 | 0 | 0 | 5 | 0 | 0 | 0 | +| bid_fifo_0 | arty_ddr3mig_7series_v4_2_axi_mc_fifo | 11 | 7 | 0 | 4 | 4 | 0 | 0 | 0 | +| axi_mc_cmd_arbiter_0 | arty_ddr3mig_7series_v4_2_axi_mc_cmd_arbiter | 34 | 34 | 0 | 0 | 31 | 0 | 0 | 0 | +| axi_mc_r_channel_0 | arty_ddr3mig_7series_v4_2_axi_mc_r_channel | 160 | 27 | 0 | 133 | 24 | 0 | 0 | 0 | +| (axi_mc_r_channel_0) | arty_ddr3mig_7series_v4_2_axi_mc_r_channel | 0 | 0 | 0 | 0 | 12 | 0 | 0 | 0 | +| rd_data_fifo_0 | arty_ddr3mig_7series_v4_2_axi_mc_fifo__parameterized0 | 141 | 13 | 0 | 128 | 6 | 0 | 0 | 0 | +| transaction_fifo_0 | arty_ddr3mig_7series_v4_2_axi_mc_fifo__parameterized1 | 19 | 14 | 0 | 5 | 6 | 0 | 0 | 0 | +| axi_mc_w_channel_0 | arty_ddr3mig_7series_v4_2_axi_mc_w_channel | 147 | 147 | 0 | 0 | 294 | 0 | 0 | 0 | +| u_ui_top | arty_ddr3mig_7series_v4_2_ui_top | 472 | 276 | 196 | 0 | 550 | 0 | 0 | 0 | +| ui_cmd0 | arty_ddr3mig_7series_v4_2_ui_cmd | 38 | 38 | 0 | 0 | 54 | 0 | 0 | 0 | +| ui_rd_data0 | arty_ddr3mig_7series_v4_2_ui_rd_data | 124 | 32 | 92 | 0 | 163 | 0 | 0 | 0 | +| ui_wr_data0 | arty_ddr3mig_7series_v4_2_ui_wr_data | 310 | 206 | 104 | 0 | 333 | 0 | 0 | 0 | +| memory_cdc | toy_axi_cdc | 530 | 252 | 278 | 0 | 1326 | 0 | 0 | 0 | +| (memory_cdc) | toy_axi_cdc | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| inst | toy_axi_cdcaxi_clock_converter_v2_1_30_axi_clock_converter | 530 | 252 | 278 | 0 | 1326 | 0 | 0 | 0 | +| (inst) | toy_axi_cdcaxi_clock_converter_v2_1_30_axi_clock_converter | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | +| gen_clock_conv.gen_async_conv.asyncfifo_axi | toy_axi_cdcfifo_generator_v13_2_10 | 529 | 251 | 278 | 0 | 1326 | 0 | 0 | 0 | +| (gen_clock_conv.gen_async_conv.asyncfifo_axi) | toy_axi_cdcfifo_generator_v13_2_10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| inst_fifo_gen | toy_axi_cdcfifo_generator_v13_2_10_synth | 529 | 251 | 278 | 0 | 1326 | 0 | 0 | 0 | +| gaxi_full_lite.gread_ch.grach2.axi_rach | toy_axi_cdcfifo_generator_top | 92 | 50 | 42 | 0 | 221 | 0 | 0 | 0 | +| grf.rf | toy_axi_cdcfifo_generator_ramfifo | 92 | 50 | 42 | 0 | 221 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gcx.clkx | toy_axi_cdcclk_x_pntrs__xdcDup__4 | 12 | 12 | 0 | 0 | 40 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.gcx.clkx) | toy_axi_cdcclk_x_pntrs__xdcDup__4 | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | +| rd_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__17 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| wr_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__16 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.rd | toy_axi_cdcrd_logic_21 | 15 | 15 | 0 | 0 | 18 | 0 | 0 | 0 | +| gr1.gr1_int.rfwft | toy_axi_cdcrd_fwft_27 | 9 | 9 | 0 | 0 | 8 | 0 | 0 | 0 | +| gras.rsts | toy_axi_cdcrd_status_flags_as_28 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpntr | toy_axi_cdcrd_bin_cntr_29 | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.wr | toy_axi_cdcwr_logic_22 | 8 | 8 | 0 | 0 | 14 | 0 | 0 | 0 | +| gwas.wsts | toy_axi_cdcwr_status_flags_as_25 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | +| wpntr | toy_axi_cdcwr_bin_cntr_26 | 5 | 5 | 0 | 0 | 12 | 0 | 0 | 0 | +| gntv_or_sync_fifo.mem | toy_axi_cdcmemory_23 | 42 | 0 | 42 | 0 | 122 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.mem) | toy_axi_cdcmemory_23 | 0 | 0 | 0 | 0 | 61 | 0 | 0 | 0 | +| gdm.dm_gen.dm | toy_axi_cdcdmem_24 | 42 | 0 | 42 | 0 | 61 | 0 | 0 | 0 | +| rstblk | toy_axi_cdcreset_blk_ramfifo__xdcDup__4 | 15 | 15 | 0 | 0 | 27 | 0 | 0 | 0 | +| (rstblk) | toy_axi_cdcreset_blk_ramfifo__xdcDup__4 | 15 | 15 | 0 | 0 | 13 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__12 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | toy_axi_cdcxpm_cdc_single__parameterized1__17 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | toy_axi_cdcxpm_cdc_single__parameterized1__16 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__11 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gaxi_full_lite.gread_ch.grach2.cdc_wr_rst_busy_ic_3.xpm_cdc_single_inst3 | toy_axi_cdcxpm_cdc_single | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| gaxi_full_lite.gread_ch.grdch2.axi_rdch | toy_axi_cdcfifo_generator_top__parameterized2 | 143 | 51 | 92 | 0 | 369 | 0 | 0 | 0 | +| grf.rf | toy_axi_cdcfifo_generator_ramfifo__parameterized2 | 143 | 51 | 92 | 0 | 369 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gcx.clkx | toy_axi_cdcclk_x_pntrs | 12 | 12 | 0 | 0 | 40 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.gcx.clkx) | toy_axi_cdcclk_x_pntrs | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | +| rd_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| wr_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__18 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.rd | toy_axi_cdcrd_logic_14 | 15 | 15 | 0 | 0 | 18 | 0 | 0 | 0 | +| gr1.gr1_int.rfwft | toy_axi_cdcrd_fwft_18 | 9 | 9 | 0 | 0 | 8 | 0 | 0 | 0 | +| gras.rsts | toy_axi_cdcrd_status_flags_as_19 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpntr | toy_axi_cdcrd_bin_cntr_20 | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.wr | toy_axi_cdcwr_logic_15 | 8 | 8 | 0 | 0 | 14 | 0 | 0 | 0 | +| gwas.wsts | toy_axi_cdcwr_status_flags_as_16 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | +| wpntr | toy_axi_cdcwr_bin_cntr_17 | 5 | 5 | 0 | 0 | 12 | 0 | 0 | 0 | +| gntv_or_sync_fifo.mem | toy_axi_cdcmemory__parameterized2 | 92 | 0 | 92 | 0 | 270 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.mem) | toy_axi_cdcmemory__parameterized2 | 0 | 0 | 0 | 0 | 135 | 0 | 0 | 0 | +| gdm.dm_gen.dm | toy_axi_cdcdmem__parameterized2 | 92 | 0 | 92 | 0 | 135 | 0 | 0 | 0 | +| rstblk | toy_axi_cdcreset_blk_ramfifo | 16 | 16 | 0 | 0 | 27 | 0 | 0 | 0 | +| (rstblk) | toy_axi_cdcreset_blk_ramfifo | 16 | 16 | 0 | 0 | 13 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | toy_axi_cdcxpm_cdc_async_rst | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | toy_axi_cdcxpm_cdc_single__parameterized1 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | toy_axi_cdcxpm_cdc_single__parameterized1__18 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__13 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gaxi_full_lite.gwrite_ch.gwach2.axi_wach | toy_axi_cdcfifo_generator_top__xdcDup__1 | 92 | 50 | 42 | 0 | 221 | 0 | 0 | 0 | +| grf.rf | toy_axi_cdcfifo_generator_ramfifo__xdcDup__1 | 92 | 50 | 42 | 0 | 221 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gcx.clkx | toy_axi_cdcclk_x_pntrs__xdcDup__1 | 12 | 12 | 0 | 0 | 40 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.gcx.clkx) | toy_axi_cdcclk_x_pntrs__xdcDup__1 | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | +| rd_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__11 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| wr_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__10 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.rd | toy_axi_cdcrd_logic_7 | 15 | 15 | 0 | 0 | 18 | 0 | 0 | 0 | +| gr1.gr1_int.rfwft | toy_axi_cdcrd_fwft_11 | 9 | 9 | 0 | 0 | 8 | 0 | 0 | 0 | +| gras.rsts | toy_axi_cdcrd_status_flags_as_12 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpntr | toy_axi_cdcrd_bin_cntr_13 | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.wr | toy_axi_cdcwr_logic_8 | 8 | 8 | 0 | 0 | 14 | 0 | 0 | 0 | +| gwas.wsts | toy_axi_cdcwr_status_flags_as_9 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | +| wpntr | toy_axi_cdcwr_bin_cntr_10 | 5 | 5 | 0 | 0 | 12 | 0 | 0 | 0 | +| gntv_or_sync_fifo.mem | toy_axi_cdcmemory | 42 | 0 | 42 | 0 | 122 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.mem) | toy_axi_cdcmemory | 0 | 0 | 0 | 0 | 61 | 0 | 0 | 0 | +| gdm.dm_gen.dm | toy_axi_cdcdmem | 42 | 0 | 42 | 0 | 61 | 0 | 0 | 0 | +| rstblk | toy_axi_cdcreset_blk_ramfifo__xdcDup__1 | 15 | 15 | 0 | 0 | 27 | 0 | 0 | 0 | +| (rstblk) | toy_axi_cdcreset_blk_ramfifo__xdcDup__1 | 15 | 15 | 0 | 0 | 13 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__6 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | toy_axi_cdcxpm_cdc_single__parameterized1__11 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | toy_axi_cdcxpm_cdc_single__parameterized1__10 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__5 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gaxi_full_lite.gwrite_ch.gwach2.cdc_wr_rst_busy_ic_1.xpm_cdc_single_inst1 | toy_axi_cdcxpm_cdc_single__3 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch | toy_axi_cdcfifo_generator_top__parameterized0 | 148 | 50 | 98 | 0 | 389 | 0 | 0 | 0 | +| grf.rf | toy_axi_cdcfifo_generator_ramfifo__parameterized0 | 148 | 50 | 98 | 0 | 389 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gcx.clkx | toy_axi_cdcclk_x_pntrs__xdcDup__2 | 12 | 12 | 0 | 0 | 40 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.gcx.clkx) | toy_axi_cdcclk_x_pntrs__xdcDup__2 | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | +| rd_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__13 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| wr_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__12 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.rd | toy_axi_cdcrd_logic_0 | 15 | 15 | 0 | 0 | 18 | 0 | 0 | 0 | +| gr1.gr1_int.rfwft | toy_axi_cdcrd_fwft_4 | 9 | 9 | 0 | 0 | 8 | 0 | 0 | 0 | +| gras.rsts | toy_axi_cdcrd_status_flags_as_5 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpntr | toy_axi_cdcrd_bin_cntr_6 | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.wr | toy_axi_cdcwr_logic_1 | 8 | 8 | 0 | 0 | 14 | 0 | 0 | 0 | +| gwas.wsts | toy_axi_cdcwr_status_flags_as_2 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | +| wpntr | toy_axi_cdcwr_bin_cntr_3 | 5 | 5 | 0 | 0 | 12 | 0 | 0 | 0 | +| gntv_or_sync_fifo.mem | toy_axi_cdcmemory__parameterized0 | 98 | 0 | 98 | 0 | 290 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.mem) | toy_axi_cdcmemory__parameterized0 | 0 | 0 | 0 | 0 | 145 | 0 | 0 | 0 | +| gdm.dm_gen.dm | toy_axi_cdcdmem__parameterized0 | 98 | 0 | 98 | 0 | 145 | 0 | 0 | 0 | +| rstblk | toy_axi_cdcreset_blk_ramfifo__xdcDup__2 | 15 | 15 | 0 | 0 | 27 | 0 | 0 | 0 | +| (rstblk) | toy_axi_cdcreset_blk_ramfifo__xdcDup__2 | 15 | 15 | 0 | 0 | 13 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__8 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | toy_axi_cdcxpm_cdc_single__parameterized1__13 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | toy_axi_cdcxpm_cdc_single__parameterized1__12 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__7 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gaxi_full_lite.gwrite_ch.gwdch2.cdc_wr_rst_busy_ic_2.xpm_cdc_single_inst2 | toy_axi_cdcxpm_cdc_single__4 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch | toy_axi_cdcfifo_generator_top__parameterized1 | 54 | 50 | 4 | 0 | 111 | 0 | 0 | 0 | +| grf.rf | toy_axi_cdcfifo_generator_ramfifo__parameterized1 | 54 | 50 | 4 | 0 | 111 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gcx.clkx | toy_axi_cdcclk_x_pntrs__xdcDup__3 | 12 | 12 | 0 | 0 | 40 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.gcx.clkx) | toy_axi_cdcclk_x_pntrs__xdcDup__3 | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | +| rd_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__15 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| wr_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__14 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.rd | toy_axi_cdcrd_logic | 15 | 15 | 0 | 0 | 18 | 0 | 0 | 0 | +| gr1.gr1_int.rfwft | toy_axi_cdcrd_fwft | 9 | 9 | 0 | 0 | 8 | 0 | 0 | 0 | +| gras.rsts | toy_axi_cdcrd_status_flags_as | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpntr | toy_axi_cdcrd_bin_cntr | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.wr | toy_axi_cdcwr_logic | 8 | 8 | 0 | 0 | 14 | 0 | 0 | 0 | +| gwas.wsts | toy_axi_cdcwr_status_flags_as | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | +| wpntr | toy_axi_cdcwr_bin_cntr | 5 | 5 | 0 | 0 | 12 | 0 | 0 | 0 | +| gntv_or_sync_fifo.mem | toy_axi_cdcmemory__parameterized1 | 4 | 0 | 4 | 0 | 12 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.mem) | toy_axi_cdcmemory__parameterized1 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | +| gdm.dm_gen.dm | toy_axi_cdcdmem__parameterized1 | 4 | 0 | 4 | 0 | 6 | 0 | 0 | 0 | +| rstblk | toy_axi_cdcreset_blk_ramfifo__xdcDup__3 | 15 | 15 | 0 | 0 | 27 | 0 | 0 | 0 | +| (rstblk) | toy_axi_cdcreset_blk_ramfifo__xdcDup__3 | 15 | 15 | 0 | 0 | 13 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__10 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | toy_axi_cdcxpm_cdc_single__parameterized1__15 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | toy_axi_cdcxpm_cdc_single__parameterized1__14 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__9 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| platform | toy_a7_platform | 51966 | 48791 | 2950 | 225 | 28590 | 27 | 8 | 117 | +| chip | ToyLinuxChip | 50944 | 47881 | 2838 | 225 | 27538 | 27 | 8 | 117 | +| system | ToyLinuxSystem | 50944 | 47881 | 2838 | 225 | 27538 | 27 | 8 | 117 | +| (system) | ToyLinuxSystem | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | +| bootrom_domain | bootromClockSinkDomain | 462 | 462 | 0 | 0 | 0 | 0 | 0 | 0 | +| bootrom | TLROM | 462 | 462 | 0 | 0 | 0 | 0 | 0 | 0 | +| cbus | PeripheryBus_cbus | 1023 | 869 | 154 | 0 | 364 | 0 | 0 | 0 | +| atomics | TLAtomicAutomata_cbus | 407 | 407 | 0 | 0 | 203 | 0 | 0 | 0 | +| buffer | TLBuffer_a28d64s3k1z4u | 263 | 133 | 130 | 0 | 6 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a28d64s3k1z4u | 111 | 57 | 54 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q) | Queue2_TLBundleD_a28d64s3k1z4u | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x79_445 | 107 | 53 | 54 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a28d64s3k1z4u | 152 | 76 | 76 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a28d64s3k1z4u | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x114 | 151 | 75 | 76 | 0 | 0 | 0 | 0 | 0 | +| coupler_to_bootrom | TLInterconnectCoupler_cbus_to_bootrom | 85 | 85 | 0 | 0 | 29 | 0 | 0 | 0 | +| fragmenter | TLFragmenter_bootrom | 85 | 85 | 0 | 0 | 29 | 0 | 0 | 0 | +| (fragmenter) | TLFragmenter_bootrom | 1 | 1 | 0 | 0 | 9 | 0 | 0 | 0 | +| repeater | Repeater_TLBundleA_a17d64s3k1z3u | 84 | 84 | 0 | 0 | 20 | 0 | 0 | 0 | +| coupler_to_clint | TLInterconnectCoupler_cbus_to_clint | 79 | 79 | 0 | 0 | 32 | 0 | 0 | 0 | +| fragmenter | TLFragmenter_CLINT | 79 | 79 | 0 | 0 | 32 | 0 | 0 | 0 | +| (fragmenter) | TLFragmenter_CLINT | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | +| repeater | Repeater_TLBundleA_a26d64s3k1z3u | 79 | 79 | 0 | 0 | 23 | 0 | 0 | 0 | +| coupler_to_plic | TLInterconnectCoupler_cbus_to_plic | 24 | 24 | 0 | 0 | 42 | 0 | 0 | 0 | +| fragmenter | TLFragmenter_PLIC | 24 | 24 | 0 | 0 | 42 | 0 | 0 | 0 | +| (fragmenter) | TLFragmenter_PLIC | 3 | 3 | 0 | 0 | 9 | 0 | 0 | 0 | +| repeater | Repeater_TLBundleA_a28d64s3k1z3u | 21 | 21 | 0 | 0 | 33 | 0 | 0 | 0 | +| out_xbar | TLXbar_cbus_out_i1_o4_a28d64s3k1z4u | 83 | 83 | 0 | 0 | 17 | 0 | 0 | 0 | +| wrapped_error_device | ErrorDeviceWrapper | 82 | 58 | 24 | 0 | 35 | 0 | 0 | 0 | +| buffer | TLBuffer_a14d64s3k1z4u | 44 | 20 | 24 | 0 | 6 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a14d64s3k1z4u | 29 | 17 | 12 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q) | Queue2_TLBundleD_a14d64s3k1z4u | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x79 | 25 | 13 | 12 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a14d64s3k1z4u | 15 | 3 | 12 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a14d64s3k1z4u | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x100 | 13 | 1 | 12 | 0 | 0 | 0 | 0 | 0 | +| error | TLError | 38 | 38 | 0 | 0 | 29 | 0 | 0 | 0 | +| (error) | TLError | 7 | 7 | 0 | 0 | 18 | 0 | 0 | 0 | +| a_q | Queue1_TLBundleA_a14d64s3k1z4u | 31 | 31 | 0 | 0 | 11 | 0 | 0 | 0 | +| clint_domain | CLINTClockSinkDomain | 70 | 70 | 0 | 0 | 131 | 0 | 0 | 0 | +| clint | CLINT | 70 | 70 | 0 | 0 | 129 | 0 | 0 | 0 | +| intsource | IntSyncCrossingSource_n1x2 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| reg_0 | AsyncResetRegVec_w2_i0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| coh_wrapper | CoherenceManagerWrapper | 549 | 357 | 192 | 0 | 142 | 0 | 0 | 0 | +| broadcast_1 | TLBroadcast | 549 | 357 | 192 | 0 | 142 | 0 | 0 | 0 | +| (broadcast_1) | TLBroadcast | 17 | 17 | 0 | 0 | 44 | 0 | 0 | 0 | +| TLBroadcastTracker | TLBroadcastTracker | 384 | 288 | 96 | 0 | 49 | 0 | 0 | 0 | +| (TLBroadcastTracker) | TLBroadcastTracker | 20 | 20 | 0 | 0 | 44 | 0 | 0 | 0 | +| o_data_q | Queue4_TLBroadcastData_443 | 364 | 268 | 96 | 0 | 5 | 0 | 0 | 0 | +| (o_data_q) | Queue4_TLBroadcastData_443 | 102 | 102 | 0 | 0 | 5 | 0 | 0 | 0 | +| ram_ext | ram_4x144_444 | 262 | 166 | 96 | 0 | 0 | 0 | 0 | 0 | +| TLBroadcastTracker_1 | TLBroadcastTracker_1 | 148 | 52 | 96 | 0 | 49 | 0 | 0 | 0 | +| (TLBroadcastTracker_1) | TLBroadcastTracker_1 | 32 | 32 | 0 | 0 | 44 | 0 | 0 | 0 | +| o_data_q | Queue4_TLBroadcastData | 116 | 20 | 96 | 0 | 5 | 0 | 0 | 0 | +| (o_data_q) | Queue4_TLBroadcastData | 15 | 15 | 0 | 0 | 5 | 0 | 0 | 0 | +| ram_ext | ram_4x144 | 101 | 5 | 96 | 0 | 0 | 0 | 0 | 0 | +| ibus_intsink | IntSyncAsyncCrossingSink_n1x1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | +| chain | SynchronizerShiftReg_w1_d3 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | +| output_chain | NonSyncResetSynchronizerPrimitiveShiftReg_d3 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | +| ibus_intsource | IntSyncCrossingSource_n1x1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| reg_0__0 | AsyncResetRegVec_w1_i0_442 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| mbus | MemoryBus | 745 | 489 | 256 | 0 | 330 | 0 | 0 | 0 | +| coupler_to_memory_controller_port_named_axi4 | TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4 | 745 | 489 | 256 | 0 | 330 | 0 | 0 | 0 | +| axi4yank | AXI4UserYanker_1 | 439 | 183 | 256 | 0 | 96 | 0 | 0 | 0 | +| Queue2_BundleMap | Queue2_BundleMap_6 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap) | Queue2_BundleMap_6 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_441 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_1 | Queue2_BundleMap_6_380 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_1) | Queue2_BundleMap_6_380 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_440 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_10 | Queue2_BundleMap_6_381 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_10) | Queue2_BundleMap_6_381 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_439 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_11 | Queue2_BundleMap_6_382 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_11) | Queue2_BundleMap_6_382 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_438 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_12 | Queue2_BundleMap_6_383 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_12) | Queue2_BundleMap_6_383 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_437 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_13 | Queue2_BundleMap_6_384 | 9 | 1 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_13) | Queue2_BundleMap_6_384 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_436 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_14 | Queue2_BundleMap_6_385 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_14) | Queue2_BundleMap_6_385 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_435 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_15 | Queue2_BundleMap_6_386 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_15) | Queue2_BundleMap_6_386 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_434 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_16 | Queue2_BundleMap_6_387 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_16) | Queue2_BundleMap_6_387 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_433 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_17 | Queue2_BundleMap_6_388 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_17) | Queue2_BundleMap_6_388 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_432 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_18 | Queue2_BundleMap_6_389 | 14 | 6 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_18) | Queue2_BundleMap_6_389 | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_431 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_19 | Queue2_BundleMap_6_390 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_19) | Queue2_BundleMap_6_390 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_430 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_2 | Queue2_BundleMap_6_391 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_2) | Queue2_BundleMap_6_391 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_429 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_20 | Queue2_BundleMap_6_392 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_20) | Queue2_BundleMap_6_392 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_428 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_21 | Queue2_BundleMap_6_393 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_21) | Queue2_BundleMap_6_393 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_427 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_22 | Queue2_BundleMap_6_394 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_22) | Queue2_BundleMap_6_394 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_426 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_23 | Queue2_BundleMap_6_395 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_23) | Queue2_BundleMap_6_395 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_425 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_24 | Queue2_BundleMap_6_396 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_24) | Queue2_BundleMap_6_396 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_424 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_25 | Queue2_BundleMap_6_397 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_25) | Queue2_BundleMap_6_397 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_423 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_26 | Queue2_BundleMap_6_398 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_26) | Queue2_BundleMap_6_398 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_422 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_27 | Queue2_BundleMap_6_399 | 43 | 35 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_27) | Queue2_BundleMap_6_399 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_421 | 42 | 34 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_28 | Queue2_BundleMap_6_400 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_28) | Queue2_BundleMap_6_400 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_420 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_29 | Queue2_BundleMap_6_401 | 9 | 1 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_29) | Queue2_BundleMap_6_401 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_419 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_3 | Queue2_BundleMap_6_402 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_3) | Queue2_BundleMap_6_402 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_418 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_30 | Queue2_BundleMap_6_403 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_30) | Queue2_BundleMap_6_403 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_417 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_31 | Queue2_BundleMap_6_404 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_31) | Queue2_BundleMap_6_404 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_416 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_4 | Queue2_BundleMap_6_405 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_4) | Queue2_BundleMap_6_405 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_415 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_5 | Queue2_BundleMap_6_406 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_5) | Queue2_BundleMap_6_406 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_414 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_6 | Queue2_BundleMap_6_407 | 13 | 5 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_6) | Queue2_BundleMap_6_407 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_413 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_7 | Queue2_BundleMap_6_408 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_7) | Queue2_BundleMap_6_408 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_412 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_8 | Queue2_BundleMap_6_409 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_8) | Queue2_BundleMap_6_409 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_411 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_9 | Queue2_BundleMap_6_410 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_9) | Queue2_BundleMap_6_410 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| tl2axi4 | TLToAXI4_1 | 306 | 306 | 0 | 0 | 234 | 0 | 0 | 0 | +| (tl2axi4) | TLToAXI4_1 | 3 | 3 | 0 | 0 | 41 | 0 | 0 | 0 | +| nodeOut_w_deq_q | Queue1_AXI4BundleW_1 | 83 | 83 | 0 | 0 | 146 | 0 | 0 | 0 | +| queue_arw_deq_q | Queue1_AXI4BundleARW_1 | 220 | 220 | 0 | 0 | 47 | 0 | 0 | 0 | +| plic_domain | PLICClockSinkDomain | 36 | 36 | 0 | 0 | 52 | 0 | 0 | 0 | +| intsource | IntSyncCrossingSource_n1x1_377 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| reg_0 | AsyncResetRegVec_w1_i0_379 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| intsource_1 | IntSyncCrossingSource_n1x1_378 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| reg_0 | AsyncResetRegVec_w1_i0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| plic | TLPLIC | 36 | 36 | 0 | 0 | 50 | 0 | 0 | 0 | +| (plic) | TLPLIC | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | +| gateways_gateway | LevelGateway | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| out_back_front_q | Queue1_RegMapperInput_i23_m8 | 31 | 31 | 0 | 0 | 41 | 0 | 0 | 0 | +| sbus | SystemBus | 1457 | 1111 | 346 | 0 | 608 | 0 | 0 | 0 | +| coupler_to_bus_named_cbus | TLInterconnectCoupler_sbus_to_bus_named_cbus | 143 | 143 | 0 | 0 | 191 | 0 | 0 | 0 | +| widget | TLWidthWidget16 | 143 | 143 | 0 | 0 | 191 | 0 | 0 | 0 | +| (widget) | TLWidthWidget16 | 64 | 64 | 0 | 0 | 68 | 0 | 0 | 0 | +| repeated_repeater | Repeater_TLBundleA_a28d128s3k1z4u | 79 | 79 | 0 | 0 | 123 | 0 | 0 | 0 | +| coupler_to_port_named_mmio_port_axi4 | TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4 | 804 | 458 | 346 | 0 | 353 | 0 | 0 | 0 | +| axi4buf | AXI4Buffer | 207 | 69 | 138 | 0 | 15 | 0 | 0 | 0 | +| nodeIn_b_deq_q | Queue2_AXI4BundleB | 18 | 14 | 4 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_b_deq_q) | Queue2_AXI4BundleB | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x4 | 13 | 9 | 4 | 0 | 0 | 0 | 0 | 0 | +| nodeIn_r_deq_q | Queue2_AXI4BundleR | 42 | 6 | 36 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_r_deq_q) | Queue2_AXI4BundleR | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x69 | 39 | 3 | 36 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_ar_deq_q | Queue2_AXI4BundleAR | 61 | 29 | 32 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_ar_deq_q) | Queue2_AXI4BundleAR | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x58_376 | 57 | 25 | 32 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_aw_deq_q | Queue2_AXI4BundleAW | 48 | 16 | 32 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_aw_deq_q) | Queue2_AXI4BundleAW | 6 | 6 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x58 | 42 | 10 | 32 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_w_deq_q | Queue2_AXI4BundleW | 38 | 4 | 34 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_w_deq_q) | Queue2_AXI4BundleW | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x73 | 36 | 2 | 34 | 0 | 0 | 0 | 0 | 0 | +| axi4deint | AXI4Deinterleaver | 277 | 117 | 160 | 0 | 47 | 0 | 0 | 0 | +| (axi4deint) | AXI4Deinterleaver | 0 | 0 | 0 | 0 | 19 | 0 | 0 | 0 | +| qs_queue_0 | Queue8_AXI4BundleR | 51 | 11 | 40 | 0 | 7 | 0 | 0 | 0 | +| (qs_queue_0) | Queue8_AXI4BundleR | 8 | 8 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x77_375 | 43 | 3 | 40 | 0 | 0 | 0 | 0 | 0 | +| qs_queue_1 | Queue8_AXI4BundleR_370 | 73 | 33 | 40 | 0 | 7 | 0 | 0 | 0 | +| (qs_queue_1) | Queue8_AXI4BundleR_370 | 6 | 6 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x77_374 | 67 | 27 | 40 | 0 | 0 | 0 | 0 | 0 | +| qs_queue_2 | Queue8_AXI4BundleR_371 | 49 | 9 | 40 | 0 | 7 | 0 | 0 | 0 | +| (qs_queue_2) | Queue8_AXI4BundleR_371 | 6 | 6 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x77_373 | 43 | 3 | 40 | 0 | 0 | 0 | 0 | 0 | +| qs_queue_3 | Queue8_AXI4BundleR_372 | 104 | 64 | 40 | 0 | 7 | 0 | 0 | 0 | +| (qs_queue_3) | Queue8_AXI4BundleR_372 | 6 | 6 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x77 | 98 | 58 | 40 | 0 | 0 | 0 | 0 | 0 | +| axi4yank | AXI4UserYanker | 92 | 44 | 48 | 0 | 34 | 0 | 0 | 0 | +| Queue1_BundleMap | Queue1_BundleMap | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| Queue1_BundleMap_1 | Queue1_BundleMap_359 | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| Queue2_BundleMap | Queue2_BundleMap | 15 | 7 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap) | Queue2_BundleMap | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8_369 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_1 | Queue2_BundleMap_360 | 13 | 5 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_1) | Queue2_BundleMap_360 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8_368 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_2 | Queue2_BundleMap_361 | 14 | 6 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_2) | Queue2_BundleMap_361 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8_367 | 11 | 3 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_3 | Queue2_BundleMap_362 | 14 | 6 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_3) | Queue2_BundleMap_362 | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8_366 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_4 | Queue2_BundleMap_363 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_4) | Queue2_BundleMap_363 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8_365 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_5 | Queue2_BundleMap_364 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_5) | Queue2_BundleMap_364 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| tl2axi4 | TLToAXI4 | 127 | 127 | 0 | 0 | 114 | 0 | 0 | 0 | +| (tl2axi4) | TLToAXI4 | 22 | 22 | 0 | 0 | 17 | 0 | 0 | 0 | +| nodeOut_w_deq_q | Queue1_AXI4BundleW | 57 | 57 | 0 | 0 | 50 | 0 | 0 | 0 | +| queue_arw_deq_q | Queue1_AXI4BundleARW | 48 | 48 | 0 | 0 | 47 | 0 | 0 | 0 | +| widget | TLWidthWidget16_2 | 101 | 101 | 0 | 0 | 143 | 0 | 0 | 0 | +| (widget) | TLWidthWidget16_2 | 45 | 45 | 0 | 0 | 48 | 0 | 0 | 0 | +| repeated_repeater | Repeater_TLBundleA_a31d128s3k1z3u | 56 | 56 | 0 | 0 | 95 | 0 | 0 | 0 | +| system_bus_xbar | TLXbar_sbus_i2_o3_a32d128s3k1z4c | 510 | 510 | 0 | 0 | 64 | 0 | 0 | 0 | +| tile_prci_domain | TilePRCIDomain | 46597 | 44483 | 1890 | 224 | 25903 | 27 | 8 | 117 | +| buffer | TLBuffer_a32d128s2k1z4u_1 | 1214 | 628 | 586 | 0 | 21 | 0 | 0 | 0 | +| nodeIn_b_q | Queue2_TLBundleB_a32d128s2k1z4c | 28 | 4 | 24 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_b_q) | Queue2_TLBundleB_a32d128s2k1z4c | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x60 | 25 | 1 | 24 | 0 | 0 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a32d128s2k1z4u | 101 | 5 | 96 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q) | Queue2_TLBundleD_a32d128s2k1z4u | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x142_358 | 97 | 1 | 96 | 0 | 0 | 0 | 0 | 0 | +| nodeIn_d_q_1 | Queue2_TLBundleD_a32d128s2k1z4c | 161 | 65 | 96 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q_1) | Queue2_TLBundleD_a32d128s2k1z4c | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x142 | 158 | 62 | 96 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a32d128s2k1z4u | 144 | 16 | 128 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a32d128s2k1z4u | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x189_357 | 142 | 14 | 128 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q_1 | Queue2_TLBundleA_a32d128s2k1z4c | 646 | 518 | 128 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q_1) | Queue2_TLBundleA_a32d128s2k1z4c | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x189 | 643 | 515 | 128 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_c_q | Queue2_TLBundleC_a32d128s2k1z4c | 128 | 16 | 112 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_c_q) | Queue2_TLBundleC_a32d128s2k1z4c | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x173 | 125 | 13 | 112 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_e_q | Queue2_TLBundleE_a32d128s2k1z4c | 6 | 4 | 2 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_e_q) | Queue2_TLBundleE_a32d128s2k1z4c | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_sink_ext | ram_sink_2x1 | 3 | 1 | 2 | 0 | 0 | 0 | 0 | 0 | +| element_reset_domain_bbtile | BBTile | 45383 | 43855 | 1304 | 224 | 25882 | 27 | 8 | 117 | +| (element_reset_domain_bbtile) | BBTile | 24 | 0 | 24 | 0 | 0 | 0 | 0 | 0 | +| accelerators_0 | BuckyballAccelerator | 24384 | 23650 | 510 | 224 | 15033 | 18 | 0 | 95 | +| ballDomain | BallDomain | 14446 | 14032 | 190 | 224 | 10879 | 0 | 0 | 93 | +| ballRs | BallReservationStation | 148 | 52 | 96 | 0 | 5 | 0 | 0 | 0 | +| fifo | Queue4_BallReservationStation_Anon | 148 | 52 | 96 | 0 | 5 | 0 | 0 | 0 | +| (fifo) | Queue4_BallReservationStation_Anon | 3 | 3 | 0 | 0 | 5 | 0 | 0 | 0 | +| ram_ext | ram_4x281 | 145 | 49 | 96 | 0 | 0 | 0 | 0 | 0 | +| bbus | BBus | 14298 | 13980 | 94 | 224 | 10874 | 0 | 0 | 93 | +| (bbus) | BBus | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | +| balls_0 | GemminiBall | 14298 | 13980 | 94 | 224 | 10864 | 0 | 0 | 93 | +| (balls_0) | GemminiBall | 1 | 1 | 0 | 0 | 470 | 0 | 0 | 0 | +| convUnroller | LoopConvUnroller | 521 | 521 | 0 | 0 | 375 | 0 | 0 | 20 | +| (convUnroller) | LoopConvUnroller | 40 | 40 | 0 | 0 | 375 | 0 | 0 | 0 | +| addrGen | LoopConvAddrGen | 487 | 487 | 0 | 0 | 0 | 0 | 0 | 20 | +| exCtrl | GemminiExCtrl | 13112 | 12794 | 94 | 224 | 9717 | 0 | 0 | 64 | +| (exCtrl) | GemminiExCtrl | 1428 | 1428 | 0 | 0 | 2444 | 0 | 0 | 0 | +| mesh | MeshWithDelays | 11288 | 11058 | 6 | 224 | 7259 | 0 | 0 | 64 | +| (mesh) | MeshWithDelays | 632 | 408 | 0 | 224 | 557 | 0 | 0 | 0 | +| mesh | Mesh | 9993 | 9993 | 0 | 0 | 6098 | 0 | 0 | 64 | +| (mesh) | Mesh | 225 | 225 | 0 | 0 | 3530 | 0 | 0 | 0 | +| mesh_0_0 | Tile | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_354 | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_354 | 96 | 96 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_355 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_356 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_1 | Tile_104 | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_351 | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_351 | 96 | 96 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_352 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_353 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_2 | Tile_105 | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_348 | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_348 | 96 | 96 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_349 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_350 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_3 | Tile_106 | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_345 | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_345 | 96 | 96 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_346 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_347 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_4 | Tile_107 | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_342 | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_342 | 96 | 96 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_343 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_344 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_5 | Tile_108 | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_339 | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_339 | 96 | 96 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_340 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_341 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_6 | Tile_109 | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_336 | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_336 | 96 | 96 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_337 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_338 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_7 | Tile_110 | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_333 | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_333 | 96 | 96 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_334 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_335 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_0 | Tile_111 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_330 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_330 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_331 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_332 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_1 | Tile_112 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_327 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_327 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_328 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_329 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_2 | Tile_113 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_324 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_324 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_325 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_326 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_3 | Tile_114 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_321 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_321 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_322 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_323 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_4 | Tile_115 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_318 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_318 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_319 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_320 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_5 | Tile_116 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_315 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_315 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_316 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_317 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_6 | Tile_117 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_312 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_312 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_313 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_314 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_7 | Tile_118 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_309 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_309 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_310 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_311 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_0 | Tile_119 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_306 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_306 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_307 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_308 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_1 | Tile_120 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_303 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_303 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_304 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_305 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_2 | Tile_121 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_300 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_300 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_301 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_302 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_3 | Tile_122 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_297 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_297 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_298 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_299 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_4 | Tile_123 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_294 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_294 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_295 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_296 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_5 | Tile_124 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_291 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_291 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_292 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_293 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_6 | Tile_125 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_288 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_288 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_289 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_290 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_7 | Tile_126 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_285 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_285 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_286 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_287 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_0 | Tile_127 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_282 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_282 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_283 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_284 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_1 | Tile_128 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_279 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_279 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_280 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_281 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_2 | Tile_129 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_276 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_276 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_277 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_278 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_3 | Tile_130 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_273 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_273 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_274 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_275 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_4 | Tile_131 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_270 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_270 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_271 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_272 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_5 | Tile_132 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_267 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_267 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_268 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_269 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_6 | Tile_133 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_264 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_264 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_265 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_266 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_7 | Tile_134 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_261 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_261 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_262 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_263 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_0 | Tile_135 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_258 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_258 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_259 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_260 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_1 | Tile_136 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_255 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_255 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_256 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_257 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_2 | Tile_137 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_252 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_252 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_253 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_254 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_3 | Tile_138 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_249 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_249 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_250 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_251 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_4 | Tile_139 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_246 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_246 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_247 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_248 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_5 | Tile_140 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_243 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_243 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_244 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_245 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_6 | Tile_141 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_240 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_240 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_241 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_242 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_7 | Tile_142 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_237 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_237 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_238 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_239 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_0 | Tile_143 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_234 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_234 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_235 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_236 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_1 | Tile_144 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_231 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_231 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_232 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_233 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_2 | Tile_145 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_228 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_228 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_229 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_230 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_3 | Tile_146 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_225 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_225 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_226 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_227 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_4 | Tile_147 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_222 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_222 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_223 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_224 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_5 | Tile_148 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_219 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_219 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_220 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_221 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_6 | Tile_149 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_216 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_216 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_217 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_218 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_7 | Tile_150 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_213 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_213 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_214 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_215 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_0 | Tile_151 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_210 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_210 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_211 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_212 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_1 | Tile_152 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_207 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_207 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_208 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_209 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_2 | Tile_153 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_204 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_204 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_205 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_206 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_3 | Tile_154 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_201 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_201 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_202 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_203 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_4 | Tile_155 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_198 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_198 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_199 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_200 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_5 | Tile_156 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_195 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_195 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_196 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_197 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_6 | Tile_157 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_192 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_192 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_193 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_194 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_7 | Tile_158 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_189 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_189 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_190 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_191 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_0 | Tile_159 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_186 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_186 | 97 | 97 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_187 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_188 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_1 | Tile_160 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_183 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_183 | 97 | 97 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_184 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_185 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_2 | Tile_161 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_180 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_180 | 97 | 97 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_181 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_182 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_3 | Tile_162 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_177 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_177 | 97 | 97 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_178 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_179 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_4 | Tile_163 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_174 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_174 | 97 | 97 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_175 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_176 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_5 | Tile_164 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_171 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_171 | 97 | 97 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_172 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_173 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_6 | Tile_165 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_168 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_168 | 97 | 97 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_169 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_170 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_7 | Tile_166 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_167 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_167 | 97 | 97 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| tagq | TagQueue | 117 | 117 | 0 | 0 | 75 | 0 | 0 | 0 | +| total_rows_q | Queue6_TagWithIdAndTotalRows | 32 | 26 | 6 | 0 | 7 | 0 | 0 | 0 | +| (total_rows_q) | Queue6_TagWithIdAndTotalRows | 5 | 5 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_6x7 | 27 | 21 | 6 | 0 | 0 | 0 | 0 | 0 | +| transposer | AlwaysOutTransposer | 514 | 514 | 0 | 0 | 522 | 0 | 0 | 0 | +| (transposer) | AlwaysOutTransposer | 8 | 8 | 0 | 0 | 10 | 0 | 0 | 0 | +| pes_0_0 | PE | 17 | 17 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_1 | PE_41 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_2 | PE_42 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_3 | PE_43 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_4 | PE_44 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_5 | PE_45 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_6 | PE_46 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_7 | PE_47 | 32 | 32 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_0 | PE_48 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_1 | PE_49 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_2 | PE_50 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_3 | PE_51 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_4 | PE_52 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_5 | PE_53 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_6 | PE_54 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_7 | PE_55 | 13 | 13 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_0 | PE_56 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_1 | PE_57 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_2 | PE_58 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_3 | PE_59 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_4 | PE_60 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_5 | PE_61 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_6 | PE_62 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_7 | PE_63 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_0 | PE_64 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_1 | PE_65 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_2 | PE_66 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_3 | PE_67 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_4 | PE_68 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_5 | PE_69 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_6 | PE_70 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_7 | PE_71 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_0 | PE_72 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_1 | PE_73 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_2 | PE_74 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_3 | PE_75 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_4 | PE_76 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_5 | PE_77 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_6 | PE_78 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_7 | PE_79 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_0 | PE_80 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_1 | PE_81 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_2 | PE_82 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_3 | PE_83 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_4 | PE_84 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_5 | PE_85 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_6 | PE_86 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_7 | PE_87 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_0 | PE_88 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_1 | PE_89 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_2 | PE_90 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_3 | PE_91 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_4 | PE_92 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_5 | PE_93 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_6 | PE_94 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_7 | PE_95 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_0 | PE_96 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_1 | PE_97 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_2 | PE_98 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_3 | PE_99 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_4 | PE_100 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_5 | PE_101 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_6 | PE_102 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_7 | PE_103 | 16 | 16 | 0 | 0 | 8 | 0 | 0 | 0 | +| rdQueue0 | Queue8_SramReadResp | 306 | 262 | 44 | 0 | 7 | 0 | 0 | 0 | +| (rdQueue0) | Queue8_SramReadResp | 100 | 100 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_data_ext | ram_data_8x64_40 | 206 | 162 | 44 | 0 | 0 | 0 | 0 | 0 | +| rdQueue1 | Queue8_SramReadResp_39 | 90 | 46 | 44 | 0 | 7 | 0 | 0 | 0 | +| (rdQueue1) | Queue8_SramReadResp_39 | 44 | 44 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_data_ext | ram_data_8x64 | 46 | 2 | 44 | 0 | 0 | 0 | 0 | 0 | +| matmulUnroller | LoopMatmulUnroller | 664 | 664 | 0 | 0 | 302 | 0 | 0 | 9 | +| cmdRouter | CmdRouter | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| bankReadReqQ_q | Queue8_BuckyballAccelerator_Anon | 33 | 17 | 16 | 0 | 7 | 0 | 0 | 0 | +| (bankReadReqQ_q) | Queue8_BuckyballAccelerator_Anon | 6 | 6 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x21_38 | 27 | 11 | 16 | 0 | 0 | 0 | 0 | 0 | +| bankReadReqQ_q_1 | Queue8_BuckyballAccelerator_Anon_10 | 37 | 21 | 16 | 0 | 7 | 0 | 0 | 0 | +| (bankReadReqQ_q_1) | Queue8_BuckyballAccelerator_Anon_10 | 6 | 6 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x21 | 31 | 15 | 16 | 0 | 0 | 0 | 0 | 0 | +| frontend | Frontend_1 | 5269 | 5073 | 196 | 0 | 2205 | 2 | 0 | 0 | +| boot | BootRom | 10 | 10 | 0 | 0 | 6 | 0 | 0 | 0 | +| scheduler | GlobalScheduler | 5259 | 5063 | 196 | 0 | 2199 | 2 | 0 | 0 | +| (scheduler) | GlobalScheduler | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | +| completeQueue | Queue16_UInt4 | 34 | 30 | 4 | 0 | 9 | 0 | 0 | 0 | +| (completeQueue) | Queue16_UInt4 | 10 | 10 | 0 | 0 | 9 | 0 | 0 | 0 | +| ram_ext | ram_16x4 | 24 | 20 | 4 | 0 | 0 | 0 | 0 | 0 | +| rob | GlobalROB | 4660 | 4660 | 0 | 0 | 1668 | 2 | 0 | 0 | +| (rob) | GlobalROB | 1446 | 1446 | 0 | 0 | 1476 | 0 | 0 | 0 | +| bat | BankAliasTable | 1017 | 1017 | 0 | 0 | 176 | 0 | 0 | 0 | +| robOperands | robOperands | 1725 | 1725 | 0 | 0 | 0 | 2 | 0 | 0 | +| robOperands_ext | robOperands_ext | 1725 | 1725 | 0 | 0 | 0 | 2 | 0 | 0 | +| scoreboard | BankScoreboard | 472 | 472 | 0 | 0 | 16 | 0 | 0 | 0 | +| subRob | SubROB | 565 | 373 | 192 | 0 | 519 | 0 | 0 | 0 | +| (subRob) | SubROB | 370 | 370 | 0 | 0 | 273 | 0 | 0 | 0 | +| sram | sram | 195 | 3 | 192 | 0 | 246 | 0 | 0 | 0 | +| sram_ext | sram_ext | 195 | 3 | 192 | 0 | 246 | 0 | 0 | 0 | +| gpDomain | GpDomain | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | +| completeQ | Queue1_GlobalSchedComplete | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | +| memDomain | MemDomain | 4599 | 4507 | 92 | 0 | 1928 | 16 | 0 | 2 | +| backend | MemBackend | 2387 | 2387 | 0 | 0 | 472 | 16 | 0 | 0 | +| privateBackend | PrivateMemBackend | 2387 | 2387 | 0 | 0 | 472 | 16 | 0 | 0 | +| (privateBackend) | PrivateMemBackend | 203 | 203 | 0 | 0 | 243 | 0 | 0 | 0 | +| accPipes_0 | AccPipe | 350 | 350 | 0 | 0 | 67 | 0 | 0 | 0 | +| accPipes_1 | AccPipe_11 | 334 | 334 | 0 | 0 | 67 | 0 | 0 | 0 | +| accPipes_2 | AccPipe_12 | 59 | 59 | 0 | 0 | 3 | 0 | 0 | 0 | +| accPipes_3 | AccPipe_13 | 292 | 292 | 0 | 0 | 3 | 0 | 0 | 0 | +| accPipes_4 | AccPipe_14 | 333 | 333 | 0 | 0 | 3 | 0 | 0 | 0 | +| accPipes_5 | AccPipe_15 | 520 | 520 | 0 | 0 | 3 | 0 | 0 | 0 | +| accPipes_6 | AccPipe_16 | 296 | 296 | 0 | 0 | 67 | 0 | 0 | 0 | +| banks_0 | SramBank | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_0) | SramBank | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_36 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_37 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_1 | SramBank_17 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_1) | SramBank_17 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_34 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_35 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_2 | SramBank_18 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_2) | SramBank_18 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_32 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_33 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_3 | SramBank_19 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_3) | SramBank_19 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_30 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_31 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_4 | SramBank_20 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_4) | SramBank_20 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_28 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_29 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_5 | SramBank_21 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_5) | SramBank_21 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_26 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_27 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_6 | SramBank_22 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_6) | SramBank_22 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_24 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_25 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_7 | SramBank_23 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_7) | SramBank_23 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| frontend | MemFrontend | 2172 | 2080 | 92 | 0 | 1446 | 0 | 0 | 2 | +| (frontend) | MemFrontend | 594 | 594 | 0 | 0 | 2 | 0 | 0 | 0 | +| configer | MemConfiger | 135 | 135 | 0 | 0 | 63 | 0 | 0 | 0 | +| (configer) | MemConfiger | 96 | 96 | 0 | 0 | 29 | 0 | 0 | 0 | +| zeroLines | ZeroLineGenerator | 39 | 39 | 0 | 0 | 34 | 0 | 0 | 0 | +| groupQuery | MemGroupQueryArbiter | 10 | 10 | 0 | 0 | 12 | 0 | 0 | 0 | +| (groupQuery) | MemGroupQueryArbiter | 10 | 10 | 0 | 0 | 11 | 0 | 0 | 0 | +| arbiter | RRArbiter_2 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| memLoader | MemLoader | 240 | 240 | 0 | 0 | 242 | 0 | 0 | 0 | +| memRs | MemReservationStation | 164 | 72 | 92 | 0 | 5 | 0 | 0 | 0 | +| fifo | Queue4_MemReservationStation_Anon | 164 | 72 | 92 | 0 | 5 | 0 | 0 | 0 | +| (fifo) | Queue4_MemReservationStation_Anon | 3 | 3 | 0 | 0 | 5 | 0 | 0 | 0 | +| ram_ext | ram_4x158 | 161 | 69 | 92 | 0 | 0 | 0 | 0 | 0 | +| memStorer | MemStorer | 384 | 384 | 0 | 0 | 447 | 0 | 0 | 0 | +| reader | StreamReader | 548 | 548 | 0 | 0 | 304 | 0 | 0 | 2 | +| tlbCluster | BBTLBCluster | 151 | 151 | 0 | 0 | 261 | 0 | 0 | 0 | +| (tlbCluster) | BBTLBCluster | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| tlb | TLB | 151 | 151 | 0 | 0 | 259 | 0 | 0 | 0 | +| tlbArb | RRArbiter_1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| writer | StreamWriter | 5 | 5 | 0 | 0 | 110 | 0 | 0 | 0 | +| midend | MemMidend | 40 | 40 | 0 | 0 | 10 | 0 | 0 | 0 | +| barrierUnit | BarrierUnit | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | +| buffer | TLBuffer_a32d64s1k1z4u | 130 | 50 | 80 | 0 | 6 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a32d64s1k1z4u_7 | 94 | 42 | 52 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q) | Queue2_TLBundleD_a32d64s1k1z4u_7 | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x77 | 90 | 38 | 52 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a32d64s1k1z4u_8 | 36 | 8 | 28 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a32d64s1k1z4u_8 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x116_9 | 33 | 5 | 28 | 0 | 0 | 0 | 0 | 0 | +| buffer_1 | TLBuffer_a32d64s1k1z4u_1 | 147 | 75 | 72 | 0 | 6 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a32d64s1k1z4u | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a32d64s1k1z4u | 143 | 71 | 72 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a32d64s1k1z4u | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x116 | 140 | 68 | 72 | 0 | 0 | 0 | 0 | 0 | +| buffer_2 | TLBuffer_a32d64s2k1z4u | 241 | 109 | 132 | 0 | 6 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a32d64s2k1z4u | 57 | 5 | 52 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q) | Queue2_TLBundleD_a32d64s2k1z4u | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x78 | 54 | 2 | 52 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a32d64s2k1z4u | 184 | 104 | 80 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a32d64s2k1z4u | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x117 | 183 | 103 | 80 | 0 | 0 | 0 | 0 | 0 | +| cores_0 | RocketBB | 6198 | 6110 | 88 | 0 | 1898 | 0 | 0 | 13 | +| (cores_0) | RocketBB | 2423 | 2423 | 0 | 0 | 755 | 0 | 0 | 0 | +| csr | CSRFile | 1983 | 1983 | 0 | 0 | 870 | 0 | 0 | 0 | +| div | MulDiv | 1571 | 1571 | 0 | 0 | 214 | 0 | 0 | 13 | +| ibuf | IBuf | 102 | 102 | 0 | 0 | 59 | 0 | 0 | 0 | +| rf_ext | rf_31x64 | 119 | 31 | 88 | 0 | 0 | 0 | 0 | 0 | +| dcache | NonBlockingDCache | 3253 | 3161 | 92 | 0 | 3330 | 9 | 0 | 0 | +| (dcache) | NonBlockingDCache | 519 | 519 | 0 | 0 | 1150 | 0 | 0 | 0 | +| data | DataArray | 256 | 256 | 0 | 0 | 2 | 8 | 0 | 0 | +| (data) | DataArray | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| array_0_0 | array_0_0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_0_0_ext | array_0_0_ext_6 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_0_1 | array_0_1 | 64 | 64 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_0_0_ext | array_0_0_ext_5 | 64 | 64 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_2_0 | array_2_0 | 64 | 64 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_0_0_ext | array_0_0_ext_4 | 64 | 64 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_2_1 | array_2_1 | 128 | 128 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_0_0_ext | array_0_0_ext | 128 | 128 | 0 | 0 | 0 | 2 | 0 | 0 | +| dtlb | DTLB | 1277 | 1277 | 0 | 0 | 1692 | 0 | 0 | 0 | +| lfsr_prng | MaxPeriodFibonacciLFSR_3 | 13 | 13 | 0 | 0 | 16 | 0 | 0 | 0 | +| meta | L1MetadataArray | 129 | 37 | 92 | 0 | 98 | 0 | 0 | 0 | +| (meta) | L1MetadataArray | 3 | 3 | 0 | 0 | 6 | 0 | 0 | 0 | +| tag_array | tag_array | 126 | 34 | 92 | 0 | 92 | 0 | 0 | 0 | +| tag_array_ext | tag_array_ext | 126 | 34 | 92 | 0 | 92 | 0 | 0 | 0 | +| mshrs | MSHRFile | 693 | 693 | 0 | 0 | 292 | 1 | 0 | 0 | +| (mshrs) | MSHRFile | 2 | 2 | 0 | 0 | 26 | 0 | 0 | 0 | +| mmios_0 | IOMSHR | 297 | 297 | 0 | 0 | 180 | 0 | 0 | 0 | +| mshrs_0 | MSHR | 314 | 314 | 0 | 0 | 86 | 0 | 0 | 0 | +| (mshrs_0) | MSHR | 119 | 119 | 0 | 0 | 75 | 0 | 0 | 0 | +| grantackq | Queue1_TLBundleE_a32d128s1k1z4c | 78 | 78 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpq | Queue16_ReplayInternal | 117 | 117 | 0 | 0 | 9 | 0 | 0 | 0 | +| sdq_ext | sdq_17x64 | 80 | 80 | 0 | 0 | 0 | 1 | 0 | 0 | +| prober | ProbeUnit | 81 | 81 | 0 | 0 | 40 | 0 | 0 | 0 | +| wb | WritebackUnit | 285 | 285 | 0 | 0 | 40 | 0 | 0 | 0 | +| dcacheArb | HellaCacheArbiter | 15 | 15 | 0 | 0 | 4 | 0 | 0 | 0 | +| fpuOpts_0 | FPU | 8025 | 7761 | 264 | 0 | 2618 | 0 | 0 | 9 | +| (fpuOpts_0) | FPU | 28 | 28 | 0 | 0 | 193 | 0 | 0 | 0 | +| divSqrt | DivSqrtRecFM_small_e5_s11 | 152 | 152 | 0 | 0 | 60 | 0 | 0 | 0 | +| divSqrtRecFNToRaw | DivSqrtRecFMToRaw_small_e5_s11 | 152 | 152 | 0 | 0 | 60 | 0 | 0 | 0 | +| divSqrtRawFN | DivSqrtRawFN_small_e5_s11 | 152 | 152 | 0 | 0 | 60 | 0 | 0 | 0 | +| roundRawFNToRecFN | RoundRawFNToRecFN_e5_s11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie5_is13_oe5_os11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| divSqrt_1 | DivSqrtRecFM_small_e8_s24 | 345 | 345 | 0 | 0 | 103 | 0 | 0 | 0 | +| divSqrtRecFNToRaw | DivSqrtRecFMToRaw_small_e8_s24 | 340 | 340 | 0 | 0 | 103 | 0 | 0 | 0 | +| divSqrtRawFN | DivSqrtRawFN_small_e8_s24 | 340 | 340 | 0 | 0 | 103 | 0 | 0 | 0 | +| roundRawFNToRecFN | RoundRawFNToRecFN_e8_s24 | 5 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie8_is26_oe8_os24 | 5 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | +| divSqrt_2 | DivSqrtRecFM_small_e11_s53 | 858 | 858 | 0 | 0 | 195 | 0 | 0 | 0 | +| divSqrtRecFNToRaw | DivSqrtRecFMToRaw_small_e11_s53 | 849 | 849 | 0 | 0 | 195 | 0 | 0 | 0 | +| divSqrtRawFN | DivSqrtRawFN_small_e11_s53 | 849 | 849 | 0 | 0 | 195 | 0 | 0 | 0 | +| roundRawFNToRecFN | RoundRawFNToRecFN_e11_s53 | 9 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie11_is55_oe11_os53 | 9 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | +| fpiu | FPToInt | 1044 | 1044 | 0 | 0 | 140 | 0 | 0 | 0 | +| (fpiu) | FPToInt | 993 | 993 | 0 | 0 | 140 | 0 | 0 | 0 | +| dcmp | CompareRecFN | 51 | 51 | 0 | 0 | 0 | 0 | 0 | 0 | +| fpmu | FPToFP | 436 | 436 | 0 | 0 | 208 | 0 | 0 | 0 | +| (fpmu) | FPToFP | 93 | 93 | 0 | 0 | 208 | 0 | 0 | 0 | +| narrower | RecFNToRecFN | 126 | 126 | 0 | 0 | 0 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie11_is53_oe5_os11 | 126 | 126 | 0 | 0 | 0 | 0 | 0 | 0 | +| narrower_1 | RecFNToRecFN_1 | 217 | 217 | 0 | 0 | 0 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie11_is53_oe8_os24 | 217 | 217 | 0 | 0 | 0 | 0 | 0 | 0 | +| ifpu | IntToFP | 1581 | 1581 | 0 | 0 | 695 | 0 | 0 | 0 | +| (ifpu) | IntToFP | 61 | 61 | 0 | 0 | 140 | 0 | 0 | 0 | +| i2f_0 | PipelinedINToRecFN | 799 | 799 | 0 | 0 | 281 | 0 | 0 | 0 | +| (i2f_0) | PipelinedINToRecFN | 772 | 772 | 0 | 0 | 281 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie7_is64_oe5_os11 | 27 | 27 | 0 | 0 | 0 | 0 | 0 | 0 | +| i2f_1 | PipelinedINToRecFN_1 | 361 | 361 | 0 | 0 | 137 | 0 | 0 | 0 | +| (i2f_1) | PipelinedINToRecFN_1 | 333 | 333 | 0 | 0 | 137 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie7_is64_oe8_os24 | 28 | 28 | 0 | 0 | 0 | 0 | 0 | 0 | +| i2f_2 | PipelinedINToRecFN_2 | 360 | 360 | 0 | 0 | 137 | 0 | 0 | 0 | +| (i2f_2) | PipelinedINToRecFN_2 | 319 | 319 | 0 | 0 | 137 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie7_is64_oe11_os53 | 41 | 41 | 0 | 0 | 0 | 0 | 0 | 0 | +| regfile_ext | regfile_32x65 | 1108 | 844 | 264 | 0 | 32 | 0 | 0 | 0 | +| sharedFma | FPUSharedFMAPipe | 2473 | 2473 | 0 | 0 | 992 | 0 | 0 | 9 | +| (sharedFma) | FPUSharedFMAPipe | 15 | 15 | 0 | 0 | 238 | 0 | 0 | 0 | +| fma | SharedMulAddRecFNPipe | 2458 | 2458 | 0 | 0 | 754 | 0 | 0 | 9 | +| frontend | Frontend | 2154 | 2112 | 42 | 0 | 2221 | 0 | 8 | 0 | +| (frontend) | Frontend | 3 | 3 | 0 | 0 | 90 | 0 | 0 | 0 | +| fq | ShiftQueue | 775 | 775 | 0 | 0 | 375 | 0 | 0 | 0 | +| icache | ICache | 550 | 508 | 42 | 0 | 294 | 0 | 8 | 0 | +| (icache) | ICache | 266 | 266 | 0 | 0 | 236 | 0 | 0 | 0 | +| bbtile_icache_data_arrays_0 | bbtile_icache_data_arrays_0 | 2 | 2 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_0_ext | bbtile_icache_data_arrays_0_ext_2 | 2 | 2 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_1 | bbtile_icache_data_arrays_1 | 43 | 43 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_0_ext | bbtile_icache_data_arrays_0_ext_1 | 43 | 43 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_2 | bbtile_icache_data_arrays_2 | 2 | 2 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_0_ext | bbtile_icache_data_arrays_0_ext_0 | 2 | 2 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_3 | bbtile_icache_data_arrays_3 | 45 | 45 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_0_ext | bbtile_icache_data_arrays_0_ext | 45 | 45 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_tag_array | bbtile_icache_tag_array | 63 | 21 | 42 | 0 | 42 | 0 | 0 | 0 | +| bbtile_icache_tag_array_ext | bbtile_icache_tag_array_ext | 63 | 21 | 42 | 0 | 42 | 0 | 0 | 0 | +| repl_way_v0_prng | MaxPeriodFibonacciLFSR | 129 | 129 | 0 | 0 | 16 | 0 | 0 | 0 | +| tlb | ITLB | 826 | 826 | 0 | 0 | 1462 | 0 | 0 | 0 | +| ptw | PTW | 786 | 786 | 0 | 0 | 567 | 0 | 0 | 0 | +| roccMemIF | SimpleHellaCacheIF | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| (roccMemIF) | SimpleHellaCacheIF | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| replayq | SimpleHellaCacheIFReplayQueue | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 | +| (replayq) | SimpleHellaCacheIFReplayQueue | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| nackq | Queue3_UInt2 | 8 | 8 | 0 | 0 | 5 | 0 | 0 | 0 | +| tlMasterXbar | TLXbar_MasterXbar_BBTile_i2_o1_a32d128s2k1z4c | 44 | 44 | 0 | 0 | 11 | 0 | 0 | 0 | +| widget_3 | TLWidthWidget8_4 | 85 | 85 | 0 | 0 | 160 | 0 | 0 | 0 | +| (widget_3) | TLWidthWidget8_4 | 1 | 1 | 0 | 0 | 81 | 0 | 0 | 0 | +| repeated_repeater | Repeater_TLBundleD_a32d128s2k1z4u | 84 | 84 | 0 | 0 | 79 | 0 | 0 | 0 | +| xbar | TLXbar_i2_o1_a32d64s2k1z4u | 65 | 65 | 0 | 0 | 13 | 0 | 0 | 0 | +| load_bridge | loader_axi | 41 | 41 | 0 | 0 | 306 | 0 | 0 | 0 | +| loader | ddr_uart_loader | 441 | 377 | 64 | 0 | 159 | 0 | 0 | 0 | +| normalizer | axi_fullwidth | 334 | 334 | 0 | 0 | 376 | 0 | 0 | 0 | +| peripherals | axi_scu | 152 | 104 | 48 | 0 | 162 | 0 | 0 | 0 | +| receiver | uart_rx | 39 | 39 | 0 | 0 | 31 | 0 | 0 | 0 | +| transmitter | uart_tx | 15 | 15 | 0 | 0 | 18 | 0 | 0 | 0 | ++----------------------------------------------------------------------------------------+-----------------------------------------------------------------+------------+------------+---------+------+-------+--------+--------+------------+ + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/synth-timing.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/synth-timing.rpt new file mode 100644 index 0000000..d53b91f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/synth-timing.rpt @@ -0,0 +1,4930 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Mon Oct 12 20:30:55 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_timing_summary -delay_type min_max -file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/synth-timing.rpt +| Design : toy_a7_top +| Device : 7a100t-csg324 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +| Design State : Synthesized +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : No + Borrow Time for Max Delay Exceptions : Yes + Merge Timing Exceptions : Yes + Inter-SLR Compensation : Conservative + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + +------------------------------------------------------------------------------------------------ +| Report Methodology +| ------------------ +------------------------------------------------------------------------------------------------ + +No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations. + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock (0) +2. checking constant_clock (0) +3. checking pulse_width_clock (0) +4. checking unconstrained_internal_endpoints (0) +5. checking no_input_delay (3) +6. checking no_output_delay (6) +7. checking multiple_clock (0) +8. checking generated_clocks (0) +9. checking loops (0) +10. checking partial_input_delay (0) +11. checking partial_output_delay (0) +12. checking latch_loops (0) + +1. checking no_clock (0) +------------------------ + There are 0 register/latch pins with no clock. + + +2. checking constant_clock (0) +------------------------------ + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock (0) +--------------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints (0) +------------------------------------------------ + There are 0 pins that are not constrained for maximum delay. + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay (3) +------------------------------ + There is 1 input port with no input delay specified. (HIGH) + + There are 2 input ports with no input delay but user has a false path constraint. (MEDIUM) + + +6. checking no_output_delay (6) +------------------------------- + There are 0 ports with no output delay specified. + + There are 6 ports with no output delay but user has a false path constraint (MEDIUM) + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock (0) +------------------------------ + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks (0) +-------------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops (0) +--------------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay (0) +------------------------------------ + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay (0) +------------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops (0) +---------------------------- + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + 1.277 0.000 0 108329 -1.631 -26.741 55 108287 0.187 0.000 0 42005 + + +Timing constraints are not met. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + +Clock Waveform(ns) Period(ns) Frequency(MHz) +----- ------------ ---------- -------------- +board_clk {0.000 5.000} 10.000 100.000 + core_raw {0.000 20.000} 40.000 25.000 + fb {0.000 5.000} 10.000 100.000 + ref_raw {0.000 2.500} 5.000 200.000 + sys_raw {0.000 3.000} 6.000 166.667 + freq_refclk {0.000 0.750} 1.500 666.667 + u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk {0.000 1.500} 3.000 333.333 + iserdes_clkdiv {0.000 6.000} 12.000 83.333 + u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk {0.000 1.500} 3.000 333.333 + iserdes_clkdiv_1 {0.000 6.000} 12.000 83.333 + mem_refclk {0.000 1.500} 3.000 333.333 + oserdes_clk {0.000 1.500} 3.000 333.333 + oserdes_clkdiv {0.000 6.000} 12.000 83.333 + oserdes_clk_1 {0.000 1.500} 3.000 333.333 + oserdes_clkdiv_1 {0.000 6.000} 12.000 83.333 + oserdes_clk_2 {0.000 1.500} 3.000 333.333 + oserdes_clkdiv_2 {0.000 3.000} 6.000 166.667 + oserdes_clk_3 {0.000 1.500} 3.000 333.333 + oserdes_clkdiv_3 {0.000 3.000} 6.000 166.667 + pll_clk3_out {0.000 6.000} 12.000 83.333 + clk_div2_bufg_in {0.000 3.000} 6.000 166.667 + clk_pll_i {0.000 6.000} 12.000 83.333 + mmcm_ps_clk_bufg_in {0.000 12.000} 24.000 41.667 + pll_clkfbout {0.000 3.000} 6.000 166.667 + sync_pulse {1.312 4.313} 48.000 20.833 + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- +board_clk 3.000 0.000 0 1 + core_raw 14.939 0.000 0 92516 0.045 0.000 0 92516 18.750 0.000 0 35544 + fb 7.845 0.000 0 3 + ref_raw 2.263 0.000 0 130 0.045 0.000 0 130 0.264 0.000 0 69 + sys_raw 1.500 0.000 0 3 + freq_refclk 0.187 0.000 0 8 + u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk 1.333 0.000 0 16 + iserdes_clkdiv 9.972 0.000 0 33 0.071 0.000 0 33 3.850 0.000 0 9 + u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk 1.333 0.000 0 16 + iserdes_clkdiv_1 9.955 0.000 0 33 0.071 0.000 0 33 3.850 0.000 0 9 + mem_refclk 1.810 0.000 0 1 0.375 0.000 0 1 0.875 0.000 0 8 + oserdes_clk 1.333 0.000 0 12 + oserdes_clkdiv 10.094 0.000 0 44 0.113 0.000 0 44 3.850 0.000 0 12 + oserdes_clk_1 1.333 0.000 0 12 + oserdes_clkdiv_1 10.595 0.000 0 48 0.119 0.000 0 48 3.850 0.000 0 13 + oserdes_clk_2 1.442 0.000 0 4 0.440 0.000 0 4 1.333 0.000 0 12 + oserdes_clkdiv_2 4.602 0.000 0 36 0.116 0.000 0 36 0.850 0.000 0 11 + oserdes_clk_3 1.458 0.000 0 4 0.432 0.000 0 4 1.333 0.000 0 12 + oserdes_clkdiv_3 4.618 0.000 0 36 0.109 0.000 0 36 0.850 0.000 0 11 + pll_clk3_out 3.000 0.000 0 3 + clk_div2_bufg_in 4.741 0.000 0 12 0.152 0.000 0 12 2.500 0.000 0 15 + clk_pll_i 5.851 0.000 0 15062 0.034 0.000 0 15062 3.850 0.000 0 6181 + mmcm_ps_clk_bufg_in 22.715 0.000 0 12 0.152 0.000 0 12 11.500 0.000 0 15 + pll_clkfbout 4.751 0.000 0 2 + sync_pulse 1.750 0.000 0 8 + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- +clk_pll_i core_raw 10.968 0.000 0 20 +clk_pll_i ref_raw 18.960 0.000 0 1 +clk_pll_i u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk 12.367 0.000 0 8 44.683 0.000 0 8 +clk_pll_i u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk 12.374 0.000 0 8 44.679 0.000 0 8 +sync_pulse mem_refclk 1.277 0.000 0 1 0.910 0.000 0 1 +oserdes_clk oserdes_clkdiv 2.105 0.000 0 12 -0.247 -1.473 11 12 +oserdes_clk_1 oserdes_clkdiv_1 2.105 0.000 0 13 -0.268 -2.486 12 13 +oserdes_clk_2 oserdes_clkdiv_2 2.105 0.000 0 15 -0.274 -2.156 10 15 +oserdes_clk_3 oserdes_clkdiv_3 2.105 0.000 0 15 -0.197 -1.058 10 15 +core_raw clk_pll_i 38.968 0.000 0 20 +ref_raw clk_pll_i 19.759 0.000 0 12 -1.631 -19.568 12 12 + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- +**async_default** clk_pll_i clk_pll_i 9.663 0.000 0 113 0.295 0.000 0 113 +**async_default** core_raw core_raw 34.624 0.000 0 119 0.295 0.000 0 119 +**default** clk_pll_i 3.113 0.000 0 1 + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + +--------------------------------------------------------------------------------------------------- +From Clock: board_clk + To Clock: board_clk + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 3.000ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: board_clk +Waveform(ns): { 0.000 5.000 } +Period(ns): 10.000 +Sources: { CLK100MHZ } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a MMCME2_ADV/CLKIN1 n/a 1.249 10.000 8.751 clock_mmcm/CLKIN1 +Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 10.000 90.000 clock_mmcm/CLKIN1 +Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 clock_mmcm/CLKIN1 +High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 clock_mmcm/CLKIN1 + + + +--------------------------------------------------------------------------------------------------- +From Clock: core_raw + To Clock: core_raw + +Setup : 0 Failing Endpoints, Worst Slack 14.939ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.045ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 18.750ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 14.939ns (required time - arrival time) + Source: platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5/CLK + (rising edge-triggered cell DSP48E1 clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/frontend/scheduler/subRob/sram/sram_ext/lanes[0].ram_reg_0_7_234_239/RAMA_D1/I + (rising edge-triggered cell RAMD32 clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: core_raw + Path Type: Setup (Max at Slow Process Corner) + Requirement: 40.000ns (core_raw rise@40.000ns - core_raw rise@0.000ns) + Data Path Delay: 24.566ns (logic 19.514ns (79.434%) route 5.052ns (20.566%)) + Logic Levels: 12 (CARRY4=4 DSP48E1=5 LUT2=1 LUT4=1 LUT6=1) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.238ns = ( 37.762 - 40.000 ) + Source Clock Delay (SCD): -1.562ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.091ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.111 -3.045 r clock_mmcm/CLKOUT0 + net (fo=1, unplaced) 0.803 -2.242 core_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r core_buffer/O + net (fo=35560, unplaced) 0.584 -1.562 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/clk + DSP48E1 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5/CLK + ------------------------------------------------------------------- ------------------- + DSP48E1 (Prop_dsp48e1_CLK_P[16]) + 4.009 2.447 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5/P[16] + net (fo=1, unplaced) 0.803 3.250 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5_n_89 + DSP48E1 (Prop_dsp48e1_A[16]_PCOUT[47]) + 4.036 7.286 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0/PCOUT[47] + net (fo=1, unplaced) 0.000 7.286 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0_n_106 + DSP48E1 (Prop_dsp48e1_PCIN[47]_P[19]) + 1.518 8.804 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1/P[19] + net (fo=1, unplaced) 0.803 9.607 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1_n_86 + DSP48E1 (Prop_dsp48e1_C[36]_P[16]) + 1.820 11.427 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2/P[16] + net (fo=1, unplaced) 0.803 12.229 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2_n_89 + DSP48E1 (Prop_dsp48e1_A[16]_PCOUT[47]) + 4.036 16.265 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1/PCOUT[47] + net (fo=1, unplaced) 0.000 16.265 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1_n_106 + DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) + 1.518 17.783 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0/P[0] + net (fo=1, unplaced) 0.803 18.586 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0_n_105 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.659 19.245 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr_carry__3_i_5/CO[3] + net (fo=1, unplaced) 0.000 19.245 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr_carry__3_i_5_n_0 + CARRY4 (Prop_carry4_CI_O[3]) + 0.331 19.576 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr_carry__4_i_5/O[3] + net (fo=1, unplaced) 0.448 20.024 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr0[23] + LUT2 (Prop_lut2_I1_O) 0.307 20.331 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr_carry__5_i_4/O + net (fo=1, unplaced) 0.000 20.331 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr_carry__5_i_4_n_0 + CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 20.844 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr_carry__5/CO[3] + net (fo=1, unplaced) 0.000 20.844 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr_carry__5_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.337 21.181 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr_carry__6/O[1] + net (fo=1, unplaced) 0.611 21.792 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_addrGen_io_outputAddr[30] + LUT4 (Prop_lut4_I1_O) 0.306 22.098 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/lanes[0].ram_reg_0_7_234_239_i_8/O + net (fo=1, unplaced) 0.449 22.547 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_convUnroller_io_cmd_bits_slots_0_bits_dram_addr[26] + LUT6 (Prop_lut6_I5_O) 0.124 22.671 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/lanes[0].ram_reg_0_7_234_239_i_1/O + net (fo=1, unplaced) 0.333 23.004 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/frontend/scheduler/subRob/sram/sram_ext/lanes[0].ram_reg_0_7_234_239/DIA1 + RAMD32 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/frontend/scheduler/subRob/sram/sram_ext/lanes[0].ram_reg_0_7_234_239/RAMA_D1/I + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 40.000 40.000 r + E3 0.000 40.000 r CLK100MHZ (IN) + net (fo=0) 0.000 40.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r input_clock/O + net (fo=1, unplaced) 0.439 41.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.381 36.470 r clock_mmcm/CLKOUT0 + net (fo=1, unplaced) 0.763 37.232 core_raw + BUFG (Prop_bufg_I_O) 0.091 37.323 r core_buffer/O + net (fo=35560, unplaced) 0.439 37.762 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/frontend/scheduler/subRob/sram/sram_ext/lanes[0].ram_reg_0_7_234_239/WCLK + RAMD32 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/frontend/scheduler/subRob/sram/sram_ext/lanes[0].ram_reg_0_7_234_239/RAMA_D1/CLK + clock pessimism 0.531 38.293 + clock uncertainty -0.091 38.202 + RAMD32 (Setup_ramd32_CLK_I) + -0.258 37.944 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/frontend/scheduler/subRob/sram/sram_ext/lanes[0].ram_reg_0_7_234_239/RAMA_D1 + ------------------------------------------------------------------- + required time 37.944 + arrival time -23.004 + ------------------------------------------------------------------- + slack 14.939 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.045ns (arrival time - required time) + Source: btn_meta_reg/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: btn_sync_reg/D + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: core_raw + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (core_raw rise@0.000ns - core_raw rise@0.000ns) + Data Path Delay: 0.228ns (logic 0.147ns (64.493%) route 0.081ns (35.507%)) + Logic Levels: 0 + Clock Path Skew: 0.145ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -1.070ns + Source Clock Delay (SCD): -0.935ns + Clock Pessimism Removal (CPR): -0.280ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.777 -1.414 r clock_mmcm/CLKOUT0 + net (fo=1, unplaced) 0.338 -1.075 core_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r core_buffer/O + net (fo=35560, unplaced) 0.114 -0.935 clk + FDRE r btn_meta_reg/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.147 -0.788 r btn_meta_reg/Q + net (fo=1, unplaced) 0.081 -0.707 btn_meta + FDRE r btn_sync_reg/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.411 -1.715 r clock_mmcm/CLKOUT0 + net (fo=1, unplaced) 0.356 -1.358 core_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r core_buffer/O + net (fo=35560, unplaced) 0.259 -1.070 clk + FDRE r btn_sync_reg/C + clock pessimism 0.280 -0.790 + FDRE (Hold_fdre_C_D) 0.038 -0.752 btn_sync_reg + ------------------------------------------------------------------- + required time 0.752 + arrival time -0.707 + ------------------------------------------------------------------- + slack 0.045 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: core_raw +Waveform(ns): { 0.000 20.000 } +Period(ns): 40.000 +Sources: { clock_mmcm/CLKOUT0 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a DSP48E1/CLK n/a 3.884 40.000 36.116 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg/CLK +Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 40.000 173.360 clock_mmcm/CLKOUT0 +Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMA/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMA/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: fb + To Clock: fb + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 7.845ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: fb +Waveform(ns): { 0.000 5.000 } +Period(ns): 10.000 +Sources: { clock_mmcm/CLKFBOUT } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFG/I n/a 2.155 10.000 7.845 fb_buffer/I +Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 10.000 90.000 clock_mmcm/CLKFBIN + + + +--------------------------------------------------------------------------------------------------- +From Clock: ref_raw + To Clock: ref_raw + +Setup : 0 Failing Endpoints, Worst Slack 2.263ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.045ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 0.264ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 2.263ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r2_reg/C + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.sample_timer_reg[0]/R + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: ref_raw + Path Type: Setup (Max at Slow Process Corner) + Requirement: 5.000ns (ref_raw rise@5.000ns - ref_raw rise@0.000ns) + Data Path Delay: 1.968ns (logic 0.773ns (39.278%) route 1.195ns (60.722%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.238ns = ( 2.762 - 5.000 ) + Source Clock Delay (SCD): -1.562ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -5.111 -3.045 r clock_mmcm/CLKOUT2 + net (fo=1, unplaced) 0.803 -2.242 ref_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r ref_buffer/O + net (fo=67, unplaced) 0.584 -1.562 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/clk_ref_i + FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r2_reg/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.478 -1.084 r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r2_reg/Q + net (fo=32, unplaced) 0.541 -0.543 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r2 + LUT2 (Prop_lut2_I0_O) 0.295 -0.248 r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.sample_timer[10]_i_1/O + net (fo=11, unplaced) 0.654 0.406 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.sample_timer0__20 + FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.sample_timer_reg[0]/R + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 5.000 5.000 r + E3 0.000 5.000 r CLK100MHZ (IN) + net (fo=0) 0.000 5.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 6.411 r input_clock/O + net (fo=1, unplaced) 0.439 6.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -5.381 1.470 r clock_mmcm/CLKOUT2 + net (fo=1, unplaced) 0.763 2.232 ref_raw + BUFG (Prop_bufg_I_O) 0.091 2.323 r ref_buffer/O + net (fo=67, unplaced) 0.439 2.762 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/clk_ref_i + FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.sample_timer_reg[0]/C + clock pessimism 0.531 3.293 + clock uncertainty -0.067 3.226 + FDRE (Setup_fdre_C_R) -0.557 2.669 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.sample_timer_reg[0] + ------------------------------------------------------------------- + required time 2.669 + arrival time -0.406 + ------------------------------------------------------------------- + slack 2.263 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.045ns (arrival time - required time) + Source: btn_ref_meta_reg/C + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: btn_ref_sync_reg/D + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: ref_raw + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (ref_raw rise@0.000ns - ref_raw rise@0.000ns) + Data Path Delay: 0.228ns (logic 0.147ns (64.493%) route 0.081ns (35.507%)) + Logic Levels: 0 + Clock Path Skew: 0.145ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -1.070ns + Source Clock Delay (SCD): -0.935ns + Clock Pessimism Removal (CPR): -0.280ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -1.777 -1.414 r clock_mmcm/CLKOUT2 + net (fo=1, unplaced) 0.338 -1.075 ref_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r ref_buffer/O + net (fo=67, unplaced) 0.114 -0.935 ref_clk + FDRE r btn_ref_meta_reg/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.147 -0.788 r btn_ref_meta_reg/Q + net (fo=1, unplaced) 0.081 -0.707 btn_ref_meta + FDRE r btn_ref_sync_reg/D + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -2.411 -1.715 r clock_mmcm/CLKOUT2 + net (fo=1, unplaced) 0.356 -1.358 ref_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r ref_buffer/O + net (fo=67, unplaced) 0.259 -1.070 ref_clk + FDRE r btn_ref_sync_reg/C + clock pessimism 0.280 -0.790 + FDRE (Hold_fdre_C_D) 0.038 -0.752 btn_ref_sync_reg + ------------------------------------------------------------------- + required time 0.752 + arrival time -0.707 + ------------------------------------------------------------------- + slack 0.045 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: ref_raw +Waveform(ns): { 0.000 2.500 } +Period(ns): 5.000 +Sources: { clock_mmcm/CLKOUT2 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a XADC/DCLK n/a 4.000 5.000 1.000 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.XADC_inst/DCLK +Max Period n/a IDELAYCTRL/REFCLK n/a 5.264 5.000 0.264 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/u_idelayctrl_200/REFCLK +Low Pulse Width Slow FDRE/C n/a 0.500 2.500 2.000 btn_ref_meta_reg/C +High Pulse Width Slow FDRE/C n/a 0.500 2.500 2.000 btn_ref_meta_reg/C + + + +--------------------------------------------------------------------------------------------------- +From Clock: sys_raw + To Clock: sys_raw + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.500ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: sys_raw +Waveform(ns): { 0.000 3.000 } +Period(ns): 6.000 +Sources: { clock_mmcm/CLKOUT1 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFG/I n/a 2.155 6.000 3.845 sys_buffer/I +Max Period n/a PLLE2_ADV/CLKIN1 n/a 52.633 6.000 46.633 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 +Low Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 1.500 3.000 1.500 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 +High Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 1.500 3.000 1.500 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 + + + +--------------------------------------------------------------------------------------------------- +From Clock: freq_refclk + To Clock: freq_refclk + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 0.187ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: freq_refclk +Waveform(ns): { 0.000 0.750 } +Period(ns): 1.500 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a PHASER_OUT_PHY/FREQREFCLK n/a 1.250 1.500 0.250 PHASER_OUT_PHY_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/FREQREFCLK +Max Period n/a PHASER_OUT_PHY/FREQREFCLK n/a 2.500 1.500 1.000 PHASER_OUT_PHY_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/FREQREFCLK +Low Pulse Width Slow PHASER_REF/CLKIN n/a 0.562 0.750 0.188 PHASER_REF_X1Y1 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i/CLKIN +High Pulse Width Slow PHASER_OUT_PHY/FREQREFCLK n/a 0.563 0.750 0.187 PHASER_OUT_PHY_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/FREQREFCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk + To Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a ISERDESE2/CLK n/a 1.667 3.000 1.333 ILOGIC_X1Y76 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: iserdes_clkdiv + To Clock: iserdes_clkdiv + +Setup : 0 Failing Endpoints, Worst Slack 9.972ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.071ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 3.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 9.972ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLKDIVP + (rising edge-triggered cell ISERDESE2 clocked by iserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/D1[3] + (rising edge-triggered cell IN_FIFO clocked by iserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: iserdes_clkdiv + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (iserdes_clkdiv rise@12.000ns - iserdes_clkdiv rise@0.000ns) + Data Path Delay: 0.956ns (logic 0.425ns (44.456%) route 0.531ns (55.544%)) + Logic Levels: 0 + Clock Path Skew: -0.450ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.533ns = ( 12.533 - 12.000 ) + Source Clock Delay (SCD): 1.637ns + Clock Pessimism Removal (CPR): 0.654ns + Clock Uncertainty: 0.051ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.073ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock iserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, estimated) 0.607 -0.648 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.662 1.014 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.173 1.187 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, estimated) 0.450 1.637 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/iserdes_clkdiv + ILOGIC_X1Y76 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLKDIVP + ------------------------------------------------------------------- ------------------- + ILOGIC_X1Y76 ISERDESE2 (Prop_iserdese2_CLKDIVP_Q1) + 0.425 2.062 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/Q1 + net (fo=1, estimated) 0.531 2.593 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/if_d1[3] + IN_FIFO_X1Y6 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/D1[3] + ------------------------------------------------------------------- ------------------- + + (clock iserdes_clkdiv rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, unplaced) 0.439 13.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 8.470 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 9.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 9.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 10.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.083 10.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, estimated) 0.577 10.746 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.624 12.370 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.163 12.533 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, estimated) 0.000 12.533 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clkdiv + IN_FIFO_X1Y6 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK + clock pessimism 0.654 13.187 + clock uncertainty -0.051 13.136 + IN_FIFO_X1Y6 IN_FIFO (Setup_in_fifo_WRCLK_D1[3]) + -0.571 12.565 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo + ------------------------------------------------------------------- + required time 12.565 + arrival time -2.593 + ------------------------------------------------------------------- + slack 9.972 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.071ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV + (rising edge-triggered cell PHASER_IN_PHY clocked by iserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WREN + (rising edge-triggered cell IN_FIFO clocked by iserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: iserdes_clkdiv + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (iserdes_clkdiv rise@0.000ns - iserdes_clkdiv rise@0.000ns) + Data Path Delay: 0.058ns (logic 0.058ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.826ns + Source Clock Delay (SCD): 1.042ns + Clock Pessimism Removal (CPR): -0.216ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock iserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, estimated) 0.256 -0.405 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.357 0.952 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.090 1.042 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV + ------------------------------------------------------------------- ------------------- + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_ICLKDIV_WRENABLE) + 0.058 1.100 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/WRENABLE + net (fo=1, estimated) 0.000 1.100 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ififo_wr_enable + IN_FIFO_X1Y6 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WREN + ------------------------------------------------------------------- ------------------- + + (clock iserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, estimated) 0.269 -0.651 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.381 0.730 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.096 0.826 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, estimated) 0.000 0.826 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clkdiv + IN_FIFO_X1Y6 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK + clock pessimism 0.216 1.042 + IN_FIFO_X1Y6 IN_FIFO (Hold_in_fifo_WRCLK_WREN) + -0.013 1.029 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo + ------------------------------------------------------------------- + required time -1.029 + arrival time 1.100 + ------------------------------------------------------------------- + slack 0.071 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: iserdes_clkdiv +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a IN_FIFO/WRCLK n/a 5.000 12.000 7.000 IN_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK +Low Pulse Width Slow IN_FIFO/WRCLK n/a 2.150 6.000 3.850 IN_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK +High Pulse Width Slow IN_FIFO/WRCLK n/a 2.150 6.000 3.850 IN_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk + To Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a ISERDESE2/CLK n/a 1.667 3.000 1.333 ILOGIC_X1Y88 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: iserdes_clkdiv_1 + To Clock: iserdes_clkdiv_1 + +Setup : 0 Failing Endpoints, Worst Slack 9.955ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.071ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 3.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 9.955ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLKDIVP + (rising edge-triggered cell ISERDESE2 clocked by iserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/D1[3] + (rising edge-triggered cell IN_FIFO clocked by iserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: iserdes_clkdiv_1 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (iserdes_clkdiv_1 rise@12.000ns - iserdes_clkdiv_1 rise@0.000ns) + Data Path Delay: 0.956ns (logic 0.425ns (44.456%) route 0.531ns (55.544%)) + Logic Levels: 0 + Clock Path Skew: -0.467ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.523ns = ( 12.523 - 12.000 ) + Source Clock Delay (SCD): 1.644ns + Clock Pessimism Removal (CPR): 0.654ns + Clock Uncertainty: 0.051ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.073ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock iserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, estimated) 0.597 -0.658 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.662 1.004 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.173 1.177 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, estimated) 0.467 1.644 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/iserdes_clkdiv + ILOGIC_X1Y88 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLKDIVP + ------------------------------------------------------------------- ------------------- + ILOGIC_X1Y88 ISERDESE2 (Prop_iserdese2_CLKDIVP_Q1) + 0.425 2.069 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/Q1 + net (fo=1, estimated) 0.531 2.600 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/if_d1[3] + IN_FIFO_X1Y7 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/D1[3] + ------------------------------------------------------------------- ------------------- + + (clock iserdes_clkdiv_1 rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, unplaced) 0.439 13.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 8.470 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 9.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 9.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 10.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.083 10.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, estimated) 0.567 10.736 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.624 12.360 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.163 12.523 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, estimated) 0.000 12.523 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clkdiv + IN_FIFO_X1Y7 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK + clock pessimism 0.654 13.177 + clock uncertainty -0.051 13.126 + IN_FIFO_X1Y7 IN_FIFO (Setup_in_fifo_WRCLK_D1[3]) + -0.571 12.555 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo + ------------------------------------------------------------------- + required time 12.555 + arrival time -2.600 + ------------------------------------------------------------------- + slack 9.955 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.071ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV + (rising edge-triggered cell PHASER_IN_PHY clocked by iserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WREN + (rising edge-triggered cell IN_FIFO clocked by iserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: iserdes_clkdiv_1 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (iserdes_clkdiv_1 rise@0.000ns - iserdes_clkdiv_1 rise@0.000ns) + Data Path Delay: 0.058ns (logic 0.058ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.821ns + Source Clock Delay (SCD): 1.037ns + Clock Pessimism Removal (CPR): -0.216ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock iserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, estimated) 0.252 -0.409 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.357 0.947 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.090 1.037 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV + ------------------------------------------------------------------- ------------------- + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_ICLKDIV_WRENABLE) + 0.058 1.095 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/WRENABLE + net (fo=1, estimated) 0.000 1.095 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ififo_wr_enable + IN_FIFO_X1Y7 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WREN + ------------------------------------------------------------------- ------------------- + + (clock iserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, estimated) 0.265 -0.655 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.381 0.725 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.096 0.821 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, estimated) 0.000 0.821 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clkdiv + IN_FIFO_X1Y7 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK + clock pessimism 0.216 1.037 + IN_FIFO_X1Y7 IN_FIFO (Hold_in_fifo_WRCLK_WREN) + -0.013 1.024 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo + ------------------------------------------------------------------- + required time -1.024 + arrival time 1.095 + ------------------------------------------------------------------- + slack 0.071 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: iserdes_clkdiv_1 +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a IN_FIFO/WRCLK n/a 5.000 12.000 7.000 IN_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK +Low Pulse Width Slow IN_FIFO/WRCLK n/a 2.150 6.000 3.850 IN_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK +High Pulse Width Slow IN_FIFO/WRCLK n/a 2.150 6.000 3.850 IN_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: mem_refclk + To Clock: mem_refclk + +Setup : 0 Failing Endpoints, Worst Slack 1.810ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.375ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 0.875ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.810ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLMSTREMPTY + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: mem_refclk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (mem_refclk rise@3.000ns - mem_refclk rise@0.000ns) + Data Path Delay: 1.093ns (logic 0.622ns (56.908%) route 0.471ns (43.092%)) + Logic Levels: 0 + Clock Path Skew: -0.031ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.241ns = ( 1.759 - 3.000 ) + Source Clock Delay (SCD): -0.634ns + Clock Pessimism Removal (CPR): 0.576ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.621 -0.634 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + ------------------------------------------------------------------- ------------------- + PHY_CONTROL_X1Y1 PHY_CONTROL (Prop_phy_control_MEMREFCLK_PHYCTLEMPTY) + 0.622 -0.012 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLEMPTY + net (fo=1, estimated) 0.471 0.459 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i_n_1 + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLMSTREMPTY + ------------------------------------------------------------------- ------------------- + + (clock mem_refclk rise edge) + 3.000 3.000 r + E3 0.000 3.000 r CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 4.411 r input_clock/O + net (fo=1, unplaced) 0.439 4.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 -0.530 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 0.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 0.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 1.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 1.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.590 1.759 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + clock pessimism 0.576 2.335 + clock uncertainty -0.054 2.280 + PHY_CONTROL_X1Y1 PHY_CONTROL (Setup_phy_control_MEMREFCLK_PHYCTLMSTREMPTY) + -0.011 2.269 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i + ------------------------------------------------------------------- + required time 2.269 + arrival time -0.459 + ------------------------------------------------------------------- + slack 1.810 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.375ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLMSTREMPTY + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: mem_refclk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mem_refclk rise@0.000ns - mem_refclk rise@0.000ns) + Data Path Delay: 0.512ns (logic 0.313ns (61.188%) route 0.199ns (38.812%)) + Logic Levels: 0 + Clock Path Skew: 0.014ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.645ns + Source Clock Delay (SCD): -0.399ns + Clock Pessimism Removal (CPR): -0.259ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.262 -0.399 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + ------------------------------------------------------------------- ------------------- + PHY_CONTROL_X1Y1 PHY_CONTROL (Prop_phy_control_MEMREFCLK_PHYCTLEMPTY) + 0.313 -0.086 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLEMPTY + net (fo=1, estimated) 0.199 0.112 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i_n_1 + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLMSTREMPTY + ------------------------------------------------------------------- ------------------- + + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.276 -0.645 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + clock pessimism 0.259 -0.385 + PHY_CONTROL_X1Y1 PHY_CONTROL (Hold_phy_control_MEMREFCLK_PHYCTLMSTREMPTY) + 0.123 -0.262 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i + ------------------------------------------------------------------- + required time 0.262 + arrival time 0.112 + ------------------------------------------------------------------- + slack 0.375 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: mem_refclk +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a PHY_CONTROL/MEMREFCLK n/a 1.475 3.000 1.525 PHY_CONTROL_X1Y1 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK +Max Period n/a PLLE2_ADV/CLKOUT1 n/a 160.000 3.000 157.000 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 +Low Pulse Width Slow PHY_CONTROL/MEMREFCLK n/a 0.625 1.500 0.875 PHY_CONTROL_X1Y1 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK +High Pulse Width Slow PHY_CONTROL/MEMREFCLK n/a 0.625 1.500 0.875 PHY_CONTROL_X1Y1 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk + To Clock: oserdes_clk + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clk +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OSERDESE2/CLK n/a 1.667 3.000 1.333 OLOGIC_X1Y51 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[0].oserdes_dq_.sdr.oserdes_dq_i/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clkdiv + To Clock: oserdes_clkdiv + +Setup : 0 Failing Endpoints, Worst Slack 10.094ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.113ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 3.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 10.094ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[11].oserdes_dq_.sdr.oserdes_dq_i/D4 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (oserdes_clkdiv rise@12.000ns - oserdes_clkdiv rise@0.000ns) + Data Path Delay: 1.662ns (logic 0.674ns (40.554%) route 0.988ns (59.446%)) + Logic Levels: 0 + Clock Path Skew: 0.435ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.706ns = ( 13.706 - 12.000 ) + Source Clock Delay (SCD): 1.950ns + Clock Pessimism Removal (CPR): 0.679ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.614 -0.641 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 1.793 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.157 1.950 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, estimated) 0.000 1.950 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/oserdes_clkdiv + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y4 OUT_FIFO (Prop_out_fifo_RDCLK_Q6[7]) + 0.674 2.624 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/Q6[7] + net (fo=1, estimated) 0.988 3.612 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/oserdes_dq[43] + OLOGIC_X1Y50 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[11].oserdes_dq_.sdr.oserdes_dq_i/D4 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, unplaced) 0.439 13.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 8.470 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 9.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 9.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 10.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 10.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.583 10.752 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 13.123 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 13.271 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, estimated) 0.435 13.706 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y50 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[11].oserdes_dq_.sdr.oserdes_dq_i/CLKDIV + clock pessimism 0.679 14.385 + clock uncertainty -0.054 14.330 + OLOGIC_X1Y50 OSERDESE2 (Setup_oserdese2_CLKDIV_D4) + -0.625 13.705 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[11].oserdes_dq_.sdr.oserdes_dq_i + ------------------------------------------------------------------- + required time 13.705 + arrival time -3.612 + ------------------------------------------------------------------- + slack 10.094 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.113ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/D3 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv rise@0.000ns - oserdes_clkdiv rise@0.000ns) + Data Path Delay: 0.336ns (logic 0.138ns (41.109%) route 0.198ns (58.891%)) + Logic Levels: 0 + Clock Path Skew: 0.203ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.784ns + Source Clock Delay (SCD): 1.773ns + Clock Pessimism Removal (CPR): -0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.259 -0.402 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.690 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.083 1.773 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, estimated) 0.000 1.773 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/oserdes_clkdiv + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y4 OUT_FIFO (Prop_out_fifo_RDCLK_Q2[2]) + 0.138 1.911 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/Q2[2] + net (fo=1, estimated) 0.198 2.109 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/oserdes_dq[10] + OLOGIC_X1Y53 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/D3 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.272 -0.648 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.493 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.581 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, estimated) 0.203 1.784 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y53 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/CLKDIV + clock pessimism 0.192 1.976 + OLOGIC_X1Y53 OSERDESE2 (Hold_oserdese2_CLKDIV_D3) + 0.019 1.995 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i + ------------------------------------------------------------------- + required time -1.995 + arrival time 2.109 + ------------------------------------------------------------------- + slack 0.113 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clkdiv +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OUT_FIFO/RDCLK n/a 5.000 12.000 7.000 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK +Low Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK +High Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_1 + To Clock: oserdes_clk_1 + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clk_1 +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OSERDESE2/CLK n/a 1.667 3.000 1.333 OLOGIC_X1Y63 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[0].oserdes_dq_.sdr.oserdes_dq_i/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clkdiv_1 + To Clock: oserdes_clkdiv_1 + +Setup : 0 Failing Endpoints, Worst Slack 10.595ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.119ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 3.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 10.595ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[10].oserdes_dq_.sdr.oserdes_dq_i/D1 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv_1 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (oserdes_clkdiv_1 rise@12.000ns - oserdes_clkdiv_1 rise@0.000ns) + Data Path Delay: 1.144ns (logic 0.674ns (58.916%) route 0.470ns (41.084%)) + Logic Levels: 0 + Clock Path Skew: 0.419ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.679ns = ( 13.679 - 12.000 ) + Source Clock Delay (SCD): 1.939ns + Clock Pessimism Removal (CPR): 0.678ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.603 -0.652 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 1.782 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.157 1.939 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, estimated) 0.000 1.939 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/oserdes_clkdiv + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y5 OUT_FIFO (Prop_out_fifo_RDCLK_Q5[4]) + 0.674 2.613 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/Q5[4] + net (fo=1, estimated) 0.470 3.083 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/oserdes_dq[40] + OLOGIC_X1Y69 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[10].oserdes_dq_.sdr.oserdes_dq_i/D1 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_1 rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, unplaced) 0.439 13.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 8.470 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 9.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 9.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 10.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 10.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.573 10.742 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 13.112 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 13.260 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, estimated) 0.419 13.679 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y69 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[10].oserdes_dq_.sdr.oserdes_dq_i/CLKDIV + clock pessimism 0.678 14.358 + clock uncertainty -0.054 14.303 + OLOGIC_X1Y69 OSERDESE2 (Setup_oserdese2_CLKDIV_D1) + -0.625 13.678 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[10].oserdes_dq_.sdr.oserdes_dq_i + ------------------------------------------------------------------- + required time 13.678 + arrival time -3.083 + ------------------------------------------------------------------- + slack 10.595 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.119ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/D3 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv_1 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_1 rise@0.000ns - oserdes_clkdiv_1 rise@0.000ns) + Data Path Delay: 0.336ns (logic 0.138ns (41.109%) route 0.198ns (58.891%)) + Logic Levels: 0 + Clock Path Skew: 0.197ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.773ns + Source Clock Delay (SCD): 1.768ns + Clock Pessimism Removal (CPR): -0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.254 -0.407 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.685 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.083 1.768 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, estimated) 0.000 1.768 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/oserdes_clkdiv + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y5 OUT_FIFO (Prop_out_fifo_RDCLK_Q2[2]) + 0.138 1.906 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/Q2[2] + net (fo=1, estimated) 0.198 2.104 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/oserdes_dq[10] + OLOGIC_X1Y65 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/D3 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.268 -0.653 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.488 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.576 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, estimated) 0.197 1.773 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y65 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/CLKDIV + clock pessimism 0.192 1.966 + OLOGIC_X1Y65 OSERDESE2 (Hold_oserdese2_CLKDIV_D3) + 0.019 1.985 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i + ------------------------------------------------------------------- + required time -1.985 + arrival time 2.104 + ------------------------------------------------------------------- + slack 0.119 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clkdiv_1 +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OUT_FIFO/RDCLK n/a 5.000 12.000 7.000 OUT_FIFO_X1Y5 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK +Low Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y5 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK +High Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y5 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_2 + To Clock: oserdes_clk_2 + +Setup : 0 Failing Endpoints, Worst Slack 1.442ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.440ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.442ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqsts/D1 + (rising edge-triggered cell ODDR clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: oserdes_clk_2 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clk_2 rise@3.000ns - oserdes_clk_2 rise@0.000ns) + Data Path Delay: 1.041ns (logic 0.562ns (53.987%) route 0.479ns (46.013%)) + Logic Levels: 0 + Clock Path Skew: 0.423ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.285ns = ( 5.285 - 3.000 ) + Source Clock Delay (SCD): 2.577ns + Clock Pessimism Removal (CPR): 0.715ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.614 -0.641 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 1.793 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.784 2.577 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLKDELAYED_CTSBUS[0]) + 0.562 3.139 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/CTSBUS[0] + net (fo=2, estimated) 0.479 3.618 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/CTSBUS[0] + OLOGIC_X1Y82 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqsts/D1 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clk_2 rise edge) + 3.000 3.000 r + E3 0.000 3.000 r CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 4.411 r input_clock/O + net (fo=1, unplaced) 0.439 4.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 -0.530 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 0.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 0.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 1.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 1.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.583 1.752 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 4.123 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.739 4.862 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + net (fo=2, estimated) 0.423 5.285 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/oserdes_clk_delayed + OLOGIC_X1Y82 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqsts/C + clock pessimism 0.715 6.000 + clock uncertainty -0.054 5.945 + OLOGIC_X1Y82 ODDR (Setup_oddr_C_D1) -0.885 5.060 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqsts + ------------------------------------------------------------------- + required time 5.060 + arrival time -3.618 + ------------------------------------------------------------------- + slack 1.442 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.440ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqs/D1 + (rising edge-triggered cell ODDR clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: oserdes_clk_2 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clk_2 rise@0.000ns - oserdes_clk_2 rise@0.000ns) + Data Path Delay: 0.544ns (logic 0.346ns (63.590%) route 0.198ns (36.410%)) + Logic Levels: 0 + Clock Path Skew: 0.197ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 2.360ns + Source Clock Delay (SCD): 2.320ns + Clock Pessimism Removal (CPR): -0.158ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.259 -0.402 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.690 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.630 2.320 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLKDELAYED_DQSBUS[0]) + 0.346 2.666 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/DQSBUS[0] + net (fo=1, estimated) 0.198 2.865 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/DQSBUS[0] + OLOGIC_X1Y82 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqs/D1 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clk_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.272 -0.648 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.493 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.670 2.163 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + net (fo=2, estimated) 0.197 2.360 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/oserdes_clk_delayed + OLOGIC_X1Y82 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqs/C + clock pessimism 0.158 2.518 + OLOGIC_X1Y82 ODDR (Hold_oddr_C_D1) -0.093 2.425 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqs + ------------------------------------------------------------------- + required time -2.425 + arrival time 2.865 + ------------------------------------------------------------------- + slack 0.440 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clk_2 +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OSERDESE2/CLK n/a 1.667 3.000 1.333 OLOGIC_X1Y76 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[1].oserdes_dq_.ddr.oserdes_dq_i/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clkdiv_2 + To Clock: oserdes_clkdiv_2 + +Setup : 0 Failing Endpoints, Worst Slack 4.602ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.116ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 0.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 4.602ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/D1 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_2 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 6.000ns (oserdes_clkdiv_2 rise@6.000ns - oserdes_clkdiv_2 rise@0.000ns) + Data Path Delay: 1.144ns (logic 0.674ns (58.916%) route 0.470ns (41.084%)) + Logic Levels: 0 + Clock Path Skew: 0.426ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.696ns = ( 7.696 - 6.000 ) + Source Clock Delay (SCD): 1.950ns + Clock Pessimism Removal (CPR): 0.679ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.614 -0.641 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 1.793 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.157 1.950 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, estimated) 0.000 1.950 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/oserdes_clkdiv + OUT_FIFO_X1Y6 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y6 OUT_FIFO (Prop_out_fifo_RDCLK_Q6[0]) + 0.674 2.624 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/Q6[0] + net (fo=1, estimated) 0.470 3.094 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/of_dqbus[20] + OLOGIC_X1Y83 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/D1 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_2 rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, unplaced) 0.439 7.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 2.470 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 3.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 3.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 4.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 4.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.583 4.752 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 7.123 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 7.271 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, estimated) 0.426 7.696 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y83 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV + clock pessimism 0.679 8.375 + clock uncertainty -0.054 8.321 + OLOGIC_X1Y83 OSERDESE2 (Setup_oserdese2_CLKDIV_D1) + -0.625 7.696 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i + ------------------------------------------------------------------- + required time 7.696 + arrival time -3.094 + ------------------------------------------------------------------- + slack 4.602 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.116ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D3 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_2 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_2 rise@0.000ns - oserdes_clkdiv_2 rise@0.000ns) + Data Path Delay: 0.336ns (logic 0.138ns (41.109%) route 0.198ns (58.891%)) + Logic Levels: 0 + Clock Path Skew: 0.201ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.781ns + Source Clock Delay (SCD): 1.773ns + Clock Pessimism Removal (CPR): -0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.259 -0.402 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.690 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.083 1.773 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, estimated) 0.000 1.773 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/oserdes_clkdiv + OUT_FIFO_X1Y6 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y6 OUT_FIFO (Prop_out_fifo_RDCLK_Q2[2]) + 0.138 1.911 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/Q2[2] + net (fo=1, estimated) 0.198 2.109 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/of_dqbus[6] + OLOGIC_X1Y77 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D3 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.272 -0.648 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.493 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.581 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, estimated) 0.201 1.781 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y77 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV + clock pessimism 0.192 1.974 + OLOGIC_X1Y77 OSERDESE2 (Hold_oserdese2_CLKDIV_D3) + 0.019 1.993 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i + ------------------------------------------------------------------- + required time -1.993 + arrival time 2.109 + ------------------------------------------------------------------- + slack 0.116 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clkdiv_2 +Waveform(ns): { 0.000 3.000 } +Period(ns): 6.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OUT_FIFO/RDCLK n/a 5.000 6.000 1.000 OUT_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK +Low Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 3.000 0.850 OUT_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK +High Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 3.000 0.850 OUT_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_3 + To Clock: oserdes_clk_3 + +Setup : 0 Failing Endpoints, Worst Slack 1.458ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.432ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.458ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqsts/D1 + (rising edge-triggered cell ODDR clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: oserdes_clk_3 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clk_3 rise@3.000ns - oserdes_clk_3 rise@0.000ns) + Data Path Delay: 1.041ns (logic 0.562ns (53.987%) route 0.479ns (46.013%)) + Logic Levels: 0 + Clock Path Skew: 0.439ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.290ns = ( 5.290 - 3.000 ) + Source Clock Delay (SCD): 2.566ns + Clock Pessimism Removal (CPR): 0.714ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.603 -0.652 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 1.782 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.784 2.566 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLKDELAYED_CTSBUS[0]) + 0.562 3.128 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/CTSBUS[0] + net (fo=2, estimated) 0.479 3.607 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/CTSBUS[0] + OLOGIC_X1Y94 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqsts/D1 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clk_3 rise edge) + 3.000 3.000 r + E3 0.000 3.000 r CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 4.411 r input_clock/O + net (fo=1, unplaced) 0.439 4.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 -0.530 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 0.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 0.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 1.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 1.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.573 1.742 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 4.112 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.739 4.851 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + net (fo=2, estimated) 0.439 5.290 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/oserdes_clk_delayed + OLOGIC_X1Y94 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqsts/C + clock pessimism 0.714 6.005 + clock uncertainty -0.054 5.950 + OLOGIC_X1Y94 ODDR (Setup_oddr_C_D1) -0.885 5.065 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqsts + ------------------------------------------------------------------- + required time 5.065 + arrival time -3.607 + ------------------------------------------------------------------- + slack 1.458 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.432ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqs/D1 + (rising edge-triggered cell ODDR clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: oserdes_clk_3 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clk_3 rise@0.000ns - oserdes_clk_3 rise@0.000ns) + Data Path Delay: 0.544ns (logic 0.346ns (63.590%) route 0.198ns (36.410%)) + Logic Levels: 0 + Clock Path Skew: 0.205ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 2.363ns + Source Clock Delay (SCD): 2.316ns + Clock Pessimism Removal (CPR): -0.158ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.254 -0.407 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.685 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.630 2.316 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLKDELAYED_DQSBUS[0]) + 0.346 2.662 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/DQSBUS[0] + net (fo=1, estimated) 0.198 2.860 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/DQSBUS[0] + OLOGIC_X1Y94 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqs/D1 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clk_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.268 -0.653 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.488 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.670 2.158 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + net (fo=2, estimated) 0.205 2.363 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/oserdes_clk_delayed + OLOGIC_X1Y94 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqs/C + clock pessimism 0.158 2.521 + OLOGIC_X1Y94 ODDR (Hold_oddr_C_D1) -0.093 2.428 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqs + ------------------------------------------------------------------- + required time -2.428 + arrival time 2.860 + ------------------------------------------------------------------- + slack 0.432 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clk_3 +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OSERDESE2/CLK n/a 1.667 3.000 1.333 OLOGIC_X1Y88 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[1].oserdes_dq_.ddr.oserdes_dq_i/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clkdiv_3 + To Clock: oserdes_clkdiv_3 + +Setup : 0 Failing Endpoints, Worst Slack 4.618ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.109ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 0.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 4.618ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/D1 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_3 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 6.000ns (oserdes_clkdiv_3 rise@6.000ns - oserdes_clkdiv_3 rise@0.000ns) + Data Path Delay: 1.144ns (logic 0.674ns (58.916%) route 0.470ns (41.084%)) + Logic Levels: 0 + Clock Path Skew: 0.442ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.702ns = ( 7.702 - 6.000 ) + Source Clock Delay (SCD): 1.939ns + Clock Pessimism Removal (CPR): 0.678ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.603 -0.652 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 1.782 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.157 1.939 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, estimated) 0.000 1.939 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/oserdes_clkdiv + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y7 OUT_FIFO (Prop_out_fifo_RDCLK_Q6[0]) + 0.674 2.613 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/Q6[0] + net (fo=1, estimated) 0.470 3.083 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/of_dqbus[20] + OLOGIC_X1Y95 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/D1 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_3 rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, unplaced) 0.439 7.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 2.470 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 3.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 3.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 4.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 4.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.573 4.742 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 7.112 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 7.260 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, estimated) 0.442 7.702 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y95 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV + clock pessimism 0.678 8.381 + clock uncertainty -0.054 8.326 + OLOGIC_X1Y95 OSERDESE2 (Setup_oserdese2_CLKDIV_D1) + -0.625 7.701 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i + ------------------------------------------------------------------- + required time 7.701 + arrival time -3.083 + ------------------------------------------------------------------- + slack 4.618 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.109ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D3 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_3 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_3 rise@0.000ns - oserdes_clkdiv_3 rise@0.000ns) + Data Path Delay: 0.336ns (logic 0.138ns (41.109%) route 0.198ns (58.891%)) + Logic Levels: 0 + Clock Path Skew: 0.208ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.784ns + Source Clock Delay (SCD): 1.768ns + Clock Pessimism Removal (CPR): -0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.254 -0.407 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.685 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.083 1.768 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, estimated) 0.000 1.768 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/oserdes_clkdiv + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y7 OUT_FIFO (Prop_out_fifo_RDCLK_Q2[2]) + 0.138 1.906 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/Q2[2] + net (fo=1, estimated) 0.198 2.104 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/of_dqbus[6] + OLOGIC_X1Y89 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D3 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.268 -0.653 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.488 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.576 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, estimated) 0.208 1.784 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y89 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV + clock pessimism 0.192 1.976 + OLOGIC_X1Y89 OSERDESE2 (Hold_oserdese2_CLKDIV_D3) + 0.019 1.995 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i + ------------------------------------------------------------------- + required time -1.995 + arrival time 2.104 + ------------------------------------------------------------------- + slack 0.109 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clkdiv_3 +Waveform(ns): { 0.000 3.000 } +Period(ns): 6.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OUT_FIFO/RDCLK n/a 5.000 6.000 1.000 OUT_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK +Low Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 3.000 0.850 OUT_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK +High Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 3.000 0.850 OUT_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: pll_clk3_out + To Clock: pll_clk3_out + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 3.000ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: pll_clk3_out +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFH/I n/a 2.155 12.000 9.845 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/I +Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 12.000 88.000 MMCME2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKIN1 +Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 3.000 6.000 3.000 MMCME2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKIN1 +High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 3.000 6.000 3.000 MMCME2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKIN1 + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_div2_bufg_in + To Clock: clk_div2_bufg_in + +Setup : 0 Failing Endpoints, Worst Slack 4.741ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.152ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 2.500ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 4.741ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r_reg[11]/C + (rising edge-triggered cell FDPE clocked by clk_div2_bufg_in {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r1_reg/D + (rising edge-triggered cell FDPE clocked by clk_div2_bufg_in {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: clk_div2_bufg_in + Path Type: Setup (Max at Slow Process Corner) + Requirement: 6.000ns (clk_div2_bufg_in rise@6.000ns - clk_div2_bufg_in rise@0.000ns) + Data Path Delay: 0.812ns (logic 0.478ns (58.867%) route 0.334ns (41.133%)) + Logic Levels: 0 + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.872ns = ( 5.128 - 6.000 ) + Source Clock Delay (SCD): 0.040ns + Clock Pessimism Removal (CPR): 0.767ns + Clock Uncertainty: 0.082ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.149ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_div2_bufg_in rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.584 -0.671 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.127 -0.544 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.803 0.259 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.702 -1.443 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKOUT1 + net (fo=1, unplaced) 0.803 -0.640 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_div2_bufg_in + BUFG (Prop_bufg_I_O) 0.096 -0.544 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_clk_div2/O + net (fo=13, unplaced) 0.584 0.040 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_clk_div2_n_0 + FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r_reg[11]/C + ------------------------------------------------------------------- ------------------- + FDPE (Prop_fdpe_C_Q) 0.478 0.518 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r_reg[11]/Q + net (fo=1, unplaced) 0.334 0.852 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r[11] + FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r1_reg/D + ------------------------------------------------------------------- ------------------- + + (clock clk_div2_bufg_in rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, unplaced) 0.439 7.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 2.470 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 3.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 3.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 4.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 4.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.439 4.608 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.081 4.689 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.763 5.452 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.616 3.835 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKOUT1 + net (fo=1, unplaced) 0.763 4.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_div2_bufg_in + BUFG (Prop_bufg_I_O) 0.091 4.689 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_clk_div2/O + net (fo=13, unplaced) 0.439 5.128 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_clk_div2_n_0 + FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r1_reg/C + clock pessimism 0.767 5.895 + clock uncertainty -0.082 5.812 + FDPE (Setup_fdpe_C_D) -0.220 5.592 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r1_reg + ------------------------------------------------------------------- + required time 5.592 + arrival time -0.852 + ------------------------------------------------------------------- + slack 4.741 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.152ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r_reg[11]/C + (rising edge-triggered cell FDPE clocked by clk_div2_bufg_in {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r1_reg/D + (rising edge-triggered cell FDPE clocked by clk_div2_bufg_in {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: clk_div2_bufg_in + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_div2_bufg_in rise@0.000ns - clk_div2_bufg_in rise@0.000ns) + Data Path Delay: 0.288ns (logic 0.147ns (51.079%) route 0.141ns (48.921%)) + Logic Levels: 0 + Clock Path Skew: 0.145ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.359ns + Source Clock Delay (SCD): -0.413ns + Clock Pessimism Removal (CPR): -0.091ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_div2_bufg_in rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.114 -0.547 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.020 -0.527 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.338 -0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -0.703 -0.891 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKOUT1 + net (fo=1, unplaced) 0.338 -0.553 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_div2_bufg_in + BUFG (Prop_bufg_I_O) 0.026 -0.527 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_clk_div2/O + net (fo=13, unplaced) 0.114 -0.413 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_clk_div2_n_0 + FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r_reg[11]/C + ------------------------------------------------------------------- ------------------- + FDPE (Prop_fdpe_C_Q) 0.147 -0.266 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r_reg[11]/Q + net (fo=1, unplaced) 0.141 -0.125 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r[11] + FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r1_reg/D + ------------------------------------------------------------------- ------------------- + + (clock clk_div2_bufg_in rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.259 -0.661 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.043 -0.618 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.356 -0.262 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -0.741 -1.003 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKOUT1 + net (fo=1, unplaced) 0.356 -0.647 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_div2_bufg_in + BUFG (Prop_bufg_I_O) 0.029 -0.618 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_clk_div2/O + net (fo=13, unplaced) 0.259 -0.359 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_clk_div2_n_0 + FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r1_reg/C + clock pessimism 0.091 -0.268 + FDPE (Hold_fdpe_C_D) -0.009 -0.277 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r1_reg + ------------------------------------------------------------------- + required time 0.277 + arrival time -0.125 + ------------------------------------------------------------------- + slack 0.152 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: clk_div2_bufg_in +Waveform(ns): { 0.000 3.000 } +Period(ns): 6.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKOUT1 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFG/I n/a 2.155 6.000 3.845 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_clk_div2/I +Max Period n/a MMCME2_ADV/CLKOUT1 n/a 213.360 6.000 207.360 MMCME2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKOUT1 +Low Pulse Width Slow FDPE/C n/a 0.500 3.000 2.500 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r1_reg/C +High Pulse Width Slow FDPE/C n/a 0.500 3.000 2.500 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r1_reg/C + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_pll_i + To Clock: clk_pll_i + +Setup : 0 Failing Endpoints, Worst Slack 5.851ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.034ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 3.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 5.851ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrlvl_done_r1_reg/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_final_chk_reg/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: clk_pll_i + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (clk_pll_i rise@12.000ns - clk_pll_i rise@0.000ns) + Data Path Delay: 5.981ns (logic 1.393ns (23.290%) route 4.588ns (76.710%)) + Logic Levels: 6 (LUT5=1 LUT6=5) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.653ns = ( 11.347 - 12.000 ) + Source Clock Delay (SCD): 0.259ns + Clock Pessimism Removal (CPR): 0.767ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.584 -0.671 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.127 -0.544 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.803 0.259 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.702 -1.443 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, unplaced) 0.803 -0.640 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFG (Prop_bufg_I_O) 0.096 -0.544 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=6179, unplaced) 0.803 0.259 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg[14]_0 + FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrlvl_done_r1_reg/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.478 0.737 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrlvl_done_r1_reg/Q + net (fo=12, unplaced) 1.013 1.750 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrlvl_done_r1 + LUT6 (Prop_lut6_I0_O) 0.295 2.045 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/init_state_r[3]_i_24/O + net (fo=3, unplaced) 0.982 3.027 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/init_state_r[3]_i_24_n_0 + LUT6 (Prop_lut6_I0_O) 0.124 3.151 f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/init_state_r[4]_i_27/O + net (fo=2, unplaced) 0.460 3.611 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/init_state_r[4]_i_27_n_0 + LUT5 (Prop_lut5_I0_O) 0.124 3.735 f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/init_state_r[0]_i_16/O + net (fo=1, unplaced) 0.449 4.184 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/init_state_r[0]_i_16_n_0 + LUT6 (Prop_lut6_I5_O) 0.124 4.308 f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/init_state_r[0]_i_5/O + net (fo=1, unplaced) 0.732 5.040 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/init_state_r[0]_i_5_n_0 + LUT6 (Prop_lut6_I3_O) 0.124 5.164 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/init_state_r[0]_i_1/O + net (fo=2, unplaced) 0.952 6.116 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/init_state_r[0]_i_1_n_0 + LUT6 (Prop_lut6_I0_O) 0.124 6.240 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_final_chk_i_1/O + net (fo=1, unplaced) 0.000 6.240 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_final_chk_i_1_n_0 + FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_final_chk_reg/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, unplaced) 0.439 13.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 8.470 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 9.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 9.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 10.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 10.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.439 10.608 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.081 10.689 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.763 11.452 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.616 9.835 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, unplaced) 0.763 10.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFG (Prop_bufg_I_O) 0.091 10.689 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=6179, unplaced) 0.658 11.347 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg[14]_0 + FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_final_chk_reg/C + clock pessimism 0.767 12.114 + clock uncertainty -0.067 12.046 + FDRE (Setup_fdre_C_D) 0.044 12.090 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_final_chk_reg + ------------------------------------------------------------------- + required time 12.090 + arrival time -6.240 + ------------------------------------------------------------------- + slack 5.851 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.034ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_b_channel_0/bid_t_reg[0]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMB/I + (rising edge-triggered cell RAMD32 clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: clk_pll_i + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_pll_i rise@0.000ns - clk_pll_i rise@0.000ns) + Data Path Delay: 0.272ns (logic 0.131ns (48.199%) route 0.141ns (51.801%)) + Logic Levels: 0 + Clock Path Skew: 0.145ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.316ns + Clock Pessimism Removal (CPR): -0.091ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.114 -0.547 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.020 -0.527 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.338 -0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -0.703 -0.891 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, unplaced) 0.338 -0.553 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFG (Prop_bufg_I_O) 0.026 -0.527 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=6179, unplaced) 0.211 -0.316 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_b_channel_0/cnt_read_reg[0] + FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_b_channel_0/bid_t_reg[0]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.131 -0.185 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_b_channel_0/bid_t_reg[0]/Q + net (fo=1, unplaced) 0.141 -0.044 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/DIB0 + RAMD32 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMB/I + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.259 -0.661 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.043 -0.618 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.356 -0.262 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -0.741 -1.003 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, unplaced) 0.356 -0.647 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFG (Prop_bufg_I_O) 0.029 -0.618 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=6179, unplaced) 0.356 -0.262 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/WCLK + RAMD32 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMB/CLK + clock pessimism 0.091 -0.171 + RAMD32 (Hold_ramd32_CLK_I) + 0.093 -0.078 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMB + ------------------------------------------------------------------- + required time 0.078 + arrival time -0.044 + ------------------------------------------------------------------- + slack 0.034 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: clk_pll_i +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OUT_FIFO/WRCLK n/a 5.000 12.000 7.000 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/WRCLK +Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 12.000 88.000 MMCME2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBIN +Low Pulse Width Slow OUT_FIFO/WRCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/WRCLK +High Pulse Width Slow OUT_FIFO/WRCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/WRCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: mmcm_ps_clk_bufg_in + To Clock: mmcm_ps_clk_bufg_in + +Setup : 0 Failing Endpoints, Worst Slack 22.715ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.152ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 11.500ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 22.715ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r_reg[11]/C + (rising edge-triggered cell FDPE clocked by mmcm_ps_clk_bufg_in {rise@0.000ns fall@12.000ns period=24.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r1_reg/D + (rising edge-triggered cell FDPE clocked by mmcm_ps_clk_bufg_in {rise@0.000ns fall@12.000ns period=24.000ns}) + Path Group: mmcm_ps_clk_bufg_in + Path Type: Setup (Max at Slow Process Corner) + Requirement: 24.000ns (mmcm_ps_clk_bufg_in rise@24.000ns - mmcm_ps_clk_bufg_in rise@0.000ns) + Data Path Delay: 0.812ns (logic 0.478ns (58.867%) route 0.334ns (41.133%)) + Logic Levels: 0 + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.872ns = ( 23.128 - 24.000 ) + Source Clock Delay (SCD): 0.040ns + Clock Pessimism Removal (CPR): 0.767ns + Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.204ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mmcm_ps_clk_bufg_in rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.584 -0.671 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.127 -0.544 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.803 0.259 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.702 -1.443 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKOUT0 + net (fo=1, unplaced) 0.803 -0.640 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_ps_clk_bufg_in + BUFG (Prop_bufg_I_O) 0.096 -0.544 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_mmcm_ps_clk/O + net (fo=13, unplaced) 0.584 0.040 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_mmcm_ps_clk_n_0 + FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r_reg[11]/C + ------------------------------------------------------------------- ------------------- + FDPE (Prop_fdpe_C_Q) 0.478 0.518 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r_reg[11]/Q + net (fo=1, unplaced) 0.334 0.852 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r[11] + FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r1_reg/D + ------------------------------------------------------------------- ------------------- + + (clock mmcm_ps_clk_bufg_in rise edge) + 24.000 24.000 r + E3 0.000 24.000 r CLK100MHZ (IN) + net (fo=0) 0.000 24.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 25.411 r input_clock/O + net (fo=1, unplaced) 0.439 25.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 20.470 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 21.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 21.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 22.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 22.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.439 22.608 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.081 22.689 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.763 23.452 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.616 21.835 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKOUT0 + net (fo=1, unplaced) 0.763 22.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_ps_clk_bufg_in + BUFG (Prop_bufg_I_O) 0.091 22.689 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_mmcm_ps_clk/O + net (fo=13, unplaced) 0.439 23.128 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_mmcm_ps_clk_n_0 + FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r1_reg/C + clock pessimism 0.767 23.895 + clock uncertainty -0.108 23.787 + FDPE (Setup_fdpe_C_D) -0.220 23.567 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r1_reg + ------------------------------------------------------------------- + required time 23.567 + arrival time -0.852 + ------------------------------------------------------------------- + slack 22.715 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.152ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r_reg[11]/C + (rising edge-triggered cell FDPE clocked by mmcm_ps_clk_bufg_in {rise@0.000ns fall@12.000ns period=24.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r1_reg/D + (rising edge-triggered cell FDPE clocked by mmcm_ps_clk_bufg_in {rise@0.000ns fall@12.000ns period=24.000ns}) + Path Group: mmcm_ps_clk_bufg_in + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mmcm_ps_clk_bufg_in rise@0.000ns - mmcm_ps_clk_bufg_in rise@0.000ns) + Data Path Delay: 0.288ns (logic 0.147ns (51.079%) route 0.141ns (48.921%)) + Logic Levels: 0 + Clock Path Skew: 0.145ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.359ns + Source Clock Delay (SCD): -0.413ns + Clock Pessimism Removal (CPR): -0.091ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mmcm_ps_clk_bufg_in rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.114 -0.547 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.020 -0.527 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.338 -0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -0.703 -0.891 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKOUT0 + net (fo=1, unplaced) 0.338 -0.553 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_ps_clk_bufg_in + BUFG (Prop_bufg_I_O) 0.026 -0.527 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_mmcm_ps_clk/O + net (fo=13, unplaced) 0.114 -0.413 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_mmcm_ps_clk_n_0 + FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r_reg[11]/C + ------------------------------------------------------------------- ------------------- + FDPE (Prop_fdpe_C_Q) 0.147 -0.266 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r_reg[11]/Q + net (fo=1, unplaced) 0.141 -0.125 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r[11] + FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r1_reg/D + ------------------------------------------------------------------- ------------------- + + (clock mmcm_ps_clk_bufg_in rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.259 -0.661 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.043 -0.618 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.356 -0.262 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -0.741 -1.003 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKOUT0 + net (fo=1, unplaced) 0.356 -0.647 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_ps_clk_bufg_in + BUFG (Prop_bufg_I_O) 0.029 -0.618 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_mmcm_ps_clk/O + net (fo=13, unplaced) 0.259 -0.359 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_mmcm_ps_clk_n_0 + FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r1_reg/C + clock pessimism 0.091 -0.268 + FDPE (Hold_fdpe_C_D) -0.009 -0.277 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r1_reg + ------------------------------------------------------------------- + required time 0.277 + arrival time -0.125 + ------------------------------------------------------------------- + slack 0.152 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: mmcm_ps_clk_bufg_in +Waveform(ns): { 0.000 12.000 } +Period(ns): 24.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKOUT0 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFG/I n/a 2.155 24.000 21.845 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_mmcm_ps_clk/I +Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 24.000 189.360 MMCME2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKOUT0 +Low Pulse Width Slow FDPE/C n/a 0.500 12.000 11.500 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r1_reg/C +High Pulse Width Slow FDPE/C n/a 0.500 12.000 11.500 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r1_reg/C + + + +--------------------------------------------------------------------------------------------------- +From Clock: pll_clkfbout + To Clock: pll_clkfbout + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 4.751ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: pll_clkfbout +Waveform(ns): { 0.000 3.000 } +Period(ns): 6.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a PLLE2_ADV/CLKFBOUT n/a 1.249 6.000 4.751 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT +Max Period n/a PLLE2_ADV/CLKFBIN n/a 52.633 6.000 46.633 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBIN + + + +--------------------------------------------------------------------------------------------------- +From Clock: sync_pulse + To Clock: sync_pulse + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.750ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: sync_pulse +Waveform(ns): { 1.312 4.312 } +Period(ns): 48.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a PLLE2_ADV/CLKOUT2 n/a 1.249 48.000 46.751 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 +Max Period n/a PLLE2_ADV/CLKOUT2 n/a 160.000 48.000 112.000 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 +High Pulse Width Slow PHASER_OUT_PHY/SYNCIN n/a 1.250 3.000 1.750 PHASER_OUT_PHY_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/SYNCIN + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_pll_i + To Clock: core_raw + +Setup : 0 Failing Endpoints, Worst Slack 10.968ns, Total Violation 0.000ns +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 10.968ns (required time - arrival time) + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: core_raw + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (MaxDelay Path 12.000ns) + Data Path Delay: 0.812ns (logic 0.478ns (58.867%) route 0.334ns (41.133%)) + Logic Levels: 0 + Timing Exception: MaxDelay Path 12.000ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + 0.000 0.000 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C + FDRE (Prop_fdre_C_Q) 0.478 0.478 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, unplaced) 0.334 0.812 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[0] + FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + ------------------------------------------------------------------- ------------------- + + max delay 12.000 12.000 + FDRE (Setup_fdre_C_D) -0.220 11.780 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + ------------------------------------------------------------------- + required time 11.780 + arrival time -0.812 + ------------------------------------------------------------------- + slack 10.968 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_pll_i + To Clock: ref_raw + +Setup : 0 Failing Endpoints, Worst Slack 18.960ns, Total Violation 0.000ns +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 18.960ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg/D + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: ref_raw + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (MaxDelay Path 20.000ns) + Data Path Delay: 1.084ns (logic 0.773ns (71.310%) route 0.311ns (28.690%)) + Logic Levels: 1 (LUT1=1) + Timing Exception: MaxDelay Path 20.000ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + 0.000 0.000 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + FDPE (Prop_fdpe_C_Q) 0.478 0.478 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/Q + net (fo=1, unplaced) 0.311 0.789 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep_n_0 + LUT1 (Prop_lut1_I0_O) 0.295 1.084 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_inst/O + net (fo=50, unplaced) 0.000 1.084 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg_0 + FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg/D + ------------------------------------------------------------------- ------------------- + + max delay 20.000 20.000 + FDRE (Setup_fdre_C_D) 0.044 20.044 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg + ------------------------------------------------------------------- + required time 20.044 + arrival time -1.084 + ------------------------------------------------------------------- + slack 18.960 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_pll_i + To Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk + +Setup : 0 Failing Endpoints, Worst Slack 12.367ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 44.683ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 12.367ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq/DDLY + (falling edge-triggered cell ISERDESE2 clocked by u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 16.500ns (u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk fall@16.500ns - clk_pll_i rise@0.000ns) + Data Path Delay: 4.867ns (logic 4.064ns (83.504%) route 0.803ns (16.496%)) + Logic Levels: 2 (IBUF_INTERMDISABLE=1 IDELAYE2=1) + Clock Path Skew: 1.118ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.801ns = ( 2.301 - 1.500 ) + Source Clock Delay (SCD): 0.259ns + Clock Pessimism Removal (CPR): 0.576ns + Clock Uncertainty: 0.220ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.154ns + Timing Exception: MultiCycle Path Setup -end 6 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.584 -0.671 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.127 -0.544 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.803 0.259 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.702 -1.443 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, unplaced) 0.803 -0.640 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFG (Prop_bufg_I_O) 0.096 -0.544 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=6179, unplaced) 0.803 0.259 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/last_master_r_reg[2] + FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.478 0.737 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/Q + net (fo=40, unplaced) 0.803 1.539 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[13].u_iobuf_dq/IBUFDISABLE + T3 IBUF_INTERMDISABLE (Prop_ibuf_intermdisable_IBUFDISABLE_O) + 2.771 4.310 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[13].u_iobuf_dq/IBUF/O + net (fo=2, estimated) 0.000 4.310 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/mem_dq_in[1] + IDELAY_X1Y77 IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT) + 0.815 5.125 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[2].iserdes_dq_.idelay_dq.idelaye2/DATAOUT + net (fo=1, estimated) 0.000 5.125 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/data_in_dly_2 + ILOGIC_X1Y77 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq/DDLY + ------------------------------------------------------------------- ------------------- + + (clock u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk fall edge) + 16.500 16.500 f + E3 0.000 16.500 f CLK100MHZ (IN) + net (fo=0) 0.000 16.500 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 17.911 f input_clock/O + net (fo=1, unplaced) 0.439 18.350 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 12.970 f clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 13.732 sys_raw + BUFG (Prop_bufg_I_O) 0.091 13.823 f sys_buffer/O + net (fo=1, unplaced) 0.763 14.586 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.083 14.669 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, estimated) 0.577 15.246 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.624 16.870 f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + net (fo=16, estimated) 0.431 17.301 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/CLKB0 + ILOGIC_X1Y77 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq/CLKB (IS_INVERTED) + clock pessimism 0.576 17.877 + clock uncertainty -0.220 17.657 + ILOGIC_X1Y77 ISERDESE2 (Setup_iserdese2_CLKB_DDLY) + -0.165 17.492 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq + ------------------------------------------------------------------- + required time 17.492 + arrival time -5.125 + ------------------------------------------------------------------- + slack 12.367 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 44.683ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[7].iserdes_dq_.iserdesdq/DDLY + (rising edge-triggered cell ISERDESE2 clocked by u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: -45.000ns (u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk rise@15.000ns - clk_pll_i rise@60.000ns) + Data Path Delay: 1.466ns (logic 1.128ns (76.922%) route 0.338ns (23.078%)) + Logic Levels: 2 (IBUF_INTERMDISABLE=1 IDELAYE2=1) + Clock Path Skew: 1.508ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.933ns + Source Clock Delay (SCD): -0.316ns + Clock Pessimism Removal (CPR): -0.259ns + Clock Uncertainty: 0.220ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.154ns + Timing Exception: MultiCycle Path Setup -end 6 Hold -start 5 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 60.000 60.000 r + E3 0.000 60.000 r CLK100MHZ (IN) + net (fo=0) 0.000 60.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 60.250 r input_clock/O + net (fo=1, unplaced) 0.114 60.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 58.586 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 58.925 sys_raw + BUFG (Prop_bufg_I_O) 0.026 58.951 r sys_buffer/O + net (fo=1, unplaced) 0.338 59.289 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 59.339 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.114 59.453 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.020 59.473 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.338 59.811 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -0.703 59.109 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, unplaced) 0.338 59.447 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFG (Prop_bufg_I_O) 0.026 59.473 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=6179, unplaced) 0.211 59.684 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/last_master_r_reg[2] + FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.147 59.831 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/Q + net (fo=40, unplaced) 0.338 60.170 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[10].u_iobuf_dq/IBUFDISABLE + U4 IBUF_INTERMDISABLE (Prop_ibuf_intermdisable_IBUFDISABLE_O) + 0.738 60.908 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[10].u_iobuf_dq/IBUF/O + net (fo=2, estimated) 0.000 60.908 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/mem_dq_in[6] + IDELAY_X1Y84 IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT) + 0.243 61.151 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[7].iserdes_dq_.idelay_dq.idelaye2/DATAOUT + net (fo=1, estimated) 0.000 61.151 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/data_in_dly_7 + ILOGIC_X1Y84 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[7].iserdes_dq_.iserdesdq/DDLY + ------------------------------------------------------------------- ------------------- + + (clock u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk rise edge) + 15.000 15.000 r + E3 0.000 15.000 r CLK100MHZ (IN) + net (fo=0) 0.000 15.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 15.438 r input_clock/O + net (fo=1, unplaced) 0.259 15.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 13.285 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 13.642 sys_raw + BUFG (Prop_bufg_I_O) 0.029 13.671 r sys_buffer/O + net (fo=1, unplaced) 0.356 14.027 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.053 14.080 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, estimated) 0.269 14.349 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.381 15.730 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + net (fo=16, estimated) 0.203 15.933 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq_0 + ILOGIC_X1Y84 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[7].iserdes_dq_.iserdesdq/CLK + clock pessimism 0.259 16.192 + clock uncertainty 0.220 16.412 + ILOGIC_X1Y84 ISERDESE2 (Hold_iserdese2_CLK_DDLY) + 0.056 16.468 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[7].iserdes_dq_.iserdesdq + ------------------------------------------------------------------- + required time -16.468 + arrival time 61.151 + ------------------------------------------------------------------- + slack 44.683 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_pll_i + To Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk + +Setup : 0 Failing Endpoints, Worst Slack 12.374ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 44.679ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 12.374ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq/DDLY + (falling edge-triggered cell ISERDESE2 clocked by u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 16.500ns (u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk fall@16.500ns - clk_pll_i rise@0.000ns) + Data Path Delay: 4.867ns (logic 4.064ns (83.504%) route 0.803ns (16.496%)) + Logic Levels: 2 (IBUF_INTERMDISABLE=1 IDELAYE2=1) + Clock Path Skew: 1.126ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.809ns = ( 2.309 - 1.500 ) + Source Clock Delay (SCD): 0.259ns + Clock Pessimism Removal (CPR): 0.576ns + Clock Uncertainty: 0.220ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.154ns + Timing Exception: MultiCycle Path Setup -end 6 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.584 -0.671 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.127 -0.544 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.803 0.259 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.702 -1.443 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, unplaced) 0.803 -0.640 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFG (Prop_bufg_I_O) 0.096 -0.544 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=6179, unplaced) 0.803 0.259 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/last_master_r_reg[2] + FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.478 0.737 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/Q + net (fo=40, unplaced) 0.803 1.539 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[6].u_iobuf_dq/IBUFDISABLE + L4 IBUF_INTERMDISABLE (Prop_ibuf_intermdisable_IBUFDISABLE_O) + 2.771 4.310 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[6].u_iobuf_dq/IBUF/O + net (fo=2, estimated) 0.000 4.310 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/mem_dq_in[1] + IDELAY_X1Y89 IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT) + 0.815 5.125 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[2].iserdes_dq_.idelay_dq.idelaye2/DATAOUT + net (fo=1, estimated) 0.000 5.125 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/data_in_dly_2 + ILOGIC_X1Y89 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq/DDLY + ------------------------------------------------------------------- ------------------- + + (clock u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk fall edge) + 16.500 16.500 f + E3 0.000 16.500 f CLK100MHZ (IN) + net (fo=0) 0.000 16.500 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 17.911 f input_clock/O + net (fo=1, unplaced) 0.439 18.350 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 12.970 f clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 13.732 sys_raw + BUFG (Prop_bufg_I_O) 0.091 13.823 f sys_buffer/O + net (fo=1, unplaced) 0.763 14.586 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.083 14.669 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, estimated) 0.567 15.236 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.624 16.860 f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + net (fo=16, estimated) 0.448 17.309 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/CLKB0_4 + ILOGIC_X1Y89 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq/CLKB (IS_INVERTED) + clock pessimism 0.576 17.884 + clock uncertainty -0.220 17.665 + ILOGIC_X1Y89 ISERDESE2 (Setup_iserdese2_CLKB_DDLY) + -0.165 17.500 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq + ------------------------------------------------------------------- + required time 17.500 + arrival time -5.125 + ------------------------------------------------------------------- + slack 12.374 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 44.679ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[7].iserdes_dq_.iserdesdq/DDLY + (rising edge-triggered cell ISERDESE2 clocked by u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: -45.000ns (u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk rise@15.000ns - clk_pll_i rise@60.000ns) + Data Path Delay: 1.466ns (logic 1.128ns (76.922%) route 0.338ns (23.078%)) + Logic Levels: 2 (IBUF_INTERMDISABLE=1 IDELAYE2=1) + Clock Path Skew: 1.512ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.937ns + Source Clock Delay (SCD): -0.316ns + Clock Pessimism Removal (CPR): -0.259ns + Clock Uncertainty: 0.220ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.154ns + Timing Exception: MultiCycle Path Setup -end 6 Hold -start 5 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 60.000 60.000 r + E3 0.000 60.000 r CLK100MHZ (IN) + net (fo=0) 0.000 60.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 60.250 r input_clock/O + net (fo=1, unplaced) 0.114 60.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 58.586 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 58.925 sys_raw + BUFG (Prop_bufg_I_O) 0.026 58.951 r sys_buffer/O + net (fo=1, unplaced) 0.338 59.289 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 59.339 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.114 59.453 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.020 59.473 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.338 59.811 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -0.703 59.109 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, unplaced) 0.338 59.447 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFG (Prop_bufg_I_O) 0.026 59.473 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=6179, unplaced) 0.211 59.684 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/last_master_r_reg[2] + FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.147 59.831 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/Q + net (fo=40, unplaced) 0.338 60.170 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[2].u_iobuf_dq/IBUFDISABLE + K3 IBUF_INTERMDISABLE (Prop_ibuf_intermdisable_IBUFDISABLE_O) + 0.738 60.908 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[2].u_iobuf_dq/IBUF/O + net (fo=2, estimated) 0.000 60.908 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/mem_dq_in[6] + IDELAY_X1Y96 IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT) + 0.243 61.151 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[7].iserdes_dq_.idelay_dq.idelaye2/DATAOUT + net (fo=1, estimated) 0.000 61.151 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/data_in_dly_7 + ILOGIC_X1Y96 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[7].iserdes_dq_.iserdesdq/DDLY + ------------------------------------------------------------------- ------------------- + + (clock u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk rise edge) + 15.000 15.000 r + E3 0.000 15.000 r CLK100MHZ (IN) + net (fo=0) 0.000 15.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 15.438 r input_clock/O + net (fo=1, unplaced) 0.259 15.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 13.285 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 13.642 sys_raw + BUFG (Prop_bufg_I_O) 0.029 13.671 r sys_buffer/O + net (fo=1, unplaced) 0.356 14.027 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.053 14.080 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, estimated) 0.265 14.345 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.381 15.725 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + net (fo=16, estimated) 0.211 15.937 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq_0 + ILOGIC_X1Y96 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[7].iserdes_dq_.iserdesdq/CLK + clock pessimism 0.259 16.196 + clock uncertainty 0.220 16.416 + ILOGIC_X1Y96 ISERDESE2 (Hold_iserdese2_CLK_DDLY) + 0.056 16.472 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[7].iserdes_dq_.iserdesdq + ------------------------------------------------------------------- + required time -16.472 + arrival time 61.151 + ------------------------------------------------------------------- + slack 44.679 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: sync_pulse + To Clock: mem_refclk + +Setup : 0 Failing Endpoints, Worst Slack 1.277ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.910ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.277ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 + (clock source 'sync_pulse' {rise@1.312ns fall@4.312ns period=48.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/SYNCIN + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: mem_refclk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 1.687ns (mem_refclk rise@6.000ns - sync_pulse fall@4.312ns) + Data Path Delay: 0.621ns (logic 0.000ns (0.000%) route 0.621ns (100.000%)) + Logic Levels: 0 + Clock Path Skew: 0.590ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.241ns = ( 4.759 - 6.000 ) + Source Clock Delay (SCD): -1.255ns = ( 3.057 - 4.312 ) + Clock Pessimism Removal (CPR): 0.576ns + Clock Uncertainty: 0.198ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.139ns + Phase Error (PE): 0.120ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sync_pulse fall edge) + 4.312 4.312 f + E3 0.000 4.312 f CLK100MHZ (IN) + net (fo=0) 0.000 4.312 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 5.794 f input_clock/O + net (fo=1, unplaced) 0.584 6.378 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 1.267 f clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 2.070 sys_raw + BUFG (Prop_bufg_I_O) 0.096 2.166 f sys_buffer/O + net (fo=1, unplaced) 0.803 2.969 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + 0.088 3.057 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 + net (fo=7, estimated) 0.621 3.678 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/sync_pulse + PHY_CONTROL_X1Y1 PHY_CONTROL f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/SYNCIN + ------------------------------------------------------------------- ------------------- + + (clock mem_refclk rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, unplaced) 0.439 7.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 2.470 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 3.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 3.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 4.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 4.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.590 4.759 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + clock pessimism 0.576 5.335 + clock uncertainty -0.198 5.137 + PHY_CONTROL_X1Y1 PHY_CONTROL (Setup_phy_control_MEMREFCLK_SYNCIN) + -0.182 4.955 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i + ------------------------------------------------------------------- + required time 4.955 + arrival time -3.678 + ------------------------------------------------------------------- + slack 1.277 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.910ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 + (clock source 'sync_pulse' {rise@1.312ns fall@4.312ns period=48.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/SYNCIN + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: mem_refclk + Path Type: Hold (Min at Slow Process Corner) + Requirement: -1.312ns (mem_refclk rise@0.000ns - sync_pulse rise@1.312ns) + Data Path Delay: 0.590ns (logic 0.000ns (0.000%) route 0.590ns (100.000%)) + Logic Levels: 0 + Clock Path Skew: 0.621ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.634ns + Source Clock Delay (SCD): -1.831ns = ( -0.519 - 1.312 ) + Clock Pessimism Removal (CPR): 0.576ns + Clock Uncertainty: 0.198ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.139ns + Phase Error (PE): 0.120ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sync_pulse rise edge) + 1.312 1.312 r + E3 0.000 1.312 r CLK100MHZ (IN) + net (fo=0) 0.000 1.312 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 2.724 r input_clock/O + net (fo=1, unplaced) 0.439 3.163 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 -2.218 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 -1.455 sys_raw + BUFG (Prop_bufg_I_O) 0.091 -1.364 r sys_buffer/O + net (fo=1, unplaced) 0.763 -0.602 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + 0.083 -0.519 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 + net (fo=7, estimated) 0.590 0.071 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/sync_pulse + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/SYNCIN + ------------------------------------------------------------------- ------------------- + + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.621 -0.634 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + clock pessimism -0.576 -1.210 + clock uncertainty 0.198 -1.012 + PHY_CONTROL_X1Y1 PHY_CONTROL (Hold_phy_control_MEMREFCLK_SYNCIN) + 0.174 -0.838 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i + ------------------------------------------------------------------- + required time 0.838 + arrival time 0.071 + ------------------------------------------------------------------- + slack 0.910 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk + To Clock: oserdes_clkdiv + +Setup : 0 Failing Endpoints, Worst Slack 2.105ns, Total Violation 0.000ns +Hold : 11 Failing Endpoints, Worst Slack -0.247ns, Total Violation -1.473ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 2.105ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clkdiv rise@12.000ns - oserdes_clk rise@9.000ns) + Data Path Delay: 0.338ns (logic 0.338ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.148ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.271ns = ( 13.271 - 12.000 ) + Source Clock Delay (SCD): 1.793ns = ( 10.793 - 9.000 ) + Clock Pessimism Removal (CPR): 0.670ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.081ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk rise edge) + 9.000 9.000 r + E3 0.000 9.000 r CLK100MHZ (IN) + net (fo=0) 0.000 9.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 10.482 r input_clock/O + net (fo=1, unplaced) 0.584 11.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 5.955 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 6.758 sys_raw + BUFG (Prop_bufg_I_O) 0.096 6.854 r sys_buffer/O + net (fo=1, unplaced) 0.803 7.657 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 7.745 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.614 8.359 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 10.793 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.338 11.131 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/RDENABLE + net (fo=1, estimated) 0.000 11.131 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/po_rd_enable + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, unplaced) 0.439 13.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 8.470 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 9.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 9.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 10.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 10.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.583 10.752 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 13.123 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 13.271 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, estimated) 0.000 13.271 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/oserdes_clkdiv + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + clock pessimism 0.670 13.941 + clock uncertainty -0.054 13.887 + OUT_FIFO_X1Y4 OUT_FIFO (Setup_out_fifo_RDCLK_RDEN) + -0.651 13.236 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo + ------------------------------------------------------------------- + required time 13.236 + arrival time -11.131 + ------------------------------------------------------------------- + slack 2.105 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (VIOLATED) : -0.247ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[6].oserdes_dq_.sdr.oserdes_dq_i/RST + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv rise@0.000ns - oserdes_clk rise@0.000ns) + Data Path Delay: 0.602ns (logic 0.272ns (45.211%) route 0.330ns (54.789%)) + Logic Levels: 0 + Clock Path Skew: 0.289ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.782ns + Source Clock Delay (SCD): 1.690ns + Clock Pessimism Removal (CPR): -0.197ns + Timing Exception: MultiCycle Path Setup -start 2 Hold -start 1 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.259 -0.402 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.690 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OSERDESRST) + 0.272 1.962 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OSERDESRST + net (fo=11, estimated) 0.330 2.292 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/po_oserdes_rst + OLOGIC_X1Y59 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[6].oserdes_dq_.sdr.oserdes_dq_i/RST + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.272 -0.648 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.493 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.581 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, estimated) 0.201 1.782 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y59 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[6].oserdes_dq_.sdr.oserdes_dq_i/CLKDIV + clock pessimism 0.197 1.979 + OLOGIC_X1Y59 OSERDESE2 (Hold_oserdese2_CLKDIV_RST) + 0.559 2.538 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[6].oserdes_dq_.sdr.oserdes_dq_i + ------------------------------------------------------------------- + required time -2.538 + arrival time 2.292 + ------------------------------------------------------------------- + slack -0.247 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_1 + To Clock: oserdes_clkdiv_1 + +Setup : 0 Failing Endpoints, Worst Slack 2.105ns, Total Violation 0.000ns +Hold : 12 Failing Endpoints, Worst Slack -0.268ns, Total Violation -2.486ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 2.105ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_1 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv_1 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clkdiv_1 rise@12.000ns - oserdes_clk_1 rise@9.000ns) + Data Path Delay: 0.338ns (logic 0.338ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.148ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.260ns = ( 13.260 - 12.000 ) + Source Clock Delay (SCD): 1.782ns = ( 10.782 - 9.000 ) + Clock Pessimism Removal (CPR): 0.669ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.081ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_1 rise edge) + 9.000 9.000 r + E3 0.000 9.000 r CLK100MHZ (IN) + net (fo=0) 0.000 9.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 10.482 r input_clock/O + net (fo=1, unplaced) 0.584 11.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 5.955 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 6.758 sys_raw + BUFG (Prop_bufg_I_O) 0.096 6.854 r sys_buffer/O + net (fo=1, unplaced) 0.803 7.657 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 7.745 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.603 8.348 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 10.782 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.338 11.120 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/RDENABLE + net (fo=1, estimated) 0.000 11.120 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/po_rd_enable + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_1 rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, unplaced) 0.439 13.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 8.470 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 9.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 9.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 10.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 10.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.573 10.742 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 13.112 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 13.260 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, estimated) 0.000 13.260 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/oserdes_clkdiv + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + clock pessimism 0.669 13.930 + clock uncertainty -0.054 13.876 + OUT_FIFO_X1Y5 OUT_FIFO (Setup_out_fifo_RDCLK_RDEN) + -0.651 13.225 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo + ------------------------------------------------------------------- + required time 13.225 + arrival time -11.120 + ------------------------------------------------------------------- + slack 2.105 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (VIOLATED) : -0.268ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_1 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[8].oserdes_dq_.sdr.oserdes_dq_i/RST + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv_1 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_1 rise@0.000ns - oserdes_clk_1 rise@0.000ns) + Data Path Delay: 0.576ns (logic 0.272ns (47.195%) route 0.304ns (52.805%)) + Logic Levels: 0 + Clock Path Skew: 0.285ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.773ns + Source Clock Delay (SCD): 1.685ns + Clock Pessimism Removal (CPR): -0.197ns + Timing Exception: MultiCycle Path Setup -start 2 Hold -start 1 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.254 -0.407 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.685 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OSERDESRST) + 0.272 1.957 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OSERDESRST + net (fo=12, estimated) 0.304 2.262 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/po_oserdes_rst + OLOGIC_X1Y73 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[8].oserdes_dq_.sdr.oserdes_dq_i/RST + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.268 -0.653 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.488 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.576 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, estimated) 0.197 1.773 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y73 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[8].oserdes_dq_.sdr.oserdes_dq_i/CLKDIV + clock pessimism 0.197 1.970 + OLOGIC_X1Y73 OSERDESE2 (Hold_oserdese2_CLKDIV_RST) + 0.559 2.529 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[8].oserdes_dq_.sdr.oserdes_dq_i + ------------------------------------------------------------------- + required time -2.529 + arrival time 2.262 + ------------------------------------------------------------------- + slack -0.268 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_2 + To Clock: oserdes_clkdiv_2 + +Setup : 0 Failing Endpoints, Worst Slack 2.105ns, Total Violation 0.000ns +Hold : 10 Failing Endpoints, Worst Slack -0.274ns, Total Violation -2.156ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 2.105ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_2 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clkdiv_2 rise@6.000ns - oserdes_clk_2 rise@3.000ns) + Data Path Delay: 0.338ns (logic 0.338ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.148ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.271ns = ( 7.271 - 6.000 ) + Source Clock Delay (SCD): 1.793ns = ( 4.793 - 3.000 ) + Clock Pessimism Removal (CPR): 0.670ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.081ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_2 rise edge) + 3.000 3.000 r + E3 0.000 3.000 r CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 4.482 r input_clock/O + net (fo=1, unplaced) 0.584 5.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -0.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 0.758 sys_raw + BUFG (Prop_bufg_I_O) 0.096 0.854 r sys_buffer/O + net (fo=1, unplaced) 0.803 1.657 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 1.745 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.614 2.359 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 4.793 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.338 5.131 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/RDENABLE + net (fo=1, estimated) 0.000 5.131 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/po_rd_enable + OUT_FIFO_X1Y6 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_2 rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, unplaced) 0.439 7.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 2.470 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 3.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 3.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 4.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 4.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.583 4.752 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 7.123 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 7.271 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, estimated) 0.000 7.271 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/oserdes_clkdiv + OUT_FIFO_X1Y6 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + clock pessimism 0.670 7.941 + clock uncertainty -0.054 7.887 + OUT_FIFO_X1Y6 OUT_FIFO (Setup_out_fifo_RDCLK_RDEN) + -0.651 7.236 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo + ------------------------------------------------------------------- + required time 7.236 + arrival time -5.131 + ------------------------------------------------------------------- + slack 2.105 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (VIOLATED) : -0.274ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/RST + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_2 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_2 rise@0.000ns - oserdes_clk_2 rise@0.000ns) + Data Path Delay: 0.574ns (logic 0.272ns (47.403%) route 0.302ns (52.597%)) + Logic Levels: 0 + Clock Path Skew: 0.289ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.781ns + Source Clock Delay (SCD): 1.690ns + Clock Pessimism Removal (CPR): -0.197ns + Timing Exception: MultiCycle Path Setup -start 2 Hold -start 1 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.259 -0.402 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.690 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OSERDESRST) + 0.272 1.962 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OSERDESRST + net (fo=10, estimated) 0.302 2.264 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/po_oserdes_rst + OLOGIC_X1Y77 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/RST + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.272 -0.648 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.493 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.581 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, estimated) 0.201 1.781 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y77 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV + clock pessimism 0.197 1.979 + OLOGIC_X1Y77 OSERDESE2 (Hold_oserdese2_CLKDIV_RST) + 0.559 2.538 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i + ------------------------------------------------------------------- + required time -2.538 + arrival time 2.264 + ------------------------------------------------------------------- + slack -0.274 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_3 + To Clock: oserdes_clkdiv_3 + +Setup : 0 Failing Endpoints, Worst Slack 2.105ns, Total Violation 0.000ns +Hold : 10 Failing Endpoints, Worst Slack -0.197ns, Total Violation -1.058ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 2.105ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_3 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clkdiv_3 rise@6.000ns - oserdes_clk_3 rise@3.000ns) + Data Path Delay: 0.338ns (logic 0.338ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.148ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.260ns = ( 7.260 - 6.000 ) + Source Clock Delay (SCD): 1.782ns = ( 4.782 - 3.000 ) + Clock Pessimism Removal (CPR): 0.669ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.081ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_3 rise edge) + 3.000 3.000 r + E3 0.000 3.000 r CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 4.482 r input_clock/O + net (fo=1, unplaced) 0.584 5.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -0.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 0.758 sys_raw + BUFG (Prop_bufg_I_O) 0.096 0.854 r sys_buffer/O + net (fo=1, unplaced) 0.803 1.657 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 1.745 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.603 2.348 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 4.782 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.338 5.120 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/RDENABLE + net (fo=1, estimated) 0.000 5.120 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/po_rd_enable + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_3 rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, unplaced) 0.439 7.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 2.470 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 3.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 3.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 4.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 4.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.573 4.742 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 7.112 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 7.260 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, estimated) 0.000 7.260 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/oserdes_clkdiv + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + clock pessimism 0.669 7.930 + clock uncertainty -0.054 7.876 + OUT_FIFO_X1Y7 OUT_FIFO (Setup_out_fifo_RDCLK_RDEN) + -0.651 7.225 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo + ------------------------------------------------------------------- + required time 7.225 + arrival time -5.120 + ------------------------------------------------------------------- + slack 2.105 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (VIOLATED) : -0.197ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[1].oserdes_dq_.ddr.oserdes_dq_i/RST + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_3 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_3 rise@0.000ns - oserdes_clk_3 rise@0.000ns) + Data Path Delay: 0.658ns (logic 0.272ns (41.330%) route 0.386ns (58.670%)) + Logic Levels: 0 + Clock Path Skew: 0.296ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.784ns + Source Clock Delay (SCD): 1.685ns + Clock Pessimism Removal (CPR): -0.197ns + Timing Exception: MultiCycle Path Setup -start 2 Hold -start 1 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.254 -0.407 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.685 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OSERDESRST) + 0.272 1.957 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OSERDESRST + net (fo=10, estimated) 0.386 2.343 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/po_oserdes_rst + OLOGIC_X1Y88 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[1].oserdes_dq_.ddr.oserdes_dq_i/RST + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.268 -0.653 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.488 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.576 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, estimated) 0.208 1.784 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y88 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[1].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV + clock pessimism 0.197 1.981 + OLOGIC_X1Y88 OSERDESE2 (Hold_oserdese2_CLKDIV_RST) + 0.559 2.540 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[1].oserdes_dq_.ddr.oserdes_dq_i + ------------------------------------------------------------------- + required time -2.540 + arrival time 2.343 + ------------------------------------------------------------------- + slack -0.197 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: core_raw + To Clock: clk_pll_i + +Setup : 0 Failing Endpoints, Worst Slack 38.968ns, Total Violation 0.000ns +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 38.968ns (required time - arrival time) + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: clk_pll_i + Path Type: Setup (Max at Slow Process Corner) + Requirement: 40.000ns (MaxDelay Path 40.000ns) + Data Path Delay: 0.812ns (logic 0.478ns (58.867%) route 0.334ns (41.133%)) + Logic Levels: 0 + Timing Exception: MaxDelay Path 40.000ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + 0.000 0.000 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + FDRE (Prop_fdre_C_Q) 0.478 0.478 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, unplaced) 0.334 0.812 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[0] + FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + ------------------------------------------------------------------- ------------------- + + max delay 40.000 40.000 + FDRE (Setup_fdre_C_D) -0.220 39.780 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + ------------------------------------------------------------------- + required time 39.780 + arrival time -0.812 + ------------------------------------------------------------------- + slack 38.968 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: ref_raw + To Clock: clk_pll_i + +Setup : 0 Failing Endpoints, Worst Slack 19.759ns, Total Violation 0.000ns +Hold : 12 Failing Endpoints, Worst Slack -1.631ns, Total Violation -19.568ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 19.759ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[0]/C + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[0]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: clk_pll_i + Path Type: Setup (Max at Fast Process Corner) + Requirement: 20.000ns (MaxDelay Path 20.000ns) + Data Path Delay: 0.331ns (logic 0.183ns (55.254%) route 0.148ns (44.746%)) + Logic Levels: 0 + Clock Path Skew: 0.454ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.316ns + Source Clock Delay (SCD): -1.070ns + Clock Pessimism Removal (CPR): -0.301ns + Clock Uncertainty: 0.245ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.178ns + Timing Exception: MaxDelay Path 20.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -2.411 -1.715 r clock_mmcm/CLKOUT2 + net (fo=1, unplaced) 0.356 -1.358 ref_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r ref_buffer/O + net (fo=67, unplaced) 0.259 -1.070 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/clk_ref_i + FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[0]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.183 -0.887 r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[0]/Q + net (fo=1, unplaced) 0.148 -0.739 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_lcl[0] + FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[0]/D + ------------------------------------------------------------------- ------------------- + + max delay 20.000 20.000 + E3 0.000 20.000 r CLK100MHZ (IN) + net (fo=0) 0.000 20.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 20.250 r input_clock/O + net (fo=1, unplaced) 0.114 20.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 18.586 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 18.925 sys_raw + BUFG (Prop_bufg_I_O) 0.026 18.951 r sys_buffer/O + net (fo=1, unplaced) 0.338 19.289 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 19.339 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.114 19.453 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.020 19.473 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.338 19.811 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -0.703 19.109 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, unplaced) 0.338 19.447 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFG (Prop_bufg_I_O) 0.026 19.473 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=6179, unplaced) 0.211 19.684 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r5_reg[11]_0 + FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[0]/C + clock pessimism -0.301 19.383 + clock uncertainty -0.245 19.138 + FDRE (Setup_fdre_C_D) -0.119 19.019 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[0] + ------------------------------------------------------------------- + required time 19.019 + arrival time 0.739 + ------------------------------------------------------------------- + slack 19.759 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (VIOLATED) : -1.631ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[0]/C + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[0]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: clk_pll_i + Path Type: Hold (Min at Slow Process Corner) + Requirement: 0.000ns (clk_pll_i rise@0.000ns - ref_raw rise@0.000ns) + Data Path Delay: 0.702ns (logic 0.385ns (54.820%) route 0.317ns (45.180%)) + Logic Levels: 0 + Clock Path Skew: 2.011ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.259ns + Source Clock Delay (SCD): -2.238ns + Clock Pessimism Removal (CPR): 0.485ns + Clock Uncertainty: 0.245ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.178ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, unplaced) 0.439 1.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -5.381 -3.530 r clock_mmcm/CLKOUT2 + net (fo=1, unplaced) 0.763 -2.768 ref_raw + BUFG (Prop_bufg_I_O) 0.091 -2.677 r ref_buffer/O + net (fo=67, unplaced) 0.439 -2.238 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/clk_ref_i + FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[0]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.385 -1.853 r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[0]/Q + net (fo=1, unplaced) 0.317 -1.535 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_lcl[0] + FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.584 -0.671 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.127 -0.544 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.803 0.259 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.702 -1.443 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, unplaced) 0.803 -0.640 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFG (Prop_bufg_I_O) 0.096 -0.544 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=6179, unplaced) 0.803 0.259 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r5_reg[11]_0 + FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[0]/C + clock pessimism -0.485 -0.227 + clock uncertainty 0.245 0.018 + FDRE (Hold_fdre_C_D) 0.077 0.095 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[0] + ------------------------------------------------------------------- + required time -0.095 + arrival time -1.535 + ------------------------------------------------------------------- + slack -1.631 + + + + + +--------------------------------------------------------------------------------------------------- +Path Group: **async_default** +From Clock: clk_pll_i + To Clock: clk_pll_i + +Setup : 0 Failing Endpoints, Worst Slack 9.663ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.295ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 9.663ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__8/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n_reg/CLR + (recovery check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 12.000ns (clk_pll_i rise@12.000ns - clk_pll_i rise@0.000ns) + Data Path Delay: 1.773ns (logic 0.773ns (43.598%) route 1.000ns (56.402%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.653ns = ( 11.347 - 12.000 ) + Source Clock Delay (SCD): 0.259ns + Clock Pessimism Removal (CPR): 0.767ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.584 -0.671 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.127 -0.544 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.803 0.259 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.702 -1.443 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, unplaced) 0.803 -0.640 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFG (Prop_bufg_I_O) 0.096 -0.544 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=6179, unplaced) 0.803 0.259 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__8/C + ------------------------------------------------------------------- ------------------- + FDPE (Prop_fdpe_C_Q) 0.478 0.737 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__8/Q + net (fo=1, unplaced) 0.311 1.048 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__8_n_0 + LUT1 (Prop_lut1_I0_O) 0.295 1.343 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_inst_rep__7/O + net (fo=47, unplaced) 0.689 2.032 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/calib_ctl_wren_reg_7 + FDCE f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, unplaced) 0.439 13.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 8.470 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 9.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 9.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 10.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 10.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.439 10.608 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.081 10.689 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.763 11.452 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.616 9.835 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, unplaced) 0.763 10.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFG (Prop_bufg_I_O) 0.091 10.689 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=6179, unplaced) 0.658 11.347 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg[14]_0 + FDCE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n_reg/C + clock pessimism 0.767 12.114 + clock uncertainty -0.067 12.046 + FDCE (Recov_fdce_C_CLR) -0.352 11.694 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n_reg + ------------------------------------------------------------------- + required time 11.694 + arrival time -2.032 + ------------------------------------------------------------------- + slack 9.663 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.295ns (arrival time - required time) + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]/CLR + (removal check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (clk_pll_i rise@0.000ns - clk_pll_i rise@0.000ns) + Data Path Delay: 0.299ns (logic 0.147ns (49.136%) route 0.152ns (50.864%)) + Logic Levels: 0 + Clock Path Skew: 0.145ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.316ns + Clock Pessimism Removal (CPR): -0.091ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.114 -0.547 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.020 -0.527 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.338 -0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -0.703 -0.891 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, unplaced) 0.338 -0.553 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFG (Prop_bufg_I_O) 0.026 -0.527 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=6179, unplaced) 0.211 -0.316 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/dest_clk + FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + FDPE (Prop_fdpe_C_Q) 0.147 -0.169 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/Q + net (fo=3, unplaced) 0.152 -0.017 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.rst_rd_reg2 + FDCE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.259 -0.661 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.043 -0.618 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.356 -0.262 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -0.741 -1.003 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, unplaced) 0.356 -0.647 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFG (Prop_bufg_I_O) 0.029 -0.618 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=6179, unplaced) 0.356 -0.262 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/m_aclk + FDCE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]/C + clock pessimism 0.091 -0.171 + FDCE (Remov_fdce_C_CLR) -0.141 -0.312 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0] + ------------------------------------------------------------------- + required time 0.312 + arrival time -0.017 + ------------------------------------------------------------------- + slack 0.295 + + + + + +--------------------------------------------------------------------------------------------------- +Path Group: **async_default** +From Clock: core_raw + To Clock: core_raw + +Setup : 0 Failing Endpoints, Worst Slack 34.624ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.295ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 34.624ns (required time - arrival time) + Source: reset_count_reg[10]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: platform/chip/system/clint_domain/intsource/reg_0/reg_0_reg[0]/CLR + (recovery check against rising-edge clock core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 40.000ns (core_raw rise@40.000ns - core_raw rise@0.000ns) + Data Path Delay: 4.788ns (logic 1.269ns (26.504%) route 3.519ns (73.496%)) + Logic Levels: 5 (LUT2=1 LUT4=2 LUT5=1 LUT6=1) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.238ns = ( 37.762 - 40.000 ) + Source Clock Delay (SCD): -1.562ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.091ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.111 -3.045 r clock_mmcm/CLKOUT0 + net (fo=1, unplaced) 0.803 -2.242 core_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r core_buffer/O + net (fo=35560, unplaced) 0.584 -1.562 clk + FDRE r reset_count_reg[10]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.478 -1.084 r reset_count_reg[10]/Q + net (fo=2, unplaced) 0.774 -0.310 platform/normalizer/reset_count_reg[10] + LUT4 (Prop_lut4_I1_O) 0.295 -0.015 f platform/normalizer/reset_count[0]_i_7/O + net (fo=1, unplaced) 0.449 0.434 platform/normalizer/reset_count[0]_i_7_n_0 + LUT5 (Prop_lut5_I4_O) 0.124 0.558 f platform/normalizer/reset_count[0]_i_5/O + net (fo=1, unplaced) 0.449 1.007 platform/normalizer/reset_count[0]_i_5_n_0 + LUT6 (Prop_lut6_I5_O) 0.124 1.131 f platform/normalizer/reset_count[0]_i_2/O + net (fo=21, unplaced) 0.510 1.641 platform/normalizer/sel + LUT4 (Prop_lut4_I3_O) 0.124 1.765 f platform/normalizer/FSM_sequential_state[2]_i_1/O + net (fo=900, unplaced) 0.589 2.354 platform/loader/cpu_run_reg_inv_20 + LUT2 (Prop_lut2_I0_O) 0.124 2.478 f platform/loader/in_pipe_v_i_1__0/O + net (fo=3765, unplaced) 0.748 3.226 platform/chip/system/clint_domain/intsource/reg_0/cpu_reset + FDCE f platform/chip/system/clint_domain/intsource/reg_0/reg_0_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 40.000 40.000 r + E3 0.000 40.000 r CLK100MHZ (IN) + net (fo=0) 0.000 40.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r input_clock/O + net (fo=1, unplaced) 0.439 41.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.381 36.470 r clock_mmcm/CLKOUT0 + net (fo=1, unplaced) 0.763 37.232 core_raw + BUFG (Prop_bufg_I_O) 0.091 37.323 r core_buffer/O + net (fo=35560, unplaced) 0.439 37.762 platform/chip/system/clint_domain/intsource/reg_0/clk + FDCE r platform/chip/system/clint_domain/intsource/reg_0/reg_0_reg[0]/C + clock pessimism 0.531 38.293 + clock uncertainty -0.091 38.202 + FDCE (Recov_fdce_C_CLR) -0.352 37.850 platform/chip/system/clint_domain/intsource/reg_0/reg_0_reg[0] + ------------------------------------------------------------------- + required time 37.850 + arrival time -3.226 + ------------------------------------------------------------------- + slack 34.624 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.295ns (arrival time - required time) + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/C + (rising edge-triggered cell FDPE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]/CLR + (removal check against rising-edge clock core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (core_raw rise@0.000ns - core_raw rise@0.000ns) + Data Path Delay: 0.299ns (logic 0.147ns (49.136%) route 0.152ns (50.864%)) + Logic Levels: 0 + Clock Path Skew: 0.145ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -1.070ns + Source Clock Delay (SCD): -0.935ns + Clock Pessimism Removal (CPR): -0.280ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.777 -1.414 r clock_mmcm/CLKOUT0 + net (fo=1, unplaced) 0.338 -1.075 core_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r core_buffer/O + net (fo=35560, unplaced) 0.114 -0.935 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/dest_clk + FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + FDPE (Prop_fdpe_C_Q) 0.147 -0.788 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/Q + net (fo=3, unplaced) 0.152 -0.636 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.rst_rd_reg2 + FDCE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.411 -1.715 r clock_mmcm/CLKOUT0 + net (fo=1, unplaced) 0.356 -1.358 core_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r core_buffer/O + net (fo=35560, unplaced) 0.259 -1.070 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/s_aclk + FDCE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]/C + clock pessimism 0.280 -0.790 + FDCE (Remov_fdce_C_CLR) -0.141 -0.931 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0] + ------------------------------------------------------------------- + required time 0.931 + arrival time -0.636 + ------------------------------------------------------------------- + slack 0.295 + + + + + +--------------------------------------------------------------------------------------------------- +Path Group: **default** +From Clock: clk_pll_i + To Clock: + +Setup : 0 Failing Endpoints, Worst Slack 3.113ns, Total Violation 0.000ns +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 3.113ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/RESET + Path Group: **default** + Path Type: Max at Slow Process Corner + Requirement: 5.000ns (MaxDelay Path 5.000ns) + Data Path Delay: 1.887ns (logic 0.773ns (40.968%) route 1.114ns (59.032%)) + Logic Levels: 1 (LUT1=1) + Output Delay: 0.000ns + Timing Exception: MaxDelay Path 5.000ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + 0.000 0.000 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + FDPE (Prop_fdpe_C_Q) 0.478 0.478 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/Q + net (fo=1, unplaced) 0.311 0.789 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep_n_0 + LUT1 (Prop_lut1_I0_O) 0.295 1.084 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_inst/O + net (fo=50, unplaced) 0.803 1.887 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i_0 + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/RESET + ------------------------------------------------------------------- ------------------- + + max delay 5.000 5.000 + PHY_CONTROL_X1Y1 PHY_CONTROL 0.000 5.000 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i + output delay -0.000 5.000 + ------------------------------------------------------------------- + required time 5.000 + arrival time -1.887 + ------------------------------------------------------------------- + slack 3.113 + + + + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/synth-utilization.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/synth-utilization.rpt new file mode 100644 index 0000000..2cf4e01 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/synth-utilization.rpt @@ -0,0 +1,233 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Mon Oct 12 20:30:48 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_utilization -file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/synth-utilization.rpt +| Design : toy_a7_top +| Device : xc7a100tcsg324-1 +| Speed File : -1 +| Design State : Synthesized +------------------------------------------------------------------------------------------------------------------------------------------------------------ + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++----------------------------+-------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++----------------------------+-------+-------+------------+-----------+-------+ +| Slice LUTs* | 57555 | 0 | 0 | 63400 | 90.78 | +| LUT as Logic | 53496 | 0 | 0 | 63400 | 84.38 | +| LUT as Memory | 4059 | 0 | 0 | 19000 | 21.36 | +| LUT as Distributed RAM | 3680 | 0 | | | | +| LUT as Shift Register | 379 | 0 | | | | +| Slice Registers | 34174 | 0 | 0 | 126800 | 26.95 | +| Register as Flip Flop | 34174 | 0 | 0 | 126800 | 26.95 | +| Register as Latch | 0 | 0 | 0 | 126800 | 0.00 | +| F7 Muxes | 689 | 0 | 0 | 31700 | 2.17 | +| F8 Muxes | 112 | 0 | 0 | 15850 | 0.71 | ++----------------------------+-------+-------+------------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. +Warning! LUT value is adjusted to account for LUT combining. +Warning! For any ECO changes, please run place_design if there are unplaced instances + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 194 | Yes | - | Set | +| 140 | Yes | - | Reset | +| 580 | Yes | Set | - | +| 33260 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++-------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------------+------+-------+------------+-----------+-------+ +| Block RAM Tile | 31 | 0 | 0 | 135 | 22.96 | +| RAMB36/FIFO* | 27 | 0 | 0 | 135 | 20.00 | +| RAMB36E1 only | 27 | | | | | +| RAMB18 | 8 | 0 | 0 | 270 | 2.96 | +| RAMB18E1 only | 8 | | | | | ++-------------------+------+-------+------------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++----------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++----------------+------+-------+------------+-----------+-------+ +| DSPs | 117 | 0 | 0 | 240 | 48.75 | +| DSP48E1 only | 117 | | | | | ++----------------+------+-------+------------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-----------------------------+------+-------+------------+-----------+-------+ +| Bonded IOB | 61 | 61 | 0 | 210 | 29.05 | +| IOB Master Pads | 29 | | | | | +| IOB Slave Pads | 29 | | | | | +| Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 | +| PHY_CONTROL | 1 | 1 | 0 | 6 | 16.67 | +| PHASER_REF | 1 | 1 | 0 | 6 | 16.67 | +| OUT_FIFO | 4 | 4 | 0 | 24 | 16.67 | +| IN_FIFO | 2 | 2 | 0 | 24 | 8.33 | +| IDELAYCTRL | 1 | 0 | 0 | 6 | 16.67 | +| IBUFDS | 0 | 0 | 0 | 202 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 4 | 4 | 0 | 24 | 16.67 | +| PHASER_OUT_PHY only | 4 | 4 | | | | +| PHASER_IN/PHASER_IN_PHY | 2 | 2 | 0 | 24 | 8.33 | +| PHASER_IN_PHY only | 2 | 2 | | | | +| IDELAYE2/IDELAYE2_FINEDELAY | 16 | 16 | 0 | 300 | 5.33 | +| IDELAYE2 only | 16 | 16 | | | | +| ILOGIC | 16 | 16 | 0 | 210 | 7.62 | +| ISERDES | 16 | 16 | 0 | 210 | | +| OLOGIC | 46 | 46 | 0 | 210 | 21.90 | +| OUTFF_ODDR_Register | 3 | 3 | | | | +| TFF_ODDR_Register | 2 | 2 | | | | +| OSERDES | 43 | 43 | 0 | 210 | | ++-----------------------------+------+-------+------------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++------------+------+-------+------------+-----------+-------+ +| BUFGCTRL | 7 | 0 | 0 | 32 | 21.88 | +| BUFIO | 0 | 0 | 0 | 24 | 0.00 | +| MMCME2_ADV | 2 | 1 | 0 | 6 | 33.33 | +| PLLE2_ADV | 1 | 1 | 0 | 6 | 16.67 | +| BUFMRCE | 0 | 0 | 0 | 12 | 0.00 | +| BUFHCE | 1 | 0 | 0 | 96 | 1.04 | +| BUFR | 0 | 0 | 0 | 24 | 0.00 | ++------------+------+-------+------------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+------------+-----------+--------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------+------+-------+------------+-----------+--------+ +| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 | +| XADC | 1 | 0 | 0 | 1 | 100.00 | ++-------------+------+-------+------------+-----------+--------+ + + +7. Primitives +------------- + ++--------------------------+-------+---------------------+ +| Ref Name | Used | Functional Category | ++--------------------------+-------+---------------------+ +| FDRE | 33260 | Flop & Latch | +| LUT6 | 19737 | LUT | +| LUT5 | 13793 | LUT | +| LUT3 | 13255 | LUT | +| LUT4 | 11100 | LUT | +| RAMD32 | 5124 | Distributed Memory | +| LUT2 | 4864 | LUT | +| CARRY4 | 2074 | CarryLogic | +| RAMS32 | 1782 | Distributed Memory | +| LUT1 | 1266 | LUT | +| MUXF7 | 689 | MuxFx | +| FDSE | 580 | Flop & Latch | +| SRL16E | 245 | Distributed Memory | +| FDPE | 194 | Flop & Latch | +| FDCE | 140 | Flop & Latch | +| SRLC32E | 134 | Distributed Memory | +| DSP48E1 | 117 | Block Arithmetic | +| RAMD64E | 112 | Distributed Memory | +| MUXF8 | 112 | MuxFx | +| OSERDESE2 | 43 | IO | +| RAMS64E | 42 | Distributed Memory | +| OBUF | 33 | IO | +| RAMB36E1 | 27 | Block Memory | +| OBUFT | 18 | IO | +| ISERDESE2 | 16 | IO | +| IDELAYE2 | 16 | IO | +| IBUF_INTERMDISABLE | 16 | IO | +| RAMB18E1 | 8 | Block Memory | +| BUFG | 7 | Clock | +| ODDR | 5 | IO | +| PHASER_OUT_PHY | 4 | IO | +| OUT_FIFO | 4 | IO | +| OBUFTDS | 4 | IO | +| IBUFDS_INTERMDISABLE_INT | 4 | IO | +| IBUF | 4 | IO | +| INV | 3 | LUT | +| PHASER_IN_PHY | 2 | IO | +| OBUFDS | 2 | IO | +| MMCME2_ADV | 2 | Clock | +| IN_FIFO | 2 | IO | +| XADC | 1 | Others | +| PLLE2_ADV | 1 | Clock | +| PHY_CONTROL | 1 | IO | +| PHASER_REF | 1 | IO | +| IDELAYCTRL | 1 | IO | +| BUFH | 1 | Clock | ++--------------------------+-------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++-------------+------+ +| Ref Name | Used | ++-------------+------+ +| toy_axi_cdc | 1 | +| arty_ddr3 | 1 | ++-------------+------+ + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/vivado.jou b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/vivado.jou new file mode 100644 index 0000000..61473e2 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/vivado.jou @@ -0,0 +1,24 @@ +#----------------------------------------------------------- +# Vivado v2024.1 (64-bit) +# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024 +# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024 +# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024 +# Start of session at: Mon Oct 12 20:13:53 2026 +# Process ID: 19966 +# Current directory: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31 +# Command line: vivado -mode batch -source /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/build_board.tcl -log /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/vivado.log -journal /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/vivado.jou -tclargs /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352 +# Log file: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/vivado.log +# Journal file: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/vivado.jou +# Running On :amax +# Platform :Ubuntu +# Operating System :Ubuntu 24.04 LTS +# Processor Detail :INTEL(R) XEON(R) GOLD 6542Y +# CPU Frequency :800.000 MHz +# CPU Physical cores:48 +# CPU Logical cores :96 +# Host memory :540650 MB +# Swap memory :130443 MB +# Total Virtual :671094 MB +# Available Virtual :661079 MB +#----------------------------------------------------------- +source /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/build_board.tcl diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/vivado.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/vivado.log new file mode 100644 index 0000000..bb9ec4d --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/vivado.log @@ -0,0 +1,5919 @@ +#----------------------------------------------------------- +# Vivado v2024.1 (64-bit) +# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024 +# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024 +# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024 +# Start of session at: Mon Oct 12 20:13:53 2026 +# Process ID: 19966 +# Current directory: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31 +# Command line: vivado -mode batch -source /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/build_board.tcl -log /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/vivado.log -journal /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/vivado.jou -tclargs /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352 +# Log file: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/vivado.log +# Journal file: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/vivado.jou +# Running On :amax +# Platform :Ubuntu +# Operating System :Ubuntu 24.04 LTS +# Processor Detail :INTEL(R) XEON(R) GOLD 6542Y +# CPU Frequency :800.000 MHz +# CPU Physical cores:48 +# CPU Logical cores :96 +# Host memory :540650 MB +# Swap memory :130443 MB +# Total Virtual :671094 MB +# Available Virtual :661079 MB +#----------------------------------------------------------- +source /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/build_board.tcl +# set root [file dirname [file dirname [file normalize [info script]]]] +# cd $root +# if {[llength $argv]<1 || [llength $argv]>2} {error "Usage: build_board.tcl OUTPUT_DIRECTORY ?flash?"} +# set flash 0 +# if {[llength $argv]==2} { +# if {[lindex $argv 1] ne "flash"} {error "Second argument must be flash"} +# set flash 1 +# } +# set out [file normalize [lindex $argv 0]] +# file mkdir $out +# file mkdir $out/ip +# proc phase {name} { +# global out +# set f [open $out/phase.txt w];puts $f $name;close $f +# puts "BOARD_PHASE $name" +# } +# set_param general.maxThreads 8 +# phase CREATE_IP +BOARD_PHASE CREATE_IP +# create_project -in_memory -part xc7a100tcsg324-1 +# set_property target_language Verilog [current_project] +# create_ip -name mig_7series -vendor xilinx.com -library ip -version 4.2 -module_name arty_ddr3 -dir $out/ip +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data0/tools/Xilinx/Vivado/2024.1/data/ip'. +# set_property CONFIG.XML_INPUT_FILE $root/board/vendor/mig.prj [get_ips arty_ddr3] +INFO: [IP_Flow 19-3484] Absolute path of file '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/vendor/mig.prj' provided. It will be converted relative to IP Instance files '../../../../board/vendor/mig.prj' +INFO: [Device 21-403] Loading part xc7a100tcsg324-1 +INFO: [Device 21-9227] Part: xc7a100tcsg324-1 does not have CEAM library. +# create_ip -name axi_clock_converter -vendor xilinx.com -library ip -version 2.1 -module_name toy_axi_cdc -dir $out/ip +# set_property -dict {CONFIG.PROTOCOL AXI4 CONFIG.ADDR_WIDTH 28 CONFIG.DATA_WIDTH 128 CONFIG.ID_WIDTH 4 CONFIG.ACLK_ASYNC 1 CONFIG.SYNCHRONIZATION_STAGES 3} [get_ips toy_axi_cdc] +# generate_target all [get_ips] +INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'arty_ddr3'... +INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'arty_ddr3'... +INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'arty_ddr3'... +INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'arty_ddr3'... +INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'arty_ddr3'... +INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'toy_axi_cdc'... +INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'toy_axi_cdc'... +WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_ooc.xdc' +INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'toy_axi_cdc'... +INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'toy_axi_cdc'... +INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'toy_axi_cdc'... +generate_target: Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 2222.848 ; gain = 275.328 ; free physical = 491940 ; free virtual = 628327 +# report_ip_status -file $out/ip-status.rpt +# phase SYNTH_IP +BOARD_PHASE SYNTH_IP +# synth_ip [get_ips] +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data0/tools/Xilinx/Vivado/2024.1/data/ip'. +WARNING: [Vivado 12-13650] The IP file '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3.xci' has been moved from its original location, as a result the outputs for this IP will now be generated in '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3'. Alternatively a copy of the IP can be imported into the project using one of the 'import_ip' or 'import_files' commands. +Command: synth_design -top arty_ddr3 -part xc7a100tcsg324-1 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. +INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes +INFO: [Synth 8-7075] Helper process launched with PID 20494 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2658.477 ; gain = 417.715 ; free physical = 491599 ; free virtual = 627992 +--------------------------------------------------------------------------------- +WARNING: [Synth 8-10515] begin/end is required for generate-for in this mode of Verilog [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v:253] +INFO: [Synth 8-11241] undeclared symbol 'dbg_sel_po_incdec', assumed default net type 'wire' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:1223] +INFO: [Synth 8-11241] undeclared symbol 'dbg_po_f_inc', assumed default net type 'wire' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:1227] +INFO: [Synth 8-11241] undeclared symbol 'dbg_po_f_stg23_sel', assumed default net type 'wire' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:1228] +INFO: [Synth 8-11241] undeclared symbol 'dbg_po_f_dec', assumed default net type 'wire' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:1229] +INFO: [Synth 8-6157] synthesizing module 'arty_ddr3' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3.v:70] +INFO: [Synth 8-6157] synthesizing module 'arty_ddr3_mig' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:75] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_tempmon' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v:69] + Parameter TCQ bound to: 100 - type: integer + Parameter TEMP_MON_CONTROL bound to: INTERNAL - type: string + Parameter XADC_CLK_PERIOD bound to: 5000 - type: integer + Parameter tTEMPSAMPLE bound to: 10000000 - type: integer +INFO: [Synth 8-6157] synthesizing module 'XADC' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:143027] + Parameter INIT_40 bound to: 16'b0001000000000000 + Parameter INIT_41 bound to: 16'b0010111111111111 + Parameter INIT_42 bound to: 16'b0000100000000000 + Parameter INIT_48 bound to: 16'b0000000100000001 + Parameter INIT_49 bound to: 16'b0000000000000000 + Parameter INIT_4A bound to: 16'b0000000100000000 + Parameter INIT_4B bound to: 16'b0000000000000000 + Parameter INIT_4C bound to: 16'b0000000000000000 + Parameter INIT_4D bound to: 16'b0000000000000000 + Parameter INIT_4E bound to: 16'b0000000000000000 + Parameter INIT_4F bound to: 16'b0000000000000000 + Parameter INIT_50 bound to: 16'b1011010111101101 + Parameter INIT_51 bound to: 16'b0101011111100100 + Parameter INIT_52 bound to: 16'b1010000101000111 + Parameter INIT_53 bound to: 16'b1100101000110011 + Parameter INIT_54 bound to: 16'b1010100100111010 + Parameter INIT_55 bound to: 16'b0101001011000110 + Parameter INIT_56 bound to: 16'b1001010101010101 + Parameter INIT_57 bound to: 16'b1010111001001110 + Parameter INIT_58 bound to: 16'b0101100110011001 + Parameter INIT_5C bound to: 16'b0101000100010001 + Parameter SIM_DEVICE bound to: 7SERIES - type: string +INFO: [Synth 8-6155] done synthesizing module 'XADC' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:143027] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_tempmon' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v:69] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_iodelay_ctrl' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_iodelay_ctrl.v:80] + Parameter TCQ bound to: 100 - type: integer + Parameter IODELAY_GRP0 bound to: ARTY_DDR3_IODELAY_MIG0 - type: string + Parameter IODELAY_GRP1 bound to: ARTY_DDR3_IODELAY_MIG1 - type: string + Parameter REFCLK_TYPE bound to: NO_BUFFER - type: string + Parameter SYSCLK_TYPE bound to: NO_BUFFER - type: string + Parameter SYS_RST_PORT bound to: FALSE - type: string + Parameter RST_ACT_LOW bound to: 1 - type: integer + Parameter DIFF_TERM_REFCLK bound to: TRUE - type: string + Parameter FPGA_SPEED_GRADE bound to: 1 - type: integer + Parameter REF_CLK_MMCM_IODELAY_CTRL bound to: FALSE - type: string +INFO: [Synth 8-6157] synthesizing module 'IDELAYCTRL' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:75739] +INFO: [Synth 8-6155] done synthesizing module 'IDELAYCTRL' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:75739] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_iodelay_ctrl' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_iodelay_ctrl.v:80] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_clk_ibuf' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_clk_ibuf.v:68] + Parameter SYSCLK_TYPE bound to: NO_BUFFER - type: string + Parameter DIFF_TERM_SYSCLK bound to: TRUE - type: string +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_clk_ibuf' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_clk_ibuf.v:68] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_infrastructure' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:78] + Parameter TCQ bound to: 100 - type: integer + Parameter CLKIN_PERIOD bound to: 6000 - type: integer + Parameter nCK_PER_CLK bound to: 4 - type: integer + Parameter SYSCLK_TYPE bound to: NO_BUFFER - type: string + Parameter CLKFBOUT_MULT bound to: 8 - type: integer + Parameter DIVCLK_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT0_DIVIDE bound to: 2 - type: integer + Parameter CLKOUT1_DIVIDE bound to: 4 - type: integer + Parameter CLKOUT2_DIVIDE bound to: 64 - type: integer + Parameter CLKOUT3_DIVIDE bound to: 16 - type: integer + Parameter MMCM_VCO bound to: 666 - type: integer + Parameter MMCM_MULT_F bound to: 8 - type: integer + Parameter MMCM_DIVCLK_DIVIDE bound to: 1 - type: integer + Parameter RST_ACT_LOW bound to: 1 - type: integer + Parameter tCK bound to: 3000 - type: integer + Parameter MEM_TYPE bound to: DDR3 - type: string +INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82388] + Parameter BANDWIDTH bound to: HIGH - type: string + Parameter CLKFBOUT_MULT_F bound to: 8.000000 - type: double + Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double + Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKIN1_PERIOD bound to: 12.000000 - type: double + Parameter CLKOUT0_DIVIDE_F bound to: 16.000000 - type: double + Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT0_USE_FINE_PS bound to: TRUE - type: string + Parameter CLKOUT1_DIVIDE bound to: 4 - type: integer + Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT4_CASCADE bound to: FALSE - type: string + Parameter COMPENSATION bound to: BUF_IN - type: string + Parameter DIVCLK_DIVIDE bound to: 1 - type: integer + Parameter REF_JITTER1 bound to: 0.000000 - type: double + Parameter STARTUP_WAIT bound to: FALSE - type: string +INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82388] +INFO: [Synth 8-6157] synthesizing module 'BUFG' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951] +INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951] +INFO: [Synth 8-6157] synthesizing module 'PLLE2_ADV' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114750] + Parameter BANDWIDTH bound to: OPTIMIZED - type: string + Parameter CLKFBOUT_MULT bound to: 8 - type: integer + Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double + Parameter CLKIN1_PERIOD bound to: 6.000000 - type: double + Parameter CLKOUT0_DIVIDE bound to: 2 - type: integer + Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT1_DIVIDE bound to: 4 - type: integer + Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT2_DIVIDE bound to: 64 - type: integer + Parameter CLKOUT2_DUTY_CYCLE bound to: 0.062500 - type: double + Parameter CLKOUT2_PHASE bound to: 9.843750 - type: double + Parameter CLKOUT3_DIVIDE bound to: 16 - type: integer + Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT3_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT4_DIVIDE bound to: 8 - type: integer + Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT4_PHASE bound to: 168.750000 - type: double + Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT5_PHASE bound to: 0.000000 - type: double + Parameter COMPENSATION bound to: INTERNAL - type: string + Parameter DIVCLK_DIVIDE bound to: 1 - type: integer + Parameter REF_JITTER1 bound to: 0.010000 - type: double + Parameter REF_JITTER2 bound to: 0.010000 - type: double + Parameter STARTUP_WAIT bound to: FALSE - type: string +INFO: [Synth 8-6155] done synthesizing module 'PLLE2_ADV' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114750] +INFO: [Synth 8-6157] synthesizing module 'BUFH' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:2199] +INFO: [Synth 8-6155] done synthesizing module 'BUFH' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:2199] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_infrastructure' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:78] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_memc_ui_top_axi' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_memc_ui_top_axi.v:71] + Parameter TCQ bound to: 100 - type: integer + Parameter DDR3_VDD_OP_VOLT bound to: 135 - type: string + Parameter PAYLOAD_WIDTH bound to: 16 - type: integer + Parameter ADDR_CMD_MODE bound to: 1T - type: string + Parameter AL bound to: 0 - type: string + Parameter BANK_WIDTH bound to: 3 - type: integer + Parameter BM_CNT_WIDTH bound to: 2 - type: integer + Parameter BURST_MODE bound to: 8 - type: string + Parameter BURST_TYPE bound to: SEQ - type: string + Parameter CA_MIRROR bound to: OFF - type: string + Parameter CK_WIDTH bound to: 1 - type: integer + Parameter CL bound to: 5 - type: integer + Parameter COL_WIDTH bound to: 10 - type: integer + Parameter CMD_PIPE_PLUS1 bound to: ON - type: string + Parameter CS_WIDTH bound to: 1 - type: integer + Parameter CKE_WIDTH bound to: 1 - type: integer + Parameter CWL bound to: 5 - type: integer + Parameter DATA_WIDTH bound to: 16 - type: integer + Parameter DATA_BUF_ADDR_WIDTH bound to: 5 - type: integer + Parameter DM_WIDTH bound to: 2 - type: integer + Parameter DQ_CNT_WIDTH bound to: 4 - type: integer + Parameter DQ_WIDTH bound to: 16 - type: integer + Parameter DQS_CNT_WIDTH bound to: 1 - type: integer + Parameter DQS_WIDTH bound to: 2 - type: integer + Parameter DRAM_TYPE bound to: DDR3 - type: string + Parameter DRAM_WIDTH bound to: 8 - type: integer + Parameter ECC bound to: OFF - type: string + Parameter ECC_WIDTH bound to: 0 - type: integer + Parameter ECC_TEST bound to: OFF - type: string + Parameter MC_ERR_ADDR_WIDTH bound to: 28 - type: integer + Parameter MASTER_PHY_CTL bound to: 0 - type: integer + Parameter nAL bound to: 0 - type: integer + Parameter nBANK_MACHS bound to: 4 - type: integer + Parameter nCK_PER_CLK bound to: 4 - type: integer + Parameter nCS_PER_RANK bound to: 1 - type: integer + Parameter ORDERING bound to: NORM - type: string + Parameter IBUF_LPWR_MODE bound to: OFF - type: string + Parameter BANK_TYPE bound to: HR_IO - type: string + Parameter DATA_IO_PRIM_TYPE bound to: HR_LP - type: string + Parameter DATA_IO_IDLE_PWRDWN bound to: ON - type: string + Parameter IODELAY_GRP0 bound to: ARTY_DDR3_IODELAY_MIG0 - type: string + Parameter IODELAY_GRP1 bound to: ARTY_DDR3_IODELAY_MIG1 - type: string + Parameter FPGA_SPEED_GRADE bound to: 1 - type: integer + Parameter OUTPUT_DRV bound to: LOW - type: string + Parameter REG_CTRL bound to: OFF - type: string + Parameter RTT_NOM bound to: 40 - type: string + Parameter RTT_WR bound to: OFF - type: string + Parameter STARVE_LIMIT bound to: 2 - type: integer + Parameter tCK bound to: 3000 - type: integer + Parameter tCKE bound to: 5625 - type: integer + Parameter tFAW bound to: 45000 - type: integer + Parameter tPRDI bound to: 1000000 - type: integer + Parameter tRAS bound to: 36000 - type: integer + Parameter tRCD bound to: 13500 - type: integer + Parameter tREFI bound to: 7800000 - type: integer + Parameter tRFC bound to: 160000 - type: integer + Parameter tRP bound to: 13500 - type: integer + Parameter tRRD bound to: 7500 - type: integer + Parameter tRTP bound to: 7500 - type: integer + Parameter tWTR bound to: 7500 - type: integer + Parameter tZQI bound to: 128000000 - type: integer + Parameter tZQCS bound to: 64 - type: integer + Parameter USER_REFRESH bound to: OFF - type: string + Parameter TEMP_MON_EN bound to: ON - type: string + Parameter WRLVL bound to: ON - type: string + Parameter DEBUG_PORT bound to: OFF - type: string + Parameter CAL_WIDTH bound to: HALF - type: string + Parameter RANK_WIDTH bound to: 1 - type: integer + Parameter RANKS bound to: 1 - type: integer + Parameter ODT_WIDTH bound to: 1 - type: integer + Parameter ROW_WIDTH bound to: 14 - type: integer + Parameter ADDR_WIDTH bound to: 28 - type: integer + Parameter APP_MASK_WIDTH bound to: 16 - type: integer + Parameter APP_DATA_WIDTH bound to: 128 - type: integer + Parameter BYTE_LANES_B0 bound to: 4'b1111 + Parameter BYTE_LANES_B1 bound to: 4'b0000 + Parameter BYTE_LANES_B2 bound to: 4'b0000 + Parameter BYTE_LANES_B3 bound to: 4'b0000 + Parameter BYTE_LANES_B4 bound to: 4'b0000 + Parameter DATA_CTL_B0 bound to: 4'b1100 + Parameter DATA_CTL_B1 bound to: 4'b0000 + Parameter DATA_CTL_B2 bound to: 4'b0000 + Parameter DATA_CTL_B3 bound to: 4'b0000 + Parameter DATA_CTL_B4 bound to: 4'b0000 + Parameter PHY_0_BITLANES bound to: 48'b001111111110001111111110111111111111101111111111 + Parameter PHY_1_BITLANES bound to: 48'b000000000000000000000000000000000000000000000000 + Parameter PHY_2_BITLANES bound to: 48'b000000000000000000000000000000000000000000000000 + Parameter CK_BYTE_MAP bound to: 144'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter ADDR_MAP bound to: 192'b000000000000000000000000000000000000000000000010000000000100000000001001000000000111000000000001000000000101000000000110000000000011000000010000000000010010000000010100000000010001000000011010 + Parameter BANK_MAP bound to: 36'b000000011011000000010111000000010011 + Parameter CAS_MAP bound to: 12'b000000010101 + Parameter CKE_ODT_BYTE_MAP bound to: 8'b00000000 + Parameter CKE_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011001 + Parameter ODT_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000 + Parameter CKE_ODT_AUX bound to: FALSE - type: string + Parameter CS_MAP bound to: 120'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001011 + Parameter PARITY_MAP bound to: 12'b000000000000 + Parameter RAS_MAP bound to: 12'b000000010110 + Parameter WE_MAP bound to: 12'b000000011000 + Parameter DQS_BYTE_MAP bound to: 144'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000011 + Parameter DATA0_MAP bound to: 96'b000000110100000000110010000000111000000000110101000000110001000000110111000000110110000000110011 + Parameter DATA1_MAP bound to: 96'b000000100011000000100110000000100010000000101000000000100101000000100111000000100001000000100100 + Parameter DATA2_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA3_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA4_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA5_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA6_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA7_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA8_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA9_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA10_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA11_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA12_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA13_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA14_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA15_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA16_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA17_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter MASK0_MAP bound to: 108'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101001000000111001 + Parameter MASK1_MAP bound to: 108'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter SLOT_0_CONFIG bound to: 8'b00000001 + Parameter SLOT_1_CONFIG bound to: 8'b00000000 + Parameter MEM_ADDR_ORDER bound to: BANK_ROW_COLUMN - type: string + Parameter CALIB_ROW_ADD bound to: 16'b0000000000000000 + Parameter CALIB_COL_ADD bound to: 12'b000000000000 + Parameter CALIB_BA_ADD bound to: 3'b000 + Parameter SIM_BYPASS_INIT_CAL bound to: OFF - type: string + Parameter REFCLK_FREQ bound to: 200.000000 - type: double + Parameter USE_CS_PORT bound to: 1 - type: integer + Parameter USE_DM_PORT bound to: 1 - type: integer + Parameter USE_ODT_PORT bound to: 1 - type: integer + Parameter IDELAY_ADJ bound to: OFF - type: string + Parameter FINE_PER_BIT bound to: OFF - type: string + Parameter CENTER_COMP_MODE bound to: OFF - type: string + Parameter PI_VAL_ADJ bound to: OFF - type: string + Parameter SKIP_CALIB bound to: FALSE - type: string + Parameter TAPSPERKCLK bound to: 112 - type: integer + Parameter C_S_AXI_ID_WIDTH bound to: 4 - type: integer + Parameter C_S_AXI_ADDR_WIDTH bound to: 28 - type: integer + Parameter C_S_AXI_DATA_WIDTH bound to: 128 - type: integer + Parameter C_S_AXI_SUPPORTS_NARROW_BURST bound to: 0 - type: integer + Parameter C_RD_WR_ARB_ALGORITHM bound to: RD_PRI_REG - type: string + Parameter C_S_AXI_REG_EN0 bound to: 20'b00000000000000000000 + Parameter C_S_AXI_REG_EN1 bound to: 20'b00000000000000000000 + Parameter C_S_AXI_CTRL_ADDR_WIDTH bound to: 32 - type: integer + Parameter C_S_AXI_CTRL_DATA_WIDTH bound to: 32 - type: integer + Parameter C_S_AXI_BASEADDR bound to: 0 - type: integer + Parameter C_ECC_ONOFF_RESET_VALUE bound to: 1 - type: integer + Parameter C_ECC_CE_COUNTER_WIDTH bound to: 8 - type: integer + Parameter FPGA_VOLT_TYPE bound to: N - type: string +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_mem_intfc' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_mem_intfc.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_mc' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v:73] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_rank_mach' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_mach.v:71] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_rank_cntrl' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v:79] +INFO: [Synth 8-6157] synthesizing module 'SRLC32E' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:137412] +INFO: [Synth 8-6155] done synthesizing module 'SRLC32E' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:137412] +WARNING: [Synth 8-567] referenced signal 'periodic_rd_generation.periodic_rd_timer_one' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v:509] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_rank_cntrl' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v:79] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_rank_common' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_common.v:72] +WARNING: [Synth 8-567] referenced signal 'zq_cntrl.zq_tick' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_common.v:172] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_round_robin_arb' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_round_robin_arb' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_round_robin_arb__parameterized0' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_round_robin_arb__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_rank_common' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_common.v:72] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_rank_mach' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_mach.v:71] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_mach' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_mach.v:72] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_compare' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v:74] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_compare' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v:74] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_state' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_queue' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_cntrl' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized0' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state__parameterized0' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_state__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue__parameterized0' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_queue__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state__parameterized1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_state__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue__parameterized1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_queue__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized2' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state__parameterized2' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_state__parameterized2' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue__parameterized2' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_queue__parameterized2' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized2' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_common' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_common.v:73] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_common' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_common.v:73] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_arb_mux' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_mux.v:69] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_arb_row_col' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v:83] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_round_robin_arb__parameterized1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_round_robin_arb__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_arb_row_col' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v:83] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_arb_select' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:75] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_arb_select' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:75] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_arb_mux' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_mux.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_mach' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_mach.v:72] +WARNING: [Synth 8-7071] port 'idle' of module 'mig_7series_v4_2_bank_mach' is unconnected for instance 'bank_mach0' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v:670] +WARNING: [Synth 8-7023] instance 'bank_mach0' of module 'mig_7series_v4_2_bank_mach' has 74 connections declared, but only 73 given [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v:670] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_col_mach' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_col_mach.v:88] +INFO: [Synth 8-6157] synthesizing module 'RAM32M' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:129077] +INFO: [Synth 8-6155] done synthesizing module 'RAM32M' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:129077] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_col_mach' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_col_mach.v:88] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_mc' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v:73] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_top' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_top.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_mc_phy_wrapper' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:71] +INFO: [Synth 8-6157] synthesizing module 'OBUF' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96458] +INFO: [Synth 8-6155] done synthesizing module 'OBUF' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96458] +INFO: [Synth 8-6157] synthesizing module 'OBUFT' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96846] +INFO: [Synth 8-6155] done synthesizing module 'OBUFT' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96846] +INFO: [Synth 8-6157] synthesizing module 'IOBUF_INTERMDISABLE' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:79002] +INFO: [Synth 8-6155] done synthesizing module 'IOBUF_INTERMDISABLE' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:79002] +INFO: [Synth 8-6157] synthesizing module 'IOBUFDS_INTERMDISABLE' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:78516] +INFO: [Synth 8-6155] done synthesizing module 'IOBUFDS_INTERMDISABLE' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:78516] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +WARNING: [Synth 8-7071] port 'afull' of module 'mig_7series_v4_2_ddr_of_pre_fifo' is unconnected for instance 'phy_ctl_pre_fifo_0' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1428] +WARNING: [Synth 8-7023] instance 'phy_ctl_pre_fifo_0' of module 'mig_7series_v4_2_ddr_of_pre_fifo' has 8 connections declared, but only 7 given [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1428] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo__parameterized0' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +WARNING: [Synth 8-7071] port 'afull' of module 'mig_7series_v4_2_ddr_of_pre_fifo' is unconnected for instance 'phy_ctl_pre_fifo_1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1445] +WARNING: [Synth 8-7023] instance 'phy_ctl_pre_fifo_1' of module 'mig_7series_v4_2_ddr_of_pre_fifo' has 8 connections declared, but only 7 given [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1445] +WARNING: [Synth 8-7071] port 'afull' of module 'mig_7series_v4_2_ddr_of_pre_fifo' is unconnected for instance 'phy_ctl_pre_fifo_2' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1462] +WARNING: [Synth 8-7023] instance 'phy_ctl_pre_fifo_2' of module 'mig_7series_v4_2_ddr_of_pre_fifo' has 8 connections declared, but only 7 given [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1462] +WARNING: [Synth 8-5974] attribute "use_dsp48" has been deprecated, please use "use_dsp" instead +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_mc_phy' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_4lanes' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:72] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo__parameterized1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +INFO: [Synth 8-6157] synthesizing module 'ODDR' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100102] +INFO: [Synth 8-6155] done synthesizing module 'ODDR' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100102] +INFO: [Synth 8-6157] synthesizing module 'OBUFDS' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96472] +INFO: [Synth 8-6155] done synthesizing module 'OBUFDS' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96472] +INFO: [Synth 8-6157] synthesizing module 'PHASER_OUT_PHY' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114573] +INFO: [Synth 8-6155] done synthesizing module 'PHASER_OUT_PHY' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114573] +INFO: [Synth 8-6157] synthesizing module 'OUT_FIFO' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100824] +INFO: [Synth 8-6155] done synthesizing module 'OUT_FIFO' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100824] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_group_io' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6157] synthesizing module 'OSERDESE2' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6155] done synthesizing module 'OSERDESE2' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_group_io' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized0' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized0' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_if_post_fifo' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v:68] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v:110] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_if_post_fifo' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v:68] +INFO: [Synth 8-6157] synthesizing module 'PHASER_IN_PHY' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114436] +INFO: [Synth 8-6155] done synthesizing module 'PHASER_IN_PHY' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114436] +INFO: [Synth 8-6157] synthesizing module 'IN_FIFO' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:78141] +INFO: [Synth 8-6155] done synthesizing module 'IN_FIFO' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:78141] +INFO: [Synth 8-6157] synthesizing module 'PHASER_OUT_PHY__parameterized0' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114573] +INFO: [Synth 8-6155] done synthesizing module 'PHASER_OUT_PHY__parameterized0' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114573] +INFO: [Synth 8-6157] synthesizing module 'OUT_FIFO__parameterized0' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100824] +INFO: [Synth 8-6155] done synthesizing module 'OUT_FIFO__parameterized0' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100824] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6157] synthesizing module 'IDELAYE2' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:75752] +INFO: [Synth 8-6155] done synthesizing module 'IDELAYE2' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:75752] +INFO: [Synth 8-6157] synthesizing module 'ISERDESE2' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:80773] +INFO: [Synth 8-6155] done synthesizing module 'ISERDESE2' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:80773] +INFO: [Synth 8-6157] synthesizing module 'OSERDESE2__parameterized0' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6155] done synthesizing module 'OSERDESE2__parameterized0' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6157] synthesizing module 'OSERDESE2__parameterized1' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6155] done synthesizing module 'OSERDESE2__parameterized1' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized2' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized2' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'BUFIO' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:2224] +INFO: [Synth 8-6155] done synthesizing module 'BUFIO' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:2224] +INFO: [Synth 8-6157] synthesizing module 'PHY_CONTROL' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114664] +INFO: [Synth 8-6155] done synthesizing module 'PHY_CONTROL' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114664] +INFO: [Synth 8-226] default block is never used [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:1557] +INFO: [Synth 8-6157] synthesizing module 'PHASER_REF' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114648] +INFO: [Synth 8-6155] done synthesizing module 'PHASER_REF' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114648] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_4lanes' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:72] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_mc_phy' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy.v:70] +WARNING: [Synth 8-689] width (12) of port connection 'pi_dqs_found_lanes' does not match port width (4) of module 'mig_7series_v4_2_ddr_mc_phy' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1671] +WARNING: [Synth 8-689] width (12) of port connection 'pi_phase_locked_lanes' does not match port width (4) of module 'mig_7series_v4_2_ddr_mc_phy' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1679] +WARNING: [Synth 8-7071] port 'of_data_a_full' of module 'mig_7series_v4_2_ddr_mc_phy' is unconnected for instance 'u_ddr_mc_phy' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1579] +WARNING: [Synth 8-7023] instance 'u_ddr_mc_phy' of module 'mig_7series_v4_2_ddr_mc_phy' has 89 connections declared, but only 88 given [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1579] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_mc_phy_wrapper' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:71] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_calib_top' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:82] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_wrlvl' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:90] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:797] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_wrlvl' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:90] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v:68] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v:68] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_dqs_found_cal_hr' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:79] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_dqs_found_cal_hr' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:79] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_rdlvl' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:79] +WARNING: [Synth 8-5974] attribute "use_dsp48" has been deprecated, please use "use_dsp" instead +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2746] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_rdlvl' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:79] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_prbs_gen' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:92] +WARNING: [Synth 8-7186] Applying attribute ram_style = "distributed" is ignored, object 'rd_addr' is not inferred as ram due to incorrect usage [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:203] +WARNING: [Synth 8-7186] Applying attribute ram_style = "distributed" is ignored, object 'mem_out' is not inferred as ram due to incorrect usage [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:205] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_prbs_gen' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:92] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_init' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:89] +INFO: [Synth 8-226] default block is never used [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:5273] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_init' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:89] +WARNING: [Synth 8-7071] port 'complex_oclk_prech_req' of module 'mig_7series_v4_2_ddr_phy_init' is unconnected for instance 'u_ddr_phy_init' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:1367] +WARNING: [Synth 8-7023] instance 'u_ddr_phy_init' of module 'mig_7series_v4_2_ddr_phy_init' has 131 connections declared, but only 130 given [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:1367] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_wrcal' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:77] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:1130] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_wrcal' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:77] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_tempmon' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_tempmon' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_calib_top' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:82] +WARNING: [Synth 8-689] width (12) of port connection 'pi_dqs_found_lanes' does not match port width (4) of module 'mig_7series_v4_2_ddr_calib_top' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_top.v:1340] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_top' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_top.v:70] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_mem_intfc' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_mem_intfc.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ui_top' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_top.v:71] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ui_cmd' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_cmd.v:70] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ui_cmd' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_cmd.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ui_wr_data' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v:131] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v:342] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v:380] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ui_wr_data' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v:131] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ui_rd_data' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:140] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:406] +WARNING: [Synth 8-567] referenced signal 'not_strict_mode.occ_cnt_r' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403] +WARNING: [Synth 8-567] referenced signal 'not_strict_mode.free_rd_buf' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403] +WARNING: [Synth 8-567] referenced signal 'not_strict_mode.occ_minus_one' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403] +WARNING: [Synth 8-567] referenced signal 'not_strict_mode.occ_plus_one' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403] +WARNING: [Synth 8-567] referenced signal 'not_strict_mode.rd_data_buf_addr_r_lcl' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:432] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ui_rd_data' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:140] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ui_top' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_top.v:71] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_axi_mc' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc.v:90] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_axi_register_slice' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axi_register_slice.v:63] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized0' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized2' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized2' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_axi_register_slice' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axi_register_slice.v:63] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_axi_mc_aw_channel' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_aw_channel.v:57] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_axi_mc_cmd_translator' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_cmd_translator.v:62] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_axi_mc_incr_cmd' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_incr_cmd.v:64] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_incr_cmd' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_incr_cmd.v:64] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_axi_mc_wrap_cmd' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wrap_cmd.v:97] +INFO: [Common 17-14] Message 'Synth 8-6157' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_wrap_cmd' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wrap_cmd.v:97] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_cmd_translator' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_cmd_translator.v:62] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_wr_cmd_fsm' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wr_cmd_fsm.v:76] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_aw_channel' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_aw_channel.v:57] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_w_channel' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_w_channel.v:64] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_fifo' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_fifo.v:70] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_b_channel' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_b_channel.v:83] +INFO: [Common 17-14] Message 'Synth 8-6155' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [Synth 8-589] replacing case/wildcard equality operator === with logical equality operator == [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_r_channel.v:189] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_r_channel.v:315] +WARNING: [Synth 8-3848] Net ui_addn_clk_0 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:140] +WARNING: [Synth 8-3848] Net ui_addn_clk_1 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:141] +WARNING: [Synth 8-3848] Net ui_addn_clk_2 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:142] +WARNING: [Synth 8-3848] Net ui_addn_clk_3 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:143] +WARNING: [Synth 8-3848] Net ui_addn_clk_4 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:144] +WARNING: [Synth 8-6014] Unused sequential element periodic_rd_generation.read_this_rank_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v:487] +WARNING: [Synth 8-3936] Found unconnected internal register 'dbl_req_reg' and it is trimmed from '6' to '5' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:145] +WARNING: [Synth 8-3936] Found unconnected internal register 'dbl_last_master_ns_reg' and it is trimmed from '6' to '4' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:143] +WARNING: [Synth 8-6014] Unused sequential element last_master_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:181] +WARNING: [Synth 8-3848] Net channel[0].inh_group in module/entity mig_7series_v4_2_round_robin_arb__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:153] +WARNING: [Synth 8-3936] Found unconnected internal register 'col_addr_template_reg' and it is trimmed from '16' to '14' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v:251] +WARNING: [Synth 8-3936] Found unconnected internal register 'dbl_req_reg' and it is trimmed from '8' to '7' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:145] +WARNING: [Synth 8-3936] Found unconnected internal register 'dbl_last_master_ns_reg' and it is trimmed from '8' to '6' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:143] +WARNING: [Synth 8-6014] Unused sequential element sent_row_or_maint_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v:357] +WARNING: [Synth 8-6014] Unused sequential element mc_aux_out_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:680] +WARNING: [Synth 8-6014] Unused sequential element mc_aux_out_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:681] +WARNING: [Synth 8-3848] Net col_mux.col_row_r in module/entity mig_7series_v4_2_arb_select does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:390] +WARNING: [Synth 8-3936] Found unconnected internal register 'read_fifo.fifo_out_data_r_reg' and it is trimmed from '12' to '8' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_col_mach.v:396] +WARNING: [Synth 8-3848] Net oserdes_dqts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:143] +WARNING: [Synth 8-3848] Net oserdes_dqs_buf in module/entity mig_7series_v4_2_ddr_byte_group_io does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:144] +WARNING: [Synth 8-3848] Net oserdes_dqsts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:145] +WARNING: [Synth 8-3848] Net iserdes_dout in module/entity mig_7series_v4_2_ddr_byte_group_io does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:92] +WARNING: [Synth 8-6014] Unused sequential element ififo_rst_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:307] +WARNING: [Synth 8-3848] Net rclk in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:147] +WARNING: [Synth 8-3848] Net pi_iserdes_rst in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:193] +WARNING: [Synth 8-3848] Net pi_fine_overflow in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:195] +WARNING: [Synth 8-3848] Net pi_counter_read_val_w in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:431] +WARNING: [Synth 8-3848] Net dqs_out_of_range in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:198] +WARNING: [Synth 8-3848] Net iserdes_clk in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:275] +WARNING: [Synth 8-3848] Net iserdes_clkdiv in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:276] +WARNING: [Synth 8-3848] Net oserdes_dqts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:143] +WARNING: [Synth 8-3848] Net oserdes_dqs_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:144] +WARNING: [Synth 8-3848] Net oserdes_dqsts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:145] +WARNING: [Synth 8-3848] Net iserdes_dout in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:92] +WARNING: [Synth 8-6014] Unused sequential element ififo_rst_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:307] +WARNING: [Synth 8-3848] Net rclk in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:147] +WARNING: [Synth 8-3848] Net pi_iserdes_rst in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:193] +WARNING: [Synth 8-3848] Net pi_fine_overflow in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:195] +WARNING: [Synth 8-3848] Net pi_counter_read_val_w in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:431] +WARNING: [Synth 8-3848] Net dqs_out_of_range in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:198] +WARNING: [Synth 8-3848] Net iserdes_clk in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:275] +WARNING: [Synth 8-3848] Net iserdes_clkdiv in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:276] +WARNING: [Synth 8-6014] Unused sequential element fine_delay_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:185] +WARNING: [Synth 8-3848] Net dummy_i5 in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized1 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:269] +WARNING: [Synth 8-3848] Net dummy_i6 in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized1 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:270] +WARNING: [Synth 8-3848] Net dummy_i5 in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized2 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:269] +WARNING: [Synth 8-3848] Net dummy_i6 in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized2 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:270] +WARNING: [Synth 8-6014] Unused sequential element B_rst_primitives_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:737] +WARNING: [Synth 8-6014] Unused sequential element C_rst_primitives_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:738] +WARNING: [Synth 8-6014] Unused sequential element D_rst_primitives_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:739] +WARNING: [Synth 8-3936] Found unconnected internal register 'byte_sel_data_map_reg' and it is trimmed from '96' to '88' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:731] +WARNING: [Synth 8-3848] Net phy_data_full in module/entity mig_7series_v4_2_ddr_mc_phy_wrapper does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:227] +WARNING: [Synth 8-6014] Unused sequential element fast_cal_fine_cnt_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:790] +WARNING: [Synth 8-6014] Unused sequential element fast_cal_coarse_cnt_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:791] +WARNING: [Synth 8-6014] Unused sequential element final_corse_dec_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:792] +WARNING: [Synth 8-6014] Unused sequential element add_smallest_reg[1] was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:516] +WARNING: [Synth 8-6014] Unused sequential element add_largest_reg[0] was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:517] +WARNING: [Synth 8-6014] Unused sequential element add_largest_reg[1] was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:517] +WARNING: [Synth 8-6014] Unused sequential element dqs_wl_po_en_stg2_c_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:628] +WARNING: [Synth 8-6014] Unused sequential element po_en_stg2_c_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v:162] +WARNING: [Synth 8-6014] Unused sequential element rank_final_loop[0].final_do_max_reg[0] was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:1116] +WARNING: [Synth 8-6014] Unused sequential element rank_final_loop[0].final_do_index_reg[0] was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:1146] +WARNING: [Synth 8-6014] Unused sequential element dqsfound_retry_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:690] +WARNING: [Synth 8-3848] Net dqsfound_retry_done in module/entity mig_7series_v4_2_ddr_phy_dqs_found_cal_hr does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:131] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[0].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[1].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[2].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[3].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[4].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[5].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[6].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[7].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_stg1_done_int_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:686] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_stg1_done_int_r2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:687] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_stg1_done_int_r3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:688] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_last_byte_done_int_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:689] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_last_byte_done_int_r2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:690] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_last_byte_done_int_r3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:691] +WARNING: [Synth 8-6014] Unused sequential element fine_dly_dec_done_r3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:940] +WARNING: [Synth 8-6014] Unused sequential element fine_dly_dec_done_r4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:941] +WARNING: [Synth 8-6014] Unused sequential element regl_rank_done_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:1044] +WARNING: [Synth 8-6014] Unused sequential element cal1_state_r2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2696] +WARNING: [Synth 8-6014] Unused sequential element cal1_state_r3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2697] +WARNING: [Synth 8-6014] Unused sequential element cal1_cnt_cpt_timing_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:610] +WARNING: [Synth 8-6014] Unused sequential element sample_cnt_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:156] +WARNING: [Synth 8-6014] Unused sequential element reseed_prbs_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:157] +WARNING: [Synth 8-6014] Unused sequential element lfsr_q_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:174] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.phy_tmp_cs1_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4271] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.phy_tmp_odt_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4273] +WARNING: [Synth 8-6014] Unused sequential element wrlvl_final_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1421] +WARNING: [Synth 8-6014] Unused sequential element wrlvl_rank_cntr_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1539] +WARNING: [Synth 8-6014] Unused sequential element cnt_pwron_cke_done_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1781] +WARNING: [Synth 8-6014] Unused sequential element cnt_init_pre_wait_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1814] +WARNING: [Synth 8-6014] Unused sequential element cnt_init_pre_wait_done_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1815] +WARNING: [Synth 8-6014] Unused sequential element rnk_ref_cnt_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1941] +WARNING: [Synth 8-6014] Unused sequential element read_calib_int_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:2720] +WARNING: [Synth 8-6014] Unused sequential element read_calib_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:2727] +WARNING: [Synth 8-6014] Unused sequential element pi_dqs_found_rank_done_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:2778] +WARNING: [Synth 8-6014] Unused sequential element pi_dqs_found_all_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:2783] +WARNING: [Synth 8-6014] Unused sequential element complex_row0_rd_done_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:3339] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_wr_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:3632] +WARNING: [Synth 8-6014] Unused sequential element extend_cal_pat_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:3638] +WARNING: [Synth 8-6014] Unused sequential element cnt_init_data_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:3714] +WARNING: [Synth 8-6014] Unused sequential element victim_byte_cnt_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:818] +WARNING: [Synth 8-3936] Found unconnected internal register 'rdlvl_start_dly0_r_reg' and it is trimmed from '16' to '15' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1228] +WARNING: [Synth 8-3936] Found unconnected internal register 'wrcal_start_dly_r_reg' and it is trimmed from '16' to '15' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1230] +WARNING: [Synth 8-3936] Found unconnected internal register 'oclkdelay_start_dly_r_reg' and it is trimmed from '16' to '15' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1232] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr2_r_reg[1] was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4265] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr2_r_reg[2] was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4265] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr2_r_reg[3] was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4265] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr1_r_reg[1] was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4268] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr1_r_reg[2] was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4268] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr1_r_reg[3] was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4268] +WARNING: [Synth 8-6014] Unused sequential element prech_done_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1303] +WARNING: [Synth 8-6014] Unused sequential element calib_cmd_wren_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4229] +WARNING: [Synth 8-3848] Net calib_aux_out in module/entity mig_7series_v4_2_ddr_phy_init does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:276] +WARNING: [Synth 8-6014] Unused sequential element rd_active_r4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:534] +WARNING: [Synth 8-6014] Unused sequential element rd_active_r5_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:535] +WARNING: [Synth 8-6014] Unused sequential element pat1_detect_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:1124] +WARNING: [Synth 8-6014] Unused sequential element early1_detect_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:1125] +WARNING: [Synth 8-6014] Unused sequential element rd_mux_sel_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:438] +WARNING: [Synth 8-3848] Net i in module/entity mig_7series_v4_2_ddr_phy_wrcal does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:155] +WARNING: [Synth 8-6014] Unused sequential element calib_complete_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v:182] +WARNING: [Synth 8-6014] Unused sequential element sample_en_cnt_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v:188] +WARNING: [Synth 8-6014] Unused sequential element device_temp_capture_102_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v:290] +WARNING: [Synth 8-6014] Unused sequential element tempmon_sel_pi_incdec_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:883] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:898] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:899] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:900] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:901] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r5_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:902] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r6_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:903] +WARNING: [Synth 8-6014] Unused sequential element skip_calib_tap_off.skip_cal_tempmon_samp_en_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:2262] +WARNING: [Synth 8-6014] Unused sequential element wrlvl_final_mux_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:834] +WARNING: [Synth 8-3848] Net dbg_skip_cal in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:673] +WARNING: [Synth 8-3848] Net coarse_dec_err in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:662] +WARNING: [Synth 8-3848] Net dbg_poc in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:335] +WARNING: [Synth 8-3848] Net fine_delay_incdec_pb in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:341] +WARNING: [Synth 8-3848] Net fine_delay_sel in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:342] +WARNING: [Synth 8-3848] Net lim_done in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:620] +WARNING: [Synth 8-3848] Net lim2init_write_request in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:619] +WARNING: [Synth 8-3848] Net complex_ocal_num_samples_done_r in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:533] +WARNING: [Synth 8-3848] Net complex_ocal_rd_victim_sel in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:534] +WARNING: [Synth 8-3848] Net complex_victim_inc in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:592] +WARNING: [Synth 8-3848] Net rd_victim_sel in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:588] +WARNING: [Synth 8-3848] Net oclkdelay_center_calib_start in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:597] +WARNING: [Synth 8-3848] Net oclk_center_write_resume in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:615] +WARNING: [Synth 8-3848] Net oclkdelay_center_calib_done in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:616] +WARNING: [Synth 8-6014] Unused sequential element app_wdf_rdy_r_copy4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v:268] +WARNING: [Synth 8-6014] Unused sequential element int_next_pending_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_incr_cmd.v:191] +WARNING: [Synth 8-6014] Unused sequential element sel_first_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_incr_cmd.v:220] +WARNING: [Synth 8-6014] Unused sequential element int_next_pending_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wrap_cmd.v:221] +WARNING: [Synth 8-6014] Unused sequential element sel_first_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wrap_cmd.v:239] +WARNING: [Synth 8-3848] Net cmd_wr_bytes in module/entity mig_7series_v4_2_axi_mc_w_channel does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_w_channel.v:96] +WARNING: [Synth 8-6014] Unused sequential element rd_last_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_r_channel.v:216] +WARNING: [Synth 8-3848] Net error in module/entity mig_7series_v4_2_memc_ui_top_axi does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_memc_ui_top_axi.v:555] +WARNING: [Synth 8-3848] Net app_correct_en_i in module/entity mig_7series_v4_2_memc_ui_top_axi does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_memc_ui_top_axi.v:500] +WARNING: [Synth 8-3848] Net s_axi_ctrl_awvalid in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:754] +WARNING: [Synth 8-3848] Net s_axi_ctrl_awaddr in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:756] +WARNING: [Synth 8-3848] Net s_axi_ctrl_wvalid in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:758] +WARNING: [Synth 8-3848] Net s_axi_ctrl_wdata in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:760] +WARNING: [Synth 8-3848] Net s_axi_ctrl_bready in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:763] +WARNING: [Synth 8-3848] Net s_axi_ctrl_arvalid in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:766] +WARNING: [Synth 8-3848] Net s_axi_ctrl_araddr in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:768] +WARNING: [Synth 8-3848] Net s_axi_ctrl_rready in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:771] +WARNING: [Synth 8-3848] Net device_temp_i in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:784] +WARNING: [Synth 8-7129] Port mc_app_rd_last in module mig_7series_v4_2_axi_mc_r_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port axlen[7] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axlen[6] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axlen[5] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axlen[4] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[2] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[1] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[0] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[2] in module mig_7series_v4_2_axi_mc_incr_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[1] in module mig_7series_v4_2_axi_mc_incr_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[0] in module mig_7series_v4_2_axi_mc_incr_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axburst[0] in module mig_7series_v4_2_axi_mc_cmd_translator is either unconnected or has no load +WARNING: [Synth 8-7129] Port arlock[1] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arlock[0] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arcache[3] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arcache[2] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arcache[1] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arcache[0] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arprot[2] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arprot[1] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arprot[0] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port b_resp_rdy in module mig_7series_v4_2_axi_mc_b_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port cmd_wr_bytes in module mig_7series_v4_2_axi_mc_w_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awvalid in module mig_7series_v4_2_axi_mc_w_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port w_ignore_begin in module mig_7series_v4_2_axi_mc_w_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port w_ignore_end in module mig_7series_v4_2_axi_mc_w_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awlock[1] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awlock[0] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awcache[3] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awcache[2] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awcache[1] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awcache[0] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awprot[2] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awprot[1] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awprot[0] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port cmd_wr_bytes in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice__parameterized1 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice__parameterized1 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice__parameterized0 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice__parameterized0 is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_AWUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_WUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_ARUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port M_AXI_BUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port M_AXI_RUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[7] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[6] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[5] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[4] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[3] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[2] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[1] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[0] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[7] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[6] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[5] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[4] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[3] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[2] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[1] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[0] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[7] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[6] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[5] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[4] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[3] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[2] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[1] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[0] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port wr_data_addr[4] in module mig_7series_v4_2_ui_top is either unconnected or has no load +WARNING: [Synth 8-7129] Port accept in module mig_7series_v4_2_ui_top is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[11] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[10] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[9] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[8] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[7] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[6] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[5] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[4] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[3] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[2] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[1] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[0] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[99] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[98] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[97] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[96] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[95] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[94] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[93] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[16] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[15] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[14] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[12] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[11] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[10] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2909.984 ; gain = 669.223 ; free physical = 491527 ; free virtual = 627929 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2909.984 ; gain = 669.223 ; free physical = 491535 ; free virtual = 627937 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2909.984 ; gain = 669.223 ; free physical = 491535 ; free virtual = 627937 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.2 . Memory (MB): peak = 2909.984 ; gain = 0.000 ; free physical = 491540 ; free virtual = 627942 +INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3_ooc.xdc] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3_ooc.xdc] +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] +WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc:346] +WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc:353] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/arty_ddr3_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/arty_ddr3_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +INFO: [Timing 38-2] Deriving generated clocks +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.828 ; gain = 0.000 ; free physical = 491553 ; free virtual = 627970 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 70 instances were transformed. + IOBUFDS_INTERMDISABLE => IOBUFDS_INTERMDISABLE (IBUFDS_INTERMDISABLE_INT(x2), INV, OBUFTDS(x2)): 2 instances + IOBUF_INTERMDISABLE => IOBUF_INTERMDISABLE (IBUF_INTERMDISABLE, OBUFT): 16 instances + OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 1 instance + RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 51 instances + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3019.828 ; gain = 0.000 ; free physical = 491557 ; free virtual = 627975 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 3019.828 ; gain = 779.066 ; free physical = 491702 ; free virtual = 628120 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a100tcsg324-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 3027.832 ; gain = 787.070 ; free physical = 491702 ; free virtual = 628120 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_ck_n[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc, line 27). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_ck_p[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc, line 28). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 3027.832 ; gain = 787.070 ; free physical = 491707 ; free virtual = 628125 +--------------------------------------------------------------------------------- +INFO: [Synth 8-802] inferred FSM for state register 'xadc_supplied_temperature.tempmon_state_reg' in module 'mig_7series_v4_2_tempmon' +INFO: [Synth 8-802] inferred FSM for state register 'wl_state_r_reg' in module 'mig_7series_v4_2_ddr_phy_wrlvl' +INFO: [Synth 8-802] inferred FSM for state register 'fine_adj_state_r_reg' in module 'mig_7series_v4_2_ddr_phy_dqs_found_cal_hr' +INFO: [Synth 8-802] inferred FSM for state register 'cal1_state_r_reg' in module 'mig_7series_v4_2_ddr_phy_rdlvl' +INFO: [Synth 8-802] inferred FSM for state register 'tempmon_state_reg' in module 'mig_7series_v4_2_ddr_phy_tempmon' +INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'mig_7series_v4_2_axi_mc_r_channel' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + INIT_IDLE | 0001 | 000 + REQUEST_READ_TEMP | 1000 | 001 + WAIT_FOR_READ | 0100 | 010 + READ | 0010 | 011 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'xadc_supplied_temperature.tempmon_state_reg' using encoding 'one-hot' in module 'mig_7series_v4_2_tempmon' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + WL_IDLE | 01110 | 00000 + WL_INIT | 10010 | 00001 + WL_INIT_FINE_INC | 01100 | 00010 + WL_INIT_FINE_INC_WAIT1 | 01000 | 00011 + WL_INIT_FINE_INC_WAIT | 01001 | 00100 + WL_INIT_FINE_DEC | 11001 | 00101 + WL_INIT_FINE_DEC_WAIT1 | 10111 | 11001 + WL_INIT_FINE_DEC_WAIT | 11000 | 00110 + WL_WAIT | 00110 | 01000 + WL_EDGE_CHECK | 11011 | 01001 + WL_DQS_CNT | 10100 | 01011 + WL_FINE_DEC | 00000 | 01110 + WL_FINE_DEC_WAIT1 | 00001 | 11010 + WL_FINE_DEC_WAIT | 10001 | 01111 + WL_CORSE_DEC | 10110 | 10100 + WL_CORSE_DEC_WAIT | 11010 | 10101 + WL_CORSE_DEC_WAIT1 | 10101 | 10110 + WL_2RANK_DQS_CNT | 00010 | 01101 + WL_DQS_CHECK | 00011 | 01010 + WL_FINE_INC | 01101 | 00111 + WL_FINE_INC_WAIT | 10011 | 10111 + WL_2RANK_FINAL_TAP | 01111 | 11000 + WL_CORSE_INC | 01011 | 10000 + WL_CORSE_INC_WAIT_TMP | 10000 | 11011 + WL_CORSE_INC_WAIT | 01010 | 10001 + WL_CORSE_INC_WAIT1 | 00111 | 10010 + WL_CORSE_INC_WAIT2 | 00101 | 10011 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'wl_state_r_reg' using encoding 'sequential' in module 'mig_7series_v4_2_ddr_phy_wrlvl' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + FINE_ADJ_IDLE | 0000 | 0000 + RST_WAIT | 0001 | 0011 + FINE_ADJ_DONE | 0010 | 1111 + RST_POSTWAIT | 0011 | 0001 + RST_POSTWAIT1 | 0100 | 0010 + FINE_ADJ_INIT | 0101 | 0100 + FINE_INC | 0110 | 0101 + FINE_INC_WAIT | 0111 | 0110 + FINE_INC_PREWAIT | 1000 | 0111 + DETECT_PREWAIT | 1001 | 1000 + DETECT_DQSFOUND | 1010 | 1001 + FINE_DEC | 1011 | 1011 + FINE_DEC_WAIT | 1100 | 1100 + FINE_DEC_PREWAIT | 1101 | 1101 + FINAL_WAIT | 1110 | 1110 + PRECH_WAIT | 1111 | 1010 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'fine_adj_state_r_reg' using encoding 'sequential' in module 'mig_7series_v4_2_ddr_phy_dqs_found_cal_hr' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + CAL1_IDLE | 00000000000000000000000000010000000 | 000000 + CAL1_NEW_DQS_WAIT | 00000000000000000000010000000000000 | 000001 + CAL1_STORE_FIRST_WAIT | 00000000000000000010000000000000000 | 000010 + CAL1_PAT_DETECT | 00000000000000100000000000000000000 | 000011 + CAL1_DQ_IDEL_TAP_INC | 00000000000000000000000000000000100 | 000100 +CAL1_DQ_IDEL_TAP_INC_WAIT | 00000000000000000000000000000001000 | 000101 + CAL1_MPR_PAT_DETECT | 00000000000000000000000010000000000 | 011111 + CAL1_VALID_WAIT | 10000000000000000000000000000000000 | 011110 + CAL1_DETECT_EDGE | 00000000000001000000000000000000000 | 001000 + CAL1_CALC_IDEL | 00000100000000000000000000000000000 | 001011 + CAL1_CENTER_WAIT | 00000000000000000000000000000000001 | 100010 + CAL1_IDEL_DEC_CPT | 00000000000000000000000000000000010 | 001100 + CAL1_DQ_IDEL_TAP_DEC | 00000000000000000001000000000000000 | 000110 +CAL1_DQ_IDEL_TAP_DEC_WAIT | 00100000000000000000000000000000000 | 000111 + CAL1_NEXT_DQS | 00000000000000000000000000000010000 | 001110 + CAL1_REGL_LOAD | 00000000000000000000000000001000000 | 011011 + CAL1_DONE | 00000000000000000000000000000100000 | 001111 + CAL1_NEW_DQS_PREWAIT | 00000000000000000000000000100000000 | 100000 + CAL1_MPR_NEW_DQS_WAIT | 00000000000000000000000001000000000 | 011101 + CAL1_IDEL_DEC_CPT_WAIT | 00000000000000000000100000000000000 | 001101 + CAL1_RD_STOP_FOR_PI_INC | 00000000000000000000000100000000000 | 100001 + CAL1_IDEL_INC_CPT | 00000000000000000000001000000000000 | 001001 + CAL1_IDEL_INC_CPT_WAIT | 00010000000000000000000000000000000 | 001010 + CAL1_RDLVL_ERR | 00000000000010000000000000000000000 | 011100 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'cal1_state_r_reg' using encoding 'one-hot' in module 'mig_7series_v4_2_ddr_phy_rdlvl' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 00000000001 | 00000000001 + INIT | 00000000010 | 00000000010 + NEUTRAL | 00001000000 | 00001000000 + ONE_DEC | 00010000000 | 00010000000 + TWO_DEC | 00100000000 | 00100000000 + THREE_DEC | 01000000000 | 01000000000 + FOUR_DEC | 10000000000 | 10000000000 + ONE_INC | 00000100000 | 00000100000 + TWO_INC | 00000010000 | 00000010000 + THREE_INC | 00000001000 | 00000001000 + FOUR_INC | 00000000100 | 00000000100 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'tempmon_state_reg' in module 'mig_7series_v4_2_ddr_phy_tempmon' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + ZERO | 11 | 10 + ONE | 01 | 11 + TWO | 00 | 01 + iSTATE | 10 | 00 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'mig_7series_v4_2_axi_mc_r_channel' +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 3027.832 ; gain = 787.070 ; free physical = 491753 ; free virtual = 628175 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 4 Input 32 Bit Adders := 2 + 3 Input 32 Bit Adders := 1 + 2 Input 28 Bit Adders := 2 + 2 Input 13 Bit Adders := 1 + 2 Input 12 Bit Adders := 15 + 2 Input 11 Bit Adders := 1 + 2 Input 10 Bit Adders := 6 + 2 Input 9 Bit Adders := 4 + 2 Input 8 Bit Adders := 8 + 3 Input 7 Bit Adders := 2 + 2 Input 7 Bit Adders := 1 + 2 Input 6 Bit Adders := 30 + 3 Input 6 Bit Adders := 3 + 2 Input 5 Bit Adders := 37 + 2 Input 4 Bit Adders := 34 + 2 Input 3 Bit Adders := 20 + 3 Input 3 Bit Adders := 1 + 2 Input 2 Bit Adders := 51 + 3 Input 2 Bit Adders := 3 + 4 Input 2 Bit Adders := 5 + 5 Input 2 Bit Adders := 1 + 8 Input 2 Bit Adders := 1 + 2 Input 1 Bit Adders := 5 + 3 Input 1 Bit Adders := 1 + 4 Input 1 Bit Adders := 1 + 5 Input 1 Bit Adders := 1 + 6 Input 1 Bit Adders := 1 + 7 Input 1 Bit Adders := 1 + 8 Input 1 Bit Adders := 1 + 9 Input 1 Bit Adders := 1 ++---XORs : + 2 Input 1 Bit XORs := 1 ++---Registers : + 144 Bit Registers := 1 + 128 Bit Registers := 5 + 88 Bit Registers := 1 + 80 Bit Registers := 3 + 56 Bit Registers := 1 + 32 Bit Registers := 3 + 30 Bit Registers := 1 + 28 Bit Registers := 6 + 16 Bit Registers := 13 + 15 Bit Registers := 4 + 14 Bit Registers := 6 + 13 Bit Registers := 1 + 12 Bit Registers := 33 + 11 Bit Registers := 1 + 10 Bit Registers := 4 + 9 Bit Registers := 12 + 8 Bit Registers := 15 + 7 Bit Registers := 5 + 6 Bit Registers := 59 + 5 Bit Registers := 46 + 4 Bit Registers := 82 + 3 Bit Registers := 47 + 2 Bit Registers := 66 + 1 Bit Registers := 1542 ++---Muxes : + 2 Input 128 Bit Muxes := 10 + 4 Input 128 Bit Muxes := 1 + 2 Input 127 Bit Muxes := 1 + 2 Input 80 Bit Muxes := 6 + 2 Input 56 Bit Muxes := 1 + 24 Input 35 Bit Muxes := 1 + 2 Input 35 Bit Muxes := 22 + 2 Input 32 Bit Muxes := 1 + 2 Input 30 Bit Muxes := 12 + 4 Input 30 Bit Muxes := 4 + 2 Input 28 Bit Muxes := 11 + 2 Input 21 Bit Muxes := 8 + 2 Input 16 Bit Muxes := 8 + 3 Input 16 Bit Muxes := 1 + 3 Input 14 Bit Muxes := 1 + 2 Input 14 Bit Muxes := 8 + 4 Input 14 Bit Muxes := 1 + 2 Input 12 Bit Muxes := 5 + 12 Input 11 Bit Muxes := 1 + 2 Input 11 Bit Muxes := 1 + 2 Input 10 Bit Muxes := 7 + 4 Input 9 Bit Muxes := 6 + 2 Input 9 Bit Muxes := 18 + 2 Input 8 Bit Muxes := 61 + 5 Input 8 Bit Muxes := 1 + 2 Input 7 Bit Muxes := 64 + 3 Input 7 Bit Muxes := 1 + 4 Input 7 Bit Muxes := 1 + 5 Input 7 Bit Muxes := 2 + 2 Input 6 Bit Muxes := 81 + 4 Input 6 Bit Muxes := 8 + 27 Input 6 Bit Muxes := 4 + 5 Input 6 Bit Muxes := 2 + 16 Input 6 Bit Muxes := 1 + 24 Input 6 Bit Muxes := 5 + 3 Input 6 Bit Muxes := 2 + 2 Input 5 Bit Muxes := 35 + 8 Input 5 Bit Muxes := 2 + 27 Input 5 Bit Muxes := 1 + 58 Input 5 Bit Muxes := 1 + 24 Input 5 Bit Muxes := 1 + 4 Input 5 Bit Muxes := 2 + 3 Input 5 Bit Muxes := 4 + 2 Input 4 Bit Muxes := 67 + 32 Input 4 Bit Muxes := 1 + 8 Input 4 Bit Muxes := 1 + 7 Input 4 Bit Muxes := 1 + 2 Input 3 Bit Muxes := 69 + 27 Input 3 Bit Muxes := 6 + 3 Input 3 Bit Muxes := 1 + 4 Input 3 Bit Muxes := 3 + 8 Input 3 Bit Muxes := 1 + 2 Input 2 Bit Muxes := 101 + 4 Input 2 Bit Muxes := 7 + 3 Input 2 Bit Muxes := 9 + 8 Input 2 Bit Muxes := 4 + 27 Input 2 Bit Muxes := 1 + 24 Input 2 Bit Muxes := 2 + 5 Input 2 Bit Muxes := 1 + 10 Input 2 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 491 + 3 Input 1 Bit Muxes := 12 + 8 Input 1 Bit Muxes := 4 + 4 Input 1 Bit Muxes := 204 + 27 Input 1 Bit Muxes := 27 + 5 Input 1 Bit Muxes := 1 + 16 Input 1 Bit Muxes := 21 + 24 Input 1 Bit Muxes := 30 + 10 Input 1 Bit Muxes := 17 + 12 Input 1 Bit Muxes := 4 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 240 (col length:80) +BRAMs: 270 (col length: RAMB18 80 RAMB36 40) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +WARNING: [Synth 8-7080] Parallel synthesis criteria is not met +WARNING: [Synth 8-3936] Found unconnected internal register 'byte_sel_data_map_reg' and it is trimmed from '88' to '4' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:731] +WARNING: [Synth 8-3936] Found unconnected internal register 'oclkdelay_start_dly_r_reg' and it is trimmed from '15' to '14' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1232] +WARNING: [Synth 8-3936] Found unconnected internal register 'wrcal_start_dly_r_reg' and it is trimmed from '15' to '14' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1230] +WARNING: [Synth 8-3332] Sequential element (FSM_onehot_cal1_state_r_reg[33]) is unused and will be removed from module mig_7series_v4_2_ddr_phy_rdlvl. +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:15 ; elapsed = 00:01:15 . Memory (MB): peak = 3300.871 ; gain = 1060.109 ; free physical = 492131 ; free virtual = 628560 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +ROM: Preliminary Mapping Report ++------------------------------+------------+---------------+----------------+ +|Module Name | RTL Object | Depth x Width | Implemented As | ++------------------------------+------------+---------------+----------------+ +|mig_7series_v4_2_ddr_prbs_gen | mem_out | 256x18 | LUT | +|mig_7series_v4_2_ddr_prbs_gen | mem_out | 256x18 | LUT | ++------------------------------+------------+---------------+----------------+ + + +Distributed RAM: Preliminary Mapping Report (see note below) ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ +|arty_ddr3 | of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ + +Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +WARNING: [Synth 8-3321] set_false_path : Empty through list for constraint at line 359 of /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc:359] +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:19 ; elapsed = 00:01:19 . Memory (MB): peak = 3300.871 ; gain = 1060.109 ; free physical = 491922 ; free virtual = 628371 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:01:19 ; elapsed = 00:01:19 . Memory (MB): peak = 3300.871 ; gain = 1060.109 ; free physical = 491872 ; free virtual = 628347 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Distributed RAM: Final Mapping Report ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ +|arty_ddr3 | of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:01:21 ; elapsed = 00:01:22 . Memory (MB): peak = 3300.871 ; gain = 1060.109 ; free physical = 491502 ; free virtual = 628069 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:01:24 ; elapsed = 00:01:25 . Memory (MB): peak = 3300.871 ; gain = 1060.109 ; free physical = 491390 ; free virtual = 628027 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:01:24 ; elapsed = 00:01:25 . Memory (MB): peak = 3300.871 ; gain = 1060.109 ; free physical = 491389 ; free virtual = 628027 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:25 ; elapsed = 00:01:25 . Memory (MB): peak = 3300.871 ; gain = 1060.109 ; free physical = 491437 ; free virtual = 628074 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:01:25 ; elapsed = 00:01:25 . Memory (MB): peak = 3300.871 ; gain = 1060.109 ; free physical = 491436 ; free virtual = 628073 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:01:25 ; elapsed = 00:01:25 . Memory (MB): peak = 3300.871 ; gain = 1060.109 ; free physical = 491436 ; free virtual = 628073 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:01:25 ; elapsed = 00:01:25 . Memory (MB): peak = 3300.871 ; gain = 1060.109 ; free physical = 491435 ; free virtual = 628073 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Static Shift Register Report: ++------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ +|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | ++------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/rclk_delay_reg[11] | 12 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/rst_r4_reg | 4 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/phy_ctl_ready_r5_reg | 5 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay/delay_done_r4_reg | 4 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/init_dqsfound_done_r5_reg | 3 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrlvl_rank_done_r7_reg | 6 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prech_done_reg | 17 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_start_dly_r_reg[5] | 6 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg[14] | 15 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_pat_match_div4.pat_data_match_valid_r_reg | 3 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] | 3 | 4 | NO | NO | YES | 4 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/wrcal_pat_resume_reg | 3 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/reset_if_r9_reg | 9 | 1 | NO | NO | YES | 1 | 0 | ++------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ + + +Dynamic Shift Register Report: ++------------+----------------+--------+------------+--------+---------+--------+--------+--------+ +|Module Name | RTL Name | Length | Data Width | SRL16E | SRLC32E | Mux F7 | Mux F8 | Mux F9 | ++------------+----------------+--------+------------+--------+---------+--------+--------+--------+ +|dsrl | memory_reg[7] | 4 | 4 | 4 | 0 | 0 | 0 | 0 | +|dsrl__1 | memory_reg[31] | 129 | 129 | 0 | 129 | 0 | 0 | 0 | +|dsrl__2 | memory_reg[29] | 7 | 7 | 0 | 7 | 0 | 0 | 0 | ++------------+----------------+--------+------------+--------+---------+--------+--------+--------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+----------------------+------+ +| |Cell |Count | ++------+----------------------+------+ +|1 |BUFG | 3| +|2 |BUFH | 1| +|3 |BUFIO | 1| +|4 |CARRY4 | 124| +|5 |IDELAYCTRL | 1| +|6 |IDELAYE2 | 16| +|7 |IN_FIFO | 2| +|8 |ISERDESE2 | 16| +|9 |LUT1 | 375| +|10 |LUT2 | 438| +|11 |LUT3 | 1023| +|12 |LUT4 | 905| +|13 |LUT5 | 1361| +|14 |LUT6 | 1262| +|15 |MMCME2_ADV | 1| +|16 |MUXF7 | 28| +|17 |ODDR | 5| +|18 |OSERDESE2 | 43| +|21 |OUT_FIFO | 4| +|23 |PHASER_IN_PHY | 2| +|24 |PHASER_OUT_PHY | 4| +|26 |PHASER_REF | 1| +|27 |PHY_CONTROL | 1| +|28 |PLLE2_ADV | 1| +|29 |RAM32M | 112| +|30 |RAM32X1D | 2| +|31 |SRL16E | 20| +|32 |SRLC32E | 134| +|33 |XADC | 1| +|34 |FDCE | 2| +|35 |FDPE | 73| +|36 |FDRE | 3995| +|37 |FDSE | 123| +|38 |IOBUFDS_INTERMDISABLE | 2| +|39 |IOBUF_INTERMDISABLE | 16| +|40 |OBUF | 24| +|41 |OBUFDS | 1| +|42 |OBUFT | 2| ++------+----------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:01:25 ; elapsed = 00:01:25 . Memory (MB): peak = 3300.871 ; gain = 1060.109 ; free physical = 491435 ; free virtual = 628072 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 6 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:01:21 ; elapsed = 00:01:23 . Memory (MB): peak = 3300.871 ; gain = 950.266 ; free physical = 491411 ; free virtual = 628048 +Synthesis Optimization Complete : Time (s): cpu = 00:01:25 ; elapsed = 00:01:26 . Memory (MB): peak = 3300.879 ; gain = 1060.109 ; free physical = 491410 ; free virtual = 628047 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.14 . Memory (MB): peak = 3300.879 ; gain = 0.000 ; free physical = 491722 ; free virtual = 628364 +INFO: [Netlist 29-17] Analyzing 325 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3_ooc.xdc] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3_ooc.xdc] +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] +INFO: [Opt 31-138] Pushed 2 inverter(s) to 16 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3356.898 ; gain = 0.000 ; free physical = 491719 ; free virtual = 628364 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 133 instances were transformed. + IOBUFDS_INTERMDISABLE => IOBUFDS_INTERMDISABLE (IBUFDS_INTERMDISABLE_INT(x2), INV, OBUFTDS(x2)): 2 instances + IOBUF_INTERMDISABLE => IOBUF_INTERMDISABLE (IBUF_INTERMDISABLE, OBUFT): 16 instances + OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 1 instance + RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 112 instances + RAM32X1D => RAM32X1D (RAMD32(x2)): 2 instances + +Synth Design complete | Checksum: cc6d6f52 +INFO: [Common 17-83] Releasing license: Synthesis +249 Infos, 303 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:01:30 ; elapsed = 00:01:28 . Memory (MB): peak = 3356.898 ; gain = 1120.105 ; free physical = 491719 ; free virtual = 628364 +INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 3059.030; main = 2758.349; forked = 445.011 +INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 4342.461; main = 3356.902; forked = 1041.586 +INFO: [Coretcl 2-1174] Renamed 88 cell refs. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-2] Deriving generated clocks +INFO: [Timing 38-480] Writing timing data to binary archive. +Write ShapeDB Complete: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3404.914 ; gain = 0.000 ; free physical = 491865 ; free virtual = 628527 +Wrote PlaceDB: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3404.914 ; gain = 0.000 ; free physical = 491865 ; free virtual = 628527 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3404.914 ; gain = 0.000 ; free physical = 491865 ; free virtual = 628527 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3404.914 ; gain = 0.000 ; free physical = 491869 ; free virtual = 628532 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3404.914 ; gain = 0.000 ; free physical = 491869 ; free virtual = 628532 +Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3404.914 ; gain = 0.000 ; free physical = 491869 ; free virtual = 628532 +Write Physdb Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3404.914 ; gain = 0.000 ; free physical = 491869 ; free virtual = 628532 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3.dcp' has been generated. +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data0/tools/Xilinx/Vivado/2024.1/data/ip'. +WARNING: [Vivado 12-13650] The IP file '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc.xci' has been moved from its original location, as a result the outputs for this IP will now be generated in '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc'. Alternatively a copy of the IP can be imported into the project using one of the 'import_ip' or 'import_files' commands. +Command: synth_design -top toy_axi_cdc -part xc7a100tcsg324-1 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 3404.914 ; gain = 0.000 ; free physical = 491808 ; free virtual = 628479 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'toy_axi_cdc' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/synth/toy_axi_cdc.v:53] +INFO: [Synth 8-6157] synthesizing module 'axi_clock_converter_v2_1_30_axi_clock_converter' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/hdl/axi_clock_converter_v2_1_vl_rfs.v:650] +INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_single' [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:152] +INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_single' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:152] +INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_async_rst' [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1175] +INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_async_rst' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1175] +INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_single__parameterized1' [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:152] +INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_single__parameterized1' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:152] +INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray' [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:283] +INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:283] +INFO: [Synth 8-6155] done synthesizing module 'axi_clock_converter_v2_1_30_axi_clock_converter' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/hdl/axi_clock_converter_v2_1_vl_rfs.v:650] +INFO: [Synth 8-6155] done synthesizing module 'toy_axi_cdc' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/synth/toy_axi_cdc.v:53] +WARNING: [Synth 8-7129] Port ALMOST_FULL_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ALMOST_EMPTY_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_ACK_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port VALID_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port OVERFLOW_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port UNDERFLOW_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DATA_COUNT_I[4] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DATA_COUNT_I[3] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DATA_COUNT_I[2] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DATA_COUNT_I[1] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DATA_COUNT_I[0] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[4] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[3] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[2] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[1] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[0] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[4] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[3] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[2] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[1] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[0] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port SBITERR_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DBITERR_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_RST in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port SAFETY_CKT_WR_RST in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[3] in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[2] in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[1] in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[0] in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module wr_bin_cntr is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_EN_INTO_LOGIC in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_RST_INTO_LOGIC in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_EN in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST_FULL_FF in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_RST_BUSY in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port EMPTY in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RAM_RD_EN in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port ALMOST_EMPTY in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[3] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[2] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[1] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[0] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[3] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[2] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[1] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[0] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_NEGATE[3] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_NEGATE[2] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_NEGATE[1] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_NEGATE[0] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module rd_fwft is either unconnected or has no load +WARNING: [Synth 8-7129] Port SAFETY_CKT_RD_RST in module rd_fwft is either unconnected or has no load +WARNING: [Synth 8-7129] Port RAM_ALMOST_EMPTY in module rd_fwft is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port SAFETY_CKT_RD_RST in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_PNTR_PLUS2[3] in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_PNTR_PLUS2[2] in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_PNTR_PLUS2[1] in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_PNTR_PLUS2[0] in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module rd_bin_cntr is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_EN_INTO_LOGIC in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_RST_INTO_LOGIC in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_RST_BUSY in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RAM_WR_EN in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RST_FULL_FF in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port ALMOST_FULL_FB in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port FULL in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS1_RD[3] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS1_RD[2] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS1_RD[1] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS1_RD[0] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[3] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[2] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[1] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[0] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_ASSERT[3] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_ASSERT[2] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_ASSERT[1] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_ASSERT[0] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_NEGATE[3] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_NEGATE[2] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_NEGATE[1] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_NEGATE[0] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_RST in module clk_x_pntrs is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_RST in module clk_x_pntrs is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module dmem__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FAB_REGOUT_EN in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port SFT_RST in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port SAFETY_CKT_RD_RST in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port SLEEP in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port INJECTDBITERR in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port INJECTSBITERR in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port CLK in module input_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port INT_CLK in module input_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[3] in module input_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[2] in module input_blk__parameterized2 is either unconnected or has no load +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 3416.914 ; gain = 12.000 ; free physical = 491891 ; free virtual = 628560 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 3416.914 ; gain = 12.000 ; free physical = 491891 ; free virtual = 628560 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 3416.914 ; gain = 12.000 ; free physical = 491891 ; free virtual = 628560 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3416.914 ; gain = 0.000 ; free physical = 491893 ; free virtual = 628563 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_ooc.xdc] for cell 'inst' +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_ooc.xdc] for cell 'inst' +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/toy_axi_cdc_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/toy_axi_cdc_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/toy_axi_cdc_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/toy_axi_cdc_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +INFO: [Project 1-1714] 33 XPM XDC files have been applied to the design. +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3462.727 ; gain = 0.000 ; free physical = 491923 ; free virtual = 628592 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3462.727 ; gain = 0.000 ; free physical = 491923 ; free virtual = 628592 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 491974 ; free virtual = 628643 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a100tcsg324-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 491974 ; free virtual = 628643 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property KEEP_HIERARCHY = SOFT for inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.cdc_wr_rst_busy_ic_3.xpm_cdc_single_inst3 . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.cdc_wr_rst_busy_ic_1.xpm_cdc_single_inst1 . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.cdc_wr_rst_busy_ic_2.xpm_cdc_single_inst2 . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 491979 ; free virtual = 628648 +--------------------------------------------------------------------------------- +INFO: [Synth 8-802] inferred FSM for state register 'gpregsm1.curr_fwft_state_reg' in module 'rd_fwft' +INFO: [Synth 8-6159] Found Keep on FSM register 'gpregsm1.curr_fwft_state_reg' in module 'rd_fwft', re-encoding will not be performed +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + invalid | 00 | 00 + stage1_valid | 10 | 10 + both_stages_valid | 11 | 11 + stage2_valid | 01 | 01 +--------------------------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 491969 ; free virtual = 628639 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 10 ++---XORs : + 2 Input 4 Bit XORs := 10 + 2 Input 1 Bit XORs := 110 ++---Registers : + 145 Bit Registers := 2 + 135 Bit Registers := 2 + 61 Bit Registers := 4 + 6 Bit Registers := 2 + 5 Bit Registers := 10 + 4 Bit Registers := 83 + 2 Bit Registers := 15 + 1 Bit Registers := 88 ++---Muxes : + 4 Input 2 Bit Muxes := 5 + 2 Input 2 Bit Muxes := 50 + 5 Input 2 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 5 + 2 Input 1 Bit Muxes := 15 + 4 Input 1 Bit Muxes := 10 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 240 (col length:80) +BRAMs: 270 (col length: RAMB18 80 RAMB36 40) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +WARNING: [Synth 8-7080] Parallel synthesis criteria is not met +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 491967 ; free virtual = 628638 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Distributed RAM: Preliminary Mapping Report (see note below) ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 61 | RAM32M x 11 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 145 | RAM32M x 25 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 6 | RAM32M x 1 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 61 | RAM32M x 11 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 135 | RAM32M x 23 | ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ + +Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 492037 ; free virtual = 628707 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 492041 ; free virtual = 628712 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Distributed RAM: Final Mapping Report ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 61 | RAM32M x 11 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 145 | RAM32M x 25 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 6 | RAM32M x 1 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 61 | RAM32M x 11 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 135 | RAM32M x 23 | ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 492048 ; free virtual = 628719 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 492084 ; free virtual = 628755 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 492084 ; free virtual = 628755 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 492084 ; free virtual = 628755 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 492084 ; free virtual = 628755 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 492084 ; free virtual = 628755 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 492084 ; free virtual = 628755 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+---------+------+ +| |Cell |Count | ++------+---------+------+ +|1 |LUT1 | 76| +|2 |LUT2 | 66| +|3 |LUT3 | 35| +|4 |LUT4 | 65| +|5 |LUT5 | 10| +|6 |LUT6 | 25| +|7 |RAM32M | 68| +|8 |RAM32X1D | 3| +|9 |FDCE | 130| +|10 |FDPE | 115| +|11 |FDRE | 1081| ++------+---------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 492084 ; free virtual = 628755 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 206 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 3462.727 ; gain = 12.000 ; free physical = 492086 ; free virtual = 628757 +Synthesis Optimization Complete : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3462.734 ; gain = 57.812 ; free physical = 492086 ; free virtual = 628757 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3462.734 ; gain = 0.000 ; free physical = 492379 ; free virtual = 629050 +INFO: [Netlist 29-17] Analyzing 71 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_ooc.xdc] for cell 'inst' +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_ooc.xdc] for cell 'inst' +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc] for cell 'inst' +INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:16] +WARNING: [Vivado_Tcl 4-2057] Waiver ID 'LUTAR-1' object list specifies likely unusable hierarchical instance 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:30] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:35] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:35] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:35] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:39] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:39] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:42] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:42] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:45] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:45] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:45] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:49] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:49] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:52] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:52] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:52] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:56] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:56] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:56] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:60] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:60] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:63] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:63] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:66] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:66] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:66] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:70] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:70] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc] for cell 'inst' +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3462.734 ; gain = 0.000 ; free physical = 492413 ; free virtual = 629084 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 71 instances were transformed. + RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 68 instances + RAM32X1D => RAM32X1D (RAMD32(x2)): 3 instances + +Synth Design complete | Checksum: ed94db3a +INFO: [Common 17-83] Releasing license: Synthesis +33 Infos, 130 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 3462.734 ; gain = 57.820 ; free physical = 492415 ; free virtual = 629086 +INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 3101.122; main = 2799.306; forked = 445.645 +INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 4504.316; main = 3462.730; forked = 1041.586 +INFO: [Coretcl 2-1174] Renamed 101 cell refs. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-480] Writing timing data to binary archive. +Write ShapeDB Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00 . Memory (MB): peak = 3470.730 ; gain = 0.000 ; free physical = 492418 ; free virtual = 629089 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc.dcp' has been generated. +INFO: [Vivado 12-3441] generate_netlist_ip - operation complete +synth_ip: Time (s): cpu = 00:02:04 ; elapsed = 00:02:00 . Memory (MB): peak = 3470.730 ; gain = 1247.883 ; free physical = 492416 ; free virtual = 629088 +INFO: [Common 17-2834] synth_ip peak Physical Memory [PSS] (MB): overall = 3101.122; main = 2799.306; forked = 445.645 +INFO: [Common 17-2834] synth_ip peak Virtual Memory [VSS] (MB): overall = 4504.316; main = 3470.734; forked = 1041.586 +# phase SYNTH_BOARD +BOARD_PHASE SYNTH_BOARD +# if {$flash} {read_verilog -sv $root/build/flash-boot/ToyLinuxChip.sv} else { +# read_verilog -sv $root/build/serial-bound/ToyLinuxChip.sv +# } +# read_verilog -sv $root/build/serial-bound/FpgaMemories.sv +# foreach f [glob $root/board/*.sv] {read_verilog -sv $f} +# set_property verilog_define {SYNTHESIS BUCKYBALL_DISABLE_DPI} [current_fileset] +# read_xdc $root/board/arty_a7.xdc +# read_xdc $root/board/flash_boot.xdc +# synth_design -top toy_a7_top -part xc7a100tcsg324-1 -flatten_hierarchy rebuilt -directive AreaOptimized_high -resource_sharing on -generic FLASH_BOOT=$flash +Command: synth_design -top toy_a7_top -part xc7a100tcsg324-1 -flatten_hierarchy rebuilt -directive AreaOptimized_high -resource_sharing on -generic FLASH_BOOT=0 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 3470.852 ; gain = 0.000 ; free physical = 492075 ; free virtual = 628755 +--------------------------------------------------------------------------------- +WARNING: [Synth 8-6901] identifier 'reset' is used before its declaration [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:30] +INFO: [Synth 8-6157] synthesizing module 'toy_a7_top' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:1] + Parameter FLASH_BOOT bound to: 0 - type: integer +INFO: [Synth 8-6157] synthesizing module 'IBUF' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:73643] +INFO: [Synth 8-6155] done synthesizing module 'IBUF' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:73643] +INFO: [Synth 8-6157] synthesizing module 'MMCME2_BASE' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82508] + Parameter CLKFBOUT_MULT_F bound to: 10.000000 - type: double + Parameter CLKIN1_PERIOD bound to: 10.000000 - type: double + Parameter CLKOUT0_DIVIDE_F bound to: 40.000000 - type: double + Parameter CLKOUT1_DIVIDE bound to: 6 - type: integer + Parameter CLKOUT2_DIVIDE bound to: 5 - type: integer + Parameter DIVCLK_DIVIDE bound to: 1 - type: integer +INFO: [Synth 8-6155] done synthesizing module 'MMCME2_BASE' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82508] +WARNING: [Synth 8-7071] port 'CLKFBOUTB' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT0B' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT1B' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT2B' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT3' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT3B' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT4' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT5' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT6' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7023] instance 'clock_mmcm' of module 'MMCME2_BASE' has 18 connections declared, but only 9 given [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:13] +INFO: [Synth 8-6157] synthesizing module 'BUFG' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951] +INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951] +INFO: [Synth 8-6157] synthesizing module 'toy_a7_platform' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_platform.sv:2] + Parameter FLASH_BOOT bound to: 0 - type: integer +INFO: [Synth 8-6157] synthesizing module 'uart_rx' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_rx.sv:3] + Parameter DIVISOR bound to: 25 - type: integer +INFO: [Synth 8-6155] done synthesizing module 'uart_rx' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_rx.sv:3] +INFO: [Synth 8-6157] synthesizing module 'uart_tx' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_tx.sv:1] + Parameter DIVISOR bound to: 25 - type: integer +INFO: [Synth 8-6155] done synthesizing module 'uart_tx' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_tx.sv:1] +INFO: [Synth 8-6157] synthesizing module 'ddr_uart_loader' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:5] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:99] +INFO: [Synth 8-6155] done synthesizing module 'ddr_uart_loader' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:5] +INFO: [Synth 8-6157] synthesizing module 'ToyLinuxChip' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:103817] +INFO: [Synth 8-6157] synthesizing module 'ToyLinuxSystem' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:102569] +INFO: [Synth 8-6157] synthesizing module 'IntSyncAsyncCrossingSink_n1x1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:61] +INFO: [Synth 8-6157] synthesizing module 'SynchronizerShiftReg_w1_d3' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:48] +INFO: [Synth 8-6157] synthesizing module 'NonSyncResetSynchronizerPrimitiveShiftReg_d3' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:31] +INFO: [Synth 8-6155] done synthesizing module 'NonSyncResetSynchronizerPrimitiveShiftReg_d3' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:31] +INFO: [Synth 8-6155] done synthesizing module 'SynchronizerShiftReg_w1_d3' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:48] +INFO: [Synth 8-6155] done synthesizing module 'IntSyncAsyncCrossingSink_n1x1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:61] +INFO: [Synth 8-6157] synthesizing module 'IntSyncCrossingSource_n1x1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:103] +INFO: [Synth 8-6157] synthesizing module 'AsyncResetRegVec_w1_i0' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:74] +INFO: [Synth 8-6155] done synthesizing module 'AsyncResetRegVec_w1_i0' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:74] +INFO: [Synth 8-6155] done synthesizing module 'IntSyncCrossingSource_n1x1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:103] +INFO: [Synth 8-6157] synthesizing module 'SystemBus' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:9400] +INFO: [Synth 8-6157] synthesizing module 'FixedClockBroadcast_3' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:118] +INFO: [Synth 8-6155] done synthesizing module 'FixedClockBroadcast_3' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:118] +INFO: [Synth 8-6157] synthesizing module 'TLXbar_sbus_i2_o3_a32d128s3k1z4c' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:2434] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:3011] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:139] +INFO: [Synth 8-6157] synthesizing module 'plusarg_reader' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104301] + Parameter FORMAT bound to: tilelink_timeout=%d - type: string + Parameter WIDTH bound to: 32 - type: integer + Parameter DEFAULT bound to: 32'b00000000000000000000000000000000 +INFO: [Synth 8-6155] done synthesizing module 'plusarg_reader' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104301] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:139] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:3033] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:987] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:987] +INFO: [Synth 8-6155] done synthesizing module 'TLXbar_sbus_i2_o3_a32d128s3k1z4c' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:2434] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_sbus_to_bus_named_cbus' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4386] +INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget16' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4218] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4310] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_2' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:3195] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_2' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:3195] +INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a28d128s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4151] +INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a28d128s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4151] +INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget16' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4218] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_sbus_to_bus_named_cbus' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4386] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8623] +INFO: [Synth 8-6157] synthesizing module 'AXI4Buffer' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4891] +INFO: [Synth 8-6157] synthesizing module 'Queue2_AXI4BundleAW' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4497] +INFO: [Synth 8-6157] synthesizing module 'ram_2x58' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4478] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x58' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4478] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_AXI4BundleAW' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4497] +INFO: [Synth 8-6157] synthesizing module 'Queue2_AXI4BundleW' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4600] +INFO: [Synth 8-6157] synthesizing module 'ram_2x73' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4581] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x73' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4581] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_AXI4BundleW' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4600] +INFO: [Synth 8-6157] synthesizing module 'Queue2_AXI4BundleB' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4676] +INFO: [Synth 8-6157] synthesizing module 'ram_2x4' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4657] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x4' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4657] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_AXI4BundleB' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4676] +INFO: [Synth 8-6157] synthesizing module 'Queue2_AXI4BundleAR' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4729] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_AXI4BundleAR' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4729] +INFO: [Synth 8-6157] synthesizing module 'Queue2_AXI4BundleR' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4832] +INFO: [Synth 8-6157] synthesizing module 'ram_2x69' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4813] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x69' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4813] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_AXI4BundleR' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4832] +INFO: [Synth 8-6155] done synthesizing module 'AXI4Buffer' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4891] +INFO: [Synth 8-6157] synthesizing module 'AXI4UserYanker' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5178] +INFO: [Synth 8-6157] synthesizing module 'Queue2_BundleMap' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5086] +INFO: [Synth 8-6157] synthesizing module 'ram_2x8' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5067] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x8' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5067] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_BundleMap' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5086] +INFO: [Synth 8-6157] synthesizing module 'Queue1_BundleMap' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5143] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_BundleMap' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5143] +INFO: [Synth 8-6155] done synthesizing module 'AXI4UserYanker' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5178] +INFO: [Synth 8-6157] synthesizing module 'AXI4Deinterleaver' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5631] +INFO: [Synth 8-6157] synthesizing module 'Queue8_AXI4BundleR' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5559] +INFO: [Synth 8-6157] synthesizing module 'ram_8x77' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5540] +INFO: [Synth 8-6155] done synthesizing module 'ram_8x77' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5540] +INFO: [Synth 8-6155] done synthesizing module 'Queue8_AXI4BundleR' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5559] +INFO: [Synth 8-6155] done synthesizing module 'AXI4Deinterleaver' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5631] +INFO: [Synth 8-6157] synthesizing module 'AXI4IdIndexer' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:6073] +INFO: [Synth 8-6155] done synthesizing module 'AXI4IdIndexer' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:6073] +INFO: [Synth 8-6157] synthesizing module 'TLToAXI4' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7148] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7423] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_3' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:6219] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_3' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:6219] +INFO: [Synth 8-6157] synthesizing module 'Queue1_AXI4BundleW' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7048] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_AXI4BundleW' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7048] +INFO: [Synth 8-6157] synthesizing module 'Queue1_AXI4BundleARW' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7082] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_AXI4BundleARW' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7082] +INFO: [Synth 8-6155] done synthesizing module 'TLToAXI4' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7148] +INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget16_2' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8463] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8551] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_4' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7529] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_4' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7529] +INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a31d128s3k1z3u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8396] +INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a31d128s3k1z3u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8396] +INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget16_2' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8463] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8623] +INFO: [Synth 8-6155] done synthesizing module 'SystemBus' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:9400] +INFO: [Synth 8-6157] synthesizing module 'PeripheryBus_cbus' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19330] +INFO: [Synth 8-6157] synthesizing module 'FixedClockBroadcast_4' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10050] +INFO: [Synth 8-6155] done synthesizing module 'FixedClockBroadcast_4' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10050] +INFO: [Synth 8-6157] synthesizing module 'TLXbar_cbus_out_i1_o4_a28d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10975] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:11207] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_5' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10073] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_5' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10073] +INFO: [Synth 8-6155] done synthesizing module 'TLXbar_cbus_out_i1_o4_a28d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10975] +INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a28d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12399] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12453] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_6' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:11288] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_6' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:11288] +INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleA_a28d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12221] +INFO: [Synth 8-6157] synthesizing module 'ram_2x114' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12202] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x114' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12202] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleA_a28d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12221] +INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleD_a28d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12320] +INFO: [Synth 8-6157] synthesizing module 'ram_2x79' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12301] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x79' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12301] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleD_a28d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12320] +INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a28d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12399] +INFO: [Synth 8-6157] synthesizing module 'TLAtomicAutomata_cbus' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:13449] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:13829] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_7' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12534] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_7' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12534] +INFO: [Synth 8-6155] done synthesizing module 'TLAtomicAutomata_cbus' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:13449] +INFO: [Synth 8-6157] synthesizing module 'ErrorDeviceWrapper' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16155] +INFO: [Synth 8-6157] synthesizing module 'TLError' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14846] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14907] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_8' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:13973] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_8' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:13973] +INFO: [Synth 8-6157] synthesizing module 'Queue1_TLBundleA_a14d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14799] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_TLBundleA_a14d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14799] +INFO: [Synth 8-6155] done synthesizing module 'TLError' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14846] +INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a14d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16028] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16078] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_9' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14953] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_9' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14953] +INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleA_a14d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15876] +INFO: [Synth 8-6157] synthesizing module 'ram_2x100' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15857] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x100' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15857] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleA_a14d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15876] +INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleD_a14d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15955] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleD_a14d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15955] +INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a14d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16028] +INFO: [Synth 8-6155] done synthesizing module 'ErrorDeviceWrapper' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16155] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_clint' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17261] +INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_CLINT' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17081] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17199] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_10' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16258] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_10' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16258] +INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a26d64s3k1z3u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17017] +INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a26d64s3k1z3u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17017] +INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_CLINT' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17081] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_clint' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17261] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_plic' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18350] +INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_PLIC' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18170] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18288] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_11' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17336] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_11' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17336] +INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a28d64s3k1z3u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18106] +INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a28d64s3k1z3u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18106] +INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_PLIC' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18170] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_plic' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18350] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_bootrom' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19263] +INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_bootrom' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19104] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19205] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_12' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18425] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19035] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_12' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18425] +INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a17d64s3k1z3u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19040] +INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a17d64s3k1z3u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19040] +INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_bootrom' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19104] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_bootrom' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19263] +INFO: [Synth 8-6155] done synthesizing module 'PeripheryBus_cbus' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19330] +INFO: [Synth 8-6157] synthesizing module 'MemoryBus' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:24031] +INFO: [Synth 8-6157] synthesizing module 'ProbePicker' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20610] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20649] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_13' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19882] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_13' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19882] +INFO: [Synth 8-6155] done synthesizing module 'ProbePicker' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20610] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:23555] +INFO: [Synth 8-6157] synthesizing module 'AXI4UserYanker_1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20764] +INFO: [Synth 8-6157] synthesizing module 'Queue2_BundleMap_6' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20707] +INFO: [Synth 8-6157] synthesizing module 'ram_2x10' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20688] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x10' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20688] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_BundleMap_6' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20707] +INFO: [Synth 8-6155] done synthesizing module 'AXI4UserYanker_1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20764] +INFO: [Synth 8-6157] synthesizing module 'AXI4IdIndexer_1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:21713] +INFO: [Synth 8-6155] done synthesizing module 'AXI4IdIndexer_1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:21713] +INFO: [Synth 8-6157] synthesizing module 'TLToAXI4_1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22687] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:23450] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_14' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:21859] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_14' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:21859] +INFO: [Synth 8-6157] synthesizing module 'Queue1_AXI4BundleW_1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22587] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_AXI4BundleW_1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22587] +INFO: [Synth 8-6157] synthesizing module 'Queue1_AXI4BundleARW_1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22621] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_AXI4BundleARW_1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22621] +INFO: [Synth 8-6155] done synthesizing module 'TLToAXI4_1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22687] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:23555] +INFO: [Synth 8-6155] done synthesizing module 'MemoryBus' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:24031] +INFO: [Synth 8-6157] synthesizing module 'CoherenceManagerWrapper' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:27491] +INFO: [Synth 8-6157] synthesizing module 'TLBroadcast' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:26100] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:26482] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_15' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:24349] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_15' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:24349] +INFO: [Synth 8-6157] synthesizing module 'BroadcastFilter' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25732] +INFO: [Common 17-14] Message 'Synth 8-6157' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-6155] done synthesizing module 'BroadcastFilter' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25732] +INFO: [Synth 8-6155] done synthesizing module 'ram_4x144' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25756] +INFO: [Synth 8-6155] done synthesizing module 'Queue4_TLBroadcastData' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25775] +INFO: [Synth 8-6155] done synthesizing module 'TLBroadcastTracker' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25828] +INFO: [Synth 8-6155] done synthesizing module 'TLBroadcastTracker_1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25964] +INFO: [Synth 8-6155] done synthesizing module 'TLBroadcast' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:26100] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:27453] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_16' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:26686] +INFO: [Common 17-14] Message 'Synth 8-6155' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29794] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29834] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43249] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43271] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44089] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44825] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:45961] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47133] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68592] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68606] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68620] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:82885] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:82084] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86970] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85223] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85231] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:90541] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:90573] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:90605] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:90637] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:90669] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:90701] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:90733] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98928] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98950] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99569] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99575] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99581] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100308] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101303] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:102505] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101968] + Parameter FLASH_BOOT bound to: 0 - type: integer +WARNING: [Synth 8-6014] Unused sequential element rmPost_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52403] +WARNING: [Synth 8-6014] Unused sequential element rmPost_pipe_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52405] +WARNING: [Synth 8-6014] Unused sequential element rm_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52416] +WARNING: [Synth 8-6014] Unused sequential element rm_pipe_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52418] +WARNING: [Synth 8-6014] Unused sequential element rm_pipe_pipe_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52420] +WARNING: [Synth 8-6014] Unused sequential element tag_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52422] +WARNING: [Synth 8-6014] Unused sequential element tag_pipe_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52424] +WARNING: [Synth 8-6014] Unused sequential element tag_pipe_pipe_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52426] +WARNING: [Synth 8-6014] Unused sequential element ex_ctrl_rxs1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:61288] +WARNING: [Synth 8-6014] Unused sequential element ex_ctrl_rfs1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62163] +WARNING: [Synth 8-6014] Unused sequential element ex_ctrl_rfs2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62183] +WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rxs2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62375] +WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rxs1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62376] +WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rfs1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62378] +WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rfs2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62379] +WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rxs2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62390] +WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rxs1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62391] +WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rfs1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62393] +WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rfs2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62394] +WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd0val_REG_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62497] +WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd0val_REG_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62498] +WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd1val_REG_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62499] +WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd1val_REG_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62500] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63220] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63221] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63222] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63223] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63224] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_5_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63225] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_6_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63226] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_7_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63227] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_8_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63228] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_9_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63229] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_10_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63230] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_11_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63231] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_12_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63232] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_13_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63233] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_14_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63234] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_15_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63235] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_2_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76912] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_2_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76914] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76916] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76919] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76922] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76926] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76930] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76935] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76940] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76946] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76952] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76959] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_2_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76968] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76970] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76973] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76977] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76982] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76988] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_84_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77024] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_85_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77026] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_87_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77029] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_90_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77033] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_94_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77038] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_99_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77044] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_105_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77052] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_106_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77054] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_108_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77057] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_111_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77061] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_115_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77066] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_120_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77072] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_dataflow_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76917] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_propagate_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76920] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_dataflow_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76923] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_dataflow_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76924] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_propagate_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76927] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_propagate_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76928] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_dataflow_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76931] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_dataflow_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76932] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_dataflow_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76933] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_propagate_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76936] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_propagate_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76937] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_propagate_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76938] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_dataflow_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76941] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_dataflow_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76942] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_dataflow_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76943] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_dataflow_r_4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76944] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_propagate_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76947] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_propagate_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76948] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_propagate_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76949] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_propagate_r_4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76950] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76953] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76954] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76955] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76956] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_5_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76957] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76960] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76961] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76962] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76963] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_5_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76964] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_shift_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76971] +INFO: [Common 17-14] Message 'Synth 8-6014' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [Synth 8-3936] Found unconnected internal register 's2_req_tag_reg' and it is trimmed from '8' to '6' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93740] +WARNING: [Synth 8-3917] design toy_a7_top has port flash_wp_n driven by constant 1 +WARNING: [Synth 8-3917] design toy_a7_top has port flash_hold_n driven by constant 1 +WARNING: [Synth 8-7129] Port wdata[63] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[62] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[61] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[60] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[59] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[58] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[57] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[56] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[55] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[54] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[53] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[52] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[51] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[50] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[49] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[48] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[47] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[46] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[45] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[44] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[43] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[42] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[41] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[40] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[39] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[38] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[37] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[36] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[35] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[34] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[33] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[32] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wstrb[7] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wstrb[6] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wstrb[5] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wstrb[4] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port flash_miso in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port flash_recovery in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port load_addr[3] in module loader_axi is either unconnected or has no load +WARNING: [Synth 8-7129] Port load_addr[2] in module loader_axi is either unconnected or has no load +WARNING: [Synth 8-7129] Port load_addr[1] in module loader_axi is either unconnected or has no load +WARNING: [Synth 8-7129] Port load_addr[0] in module loader_axi is either unconnected or has no load +WARNING: [Synth 8-7129] Port clock in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port reset in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_ready in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_valid in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_opcode[2] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_opcode[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_opcode[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_param[2] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_param[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_param[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_size[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_size[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[6] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[5] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[4] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[3] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[2] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[16] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[15] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[14] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[13] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[12] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[11] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[10] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[9] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[8] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[7] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[6] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[5] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[4] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[3] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[2] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[7] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[6] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[5] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[4] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[3] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[2] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_corrupt in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_ready in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_valid in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_size[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_size[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_source[6] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_source[5] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_source[4] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_source[3] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_source[2] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_source[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_source[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port clock in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port reset in module TLMonitor_28 is either unconnected or has no load +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 3813.723 ; gain = 342.871 ; free physical = 491660 ; free virtual = 628352 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 3828.566 ; gain = 357.715 ; free physical = 491683 ; free virtual = 628374 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 3828.566 ; gain = 357.715 ; free physical = 491683 ; free virtual = 628374 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 3828.566 ; gain = 0.000 ; free physical = 491693 ; free virtual = 628384 +INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc] for cell 'ddr_controller' +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc] for cell 'ddr_controller' +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc/toy_axi_cdc_in_context.xdc] for cell 'memory_cdc' +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc/toy_axi_cdc_in_context.xdc] for cell 'memory_cdc' +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/arty_a7.xdc] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/arty_a7.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/arty_a7.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/toy_a7_top_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/toy_a7_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/flash_boot.xdc] +CRITICAL WARNING: [Designutils 20-1307] Command 'if' is not supported in the xdc constraint file. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/flash_boot.xdc:11] +CRITICAL WARNING: [Designutils 20-1307] Command 'if' is not supported in the xdc constraint file. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/flash_boot.xdc:15] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/flash_boot.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/flash_boot.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/toy_a7_top_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/toy_a7_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +INFO: [Timing 38-2] Deriving generated clocks +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3996.254 ; gain = 0.000 ; free physical = 491625 ; free virtual = 628316 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 1 instances were transformed. + MMCME2_BASE => MMCME2_ADV: 1 instance + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.11 . Memory (MB): peak = 4000.172 ; gain = 0.000 ; free physical = 491615 ; free virtual = 628306 +WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'memory_cdc' at clock pin 'm_axi_aclk' is different from the actual clock period '12.000', this can lead to different synthesis results. +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:33 ; elapsed = 00:00:29 . Memory (MB): peak = 4000.172 ; gain = 529.320 ; free physical = 490374 ; free virtual = 627068 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a100tcsg324-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:33 ; elapsed = 00:00:29 . Memory (MB): peak = 4000.172 ; gain = 529.320 ; free physical = 490374 ; free virtual = 627068 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 2). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 3). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[10]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 4). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[10]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 5). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[11]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 6). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[11]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 7). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[12]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 8). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[12]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 9). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[13]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 10). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[13]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 11). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[1]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 12). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[1]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 13). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[2]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 14). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[2]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 15). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[3]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 16). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[3]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 17). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[4]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 18). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[4]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 19). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[5]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 20). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[5]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 21). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[6]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 22). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[6]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 23). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[7]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 24). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[7]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 25). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[8]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 26). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[8]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 27). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[9]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 28). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[9]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 29). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_ba[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 30). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_ba[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 31). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_ba[1]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 32). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_ba[1]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 33). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_ba[2]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 34). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_ba[2]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 35). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_cas_n. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 36). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_cas_n. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 37). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_ck_n[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 38). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_ck_n[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 39). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_ck_p[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 40). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_ck_p[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 41). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_cke[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 42). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_cke[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 43). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_cs_n[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 44). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_cs_n[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 45). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dm[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 46). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dm[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 47). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dm[1]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 48). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dm[1]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 49). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 50). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 51). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[10]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 52). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[10]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 53). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[11]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 54). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[11]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 55). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[12]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 56). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[12]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 57). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[13]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 58). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[13]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 59). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[14]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 60). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[14]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 61). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[15]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 62). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[15]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 63). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[1]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 64). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[1]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 65). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[2]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 66). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[2]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 67). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[3]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 68). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[3]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 69). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[4]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 70). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[4]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 71). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[5]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 72). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[5]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 73). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[6]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 74). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[6]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 75). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[7]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 76). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[7]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 77). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[8]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 78). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[8]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 79). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[9]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 80). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[9]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 81). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dqs_n[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 82). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dqs_n[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 83). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dqs_n[1]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 84). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dqs_n[1]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 85). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dqs_p[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 86). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dqs_p[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 87). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dqs_p[1]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 88). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dqs_p[1]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 89). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_odt[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 90). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_odt[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 91). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_ras_n. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 92). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_ras_n. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 93). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_reset_n. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 94). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_reset_n. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 95). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_we_n. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 96). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_we_n. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 97). +Applied set_property KEEP_HIERARCHY = SOFT for ddr_controller. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for memory_cdc. (constraint file auto generated constraint). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:33 ; elapsed = 00:00:29 . Memory (MB): peak = 4000.172 ; gain = 529.320 ; free physical = 490291 ; free virtual = 626985 +--------------------------------------------------------------------------------- +INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'uart_rx' +WARNING: [Synth 8-3936] Found unconnected internal register 'cam_a_0_bits_opcode_reg' and it is trimmed from '3' to '1' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:13813] +WARNING: [Synth 8-3936] Found unconnected internal register 'ram_reg' and it is trimmed from '100' to '13' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14825] +WARNING: [Synth 8-3936] Found unconnected internal register 'req_addr_reg' and it is trimmed from '40' to '32' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30468] +WARNING: [Synth 8-3936] Found unconnected internal register 'r_raddr_reg' and it is trimmed from '11' to '4' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36089] +WARNING: [Synth 8-3936] Found unconnected internal register 'in_fmt_reg' and it is trimmed from '2' to '1' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50199] +WARNING: [Synth 8-3936] Found unconnected internal register 'mem_reg_inst_reg' and it is trimmed from '32' to '12' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:54509] +WARNING: [Synth 8-3936] Found unconnected internal register 'ex_reg_inst_reg' and it is trimmed from '32' to '28' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:54256] +WARNING: [Synth 8-3936] Found unconnected internal register 'reg_mcounteren_reg' and it is trimmed from '32' to '3' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:55509] +WARNING: [Synth 8-3936] Found unconnected internal register 'reg_scounteren_reg' and it is trimmed from '32' to '3' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:55511] +WARNING: [Synth 8-3936] Found unconnected internal register 'reg_mideleg_reg' and it is trimmed from '64' to '14' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:55493] +WARNING: [Synth 8-3936] Found unconnected internal register 'reg_medeleg_reg' and it is trimmed from '64' to '16' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:55497] +WARNING: [Synth 8-3936] Found unconnected internal register 'wb_reg_raw_inst_reg' and it is trimmed from '32' to '16' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62407] +WARNING: [Synth 8-3936] Found unconnected internal register 'mem_reg_raw_inst_reg' and it is trimmed from '32' to '16' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62407] +WARNING: [Synth 8-3936] Found unconnected internal register 'ex_reg_raw_inst_reg' and it is trimmed from '32' to '16' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62438] +WARNING: [Synth 8-3936] Found unconnected internal register 'iter_reg_reg' and it is trimmed from '34' to '29' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84823] +WARNING: [Synth 8-3936] Found unconnected internal register 'iter_cmd_reg' and it is trimmed from '34' to '29' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84821] +WARNING: [Synth 8-3936] Found unconnected internal register 'reqReg_vaddr_reg' and it is trimmed from '64' to '39' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86206] +INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'MemConfiger' +INFO: [Synth 8-802] inferred FSM for state register 'ws_reg' in module 'axi_fullwidth' +INFO: [Synth 8-802] inferred FSM for state register 'rs_reg' in module 'axi_fullwidth' +INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'loader_axi' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + IDLE | 000 | 000 + START | 001 | 001 + DATA | 010 | 010 + STOP | 011 | 011 + WAIT_HIGH | 100 | 100 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'uart_rx' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + iSTATE3 | 00000001 | 000 + iSTATE2 | 00000010 | 001 + iSTATE6 | 00000100 | 010 + iSTATE4 | 00010000 | 011 + iSTATE1 | 00100000 | 100 + iSTATE5 | 00001000 | 101 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'MemConfiger' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + P_D965DF20 | 00 | 00 + P_D965DC20 | 01 | 01 + P_D965E030 | 10 | 10 + P_D9611170 | 11 | 11 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'ws_reg' using encoding 'sequential' in module 'axi_fullwidth' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + R_IDLE | 00 | 00 + R_SEND | 01 | 01 + R_RESP | 10 | 10 + R_RETURN | 11 | 11 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'rs_reg' using encoding 'sequential' in module 'axi_fullwidth' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + IDLE | 000001 | 000 + SEND_W | 100000 | 001 + WAIT_B | 010000 | 010 + SEND_R | 001000 | 011 + WAIT_R | 000100 | 100 + RELEASE | 000010 | 101 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'loader_axi' +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:46 ; elapsed = 00:00:42 . Memory (MB): peak = 4000.172 ; gain = 529.320 ; free physical = 486720 ; free virtual = 623434 +--------------------------------------------------------------------------------- +INFO: [Synth 8-223] decloning instance 'platform/chip/system/sbus/system_bus_xbar/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/sbus/system_bus_xbar/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/sbus/system_bus_xbar/monitor_1/plusarg_reader' (plusarg_reader) to 'platform/chip/system/sbus/system_bus_xbar/monitor_1/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/sbus/coupler_to_bus_named_cbus/widget/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/sbus/coupler_to_bus_named_cbus/widget/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/sbus/coupler_to_port_named_mmio_port_axi4/tl2axi4/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/sbus/coupler_to_port_named_mmio_port_axi4/tl2axi4/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/sbus/coupler_to_port_named_mmio_port_axi4/widget/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/sbus/coupler_to_port_named_mmio_port_axi4/widget/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/out_xbar/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/out_xbar/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/buffer/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/buffer/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/atomics/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/atomics/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/wrapped_error_device/error/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/wrapped_error_device/error/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/wrapped_error_device/buffer/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/wrapped_error_device/buffer/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/coupler_to_clint/fragmenter/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/coupler_to_clint/fragmenter/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/coupler_to_plic/fragmenter/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/coupler_to_plic/fragmenter/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/coupler_to_bootrom/fragmenter/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/coupler_to_bootrom/fragmenter/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/mbus/picker/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/mbus/picker/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/mbus/coupler_to_memory_controller_port_named_axi4/tl2axi4/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/mbus/coupler_to_memory_controller_port_named_axi4/tl2axi4/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/coh_wrapper/broadcast_1/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/coh_wrapper/broadcast_1/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/coh_wrapper/binder/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/coh_wrapper/binder/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/tlMasterXbar/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/tlMasterXbar/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/tlMasterXbar/monitor_1/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/tlMasterXbar/monitor_1/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/dtlb/mpu_ppn_barrier' (OptimizationBarrier_TLBEntryData) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/dtlb/entries_barrier_12' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/tlb/mpu_ppn_barrier' (OptimizationBarrier_TLBEntryData) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/tlb/entries_barrier_12' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/xbar/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/xbar/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/xbar/monitor_1/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/xbar/monitor_1/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer_1/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer_1/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/widget_3/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/widget_3/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer_2/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer_2/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/buffer/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/buffer/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/buffer/monitor_1/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/buffer/monitor_1/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/intsource' (IntSyncCrossingSource_n1x1) to 'platform/chip/system/tile_prci_domain/intsource_2' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/clint_domain/clint/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/clint_domain/clint/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/plic_domain/plic/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/plic_domain/plic/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/bootrom_domain/bootrom/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/bootrom_domain/bootrom/monitor/plusarg_reader_1' +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 109 Bit Adders := 1 + 2 Input 107 Bit Adders := 1 + 2 Input 73 Bit Adders := 1 + 3 Input 65 Bit Adders := 1 + 2 Input 64 Bit Adders := 21 + 3 Input 64 Bit Adders := 2 + 3 Input 58 Bit Adders := 1 + 2 Input 58 Bit Adders := 2 + 2 Input 55 Bit Adders := 4 + 2 Input 48 Bit Adders := 1 + 2 Input 40 Bit Adders := 3 + 3 Input 39 Bit Adders := 5 + 2 Input 39 Bit Adders := 3 + 2 Input 37 Bit Adders := 1 + 2 Input 34 Bit Adders := 1 + 2 Input 33 Bit Adders := 3 + 2 Input 32 Bit Adders := 18 + 3 Input 32 Bit Adders := 1 + 2 Input 30 Bit Adders := 8 + 3 Input 29 Bit Adders := 1 + 2 Input 28 Bit Adders := 1 + 2 Input 26 Bit Adders := 4 + 2 Input 20 Bit Adders := 64 + 2 Input 19 Bit Adders := 2 + 2 Input 17 Bit Adders := 2 + 3 Input 16 Bit Adders := 1 + 2 Input 16 Bit Adders := 12 + 2 Input 15 Bit Adders := 4 + 2 Input 14 Bit Adders := 7 + 4 Input 14 Bit Adders := 1 + 2 Input 13 Bit Adders := 6 + 3 Input 13 Bit Adders := 2 + 2 Input 12 Bit Adders := 12 + 3 Input 12 Bit Adders := 1 + 2 Input 11 Bit Adders := 4 + 2 Input 10 Bit Adders := 7 + 4 Input 10 Bit Adders := 1 + 3 Input 10 Bit Adders := 1 + 2 Input 9 Bit Adders := 14 + 3 Input 9 Bit Adders := 4 + 2 Input 8 Bit Adders := 16 + 3 Input 8 Bit Adders := 8 + 2 Input 7 Bit Adders := 6 + 3 Input 7 Bit Adders := 1 + 2 Input 6 Bit Adders := 13 + 3 Input 6 Bit Adders := 2 + 2 Input 5 Bit Adders := 9 + 2 Input 4 Bit Adders := 60 + 5 Input 4 Bit Adders := 1 + 4 Input 4 Bit Adders := 4 + 2 Input 3 Bit Adders := 65 + 3 Input 3 Bit Adders := 7 + 2 Input 2 Bit Adders := 70 + 3 Input 2 Bit Adders := 5 + 4 Input 2 Bit Adders := 1 + 3 Input 1 Bit Adders := 3 + 2 Input 1 Bit Adders := 126 + 4 Input 1 Bit Adders := 39 ++---XORs : + 2 Input 65 Bit XORs := 1 + 2 Input 64 Bit XORs := 5 + 2 Input 32 Bit XORs := 8 + 2 Input 29 Bit XORs := 8 + 2 Input 27 Bit XORs := 6 + 2 Input 25 Bit XORs := 16 + 2 Input 20 Bit XORs := 8 + 2 Input 18 Bit XORs := 8 + 2 Input 16 Bit XORs := 18 + 2 Input 11 Bit XORs := 8 + 2 Input 10 Bit XORs := 3 + 2 Input 4 Bit XORs := 3 + 2 Input 3 Bit XORs := 11 + 2 Input 2 Bit XORs := 8 + 2 Input 1 Bit XORs := 14 + 3 Input 1 Bit XORs := 2 + 4 Input 1 Bit XORs := 2 ++---Registers : + 1269 Bit Registers := 1 + 145 Bit Registers := 1 + 130 Bit Registers := 1 + 128 Bit Registers := 9 + 107 Bit Registers := 1 + 106 Bit Registers := 3 + 105 Bit Registers := 1 + 73 Bit Registers := 1 + 72 Bit Registers := 1 + 67 Bit Registers := 1 + 65 Bit Registers := 14 + 64 Bit Registers := 184 + 62 Bit Registers := 2 + 58 Bit Registers := 2 + 56 Bit Registers := 1 + 55 Bit Registers := 5 + 53 Bit Registers := 3 + 44 Bit Registers := 5 + 42 Bit Registers := 74 + 40 Bit Registers := 21 + 39 Bit Registers := 19 + 34 Bit Registers := 2 + 32 Bit Registers := 115 + 31 Bit Registers := 2 + 30 Bit Registers := 8 + 29 Bit Registers := 2 + 28 Bit Registers := 5 + 27 Bit Registers := 34 + 26 Bit Registers := 4 + 24 Bit Registers := 1 + 23 Bit Registers := 4 + 21 Bit Registers := 8 + 20 Bit Registers := 293 + 19 Bit Registers := 2 + 17 Bit Registers := 2 + 16 Bit Registers := 54 + 14 Bit Registers := 1 + 13 Bit Registers := 8 + 12 Bit Registers := 1 + 11 Bit Registers := 1 + 10 Bit Registers := 140 + 9 Bit Registers := 12 + 8 Bit Registers := 434 + 7 Bit Registers := 27 + 6 Bit Registers := 11 + 5 Bit Registers := 113 + 4 Bit Registers := 193 + 3 Bit Registers := 234 + 2 Bit Registers := 127 + 1 Bit Registers := 1664 ++---Multipliers : + 53x53 Multipliers := 1 + 73x73 Multipliers := 1 + 16x32 Multipliers := 6 + 16x39 Multipliers := 2 + 16x37 Multipliers := 1 ++---RAMs : + 64K Bit (1024 X 64 bit) RAMs := 8 + 8K Bit (256 X 32 bit) RAMs := 8 + 8K Bit (128 X 64 bit) RAMs := 8 + 2K Bit (16 X 128 bit) RAMs := 1 ++---Muxes : + 2 Input 130 Bit Muxes := 4 + 2 Input 128 Bit Muxes := 34 + 4 Input 128 Bit Muxes := 1 + 2 Input 109 Bit Muxes := 1 + 2 Input 108 Bit Muxes := 1 + 2 Input 65 Bit Muxes := 33 + 4 Input 65 Bit Muxes := 4 + 2 Input 64 Bit Muxes := 303 + 3 Input 64 Bit Muxes := 2 + 4 Input 64 Bit Muxes := 26 + 8 Input 64 Bit Muxes := 3 + 2 Input 62 Bit Muxes := 1 + 2 Input 61 Bit Muxes := 2 + 2 Input 58 Bit Muxes := 2 + 2 Input 56 Bit Muxes := 9 + 2 Input 55 Bit Muxes := 11 + 2 Input 54 Bit Muxes := 3 + 2 Input 53 Bit Muxes := 2 + 2 Input 52 Bit Muxes := 10 + 2 Input 51 Bit Muxes := 2 + 2 Input 48 Bit Muxes := 2 + 4 Input 44 Bit Muxes := 1 + 2 Input 44 Bit Muxes := 6 + 4 Input 42 Bit Muxes := 16 + 2 Input 40 Bit Muxes := 25 + 2 Input 39 Bit Muxes := 19 + 5 Input 39 Bit Muxes := 1 + 3 Input 39 Bit Muxes := 1 + 2 Input 38 Bit Muxes := 1 + 2 Input 34 Bit Muxes := 57 + 2 Input 33 Bit Muxes := 1 + 2 Input 32 Bit Muxes := 129 + 3 Input 32 Bit Muxes := 2 + 4 Input 32 Bit Muxes := 4 + 13 Input 32 Bit Muxes := 2 + 10 Input 32 Bit Muxes := 1 + 8 Input 32 Bit Muxes := 1 + 2 Input 31 Bit Muxes := 4 + 2 Input 30 Bit Muxes := 8 + 2 Input 29 Bit Muxes := 5 + 2 Input 28 Bit Muxes := 13 + 2 Input 27 Bit Muxes := 5 + 2 Input 26 Bit Muxes := 15 + 2 Input 25 Bit Muxes := 6 + 2 Input 24 Bit Muxes := 2 + 2 Input 23 Bit Muxes := 11 + 2 Input 22 Bit Muxes := 388 + 2 Input 21 Bit Muxes := 6 + 2 Input 20 Bit Muxes := 621 + 2 Input 19 Bit Muxes := 11 + 4 Input 18 Bit Muxes := 1 + 2 Input 17 Bit Muxes := 1 + 4 Input 16 Bit Muxes := 1 + 2 Input 16 Bit Muxes := 134 + 13 Input 16 Bit Muxes := 3 + 10 Input 16 Bit Muxes := 1 + 8 Input 16 Bit Muxes := 1 + 2 Input 14 Bit Muxes := 12 + 2 Input 13 Bit Muxes := 23 + 2 Input 12 Bit Muxes := 21 + 5 Input 12 Bit Muxes := 1 + 2 Input 11 Bit Muxes := 8 + 2 Input 10 Bit Muxes := 53 + 2 Input 9 Bit Muxes := 41 + 4 Input 9 Bit Muxes := 1 + 13 Input 9 Bit Muxes := 2 + 2 Input 8 Bit Muxes := 370 + 6 Input 8 Bit Muxes := 1 + 3 Input 8 Bit Muxes := 1 + 5 Input 8 Bit Muxes := 1 + 13 Input 8 Bit Muxes := 3 + 4 Input 8 Bit Muxes := 2 + 2 Input 7 Bit Muxes := 28 + 4 Input 7 Bit Muxes := 1 + 7 Input 7 Bit Muxes := 2 + 6 Input 7 Bit Muxes := 1 + 2 Input 6 Bit Muxes := 32 + 4 Input 6 Bit Muxes := 1 + 5 Input 6 Bit Muxes := 1 + 6 Input 6 Bit Muxes := 1 + 2 Input 5 Bit Muxes := 103 + 4 Input 5 Bit Muxes := 1 + 5 Input 5 Bit Muxes := 1 + 3 Input 5 Bit Muxes := 1 + 4 Input 4 Bit Muxes := 10 + 2 Input 4 Bit Muxes := 198 + 3 Input 4 Bit Muxes := 5 + 5 Input 4 Bit Muxes := 1 + 8 Input 4 Bit Muxes := 4 + 6 Input 4 Bit Muxes := 1 + 13 Input 4 Bit Muxes := 1 + 2 Input 3 Bit Muxes := 225 + 8 Input 3 Bit Muxes := 6 + 3 Input 3 Bit Muxes := 7 + 4 Input 3 Bit Muxes := 11 + 5 Input 3 Bit Muxes := 5 + 6 Input 3 Bit Muxes := 2 + 2 Input 2 Bit Muxes := 257 + 4 Input 2 Bit Muxes := 16 + 3 Input 2 Bit Muxes := 9 + 5 Input 2 Bit Muxes := 2 + 16 Input 2 Bit Muxes := 5 + 2 Input 1 Bit Muxes := 1279 + 8 Input 1 Bit Muxes := 6 + 6 Input 1 Bit Muxes := 12 + 4 Input 1 Bit Muxes := 33 + 3 Input 1 Bit Muxes := 2 + 5 Input 1 Bit Muxes := 6 + 13 Input 1 Bit Muxes := 10 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 240 (col length:80) +BRAMs: 270 (col length: RAMB18 80 RAMB36 40) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +WARNING: [Synth 8-3936] Found unconnected internal register 'subRob/sram/sram_ext/lanes[0].R0_data_reg' and it is trimmed from '1269' to '1262' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:103] +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +WARNING: [Synth 8-3917] design toy_a7_top has port flash_wp_n driven by constant 1 +WARNING: [Synth 8-3917] design toy_a7_top has port flash_hold_n driven by constant 1 +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 10 [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52365] +DSP Report: Generating DSP product_pipe_b0, operation Mode is: A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b0, operation Mode is: PCIN+A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b_reg, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +DSP Report: Generating DSP product_pipe_b0, operation Mode is: A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b0, operation Mode is: PCIN+A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b_reg, operation Mode is: (PCIN+A2*B2)'. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +DSP Report: Generating DSP product_pipe_b0, operation Mode is: A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b0, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b_reg, operation Mode is: (PCIN+A2*B2)'. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +INFO: [Synth 8-4471] merging register 'cfg_max_j_reg[15:0]' into 'cfg_max_j_reg[15:0]' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79428] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79511] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79576] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79605] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79627] +DSP Report: Generating DSP _GEN_363, operation Mode is: A2*B2. +DSP Report: register cfg_max_j_reg is absorbed into DSP _GEN_363. +DSP Report: register cfg_max_i_reg is absorbed into DSP _GEN_363. +DSP Report: operator _GEN_363 is absorbed into DSP _GEN_363. +DSP Report: Generating DSP _GEN_362, operation Mode is: A*B2. +DSP Report: register _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: operator _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: operator _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: Generating DSP _GEN_362, operation Mode is: (PCIN>>17)+A2*B. +DSP Report: register _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: operator _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: operator _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: Generating DSP io_cmd_bits_slots_0_bits_dram_addr5, operation Mode is: A2*B2. +DSP Report: register io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: register io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: operator io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: operator io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: Generating DSP io_cmd_bits_slots_0_bits_dram_addr5, operation Mode is: (PCIN>>17)+A2*B. +DSP Report: register io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: operator io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: operator io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: Generating DSP io_cmd_bits_slots_1_bits_dram_addr4, operation Mode is: A2*B. +DSP Report: register io_cmd_bits_slots_1_bits_dram_addr4 is absorbed into DSP io_cmd_bits_slots_1_bits_dram_addr4. +DSP Report: operator io_cmd_bits_slots_1_bits_dram_addr4 is absorbed into DSP io_cmd_bits_slots_1_bits_dram_addr4. +DSP Report: operator io_cmd_bits_slots_1_bits_dram_addr4 is absorbed into DSP io_cmd_bits_slots_1_bits_dram_addr4. +DSP Report: Generating DSP io_cmd_bits_slots_1_bits_dram_addr4, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_cmd_bits_slots_1_bits_dram_addr4 is absorbed into DSP io_cmd_bits_slots_1_bits_dram_addr4. +DSP Report: operator io_cmd_bits_slots_1_bits_dram_addr4 is absorbed into DSP io_cmd_bits_slots_1_bits_dram_addr4. +DSP Report: Generating DSP io_cmd_bits_slots_2_bits_dram_addr2, operation Mode is: A2*B. +DSP Report: register io_cmd_bits_slots_2_bits_dram_addr2 is absorbed into DSP io_cmd_bits_slots_2_bits_dram_addr2. +DSP Report: operator io_cmd_bits_slots_2_bits_dram_addr2 is absorbed into DSP io_cmd_bits_slots_2_bits_dram_addr2. +DSP Report: operator io_cmd_bits_slots_2_bits_dram_addr2 is absorbed into DSP io_cmd_bits_slots_2_bits_dram_addr2. +DSP Report: Generating DSP io_cmd_bits_slots_2_bits_dram_addr2, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_cmd_bits_slots_2_bits_dram_addr2 is absorbed into DSP io_cmd_bits_slots_2_bits_dram_addr2. +DSP Report: operator io_cmd_bits_slots_2_bits_dram_addr2 is absorbed into DSP io_cmd_bits_slots_2_bits_dram_addr2. +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79673] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79673] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79677] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79681] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79681] +DSP Report: Generating DSP _irow_T_7, operation Mode is: C+A*B. +DSP Report: operator _irow_T_7 is absorbed into DSP _irow_T_7. +DSP Report: operator _irow_T_71 is absorbed into DSP _irow_T_7. +DSP Report: Generating DSP io_inputAddr4, operation Mode is: A*B. +DSP Report: operator io_inputAddr4 is absorbed into DSP io_inputAddr4. +DSP Report: Generating DSP io_inputAddr5, operation Mode is: A*B. +DSP Report: operator io_inputAddr5 is absorbed into DSP io_inputAddr5. +DSP Report: Generating DSP io_inputAddr4, operation Mode is: A*B. +DSP Report: operator io_inputAddr4 is absorbed into DSP io_inputAddr4. +DSP Report: operator io_inputAddr4 is absorbed into DSP io_inputAddr4. +DSP Report: Generating DSP io_inputAddr4, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_inputAddr4 is absorbed into DSP io_inputAddr4. +DSP Report: operator io_inputAddr4 is absorbed into DSP io_inputAddr4. +DSP Report: Generating DSP _icol_T_7, operation Mode is: C+A*B. +DSP Report: operator _icol_T_7 is absorbed into DSP _icol_T_7. +DSP Report: operator _icol_T_71 is absorbed into DSP _icol_T_7. +DSP Report: Generating DSP io_inputAddr2, operation Mode is: PCIN+A:B+C. +DSP Report: operator io_inputAddr2 is absorbed into DSP io_inputAddr2. +DSP Report: Generating DSP io_inputAddr1, operation Mode is: A*B. +DSP Report: operator io_inputAddr1 is absorbed into DSP io_inputAddr1. +DSP Report: operator io_inputAddr1 is absorbed into DSP io_inputAddr1. +DSP Report: Generating DSP io_inputAddr1, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_inputAddr1 is absorbed into DSP io_inputAddr1. +DSP Report: operator io_inputAddr1 is absorbed into DSP io_inputAddr1. +DSP Report: Generating DSP io_weightAddr4, operation Mode is: C+A*B. +DSP Report: operator io_weightAddr4 is absorbed into DSP io_weightAddr4. +DSP Report: operator io_weightAddr5 is absorbed into DSP io_weightAddr4. +DSP Report: Generating DSP io_weightAddr2, operation Mode is: C+A*B. +DSP Report: operator io_weightAddr2 is absorbed into DSP io_weightAddr2. +DSP Report: operator io_weightAddr3 is absorbed into DSP io_weightAddr2. +DSP Report: Generating DSP io_weightAddr1, operation Mode is: A*B. +DSP Report: operator io_weightAddr1 is absorbed into DSP io_weightAddr1. +DSP Report: operator io_weightAddr1 is absorbed into DSP io_weightAddr1. +DSP Report: Generating DSP io_weightAddr1, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_weightAddr1 is absorbed into DSP io_weightAddr1. +DSP Report: operator io_weightAddr1 is absorbed into DSP io_weightAddr1. +DSP Report: Generating DSP io_outputAddr4, operation Mode is: A*B. +DSP Report: operator io_outputAddr4 is absorbed into DSP io_outputAddr4. +DSP Report: Generating DSP io_outputAddr5, operation Mode is: A*B. +DSP Report: operator io_outputAddr5 is absorbed into DSP io_outputAddr5. +DSP Report: Generating DSP io_outputAddr4, operation Mode is: A*B. +DSP Report: operator io_outputAddr4 is absorbed into DSP io_outputAddr4. +DSP Report: operator io_outputAddr4 is absorbed into DSP io_outputAddr4. +DSP Report: Generating DSP io_outputAddr4, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_outputAddr4 is absorbed into DSP io_outputAddr4. +DSP Report: operator io_outputAddr4 is absorbed into DSP io_outputAddr4. +DSP Report: Generating DSP io_outputAddr2, operation Mode is: PCIN+(A:0x0):B+C. +DSP Report: operator io_outputAddr2 is absorbed into DSP io_outputAddr2. +DSP Report: Generating DSP io_outputAddr1, operation Mode is: A*B. +DSP Report: operator io_outputAddr1 is absorbed into DSP io_outputAddr1. +DSP Report: operator io_outputAddr1 is absorbed into DSP io_outputAddr1. +DSP Report: Generating DSP io_outputAddr1, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_outputAddr1 is absorbed into DSP io_outputAddr1. +DSP Report: operator io_outputAddr1 is absorbed into DSP io_outputAddr1. +WARNING: [Synth 8-3936] Found unconnected internal register 'cfg_input_stride_reg' and it is trimmed from '32' to '22' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79776] +WARNING: [Synth 8-3936] Found unconnected internal register 'cfg_output_stride_reg' and it is trimmed from '32' to '24' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79780] +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_domain_id[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_domain_id[2] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_funct[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[63] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[62] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[61] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[60] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[59] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[58] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_domain_id[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_domain_id[2] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_funct[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[63] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[62] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[61] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[60] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[59] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[58] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_domain_id[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_domain_id[2] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_funct[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[63] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[62] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[61] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[60] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[59] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[58] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[4] driven by constant 0 +INFO: [Synth 8-4471] merging register 'reqReg_pixel_bytes_reg[9:0]' into 'reqReg_pixel_bytes_reg[9:0]' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86013] +DSP Report: Generating DSP rowSkip_reg, operation Mode is: (A*B)'. +DSP Report: register rowSkip_reg is absorbed into DSP rowSkip_reg. +DSP Report: operator rowSkip0 is absorbed into DSP rowSkip_reg. +DSP Report: Generating DSP readVaddr1, operation Mode is: A*B2. +DSP Report: register reqReg_pixel_bytes_reg is absorbed into DSP readVaddr1. +DSP Report: operator readVaddr1 is absorbed into DSP readVaddr1. +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 17 [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:58083] +DSP Report: Generating DSP remainder1, operation Mode is: A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [Synth 8-6430] The Block RAM "dcache/mshrs/sdq_ext/Memory_reg" may get memory collision error if read and write address collide. Use attribute (* rw_addr_collision= "yes" *) to avoid collision +WARNING: [Synth 8-3917] design BBTile__GCB2 has port io_requestor_1_resp_bits_tag[7] driven by constant 0 +WARNING: [Synth 8-3917] design BBTile__GCB2 has port io_requestor_1_resp_bits_tag[6] driven by constant 0 +WARNING: [Synth 8-3917] design BBTile__GCB2 has port io_requestor_2_resp_bits_tag[7] driven by constant 0 +WARNING: [Synth 8-3917] design BBTile__GCB2 has port io_requestor_2_resp_bits_tag[6] driven by constant 0 +WARNING: [Synth 8-3917] design BBTile__GCB2 has port auto_buffer_out_1_c_bits_source[1] driven by constant 0 +RAM Pipeline Warning: Read Address Register Found For RAM sdq_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance. +RAM Pipeline Warning: Read Address Register Found For RAM sdq_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance. +RAM Pipeline Warning: Read Address Register Found For RAM sdq_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance. +WARNING: [Synth 8-6430] The Block RAM "dcache/mshrs/sdq_ext/Memory_reg" may get memory collision error if read and write address collide. Use attribute (* rw_addr_collision= "yes" *) to avoid collision +RAM Pipeline Warning: Read Address Register Found For RAM sdq_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance. +--------------------------------------------------------------------------------- +Start Pre Area Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Iterative Area Optimization +--------------------------------------------------------------------------------- +INFO: [Synth 8-3333] propagating constant 0 across sequential element (fpmu/\io_out_pipe_b_exc_reg[3] ) +INFO: [Synth 8-3886] merging instance 'wb_toint_exc_reg[1]' (FDE) to 'wb_toint_exc_reg[3]' +INFO: [Synth 8-3886] merging instance 'wb_toint_exc_reg[2]' (FDE) to 'wb_toint_exc_reg[3]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\wb_toint_exc_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (sharedFma/\io_out_pipe_b_exc_reg[3] ) +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[47]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[46]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[45]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[44]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[43]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[42]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[41]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[40]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[39]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[38]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[37]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[36]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[35]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[34]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[33]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[32]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[31]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[30]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[29]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[28]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[27]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[26]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[25]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[24]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[23]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[22]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[21]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[47]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[46]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[45]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[44]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[43]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[42]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[41]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[40]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[39]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[38]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[37]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[36]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[35]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[34]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[33]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[32]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[31]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[30]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[29]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[28]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[27]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[26]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[25]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[24]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[23]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[22]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[21]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[20]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[19]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[18]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[17]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[47]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[46]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[45]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[44]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[43]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[42]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[41]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[40]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[39]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[38]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[37]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[36]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[35]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[34]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[33]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[32]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[31]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[30]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[29]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[28]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[27]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[26]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[25]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[24]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[23]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[22]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[21]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[20]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[19]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[18]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[17]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_15_reg[9]' (FDRE) to 'bat/entNewAlias_15_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_15_reg[6]' (FDRE) to 'bat/entNewAlias_15_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_15_reg[7]' (FDRE) to 'bat/entNewAlias_15_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_15_reg[8]' (FDRE) to 'bat/entNewAlias_15_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_15_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_14_reg[9]' (FDRE) to 'bat/entNewAlias_14_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_14_reg[6]' (FDRE) to 'bat/entNewAlias_14_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_14_reg[7]' (FDRE) to 'bat/entNewAlias_14_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_14_reg[8]' (FDRE) to 'bat/entNewAlias_14_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_14_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_13_reg[9]' (FDRE) to 'bat/entNewAlias_13_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_13_reg[6]' (FDRE) to 'bat/entNewAlias_13_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_13_reg[7]' (FDRE) to 'bat/entNewAlias_13_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_13_reg[8]' (FDRE) to 'bat/entNewAlias_13_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_13_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_12_reg[9]' (FDRE) to 'bat/entNewAlias_12_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_12_reg[6]' (FDRE) to 'bat/entNewAlias_12_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_12_reg[7]' (FDRE) to 'bat/entNewAlias_12_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_12_reg[8]' (FDRE) to 'bat/entNewAlias_12_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_12_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_11_reg[9]' (FDRE) to 'bat/entNewAlias_11_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_11_reg[6]' (FDRE) to 'bat/entNewAlias_11_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_11_reg[7]' (FDRE) to 'bat/entNewAlias_11_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_11_reg[8]' (FDRE) to 'bat/entNewAlias_11_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_11_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_10_reg[9]' (FDRE) to 'bat/entNewAlias_10_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_10_reg[6]' (FDRE) to 'bat/entNewAlias_10_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_10_reg[7]' (FDRE) to 'bat/entNewAlias_10_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_10_reg[8]' (FDRE) to 'bat/entNewAlias_10_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_10_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_9_reg[9]' (FDRE) to 'bat/entNewAlias_9_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_9_reg[6]' (FDRE) to 'bat/entNewAlias_9_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_9_reg[7]' (FDRE) to 'bat/entNewAlias_9_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_9_reg[8]' (FDRE) to 'bat/entNewAlias_9_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_9_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_8_reg[9]' (FDRE) to 'bat/entNewAlias_8_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_8_reg[6]' (FDRE) to 'bat/entNewAlias_8_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_8_reg[7]' (FDRE) to 'bat/entNewAlias_8_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_8_reg[8]' (FDRE) to 'bat/entNewAlias_8_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_8_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_7_reg[9]' (FDRE) to 'bat/entNewAlias_7_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_7_reg[6]' (FDRE) to 'bat/entNewAlias_7_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_7_reg[7]' (FDRE) to 'bat/entNewAlias_7_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_7_reg[8]' (FDRE) to 'bat/entNewAlias_7_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_7_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_6_reg[9]' (FDRE) to 'bat/entNewAlias_6_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_6_reg[6]' (FDRE) to 'bat/entNewAlias_6_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_6_reg[7]' (FDRE) to 'bat/entNewAlias_6_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_6_reg[8]' (FDRE) to 'bat/entNewAlias_6_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_6_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_5_reg[9]' (FDRE) to 'bat/entNewAlias_5_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_5_reg[6]' (FDRE) to 'bat/entNewAlias_5_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_5_reg[7]' (FDRE) to 'bat/entNewAlias_5_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_5_reg[8]' (FDRE) to 'bat/entNewAlias_5_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_5_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_4_reg[9]' (FDRE) to 'bat/entNewAlias_4_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_4_reg[6]' (FDRE) to 'bat/entNewAlias_4_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_4_reg[7]' (FDRE) to 'bat/entNewAlias_4_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_4_reg[8]' (FDRE) to 'bat/entNewAlias_4_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_4_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_3_reg[9]' (FDRE) to 'bat/entNewAlias_3_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_3_reg[6]' (FDRE) to 'bat/entNewAlias_3_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_3_reg[7]' (FDRE) to 'bat/entNewAlias_3_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_3_reg[8]' (FDRE) to 'bat/entNewAlias_3_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_3_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_2_reg[9]' (FDRE) to 'bat/entNewAlias_2_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_2_reg[6]' (FDRE) to 'bat/entNewAlias_2_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_2_reg[7]' (FDRE) to 'bat/entNewAlias_2_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_2_reg[8]' (FDRE) to 'bat/entNewAlias_2_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_2_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_1_reg[9]' (FDRE) to 'bat/entNewAlias_1_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_1_reg[6]' (FDRE) to 'bat/entNewAlias_1_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_1_reg[7]' (FDRE) to 'bat/entNewAlias_1_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_1_reg[8]' (FDRE) to 'bat/entNewAlias_1_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_1_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_0_reg[9]' (FDRE) to 'bat/entNewAlias_0_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_0_reg[6]' (FDRE) to 'bat/entNewAlias_0_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_0_reg[7]' (FDRE) to 'bat/entNewAlias_0_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_0_reg[8]' (FDRE) to 'bat/entNewAlias_0_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_0_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/v2a_15_reg[9]' (FDRE) to 'bat/v2a_15_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_14_reg[9]' (FDRE) to 'bat/v2a_14_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_13_reg[9]' (FDRE) to 'bat/v2a_13_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_12_reg[9]' (FDRE) to 'bat/v2a_12_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_11_reg[9]' (FDRE) to 'bat/v2a_11_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_10_reg[9]' (FDRE) to 'bat/v2a_10_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_9_reg[9]' (FDRE) to 'bat/v2a_9_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_8_reg[9]' (FDRE) to 'bat/v2a_8_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_7_reg[9]' (FDRE) to 'bat/v2a_7_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_6_reg[9]' (FDRE) to 'bat/v2a_6_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_5_reg[9]' (FDRE) to 'bat/v2a_5_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_4_reg[9]' (FDRE) to 'bat/v2a_4_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_3_reg[9]' (FDRE) to 'bat/v2a_3_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_2_reg[9]' (FDRE) to 'bat/v2a_2_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_1_reg[9]' (FDRE) to 'bat/v2a_1_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_0_reg[9]' (FDRE) to 'bat/v2a_0_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_15_reg[6]' (FDRE) to 'bat/v2a_15_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_14_reg[6]' (FDRE) to 'bat/v2a_14_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_13_reg[6]' (FDRE) to 'bat/v2a_13_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_12_reg[6]' (FDRE) to 'bat/v2a_12_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_11_reg[6]' (FDRE) to 'bat/v2a_11_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_10_reg[6]' (FDRE) to 'bat/v2a_10_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_9_reg[6]' (FDRE) to 'bat/v2a_9_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_8_reg[6]' (FDRE) to 'bat/v2a_8_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_7_reg[6]' (FDRE) to 'bat/v2a_7_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_6_reg[6]' (FDRE) to 'bat/v2a_6_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_5_reg[6]' (FDRE) to 'bat/v2a_5_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_4_reg[6]' (FDRE) to 'bat/v2a_4_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_3_reg[6]' (FDRE) to 'bat/v2a_3_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_2_reg[6]' (FDRE) to 'bat/v2a_2_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_1_reg[6]' (FDRE) to 'bat/v2a_1_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_0_reg[6]' (FDRE) to 'bat/v2a_0_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_15_reg[7]' (FDRE) to 'bat/v2a_15_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_14_reg[7]' (FDRE) to 'bat/v2a_14_reg[8]' +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_15_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_14_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_13_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_12_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_11_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_10_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_9_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_8_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_7_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_6_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_5_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_4_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_3_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_2_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_1_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_0_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_15_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_14_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_13_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_12_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_11_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_10_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_9_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_8_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_7_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_6_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_5_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_4_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_3_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_2_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_1_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_0_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_15_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_0_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_1_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_2_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_3_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_4_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_5_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_6_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_7_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_8_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_9_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_10_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_11_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_12_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_13_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_14_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [Synth 8-3332] Sequential element (FSM_onehot_state_reg[7]) is unused and will be removed from module MemConfiger. +WARNING: [Synth 8-3332] Sequential element (FSM_onehot_state_reg[6]) is unused and will be removed from module MemConfiger. +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\roccMemIF/s1_req_tag_reg[0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/\ex_reg_cause_reg[7] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_mie_reg[38] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_mcountinhibit_reg[1] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\roccMemIF/io_cache_s1_data_r_data_reg[63] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/reg_singleStepped_reg) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_satp_mode_reg[2] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[40] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[41] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[42] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[43] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[44] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[45] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[46] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[47] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[48] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[49] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[50] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[51] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[52] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[53] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[54] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[55] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[56] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[57] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[58] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[59] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[60] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[61] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[62] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (cores_0/csr/\reg_misa_reg[63] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[7] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[10] ) +INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_114_115 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_108_113 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_102_107 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_96_101 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_90_95 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_84_89 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_78_83 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_72_77 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_66_71 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_60_65 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_54_59 from module BBTile__GCB1 due to constant propagation +INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_114_115 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_72_77 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_66_71 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_60_65 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_54_59 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_48_53 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_42_47 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_36_41 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_30_35 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_24_29 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_18_23 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_72_77 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_10/buffer_1/nodeOut_a_q/ram_ext/Memory_reg_0_1_6_11 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_4/coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_r_deq_q/ram_ext/Memory_reg_0_1_60_65 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_4/coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_r_deq_q/ram_ext/Memory_reg_0_1_54_59 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_4/coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_r_deq_q/ram_ext/Memory_reg_0_1_48_53 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_11/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_0/ram_ext/Memory_reg_0_7_60_65 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_12/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_1/ram_ext/Memory_reg_0_7_60_65 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_13/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_2/ram_ext/Memory_reg_0_7_60_65 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_14/i_0/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_3/ram_ext/Memory_reg_0_7_60_65 from module extram__61 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_11/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_0/ram_ext/Memory_reg_0_7_54_59 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_12/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_1/ram_ext/Memory_reg_0_7_60_65 from module SystemBus due to constant propagation +--------------------------------------------------------------------------------- +Start Post Area Optimization : Time (s): cpu = 00:12:02 ; elapsed = 00:12:36 . Memory (MB): peak = 6506.113 ; gain = 3035.262 ; free physical = 468157 ; free virtual = 608469 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:12:08 ; elapsed = 00:12:42 . Memory (MB): peak = 6506.113 ; gain = 3035.262 ; free physical = 467930 ; free virtual = 608253 +--------------------------------------------------------------------------------- + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_0 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_0 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_10 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_10 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_11 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_12 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_13 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_14 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_15 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_16 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_17 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_18 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_19 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1a : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1b : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1c : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1d : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1e : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1f : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_2 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_20 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_21 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_22 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_23 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_24 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_25 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_26 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_27 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_28 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_29 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2a : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2b : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2c : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2d : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2e : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2f : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_3 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_3 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_30 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_4 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_4 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_5 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_5 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_6 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_6 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_7 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_7 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_8 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_8 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_9 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_9 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_a : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_a : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_b : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_b : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_c : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_c : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_d : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_d : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_e : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_e : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_f : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_f : 0 0 : 519 519 : Used 1 time 100 + Sort Area is BBTile__GCB0 remainder1_8 : 0 0 : 3475 13938 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_8 : 0 1 : 3494 13938 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_8 : 0 2 : 3475 13938 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_8 : 0 3 : 3494 13938 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_6 : 0 0 : 3137 13243 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_6 : 0 1 : 3475 13243 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_6 : 0 2 : 3494 13243 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_6 : 0 3 : 3137 13243 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_4 : 0 0 : 3137 12905 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_4 : 0 1 : 3137 12905 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_4 : 0 2 : 3494 12905 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_4 : 0 3 : 3137 12905 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_0 : 0 0 : 3137 12586 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_0 : 0 1 : 3156 12586 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_0 : 0 2 : 3137 12586 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_0 : 0 3 : 3156 12586 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_8 : 0 0 : 3274 9889 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_8 : 0 1 : 3274 9889 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_8 : 0 2 : 3341 9889 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_4 : 0 0 : 3274 9733 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_4 : 0 1 : 3137 9733 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_4 : 0 2 : 3322 9733 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_0 : 0 0 : 3137 9478 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_0 : 0 1 : 3156 9478 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_0 : 0 2 : 3185 9478 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr1_15 : 0 0 : 2588 5929 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr1_15 : 0 1 : 3341 5929 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_weightAddr1_1b : 0 0 : 2588 5929 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_weightAddr1_1b : 0 1 : 3341 5929 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr1_20 : 0 0 : 2588 5807 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr1_20 : 0 1 : 3219 5807 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_0_bits_dram_addr5_5 : 0 0 : 3052 5790 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_0_bits_dram_addr5_5 : 0 1 : 2738 5790 : Used 1 time 0 + Sort Area is GemminiBall__GC0 _GEN_362_2 : 0 0 : 3034 5772 : Used 1 time 0 + Sort Area is GemminiBall__GC0 _GEN_362_2 : 0 1 : 2738 5772 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_1_bits_dram_addr4_7 : 0 0 : 3035 5756 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_1_bits_dram_addr4_7 : 0 1 : 2721 5756 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_2_bits_dram_addr2_a : 0 0 : 3035 5756 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_2_bits_dram_addr2_a : 0 1 : 2721 5756 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr4_f : 0 0 : 2588 5309 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr4_f : 0 1 : 2721 5309 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr4_1d : 0 0 : 2588 5309 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr4_1d : 0 1 : 2721 5309 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr4_12 : 0 0 : 2722 2987 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr4_12 : 0 1 : 265 2987 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_weightAddr2_19 : 0 0 : 2838 2838 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr4_1e : 0 0 : 1946 2168 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr4_1e : 0 1 : 222 2168 : Used 1 time 0 + Sort Area is GemminiBall__GC0 _GEN_363_0 : 0 0 : 1978 1978 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr5_d : 0 0 : 1946 1946 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr5_1c : 0 0 : 1946 1946 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_a : 0 0 : 1207 1207 : Used 1 time 0 + Sort Area is GemminiBall__GC0 _icol_T_7_b : 0 0 : 949 949 : Used 1 time 0 + Sort Area is GemminiBall__GC0 _irow_T_7_11 : 0 0 : 949 949 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_weightAddr4_17 : 0 0 : 949 949 : Used 1 time 0 + Sort Area is MemFrontend rowSkip_reg_0 : 0 0 : 768 768 : Used 1 time 0 + Sort Area is MemFrontend readVaddr1_2 : 0 0 : 733 733 : Used 1 time 0 +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Block RAM: Preliminary Mapping Report (see note below) ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|GlobalROB__GB1 | robOperands/robOperands_ext/lanes[0].ram_reg | 16 x 128(READ_FIRST) | W | | 16 x 128(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_0 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_1 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_2 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_3 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_4 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_5 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_6 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_7 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|dcache/mshrs | sdq_ext/Memory_reg | 17 x 64(READ_FIRST) | W | | 17 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_0/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_0/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_1/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_1/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_0/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_0/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_1/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_1/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ + +Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once. + +Distributed RAM: Preliminary Mapping Report (see note below) ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ +|regfile_ext | bank0_reg | User Attribute | 32 x 65 | RAM32M x 33 | +|regfile_ext | bank1_reg | User Attribute | 32 x 65 | RAM32M x 33 | +|toy_a7_top | completeQueue/ram_ext/Memory_reg | Implied | 16 x 4 | RAM32M x 1 | +|toy_a7_top | subRob/sram/sram_ext/lanes[0].ram_reg | User Attribute | 8 x 1262 | RAM32M x 211 | +|toy_a7_top | total_rows_q/ram_ext/Memory_reg | Implied | 8 x 7 | RAM32M x 2 | +|GemminiExCtrl__GC0 | rdQueue0/ram_data_ext/Memory_reg | Implied | 8 x 64 | RAM32M x 11 | +|GemminiExCtrl__GC0 | rdQueue1/ram_data_ext/Memory_reg | Implied | 8 x 64 | RAM32M x 11 | +|toy_a7_top | ballRs/fifo/ram_ext/Memory_reg | Implied | 4 x 281 | RAM32M x 47 | +|memRs | fifo/ram_ext/Memory_reg | Implied | 4 x 158 | RAM32M x 27 | +|toy_a7_top | bankReadReqQ_q/ram_ext/Memory_reg | Implied | 8 x 21 | RAM32M x 4 | +|toy_a7_top | bankReadReqQ_q_1/ram_ext/Memory_reg | Implied | 8 x 21 | RAM32M x 4 | +|cores_0 | rf_ext/Memory_reg | Implied | 32 x 64 | RAM32M x 22 | +|BBTile__GCB0 | buffer_2/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 117 | RAM32M x 20 | +|BBTile__GCB0 | buffer_2/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 78 | RAM32M x 13 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_tag_array/bbtile_icache_tag_array_ext/lanes[0].ram_reg | User Attribute | 64 x 21 | RAM64X1S x 21 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_tag_array/bbtile_icache_tag_array_ext/lanes[1].ram_reg | User Attribute | 64 x 21 | RAM64X1S x 21 | +|BBTile__GCB1 | buffer_1/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 116 | RAM32M x 20 | +|BBTile__GCB1 | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 116 | RAM32M x 20 | +|BBTile__GCB1 | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 76 | RAM32M x 13 | +|dcache/mshrs | mshrs_0/rpq/ram_ext/Memory_reg | Implied | 16 x 64 | RAM32M x 11 | +|dcache/meta | tag_array/tag_array_ext/lanes[0].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[1].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[2].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[3].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|toy_a7_top | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 189 | RAM32M x 32 | +|toy_a7_top | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 142 | RAM32M x 24 | +|toy_a7_top | buffer/nodeOut_a_q_1/ram_ext/Memory_reg | Implied | 2 x 188 | RAM32M x 32 | +|toy_a7_top | buffer/nodeIn_d_q_1/ram_ext/Memory_reg | Implied | 2 x 142 | RAM32M x 24 | +|toy_a7_top | buffer/nodeIn_b_q/ram_ext/Memory_reg | Implied | 2 x 60 | RAM32M x 10 | +|toy_a7_top | buffer/nodeOut_c_q/ram_ext/Memory_reg | Implied | 2 x 172 | RAM32M x 29 | +|toy_a7_top | buffer/nodeOut_e_q/ram_sink_ext/Memory_reg | Implied | 2 x 1 | RAM16X1D x 1 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_aw_deq_q/ram_ext/Memory_reg | Implied | 2 x 58 | RAM32M x 10 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_w_deq_q/ram_ext/Memory_reg | Implied | 2 x 73 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_b_deq_q/ram_ext/Memory_reg | Implied | 2 x 4 | RAM32M x 1 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_ar_deq_q/ram_ext/Memory_reg | Implied | 2 x 58 | RAM32M x 10 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_r_deq_q/ram_ext/Memory_reg | Implied | 2 x 69 | RAM32M x 12 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_1/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_2/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_3/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_4/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_5/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_0/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_1/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_2/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_3/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|cbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 114 | RAM32M x 19 | +|cbus | wrapped_error_device/buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 100 | RAM32M x 17 | +|cbus | wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 79 | RAM32M x 14 | +|cbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 79 | RAM32M x 14 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_1/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_2/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_3/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_4/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_5/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_6/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_7/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_8/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_9/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_10/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_11/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_12/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_13/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_14/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_15/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_16/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_17/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_18/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_19/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_20/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_21/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_22/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_23/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_24/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_25/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_26/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_27/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_28/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_29/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_30/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_31/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|coh_wrapper | broadcast_1/TLBroadcastTracker/o_data_q/ram_ext/Memory_reg | Implied | 4 x 144 | RAM32M x 24 | +|coh_wrapper | broadcast_1/TLBroadcastTracker_1/o_data_q/ram_ext/Memory_reg | Implied | 4 x 144 | RAM32M x 24 | +|platformi_21/loader | payload_reg | User Attribute | 256 x 8 | RAM128X1D x 16 | +|platformi_21/peripherals | fifo_reg | User Attribute | 256 x 8 | RAM64M x 12 | ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ + +Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. + +DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set) ++----------------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ +|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | ++----------------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | A2*B2 | 20 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | PCIN+A2*B2 | 20 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN>>17)+A2*B2 | 20 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 1 | +|SharedMulAddRecFNPipe | A2*B2 | 20 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN+A2*B2)' | 20 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 1 | +|SharedMulAddRecFNPipe | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN>>17)+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN+A2*B2)' | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 1 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopMatmulUnroller | A2*B2 | 16 | 16 | - | - | 32 | 1 | 1 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A*B2 | 18 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | (PCIN>>17)+A2*B | 17 | 16 | - | - | 48 | 1 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A2*B2 | 18 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | (PCIN>>17)+A2*B | 17 | 16 | - | - | 48 | 1 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A2*B | 18 | 17 | - | - | 48 | 1 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | (PCIN>>17)+A*B | 17 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A2*B | 18 | 17 | - | - | 48 | 1 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | (PCIN>>17)+A*B | 17 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | C+A*B | 16 | 8 | 24 | - | 24 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 24 | 16 | - | - | 40 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 16 | 16 | - | - | 32 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 18 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | (PCIN>>17)+A*B | 17 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | C+A*B | 16 | 8 | 24 | - | 24 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN+A:B+C | 6 | 18 | 39 | - | -1 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 18 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | (PCIN>>17)+A*B | 23 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | C+A*B | 16 | 8 | 16 | - | 24 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | C+A*B | 24 | 16 | 16 | - | 39 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 18 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | (PCIN>>17)+A*B | 23 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 16 | 16 | - | - | 32 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 16 | 16 | - | - | 32 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 18 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | (PCIN>>17)+A*B | 17 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN+(A:0x0):B+C | 30 | 16 | 37 | - | -1 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 18 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | (PCIN>>17)+A*B | 21 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|StreamReader | (A*B)' | 19 | 6 | - | - | 25 | 0 | 0 | - | - | - | 1 | 0 | +|StreamReader | A*B2 | 10 | 10 | - | - | 20 | 0 | 1 | - | - | - | 0 | 0 | +|MulDiv | A2*B2 | 23 | 6 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | ++----------------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ + +Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once. +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:12:14 ; elapsed = 00:12:49 . Memory (MB): peak = 6506.113 ; gain = 3035.262 ; free physical = 466997 ; free virtual = 607433 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:12:27 ; elapsed = 00:13:02 . Memory (MB): peak = 6506.113 ; gain = 3035.262 ; free physical = 466864 ; free virtual = 607304 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Block RAM: Final Mapping Report ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|GlobalROB__GB1 | robOperands/robOperands_ext/lanes[0].ram_reg | 16 x 128(READ_FIRST) | W | | 16 x 128(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_0 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_1 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_2 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_3 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_4 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_5 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_6 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_7 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|dcache/mshrs | sdq_ext/Memory_reg | 17 x 64(READ_FIRST) | W | | 17 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_0/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_0/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_1/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_1/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_0/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_0/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_1/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_1/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ + + +Distributed RAM: Final Mapping Report ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ +|regfile_ext | bank0_reg | User Attribute | 32 x 65 | RAM32M x 33 | +|regfile_ext | bank1_reg | User Attribute | 32 x 65 | RAM32M x 33 | +|toy_a7_top | total_rows_q/ram_ext/Memory_reg | Implied | 8 x 7 | RAM32M x 2 | +|GemminiExCtrl__GC0 | rdQueue0/ram_data_ext/Memory_reg | Implied | 8 x 64 | RAM32M x 11 | +|GemminiExCtrl__GC0 | rdQueue1/ram_data_ext/Memory_reg | Implied | 8 x 64 | RAM32M x 11 | +|toy_a7_top | ballRs/fifo/ram_ext/Memory_reg | Implied | 4 x 281 | RAM32M x 47 | +|memRs | fifo/ram_ext/Memory_reg | Implied | 4 x 158 | RAM32M x 27 | +|toy_a7_top | bankReadReqQ_q/ram_ext/Memory_reg | Implied | 8 x 21 | RAM32M x 4 | +|toy_a7_top | bankReadReqQ_q_1/ram_ext/Memory_reg | Implied | 8 x 21 | RAM32M x 4 | +|toy_a7_top | completeQueue/ram_ext/Memory_reg | Implied | 16 x 4 | RAM32M x 1 | +|toy_a7_top | subRob/sram/sram_ext/lanes[0].ram_reg | User Attribute | 8 x 1262 | RAM32M x 211 | +|cores_0 | rf_ext/Memory_reg | Implied | 32 x 64 | RAM32M x 22 | +|BBTile__GCB0 | buffer_2/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 117 | RAM32M x 20 | +|BBTile__GCB0 | buffer_2/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 78 | RAM32M x 13 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_tag_array/bbtile_icache_tag_array_ext/lanes[0].ram_reg | User Attribute | 64 x 21 | RAM64X1S x 21 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_tag_array/bbtile_icache_tag_array_ext/lanes[1].ram_reg | User Attribute | 64 x 21 | RAM64X1S x 21 | +|BBTile__GCB1 | buffer_1/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 116 | RAM32M x 20 | +|BBTile__GCB1 | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 116 | RAM32M x 20 | +|BBTile__GCB1 | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 76 | RAM32M x 13 | +|dcache/mshrs | mshrs_0/rpq/ram_ext/Memory_reg | Implied | 16 x 64 | RAM32M x 11 | +|dcache/meta | tag_array/tag_array_ext/lanes[0].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[1].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[2].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[3].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|toy_a7_top | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 189 | RAM32M x 32 | +|toy_a7_top | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 142 | RAM32M x 24 | +|toy_a7_top | buffer/nodeOut_a_q_1/ram_ext/Memory_reg | Implied | 2 x 188 | RAM32M x 32 | +|toy_a7_top | buffer/nodeIn_d_q_1/ram_ext/Memory_reg | Implied | 2 x 142 | RAM32M x 24 | +|toy_a7_top | buffer/nodeIn_b_q/ram_ext/Memory_reg | Implied | 2 x 60 | RAM32M x 10 | +|toy_a7_top | buffer/nodeOut_c_q/ram_ext/Memory_reg | Implied | 2 x 172 | RAM32M x 29 | +|toy_a7_top | buffer/nodeOut_e_q/ram_sink_ext/Memory_reg | Implied | 2 x 1 | RAM16X1D x 1 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_aw_deq_q/ram_ext/Memory_reg | Implied | 2 x 58 | RAM32M x 10 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_w_deq_q/ram_ext/Memory_reg | Implied | 2 x 73 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_b_deq_q/ram_ext/Memory_reg | Implied | 2 x 4 | RAM32M x 1 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_ar_deq_q/ram_ext/Memory_reg | Implied | 2 x 58 | RAM32M x 10 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_r_deq_q/ram_ext/Memory_reg | Implied | 2 x 69 | RAM32M x 12 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_1/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_2/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_3/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_4/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_5/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_0/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_1/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_2/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_3/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|cbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 114 | RAM32M x 19 | +|cbus | wrapped_error_device/buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 100 | RAM32M x 17 | +|cbus | wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 79 | RAM32M x 14 | +|cbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 79 | RAM32M x 14 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_1/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_2/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_3/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_4/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_5/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_6/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_7/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_8/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_9/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_10/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_11/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_12/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_13/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_14/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_15/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_16/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_17/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_18/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_19/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_20/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_21/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_22/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_23/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_24/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_25/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_26/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_27/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_28/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_29/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_30/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_31/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|coh_wrapper | broadcast_1/TLBroadcastTracker/o_data_q/ram_ext/Memory_reg | Implied | 4 x 144 | RAM32M x 24 | +|coh_wrapper | broadcast_1/TLBroadcastTracker_1/o_data_q/ram_ext/Memory_reg | Implied | 4 x 144 | RAM32M x 24 | +|platformi_21/loader | payload_reg | User Attribute | 256 x 8 | RAM128X1D x 16 | +|platformi_21/peripherals | fifo_reg | User Attribute | 256 x 8 | RAM64M x 12 | ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_0/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_0/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_1/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_1/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_2/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_2/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_3/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_3/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_4/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_4/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_5/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_5/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_6/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_6/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_7/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_7/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/mshrs/sdq_ext/Memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_0/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_0/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_1/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_1/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_0/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_0/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_1/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_1/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:12:46 ; elapsed = 00:13:20 . Memory (MB): peak = 6518.039 ; gain = 3047.188 ; free physical = 466890 ; free virtual = 607336 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_0/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_0/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_1/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_1/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_2/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_2/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_3/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_3/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_4/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_4/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_5/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_5/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_6/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_6/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_7/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_7/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/mshrs/sdq_ext/Memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_0/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_0/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_1/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_1/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_0/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_0/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_1/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_1/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/frontend/scheduler/rob/itraceComp of module ITraceDPI__1 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/frontend/scheduler/rob/itraceIssue of module ITraceDPI__2 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/frontend/scheduler/rob/itraceAlloc of module ITraceDPI having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/pmc/pmcTraces_0 of module PMCTraceDPI having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/pmc/ldPmcTrace of module MemPMCTraceDPI__1 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/pmc/stPmcTrace of module MemPMCTraceDPI having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_0 of module MTraceDPI__1 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_1 of module MTraceDPI__2 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_2 of module MTraceDPI__3 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_3 of module MTraceDPI__4 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_4 of module MTraceDPI__5 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_5 of module MTraceDPI__6 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_6 of module MTraceDPI having unconnected or no output ports +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:12:55 ; elapsed = 00:13:30 . Memory (MB): peak = 6518.039 ; gain = 3047.188 ; free physical = 466689 ; free virtual = 607217 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:12:55 ; elapsed = 00:13:30 . Memory (MB): peak = 6518.039 ; gain = 3047.188 ; free physical = 466688 ; free virtual = 607216 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:13:08 ; elapsed = 00:13:43 . Memory (MB): peak = 6518.039 ; gain = 3047.188 ; free physical = 466720 ; free virtual = 607249 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:13:08 ; elapsed = 00:13:43 . Memory (MB): peak = 6518.039 ; gain = 3047.188 ; free physical = 466720 ; free virtual = 607249 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:13:10 ; elapsed = 00:13:45 . Memory (MB): peak = 6518.039 ; gain = 3047.188 ; free physical = 466713 ; free virtual = 607242 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:13:10 ; elapsed = 00:13:45 . Memory (MB): peak = 6518.039 ; gain = 3047.188 ; free physical = 466706 ; free virtual = 607235 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Static Shift Register Report: ++------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ +|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | ++------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/out_matmul_id_RegShifted_0_0_reg[2] | 16 | 3 | NO | NO | YES | 3 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_0_0_reg[19] | 7 | 20 | NO | NO | YES | 20 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_1_6_0_reg[19] | 6 | 20 | NO | NO | YES | 20 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_2_6_0_reg[19] | 5 | 20 | NO | NO | YES | 20 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_3_6_0_reg[19] | 4 | 20 | NO | NO | YES | 20 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_4_6_0_reg[19] | 3 | 20 | NO | NO | YES | 20 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/out_last_RegShifted_0_0_reg | 16 | 1 | NO | NO | YES | 1 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_3_0_reg[7] | 3 | 8 | NO | NO | YES | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_4_0_reg[7] | 4 | 8 | NO | NO | YES | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_5_0_reg[7] | 5 | 8 | NO | NO | YES | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_6_0_reg[7] | 6 | 8 | NO | NO | YES | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_7_0_reg[7] | 7 | 8 | NO | NO | YES | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_3_1_0_reg[7] | 3 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_4_1_0_reg[7] | 4 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_5_1_0_reg[7] | 5 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_6_1_0_reg[7] | 6 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_7_1_0_reg[7] | 7 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_3_2_0_reg[7] | 3 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_4_2_0_reg[7] | 4 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_5_2_0_reg[7] | 5 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_6_2_0_reg[7] | 6 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_7_2_0_reg[7] | 7 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/ibus_intsink/chain/output_chain/sync_0_reg | 3 | 1 | NO | NO | YES | 1 | 0 | ++------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +DSP Final Report (the ' indicates corresponding REG is set) ++----------------------+--------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ +|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | ++----------------------+--------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ +|LoopConvAddrGen | C'+A'*B'' | 16 | 8 | 24 | - | 24 | 1 | 2 | 2 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 24 | 16 | - | - | 40 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A'*B'' | 16 | 16 | - | - | 32 | 1 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN>>17+A''*B | 16 | 15 | - | - | 48 | 2 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | C'+A'*B'' | 16 | 8 | 24 | - | 24 | 1 | 2 | 2 | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN+A:B+C | 6 | 18 | - | - | 39 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN>>17+A*B'' | 22 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | C'+A'*B'' | 16 | 8 | 16 | - | 24 | 1 | 2 | 2 | - | - | 0 | 0 | +|LoopConvAddrGen | C'+A*B'' | 24 | 16 | 16 | - | 39 | 0 | 2 | 2 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN>>17+A*B'' | 22 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A'*B'' | 16 | 16 | - | - | 32 | 1 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A'*B'' | 16 | 16 | - | - | 32 | 1 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN>>17+A''*B | 16 | 15 | - | - | 48 | 2 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN+A:B'+C | 0 | 16 | - | - | 37 | 0 | 1 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN>>17+A*B'' | 20 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|FpgaDspMac | C+A'*B | 30 | 18 | 48 | - | 20 | 1 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|LoopMatmulUnroller | A''*B'' | 16 | 16 | - | - | 32 | 2 | 2 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | PCIN>>17+A''*B | 16 | 15 | - | - | 48 | 2 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A''*B' | 17 | 16 | - | - | 48 | 2 | 1 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | PCIN>>17+A'*B'' | 16 | 15 | - | - | 48 | 1 | 2 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A''*B | 17 | 16 | - | - | 48 | 2 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | PCIN>>17+A*B'' | 16 | 15 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A''*B | 17 | 16 | - | - | 48 | 2 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | PCIN>>17+A*B'' | 16 | 15 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|StreamReader | (A*B')' | 19 | 4 | - | - | 25 | 0 | 1 | - | - | - | 0 | 1 | +|StreamReader | A*B' | 10 | 10 | - | - | 20 | 0 | 1 | - | - | - | 0 | 0 | +|MulDiv | A'*B' | 22 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A'*B' | 17 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A'*B' | 22 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN>>17+A'*B' | 22 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A'*B' | 17 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN>>17+A'*B' | 22 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN>>17+A'*B' | 17 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN>>17+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | A'*B' | 19 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | PCIN+A'*B'' | 19 | 17 | - | - | 48 | 1 | 2 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN>>17+A'*B'')' | 19 | 17 | - | - | 48 | 1 | 2 | - | - | - | 0 | 1 | +|SharedMulAddRecFNPipe | A'*B' | 19 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | PCIN+A'*B'' | 17 | 17 | - | - | 0 | 1 | 2 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN+A'*B'')' | 19 | 17 | - | - | 48 | 1 | 2 | - | - | - | 0 | 1 | +|SharedMulAddRecFNPipe | A'*B'' | 17 | 17 | - | - | 48 | 1 | 2 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | PCIN>>17+A'*B'' | 17 | 17 | - | - | 0 | 1 | 2 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN+A'*B'')' | 17 | 17 | - | - | 48 | 1 | 2 | - | - | - | 0 | 1 | ++----------------------+--------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ + + +Report BlackBoxes: ++------+--------------+----------+ +| |BlackBox name |Instances | ++------+--------------+----------+ +|1 |toy_axi_cdc | 1| +|2 |arty_ddr3 | 1| ++------+--------------+----------+ + +Report Cell Usage: ++------+------------+------+ +| |Cell |Count | ++------+------------+------+ +|1 |arty_ddr3 | 1| +|2 |toy_axi_cdc | 1| +|3 |BUFG | 4| +|4 |CARRY4 | 1950| +|5 |DSP48E1 | 117| +|18 |LUT1 | 817| +|19 |LUT2 | 4360| +|20 |LUT3 | 12197| +|21 |LUT4 | 10130| +|22 |LUT5 | 12422| +|23 |LUT6 | 18450| +|24 |MMCME2_BASE | 1| +|25 |MUXF7 | 629| +|26 |MUXF8 | 112| +|27 |RAM128X1D | 16| +|28 |RAM16X1D | 1| +|29 |RAM32M | 665| +|30 |RAM32X1D | 21| +|31 |RAM32X1S | 92| +|32 |RAM64M | 12| +|33 |RAM64X1S | 42| +|34 |RAMB18E1 | 8| +|35 |RAMB36E1 | 27| +|38 |SRL16E | 225| +|39 |FDCE | 8| +|40 |FDPE | 6| +|41 |FDRE | 28184| +|42 |FDSE | 457| +|43 |IBUF | 4| +|44 |OBUF | 9| ++------+------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:13:10 ; elapsed = 00:13:45 . Memory (MB): peak = 6518.039 ; gain = 3047.188 ; free physical = 466706 ; free virtual = 607235 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 571 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:12:56 ; elapsed = 00:13:37 . Memory (MB): peak = 6518.039 ; gain = 2875.582 ; free physical = 474549 ; free virtual = 615080 +Synthesis Optimization Complete : Time (s): cpu = 00:13:13 ; elapsed = 00:13:48 . Memory (MB): peak = 6518.039 ; gain = 3047.188 ; free physical = 474565 ; free virtual = 615078 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Project 1-454] Reading design checkpoint '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc.dcp' for cell 'memory_cdc' +INFO: [Project 1-454] Reading design checkpoint '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3.dcp' for cell 'ddr_controller' +Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 6518.039 ; gain = 0.000 ; free physical = 474568 ; free virtual = 615080 +INFO: [Netlist 29-17] Analyzing 4089 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2024.1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] for cell 'ddr_controller' +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] for cell 'ddr_controller' +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/arty_a7.xdc] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/arty_a7.xdc] +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/flash_boot.xdc] +CRITICAL WARNING: [Designutils 20-1307] Command 'if' is not supported in the xdc constraint file. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/flash_boot.xdc:11] +CRITICAL WARNING: [Designutils 20-1307] Command 'if' is not supported in the xdc constraint file. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/flash_boot.xdc:15] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/flash_boot.xdc] +INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3.dcp' +INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc.dcp' +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc] for cell 'memory_cdc/inst' +INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:16] +INFO: [Timing 38-2] Deriving generated clocks [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:16] +all_fanout: Time (s): cpu = 00:00:14 ; elapsed = 00:00:06 . Memory (MB): peak = 6518.039 ; gain = 0.000 ; free physical = 474581 ; free virtual = 615093 +WARNING: [Vivado_Tcl 4-2057] Waiver ID 'LUTAR-1' object list specifies likely unusable hierarchical instance 'memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:30] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:35] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:39] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:42] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:45] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:49] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:52] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:56] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:60] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:63] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:66] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:70] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc] for cell 'memory_cdc/inst' +INFO: [Project 1-1714] 33 XPM XDC files have been applied to the design. +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-1687] 16 scoped IP constraints or related sub-commands were skipped due to synthesis logic optimizations usually triggered by constant connectivity or unconnected output pins. To review the skipped constraints and messages, run the command 'set_param netlist.IPMsgFiltering false' before opening the design. +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 6518.039 ; gain = 0.000 ; free physical = 474560 ; free virtual = 615073 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 1054 instances were transformed. + IOBUFDS_INTERMDISABLE => IOBUFDS_INTERMDISABLE (IBUFDS_INTERMDISABLE_INT(x2), INV, OBUFTDS(x2)): 2 instances + IOBUF_INTERMDISABLE => IOBUF_INTERMDISABLE (IBUF_INTERMDISABLE, OBUFT): 16 instances + MMCME2_BASE => MMCME2_ADV: 1 instance + OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 1 instance + RAM128X1D => RAM128X1D (MUXF7(x2), RAMD64E(x4)): 16 instances + RAM16X1D => RAM32X1D (RAMD32(x2)): 1 instance + RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 845 instances + RAM32X1D => RAM32X1D (RAMD32(x2)): 26 instances + RAM32X1S => RAM32X1S (RAMS32): 92 instances + RAM64M => RAM64M (RAMD64E(x4)): 12 instances + RAM64X1S => RAM64X1S (RAMS64E): 42 instances + +Synth Design complete | Checksum: 2dfdb574 +INFO: [Common 17-83] Releasing license: Synthesis +608 Infos, 466 Warnings, 4 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:13:44 ; elapsed = 00:14:10 . Memory (MB): peak = 6518.039 ; gain = 3047.309 ; free physical = 474561 ; free virtual = 615074 +INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 13700.579; main = 5845.433; forked = 8252.530 +INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 19180.555; main = 6514.125; forked = 12666.434 +# write_checkpoint -force $out/synthesized.dcp +INFO: [Timing 38-480] Writing timing data to binary archive. +Wrote PlaceDB: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6538.129 ; gain = 0.000 ; free physical = 474561 ; free virtual = 615074 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6538.129 ; gain = 0.000 ; free physical = 474561 ; free virtual = 615074 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.02 . Memory (MB): peak = 6538.129 ; gain = 0.000 ; free physical = 474561 ; free virtual = 615074 +Wrote Netlist Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 6538.129 ; gain = 0.000 ; free physical = 474561 ; free virtual = 615074 +Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 6538.129 ; gain = 0.000 ; free physical = 474560 ; free virtual = 615074 +Write Physdb Complete: Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.03 . Memory (MB): peak = 6538.129 ; gain = 0.000 ; free physical = 474560 ; free virtual = 615074 +Write ShapeDB Complete: Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.09 . Memory (MB): peak = 6538.129 ; gain = 0.000 ; free physical = 474553 ; free virtual = 615074 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/synthesized.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 6538.129 ; gain = 20.090 ; free physical = 474489 ; free virtual = 615068 +# report_utilization -file $out/synth-utilization.rpt +# report_utilization -hierarchical -file $out/synth-hierarchy.rpt +# report_timing_summary -delay_type min_max -file $out/synth-timing.rpt +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. +report_timing_summary: Time (s): cpu = 00:00:20 ; elapsed = 00:00:06 . Memory (MB): peak = 6538.129 ; gain = 0.000 ; free physical = 474378 ; free virtual = 614957 +# set unresolved [get_cells -hier -quiet -filter {IS_BLACKBOX == 1}] +# if {[llength $unresolved]} {error "Unresolved black boxes: $unresolved"} +# phase OPTIMIZE +BOARD_PHASE OPTIMIZE +# opt_design -directive ExploreArea +Command: opt_design -directive ExploreArea +INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: ExploreArea +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 8 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.74 . Memory (MB): peak = 6570.145 ; gain = 32.016 ; free physical = 474363 ; free virtual = 614942 + +Starting Logic Optimization Task + +Phase 1 Initialization + +Phase 1.1 Core Generation And Design Setup +Phase 1.1 Core Generation And Design Setup | Checksum: 24b21dee2 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 474154 ; free virtual = 614733 + +Phase 1.2 Setup Constraints And Sort Netlist +Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 24b21dee2 + +Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 474146 ; free virtual = 614725 +Phase 1 Initialization | Checksum: 24b21dee2 + +Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.05 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 474146 ; free virtual = 614725 + +Phase 2 Timer Update And Timing Data Collection + +Phase 2.1 Timer Update +Phase 2.1 Timer Update | Checksum: 24b21dee2 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 473991 ; free virtual = 614570 + +Phase 2.2 Timing Data Collection +Phase 2.2 Timing Data Collection | Checksum: 24b21dee2 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 473983 ; free virtual = 614562 +Phase 2 Timer Update And Timing Data Collection | Checksum: 24b21dee2 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 473983 ; free virtual = 614562 + +Phase 3 Retarget +INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0 +INFO: [Opt 31-1566] Pulled 311 inverters resulting in an inversion of 2868 pins +INFO: [Opt 31-138] Pushed 8 inverter(s) to 9 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 3 Retarget | Checksum: 21a22d777 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 473922 ; free virtual = 614502 +Retarget | Checksum: 21a22d777 +INFO: [Opt 31-389] Phase Retarget created 97 cells and removed 603 cells +INFO: [Opt 31-1021] In phase Retarget, 52 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 4 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 4 Constant propagation | Checksum: 2d2bd90bb + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 473896 ; free virtual = 614496 +Constant propagation | Checksum: 2d2bd90bb +INFO: [Opt 31-389] Phase Constant propagation created 12 cells and removed 19 cells +INFO: [Opt 31-1021] In phase Constant propagation, 30 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 5 Sweep +Phase 5 Sweep | Checksum: 2d6232e06 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 473899 ; free virtual = 614500 +Sweep | Checksum: 2d6232e06 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 333 cells +INFO: [Opt 31-1021] In phase Sweep, 150 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 6 BUFG optimization +Phase 6 BUFG optimization | Checksum: 264ce99c3 + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 473900 ; free virtual = 614501 +BUFG optimization | Checksum: 264ce99c3 +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. + +Phase 7 Shift Register Optimization +INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs +Phase 7 Shift Register Optimization | Checksum: 264ce99c3 + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 473900 ; free virtual = 614500 +Shift Register Optimization | Checksum: 264ce99c3 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells +INFO: [Opt 31-1555] control_set_opt supports Versal devices only, and device 7a100t is unsupported + +Phase 8 Resynthesis +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Opt 31-74] Optimized 105 modules. +INFO: [Opt 31-75] Optimized module 'AccPipe'. +INFO: [Opt 31-75] Optimized module 'AccPipe_11'. +INFO: [Opt 31-75] Optimized module 'AccPipe_12'. +INFO: [Opt 31-75] Optimized module 'AccPipe_13'. +INFO: [Opt 31-75] Optimized module 'AccPipe_14'. +INFO: [Opt 31-75] Optimized module 'AccPipe_15'. +INFO: [Opt 31-75] Optimized module 'AccPipe_16'. +INFO: [Opt 31-75] Optimized module 'BankScoreboard'. +INFO: [Opt 31-75] Optimized module 'DTLB'. +INFO: [Opt 31-75] Optimized module 'DivSqrtRawFN_small_e8_s24'. +INFO: [Opt 31-75] Optimized module 'FPToInt'. +INFO: [Opt 31-75] Optimized module 'GemminiExCtrl'. +INFO: [Opt 31-75] Optimized module 'IBuf'. +INFO: [Opt 31-75] Optimized module 'ICache'. +INFO: [Opt 31-75] Optimized module 'ITLB'. +INFO: [Opt 31-75] Optimized module 'LoopConvUnroller'. +INFO: [Opt 31-75] Optimized module 'MaxPeriodFibonacciLFSR_3'. +INFO: [Opt 31-75] Optimized module 'MemConfiger'. +INFO: [Opt 31-75] Optimized module 'MemMidend'. +INFO: [Opt 31-75] Optimized module 'MeshWithDelays'. +INFO: [Opt 31-75] Optimized module 'NonBlockingDCache'. +INFO: [Opt 31-75] Optimized module 'PE_64_186'. +INFO: [Opt 31-75] Optimized module 'PE_64_189'. +INFO: [Opt 31-75] Optimized module 'PE_64_192'. +INFO: [Opt 31-75] Optimized module 'PE_64_195'. +INFO: [Opt 31-75] Optimized module 'PE_64_198'. +INFO: [Opt 31-75] Optimized module 'PE_64_201'. +INFO: [Opt 31-75] Optimized module 'PE_64_204'. +INFO: [Opt 31-75] Optimized module 'PE_64_207'. +INFO: [Opt 31-75] Optimized module 'PE_64_210'. +INFO: [Opt 31-75] Optimized module 'PE_64_213'. +INFO: [Opt 31-75] Optimized module 'PE_64_216'. +INFO: [Opt 31-75] Optimized module 'PE_64_219'. +INFO: [Opt 31-75] Optimized module 'PE_64_222'. +INFO: [Opt 31-75] Optimized module 'PE_64_225'. +INFO: [Opt 31-75] Optimized module 'PE_64_228'. +INFO: [Opt 31-75] Optimized module 'PE_64_231'. +INFO: [Opt 31-75] Optimized module 'PE_64_234'. +INFO: [Opt 31-75] Optimized module 'PE_64_237'. +INFO: [Opt 31-75] Optimized module 'PE_64_240'. +INFO: [Opt 31-75] Optimized module 'PE_64_243'. +INFO: [Opt 31-75] Optimized module 'PE_64_246'. +INFO: [Opt 31-75] Optimized module 'PE_64_249'. +INFO: [Opt 31-75] Optimized module 'PE_64_252'. +INFO: [Opt 31-75] Optimized module 'PE_64_255'. +INFO: [Opt 31-75] Optimized module 'PE_64_258'. +INFO: [Opt 31-75] Optimized module 'PE_64_261'. +INFO: [Opt 31-75] Optimized module 'PE_64_264'. +INFO: [Opt 31-75] Optimized module 'PE_64_267'. +INFO: [Opt 31-75] Optimized module 'PE_64_270'. +INFO: [Opt 31-75] Optimized module 'PE_64_273'. +INFO: [Opt 31-75] Optimized module 'PE_64_276'. +INFO: [Opt 31-75] Optimized module 'PE_64_279'. +INFO: [Opt 31-75] Optimized module 'PE_64_282'. +INFO: [Opt 31-75] Optimized module 'PE_64_285'. +INFO: [Opt 31-75] Optimized module 'PE_64_288'. +INFO: [Opt 31-75] Optimized module 'PE_64_291'. +INFO: [Opt 31-75] Optimized module 'PE_64_294'. +INFO: [Opt 31-75] Optimized module 'PE_64_297'. +INFO: [Opt 31-75] Optimized module 'PE_64_300'. +INFO: [Opt 31-75] Optimized module 'PE_64_303'. +INFO: [Opt 31-75] Optimized module 'PE_64_306'. +INFO: [Opt 31-75] Optimized module 'PE_64_309'. +INFO: [Opt 31-75] Optimized module 'PE_64_312'. +INFO: [Opt 31-75] Optimized module 'PE_64_315'. +INFO: [Opt 31-75] Optimized module 'PE_64_318'. +INFO: [Opt 31-75] Optimized module 'PE_64_321'. +INFO: [Opt 31-75] Optimized module 'PE_64_324'. +INFO: [Opt 31-75] Optimized module 'PE_64_327'. +INFO: [Opt 31-75] Optimized module 'PE_64_330'. +INFO: [Opt 31-75] Optimized module 'PE_64_333'. +INFO: [Opt 31-75] Optimized module 'PE_64_336'. +INFO: [Opt 31-75] Optimized module 'PE_64_339'. +INFO: [Opt 31-75] Optimized module 'PE_64_342'. +INFO: [Opt 31-75] Optimized module 'PE_64_345'. +INFO: [Opt 31-75] Optimized module 'PE_64_348'. +INFO: [Opt 31-75] Optimized module 'PE_64_351'. +INFO: [Opt 31-75] Optimized module 'PE_64_354'. +INFO: [Opt 31-75] Optimized module 'Queue16_ReplayInternal'. +INFO: [Opt 31-75] Optimized module 'Queue1_RegMapperInput_i23_m8'. +INFO: [Opt 31-75] Optimized module 'Queue4_TLBroadcastData'. +INFO: [Opt 31-75] Optimized module 'Queue8_SramReadResp_39'. +INFO: [Opt 31-75] Optimized module 'Repeater_TLBundleA_a17d64s3k1z3u'. +INFO: [Opt 31-75] Optimized module 'ShiftQueue'. +INFO: [Opt 31-75] Optimized module 'SubROB'. +INFO: [Opt 31-75] Optimized module 'TLB'. +INFO: [Opt 31-75] Optimized module 'TLXbar_sbus_i2_o3_a32d128s3k1z4c'. +INFO: [Opt 31-75] Optimized module 'TagQueue'. +INFO: [Opt 31-75] Optimized module 'WritebackUnit'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_axi_mc_wr_cmd_fsm'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_bank_state__parameterized2'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_ddr_if_post_fifo'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_ddr_phy_rdlvl'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_ddr_phy_wrcal'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_rank_common'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_round_robin_arb'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_tempmon'. +INFO: [Opt 31-75] Optimized module 'axi_fullwidth'. +INFO: [Opt 31-75] Optimized module 'ram_2x58'. +INFO: [Opt 31-75] Optimized module 'ram_2x58_376'. +INFO: [Common 17-14] Message 'Opt 31-75' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Opt 31-1566] Pulled 2280 inverters resulting in an inversion of 7908 pins +INFO: [Opt 31-138] Pushed 4 inverter(s) to 19 load pin(s). +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 8 Resynthesis | Checksum: 23ff3679c + +Time (s): cpu = 00:02:41 ; elapsed = 00:00:53 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 472072 ; free virtual = 612675 +Resynthesis | Checksum: 23ff3679c +INFO: [Opt 31-389] Phase Resynthesis created 19062 cells and removed 19811 cells +INFO: [Opt 31-1021] In phase Resynthesis, 151 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 9 Post Processing Netlist +Phase 9 Post Processing Netlist | Checksum: 23ff3679c + +Time (s): cpu = 00:02:41 ; elapsed = 00:00:53 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 472074 ; free virtual = 612678 +Post Processing Netlist | Checksum: 23ff3679c +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells +INFO: [Opt 31-1021] In phase Post Processing Netlist, 45 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 10 Finalization + +Phase 10.1 Finalizing Design Cores and Updating Shapes +Phase 10.1 Finalizing Design Cores and Updating Shapes | Checksum: 1a072e151 + +Time (s): cpu = 00:02:42 ; elapsed = 00:00:54 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 472083 ; free virtual = 612686 + +Phase 10.2 Verifying Netlist Connectivity + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.12 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 471942 ; free virtual = 612545 +Phase 10.2 Verifying Netlist Connectivity | Checksum: 1a072e151 + +Time (s): cpu = 00:02:42 ; elapsed = 00:00:54 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 471934 ; free virtual = 612537 +Phase 10 Finalization | Checksum: 1a072e151 + +Time (s): cpu = 00:02:42 ; elapsed = 00:00:54 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 471926 ; free virtual = 612529 +Opt_design Change Summary +========================= + + +------------------------------------------------------------------------------------------------------------------------- +| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | +------------------------------------------------------------------------------------------------------------------------- +| Retarget | 97 | 603 | 52 | +| Constant propagation | 12 | 19 | 30 | +| Sweep | 0 | 333 | 150 | +| BUFG optimization | 0 | 0 | 0 | +| Shift Register Optimization | 0 | 0 | 0 | +| Resynthesis | 19062 | 19811 | 151 | +| Post Processing Netlist | 0 | 0 | 45 | +------------------------------------------------------------------------------------------------------------------------- + + +Ending Logic Optimization Task | Checksum: 1a072e151 + +Time (s): cpu = 00:02:42 ; elapsed = 00:00:54 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 471926 ; free virtual = 612529 + +Starting Netlist Obfuscation Task +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 471723 ; free virtual = 612326 +Ending Netlist Obfuscation Task | Checksum: 1a072e151 + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 471715 ; free virtual = 612318 +INFO: [Common 17-83] Releasing license: Implementation +131 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:02:46 ; elapsed = 00:00:56 . Memory (MB): peak = 6570.145 ; gain = 32.016 ; free physical = 471661 ; free virtual = 612265 +# write_checkpoint -force $out/optimized.dcp +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-480] Writing timing data to binary archive. +Wrote PlaceDB: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470083 ; free virtual = 610686 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470083 ; free virtual = 610686 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.02 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470082 ; free virtual = 610686 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470082 ; free virtual = 610686 +Wrote Device Cache: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470082 ; free virtual = 610687 +Write Physdb Complete: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.03 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470081 ; free virtual = 610686 +Write ShapeDB Complete: Time (s): cpu = 00:00:00.43 ; elapsed = 00:00:00.11 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470074 ; free virtual = 610689 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/optimized.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:19 ; elapsed = 00:00:12 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470006 ; free virtual = 610681 +# report_utilization -file $out/opt-utilization.rpt +# phase PLACE +BOARD_PHASE PLACE +# place_design -directive Explore +Command: place_design -directive Explore +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-83] Releasing license: Implementation +INFO: [DRC 23-27] Running DRC with 8 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +INFO: [Vivado_Tcl 4-2302] The placer was invoked with the 'Explore' directive. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 8 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs + +Starting Placer Task + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470014 ; free virtual = 610691 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 14f5d1a2b + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470014 ; free virtual = 610691 +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470013 ; free virtual = 610690 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 17dfc4ae4 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470042 ; free virtual = 610722 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 189c2ca53 + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:12 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 470095 ; free virtual = 610790 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 189c2ca53 + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:12 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 470095 ; free virtual = 610790 +Phase 1 Placer Initialization | Checksum: 189c2ca53 + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:12 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 470095 ; free virtual = 610791 + +Phase 2 Global Placement + +Phase 2.1 Floorplanning +Phase 2.1 Floorplanning | Checksum: 20bb1dab5 + +Time (s): cpu = 00:00:34 ; elapsed = 00:00:14 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 470120 ; free virtual = 610816 + +Phase 2.2 Update Timing before SLR Path Opt +Phase 2.2 Update Timing before SLR Path Opt | Checksum: 2286fe973 + +Time (s): cpu = 00:00:40 ; elapsed = 00:00:17 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 470140 ; free virtual = 610839 + +Phase 2.3 Post-Processing in Floorplanning +Phase 2.3 Post-Processing in Floorplanning | Checksum: 2286fe973 + +Time (s): cpu = 00:00:41 ; elapsed = 00:00:17 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 470127 ; free virtual = 610826 + +Phase 2.4 Global Placement Core + +Phase 2.4.1 UpdateTiming Before Physical Synthesis +Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 1a630b68c + +Time (s): cpu = 00:02:11 ; elapsed = 00:00:50 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 470167 ; free virtual = 610887 + +Phase 2.4.2 Physical Synthesis In Placer +INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 5152 LUT instances to create LUTNM shape +INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0 +INFO: [Physopt 32-1138] End 1 Pass. Optimized 2204 nets or LUTs. Breaked 0 LUT, combined 2204 existing LUTs and moved 0 existing LUT +INFO: [Physopt 32-65] No nets found for high-fanout optimization. +INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. +INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed. +INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. +INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. +INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed. +INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 470052 ; free virtual = 610865 + +Summary of Physical Synthesis Optimizations +============================================ + + +----------------------------------------------------------------------------------------------------------------------------------------------------------- +| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | +----------------------------------------------------------------------------------------------------------------------------------------------------------- +| LUT Combining | 0 | 2204 | 2204 | 0 | 1 | 00:00:02 | +| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Total | 0 | 2204 | 2204 | 0 | 4 | 00:00:02 | +----------------------------------------------------------------------------------------------------------------------------------------------------------- + + +Phase 2.4.2 Physical Synthesis In Placer | Checksum: 2a3298b58 + +Time (s): cpu = 00:02:21 ; elapsed = 00:00:55 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 469384 ; free virtual = 610551 +Phase 2.4 Global Placement Core | Checksum: 28e960a12 + +Time (s): cpu = 00:02:34 ; elapsed = 00:01:00 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 469678 ; free virtual = 610874 +Phase 2 Global Placement | Checksum: 28e960a12 + +Time (s): cpu = 00:02:34 ; elapsed = 00:01:01 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 469678 ; free virtual = 610874 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 2ba6ea6d8 + +Time (s): cpu = 00:02:41 ; elapsed = 00:01:03 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 469681 ; free virtual = 610876 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 2733bb972 + +Time (s): cpu = 00:02:53 ; elapsed = 00:01:07 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 469671 ; free virtual = 610867 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 27d09f09c + +Time (s): cpu = 00:02:54 ; elapsed = 00:01:08 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 469668 ; free virtual = 610864 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 280076c81 + +Time (s): cpu = 00:02:54 ; elapsed = 00:01:08 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 469675 ; free virtual = 610871 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 274e2b06e + +Time (s): cpu = 00:03:15 ; elapsed = 00:01:28 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 465571 ; free virtual = 607195 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 2462932d4 + +Time (s): cpu = 00:03:17 ; elapsed = 00:01:30 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 465456 ; free virtual = 607080 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 3265b2010 + +Time (s): cpu = 00:03:17 ; elapsed = 00:01:30 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 465404 ; free virtual = 607046 +Phase 3 Detail Placement | Checksum: 3265b2010 + +Time (s): cpu = 00:03:18 ; elapsed = 00:01:31 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 465246 ; free virtual = 606904 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Phase 4.1.1 Post Placement Optimization +Post Placement Optimization Initialization | Checksum: 260892d3c + +Phase 4.1.1.1 BUFG Insertion + +Starting Physical Synthesis Task + +Phase 1 Physical Synthesis Initialization +INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=1.277 | TNS=0.000 | +Phase 1 Physical Synthesis Initialization | Checksum: 1113813e2 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 459558 ; free virtual = 602864 +INFO: [Place 46-33] Processed net platform/loader/SR[0], BUFG insertion was skipped due to placement/routing conflicts. +INFO: [Place 46-56] BUFG insertion identified 1 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 1, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. +Ending Physical Synthesis Task | Checksum: 1f7ac6828 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 455937 ; free virtual = 600446 +Phase 4.1.1.1 BUFG Insertion | Checksum: 260892d3c + +Time (s): cpu = 00:03:51 ; elapsed = 00:01:43 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 454364 ; free virtual = 599397 + +Phase 4.1.1.2 Post Placement Timing Optimization +INFO: [Place 30-746] Post Placement Timing Summary WNS=1.277. For the most accurate timing information please run report_timing. +Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 29d6b1f6b + +Time (s): cpu = 00:03:53 ; elapsed = 00:01:44 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 452011 ; free virtual = 597821 + +Time (s): cpu = 00:03:53 ; elapsed = 00:01:44 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 452010 ; free virtual = 597821 +Phase 4.1 Post Commit Optimization | Checksum: 29d6b1f6b + +Time (s): cpu = 00:03:53 ; elapsed = 00:01:44 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 450421 ; free virtual = 596761 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 29d6b1f6b + +Time (s): cpu = 00:03:54 ; elapsed = 00:01:45 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 448028 ; free virtual = 595156 + +Phase 4.3 Placer Reporting + +Phase 4.3.1 Print Estimated Congestion +INFO: [Place 30-612] Post-Placement Estimated Congestion + ____________________________________________________ +| | Global Congestion | Short Congestion | +| Direction | Region Size | Region Size | +|___________|___________________|___________________| +| North| 1x1| 8x8| +|___________|___________________|___________________| +| South| 2x2| 8x8| +|___________|___________________|___________________| +| East| 2x2| 8x8| +|___________|___________________|___________________| +| West| 1x1| 2x2| +|___________|___________________|___________________| + +Phase 4.3.1 Print Estimated Congestion | Checksum: 29d6b1f6b + +Time (s): cpu = 00:03:55 ; elapsed = 00:01:45 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 446097 ; free virtual = 593864 +Phase 4.3 Placer Reporting | Checksum: 29d6b1f6b + +Time (s): cpu = 00:03:55 ; elapsed = 00:01:46 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 444507 ; free virtual = 592800 + +Phase 4.4 Final Placement Cleanup +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 444337 ; free virtual = 592687 + +Time (s): cpu = 00:03:55 ; elapsed = 00:01:46 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 444336 ; free virtual = 592686 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 2e4b25a14 + +Time (s): cpu = 00:03:55 ; elapsed = 00:01:46 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 442564 ; free virtual = 591473 +Ending Placer Task | Checksum: 1eddddbab + +Time (s): cpu = 00:03:56 ; elapsed = 00:01:46 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 441290 ; free virtual = 590627 +30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +place_design: Time (s): cpu = 00:04:00 ; elapsed = 00:01:48 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 440996 ; free virtual = 590428 +# write_checkpoint -force $out/placed.dcp +INFO: [Timing 38-480] Writing timing data to binary archive. +Write ShapeDB Complete: Time (s): cpu = 00:00:00.75 ; elapsed = 00:00:00.16 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 440814 ; free virtual = 590264 +Wrote PlaceDB: Time (s): cpu = 00:00:09 ; elapsed = 00:00:03 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 451981 ; free virtual = 601581 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 451981 ; free virtual = 601581 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 452075 ; free virtual = 601675 +Wrote Netlist Cache: Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.1 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 452552 ; free virtual = 602161 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 452552 ; free virtual = 602161 +Write Physdb Complete: Time (s): cpu = 00:00:09 ; elapsed = 00:00:03 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 452552 ; free virtual = 602161 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/placed.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:16 ; elapsed = 00:00:11 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 453042 ; free virtual = 603197 +# phase PHYS_OPT +BOARD_PHASE PHYS_OPT +# phys_opt_design -directive Explore +Command: phys_opt_design -directive Explore +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: Explore + +Starting Initial Update Timing Task + +Time (s): cpu = 00:00:19 ; elapsed = 00:00:06 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 441326 ; free virtual = 602523 +INFO: [Vivado_Tcl 4-2279] Estimated Timing Summary | WNS= 1.277 | TNS= 0.000 | +INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. All physical synthesis setup optimizations will be skipped. +INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified. +INFO: [Common 17-83] Releasing license: Implementation +6 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +phys_opt_design completed successfully +phys_opt_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:06 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 441326 ; free virtual = 602523 +# phase ROUTE +BOARD_PHASE ROUTE +# route_design -directive Explore +Command: route_design -directive Explore +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 8 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-270] Using Router directive 'Explore'. +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs + +Phase 1 Build RT Design +Checksum: PlaceDB: ee9480ea ConstDB: 0 ShapeSum: 4d76fb2b RouteDB: b1d25f96 +Post Restoration Checksum: NetGraph: 3122703f | NumContArr: 80923bb4 | Constraints: c2a8fa9d | Timing: c2a8fa9d +Phase 1 Build RT Design | Checksum: 23706a12d + +Time (s): cpu = 00:00:33 ; elapsed = 00:00:14 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 434318 ; free virtual = 603900 + +Phase 2 Router Initialization + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 23706a12d + +Time (s): cpu = 00:00:34 ; elapsed = 00:00:15 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 434125 ; free virtual = 603900 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 23706a12d + +Time (s): cpu = 00:00:35 ; elapsed = 00:00:15 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 434083 ; free virtual = 603902 + Number of Nodes with overlaps = 0 + +Phase 2.3 Update Timing +Phase 2.3 Update Timing | Checksum: 2919fd49e + +Time (s): cpu = 00:01:07 ; elapsed = 00:00:24 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 429576 ; free virtual = 603961 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.274 | TNS=0.000 | WHS=-1.411 | THS=-707.945| + + +Phase 2.4 Update Timing for Bus Skew + +Phase 2.4.1 Update Timing +Phase 2.4.1 Update Timing | Checksum: 24d0d505a + +Time (s): cpu = 00:01:30 ; elapsed = 00:00:30 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 426124 ; free virtual = 603406 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.274 | TNS=0.000 | WHS=-2.372 | THS=-68.356| + +Phase 2.4 Update Timing for Bus Skew | Checksum: 25d8558af + +Time (s): cpu = 00:01:30 ; elapsed = 00:00:30 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 426009 ; free virtual = 603350 + +Router Utilization Summary + Global Vertical Routing Utilization = 0 % + Global Horizontal Routing Utilization = 0 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 93600 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 93600 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Phase 2 Router Initialization | Checksum: 30f73531b + +Time (s): cpu = 00:01:32 ; elapsed = 00:00:31 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 425562 ; free virtual = 603128 + +Phase 3 Global Routing +Phase 3 Global Routing | Checksum: 30f73531b + +Time (s): cpu = 00:01:32 ; elapsed = 00:00:31 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 425546 ; free virtual = 603120 + +Phase 4 Initial Routing + +Phase 4.1 Initial Net Routing Pass +Phase 4.1 Initial Net Routing Pass | Checksum: 373819a83 + +Time (s): cpu = 00:01:47 ; elapsed = 00:00:34 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424373 ; free virtual = 603481 +Phase 4 Initial Routing | Checksum: 373819a83 + +Time (s): cpu = 00:01:48 ; elapsed = 00:00:34 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424370 ; free virtual = 603478 + +Phase 5 Rip-up And Reroute + +Phase 5.1 Global Iteration 0 + Number of Nodes with overlaps = 14547 + Number of Nodes with overlaps = 1474 + Number of Nodes with overlaps = 372 + Number of Nodes with overlaps = 120 + Number of Nodes with overlaps = 28 + Number of Nodes with overlaps = 9 + Number of Nodes with overlaps = 4 + Number of Nodes with overlaps = 2 + Number of Nodes with overlaps = 4 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 0 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.274 | TNS=0.000 | WHS=N/A | THS=N/A | + +Phase 5.1 Global Iteration 0 | Checksum: 22ddfe875 + +Time (s): cpu = 00:03:05 ; elapsed = 00:01:18 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424370 ; free virtual = 603561 + +Phase 5.2 Global Iteration 1 + Number of Nodes with overlaps = 6 + Number of Nodes with overlaps = 18 + Number of Nodes with overlaps = 35 + Number of Nodes with overlaps = 9 + Number of Nodes with overlaps = 4 + Number of Nodes with overlaps = 3 + Number of Nodes with overlaps = 2 + Number of Nodes with overlaps = 0 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.274 | TNS=0.000 | WHS=N/A | THS=N/A | + +Phase 5.2 Global Iteration 1 | Checksum: 2caa5e21c + +Time (s): cpu = 00:03:21 ; elapsed = 00:01:25 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424320 ; free virtual = 603539 +Phase 5 Rip-up And Reroute | Checksum: 2caa5e21c + +Time (s): cpu = 00:03:21 ; elapsed = 00:01:26 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424320 ; free virtual = 603539 + +Phase 6 Delay and Skew Optimization + +Phase 6.1 Delay CleanUp + +Phase 6.1.1 Update Timing +Phase 6.1.1 Update Timing | Checksum: 23ffe80c8 + +Time (s): cpu = 00:03:30 ; elapsed = 00:01:28 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424280 ; free virtual = 603499 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.274 | TNS=0.000 | WHS=N/A | THS=N/A | + +Phase 6.1 Delay CleanUp | Checksum: 2c7712393 + +Time (s): cpu = 00:03:30 ; elapsed = 00:01:28 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424280 ; free virtual = 603499 + +Phase 6.2 Clock Skew Optimization +Phase 6.2 Clock Skew Optimization | Checksum: 2c7712393 + +Time (s): cpu = 00:03:31 ; elapsed = 00:01:28 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424280 ; free virtual = 603499 +Phase 6 Delay and Skew Optimization | Checksum: 2c7712393 + +Time (s): cpu = 00:03:31 ; elapsed = 00:01:28 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424280 ; free virtual = 603500 + +Phase 7 Post Hold Fix + +Phase 7.1 Hold Fix Iter +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.274 | TNS=0.000 | WHS=0.010 | THS=0.000 | + +Phase 7.1 Hold Fix Iter | Checksum: 3069ea4f8 + +Time (s): cpu = 00:03:41 ; elapsed = 00:01:30 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424301 ; free virtual = 603520 +Phase 7 Post Hold Fix | Checksum: 3069ea4f8 + +Time (s): cpu = 00:03:41 ; elapsed = 00:01:30 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424301 ; free virtual = 603520 + +Phase 8 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 21.9621 % + Global Horizontal Routing Utilization = 26.5401 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Phase 8 Route finalize | Checksum: 3069ea4f8 + +Time (s): cpu = 00:03:42 ; elapsed = 00:01:30 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424309 ; free virtual = 603528 + +Phase 9 Verifying routed nets + + Verification completed successfully +Phase 9 Verifying routed nets | Checksum: 3069ea4f8 + +Time (s): cpu = 00:03:42 ; elapsed = 00:01:31 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424309 ; free virtual = 603528 + +Phase 10 Depositing Routes +Phase 10 Depositing Routes | Checksum: 29fc7be2a + +Time (s): cpu = 00:03:49 ; elapsed = 00:01:34 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424316 ; free virtual = 603535 + +Phase 11 Post Process Routing +Phase 11 Post Process Routing | Checksum: 29fc7be2a + +Time (s): cpu = 00:03:49 ; elapsed = 00:01:34 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424316 ; free virtual = 603535 + +Phase 12 Post Router Timing +INFO: [Route 35-20] Post Routing Timing Summary | WNS=1.276 | TNS=0.000 | WHS=0.012 | THS=0.000 | + +Phase 12 Post Router Timing | Checksum: 1f006e4a8 + +Time (s): cpu = 00:04:17 ; elapsed = 00:01:40 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424343 ; free virtual = 603562 +INFO: [Route 35-61] The design met the timing requirement. +Total Elapsed time in route_design: 100.15 secs + +Phase 13 Post-Route Event Processing +Phase 13 Post-Route Event Processing | Checksum: fa658e56 + +Time (s): cpu = 00:04:17 ; elapsed = 00:01:41 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424343 ; free virtual = 603562 +INFO: [Route 35-16] Router Completed Successfully +Ending Routing Task | Checksum: fa658e56 + +Time (s): cpu = 00:04:18 ; elapsed = 00:01:41 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424351 ; free virtual = 603571 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +16 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:04:24 ; elapsed = 00:01:45 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424352 ; free virtual = 603571 +# write_checkpoint -force $out/routed.dcp +INFO: [Timing 38-480] Writing timing data to binary archive. +Write ShapeDB Complete: Time (s): cpu = 00:00:00.79 ; elapsed = 00:00:00.16 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424337 ; free virtual = 603574 +Wrote PlaceDB: Time (s): cpu = 00:00:08 ; elapsed = 00:00:03 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424235 ; free virtual = 603557 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424235 ; free virtual = 603557 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00.92 ; elapsed = 00:00:00.54 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424229 ; free virtual = 603567 +Wrote Netlist Cache: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424222 ; free virtual = 603569 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424214 ; free virtual = 603561 +Write Physdb Complete: Time (s): cpu = 00:00:09 ; elapsed = 00:00:04 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424214 ; free virtual = 603561 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/routed.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:24 ; elapsed = 00:00:14 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424299 ; free virtual = 603605 +# phase REPORT +BOARD_PHASE REPORT +# report_utilization -file $out/routed-utilization.rpt +# report_utilization -hierarchical -file $out/routed-hierarchy.rpt +# report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -file $out/routed-timing.rpt +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. +report_timing_summary: Time (s): cpu = 00:00:25 ; elapsed = 00:00:07 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424242 ; free virtual = 603549 +# report_route_status -file $out/route-status.rpt +# report_drc -file $out/drc.rpt +Command: report_drc -file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/drc.rpt +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 8 threads +INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/drc.rpt. +report_drc completed successfully +INFO: [Timing 38-91] UpdateTimingParams: No interconnect No Cell Dly, Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +INFO: [Timing 38-314] The report_cdc command only analyzes and reports clock domain crossing paths where clocks have been defined on both source and destination sides. Ports with no input delay constraint are skipped. Please run check_timing to verify there are no missing clock definitions in your design, nor any unconstrained input port. +# set cdc [report_cdc -details -return_string] +# set f [open $out/cdc.rpt w] +# puts $f $cdc +# close $f +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +# set skew [report_bus_skew -return_string] +# set f [open $out/bus-skew.rpt w] +# puts $f $skew +# close $f +# report_methodology -file $out/methodology.rpt +Command: report_methodology -file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/methodology.rpt +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 8 threads +INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/methodology.rpt. +report_methodology completed successfully +report_methodology: Time (s): cpu = 00:00:30 ; elapsed = 00:00:10 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424266 ; free virtual = 603608 +# report_io -file $out/io.rpt +report_io: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.18 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424268 ; free virtual = 603610 +# report_clocks -file $out/clocks.rpt +INFO: [Timing 38-35] Done setting XDC timing constraints. +# check_timing -verbose -file $out/check-timing.rpt +# if {[regexp {CDC-[0-9]+\s+Critical} $cdc]} {error "Critical CDC findings; see cdc.rpt"} +# if {[string match *VIOLATED* $skew]} {error "Bus skew failed; see bus-skew.rpt"} +# foreach kind {max min} { +# set paths [get_timing_paths -delay_type $kind -max_paths 1] +# if {[llength $paths]==0} {error "Missing $kind timing paths"} +# if {[get_property SLACK [lindex $paths 0]]<0} {error "$kind timing failed"} +# } +# if {![report_route_status -boolean_check ROUTED_FULLY]} {error "Routing incomplete"} +# if {[report_route_status -boolean_check ERRORS_IN_ROUTES]} {error "Routing errors"} +# set errors [get_drc_violations -quiet -filter {SEVERITY == Error || SEVERITY == {Critical Warning}}] +# if {[llength $errors]} {error "DRC errors/critical warnings: $errors"} +# phase BITSTREAM +BOARD_PHASE BITSTREAM +# set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +# write_bitstream -force $out/toy_a7.bit +Command: write_bitstream -force /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/toy_a7.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +Running DRC as a precondition to command write_bitstream +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 8 threads +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +INFO: [Common 17-14] Message 'DRC DPIP-1' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +INFO: [Common 17-14] Message 'DRC DPOP-1' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/rowSkip_reg multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/rowSkip_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +INFO: [Common 17-14] Message 'DRC DPOP-2' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [DRC REQP-1709] Clock output buffering: PLLE2_ADV connectivity violation. The signal ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out on the ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 pin of ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i does not drive the same kind of BUFFER load as the other CLKOUT pins. Routing from the different buffer types will not be phase aligned. +WARNING: [DRC RTSTAT-10] No routable loads: 45 net(s) have no routable loads. The problem bus(es) and/or net(s) are memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0]... and (the first 15 of 25 listed). +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 360 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Bitstream compression saved 7428160 bits. +Writing bitstream /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/toy_a7.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-83] Releasing license: Implementation +12 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:45 ; elapsed = 00:00:24 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424219 ; free virtual = 603708 +# phase COMPLETE +BOARD_PHASE COMPLETE +# puts "PASS BOARD_PLACE_ROUTE_TIMING_BITSTREAM: engineering Rev E target; flash=$flash; this build does not validate physical boot" +PASS BOARD_PLACE_ROUTE_TIMING_BITSTREAM: engineering Rev E target; flash=0; this build does not validate physical boot +INFO: [Common 17-206] Exiting Vivado at Mon Oct 12 20:37:08 2026... diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/README.md b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/README.md new file mode 100644 index 0000000..af10a48 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/README.md @@ -0,0 +1,27 @@ +# Board integration + +Build and programming commands are in [the platform guide](../README.md). +This directory targets Arty A7-100T `xc7a100tcsg324-1` with official Digilent +Rev E.0 DDR parameters. The recorded hardware run passes full payload DDR +readback and Linux checks; physical PCB revision remains unconfirmed. + +- `toy_a7_top.sv`: 100 MHz input, MMCM/BUFG clocks, per-domain reset sequencing, + physical UART/LED/DDR pins, actual MIG and AXI Clock Converter instances. +- `toy_a7_platform.sv`: validated Chisel core, loader/CPU DDR arbitration, + fullwidth memory adapter and SCU console. CPU remains reset until verified RUN. +- `axi_fullwidth.sv`: preserves lanes, strobes, IDs and backpressure while + translating narrow INCR/FIXED beats into aligned 128-bit DDR accesses. +- `ddr_uart_loader.sv` / `loader_axi.sv`: CRC-framed load, readback and release; + acknowledgements wait for DDR responses. INFO bytes preserve LUTRAM inference. +- `axi_scu.sv`: UART/exit MMIO and 256-byte RX FIFO, with accepted-response pops. +- `arty_a7.xdc`: actual pins and targeted asynchronous I/O/reset exceptions; + DDR data/address/control and internal CPU timing remain checked. +- `build_board.tcl`: complete IP generation, synthesis, placement, routing and + bitstream. Setup/hold, CDC Critical, bus skew, routing errors and DRC errors + stop the build. No warning severity downgrade or CDC waiver is applied. +- `program_arty.tcl`: explicit volatile JTAG programming; exactly one target + and one XC7A100T required. The platform's `../program.tcl` entry delegates here. + The exact script used for first bring-up is also archived with the hardware logs. + +`vendor/` contains unmodified pinned Digilent MIG/board inputs and their license. +Vivado generates proprietary vendor IP into ignored build directories locally. diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/SOURCE_MANIFEST.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/SOURCE_MANIFEST.json new file mode 100644 index 0000000..3ced1fd --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/SOURCE_MANIFEST.json @@ -0,0 +1,18 @@ +{ + "core_sha256": "4c6aacf64660bbbf14b1114e8d5e4439d6a4e1427aaf1f681c6a4f618f2d2779", + "copied_files": { + "uart_rx.sv": "0b35263884577324f146ff7fd516e5b561dcc8787e0d8ad599669bac1958406d", + "uart_tx.sv": "c20d420fc20be4f6313bdde5abc45ef0b9f8e93bf75350dd9951bc8868b3b65c", + "vendor/board.xml": "5bd9a7ca97ccb2fef617515a14401166464b45a06684d663c0be1a06b02a86df", + "vendor/MANIFEST.json": "3fbfac2499bc99a23356873a5d81e0f87d32f02ec1b7929ead51a15f33d9af85", + "vendor/mig.prj": "914a9e4bb1b3002837592944cdf49f8dfbaf4d112552dd8b5be48602ff1ac329", + "vendor/part0_pins.xml": "50aa844aa9c78af6342de68ae3c980f7618716447b28282878d5a106f86fed31", + "vendor/preset.xml": "ff95b9b976323fefa588873588dfa2bdce1673759c0a9e91c12ee9f2a2955bce" + }, + "clock_hz": 25000000, + "uart_baud": 1000000, + "memory_bytes": 268435456, + "clint_actual_hz": 500000, + "vendor_revision": "E.0", + "physical_board_revision": "unknown" +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/arty_a7.xdc b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/arty_a7.xdc new file mode 100644 index 0000000..51efe3b --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/arty_a7.xdc @@ -0,0 +1,27 @@ +# User pins from Digilent Arty A7-100 Master XDC Rev D/E. DDR pins/timing +# are supplied by the unmodified official MIG output products. +set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports CLK100MHZ] +create_clock -name board_clk -period 10.000 [get_ports CLK100MHZ] +set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS33} [get_ports btn0] +set_property -dict {PACKAGE_PIN A9 IOSTANDARD LVCMOS33} [get_ports uart_txd_in] +set_property -dict {PACKAGE_PIN D10 IOSTANDARD LVCMOS33} [get_ports uart_rxd_out] +set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports {led[0]}] +set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports {led[1]}] +set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {led[2]}] +set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {led[3]}] +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property DRIVE 8 [get_ports {led[*] uart_rxd_out}] +set_property SLEW SLOW [get_ports {led[*] uart_rxd_out}] +# Asynchronous button and UART input: cut only the first synchronizer stage. +set_false_path -from [get_ports btn0] -to [get_pins -hier -filter {NAME =~ *btn_meta_reg/D || NAME =~ *btn_ref_meta_reg/D}] +set_false_path -from [get_ports uart_txd_in] -to [get_pins -hier -filter {NAME =~ *rx_meta_reg/D}] +# Reset assertion is asynchronous; deassertion is synchronized in each domain. +set_false_path -to [get_pins -hier -filter {NAME =~ *lock_sync_reg*/PRE || NAME =~ *ui_reset_pipe_reg*/PRE}] +# Calibration status crosses ui_clk to core_clk through a two-stage synchronizer. +set_false_path -to [get_pins -hier -regexp {.*calib_sync_reg\[0\]/D}] +# Human-visible indicators and asynchronous serial TX have no external clock. +set_false_path -to [get_ports {led[*] uart_rxd_out}] +# DDR RESET_N is an asynchronous memory reset, sequenced by the unmodified MIG +# initialization FSM. It is not a command/data signal sampled on DDR CK edges. +set_false_path -to [get_ports ddr3_reset_n] diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/axi_fullwidth.sv b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/axi_fullwidth.sv new file mode 100644 index 0000000..a17053c --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/axi_fullwidth.sv @@ -0,0 +1,115 @@ +// Serialize each INCR/FIXED AXI beat into an aligned 128-bit MIG transaction. +// Lane positions/strobes and IDs are preserved. Narrow reads may overfetch DDR +// bytes but never MMIO. One read and one write burst can progress independently. +module axi_fullwidth ( + input wire clk, reset, + input wire [3:0] s_awid, s_arid, + input wire [31:0] s_awaddr, s_araddr, + input wire [7:0] s_awlen, s_arlen, + input wire [2:0] s_awsize, s_arsize, + input wire [1:0] s_awburst, s_arburst, + input wire s_awvalid, s_arvalid, s_wvalid, s_wlast, s_bready, s_rready, + output wire s_awready, s_arready, s_wready, + input wire [127:0] s_wdata, input wire [15:0] s_wstrb, + output reg [3:0] s_bid, s_rid, + output reg [1:0] s_bresp, s_rresp, + output reg s_bvalid, s_rvalid, s_rlast, output reg [127:0] s_rdata, + output wire [3:0] m_awid, m_arid, + output wire [27:0] m_awaddr, m_araddr, + output wire [7:0] m_awlen, m_arlen, + output wire [2:0] m_awsize, m_arsize, + output wire [1:0] m_awburst, m_arburst, + output wire m_awvalid, m_arvalid, m_wvalid, m_wlast, m_bready, m_rready, + input wire m_awready, m_arready, m_wready, + output wire [127:0] m_wdata, output wire [15:0] m_wstrb, + input wire [3:0] m_bid, m_rid, + input wire [1:0] m_bresp, m_rresp, + input wire m_bvalid, m_rvalid, m_rlast, input wire [127:0] m_rdata +); + localparam W_IDLE=0, W_DATA=1, W_SEND=2, W_RESP=3; + localparam R_IDLE=0, R_SEND=1, R_RESP=2, R_RETURN=3; + reg [1:0] ws, rs; + reg [31:0] wa, ra; + reg [7:0] wl, rl; + reg [2:0] wz, rz; + reg wi, ri, wbad, rbad, aw_sent, w_sent; + reg [127:0] wd; + reg [15:0] wm; + wire [32:0] wend = {1'b0,s_awaddr} + ({25'd0,s_awlen} << s_awsize); + wire [32:0] rend = {1'b0,s_araddr} + ({25'd0,s_arlen} << s_arsize); + wire wlegal = s_awaddr[31:28]==4'h8 && s_awsize<=4 && s_awburst<=1 && + (s_awaddr & ((32'd1<3 || awburst>1 || + (awaddr & ((31'd1<3 || arburst>1 || (araddr & ((31'd1<=3) rdata[47:40]<={5'd0,framing,overflow,count!=0}; + end else rresp<=2; + end + if(push) begin fifo[wp]<=rx_data;wp<=wp+1'b1;end + if(pop) rp<=rp+1'b1; + case({push,pop}) + 2'b10:count<=count+1'b1; + 2'b01:count<=count-1'b1; + default:count<=count; + endcase + if(rx_valid && !push) overflow<=1; + if(rx_error) framing<=1; + end + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/backup_flash.tcl b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/backup_flash.tcl new file mode 100644 index 0000000..7c44264 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/backup_flash.tcl @@ -0,0 +1,32 @@ +# Read all existing Flash before any erase. This temporarily replaces FPGA SRAM +# with Vivado's SPI bridge, but never requests a Flash write/erase. +if {$argc!=2} {error "Usage: backup_flash.tcl FLASH_PART output.bin"} +lassign $argv part backup +set backup [file normalize $backup] +if {[file exists $backup]} {error "Refusing to overwrite an existing backup"} +if {$part ni {s25fl128sxxxxxx0-spi-x1_x2_x4 s25fl128sxxxxxx1-spi-x1_x2_x4 mt25ql128-spi-x1_x2_x4}} { + error "Select the exact supported 128-Mbit Arty Flash model" +} +open_hw_manager +connect_hw_server -allow_non_jtag +set targets [get_hw_targets -quiet] +if {[llength $targets]!=1} {error "Expected one attached JTAG target"} +open_hw_target [lindex $targets 0] +set devices [get_hw_devices -quiet -filter {PART == xc7a100t}] +if {[llength $devices]!=1} {error "Expected one XC7A100T"} +set device [lindex $devices 0] +current_hw_device $device +set choices [get_cfgmem_parts -of_objects $device -filter "NAME == $part"] +if {[llength $choices]!=1} {error "Flash part is not uniquely compatible with this FPGA"} +create_hw_cfgmem -hw_device $device [lindex $choices 0] +set memory [get_property PROGRAM.HW_CFGMEM $device] +create_hw_bitstream -hw_device $device [get_property PROGRAM.HW_CFGMEM_BITFILE $device] +program_hw_devices $device +file mkdir [file dirname $backup] +readback_hw_cfgmem -all -file $backup -format bin $memory +if {[file size $backup]!=16777216} {error "Incomplete Flash backup"} +puts "PASS FLASH_BACKUP: $part $backup bytes=16777216" +close_hw_target +disconnect_hw_server +close_hw_manager +exit diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/build_board.tcl b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/build_board.tcl new file mode 100644 index 0000000..93159c2 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/build_board.tcl @@ -0,0 +1,86 @@ +set root [file dirname [file dirname [file normalize [info script]]]] +cd $root +if {[llength $argv]<1 || [llength $argv]>2} {error "Usage: build_board.tcl OUTPUT_DIRECTORY ?flash?"} +set flash 0 +if {[llength $argv]==2} { + if {[lindex $argv 1] ne "flash"} {error "Second argument must be flash"} + set flash 1 +} +set out [file normalize [lindex $argv 0]] +file mkdir $out +file mkdir $out/ip +proc phase {name} { + global out + set f [open $out/phase.txt w];puts $f $name;close $f + puts "BOARD_PHASE $name" +} +set_param general.maxThreads 8 +phase CREATE_IP +create_project -in_memory -part xc7a100tcsg324-1 +set_property target_language Verilog [current_project] +create_ip -name mig_7series -vendor xilinx.com -library ip -version 4.2 -module_name arty_ddr3 -dir $out/ip +set_property CONFIG.XML_INPUT_FILE $root/board/vendor/mig.prj [get_ips arty_ddr3] +create_ip -name axi_clock_converter -vendor xilinx.com -library ip -version 2.1 -module_name toy_axi_cdc -dir $out/ip +set_property -dict {CONFIG.PROTOCOL AXI4 CONFIG.ADDR_WIDTH 28 CONFIG.DATA_WIDTH 128 CONFIG.ID_WIDTH 4 CONFIG.ACLK_ASYNC 1 CONFIG.SYNCHRONIZATION_STAGES 3} [get_ips toy_axi_cdc] +generate_target all [get_ips] +report_ip_status -file $out/ip-status.rpt +phase SYNTH_IP +synth_ip [get_ips] +phase SYNTH_BOARD +if {$flash} {read_verilog -sv $root/build/flash-boot/ToyLinuxChip.sv} else { + read_verilog -sv $root/build/serial-bound/ToyLinuxChip.sv +} +read_verilog -sv $root/build/serial-bound/FpgaMemories.sv +foreach f [glob $root/board/*.sv] {read_verilog -sv $f} +set_property verilog_define {SYNTHESIS BUCKYBALL_DISABLE_DPI} [current_fileset] +read_xdc $root/board/arty_a7.xdc +read_xdc $root/board/flash_boot.xdc +synth_design -top toy_a7_top -part xc7a100tcsg324-1 -flatten_hierarchy rebuilt -directive AreaOptimized_high -resource_sharing on -generic FLASH_BOOT=$flash +write_checkpoint -force $out/synthesized.dcp +report_utilization -file $out/synth-utilization.rpt +report_utilization -hierarchical -file $out/synth-hierarchy.rpt +report_timing_summary -delay_type min_max -file $out/synth-timing.rpt +set unresolved [get_cells -hier -quiet -filter {IS_BLACKBOX == 1}] +if {[llength $unresolved]} {error "Unresolved black boxes: $unresolved"} +phase OPTIMIZE +opt_design -directive ExploreArea +write_checkpoint -force $out/optimized.dcp +report_utilization -file $out/opt-utilization.rpt +phase PLACE +place_design -directive Explore +write_checkpoint -force $out/placed.dcp +phase PHYS_OPT +phys_opt_design -directive Explore +phase ROUTE +route_design -directive Explore +write_checkpoint -force $out/routed.dcp +phase REPORT +report_utilization -file $out/routed-utilization.rpt +report_utilization -hierarchical -file $out/routed-hierarchy.rpt +report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -file $out/routed-timing.rpt +report_route_status -file $out/route-status.rpt +report_drc -file $out/drc.rpt +set cdc [report_cdc -details -return_string] +set f [open $out/cdc.rpt w];puts $f $cdc;close $f +set skew [report_bus_skew -return_string] +set f [open $out/bus-skew.rpt w];puts $f $skew;close $f +report_methodology -file $out/methodology.rpt +report_io -file $out/io.rpt +report_clocks -file $out/clocks.rpt +check_timing -verbose -file $out/check-timing.rpt +if {[regexp {CDC-[0-9]+\s+Critical} $cdc]} {error "Critical CDC findings; see cdc.rpt"} +if {[string match *VIOLATED* $skew]} {error "Bus skew failed; see bus-skew.rpt"} +foreach kind {max min} { + set paths [get_timing_paths -delay_type $kind -max_paths 1] + if {[llength $paths]==0} {error "Missing $kind timing paths"} + if {[get_property SLACK [lindex $paths 0]]<0} {error "$kind timing failed"} +} +if {![report_route_status -boolean_check ROUTED_FULLY]} {error "Routing incomplete"} +if {[report_route_status -boolean_check ERRORS_IN_ROUTES]} {error "Routing errors"} +set errors [get_drc_violations -quiet -filter {SEVERITY == Error || SEVERITY == {Critical Warning}}] +if {[llength $errors]} {error "DRC errors/critical warnings: $errors"} +phase BITSTREAM +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +write_bitstream -force $out/toy_a7.bit +phase COMPLETE +puts "PASS BOARD_PLACE_ROUTE_TIMING_BITSTREAM: engineering Rev E target; flash=$flash; this build does not validate physical boot" diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/ddr_uart_loader.sv b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/ddr_uart_loader.sv new file mode 100644 index 0000000..9aa2dc9 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/ddr_uart_loader.sv @@ -0,0 +1,169 @@ +// Stop-and-wait serial boot protocol. Requests: A5 5A op seq addrLE32 lenLE16 +// [WRITE payload] crcLE16. CRC-16/CCITT-FALSE covers op through payload. +// Responses: 5A A5 (op|80) seq status lenLE16 [data] crcLE16. +// CRC is checked before any DDR write; CPU starts after the RUN reply drains. +module ddr_uart_loader #( + parameter integer RAM_BYTES = 268435456, + parameter integer CLOCK_HZ = 25000000, + parameter integer RX_TIMEOUT = CLOCK_HZ/10 +) ( + input wire clk, reset, + input wire rx_valid, input wire [7:0] rx_data, input wire rx_error, + output wire tx_valid, output reg [7:0] tx_data, input wire tx_ready, + output reg cpu_run, output reg error_seen, + output wire load_en, + output wire [$clog2(RAM_BYTES)-1:0] load_addr, + output reg [127:0] load_data, + output reg [15:0] load_mask, + input wire load_valid, load_error, input wire [127:0] load_result +); + localparam [3:0] SYNC0=0,SYNC1=1,HEADER=2,PAYLOAD=3,CRC0=4,CRC1=5, + EXECUTE=6,WRITE=7,READ_REQ=8,READ_WAIT=9,REPLY=10,DRAIN=11; + reg [3:0] state; + reg [7:0] operation, sequence_id, status; + reg [31:0] address; + reg [15:0] length, reply_length, crc, received_crc; + reg [8:0] cursor, reply_index; + reg [3:0] header_index; + (* ram_style="distributed" *) reg [7:0] payload [0:255]; + reg pending_run, image_loaded; + reg [$clog2(RX_TIMEOUT+1)-1:0] timeout_count; + wire receiving = state==SYNC1 || state==HEADER || state==PAYLOAD || state==CRC0 || state==CRC1; + wire [32:0] end_address = {1'b0,address}+length; + wire valid_range = length!=0 && length<=256 && address>=32'h80000000 && + end_address<=33'h080000000+RAM_BYTES; + wire [31:0] byte_address = address + cursor; + assign load_addr = byte_address[$clog2(RAM_BYTES)-1:0]; + assign load_en = !cpu_run && (state==WRITE || state==READ_REQ); + always @* begin + load_data=0;load_mask=0; + if(state==WRITE) begin + load_data[byte_address[3:0]*8 +: 8]=payload[cursor[7:0]]; + load_mask=16'b1<> ((reply_index-11)*8); + 15,16,17,18:tx_data=CLOCK_HZ >> ((reply_index-15)*8); + default:tx_data=0; + endcase + else tx_data=payload[(reply_index-7) & 255]; + end + else if(reply_index==7+reply_length) tx_data=crc[7:0]; + else tx_data=crc[15:8]; + end + endcase + end + always @(posedge clk) begin + if(reset) begin + state<=SYNC0;cpu_run<=0;error_seen<=0;image_loaded<=0;pending_run<=0; + operation<=0;sequence_id<=0;status<=0;address<=0;length<=0; + reply_length<=0;crc<=16'hffff;received_crc<=0;cursor<=0; + reply_index<=0;header_index<=0;timeout_count<=0; + end else if(!cpu_run) begin + if(!receiving || rx_valid) timeout_count<=0; + else timeout_count<=timeout_count+1'b1; + if((receiving && timeout_count==RX_TIMEOUT-1) || (receiving && rx_error)) begin + state<=SYNC0;error_seen<=1;timeout_count<=0; + end else case(state) + SYNC0: if(rx_valid && rx_data==8'ha5) state<=SYNC1; + SYNC1: if(rx_valid) begin + if(rx_data==8'h5a) begin + state<=HEADER;header_index<=0;crc<=16'hffff;length<=0;address<=0; + pending_run<=0;reply_index<=0;reply_length<=0;status<=0; + end else if(rx_data!=8'ha5) state<=SYNC0; + end + HEADER: if(rx_valid) begin + crc<=crc_next(crc,rx_data); + case(header_index) + 0:operation<=rx_data; + 1:sequence_id<=rx_data; + 2:address[7:0]<=rx_data; + 3:address[15:8]<=rx_data; + 4:address[23:16]<=rx_data; + 5:address[31:24]<=rx_data; + 6:length[7:0]<=rx_data; + 7:begin + length[15:8]<=rx_data;cursor<=0; + if({rx_data,length[7:0]}>256) begin state<=SYNC0;error_seen<=1;end + else if(operation==1 && {rx_data,length[7:0]}!=0) state<=PAYLOAD; + else state<=CRC0; + end + endcase + header_index<=header_index+1'b1; + end + PAYLOAD: if(rx_valid) begin + payload[cursor[7:0]]<=rx_data;crc<=crc_next(crc,rx_data); + cursor<=cursor+1'b1; + if(cursor+1==length) state<=CRC0; + end + CRC0: if(rx_valid) begin received_crc[7:0]<=rx_data;state<=CRC1;end + CRC1: if(rx_valid) begin + cursor<=0; + if({rx_data,received_crc[7:0]}!=crc) begin + status<=1;error_seen<=1;crc<=16'hffff;state<=REPLY; + end else state<=EXECUTE; + end + EXECUTE: begin + crc<=16'hffff; + if(operation==1 || operation==2) begin + if(!valid_range) begin status<=2;error_seen<=1;state<=REPLY;end + else if(operation==1) state<=WRITE; + else begin reply_length<=length;state<=READ_REQ;end + end else if(operation==3 && length==0 && address==32'h80000000) begin + if(!image_loaded) begin status<=5;error_seen<=1;end + else pending_run<=1; + state<=REPLY; + end else if(operation==4 && length==0 && address==0) begin + reply_length<=12;state<=REPLY; + end else begin status<=3;error_seen<=1;state<=REPLY;end + end + WRITE: if(load_valid) begin + if(load_error) begin status<=6;error_seen<=1;state<=REPLY;end + else if(cursor+1==length) begin image_loaded<=1;state<=REPLY;end + else cursor<=cursor+1'b1; + end + READ_REQ: state<=READ_WAIT; + READ_WAIT: if(load_valid) begin + if(load_error) begin status<=6;error_seen<=1;reply_length<=0;state<=REPLY;end + else begin + payload[cursor[7:0]]<=load_result[byte_address[3:0]*8 +: 8]; + if(cursor+1==length) state<=REPLY; + else begin cursor<=cursor+1'b1;state<=READ_REQ;end + end + end + REPLY: if(tx_ready) begin + if(reply_index>=2 && reply_index<7+reply_length) crc<=crc_next(crc,tx_data); + if(reply_index==8+reply_length) state<=DRAIN; + else reply_index<=reply_index+1'b1; + end + DRAIN: if(tx_ready) begin + if(pending_run) cpu_run<=1; + state<=SYNC0; + end + default:state<=SYNC0; + endcase + end + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/flash_boot.xdc b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/flash_boot.xdc new file mode 100644 index 0000000..902d6a7 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/flash_boot.xdc @@ -0,0 +1,19 @@ +# Digilent Arty-A7-100-Master.xdc Rev D/E; CCLK is owned by STARTUPE2. +set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS33} [get_ports sw0] +set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS33} [get_ports flash_cs_n] +set_property -dict {PACKAGE_PIN K17 IOSTANDARD LVCMOS33} [get_ports flash_mosi] +set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33} [get_ports flash_miso] +set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS33} [get_ports flash_wp_n] +set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS33} [get_ports flash_hold_n] +set_property DRIVE 8 [get_ports {flash_cs_n flash_mosi flash_wp_n flash_hold_n}] +set_property SLEW SLOW [get_ports {flash_cs_n flash_mosi flash_wp_n flash_hold_n}] +set switch_sync [get_pins -quiet -hier -filter {NAME =~ *sw_meta_reg/D}] +if {[llength $switch_sync]} {set_false_path -from [get_ports sw0] -to $switch_sync} +# Serial input sampled after two synchronizer stages. Mode-0 half bit is 160 ns; +# the external data settles before these stages, then is sampled on the next rise. +set flash_sync [get_pins -quiet -hier -filter {NAME =~ *miso_meta_reg/D}] +if {[llength $flash_sync]} {set_false_path -from [get_ports flash_miso] -to $flash_sync} +set_false_path -to [get_ports {flash_cs_n flash_mosi flash_wp_n flash_hold_n}] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 1 [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 16 [current_design] +set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/flash_spi_byte.sv b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/flash_spi_byte.sv new file mode 100644 index 0000000..1610a12 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/flash_spi_byte.sv @@ -0,0 +1,33 @@ +// Read-only boot software uses this mode-0 byte engine; no Flash writes in RTL. +// 25 MHz / (2 * 4) = 3.125 MHz. Two MISO synchronizers settle within a half bit. +module flash_spi_byte ( + input wire clk, reset, start, + input wire [7:0] tx_data, + input wire miso, + output reg busy, sck, + output wire mosi, + output reg [7:0] rx_data +); + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg miso_meta, miso_sync; + reg [7:0] shift_tx, shift_rx; + reg [2:0] bit_count; + reg [1:0] divider; + assign mosi=shift_tx[7]; + always @(posedge clk) begin + miso_meta<=miso;miso_sync<=miso_meta; + if(reset) begin + busy<=0;sck<=0;shift_tx<=0;shift_rx<=0;rx_data<=0;bit_count<=0;divider<=0; + end else if(!busy) begin + sck<=0; + if(start) begin busy<=1;shift_tx<=tx_data;shift_rx<=0;bit_count<=0;divider<=0;end + end else if(divider==3) begin + divider<=0;sck<=!sck; + if(!sck) shift_rx<={shift_rx[6:0],miso_sync}; + else begin + shift_tx<={shift_tx[6:0],1'b1}; + if(bit_count==7) begin busy<=0;rx_data<=shift_rx;end + else bit_count<=bit_count+1'b1; + end + end else divider<=divider+1'b1; + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/loader_axi.sv b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/loader_axi.sv new file mode 100644 index 0000000..096ddb0 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/loader_axi.sv @@ -0,0 +1,53 @@ +// Convert a held loader byte request into a completed AXI transaction. +// The loader advances only after B/R. A RELEASE cycle prevents resubmission +// while its synchronous state machine consumes the acknowledgement. +module loader_axi ( + input wire clk, reset, load_en, + input wire [27:0] load_addr, + input wire [127:0] load_data, input wire [15:0] load_mask, + output reg load_valid, load_error, output reg [127:0] load_result, + output wire [27:0] awaddr, araddr, + output wire awvalid, wvalid, arvalid, bready, rready, + input wire awready, wready, arready, bvalid, rvalid, + output wire [127:0] wdata, output wire [15:0] wstrb, + input wire [1:0] bresp, rresp, input wire [127:0] rdata +); + localparam IDLE=0, SEND_W=1, WAIT_B=2, SEND_R=3, WAIT_R=4, RELEASE=5; + reg [2:0] state; + reg [27:0] addr; + reg [127:0] data; + reg [15:0] mask; + reg sent_aw, sent_w; + assign awaddr=addr;assign araddr=addr; + assign wdata=data;assign wstrb=mask; + assign awvalid=!reset && state==SEND_W && !sent_aw; + assign wvalid=!reset && state==SEND_W && !sent_w; + assign arvalid=!reset && state==SEND_R; + assign bready=!reset && state==WAIT_B; + assign rready=!reset && state==WAIT_R; + always @(posedge clk) begin + load_valid<=0; + if(reset) begin + state<=IDLE;addr<=0;data<=0;mask<=0;sent_aw<=0;sent_w<=0; + load_valid<=0;load_error<=0;load_result<=0; + end else case(state) + IDLE:if(load_en) begin + addr<={load_addr[27:4],4'd0};data<=load_data;mask<=load_mask; + sent_aw<=0;sent_w<=0;load_error<=0; + state<=|load_mask ? SEND_W : SEND_R; + end + SEND_W:begin + if(awvalid && awready) sent_aw<=1; + if(wvalid && wready) sent_w<=1; + if((sent_aw || awready) && (sent_w || wready)) state<=WAIT_B; + end + WAIT_B:if(bvalid) begin load_valid<=1;load_error<=bresp!=0;state<=RELEASE;end + SEND_R:if(arready) state<=WAIT_R; + WAIT_R:if(rvalid) begin + load_valid<=1;load_error<=rresp!=0;load_result<=rdata;state<=RELEASE; + end + RELEASE:state<=IDLE; + default:state<=IDLE; + endcase + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/make_flash_image.tcl b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/make_flash_image.tcl new file mode 100644 index 0000000..ad0a6d6 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/make_flash_image.tcl @@ -0,0 +1,18 @@ +# Combine configuration and packed software without crossing partitions. +if {$argc!=3} {error "Usage: make_flash_image.tcl toy_a7.bit flash_payload.bin output.mcs"} +lassign $argv bitfile payload output +set bitfile [file normalize $bitfile] +set payload [file normalize $payload] +set output [file normalize $output] +if {![file isfile $bitfile] || ![file isfile $payload]} {error "Missing input file"} +if {[file size $bitfile]>=0x400000} {error "Configuration exceeds the 4 MiB partition"} +if {[file size $payload]<=32 || [file size $payload]>0xc00000} {error "Invalid software partition size"} +set f [open $payload rb] +set magic [read $f 8] +close $f +if {$magic ne "TOYFLZ4\x00"} {error "Expected a packed TOYFLZ4 image"} +file mkdir [file dirname $output] +write_cfgmem -force -format mcs -interface SPIx1 -size 16 \ + -loadbit [list up 0x00000000 $bitfile] -loaddata [list up 0x00400000 $payload] -file $output +puts "PASS FLASH_IMAGE_LAYOUT: config=0x0 software=0x400000 capacity=16MiB" +exit diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/program_arty.tcl b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/program_arty.tcl new file mode 100644 index 0000000..f70f054 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/program_arty.tcl @@ -0,0 +1,25 @@ +# Volatile JTAG programming only. Usage: +# Confirm physical Rev E DDR compatibility before using this engineering image. +# vivado -mode batch -source board/program_arty.tcl -tclargs /path/to/toy_a7.bit +if {$argc != 1} { error "Supply the Arty A7-100T .bit file" } +set bitfile [file normalize [lindex $argv 0]] +if {![file isfile $bitfile]} { error "Bitstream not found: $bitfile" } +open_hw_manager +connect_hw_server -allow_non_jtag +set targets [get_hw_targets -quiet] +if {[llength $targets] != 1} { + error "Expected one connected JTAG target. Select the Arty manually in Hardware Manager if multiple boards are attached." +} +open_hw_target [lindex $targets 0] +set devices [get_hw_devices -quiet -filter {PART == xc7a100t}] +if {[llength $devices] != 1} { error "Expected one XC7A100T; inspect the connected board" } +set device [lindex $devices 0] +current_hw_device $device +set_property PROGRAM.FILE $bitfile $device +program_hw_devices $device +refresh_hw_device $device +puts "ARTY_JTAG_PROGRAMMED: $bitfile" +close_hw_target +disconnect_hw_server +close_hw_manager +exit diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/program_flash.tcl b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/program_flash.tcl new file mode 100644 index 0000000..82a6c4f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/program_flash.tcl @@ -0,0 +1,51 @@ +# Explicit nonvolatile programming: backs up Flash, then erases/programs/verifies. +if {$argc!=3} {error "Usage: program_flash.tcl image.mcs FLASH_PART fresh-backup.bin"} +lassign $argv image part backup +set image [file normalize $image] +set backup [file normalize $backup] +if {![file isfile $image]} {error "Missing Flash image"} +if {[file exists $backup]} {error "Refusing to overwrite an existing backup"} +if {$part ni {s25fl128sxxxxxx0-spi-x1_x2_x4 s25fl128sxxxxxx1-spi-x1_x2_x4 mt25ql128-spi-x1_x2_x4}} { + error "Select the exact supported 128-Mbit Arty Flash model" +} +open_hw_manager +connect_hw_server -allow_non_jtag +set targets [get_hw_targets -quiet] +if {[llength $targets]!=1} {error "Expected one attached JTAG target"} +open_hw_target [lindex $targets 0] +set devices [get_hw_devices -quiet -filter {PART == xc7a100t}] +if {[llength $devices]!=1} {error "Expected one XC7A100T"} +set device [lindex $devices 0] +current_hw_device $device +set choices [get_cfgmem_parts -of_objects $device -filter "NAME == $part"] +if {[llength $choices]!=1} {error "Flash part is not uniquely compatible with this FPGA"} +create_hw_cfgmem -hw_device $device [lindex $choices 0] +set memory [get_property PROGRAM.HW_CFGMEM $device] +create_hw_bitstream -hw_device $device [get_property PROGRAM.HW_CFGMEM_BITFILE $device] +program_hw_devices $device +file mkdir [file dirname $backup] +readback_hw_cfgmem -all -file $backup -format bin $memory +if {[file size $backup]!=16777216} {error "Incomplete backup; programming cancelled"} +puts "PASS FLASH_BACKUP: $backup bytes=16777216" +set_property PROGRAM.ADDRESS_RANGE use_file $memory +set_property PROGRAM.FILES [list $image] $memory +set_property PROGRAM.BLANK_CHECK 0 $memory +set_property PROGRAM.ERASE 1 $memory +set_property PROGRAM.CFG_PROGRAM 1 $memory +set_property PROGRAM.VERIFY 1 $memory +set_property PROGRAM.CHECKSUM 0 $memory +program_hw_cfgmem $memory +puts "PASS FLASH_PROGRAM_VERIFY: $part $image" +# JP1 must be shorted; this reloads the FPGA from Flash without downloading .bit. +boot_hw_device -timeout 60 $device +refresh_hw_device $device +if {[get_property REGISTER.CONFIG_STATUS.BIT14_DONE_PIN $device]!=1 || + [get_property REGISTER.CONFIG_STATUS.BIT04_END_OF_STARTUP_(EOS)_STATUS $device]!=1 || + [get_property REGISTER.CONFIG_STATUS.BIT00_CRC_ERROR $device]!=0} { + error "FPGA did not successfully reconfigure from Flash" +} +puts "FLASH_BOOT_CONFIG_STATUS [get_property REGISTER.CONFIG_STATUS $device]" +close_hw_target +disconnect_hw_server +close_hw_manager +exit diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/toy_a7_platform.sv b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/toy_a7_platform.sv new file mode 100644 index 0000000..e26d6dc --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/toy_a7_platform.sv @@ -0,0 +1,450 @@ +// Generated wiring; source CPU/accelerator RTL is byte-identical. +module toy_a7_platform #(parameter UART_DIVISOR=25, parameter FLASH_BOOT=0) ( + input wire clk, reset, uart_rx_in, + output wire uart_tx_out, cpu_run, exited, loader_error, + output wire [31:0] exit_code, + output wire [3:0] ddr_awid, + output wire [27:0] ddr_awaddr, + output wire [7:0] ddr_awlen, + output wire [2:0] ddr_awsize, + output wire [1:0] ddr_awburst, + output wire ddr_awvalid, + input wire ddr_awready, + output wire [127:0] ddr_wdata, + output wire [15:0] ddr_wstrb, + output wire ddr_wlast, + output wire ddr_wvalid, + input wire ddr_wready, + input wire [3:0] ddr_bid, + input wire [1:0] ddr_bresp, + input wire ddr_bvalid, + output wire ddr_bready, + output wire [3:0] ddr_arid, + output wire [27:0] ddr_araddr, + output wire [7:0] ddr_arlen, + output wire [2:0] ddr_arsize, + output wire [1:0] ddr_arburst, + output wire ddr_arvalid, + input wire ddr_arready, + input wire [3:0] ddr_rid, + input wire [127:0] ddr_rdata, + input wire [1:0] ddr_rresp, + input wire ddr_rlast, + input wire ddr_rvalid, + output wire ddr_rready, + input wire flash_miso, flash_recovery, + output wire flash_mosi, flash_sck, flash_cs_n +); + wire cpu_reset=reset || !cpu_run; + wire loader_cpu_run; + assign cpu_run=loader_cpu_run || (FLASH_BOOT && !flash_recovery); + wire irq; + wire rx_valid, rx_error, tx_ready, loader_tx_valid, mmio_tx_valid; + wire [7:0] rx_data, loader_tx_data, mmio_tx_data; + wire load_en, load_valid, load_error; wire [27:0] load_addr; + wire [127:0] load_data, load_result; wire [15:0] load_mask; + uart_rx #(.DIVISOR(UART_DIVISOR)) receiver (.clk(clk),.reset(reset),.rx(uart_rx_in), + .valid(rx_valid),.data(rx_data),.frame_error(rx_error)); + uart_tx #(.DIVISOR(UART_DIVISOR)) transmitter (.clk(clk),.reset(reset), + .valid(cpu_run ? mmio_tx_valid : loader_tx_valid),.data(cpu_run ? mmio_tx_data : loader_tx_data), + .ready(tx_ready),.tx(uart_tx_out)); + ddr_uart_loader loader (.clk(clk),.reset(reset),.rx_valid(rx_valid && !cpu_run),.rx_data(rx_data), + .rx_error(rx_error),.tx_valid(loader_tx_valid),.tx_data(loader_tx_data),.tx_ready(tx_ready), + .cpu_run(loader_cpu_run),.error_seen(loader_error),.load_en(load_en),.load_addr(load_addr), + .load_data(load_data),.load_mask(load_mask),.load_valid(load_valid),.load_error(load_error),.load_result(load_result)); + wire memory_aw_ready; + wire memory_aw_valid; + wire [3:0] memory_aw_bits_id; + wire [31:0] memory_aw_bits_addr; + wire [7:0] memory_aw_bits_len; + wire [2:0] memory_aw_bits_size; + wire [1:0] memory_aw_bits_burst; + wire memory_aw_bits_lock; + wire [3:0] memory_aw_bits_cache; + wire [2:0] memory_aw_bits_prot; + wire [3:0] memory_aw_bits_qos; + wire memory_w_ready; + wire memory_w_valid; + wire [127:0] memory_w_bits_data; + wire [15:0] memory_w_bits_strb; + wire memory_w_bits_last; + wire memory_b_ready; + wire memory_b_valid; + wire [3:0] memory_b_bits_id; + wire [1:0] memory_b_bits_resp; + wire memory_ar_ready; + wire memory_ar_valid; + wire [3:0] memory_ar_bits_id; + wire [31:0] memory_ar_bits_addr; + wire [7:0] memory_ar_bits_len; + wire [2:0] memory_ar_bits_size; + wire [1:0] memory_ar_bits_burst; + wire memory_ar_bits_lock; + wire [3:0] memory_ar_bits_cache; + wire [2:0] memory_ar_bits_prot; + wire [3:0] memory_ar_bits_qos; + wire memory_r_ready; + wire memory_r_valid; + wire [3:0] memory_r_bits_id; + wire [127:0] memory_r_bits_data; + wire [1:0] memory_r_bits_resp; + wire memory_r_bits_last; + wire peripherals_aw_ready; + wire peripherals_aw_valid; + wire [1:0] peripherals_aw_bits_id; + wire [30:0] peripherals_aw_bits_addr; + wire [7:0] peripherals_aw_bits_len; + wire [2:0] peripherals_aw_bits_size; + wire [1:0] peripherals_aw_bits_burst; + wire peripherals_aw_bits_lock; + wire [3:0] peripherals_aw_bits_cache; + wire [2:0] peripherals_aw_bits_prot; + wire [3:0] peripherals_aw_bits_qos; + wire peripherals_w_ready; + wire peripherals_w_valid; + wire [63:0] peripherals_w_bits_data; + wire [7:0] peripherals_w_bits_strb; + wire peripherals_w_bits_last; + wire peripherals_b_ready; + wire peripherals_b_valid; + wire [1:0] peripherals_b_bits_id; + wire [1:0] peripherals_b_bits_resp; + wire peripherals_ar_ready; + wire peripherals_ar_valid; + wire [1:0] peripherals_ar_bits_id; + wire [30:0] peripherals_ar_bits_addr; + wire [7:0] peripherals_ar_bits_len; + wire [2:0] peripherals_ar_bits_size; + wire [1:0] peripherals_ar_bits_burst; + wire peripherals_ar_bits_lock; + wire [3:0] peripherals_ar_bits_cache; + wire [2:0] peripherals_ar_bits_prot; + wire [3:0] peripherals_ar_bits_qos; + wire peripherals_r_ready; + wire peripherals_r_valid; + wire [1:0] peripherals_r_bits_id; + wire [63:0] peripherals_r_bits_data; + wire [1:0] peripherals_r_bits_resp; + wire peripherals_r_bits_last; + ToyLinuxChip chip ( + .clock(clk), + .reset(cpu_reset), + .interrupt(irq), + .memory_aw_ready(memory_aw_ready), + .memory_aw_valid(memory_aw_valid), + .memory_aw_bits_id(memory_aw_bits_id), + .memory_aw_bits_addr(memory_aw_bits_addr), + .memory_aw_bits_len(memory_aw_bits_len), + .memory_aw_bits_size(memory_aw_bits_size), + .memory_aw_bits_burst(memory_aw_bits_burst), + .memory_aw_bits_lock(memory_aw_bits_lock), + .memory_aw_bits_cache(memory_aw_bits_cache), + .memory_aw_bits_prot(memory_aw_bits_prot), + .memory_aw_bits_qos(memory_aw_bits_qos), + .memory_w_ready(memory_w_ready), + .memory_w_valid(memory_w_valid), + .memory_w_bits_data(memory_w_bits_data), + .memory_w_bits_strb(memory_w_bits_strb), + .memory_w_bits_last(memory_w_bits_last), + .memory_b_ready(memory_b_ready), + .memory_b_valid(memory_b_valid), + .memory_b_bits_id(memory_b_bits_id), + .memory_b_bits_resp(memory_b_bits_resp), + .memory_ar_ready(memory_ar_ready), + .memory_ar_valid(memory_ar_valid), + .memory_ar_bits_id(memory_ar_bits_id), + .memory_ar_bits_addr(memory_ar_bits_addr), + .memory_ar_bits_len(memory_ar_bits_len), + .memory_ar_bits_size(memory_ar_bits_size), + .memory_ar_bits_burst(memory_ar_bits_burst), + .memory_ar_bits_lock(memory_ar_bits_lock), + .memory_ar_bits_cache(memory_ar_bits_cache), + .memory_ar_bits_prot(memory_ar_bits_prot), + .memory_ar_bits_qos(memory_ar_bits_qos), + .memory_r_ready(memory_r_ready), + .memory_r_valid(memory_r_valid), + .memory_r_bits_id(memory_r_bits_id), + .memory_r_bits_data(memory_r_bits_data), + .memory_r_bits_resp(memory_r_bits_resp), + .memory_r_bits_last(memory_r_bits_last), + .peripherals_aw_ready(peripherals_aw_ready), + .peripherals_aw_valid(peripherals_aw_valid), + .peripherals_aw_bits_id(peripherals_aw_bits_id), + .peripherals_aw_bits_addr(peripherals_aw_bits_addr), + .peripherals_aw_bits_len(peripherals_aw_bits_len), + .peripherals_aw_bits_size(peripherals_aw_bits_size), + .peripherals_aw_bits_burst(peripherals_aw_bits_burst), + .peripherals_aw_bits_lock(peripherals_aw_bits_lock), + .peripherals_aw_bits_cache(peripherals_aw_bits_cache), + .peripherals_aw_bits_prot(peripherals_aw_bits_prot), + .peripherals_aw_bits_qos(peripherals_aw_bits_qos), + .peripherals_w_ready(peripherals_w_ready), + .peripherals_w_valid(peripherals_w_valid), + .peripherals_w_bits_data(peripherals_w_bits_data), + .peripherals_w_bits_strb(peripherals_w_bits_strb), + .peripherals_w_bits_last(peripherals_w_bits_last), + .peripherals_b_ready(peripherals_b_ready), + .peripherals_b_valid(peripherals_b_valid), + .peripherals_b_bits_id(peripherals_b_bits_id), + .peripherals_b_bits_resp(peripherals_b_bits_resp), + .peripherals_ar_ready(peripherals_ar_ready), + .peripherals_ar_valid(peripherals_ar_valid), + .peripherals_ar_bits_id(peripherals_ar_bits_id), + .peripherals_ar_bits_addr(peripherals_ar_bits_addr), + .peripherals_ar_bits_len(peripherals_ar_bits_len), + .peripherals_ar_bits_size(peripherals_ar_bits_size), + .peripherals_ar_bits_burst(peripherals_ar_bits_burst), + .peripherals_ar_bits_lock(peripherals_ar_bits_lock), + .peripherals_ar_bits_cache(peripherals_ar_bits_cache), + .peripherals_ar_bits_prot(peripherals_ar_bits_prot), + .peripherals_ar_bits_qos(peripherals_ar_bits_qos), + .peripherals_r_ready(peripherals_r_ready), + .peripherals_r_valid(peripherals_r_valid), + .peripherals_r_bits_id(peripherals_r_bits_id), + .peripherals_r_bits_data(peripherals_r_bits_data), + .peripherals_r_bits_resp(peripherals_r_bits_resp), + .peripherals_r_bits_last(peripherals_r_bits_last) + ); + wire [3:0] c_awid; + wire [27:0] c_awaddr; + wire [7:0] c_awlen; + wire [2:0] c_awsize; + wire [1:0] c_awburst; + wire c_awvalid; + wire c_awready; + wire [127:0] c_wdata; + wire [15:0] c_wstrb; + wire c_wlast; + wire c_wvalid; + wire c_wready; + wire [3:0] c_bid; + wire [1:0] c_bresp; + wire c_bvalid; + wire c_bready; + wire [3:0] c_arid; + wire [27:0] c_araddr; + wire [7:0] c_arlen; + wire [2:0] c_arsize; + wire [1:0] c_arburst; + wire c_arvalid; + wire c_arready; + wire [3:0] c_rid; + wire [127:0] c_rdata; + wire [1:0] c_rresp; + wire c_rlast; + wire c_rvalid; + wire c_rready; + wire [3:0] l_awid; + wire [27:0] l_awaddr; + wire [7:0] l_awlen; + wire [2:0] l_awsize; + wire [1:0] l_awburst; + wire l_awvalid; + wire l_awready; + wire [127:0] l_wdata; + wire [15:0] l_wstrb; + wire l_wlast; + wire l_wvalid; + wire l_wready; + wire [3:0] l_bid; + wire [1:0] l_bresp; + wire l_bvalid; + wire l_bready; + wire [3:0] l_arid; + wire [27:0] l_araddr; + wire [7:0] l_arlen; + wire [2:0] l_arsize; + wire [1:0] l_arburst; + wire l_arvalid; + wire l_arready; + wire [3:0] l_rid; + wire [127:0] l_rdata; + wire [1:0] l_rresp; + wire l_rlast; + wire l_rvalid; + wire l_rready; + axi_fullwidth normalizer ( + .clk(clk), + .reset(reset), + .s_awid(memory_aw_bits_id), + .m_awid(c_awid), + .s_awaddr(memory_aw_bits_addr), + .m_awaddr(c_awaddr), + .s_awlen(memory_aw_bits_len), + .m_awlen(c_awlen), + .s_awsize(memory_aw_bits_size), + .m_awsize(c_awsize), + .s_awburst(memory_aw_bits_burst), + .m_awburst(c_awburst), + .s_awvalid(memory_aw_valid), + .m_awvalid(c_awvalid), + .s_awready(memory_aw_ready), + .m_awready(c_awready), + .s_wdata(memory_w_bits_data), + .m_wdata(c_wdata), + .s_wstrb(memory_w_bits_strb), + .m_wstrb(c_wstrb), + .s_wlast(memory_w_bits_last), + .m_wlast(c_wlast), + .s_wvalid(memory_w_valid), + .m_wvalid(c_wvalid), + .s_wready(memory_w_ready), + .m_wready(c_wready), + .s_bid(memory_b_bits_id), + .m_bid(c_bid), + .s_bresp(memory_b_bits_resp), + .m_bresp(c_bresp), + .s_bvalid(memory_b_valid), + .m_bvalid(c_bvalid), + .s_bready(memory_b_ready), + .m_bready(c_bready), + .s_arid(memory_ar_bits_id), + .m_arid(c_arid), + .s_araddr(memory_ar_bits_addr), + .m_araddr(c_araddr), + .s_arlen(memory_ar_bits_len), + .m_arlen(c_arlen), + .s_arsize(memory_ar_bits_size), + .m_arsize(c_arsize), + .s_arburst(memory_ar_bits_burst), + .m_arburst(c_arburst), + .s_arvalid(memory_ar_valid), + .m_arvalid(c_arvalid), + .s_arready(memory_ar_ready), + .m_arready(c_arready), + .s_rid(memory_r_bits_id), + .m_rid(c_rid), + .s_rdata(memory_r_bits_data), + .m_rdata(c_rdata), + .s_rresp(memory_r_bits_resp), + .m_rresp(c_rresp), + .s_rlast(memory_r_bits_last), + .m_rlast(c_rlast), + .s_rvalid(memory_r_valid), + .m_rvalid(c_rvalid), + .s_rready(memory_r_ready), + .m_rready(c_rready) + ); + loader_axi load_bridge ( + .clk(clk), + .reset(reset), + .load_en(load_en), + .load_addr(load_addr), + .load_data(load_data), + .load_mask(load_mask), + .load_valid(load_valid), + .load_error(load_error), + .load_result(load_result), + .awaddr(l_awaddr), + .araddr(l_araddr), + .awvalid(l_awvalid), + .wvalid(l_wvalid), + .arvalid(l_arvalid), + .bready(l_bready), + .rready(l_rready), + .awready(l_awready), + .wready(l_wready), + .arready(l_arready), + .bvalid(l_bvalid), + .rvalid(l_rvalid), + .wdata(l_wdata), + .wstrb(l_wstrb), + .bresp(l_bresp), + .rresp(l_rresp), + .rdata(l_rdata) + ); + assign l_awid=0; + assign l_arid=0; + assign l_awlen=0; + assign l_arlen=0; + assign l_awsize=4; + assign l_arsize=4; + assign l_awburst=1; + assign l_arburst=1; + assign l_wlast=1; + assign ddr_awid=cpu_run ? c_awid : l_awid; + assign ddr_awaddr=cpu_run ? c_awaddr : l_awaddr; + assign ddr_awlen=cpu_run ? c_awlen : l_awlen; + assign ddr_awsize=cpu_run ? c_awsize : l_awsize; + assign ddr_awburst=cpu_run ? c_awburst : l_awburst; + assign ddr_awvalid=cpu_run ? c_awvalid : l_awvalid; + assign c_awready=ddr_awready && cpu_run; + assign l_awready=ddr_awready && !cpu_run; + assign ddr_wdata=cpu_run ? c_wdata : l_wdata; + assign ddr_wstrb=cpu_run ? c_wstrb : l_wstrb; + assign ddr_wlast=cpu_run ? c_wlast : l_wlast; + assign ddr_wvalid=cpu_run ? c_wvalid : l_wvalid; + assign c_wready=ddr_wready && cpu_run; + assign l_wready=ddr_wready && !cpu_run; + assign c_bid=ddr_bid; + assign l_bid=ddr_bid; + assign c_bresp=ddr_bresp; + assign l_bresp=ddr_bresp; + assign c_bvalid=ddr_bvalid && cpu_run; + assign l_bvalid=ddr_bvalid && !cpu_run; + assign ddr_bready=cpu_run ? c_bready : l_bready; + assign ddr_arid=cpu_run ? c_arid : l_arid; + assign ddr_araddr=cpu_run ? c_araddr : l_araddr; + assign ddr_arlen=cpu_run ? c_arlen : l_arlen; + assign ddr_arsize=cpu_run ? c_arsize : l_arsize; + assign ddr_arburst=cpu_run ? c_arburst : l_arburst; + assign ddr_arvalid=cpu_run ? c_arvalid : l_arvalid; + assign c_arready=ddr_arready && cpu_run; + assign l_arready=ddr_arready && !cpu_run; + assign c_rid=ddr_rid; + assign l_rid=ddr_rid; + assign c_rdata=ddr_rdata; + assign l_rdata=ddr_rdata; + assign c_rresp=ddr_rresp; + assign l_rresp=ddr_rresp; + assign c_rlast=ddr_rlast; + assign l_rlast=ddr_rlast; + assign c_rvalid=ddr_rvalid && cpu_run; + assign l_rvalid=ddr_rvalid && !cpu_run; + assign ddr_rready=cpu_run ? c_rready : l_rready; + wire [1:0] scu_bresp; + assign peripherals_b_bits_resp=|scu_bresp; + axi_scu #(.FLASH_BOOT(FLASH_BOOT)) peripherals ( + .clk(clk), + .reset(cpu_reset), + .awid(peripherals_aw_bits_id), + .awaddr(peripherals_aw_bits_addr), + .awlen(peripherals_aw_bits_len), + .awsize(peripherals_aw_bits_size), + .awburst(peripherals_aw_bits_burst), + .awvalid(peripherals_aw_valid), + .awready(peripherals_aw_ready), + .wdata(peripherals_w_bits_data), + .wstrb(peripherals_w_bits_strb), + .wlast(peripherals_w_bits_last), + .wvalid(peripherals_w_valid), + .wready(peripherals_w_ready), + .bid(peripherals_b_bits_id), + .bresp(scu_bresp), + .bvalid(peripherals_b_valid), + .bready(peripherals_b_ready), + .arid(peripherals_ar_bits_id), + .araddr(peripherals_ar_bits_addr), + .arlen(peripherals_ar_bits_len), + .arsize(peripherals_ar_bits_size), + .arburst(peripherals_ar_bits_burst), + .arvalid(peripherals_ar_valid), + .arready(peripherals_ar_ready), + .rid(peripherals_r_bits_id), + .rdata(peripherals_r_bits_data), + .rresp(peripherals_r_bits_resp), + .rlast(peripherals_r_bits_last), + .rvalid(peripherals_r_valid), + .rready(peripherals_r_ready), + .rx_valid(rx_valid && cpu_run), + .rx_data(rx_data), + .rx_error(rx_error), + .tx_valid(mmio_tx_valid), + .tx_data(mmio_tx_data), + .tx_ready(tx_ready), + .exited(exited), + .exit_code(exit_code), + .interrupt(irq),.flash_miso(flash_miso),.flash_recovery(flash_recovery), + .flash_mosi(flash_mosi),.flash_sck(flash_sck),.flash_cs_n(flash_cs_n) + ); +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/toy_a7_top.sv b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/toy_a7_top.sv new file mode 100644 index 0000000..397a262 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/toy_a7_top.sv @@ -0,0 +1,305 @@ +module toy_a7_top #(parameter FLASH_BOOT=0) ( + input wire CLK100MHZ, btn0, uart_txd_in, output wire uart_rxd_out, output wire [3:0] led, + inout wire [15:0] ddr3_dq, inout wire [1:0] ddr3_dqs_n, ddr3_dqs_p, + output wire [13:0] ddr3_addr, output wire [2:0] ddr3_ba, + output wire ddr3_ras_n, ddr3_cas_n, ddr3_we_n, ddr3_reset_n, + output wire [0:0] ddr3_ck_p, ddr3_ck_n, ddr3_cke, ddr3_cs_n, ddr3_odt, output wire [1:0] ddr3_dm, + input wire sw0, flash_miso, + output wire flash_mosi, flash_cs_n, flash_wp_n, flash_hold_n +); + wire clk_in,fb,fb_buf,core_raw,sys_raw,ref_raw,clk,sys_clk,ref_clk,locked; + IBUF input_clock (.I(CLK100MHZ),.O(clk_in)); + MMCME2_BASE #(.CLKIN1_PERIOD(10.0),.DIVCLK_DIVIDE(1),.CLKFBOUT_MULT_F(10.0), + .CLKOUT0_DIVIDE_F(40.0),.CLKOUT1_DIVIDE(6),.CLKOUT2_DIVIDE(5)) clock_mmcm ( + .CLKIN1(clk_in),.CLKFBIN(fb_buf),.CLKFBOUT(fb),.CLKOUT0(core_raw), + .CLKOUT1(sys_raw),.CLKOUT2(ref_raw),.LOCKED(locked),.RST(1'b0),.PWRDWN(1'b0)); + BUFG fb_buffer (.I(fb),.O(fb_buf)); BUFG core_buffer (.I(core_raw),.O(clk)); + BUFG sys_buffer (.I(sys_raw),.O(sys_clk)); BUFG ref_buffer (.I(ref_raw),.O(ref_clk)); + wire ui_clk,ui_rst,mig_locked,calibrated; + wire flash_sck; + assign flash_wp_n=1;assign flash_hold_n=1; + generate if(FLASH_BOOT) begin : flash_clock + STARTUPE2 startup (.CLK(1'b0),.GSR(1'b0),.GTS(1'b0),.KEYCLEARB(1'b1),.PACK(1'b0), + .USRCCLKO(flash_sck),.USRCCLKTS(1'b0),.USRDONEO(1'b1),.USRDONETS(1'b1), + .CFGCLK(),.CFGMCLK(),.EOS(),.PREQ()); + end endgenerate + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg sw_meta=0,sw_sync=0; + reg flash_recovery=0; + always @(posedge clk) begin + sw_meta<=sw0;sw_sync<=sw_meta; + if(reset) flash_recovery<=sw_sync; + end + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg [2:0] lock_sync=7; + always @(posedge clk or negedge locked) if(!locked) lock_sync<=7;else lock_sync<={lock_sync[1:0],1'b0}; + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg btn_meta=0,btn_sync=0; + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg btn_ref_meta=0,btn_ref_sync=0; + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg [2:0] mig_resetn_pipe=0; + always @(posedge ref_clk) begin btn_ref_meta<=btn0;btn_ref_sync<=btn_ref_meta;end + always @(posedge ref_clk or negedge locked) if(!locked) mig_resetn_pipe<=0; + else mig_resetn_pipe<={mig_resetn_pipe[1:0],!btn_ref_sync}; + wire mig_resetn=mig_resetn_pipe[2]; + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg [1:0] calib_sync=0; + always @(posedge clk) begin btn_meta<=btn0;btn_sync<=btn_meta;calib_sync<={calib_sync[0],calibrated};end + reg [17:0] reset_count=0;wire reset=lock_sync[2] || btn_sync || !calib_sync[1] || !(&reset_count); + always @(posedge clk) if(lock_sync[2] || btn_sync || !calib_sync[1]) reset_count<=0; + else if(!(&reset_count)) reset_count<=reset_count+1'b1; + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg [2:0] ui_reset_pipe=7; + always @(posedge ui_clk or posedge ui_rst) if(ui_rst) ui_reset_pipe<=7; + else ui_reset_pipe<={ui_reset_pipe[1:0],1'b0}; + wire ui_aresetn=~ui_reset_pipe[2]; + wire cpu_run,exited,loader_error;wire [31:0] exit_code;reg [24:0] heartbeat=0; + always @(posedge clk) if(reset) heartbeat<=0;else heartbeat<=heartbeat+1'b1; + assign led={heartbeat[24],cpu_run && !reset,loader_error || (exited && exit_code!=0),calib_sync[1]}; + wire [3:0] ddr_awid; + wire [27:0] ddr_awaddr; + wire [7:0] ddr_awlen; + wire [2:0] ddr_awsize; + wire [1:0] ddr_awburst; + wire ddr_awvalid; + wire ddr_awready; + wire [127:0] ddr_wdata; + wire [15:0] ddr_wstrb; + wire ddr_wlast; + wire ddr_wvalid; + wire ddr_wready; + wire [3:0] ddr_bid; + wire [1:0] ddr_bresp; + wire ddr_bvalid; + wire ddr_bready; + wire [3:0] ddr_arid; + wire [27:0] ddr_araddr; + wire [7:0] ddr_arlen; + wire [2:0] ddr_arsize; + wire [1:0] ddr_arburst; + wire ddr_arvalid; + wire ddr_arready; + wire [3:0] ddr_rid; + wire [127:0] ddr_rdata; + wire [1:0] ddr_rresp; + wire ddr_rlast; + wire ddr_rvalid; + wire ddr_rready; + wire [3:0] ui_awid; + wire [27:0] ui_awaddr; + wire [7:0] ui_awlen; + wire [2:0] ui_awsize; + wire [1:0] ui_awburst; + wire ui_awvalid; + wire ui_awready; + wire [127:0] ui_wdata; + wire [15:0] ui_wstrb; + wire ui_wlast; + wire ui_wvalid; + wire ui_wready; + wire [3:0] ui_bid; + wire [1:0] ui_bresp; + wire ui_bvalid; + wire ui_bready; + wire [3:0] ui_arid; + wire [27:0] ui_araddr; + wire [7:0] ui_arlen; + wire [2:0] ui_arsize; + wire [1:0] ui_arburst; + wire ui_arvalid; + wire ui_arready; + wire [3:0] ui_rid; + wire [127:0] ui_rdata; + wire [1:0] ui_rresp; + wire ui_rlast; + wire ui_rvalid; + wire ui_rready; + toy_a7_platform #(.FLASH_BOOT(FLASH_BOOT)) platform ( + .clk(clk), + .reset(reset), + .uart_rx_in(uart_txd_in), + .uart_tx_out(uart_rxd_out), + .cpu_run(cpu_run), + .exited(exited), + .loader_error(loader_error), + .exit_code(exit_code), + .flash_miso(flash_miso),.flash_mosi(flash_mosi),.flash_sck(flash_sck), + .flash_cs_n(flash_cs_n),.flash_recovery(flash_recovery), + .ddr_awid(ddr_awid), + .ddr_awaddr(ddr_awaddr), + .ddr_awlen(ddr_awlen), + .ddr_awsize(ddr_awsize), + .ddr_awburst(ddr_awburst), + .ddr_awvalid(ddr_awvalid), + .ddr_awready(ddr_awready), + .ddr_wdata(ddr_wdata), + .ddr_wstrb(ddr_wstrb), + .ddr_wlast(ddr_wlast), + .ddr_wvalid(ddr_wvalid), + .ddr_wready(ddr_wready), + .ddr_bid(ddr_bid), + .ddr_bresp(ddr_bresp), + .ddr_bvalid(ddr_bvalid), + .ddr_bready(ddr_bready), + .ddr_arid(ddr_arid), + .ddr_araddr(ddr_araddr), + .ddr_arlen(ddr_arlen), + .ddr_arsize(ddr_arsize), + .ddr_arburst(ddr_arburst), + .ddr_arvalid(ddr_arvalid), + .ddr_arready(ddr_arready), + .ddr_rid(ddr_rid), + .ddr_rdata(ddr_rdata), + .ddr_rresp(ddr_rresp), + .ddr_rlast(ddr_rlast), + .ddr_rvalid(ddr_rvalid), + .ddr_rready(ddr_rready) + ); + toy_axi_cdc memory_cdc ( + .s_axi_aclk(clk), + .s_axi_aresetn(!reset), + .m_axi_aclk(ui_clk), + .m_axi_aresetn(ui_aresetn), + .s_axi_awid(ddr_awid), + .s_axi_awaddr(ddr_awaddr), + .s_axi_awlen(ddr_awlen), + .s_axi_awsize(ddr_awsize), + .s_axi_awburst(ddr_awburst), + .s_axi_awvalid(ddr_awvalid), + .s_axi_awready(ddr_awready), + .s_axi_wdata(ddr_wdata), + .s_axi_wstrb(ddr_wstrb), + .s_axi_wlast(ddr_wlast), + .s_axi_wvalid(ddr_wvalid), + .s_axi_wready(ddr_wready), + .s_axi_bid(ddr_bid), + .s_axi_bresp(ddr_bresp), + .s_axi_bvalid(ddr_bvalid), + .s_axi_bready(ddr_bready), + .s_axi_arid(ddr_arid), + .s_axi_araddr(ddr_araddr), + .s_axi_arlen(ddr_arlen), + .s_axi_arsize(ddr_arsize), + .s_axi_arburst(ddr_arburst), + .s_axi_arvalid(ddr_arvalid), + .s_axi_arready(ddr_arready), + .s_axi_rid(ddr_rid), + .s_axi_rdata(ddr_rdata), + .s_axi_rresp(ddr_rresp), + .s_axi_rlast(ddr_rlast), + .s_axi_rvalid(ddr_rvalid), + .s_axi_rready(ddr_rready), + .s_axi_awlock(1'b0), + .s_axi_arlock(1'b0), + .s_axi_awcache(4'b0011), + .s_axi_arcache(4'b0011), + .s_axi_awprot(3'd0), + .s_axi_arprot(3'd0), + .s_axi_awqos(4'd0), + .s_axi_arqos(4'd0), + .s_axi_awregion(4'd0), + .s_axi_arregion(4'd0), + .m_axi_awid(ui_awid), + .m_axi_awaddr(ui_awaddr), + .m_axi_awlen(ui_awlen), + .m_axi_awsize(ui_awsize), + .m_axi_awburst(ui_awburst), + .m_axi_awvalid(ui_awvalid), + .m_axi_awready(ui_awready), + .m_axi_wdata(ui_wdata), + .m_axi_wstrb(ui_wstrb), + .m_axi_wlast(ui_wlast), + .m_axi_wvalid(ui_wvalid), + .m_axi_wready(ui_wready), + .m_axi_bid(ui_bid), + .m_axi_bresp(ui_bresp), + .m_axi_bvalid(ui_bvalid), + .m_axi_bready(ui_bready), + .m_axi_arid(ui_arid), + .m_axi_araddr(ui_araddr), + .m_axi_arlen(ui_arlen), + .m_axi_arsize(ui_arsize), + .m_axi_arburst(ui_arburst), + .m_axi_arvalid(ui_arvalid), + .m_axi_arready(ui_arready), + .m_axi_rid(ui_rid), + .m_axi_rdata(ui_rdata), + .m_axi_rresp(ui_rresp), + .m_axi_rlast(ui_rlast), + .m_axi_rvalid(ui_rvalid), + .m_axi_rready(ui_rready), + .m_axi_awlock(), + .m_axi_arlock(), + .m_axi_awcache(), + .m_axi_arcache(), + .m_axi_awprot(), + .m_axi_arprot(), + .m_axi_awqos(), + .m_axi_arqos(), + .m_axi_awregion(), + .m_axi_arregion() + ); + arty_ddr3 ddr_controller ( + .ddr3_dq(ddr3_dq), + .ddr3_dqs_n(ddr3_dqs_n), + .ddr3_dqs_p(ddr3_dqs_p), + .ddr3_addr(ddr3_addr), + .ddr3_ba(ddr3_ba), + .ddr3_ras_n(ddr3_ras_n), + .ddr3_cas_n(ddr3_cas_n), + .ddr3_we_n(ddr3_we_n), + .ddr3_reset_n(ddr3_reset_n), + .ddr3_ck_p(ddr3_ck_p), + .ddr3_ck_n(ddr3_ck_n), + .ddr3_cke(ddr3_cke), + .ddr3_cs_n(ddr3_cs_n), + .ddr3_dm(ddr3_dm), + .ddr3_odt(ddr3_odt), + .sys_clk_i(sys_clk), + .clk_ref_i(ref_clk), + .sys_rst(mig_resetn), + .ui_clk(ui_clk), + .ui_clk_sync_rst(ui_rst), + .mmcm_locked(mig_locked), + .aresetn(ui_aresetn), + .init_calib_complete(calibrated), + .device_temp(), + .app_sr_req(1'b0), + .app_ref_req(1'b0), + .app_zq_req(1'b0), + .app_sr_active(), + .app_ref_ack(), + .app_zq_ack(), + .s_axi_awid(ui_awid), + .s_axi_awaddr(ui_awaddr), + .s_axi_awlen(ui_awlen), + .s_axi_awsize(ui_awsize), + .s_axi_awburst(ui_awburst), + .s_axi_awvalid(ui_awvalid), + .s_axi_awready(ui_awready), + .s_axi_wdata(ui_wdata), + .s_axi_wstrb(ui_wstrb), + .s_axi_wlast(ui_wlast), + .s_axi_wvalid(ui_wvalid), + .s_axi_wready(ui_wready), + .s_axi_bid(ui_bid), + .s_axi_bresp(ui_bresp), + .s_axi_bvalid(ui_bvalid), + .s_axi_bready(ui_bready), + .s_axi_arid(ui_arid), + .s_axi_araddr(ui_araddr), + .s_axi_arlen(ui_arlen), + .s_axi_arsize(ui_arsize), + .s_axi_arburst(ui_arburst), + .s_axi_arvalid(ui_arvalid), + .s_axi_arready(ui_arready), + .s_axi_rid(ui_rid), + .s_axi_rdata(ui_rdata), + .s_axi_rresp(ui_rresp), + .s_axi_rlast(ui_rlast), + .s_axi_rvalid(ui_rvalid), + .s_axi_rready(ui_rready), + .s_axi_awlock(1'b0), + .s_axi_arlock(1'b0), + .s_axi_awcache(4'b0011), + .s_axi_arcache(4'b0011), + .s_axi_awprot(3'd0), + .s_axi_arprot(3'd0), + .s_axi_awqos(4'd0), + .s_axi_arqos(4'd0) + ); +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/uart_rx.sv b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/uart_rx.sv new file mode 100644 index 0000000..567b8b4 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/uart_rx.sv @@ -0,0 +1,40 @@ +// 8-N-1 receiver. Data is sampled in the middle of each bit after a verified +// start bit. A held-low/broken line reports one framing error, then waits high. +module uart_rx #( + parameter integer DIVISOR = 434 +) ( + input wire clk, reset, rx, + output reg valid, + output reg [7:0] data, + output reg frame_error +); + (* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) reg rx_meta = 1, rx_sync = 1; + always @(posedge clk) begin rx_meta <= rx; rx_sync <= rx_meta; end + localparam integer WIDTH = $clog2(DIVISOR) < 1 ? 1 : $clog2(DIVISOR); + localparam [2:0] IDLE=0, START=1, DATA=2, STOP=3, WAIT_HIGH=4; + reg [2:0] state, bit_index; + reg [WIDTH-1:0] count; + reg [7:0] shift; + always @(posedge clk) begin + valid <= 0; frame_error <= 0; + if (reset) begin + state <= IDLE; bit_index <= 0; count <= 0; shift <= 0; data <= 0; + end else case (state) + IDLE: if (!rx_sync) begin state <= START; count <= DIVISOR/2 - 1; end + START: if (count != 0) count <= count - 1'b1; + else if (rx_sync) state <= IDLE; + else begin state <= DATA; bit_index <= 0; count <= DIVISOR - 1; end + DATA: if (count != 0) count <= count - 1'b1; + else begin + shift[bit_index] <= rx_sync; count <= DIVISOR - 1; + if (bit_index == 7) state <= STOP; + else bit_index <= bit_index + 1'b1; + end + STOP: if (count != 0) count <= count - 1'b1; + else if (rx_sync) begin data <= shift; valid <= 1; state <= IDLE; end + else begin frame_error <= 1; state <= WAIT_HIGH; end + WAIT_HIGH: if (rx_sync) state <= IDLE; + default: state <= IDLE; + endcase + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/uart_tx.sv b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/uart_tx.sv new file mode 100644 index 0000000..11f6e4a --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/uart_tx.sv @@ -0,0 +1,37 @@ +module uart_tx #( + parameter integer DIVISOR = 434 // 50 MHz / 115200, error < 0.01%. +) ( + input wire clk, + input wire reset, + input wire valid, + input wire [7:0] data, + output wire ready, + output wire tx +); + localparam integer COUNT_BITS = $clog2(DIVISOR) < 1 ? 1 : $clog2(DIVISOR); + reg [COUNT_BITS-1:0] count; + reg [9:0] shift; + reg [3:0] bits_left; + assign ready = bits_left == 0; + assign tx = shift[0]; + + always @(posedge clk) begin + if (reset) begin + count <= 0; + shift <= 10'h3ff; + bits_left <= 0; + end else if (ready) begin + if (valid) begin + shift <= {1'b1, data, 1'b0}; + bits_left <= 10; + count <= DIVISOR - 1; + end + end else if (count == 0) begin + shift <= {1'b1, shift[9:1]}; + bits_left <= bits_left - 1'b1; + count <= DIVISOR - 1; + end else begin + count <= count - 1'b1; + end + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/vendor/License.txt b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/vendor/License.txt new file mode 100644 index 0000000..b76cf0c --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/vendor/License.txt @@ -0,0 +1,21 @@ +MIT License + +Copyright (c) 2021 Digilent, Inc. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. \ No newline at end of file diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/vendor/MANIFEST.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/vendor/MANIFEST.json new file mode 100644 index 0000000..ae5699f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/vendor/MANIFEST.json @@ -0,0 +1,24 @@ +{ + "repository": "Digilent/vivado-boards", + "commit": "36f34ab687b7fa9c778b779d027f3bce63b3ace9", + "vendor_revision": "E.0", + "physical_board_revision": "unknown", + "files": { + "board.xml": { + "url": "https://raw.githubusercontent.com/Digilent/vivado-boards/36f34ab687b7fa9c778b779d027f3bce63b3ace9/new/board_files/arty-a7-100/E.0/1.0/board.xml", + "sha256": "5bd9a7ca97ccb2fef617515a14401166464b45a06684d663c0be1a06b02a86df" + }, + "part0_pins.xml": { + "url": "https://raw.githubusercontent.com/Digilent/vivado-boards/36f34ab687b7fa9c778b779d027f3bce63b3ace9/new/board_files/arty-a7-100/E.0/1.0/part0_pins.xml", + "sha256": "50aa844aa9c78af6342de68ae3c980f7618716447b28282878d5a106f86fed31" + }, + "mig.prj": { + "url": "https://raw.githubusercontent.com/Digilent/vivado-boards/36f34ab687b7fa9c778b779d027f3bce63b3ace9/new/board_files/arty-a7-100/E.0/1.0/mig.prj", + "sha256": "914a9e4bb1b3002837592944cdf49f8dfbaf4d112552dd8b5be48602ff1ac329" + }, + "preset.xml": { + "url": "https://raw.githubusercontent.com/Digilent/vivado-boards/36f34ab687b7fa9c778b779d027f3bce63b3ace9/new/board_files/arty-a7-100/E.0/1.0/preset.xml", + "sha256": "ff95b9b976323fefa588873588dfa2bdce1673759c0a9e91c12ee9f2a2955bce" + } + } +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/vendor/board.xml b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/vendor/board.xml new file mode 100644 index 0000000..50f4535 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/vendor/board.xml @@ -0,0 +1,1247 @@ + + + + + E.0 + +1.0 +Arty A7-100 + + + + + DDR3 board interface, it can use MIG IP for connection. + + + + + + 4-position user DIP Switches + + + + + + + + + + + + + + + + Secondary interface to communicate with ethernet phy. + + + + + + + + + + + + + + + + + + + + + + + + + Primary interface to communicate with ethernet phy in MII mode. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Shield I2C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + I2C Pullups to enable shield I2C + + + + + + + + + + + + + + 4 LEDs + + + + + + + + + + + + + + + + 4 Push Buttons + + + + + + + + + + + + + + + + Quad SPI Flash + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Onboard Reset Button + + + + + + + + + + + + + + + + 4 RGB LEDs + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 256 MB DDR3L memory SODIMM + + + + + + + DIP Switches 3 to 0 + + + PHY Ethernet on the board + + + + + + + + + + + Shield i2c + + + Shield i2c pullups, must pull high if using the shield I2C on J3 + + + LEDs 3 to 0 + + + Push buttons 3 to 0 + + + 16 MB of nonvolatile storage that can be used for configuration or data storage + + + CPU Reset Push Button, active low + + + RGB leds 12 to 0 (3 per LED) + + + Shield pins 0 through 19 + + + Shield pins 26 through 41 + + + Shield SPI + + + 3.3V Single-Ended 100MHz oscillator used as system clock on the board + + + USB-to-UART Bridge, which allows a connection to a host computer with a USB port + + + Pmod Connector JA + + + Pmod Connector JB + + + Pmod Connector JC + + + Pmod Connector JD + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/vendor/mig.prj b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/vendor/mig.prj new file mode 100644 index 0000000..1bff709 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/vendor/mig.prj @@ -0,0 +1,134 @@ + + + + design_1_mig_7series_0_0 + 1 + 1 + OFF + 1024 + ON + Enabled + xc7a100t-csg324/-1 + 2.3 + No Buffer + No Buffer + ACTIVE LOW + FALSE + 1 + 50 Ohms + 0 + + DDR3_SDRAM/Components/MT41K128M16XX-15E + 3000 + 1.8V + 4:1 + 166.666 + 0 + 666 + 1.000 + 1 + 1 + 1 + 1 + 16 + 1 + 1 + Disabled + Normal + FALSE + + 14 + 10 + 3 + 1.35V + 268435456 + BANK_ROW_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 5 + Normal + No + Slow Exit + Enable + RZQ/6 + Disable + Enable + RZQ/6 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 5 + Enabled + Normal + Dynamic ODT off + AXI + + RD_PRI_REG + 28 + 128 + 4 + 0 + + + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/vendor/part0_pins.xml b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/vendor/part0_pins.xml new file mode 100644 index 0000000..dc32e54 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/vendor/part0_pins.xml @@ -0,0 +1,156 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/vendor/preset.xml b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/vendor/preset.xml new file mode 100644 index 0000000..ec20fb4 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/vendor/preset.xml @@ -0,0 +1,418 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/build.sbt b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/build.sbt new file mode 100644 index 0000000..79eb11f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/build.sbt @@ -0,0 +1,70 @@ +ThisBuild / scalaVersion := "2.13.16" +ThisBuild / organization := "srtp.fpga" +ThisBuild / version := "0.1.0" +ThisBuild / scalacOptions ++= Seq("-language:reflectiveCalls", "-Ymacro-annotations", "-deprecation", "-feature") + +lazy val chiselSettings = Seq( + scalaVersion := "2.13.16", + libraryDependencies += "org.chipsalliance" %% "chisel" % "6.7.0", + addCompilerPlugin("org.chipsalliance" % "chisel-plugin" % "6.7.0" cross CrossVersion.full) +) +lazy val cde = project.in(file("thirdparty/cde")).settings(chiselSettings).settings( + Compile / unmanagedSourceDirectories += baseDirectory.value / "cde/src/chipsalliance" +) +lazy val diplomacy = project.in(file("thirdparty/diplomacy/diplomacy")).dependsOn(cde).settings(chiselSettings).settings( + Compile / unmanagedSourceDirectories += baseDirectory.value / "src/diplomacy", + libraryDependencies += "com.lihaoyi" %% "sourcecode" % "0.3.0" +) +lazy val hardfloat = project.in(file("thirdparty/hardfloat/hardfloat")).dependsOn(cde).settings(chiselSettings) +lazy val macros = project.in(file("thirdparty/rocket-chip/macros")).settings( + libraryDependencies += "org.scala-lang" % "scala-reflect" % "2.13.16" +) +lazy val rocket = project.in(file("thirdparty/rocket-chip")).dependsOn(cde, diplomacy, hardfloat, macros).settings(chiselSettings).settings( + Compile / unmanagedSources := { + val original = ((baseDirectory.value / "src/main/scala") ** "*.scala").get + original.filterNot(f => f.getName == "FPU.scala") ++ + ((baseDirectory.value / "../../patches/rocket") ** "*.scala").get + }, + libraryDependencies ++= Seq( + "com.lihaoyi" %% "mainargs" % "0.5.0", + "org.json4s" %% "json4s-jackson" % "4.0.5", + "org.scala-graph" %% "graph-core" % "1.13.5" + ) +) +lazy val inclusive = project.in(file("thirdparty/inclusive-cache")).dependsOn(rocket).settings(chiselSettings).settings( + Compile / unmanagedSourceDirectories += baseDirectory.value / "design/craft" +) +lazy val midas = project.in(file("thirdparty/firesim-compile")).settings(chiselSettings).settings( + Compile / unmanagedSourceDirectories += baseDirectory.value / "../firesim/sim/midas/targetutils/src/main/scala" +) +lazy val gemmini = project.in(file("thirdparty/gemmini-compile")).dependsOn(rocket, midas).settings(chiselSettings).settings( + Compile / unmanagedSources := { + val original = ((baseDirectory.value / "../gemmini/src/main/scala") ** "*.scala").get + original.filterNot(f => Set("PE.scala", "Tile.scala", "Mesh.scala")(f.getName)) ++ + ((baseDirectory.value / "../../patches/gemmini") ** "*.scala").get + }, + Compile / unmanagedResourceDirectories += baseDirectory.value / "../gemmini/src/main/resources" +) +lazy val root = project.in(file(".")).dependsOn(inclusive, gemmini).settings(chiselSettings).settings( + name := "toy-arty-a7-linux", + libraryDependencies ++= Seq( + "com.lihaoyi" %% "upickle" % "3.3.1", + "tech.sparse" %% "toml-scala" % "0.2.2" + ), + Compile / unmanagedSources ++= { + val upstream = baseDirectory.value / "upstream" + val framework = upstream / "arch/src/main/scala/framework" + val directories = Seq("balldomain", "builtin", "dpi", "frontend", "gpdomain", "memdomain", "top", + "system/core/rocket", "system/core/accelerator", "system/tile") + val shared = directories.flatMap(d => ((framework / d) ** "*.scala").get) + .filterNot(f => Set("WithBuckyballTiles.scala", "WithBoomTile.scala", "MemMidend.scala", "MemStorer.scala", "PrivateMemBackend.scala", "SubROB.scala", "GlobalROB.scala", "MemFrontend.scala", "MemLoader.scala")(f.getName)) + shared ++ ((baseDirectory.value / "patches/framework") ** "*.scala").get ++ + ((baseDirectory.value / "patches/buckyball") ** "*.scala").get ++ ((upstream / "arch/src/main/scala/sims/hash") ** "*.scala").get ++ Seq("gemmini", "trace", "mxfp2int", "relu").flatMap { name => + val ball = upstream / "examples/balls" / name + ((ball / "arch/src/main/scala") ** "*.scala").get.filterNot(f => + Set("GemminiExCtrl.scala", "GemminiExCtrlDefs.scala", + "GemminiExCtrlComputeFeedState.scala", "GemminiExCtrlStoreOps.scala", + "GemminiExCtrlPreloadStates.scala", "GemminiExCtrlCmdStates.scala", "GemminiBall.scala", "LoopMatmulUnroller.scala")(f.getName)) ++ ((ball / "configs") ** "*.scala").get + } + } +) diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/patches/framework/GlobalROB.scala b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/patches/framework/GlobalROB.scala new file mode 100644 index 0000000..750c2a3 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/patches/framework/GlobalROB.scala @@ -0,0 +1,599 @@ +package framework.frontend.globalrs + +import chisel3._ +import chisel3.util._ +import chisel3.experimental._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import framework.top.GlobalConfig +import framework.frontend.decoder.{DomainId, PostGDCmd} +import framework.frontend.scoreboard.{BankAccessInfo, BankAliasTable, BankScoreboard} +import framework.memdomain.frontend.cmd.decoder.DISA.MSET_BITPAT +import framework.memdomain.backend.shared.SharedMemLayout +import framework.memdomain.backend.banks.btrace.{BTraceDPI, PhysicalBankHash} + +@instantiable +class GlobalROB(val b: GlobalConfig, useOperandRam: Boolean = true) extends Module { + + val robDepth = b.frontend.rob_entries + val idWidth = log2Up(robDepth) + val scoreBankNum = b.memDomain.virtualBankCount + robDepth + val sharedHashCount = if (b.memDomain.sharedEnable) SharedMemLayout.totalBank(b) else 0 + val physicalBankCount = b.memDomain.bankNum + sharedHashCount + + require( + b.frontend.vbank_id_upper_bound < b.memDomain.virtualBankCount, + s"vbank_id_upper_bound(${b.frontend.vbank_id_upper_bound}) must be < virtualBankCount(${b.memDomain.virtualBankCount})" + ) + + @public + val io = IO(new Bundle { + val hart_id = Input(UInt(b.tile.xLen.W)) + val alloc = Flipped(new DecoupledIO(new PostGDCmd(b))) + val issue = new DecoupledIO(new GlobalRobEntry(b)) + val complete = Flipped(new DecoupledIO(UInt(idWidth.W))) + + val empty = Output(Bool()) + val full = Output(Bool()) + val head_ptr = Output(UInt(idWidth.W)) + val issued_count = Output(UInt(log2Up(robDepth + 1).W)) + val entry_valid = Output(Vec(robDepth, Bool())) + val entry_complete = Output(Vec(robDepth, Bool())) + + val subRobActive = Input(Bool()) + val inst_ids = Output(Vec(robDepth, UInt(64.W))) + + val bank_hashes = + if (b.sim.diffTest) { + Some(Input(Vec(physicalBankCount, new PhysicalBankHash(b)))) + } else { + None + } + + }) + + // --------------------------------------------------------------------------- + // BAT + Bank Scoreboard + // --------------------------------------------------------------------------- + val bat: Instance[BankAliasTable] = Instantiate( + new BankAliasTable( + bankIdLen = b.frontend.bank_id_len, + vbankUpper = b.memDomain.virtualBankCount - 1, + robEntries = robDepth + ) + ) + + val scoreboard: Instance[BankScoreboard] = + Instantiate(new BankScoreboard(b.frontend.bank_id_len, scoreBankNum, robDepth)) + + // --------------------------------------------------------------------------- + // Instruction trace (DPI-C, defined in ITraceDPI.scala) + // --------------------------------------------------------------------------- + val itraceAlloc = Module(new ITraceDPI) + val itraceIssue = Module(new ITraceDPI) + val itraceComp = Module(new ITraceDPI) + + for (t <- Seq(itraceAlloc, itraceIssue, itraceComp)) { + t.io.clock := clock + t.io.reset := reset.asBool + t.io.is_issue := 0.U + t.io.hart_id := io.hart_id + t.io.rob_id := 0.U + t.io.inst_id := 0.U + t.io.domain_id := 0.U + t.io.funct := 0.U + t.io.pc := 0.U + t.io.rs1_data := 0.U + t.io.rs2_data := 0.U + t.io.enable := false.B + } + + // --------------------------------------------------------------------------- + // Storage + // --------------------------------------------------------------------------- + val robEntries = RegInit(VecInit(Seq.fill(robDepth)(0.U.asTypeOf(new GlobalRobEntry(b))))) + // Only the issued payload needs the full operands. Keep existing copies for + // trace/commit observation; Vivado removes trace-only bits with DPI disabled. + // MSET's low rs2 bits stay in registers for the parallel commit scan. + private val operandWidth = b.tile.xLen + private val operandRam = if (useOperandRam) { + Some(SyncReadMem(robDepth, UInt((2 * operandWidth).W)).suggestName("robOperands")) + } else None + val robValid = RegInit(VecInit(Seq.fill(robDepth)(false.B))) + val robIssued = RegInit(VecInit(Seq.fill(robDepth)(false.B))) + val robComplete = RegInit(VecInit(Seq.fill(robDepth)(false.B))) + val instIds = RegInit(VecInit(Seq.fill(robDepth)(0.U(64.W)))) + val nextInstId = RegInit(1.U(64.W)) + + val statusHashes = + if (b.sim.diffTest) { + Some(RegInit(VecInit(Seq.fill(robDepth)(VecInit(Seq.fill(3)(0.U(32.W))))))) + } else { + None + } + + io.inst_ids := instIds + + val headPtr = RegInit(0.U(idWidth.W)) + val tailPtr = RegInit(0.U(idWidth.W)) + val issuedCount = RegInit(0.U(log2Up(robDepth + 1).W)) + private val bankColWidth = b.memDomain.groupCountWidth + val bankCols = RegInit(VecInit(Seq.fill(b.memDomain.virtualBankCount)(0.U(bankColWidth.W)))) + // In-flight ownership is tracked in the architectural vbank namespace. + private val vbankMaskWidth = b.memDomain.virtualBankCount + val vbankBusy = RegInit(0.U(vbankMaskWidth.W)) + + // Dependency state is maintained incrementally instead of rebuilding all + // older-entry comparisons every cycle. A bit in slot k names the ROB slot + // that currently blocks k. Ordinary RAW dependencies disappear at complete; + // dependencies involving a mapping/config instruction disappear at commit. + // Keeping one union mask is sufficient because a config dependency is never + // allowed to clear earlier than commit, even when it also looks like a RAW. + val dependencyMask = RegInit(VecInit(Seq.fill(robDepth)(0.U(robDepth.W)))) + + val isEmpty = headPtr === tailPtr && !robValid(headPtr) + val isFull = headPtr === tailPtr && robValid(headPtr) + + def nextPtr(p: UInt): UInt = Mux(p === (robDepth - 1).U, 0.U, p + 1.U) + def wrapPtr(v: UInt): UInt = Mux(v >= robDepth.U, v - robDepth.U, v) + def robIdx(v: UInt): UInt = v(idWidth - 1, 0) + + def isMappingConfig(entry: GlobalRobEntry): Bool = + entry.cmd.domain_id === DomainId.MEM && + (entry.cmd.cmd.funct === MSET_BITPAT) + + def accessUsesBank(access: BankAccessInfo, bank: UInt): Bool = + (access.rd_bank_0_valid && access.rd_bank_0_id === bank) || + (access.rd_bank_1_valid && access.rd_bank_1_id === bank) || + (access.wr_bank_valid && access.wr_bank_id === bank) + + // Build one architectural-vbank mask per ROB slot once, then hazard checks + // become mask intersections instead of repeating ID comparisons. + private val hazardBankCount = b.memDomain.virtualBankCount + + def rawReadMask(access: BankAccessInfo): UInt = { + val rd0 = Mux( + access.rd_bank_0_valid && access.rd_bank_0_id < hazardBankCount.U, + UIntToOH(access.rd_bank_0_id, hazardBankCount), + 0.U(hazardBankCount.W) + ) + val rd1 = Mux( + access.rd_bank_1_valid && access.rd_bank_1_id < hazardBankCount.U, + UIntToOH(access.rd_bank_1_id, hazardBankCount), + 0.U(hazardBankCount.W) + ) + rd0 | rd1 + } + + def rawWriteMask(access: BankAccessInfo): UInt = Mux( + access.wr_bank_valid && access.wr_bank_id < hazardBankCount.U, + UIntToOH(access.wr_bank_id, hazardBankCount), + 0.U(hazardBankCount.W) + ) + + def rawUseMask(access: BankAccessInfo): UInt = + rawReadMask(access) | rawWriteMask(access) + + // --------------------------------------------------------------------------- + // Allocate: enqueue decoded instruction into ROB + // rob_id == tailPtr at allocation time (no separate counter needed) + // --------------------------------------------------------------------------- + val commitMask = Wire(Vec(robDepth, Bool())) + for (i <- 0 until robDepth) { + commitMask(i) := false.B + } + bat.io.free.valid := commitMask.asUInt.orR + bat.io.free.mask := commitMask + + val commitScan = Wire(Vec(robDepth, Bool())) + val commitKeep = Wire(Vec(robDepth + 1, Bool())) + commitKeep(0) := true.B + for (i <- 0 until robDepth) { + val ptr = robIdx(wrapPtr(headPtr + i.U)) + commitScan(i) := commitKeep(i) && robValid(ptr) && robComplete(ptr) + commitKeep(i + 1) := (if (b.sim.diffTest) false.B else commitScan(i)) + } + val hasCommit = commitScan.asUInt.orR + val tailAlias = Wire(UInt(b.frontend.bank_id_len.W)) + tailAlias := + b.memDomain.virtualBankCount.U(b.frontend.bank_id_len.W) + tailPtr + + val tailAliasLive = WireDefault(false.B) + for (i <- 0 until robDepth) { + when(robValid(i) && !robComplete(i) && accessUsesBank(robEntries(i).renamedBankAccess, tailAlias)) { + tailAliasLive := true.B + } + } + + io.alloc.ready := !isFull && !hasCommit && !tailAliasLive + bat.io.alloc.valid := io.alloc.fire + bat.io.alloc.rob_id := tailPtr + bat.io.alloc.raw := io.alloc.bits.bankAccess + + // Mark write alias as busy in scoreboard at alloc time (not issue time). + scoreboard.alloc.valid := io.alloc.fire && io.alloc.bits.bankAccess.wr_bank_valid + scoreboard.alloc.bits := bat.io.alloc_renamed + + // Bank masks are shared by allocation and issue. This avoids rebuilding the + // UIntToOH decoders once for every older-entry comparison at allocation. + val entryRawReads = Wire(Vec(robDepth, UInt(hazardBankCount.W))) + val entryRawWrites = Wire(Vec(robDepth, UInt(hazardBankCount.W))) + val entryIsConfig = Wire(Vec(robDepth, Bool())) + for (slot <- 0 until robDepth) { + entryRawReads(slot) := rawReadMask(robEntries(slot).cmd.bankAccess) + entryRawWrites(slot) := rawWriteMask(robEntries(slot).cmd.bankAccess) + entryIsConfig(slot) := isMappingConfig(robEntries(slot)) + } + + // A newly allocated entry is always younger than all currently valid ROB + // entries (tailPtr points at the first free slot). Capture its older-entry + // dependencies once here; issue no longer repeats pairwise comparisons. + val allocReadMask = rawReadMask(io.alloc.bits.bankAccess) + val allocWriteMask = rawWriteMask(io.alloc.bits.bankAccess) + val allocIsConfig = io.alloc.bits.domain_id === DomainId.MEM && + (io.alloc.bits.cmd.funct === MSET_BITPAT) + val allocIsBall = io.alloc.bits.domain_id === DomainId.BALL + val allocDependencyBits = Wire(Vec(robDepth, Bool())) + for (older <- 0 until robDepth) { + val olderUseMask = entryRawReads(older) | entryRawWrites(older) + val rawConflict = ((allocReadMask & entryRawWrites(older)) | + (allocWriteMask & olderUseMask)).orR + val configConflict = (allocIsConfig && entryIsConfig(older)) || + ((allocIsConfig || entryIsConfig(older)) && ((allocReadMask | allocWriteMask) & olderUseMask).orR) + val sameBall = allocIsBall && + robEntries(older).cmd.domain_id === DomainId.BALL && + robEntries(older).cmd.ball_bid === io.alloc.bits.ball_bid + // Config conflicts include entries that have completed but are waiting to + // commit. RAW conflicts and same-Ball commands release at completion. + allocDependencyBits(older) := + (robValid(older) && !robComplete(older) && (rawConflict || sameBall)) || + (robValid(older) && configConflict) + } + val allocDependencies = allocDependencyBits.asUInt + val allocUsesInstId = io.alloc.bits.cmd.pc =/= 0.U + + when(io.alloc.fire) { + operandRam.foreach(_.write(tailPtr, Cat(io.alloc.bits.cmd.rs1Data, io.alloc.bits.cmd.rs2Data))) + itraceAlloc.io.is_issue := 2.U + itraceAlloc.io.rob_id := tailPtr + itraceAlloc.io.inst_id := Mux(allocUsesInstId, nextInstId, 0.U) + itraceAlloc.io.domain_id := io.alloc.bits.domain_id + itraceAlloc.io.funct := io.alloc.bits.cmd.funct + itraceAlloc.io.pc := io.alloc.bits.cmd.pc + itraceAlloc.io.rs1_data := io.alloc.bits.cmd.rs1Data + itraceAlloc.io.rs2_data := io.alloc.bits.cmd.rs2Data + itraceAlloc.io.enable := true.B + + robEntries(tailPtr).cmd := io.alloc.bits + robEntries(tailPtr).renamedBankAccess := bat.io.alloc_renamed + robEntries(tailPtr).rob_id := tailPtr + instIds(tailPtr) := Mux(allocUsesInstId, nextInstId, 0.U) + robValid(tailPtr) := true.B + robIssued(tailPtr) := false.B + robComplete(tailPtr) := false.B + statusHashes.foreach { hashes => + for (slot <- 0 until 3) { + hashes(tailPtr)(slot) := 0.U + } + } + tailPtr := nextPtr(tailPtr) + when(allocUsesInstId) { + nextInstId := nextInstId + 1.U + } + } + + // --------------------------------------------------------------------------- + // Complete: mark entry as completed, release scoreboard resources + // --------------------------------------------------------------------------- + if (b.sim.diffTest) { + val collecting = RegInit(false.B) + val collectCid = Reg(UInt(idWidth.W)) + val collectSlot = Reg(UInt(2.W)) + val collectGroup = Reg(UInt(32.W)) + val currentHash = Reg(UInt(32.W)) + val hashReady = RegInit(false.B) + val hashCid = Reg(UInt(idWidth.W)) + + val incomingAccess = robEntries(io.complete.bits).cmd.bankAccess + val incomingNeedsHash = instIds(io.complete.bits) =/= 0.U && !isMappingConfig(robEntries(io.complete.bits)) && + (incomingAccess.rd_bank_0_valid || incomingAccess.rd_bank_1_valid || incomingAccess.wr_bank_valid) + io.complete.ready := !incomingNeedsHash || (hashReady && hashCid === io.complete.bits) + + when(!collecting && !hashReady && io.complete.valid && incomingNeedsHash) { + collecting := true.B + collectCid := io.complete.bits + collectSlot := Mux(incomingAccess.rd_bank_0_valid, 0.U, Mux(incomingAccess.rd_bank_1_valid, 1.U, 2.U)) + collectGroup := 0.U + currentHash := 0.U + } + + val access = robEntries(collectCid).cmd.bankAccess + val vbank = MuxLookup(collectSlot, access.wr_bank_id)(Seq( + 0.U -> access.rd_bank_0_id, + 1.U -> access.rd_bank_1_id, + 2.U -> access.wr_bank_id + )) + val hasNextSlot = MuxLookup(collectSlot, false.B)(Seq( + 0.U -> (access.rd_bank_1_valid || access.wr_bank_valid), + 1.U -> access.wr_bank_valid + )) + val nextSlot = Mux(collectSlot === 0.U && access.rd_bank_1_valid, 1.U, 2.U) + val matches = VecInit(io.bank_hashes.get.map { state => + state.valid && state.hartId === io.hart_id && state.vbankId === vbank && state.groupId === collectGroup + }) + val nextMatches = VecInit(io.bank_hashes.get.map { state => + state.valid && state.hartId === io.hart_id && state.vbankId === vbank && state.groupId === collectGroup + 1.U + }) + val physical = Mux1H(matches, io.bank_hashes.get) + def rotateLeft(value: UInt, amount: Int): UInt = Cat(value(31 - amount, 0), value(31, 32 - amount)) + + val mixed = physical.statusHash ^ rotateLeft(physical.groupId, 7) ^ "h9e3779b9".U + val nextHash = rotateLeft(currentHash, 5) ^ mixed ^ rotateLeft(mixed, 13) + + when(collecting) { + assert(PopCount(matches) === 1.U, "BTrace requires exactly one physical bank per vbank group") + when(nextMatches.asUInt.orR) { + currentHash := nextHash + collectGroup := collectGroup + 1.U + }.otherwise { + statusHashes.get(collectCid)(collectSlot) := nextHash + when(hasNextSlot) { + collectSlot := nextSlot + collectGroup := 0.U + currentHash := 0.U + }.otherwise { + collecting := false.B + hashReady := true.B + hashCid := collectCid + } + } + } + + when(io.complete.fire) { + hashReady := false.B + } + } else { + io.complete.ready := true.B + } + + scoreboard.complete.valid := false.B + scoreboard.complete.bits := 0.U.asTypeOf(scoreboard.complete.bits) + + val issueFired = WireDefault(false.B) + val completeIssuedEntry = io.complete.fire && robIssued(io.complete.bits) + + when(io.complete.fire) { + val cid = io.complete.bits + robComplete(cid) := true.B + scoreboard.complete.valid := true.B + scoreboard.complete.bits := robEntries(cid).renamedBankAccess + + itraceComp.io.is_issue := 0.U + itraceComp.io.rob_id := cid + itraceComp.io.inst_id := instIds(cid) + itraceComp.io.domain_id := robEntries(cid).cmd.domain_id + itraceComp.io.funct := robEntries(cid).cmd.cmd.funct + itraceComp.io.pc := robEntries(cid).cmd.cmd.pc + itraceComp.io.rs1_data := robEntries(cid).cmd.cmd.rs1Data + itraceComp.io.rs2_data := robEntries(cid).cmd.cmd.rs2Data + itraceComp.io.enable := true.B + } + + val completedBitMask = Mux( + io.complete.fire, + UIntToOH(io.complete.bits, robDepth), + 0.U(robDepth.W) + ) + + // --------------------------------------------------------------------------- + // Issue: scan from head for first issuable entry (valid && !issued && !complete) + // --------------------------------------------------------------------------- + val scanValid = Wire(Vec(robDepth, Bool())) + val scanReady = Wire(Vec(robDepth, Bool())) + val vbankMasks = Wire(Vec(robDepth, UInt(vbankMaskWidth.W))) + for (slot <- 0 until robDepth) { + // Reuse the raw hazard mask for active-command ownership. + vbankMasks(slot) := entryRawReads(slot) | entryRawWrites(slot) + } + + // Check each candidate against older ROB entries using mask intersections. + // The masks are precomputed once per slot, so this retains the original + // age-sensitive RAW/WAR/WAW semantics without replicating three equality + // comparators for every bank access pair. + for (i <- 0 until robDepth) { + val ptr = robIdx(wrapPtr(headPtr + i.U)) + scanValid(i) := robValid(ptr) && !robIssued(ptr) && !robComplete(ptr) + scoreboard.queryVec(i) := robEntries(ptr).renamedBankAccess + scanReady(i) := scanValid(i) && !scoreboard.hazardVec(i) && + !dependencyMask(ptr).orR && + !(vbankMasks(ptr) & vbankBusy).orR + } + + val hasReady = scanReady.asUInt.orR + val firstReady = PriorityEncoder(scanReady.asUInt) + val actualIssuePtr = robIdx(wrapPtr(headPtr + firstReady)) + + scoreboard.query := robEntries(actualIssuePtr).renamedBankAccess + val canIssue = hasReady + + val issueStageValid = RegInit(false.B) + val issueStageEntry = Reg(new GlobalRobEntry(b)) + val issueStageFire = issueStageValid && !io.subRobActive && io.issue.ready + val issueStageReady = !issueStageValid || issueStageFire + + // Keep the wide ROB entry and bank-column mux one register boundary away + // from the age/scoreboard scan. The pointer stage can accept one candidate + // per cycle; the payload stage drains at one per cycle, so steady-state II + // remains one while the extra latency is hidden by in-flight commands. + val issuePtrValid = RegInit(false.B) + val issuePtr = Reg(UInt(idWidth.W)) + val issuePtrFire = issuePtrValid && issueStageReady + val issuePtrReady = !issuePtrValid || issuePtrFire + val issueLoad = canIssue && !io.subRobActive && issuePtrReady + val issuePayload = Wire(new GlobalRobEntry(b)) + issuePayload := robEntries(issuePtr) + operandRam.foreach { memory => + // Read at pointer selection, then re-read while that pointer is stalled. + // Replacement selects the new pointer; the current response is consumed + // before the next edge. This preserves the existing two-stage issue timing. + val readAddress = Mux(issueLoad, actualIssuePtr, issuePtr) + val readEnable = issueLoad || issuePtrValid + val operands = memory.read(readAddress, readEnable) + issuePayload.cmd.cmd.rs1Data := operands(2 * operandWidth - 1, operandWidth) + issuePayload.cmd.cmd.rs2Data := operands(operandWidth - 1, 0) + when(io.alloc.fire && readEnable) { + assert(tailPtr =/= readAddress, "ROB operand RAM read/write collision") + } + } + issuePayload.cmd.op1_col := Mux( + issuePayload.cmd.bankAccess.rd_bank_0_valid, + bankCols(issuePayload.cmd.bankAccess.rd_bank_0_id(b.memDomain.vbankIdWidth - 1, 0)), + 0.U + ) + issuePayload.cmd.op2_col := Mux( + issuePayload.cmd.bankAccess.rd_bank_1_valid, + bankCols(issuePayload.cmd.bankAccess.rd_bank_1_id(b.memDomain.vbankIdWidth - 1, 0)), + 0.U + ) + issuePayload.cmd.wr_col := Mux( + issuePayload.cmd.bankAccess.wr_bank_valid, + bankCols(issuePayload.cmd.bankAccess.wr_bank_id(b.memDomain.vbankIdWidth - 1, 0)), + 0.U + ) + + io.issue.valid := issueStageValid && !io.subRobActive + io.issue.bits := issueStageEntry + + when(issuePtrReady) { + issuePtrValid := issueLoad + when(issueLoad) { + issuePtr := actualIssuePtr + } + } + when(issueStageReady) { + issueStageValid := issuePtrValid + when(issuePtrFire) { + issueStageEntry := issuePayload + } + } + + scoreboard.issue.valid := false.B + scoreboard.issue.bits := 0.U.asTypeOf(scoreboard.issue.bits) + + when(issueLoad) { + robIssued(actualIssuePtr) := true.B + issueFired := true.B + scoreboard.issue.valid := true.B + scoreboard.issue.bits := robEntries(actualIssuePtr).renamedBankAccess + + itraceIssue.io.is_issue := 1.U + itraceIssue.io.rob_id := robEntries(actualIssuePtr).rob_id + itraceIssue.io.inst_id := instIds(actualIssuePtr) + itraceIssue.io.domain_id := robEntries(actualIssuePtr).cmd.domain_id + itraceIssue.io.funct := robEntries(actualIssuePtr).cmd.cmd.funct + itraceIssue.io.pc := robEntries(actualIssuePtr).cmd.cmd.pc + itraceIssue.io.rs1_data := robEntries(actualIssuePtr).cmd.cmd.rs1Data + itraceIssue.io.rs2_data := robEntries(actualIssuePtr).cmd.cmd.rs2Data + itraceIssue.io.enable := true.B + } + + // Preserve the original update ordering when issue and complete coincide: + // a completion clears ownership after the newly issued transaction marks + // its banks busy. + val issuedVbankMask = Mux(issueLoad, vbankMasks(actualIssuePtr), 0.U) + val completedVbankMask = Mux(io.complete.fire, vbankMasks(io.complete.bits), 0.U) + when(issueLoad || io.complete.fire) { + vbankBusy := + (vbankBusy & ~completedVbankMask) | issuedVbankMask + } + + issuedCount := issuedCount + issueFired.asUInt - completeIssuedEntry.asUInt + + // --------------------------------------------------------------------------- + // Commit: clear completed entries. + // Explicitly skip entries being allocated or completed this cycle. + // --------------------------------------------------------------------------- + for (i <- 0 until robDepth) { + val hits = (0 until robDepth).map { off => + val ptr = robIdx(wrapPtr(headPtr + off.U)) + commitScan(off) && ptr === i.U + } + commitMask(i) := hits.reduce(_ || _) + when(commitMask(i)) { + when(robEntries(i).cmd.domain_id === DomainId.MEM && robEntries(i).cmd.cmd.funct === MSET_BITPAT) { + val bankId = robEntries(i).cmd.bankAccess.wr_bank_id + val bank = bankId(b.memDomain.vbankIdWidth - 1, 0) + val col = robEntries(i).cmd.cmd.rs2Data(9, 5) + when(robEntries(i).cmd.cmd.rs2Data(10)) { + val fullCol = + if (b.memDomain.sharedEnable) { + Mux( + bankId >= b.frontend.shared_bank_id_base.U && bankId < b.memDomain.virtualBankCount.U, + SharedMemLayout.totalBank(b).U(bankColWidth.W), + b.memDomain.bankNum.U(bankColWidth.W) + ) + } else { + b.memDomain.bankNum.U(bankColWidth.W) + } + bankCols(bank) := Mux(col === 0.U, fullCol, col) + }.otherwise { + bankCols(bank) := 0.U + } + } + robValid(i) := false.B + robIssued(i) := false.B + robComplete(i) := false.B + } + } + + if (b.sim.diffTest) { + val commitIndex = PriorityEncoder(commitMask.asUInt) + val commitAccess = robEntries(commitIndex).cmd.bankAccess + val invalidVbank = "hffffffff".U(32.W) + val btrace = Module(new BTraceDPI) + btrace.io.clock := clock + btrace.io.reset := reset.asBool + btrace.io.instId := instIds(commitIndex) + btrace.io.hartId := io.hart_id + btrace.io.r0Vbank := Mux(commitAccess.rd_bank_0_valid, commitAccess.rd_bank_0_id, invalidVbank) + btrace.io.r0Hash := Mux(commitAccess.rd_bank_0_valid, statusHashes.get(commitIndex)(0), 0.U) + btrace.io.r1Vbank := Mux(commitAccess.rd_bank_1_valid, commitAccess.rd_bank_1_id, invalidVbank) + btrace.io.r1Hash := Mux(commitAccess.rd_bank_1_valid, statusHashes.get(commitIndex)(1), 0.U) + btrace.io.w0Vbank := Mux(commitAccess.wr_bank_valid, commitAccess.wr_bank_id, invalidVbank) + btrace.io.w0Hash := Mux(commitAccess.wr_bank_valid, statusHashes.get(commitIndex)(2), 0.U) + btrace.io.fire := hasCommit && instIds(commitIndex) =/= 0.U && !isMappingConfig(robEntries(commitIndex)) && + (commitAccess.rd_bank_0_valid || commitAccess.rd_bank_1_valid || commitAccess.wr_bank_valid) + } + + // Maintain dependency masks at the same architectural events that gate the + // issue scan. A dependency involving a config entry (on either side) clears + // only at commit; all other dependencies clear at complete. This is the + // union-mask form of the former separate RAW/config masks. + val configEntryMask = entryIsConfig.asUInt + for (slot <- 0 until robDepth) { + val isAllocatedSlot = io.alloc.fire && tailPtr === slot.U + val slotIsConfig = Mux(isAllocatedSlot, allocIsConfig, entryIsConfig(slot)) + // Each dependency bit names the older entry that blocks this slot. Keep a + // config-related edge through completion when either endpoint is config. + val configRelated = configEntryMask | Fill(robDepth, slotIsConfig) + val clearMask = commitMask.asUInt | (completedBitMask & ~configRelated) + when(isAllocatedSlot) { + dependencyMask(slot) := allocDependencies & ~clearMask + }.otherwise { + dependencyMask(slot) := dependencyMask(slot) & ~clearMask + } + } + + val commitCount = PopCount(commitScan) + headPtr := wrapPtr(headPtr + commitCount) + + // --------------------------------------------------------------------------- + // Status outputs + // --------------------------------------------------------------------------- + io.empty := isEmpty + io.full := isFull + io.head_ptr := headPtr + io.issued_count := issuedCount + io.entry_valid := robValid + io.entry_complete := robComplete + +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/bind_fpu_rf.py b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/bind_fpu_rf.py new file mode 100644 index 0000000..4646b37 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/bind_fpu_rf.py @@ -0,0 +1,33 @@ +"""Bind the already validated zero-latency FPU RF adapter after SRAM binding.""" + +import hashlib +import json +from pathlib import Path +import re + +ROOT = Path(__file__).resolve().parents[1] +output = ROOT / "build/serial-bound" +core = output / "ToyLinuxChip.sv" +original = core.read_text(encoding="utf-8") +matches = list(re.finditer(r"^module regfile_32x65\(.*?^endmodule", original, re.M | re.S)) +assert len(matches) == 1 +match = matches[0] +reference = (ROOT / "rtl/FpuRfOriginal.sv").read_text(encoding="utf-8").strip() +assert match.group() == reference.replace("module FpuRfOriginal(", "module regfile_32x65(") +replacement = (ROOT / "rtl/FpuRfLvt.sv").read_text(encoding="utf-8").strip() +replacement = replacement.replace("module FpuRfLvt(", "module regfile_32x65(") +adapted = original[:match.start()] + replacement + original[match.end():] +core.write_text(adapted, encoding="utf-8", newline="\n") +assert adapted.replace(replacement, match.group(), 1) == original +manifest = json.loads((output / "MEMORY_MANIFEST.json").read_text()) +manifest["baseline_core_rtl_sha256"] = manifest["core_rtl_sha256"] +manifest["core_rtl_sha256"] = hashlib.sha256(core.read_bytes()).hexdigest() +manifest["additional_memory_adapters"] = [{ + "module": "regfile_32x65", "implementation": "two single-write LUTRAM banks and LVT", + "read_ports": 3, "write_ports": 2, "read_latency": 0, + "same_address_write_priority": "W1", "added_cycles": 0, + "adapter_sha256": hashlib.sha256((ROOT / "rtl/FpuRfLvt.sv").read_bytes()).hexdigest(), +}] +(output / "MEMORY_MANIFEST.json").write_text(json.dumps(manifest, indent=2) + "\n") +print("PASS RF adapter matches original port contract; only RF module body replaced") +print("Final core SHA256:", manifest["core_rtl_sha256"]) diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/check_board_linux.py b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/check_board_linux.py new file mode 100644 index 0000000..9007ba9 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/check_board_linux.py @@ -0,0 +1,91 @@ +"""Boot OpenSBI/Linux/BusyBox on the actual core and board AXI/SCU RTL. + +The external DDR PHY/CDC is a stalled AXI memory model. Loader start is forced +only in this bench; commands enter through the real 1 Mbps UART receiver. +""" +import hashlib +import json +from pathlib import Path +import subprocess + +ROOT=Path(__file__).resolve().parents[1] +OUT=ROOT/"build/board-linux-final" + + +def main(): + OUT.mkdir(parents=True,exist_ok=True) + payload=ROOT/"build/board-software/fw_payload.bin" + # Chunked writes avoid creating a giant intermediate Python string. + with payload.open("rb") as src,(OUT/"payload.hex").open("w") as dst: + while data:=src.read(65536):dst.write("\n".join(f"{b:02x}" for b in data)+"\n") + bench=(ROOT/"build/board-cpu/tb_board_cpu.sv").read_text() + bench=bench.replace("tb_board_cpu","tb_board_linux") + bench=bench.replace("always #5 clk=~clk;", "always #20 clk=~clk;") + first=bench.index(" if(exited &&") + last=bench.index(" end\n axi_smoke_memory",first) + bench=bench[:first]+" if(cycles>500000000) $fatal(1,\"Linux cycle watchdog\");\n"+bench[last:] + bench=bench.replace(".CAPACITY(262144)",".CAPACITY(268435456)") + bench=bench.replace('"smoke.hex"','"payload.hex"') + console=''' + reg [255:0] tail=0; + reg init_seen=0,prompt_seen=0; + integer characters=0; + always @(posedge clk) if(!reset && platform.mmio_tx_valid && platform.tx_ready && cpu_run) begin + tail={tail[247:0],platform.mmio_tx_data};characters=characters+1; + $write("%c",platform.mmio_tx_data);$fflush(); + if(tail[95:0]=="init process") init_seen=1; + if(init_seen && tail[15:0]==16'h2320) prompt_seen=1; + if(tail[183:0]=="PASS LINUX_SYSTEM_CHECK") begin + $display("\\nPASS BOARD_LINUX_USERSPACE cycles=%0d characters=%0d",cycles,characters);$finish; + end + if(tail[95:0]=="Kernel panic") $fatal(1,"Kernel panic"); + end + task automatic send_byte(input [7:0] value); + @(negedge clk);uart_rx_in=0;repeat(25) @(negedge clk); + for(integer n=0;n<8;n=n+1) begin uart_rx_in=value[n];repeat(25) @(negedge clk);end + uart_rx_in=1;repeat(25) @(negedge clk); + // Allow the polled SBI/HVC console to drain its RAM-backed RX FIFO. + repeat(250000) @(negedge clk); + endtask + initial begin + wait(prompt_seen); + $display("\\nSIM_SHELL_PROMPT cycles=%0d",cycles);$fflush(); + send_byte("/");send_byte("r");send_byte("o");send_byte("o");send_byte("t");send_byte("/"); + send_byte("l");send_byte("i");send_byte("n");send_byte("u");send_byte("x");send_byte("_"); + send_byte("s");send_byte("y");send_byte("s");send_byte("t");send_byte("e");send_byte("m");send_byte("_"); + send_byte("c");send_byte("h");send_byte("e");send_byte("c");send_byte("k");send_byte("-"); + send_byte("l");send_byte("i");send_byte("n");send_byte("u");send_byte("x");send_byte(10); + $display("\\nSIM_COMMAND_SENT cycles=%0d overflow=%0d framing=%0d pending_rx=%0d",cycles, + platform.peripherals.overflow,platform.peripherals.framing,platform.peripherals.count);$fflush(); + if(platform.peripherals.overflow || platform.peripherals.framing) $fatal(1,"UART input loss"); + end +''' + bench=bench.replace("endmodule",console+"\nendmodule") + path=OUT/"tb_board_linux.sv" + path.write_text(bench) + files=[ROOT/"build/serial-bound/ToyLinuxChip.sv",ROOT/"build/serial-bound/FpgaMemories.sv", + ROOT/"tests/axi_smoke_memory.sv",path]+[p for p in (ROOT/"board").glob("*.sv") if p.name!="toy_a7_top.sv"] + with (OUT/"compile.log").open("w") as log: + subprocess.run(["verilator","--binary","--timing","-j","8","-Wno-fatal","-DSYNTHESIS", + "-DBUCKYBALL_DISABLE_DPI","--top-module","tb_board_linux","--Mdir",str(OUT/"obj")]+[str(p) for p in files], + stdout=log,stderr=log,check=True,timeout=900) + with (OUT/"simulation.log").open("w") as log: + result=subprocess.run([str(OUT/"obj/Vtb_board_linux")],cwd=OUT,stdout=log,stderr=log,timeout=3000) + transcript=(OUT/"simulation.log").read_text() + result.check_returncode() + required=["OpenSBI","Linux version","PASS VM_COPY_ON_WRITE","PASS VM_PAGE_PROTECTION", + "PASS FP64_PROCESS_CONTEXT","PASS LINUX_TIMER","PASS LINUX_SYSTEM_CHECK","PASS BOARD_LINUX_USERSPACE"] + for marker in required:assert marker in transcript,marker + record=dict(result="PASS_RTL_LINUX_USERSPACE",payload_sha256=hashlib.sha256(payload.read_bytes()).hexdigest(), + checks=required,physical_mig_simulated=False,physical_board_tested=False,uart_rx_command_tested=True) + (OUT/"RESULT.json").write_text(json.dumps(record,indent=2)+"\n") + print(transcript[-2000:]) + + +if __name__=="__main__": + try: + main() + except Exception as error: + OUT.mkdir(parents=True,exist_ok=True) + (OUT/"RESULT.json").write_text(json.dumps(dict(result="FAIL",error=str(error),physical_board_tested=False),indent=2)+"\n") + raise diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/check_globalrob.py b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/check_globalrob.py new file mode 100644 index 0000000..d563932 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/check_globalrob.py @@ -0,0 +1,64 @@ +"""核验同步 RAM 与原寄存器路径逐周期等价，包括背压、绕回和中途复位。""" + +import argparse +import hashlib +import json +from pathlib import Path +import re +import subprocess + +ROOT = Path(__file__).resolve().parents[1] + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--skip-elaboration", action="store_true") + args = parser.parse_args() + out = ROOT / "build/globalrob-check" + out.mkdir(parents=True, exist_ok=True) + commands = [] + if not args.skip_elaboration: + commands.append((["sbt", "-batch", "runMain fpga.arty.linux.EmitGlobalRobCheck"], + "elaboration.log", 900)) + for command, name, timeout in commands: + with (out / name).open("w") as log: + subprocess.run(command, cwd=ROOT, stdout=log, stderr=subprocess.STDOUT, + timeout=timeout, check=True) + # CIRCT appends named inline resources and the .f index to one emission. + # Keep the untouched emission, compile only Verilog sections. + parts = re.split(r'// ----- 8< ----- FILE "([^"]+)" ----- 8< -----', + (out / "GlobalRobCheck.sv").read_text()) + modules = [parts[0]] + for name, body in zip(parts[1::2], parts[2::2]): + if name.endswith((".sv", ".v")): + modules.append(body) + elif name == "firrtl_black_box_resource_files.f": + if not all(line.strip().endswith(".v") for line in body.splitlines() if line.strip()): + raise ValueError("Unexpected inline resource index") + else: + raise ValueError("Unexpected emitted resource: " + name) + rtl = out / "GlobalRobCheck.sim.sv" + rtl.write_text("\n".join(modules)) + commands = [(["verilator", "--binary", "--timing", "--assert", "-j", "4", "-Wno-fatal", + "-DBUCKYBALL_DISABLE_DPI", "--top-module", "tb", "--Mdir", str(out / "obj"), + str(rtl), str(ROOT / "tests/tb_globalrob.sv")], + "compile.log", 600), + ([str(out / "obj/Vtb")], "simulation.log", 60)] + for command, name, timeout in commands: + with (out / name).open("w") as log: + subprocess.run(command, cwd=ROOT, stdout=log, stderr=subprocess.STDOUT, + timeout=timeout, check=True) + transcript = (out / "simulation.log").read_text() + if "PASS GLOBALROB RAM/register cycle comparison" not in transcript: + raise ValueError("GlobalROB passing marker missing") + record = {"result": "PASS", "cycle_equivalence": True, + "coverage": ["accepted operand integrity", "ROB full", "pointer wrap", + "issue backpressure", "SubROB ownership stall", "mid-flight resets", + "concurrent allocation/issue/completion", "complete drain"], + "rtl_sha256": hashlib.sha256((out / "GlobalRobCheck.sv").read_bytes()).hexdigest()} + (out / "RESULT.json").write_text(json.dumps(record, indent=2) + "\n") + print(transcript) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/prepare_fpga_memories.py b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/prepare_fpga_memories.py new file mode 100644 index 0000000..049f434 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/prepare_fpga_memories.py @@ -0,0 +1,197 @@ +"""Bind CIRCT 1RW and 1R1W SRAM macros to synchronous FPGA RAM templates. + +The emitted CPU/operator RTL is not rewritten. Only compiler-declared external +memory modules receive implementations. Undefined read results during a write +or disabled cycle hold their previous value. No memory contents are reset. +""" + +import argparse +import hashlib +import json +import re +from pathlib import Path + + +def unpack_emission(raw): + parts = re.split(r'// ----- 8< ----- FILE "([^"]+)" ----- 8< -----', raw) + rtl = [parts[0]] + metadata = None + config = None + for name, body in zip(parts[1::2], parts[2::2]): + if name.endswith((".sv", ".v")): + rtl.append(body) + elif name == "metadata/seq_mems.json": + assert metadata is None + metadata = json.loads(body) + elif name.endswith("/memories.conf"): + assert config is None + config = body.strip() + "\n" + elif name == "firrtl_black_box_resource_files.f": + assert all(x.strip().endswith(".v") for x in body.splitlines() if x.strip()) + else: + raise ValueError(f"Unrecognized emitted section: {name}") + assert metadata and config, "Elaborate with --fpga-memories first" + return "\n".join(rtl), metadata, config + + +def validate(metadata, config): + entries = {} + for line in config.splitlines(): + words = line.split() + assert len(words) % 2 == 0 + row = dict(zip(words[::2], words[1::2])) + assert set(row) <= {"name", "depth", "width", "ports", "mask_gran"} + assert row["ports"] in ("rw", "mrw", "write,read", "mwrite,read"), row + assert row["name"] not in entries + entries[row["name"]] = row + assert len(entries) == len(metadata) + for mem in metadata: + name = mem["module_name"] + assert re.fullmatch(r"[A-Za-z_][A-Za-z0-9_]*", name) + topology = (mem["read"], mem["write"], mem["readwrite"]) + assert topology in ((0, 0, 1), (1, 1, 0)) + assert not mem["extra_ports"] + row = entries[name] + assert int(row["depth"]) == mem["depth"] > 1 + assert int(row["width"]) == mem["width"] > 0 + assert (row["ports"] in ("mrw", "mwrite,read")) == mem["masked"] + assert ("," in row["ports"]) == (topology == (1, 1, 0)) + if mem["masked"]: + gran = mem["mask_granularity"] + assert int(row["mask_gran"]) == gran and mem["width"] % gran == 0 + + +def emit_dual_memory(mem, style): + name, depth, width = (mem[k] for k in ("module_name", "depth", "width")) + gran = mem.get("mask_granularity", width) + lanes = width // gran + addr = (depth - 1).bit_length() + mask = f",\n input [{lanes-1}:0] W0_mask" if mem["masked"] else "" + lines = [ + f"""module {name}( + input [{addr-1}:0] R0_addr, + input R0_en, R0_clk, + output reg [{width-1}:0] R0_data, + input [{addr-1}:0] W0_addr, + input W0_en, W0_clk, + input [{width-1}:0] W0_data{mask} +);""" + ] + # Split non-native masks into independent RAM lanes; keep both clocks. + write_enable = "W0_en && W0_mask[lane]" if mem["masked"] else "W0_en" + lines += [ + f" for (genvar lane = 0; lane < {lanes}; lane = lane + 1) begin : lanes", + f' (* ram_style = "{style}" *) reg [{gran-1}:0] ram [0:{depth-1}];', + " always @(posedge W0_clk)", + f" if ({write_enable}) ram[W0_addr] <= W0_data[lane*{gran} +: {gran}];", + " always @(posedge R0_clk)", + f" if (R0_en) R0_data[lane*{gran} +: {gran}] <= ram[R0_addr];", + " end", + "endmodule", + "", + ] + return "\n".join(lines), style + + +def emit_memory(mem, force_block=False): + name, depth, width = (mem[k] for k in ("module_name", "depth", "width")) + gran = mem.get("mask_granularity", width) + lanes = width // gran + addr = (depth - 1).bit_length() + # A 64-row bank fits one LUT RAM per bit. Avoid wasting deep BRAM blocks + # on shallow tags, MMIO banks and SubROB; keep 1024-row data banks in BRAM. + style = "block" if force_block else "distributed" if depth <= 64 else "block" + if mem["read"] == 1: + return emit_dual_memory(mem, style) + ports = [ + f" input [{addr-1}:0] RW0_addr", + " input RW0_en, RW0_clk, RW0_wmode", + f" input [{width-1}:0] RW0_wdata", + f" output reg [{width-1}:0] RW0_rdata", + ] + if mem["masked"]: + ports.append(f" input [{lanes-1}:0] RW0_wmask") + lines = [f"module {name}(" + ",\n".join(ports) + "\n);"] + # Native byte masks share a wide array. Other mask widths get independent + # arrays so e.g. 17-bit L2 tags never require unsupported byte enables. + if not mem["masked"] or gran in (8, 9): + lines += [ + f' (* ram_style = "{style}" *) reg [{width-1}:0] ram [0:{depth-1}];', + " always @(posedge RW0_clk) begin", + " if (RW0_en) begin", + " if (RW0_wmode) begin", + ] + if mem["masked"]: + lines += [ + f" for (integer lane = 0; lane < {lanes}; lane = lane + 1)", + " if (RW0_wmask[lane])", + f" ram[RW0_addr][lane*{gran} +: {gran}] <= " + f"RW0_wdata[lane*{gran} +: {gran}];", + ] + else: + lines.append(" ram[RW0_addr] <= RW0_wdata;") + lines += [ + " end else RW0_rdata <= ram[RW0_addr];", + " end", + " end", + ] + else: + lines += [ + f" for (genvar lane = 0; lane < {lanes}; lane = lane + 1) begin : lanes", + f' (* ram_style = "{style}" *) reg [{gran-1}:0] ram [0:{depth-1}];', + " always @(posedge RW0_clk) begin", + " if (RW0_en) begin", + " if (RW0_wmode) begin", + " if (RW0_wmask[lane]) ram[RW0_addr] <= " + f"RW0_wdata[lane*{gran} +: {gran}];", + f" end else RW0_rdata[lane*{gran} +: {gran}] <= ram[RW0_addr];", + " end", + " end", + " end", + ] + return "\n".join(lines + ["endmodule", ""]), style + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("emission", type=Path) + parser.add_argument("--output-dir", type=Path, required=True) + parser.add_argument("--block-memory", action="append", default=[], + help="明确将指定宏映射到 BRAM，包括 ROB 的浅层宽操作数 RAM") + args = parser.parse_args() + raw = args.emission.read_bytes() + rtl, metadata, config = unpack_emission(raw.decode()) + validate(metadata, config) + requested = set(args.block_memory) + available = {mem["module_name"] for mem in metadata} + if not requested <= available: + raise ValueError("Unknown block memory: " + ", ".join(sorted(requested - available))) + modules, mappings = [], [] + for mem in metadata: + module, style = emit_memory(mem, mem["module_name"] in requested) + modules.append(module) + mappings.append({**mem, "ram_style": style}) + macros = "\n".join(modules) + args.output_dir.mkdir(parents=True, exist_ok=True) + (args.output_dir / "ToyLinuxChip.sv").write_bytes(rtl.encode()) + (args.output_dir / "FpgaMemories.sv").write_bytes(macros.encode()) + (args.output_dir / "memories.conf").write_bytes(config.encode()) + record = { + "emitted_sha256": hashlib.sha256(raw).hexdigest(), + "core_rtl_sha256": hashlib.sha256(rtl.encode()).hexdigest(), + "memory_rtl_sha256": hashlib.sha256(macros.encode()).hexdigest(), + "read_latency": 1, + "write_latency": 1, + "undefined_output_policy": "hold on disabled/write cycle", + "dual_port_collision_policy": "read/write same address is undefined", + "memories": mappings, + } + (args.output_dir / "MEMORY_MANIFEST.json").write_text( + json.dumps(record, indent=2) + "\n" + ) + instances = sum(len(m["hierarchy"]) for m in metadata) + print(f"Bound {len(metadata)} memory types, {instances} instances") + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/prepare_rob_candidate.py b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/prepare_rob_candidate.py new file mode 100644 index 0000000..615b19d --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/prepare_rob_candidate.py @@ -0,0 +1,60 @@ +"""为 ROB 操作数候选显式绑定 BRAM，核对 profile 与已有存储器几何参数。""" + +import argparse +import hashlib +import json +from pathlib import Path +import subprocess +import sys + +from prepare_fpga_memories import unpack_emission, validate + +ROOT = Path(__file__).resolve().parents[1] + + +def digest(path): + return hashlib.sha256(path.read_bytes()).hexdigest() + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--baseline-memory-manifest", type=Path, required=True) + args = parser.parse_args() + raw = ROOT / "build/serial-raw/ToyLinuxChip.sv" + profile = json.loads((ROOT / "build/serial-raw/ToyLinuxChip.profile.json").read_text()) + expected = json.loads((ROOT / "evidence/2026-10-11/ToyLinuxChip.profile.json").read_text()) + if profile != expected: + raise ValueError("Optimization changed the architectural hardware profile") + _, memories, config = unpack_emission(raw.read_text()) + validate(memories, config) + operands = [m for m in memories if any("robOperands" in h for h in m["hierarchy"])] + if len(operands) != 1: + raise ValueError("Expected one ROB operand memory type") + operand = operands[0] + if (operand["depth"], operand["width"], operand["read"], operand["write"], + operand["readwrite"], operand["masked"], len(operand["hierarchy"])) != (16, 128, 1, 1, 0, False, 1): + raise ValueError("Unexpected ROB memory geometry or topology") + baseline = json.loads(args.baseline_memory_manifest.read_text()) + if baseline["core_rtl_sha256"] != "4c6aacf64660bbbf14b1114e8d5e4439d6a4e1427aaf1f681c6a4f618f2d2779": + raise ValueError("Wrong baseline memory manifest") + def signature(memory): + return tuple(memory.get(k) for k in + ("depth", "width", "read", "write", "readwrite", "masked", "mask_granularity")) + before = sorted((signature(m), len(m["hierarchy"])) for m in baseline["memories"]) + after = sorted((signature(m), len(m["hierarchy"])) for m in memories if m != operand) + if before != after: + raise ValueError("An existing memory geometry/topology changed") + subprocess.run([sys.executable, str(ROOT / "scripts/prepare_fpga_memories.py"), str(raw), + "--output-dir", str(ROOT / "build/serial-bound"), + "--block-memory", operand["module_name"]], check=True, timeout=60) + subprocess.run([sys.executable, str(ROOT / "scripts/bind_fpu_rf.py")], check=True, timeout=60) + record = {"result": "PREPARED_NOT_VALIDATED", "architectural_profile_unchanged": True, + "existing_memory_geometry_unchanged": True, "rob_operand_memory": operand, + "rob_operand_ram_style": "block", "core_rtl_sha256": digest(ROOT / "build/serial-bound/ToyLinuxChip.sv"), + "memory_rtl_sha256": digest(ROOT / "build/serial-bound/FpgaMemories.sv")} + (ROOT / "build/ROB_RAM_PREPARED.json").write_text(json.dumps(record, indent=2) + "\n") + print(json.dumps(record, indent=2)) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/run_board_regression.py b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/run_board_regression.py new file mode 100644 index 0000000..6d17780 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/run_board_regression.py @@ -0,0 +1,14 @@ +"""Repeat the unchanged CPU/Gemmini/loop/DMA oracles through board RTL.""" +import json +from pathlib import Path +import subprocess +import sys + +ROOT=Path(__file__).resolve().parents[1] +subprocess.run([sys.executable,str(ROOT/"scripts/check_board.py")],check=True,timeout=180) +records={} +for name in ("cpu","gemmini","loop","dma"): + subprocess.run([sys.executable,str(ROOT/"scripts/check_board_cpu.py"),"--test",name],check=True,timeout=1000) + records[name]=json.loads((ROOT/("build/board-"+name)/"RESULT.json").read_text()) +(ROOT/"build/BOARD_REGRESSION.json").write_text(json.dumps(dict(result="PASS",tests=records),indent=2)+"\n") +print("PASS BOARD_REGRESSION CPU/Gemmini/loop/DMA") diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/start_board_build.py b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/start_board_build.py new file mode 100644 index 0000000..a8c7b7a --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/start_board_build.py @@ -0,0 +1,92 @@ +"""Run the complete board flow in isolation with a one-hour hard timeout.""" +from datetime import datetime, timedelta, timezone +import argparse +import hashlib +import json +import os +from pathlib import Path +import subprocess +import sys +import time + +ROOT=Path(__file__).resolve().parents[1] +TZ=timezone(timedelta(hours=8)) +EXPECTED="4c6aacf64660bbbf14b1114e8d5e4439d6a4e1427aaf1f681c6a4f618f2d2779" + + +def sha(path): + return hashlib.sha256(path.read_bytes()).hexdigest() + + +def save(path, record): + temp=path.with_suffix(".tmp") + temp.write_text(json.dumps(record,indent=2)+"\n",encoding="utf-8") + temp.replace(path) + + +def worker(out): + manifest=out/"RUN.json" + record=json.loads(manifest.read_text()) + now=datetime.now(TZ) + script=Path(record.get("execution_script",str(ROOT/"board/build_board.tcl"))) + if "execution_script_sha256" in record: + assert sha(script)==record["execution_script_sha256"] + command=["timeout","--signal=TERM","--kill-after=15s","3600s",os.environ.get("VIVADO", "vivado"), + "-mode","batch","-source",str(script), + "-log",str(out/"vivado.log"),"-journal",str(out/"vivado.jou"),"-tclargs",str(out)] + if record.get("flash_boot"): + command.append("flash") + record.update(status="RUNNING",started_at=now.isoformat(),deadline=(now+timedelta(hours=1)).isoformat(), + command=command,worker_pid=os.getpid()) + started=time.monotonic() + try: + with (out/"console.log").open("w") as log: + p=subprocess.Popen(command,cwd=ROOT,stdin=subprocess.DEVNULL,stdout=log, + stderr=subprocess.STDOUT,start_new_session=True) + record["timeout_process_pid"]=p.pid + save(manifest,record) + code=p.wait() + record.update(exit_code=code,status="TIMED_OUT" if code in (124,137) else "COMPLETED" if code==0 else "FAILED") + except Exception as e: + record.update(status="LAUNCH_FAILED",error=str(e)) + record.update(elapsed_seconds=time.monotonic()-started,finished_at=datetime.now(TZ).isoformat(), + core_unchanged=sha(ROOT/"build/serial-bound/ToyLinuxChip.sv")==EXPECTED, + bitstream_generated=(out/"toy_a7.bit").is_file()) + save(manifest,record) + + +def main(): + p=argparse.ArgumentParser(description=__doc__) + p.add_argument("--worker",type=Path) + p.add_argument("--flash",action="store_true",help="Use the validated Flash boot ROM and SPI port") + args=p.parse_args() + if args.worker: + worker(args.worker.resolve());return + assert sha(ROOT/"build/serial-bound/ToyLinuxChip.sv")==EXPECTED + if args.flash: + flash_manifest=json.loads((ROOT/"build/flash-boot/MANIFEST.json").read_text()) + assert flash_manifest["original_core_sha256"]==EXPECTED + assert sha(ROOT/"build/flash-boot/ToyLinuxChip.sv")==flash_manifest["adapted_core_sha256"] + for path in (ROOT/"build").glob("board-*/RUN.json"): + assert json.loads(path.read_text())["status"] not in ("CREATED","RUNNING"),f"Active build: {path}" + out=ROOT/"build"/("board-"+datetime.now(TZ).strftime("%Y%m%d-%H%M%S")) + out.mkdir() + # Snapshot the exact board sources used by this attempt, including failures. + import shutil + shutil.copytree(ROOT/"board",out/"inputs/board") + files={str(p.relative_to(ROOT)):sha(p) for p in (ROOT/"board").rglob("*") if p.is_file()} + record=dict(status="CREATED",timeout_seconds=3600,termination_grace_seconds=15, + output_directory=str(out),part="xc7a100tcsg324-1",core_sha256=EXPECTED, + board_sources=files,core_clock_hz=25000000,uart_baud=1000000, + vendor_revision="E.0",physical_board_revision="unknown",physical_boot_tested=False, + flash_boot=args.flash) + save(out/"RUN.json",record) + with (out/"launcher.log").open("w") as log: + p=subprocess.Popen([sys.executable,str(Path(__file__).resolve()),"--worker",str(out)], + cwd=ROOT,stdout=log,stderr=subprocess.STDOUT,stdin=subprocess.DEVNULL, + start_new_session=True,close_fds=True) + print(json.dumps({"output_directory":str(out),"worker_pid":p.pid,"timeout_seconds":3600})) + + +if __name__=="__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/start_rob_board_build.py b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/start_rob_board_build.py new file mode 100644 index 0000000..de57b6d --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/start_rob_board_build.py @@ -0,0 +1,63 @@ +"""以独立候选记录执行同一整板流程；不继承旧位流的资格结论。""" + +import argparse +from datetime import datetime +import json +import os +from pathlib import Path +import shutil +import subprocess +import sys + +from start_board_build import ROOT, TZ, save, sha, worker + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--worker", type=Path) + args = parser.parse_args() + if args.worker: + out = args.worker.resolve() + worker(out) + record = json.loads((out / "RUN.json").read_text()) + record["candidate_core_unchanged"] = sha(ROOT / "build/serial-bound/ToyLinuxChip.sv") == record["core_sha256"] + record["candidate_memory_unchanged"] = sha(ROOT / "build/serial-bound/FpgaMemories.sv") == record["memory_sha256"] + if not record["candidate_core_unchanged"] or not record["candidate_memory_unchanged"]: + record["status"] = "INPUT_CHANGED_REJECTED" + save(out / "RUN.json", record) + return + prepared = json.loads((ROOT / "build/ROB_RAM_PREPARED.json").read_text()) + for path in ["build/globalrob-check/RESULT.json", "build/BOARD_REGRESSION.json"]: + if json.loads((ROOT / path).read_text())["result"] != "PASS": + raise ValueError("Candidate regression has not passed: " + path) + core = ROOT / "build/serial-bound/ToyLinuxChip.sv" + memories = ROOT / "build/serial-bound/FpgaMemories.sv" + if sha(core) != prepared["core_rtl_sha256"] or sha(memories) != prepared["memory_rtl_sha256"]: + raise ValueError("Candidate inputs changed after preparation") + for path in (ROOT / "build").glob("board-*/RUN.json"): + if json.loads(path.read_text())["status"] in ("CREATED", "RUNNING"): + raise ValueError("An isolated board build is already active") + out = ROOT / "build" / ("board-rob-ram-" + datetime.now(TZ).strftime("%Y%m%d-%H%M%S")) + out.mkdir() + shutil.copytree(ROOT / "board", out / "inputs/board") + files = {str(p.relative_to(ROOT)): sha(p) for p in (ROOT / "board").rglob("*") if p.is_file()} + script = out / "inputs/board/build_board.tcl" + # Keep the input snapshot for audit, execute the identical script at its + # normal root so relative HDL/IP paths resolve without rewriting Tcl. + record = {"status": "CREATED", "optimization": "ROB_OPERAND_BRAM", "timeout_seconds": 3600, + "termination_grace_seconds": 15, "part": "xc7a100tcsg324-1", + "core_sha256": sha(core), "memory_sha256": sha(memories), "board_sources": files, + "execution_script": str(ROOT / "board/build_board.tcl"), "execution_script_sha256": sha(script), + "core_clock_hz": 25000000, "uart_baud": 1000000, + "architectural_profile_unchanged": True, "flash_boot": False, + "physical_boot_tested": False, "inherits_baseline_hardware_qualification": False} + save(out / "RUN.json", record) + with (out / "launcher.log").open("w") as log: + process = subprocess.Popen([sys.executable, str(Path(__file__).resolve()), "--worker", str(out)], + cwd=ROOT, stdout=log, stderr=subprocess.STDOUT, stdin=subprocess.DEVNULL, + start_new_session=True, close_fds=True) + print(json.dumps({"output_directory": str(out), "worker_pid": process.pid, "timeout_seconds": 3600})) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/src/main/scala/EmitGlobalRobCheck.scala b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/src/main/scala/EmitGlobalRobCheck.scala new file mode 100644 index 0000000..859e462 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/src/main/scala/EmitGlobalRobCheck.scala @@ -0,0 +1,110 @@ +package fpga.arty.linux + +import chisel3._ +import chisel3.util._ +import _root_.circt.stage.ChiselStage +import framework.frontend.globalrs.GlobalROB +import framework.frontend.decoder.{DomainId, PostGDCmd} +import framework.memdomain.frontend.cmd.decoder.DISA.MSET_BITPAT + +/** Cycle comparison of register and synchronous-RAM operand storage. */ +class GlobalRobCheck extends Module { + val seed = IO(Input(UInt(32.W))) + val passed = IO(Output(Bool())) + private val b = OriginalToy.serial + val dut = Module(new GlobalROB(b, useOperandRam = true)) + val reference = Module(new GlobalROB(b, useOperandRam = false)) + val cycle = RegInit(0.U(16.W)) + val random = RegInit(seed) + cycle := cycle + 1.U + random := Cat(random(30, 0), random(31) ^ random(21) ^ random(1) ^ random(0)) + assert(cycle < 9000.U, "GlobalROB drain timeout") + + val source = Module(new Queue(new PostGDCmd(b), 2)) + val generated = Wire(new PostGDCmd(b)) + generated := 0.U.asTypeOf(generated) + val config = random(5, 2) === 0.U + generated.domain_id := Mux(config || random(2), DomainId.MEM, DomainId.BALL) + generated.ball_bid := 0.U + generated.cmd.funct := Mux(config, MSET_BITPAT.value.U(7.W), Mux(random(3), 53.U, 66.U)) + generated.cmd.raw_inst := random + generated.cmd.pc := Cat(random, ~random) + generated.cmd.rs1Data := Cat(random, random ^ "h597bdf03".U) + generated.cmd.rs2Data := Mux(config, + Cat(random, 0.U(21.W), 1.U(1.W), 0.U(3.W), random(1, 0), 0.U(5.W)), + Cat(~random, random ^ "h26ac048e".U)) + generated.bankAccess.rd_bank_0_valid := !config && random(8) + generated.bankAccess.rd_bank_1_valid := !config && random(9) + generated.bankAccess.wr_bank_valid := config || random(10) + generated.bankAccess.rd_bank_0_id := random(14, 11) + generated.bankAccess.rd_bank_1_id := random(18, 15) + generated.bankAccess.wr_bank_id := random(22, 19) + source.io.enq.valid := cycle < 5000.U && random(0) + source.io.enq.bits := generated + dut.io.alloc <> source.io.deq + reference.io.alloc.valid := dut.io.alloc.valid + reference.io.alloc.bits := dut.io.alloc.bits + + val completions = Module(new Queue(UInt(log2Ceil(b.frontend.rob_entries).W), 16)) + val active = cycle(9, 6) === 13.U + val ready = completions.io.enq.ready && random(7) && cycle(8, 5) =/= 7.U + dut.io.issue.ready := ready + reference.io.issue.ready := ready + completions.io.enq.valid := dut.io.issue.fire + completions.io.enq.bits := dut.io.issue.bits.rob_id + dut.io.complete.valid := completions.io.deq.valid && random(4) + dut.io.complete.bits := completions.io.deq.bits + reference.io.complete.valid := dut.io.complete.valid + reference.io.complete.bits := dut.io.complete.bits + completions.io.deq.ready := dut.io.complete.ready && random(4) + dut.io.hart_id := 0.U + reference.io.hart_id := 0.U + dut.io.subRobActive := active + reference.io.subRobActive := active + + assert(dut.io.alloc.ready === reference.io.alloc.ready, "ROB allocation timing mismatch") + assert(dut.io.complete.ready === reference.io.complete.ready, "ROB completion timing mismatch") + assert(dut.io.issue.valid === reference.io.issue.valid, "ROB issue timing mismatch") + when(dut.io.issue.valid) { + assert(dut.io.issue.bits.asUInt === reference.io.issue.bits.asUInt, "ROB issue payload mismatch") + } + assert(dut.io.empty === reference.io.empty && dut.io.full === reference.io.full) + assert(dut.io.head_ptr === reference.io.head_ptr) + assert(dut.io.issued_count === reference.io.issued_count) + assert(dut.io.entry_valid.asUInt === reference.io.entry_valid.asUInt) + assert(dut.io.entry_complete.asUInt === reference.io.entry_complete.asUInt) + assert(dut.io.inst_ids.asUInt === reference.io.inst_ids.asUInt) + + val allocated = RegInit(0.U(16.W)) + val issued = RegInit(0.U(16.W)) + val completed = RegInit(0.U(16.W)) + val sawFull = RegInit(false.B) + val sawStall = RegInit(false.B) + val expected = Reg(Vec(b.frontend.rob_entries, chiselTypeOf(generated.cmd))) + val allocationSlot = RegInit(0.U(log2Ceil(b.frontend.rob_entries).W)) + when(dut.io.alloc.fire) { + allocated := allocated + 1.U + expected(allocationSlot) := dut.io.alloc.bits.cmd + allocationSlot := Mux(allocationSlot === (b.frontend.rob_entries - 1).U, + 0.U, allocationSlot + 1.U) + } + when(dut.io.issue.fire) { + issued := issued + 1.U + assert(dut.io.issue.bits.cmd.cmd.asUInt === expected(dut.io.issue.bits.rob_id).asUInt, + "ROB changed accepted command operands") + } + when(dut.io.complete.fire) { completed := completed + 1.U } + when(dut.io.full) { sawFull := true.B } + when(dut.io.issue.valid && !ready) { sawStall := true.B } + passed := cycle > 5005.U && !source.io.deq.valid && dut.io.empty && !completions.io.deq.valid + when(passed) { + assert(allocated === issued && issued === completed && allocated > 64.U) + assert(sawFull && sawStall, "Missing ROB full/stall coverage") + } +} + +object EmitGlobalRobCheck extends App { + ChiselStage.emitSystemVerilogFile(new GlobalRobCheck, + Array("--target-dir", args.headOption.getOrElse("build/globalrob-check")), + Array("-disable-all-randomization", "-strip-debug-info")) +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/tests/tb_globalrob.sv b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/tests/tb_globalrob.sv new file mode 100644 index 0000000..8213b7d --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/tests/tb_globalrob.sv @@ -0,0 +1,29 @@ +`timescale 1ns/1ps +module tb; + reg clock = 0, reset = 1; + reg [31:0] seed = 32'h12345678; + wire passed; + integer cycles = 0; + GlobalRobCheck dut(.*); + always #5 clock = ~clock; + initial begin + repeat (5) @(negedge clock); + reset = 0; + repeat (1200) @(negedge clock); + reset = 1; seed = 32'hda7a0319; + repeat (5) @(negedge clock); + reset = 0; + repeat (1800) @(negedge clock); + reset = 1; seed = 32'habcdef01; + repeat (5) @(negedge clock); + reset = 0; + end + always @(posedge clock) begin + cycles <= cycles + 1; + if (!reset && passed) begin + $display("PASS GLOBALROB RAM/register cycle comparison, payloads, wrap, stalls, resets cycles=%0d", cycles); + $finish; + end + if (cycles > 15000) $fatal(1, "GlobalROB test timeout"); + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/BOARD_REGRESSION.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/BOARD_REGRESSION.json new file mode 100644 index 0000000..79e2fd2 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/BOARD_REGRESSION.json @@ -0,0 +1,41 @@ +{ + "result": "PASS", + "tests": { + "cpu": { + "result": "PASS", + "test": "cpu", + "binary_sha256": "3bbf33f7bf2b6bb0f3888ab4a649a11272de3f74458f6ea36b266f9670df75f5", + "original_cpu_oracle": true, + "ddr_phy_simulated": false, + "physical_linux_boot_tested": false, + "cycles": 709434 + }, + "gemmini": { + "result": "PASS", + "test": "gemmini", + "binary_sha256": "d6307d194aadb9f23e14edf695ce98ab1ea361881237576b15c251573af2826e", + "original_cpu_oracle": true, + "ddr_phy_simulated": false, + "physical_linux_boot_tested": false, + "cycles": 251063 + }, + "loop": { + "result": "PASS", + "test": "loop", + "binary_sha256": "bbe9646dc565ac9ac1188c6b3d53d24b1b37985ee158ee2ac918df04c3267ce2", + "original_cpu_oracle": true, + "ddr_phy_simulated": false, + "physical_linux_boot_tested": false, + "cycles": 684219 + }, + "dma": { + "result": "PASS", + "test": "dma", + "binary_sha256": "082965476d4dcc98cc556b8f79fa2fdf659cea501665e207d04349d40469e9d2", + "original_cpu_oracle": true, + "ddr_phy_simulated": false, + "physical_linux_boot_tested": false, + "cycles": 1914839 + } + } +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/board-unit/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/board-unit/RESULT.json new file mode 100644 index 0000000..62b7f31 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/board-unit/RESULT.json @@ -0,0 +1,18 @@ +{ + "result": "PASS", + "tests": 3, + "physical_mig_simulated": false, + "sources": { + "board/loader_axi.sv": "05609b0870054ea675aedb406f6215cd456f18db6d6428b461cbae03d9a662f4", + "board/flash_spi_byte.sv": "4d1fac5238f31fb3a69a58d1aca9ccec722e833d788113b94d86c6a1b861045a", + "board/uart_rx.sv": "0b35263884577324f146ff7fd516e5b561dcc8787e0d8ad599669bac1958406d", + "board/toy_a7_top.sv": "c8af97f543b8ae5d6dc21a85ba13b16a28fe3ba5bf93f8051c9e38c99f3350bd", + "board/ddr_uart_loader.sv": "980f4cd2e3fa2a00b66143f879bc749ed952c2c1e54331460821bac0300c43d6", + "board/axi_scu.sv": "ee77bf641d61811b4c1faea845752850c22461a63b4cdfd3d6f9cd223e6c2fc2", + "board/toy_a7_platform.sv": "01fe1f8e2621a1a023ac3b8d91758868b190760f6e706ae1d34a67857b96d846", + "board/axi_fullwidth.sv": "bf07ae27724dbd0a361d732dfb57109f06beef207c47a066d400cb06d7f07d5a", + "board/uart_tx.sv": "c20d420fc20be4f6313bdde5abc45ef0b9f8e93bf75350dd9951bc8868b3b65c", + "tests/tb_axi_fullwidth.sv": "1d3964fab0eaa76a6f864f07a7dedf01639ba12a9400a15d0839e707ab73c4ed", + "tests/tb_axi_scu.sv": "5dfd1d6cac3201f0e5188e9b73e60ade27c4551570d4b00d387301713d9fbe97" + } +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/cpu/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/cpu/RESULT.json new file mode 100644 index 0000000..8849267 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/cpu/RESULT.json @@ -0,0 +1,9 @@ +{ + "result": "PASS", + "test": "cpu", + "binary_sha256": "3bbf33f7bf2b6bb0f3888ab4a649a11272de3f74458f6ea36b266f9670df75f5", + "original_cpu_oracle": true, + "ddr_phy_simulated": false, + "physical_linux_boot_tested": false, + "cycles": 709434 +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/cpu/compile.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/cpu/compile.log new file mode 100644 index 0000000..bb2cd6d --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/cpu/compile.log @@ -0,0 +1,2197 @@ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:31:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 31 | module NonSyncResetSynchronizerPrimitiveShiftReg_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ + ... For warning description see https://verilator.org/warn/TIMESCALEMOD?v=5.050 + ... Use "/* verilator lint_off TIMESCALEMOD */" and lint_on around source to disable this message. +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:48:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 48 | module SynchronizerShiftReg_w1_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:61:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 61 | module IntSyncAsyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:74:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 74 | module AsyncResetRegVec_w1_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:103:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 103 | module IntSyncCrossingSource_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:118:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 118 | module FixedClockBroadcast_3( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:139:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 139 | module TLMonitor( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:987:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 987 | module TLMonitor_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:2434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 2434 | module TLXbar_sbus_i2_o3_a32d128s3k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:3195:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3195 | module TLMonitor_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4151 | module Repeater_TLBundleA_a28d128s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4218 | module TLWidthWidget16( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4386 | module TLInterconnectCoupler_sbus_to_bus_named_cbus( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4478:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4478 | module ram_2x58( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4497:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4497 | module Queue2_AXI4BundleAW( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4581:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4581 | module ram_2x73( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4600:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4600 | module Queue2_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4657:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4657 | module ram_2x4( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4676:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4676 | module Queue2_AXI4BundleB( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4729:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4729 | module Queue2_AXI4BundleAR( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4813:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4813 | module ram_2x69( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4832:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4832 | module Queue2_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4891:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4891 | module AXI4Buffer( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5067:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5067 | module ram_2x8( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5086:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5086 | module Queue2_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5143:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5143 | module Queue1_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5178 | module AXI4UserYanker( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5540:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5540 | module ram_8x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5559:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5559 | module Queue8_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5631 | module AXI4Deinterleaver( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:6073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6073 | module AXI4IdIndexer( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:6219:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6219 | module TLMonitor_3( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7048:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7048 | module Queue1_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7082:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7082 | module Queue1_AXI4BundleARW( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7148:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7148 | module TLToAXI4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7529:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7529 | module TLMonitor_4( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8396:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8396 | module Repeater_TLBundleA_a31d128s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8463 | module TLWidthWidget16_2( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8623:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8623 | module TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:9400:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 9400 | module SystemBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10050 | module FixedClockBroadcast_4( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10073 | module TLMonitor_5( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10975:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10975 | module TLXbar_cbus_out_i1_o4_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:11288:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +11288 | module TLMonitor_6( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12202:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12202 | module ram_2x114( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12221 | module Queue2_TLBundleA_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12301 | module ram_2x79( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12320:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12320 | module Queue2_TLBundleD_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12399:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12399 | module TLBuffer_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12534:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12534 | module TLMonitor_7( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:13449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13449 | module TLAtomicAutomata_cbus( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:13973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13973 | module TLMonitor_8( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14799 | module Queue1_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14846:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14846 | module TLError( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14953 | module TLMonitor_9( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15857 | module ram_2x100( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15876:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15876 | module Queue2_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15955:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15955 | module Queue2_TLBundleD_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16028 | module TLBuffer_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16155 | module ErrorDeviceWrapper( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16258 | module TLMonitor_10( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17017:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17017 | module Repeater_TLBundleA_a26d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17081:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17081 | module TLFragmenter_CLINT( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17261:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17261 | module TLInterconnectCoupler_cbus_to_clint( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17336:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17336 | module TLMonitor_11( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18106:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18106 | module Repeater_TLBundleA_a28d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18170:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18170 | module TLFragmenter_PLIC( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18350 | module TLInterconnectCoupler_cbus_to_plic( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18425:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18425 | module TLMonitor_12( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19040 | module Repeater_TLBundleA_a17d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19104:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19104 | module TLFragmenter_bootrom( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19263:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19263 | module TLInterconnectCoupler_cbus_to_bootrom( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19330:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19330 | module PeripheryBus_cbus( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19882 | module TLMonitor_13( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20610:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20610 | module ProbePicker( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20688:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20688 | module ram_2x10( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20707:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20707 | module Queue2_BundleMap_6( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20764:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20764 | module AXI4UserYanker_1( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:21713:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21713 | module AXI4IdIndexer_1( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:21859:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21859 | module TLMonitor_14( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22587:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22587 | module Queue1_AXI4BundleW_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22621 | module Queue1_AXI4BundleARW_1( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22687:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22687 | module TLToAXI4_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:23555:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +23555 | module TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:24031:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24031 | module MemoryBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:24349:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24349 | module TLMonitor_15( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25732:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25732 | module BroadcastFilter( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25756:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25756 | module ram_4x144( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25775:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25775 | module Queue4_TLBroadcastData( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25828:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25828 | module TLBroadcastTracker( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25964:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25964 | module TLBroadcastTracker_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:26100:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26100 | module TLBroadcast( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:26686:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26686 | module TLMonitor_16( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:27414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27414 | module BankBinder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:27491:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27491 | module CoherenceManagerWrapper( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:27669:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27669 | module TLMonitor_17( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29229:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29229 | module TLMonitor_18( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29635:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29635 | module TLXbar_MasterXbar_BBTile_i2_o1_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29898 | module IntXbar_i4_o1( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29918:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29918 | module WritebackUnit( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30014:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30014 | module ProbeUnit( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30154:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30154 | module Arbiter1_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30168:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30168 | module Arbiter1_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30191 | module Arbiter1_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30214 | module Arbiter1_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30249:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30249 | module Arbiter1_Bool( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30258 | module ram_16x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30277:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30277 | module Queue16_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30360:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30360 | module Queue1_TLBundleE_a32d128s1k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30388:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30388 | module MSHR( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30835:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30835 | module Arbiter1_HellaCacheResp( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30879:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30879 | module IOMSHR( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:31790:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31790 | module sdq_17x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:31809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31809 | module MSHRFile( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:32350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32350 | module OptimizationBarrier_TLBEntryData( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:32406:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32406 | module PMPChecker_s3( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:32691:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32691 | module PMAChecker( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:32731:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32731 | module DTLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:35923:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35923 | module L1MetadataArray( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:35990:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35990 | module Arbiter5_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36023:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36023 | module Arbiter2_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36055 | module DataArray( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36151 | module Arbiter4_L1DataReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36180:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36180 | module Arbiter2_L1DataWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36206:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36206 | module AMOALU( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36248:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36248 | module MaxPeriodFibonacciLFSR( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36342:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36342 | module Arbiter2_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36377:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36377 | module NonBlockingDCache( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:37660:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37660 | module ICache( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:37914:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37914 | module ShiftQueue( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:38054:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38054 | module PMPChecker_s2( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:38215:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38215 | module ITLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:41129:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41129 | module Frontend( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:41494:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41494 | module TLMonitor_19( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:42301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +42301 | module TLMonitor_20( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43108:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43108 | module TLXbar_i2_o1_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43343 | module TLMonitor_21( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43851:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43851 | module ram_2x116( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43870:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43870 | module Queue2_TLBundleA_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43947:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43947 | module ram_2x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43966:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43966 | module Queue2_TLBundleD_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44045:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44045 | module TLBuffer_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44158:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44158 | module TLMonitor_22( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44783 | module TLBuffer_a32d64s1k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44892:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44892 | module TLMonitor_23( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:45699:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45699 | module Repeater_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:45766:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45766 | module TLWidthWidget8_4( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:46074:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46074 | module TLMonitor_24( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:46882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46882 | module ram_2x117( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:46901:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46901 | module Queue2_TLBundleA_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:46981:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46981 | module ram_2x78( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47000:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47000 | module Queue2_TLBundleD_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47079:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47079 | module TLBuffer_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47214 | module HellaCacheArbiter( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47381 | module Arbiter3_Valid_PTWReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47419:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47419 | module OptimizationBarrier_UInt( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47427 | module OptimizationBarrier_PTE( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47459 | module PTW( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:48434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +48434 | module FPUDecoder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:49794:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49794 | module CompareRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:49824:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49824 | module RecFNToIN_e11_s53_i64( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:49873:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49873 | module RecFNToIN_e11_s53_i32( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:49912:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49912 | module FPToInt( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50375:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50375 | module RoundAnyRawFNToRecFN_ie7_is64_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50410:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50410 | module PipelinedINToRecFN( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50513:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50513 | module RoundAnyRawFNToRecFN_ie7_is64_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50539 | module PipelinedINToRecFN_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50614 | module RoundAnyRawFNToRecFN_ie7_is64_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50642:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50642 | module PipelinedINToRecFN_2( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50717 | module IntToFP( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51072:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51072 | module RoundAnyRawFNToRecFN_ie11_is53_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51199:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51199 | module RecFNToRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51221 | module RoundAnyRawFNToRecFN_ie11_is53_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51321:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51321 | module RecFNToRecFN_1( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51343 | module FPToFP( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51469:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51469 | module MulAddRecFNToRaw_preMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51569 | module MulAddRecFNToRaw_postMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51822:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51822 | module RoundAnyRawFNToRecFN_ie11_is55_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51953 | module RoundAnyRawFNToRecFN_ie11_is55_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52060:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52060 | module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52194:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52194 | module SharedMulAddRecFNPipe( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52551:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52551 | module FPUSharedFMAPipe( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52682:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52682 | module DivSqrtRawFN_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52852:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52852 | module DivSqrtRecFMToRaw_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52907:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52907 | module RoundAnyRawFNToRecFN_ie5_is13_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53039:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53039 | module RoundRawFNToRecFN_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53068:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53068 | module DivSqrtRecFM_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53128:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53128 | module DivSqrtRawFN_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53297:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53297 | module DivSqrtRecFMToRaw_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53352:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53352 | module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53456:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53456 | module RoundRawFNToRecFN_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53485:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53485 | module DivSqrtRecFM_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53545:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53545 | module DivSqrtRawFN_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53715:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53715 | module DivSqrtRecFMToRaw_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53770:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53770 | module RoundRawFNToRecFN_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53799 | module DivSqrtRecFM_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53860:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53860 | module regfile_32x65( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53905:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53905 | module FPU( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:54820:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +54820 | module RVCExpander( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:55183:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55183 | module IBuf( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:55307:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55307 | module CSRFile( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:57223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57223 | module RocketALU( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:57809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57809 | module MulDiv( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:58107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58107 | module Arbiter3_LLWB( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:58125:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58125 | module rf_31x64( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:58149:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58149 | module RocketBB( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62838:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62838 | module GlobalDecoder( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62928:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62928 | module BankAliasTable( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:64252:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64252 | module BankScoreboard( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:64627:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64627 | module GlobalROB( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68674:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68674 | module Arbiter3_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68717 | module ram_16x4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68736:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68736 | module Queue16_UInt4( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68782:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68782 | module SubROB( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:69357:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69357 | module Arbiter1_SubRobRow( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:69722:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69722 | module GlobalScheduler( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:70973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +70973 | module BootRom( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:71013:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71013 | module Frontend_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:71637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71637 | module PE( + | ^~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:71656:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71656 | module AlwaysOutTransposer( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:72411:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72411 | module MacUnit( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:72426:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72426 | module PE_64( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:72524:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72524 | module Tile( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:72571:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72571 | module Mesh( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76050 | module TagQueue( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76191 | module ram_6x7( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76210:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76210 | module Queue6_TagWithIdAndTotalRows( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76271:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76271 | module MeshWithDelays( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77318:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77318 | module ram_data_8x64( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77337 | module Queue8_SramReadResp( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77385:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77385 | module GemminiExCtrl( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79354:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79354 | module LoopMatmulUnroller( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79637 | module LoopConvAddrGen( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79690:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79690 | module LoopConvUnroller( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:80113:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80113 | module LoopCmdEncoder( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:80402:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80402 | module Arbiter2_LoopCmd( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:80598:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80598 | module GemminiBall( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:81783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81783 | module RRArbiter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:81857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81857 | module CmdRouter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:81985:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81985 | module BallCyclePMC( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:82095:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82095 | module BBus( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:82898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82898 | module BallDomainDecoder( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83028 | module ram_4x281( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83047:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83047 | module Queue4_BallReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83178 | module Arbiter1_BallRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83198:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83198 | module BallReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83328:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83328 | module BallDomain( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84141:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84141 | module MemDomainDecoder( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84300:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84300 | module ram_4x158( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84319:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84319 | module Queue4_MemReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84421:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84421 | module Arbiter3_MemRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84463 | module MemReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84631 | module MemLoader( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84869:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84869 | module MemStorer( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85122:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85122 | module MemCyclePMC( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85241:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85241 | module TLB( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85621 | module RRArbiter_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85649:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85649 | module BBTLBCluster( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85777 | module StreamReader( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86142:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86142 | module StreamWriter( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86223 | module ZeroLineGenerator( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86264:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86264 | module MemConfiger( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86433:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86433 | module RRArbiter_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86465:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86465 | module MemGroupQueryArbiter( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86543:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86543 | module MemFrontend( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:87160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87160 | module MemMidend( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:87621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87621 | module SramBank( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:87672:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87672 | module AccPipe( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:87781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87781 | module PrivateMemBackend( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:90777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +90777 | module MemBackend( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:91055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91055 | module MemDomain( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:91973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91973 | module Queue1_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:92008:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92008 | module GpDomain( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:92040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92040 | module ram_8x21( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:92059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92059 | module Queue8_BuckyballAccelerator_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:92123:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92123 | module BuckyballAccelerator( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93569 | module Queue3_UInt2( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93614 | module SimpleHellaCacheIFReplayQueue( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93667:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93667 | module Arbiter2_HellaCacheReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93678:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93678 | module SimpleHellaCacheIF( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93768:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93768 | module BarrierUnit( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93785:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93785 | module BBTile( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:95579:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +95579 | module TLMonitor_25( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:96427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +96427 | module TLMonitor_26( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98184:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98184 | module ram_2x189( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98203:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98203 | module Queue2_TLBundleA_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98283:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98283 | module ram_2x142( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98302:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98302 | module Queue2_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98381 | module Queue2_TLBundleA_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98459 | module Queue2_TLBundleD_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98539 | module ram_2x60( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98558:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98558 | module Queue2_TLBundleB_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98622:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98622 | module ram_2x173( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98641:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98641 | module Queue2_TLBundleC_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98716:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98716 | module ram_sink_2x1( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98735:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98735 | module Queue2_TLBundleE_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98781 | module TLBuffer_a32d128s2k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99162:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99162 | module IntSyncSyncCrossingSink_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99173:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99173 | module IntSyncSyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99181:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99181 | module TilePRCIDomain( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99589:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99589 | module BundleBridgeNexus_UInt1_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99597:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99597 | module TLMonitor_27( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100216:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100216 | module CLINT( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100337 | module AsyncResetRegVec_w2_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100366:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100366 | module IntSyncCrossingSource_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100386 | module CLINTClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100449 | module TLMonitor_28( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101080:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101080 | module LevelGateway( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101099:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101099 | module PLICFanIn( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101111:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101111 | module Queue1_RegMapperInput_i23_m8( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101160 | module TLPLIC( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101389:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101389 | module PLICClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101452:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101452 | module TLMonitor_29( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101973 | module TLROM( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:102530:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102530 | module bootromClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:102569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102569 | module ToyLinuxSystem( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:103817:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103817 | module ToyLinuxChip( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:103984:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103984 | module tag_array( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104007:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104007 | module array_0_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104034:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104034 | module array_0_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104059 | module array_2_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104084:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104084 | module array_2_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104109:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104109 | module bbtile_icache_tag_array( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104132:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104132 | module bbtile_icache_data_arrays_0( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104155 | module bbtile_icache_data_arrays_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104176:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104176 | module bbtile_icache_data_arrays_2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104197:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104197 | module bbtile_icache_data_arrays_3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104218 | module robOperands( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104243:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104243 | module sram( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104268:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104268 | module mem( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104301 | module plusarg_reader #( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104326:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104326 | module ITraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104404:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104404 | module FpgaDspMac(input [7:0] a, b, input [19:0] c, output [19:0] y); + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104414 | module PMCTraceDPI( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104464:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104464 | module MemPMCTraceDPI( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104514:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104514 | module MTraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:1:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 1 | module tag_array_ext( input [4:0] RW0_addr, + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 19 | module array_0_0_ext( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:37:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 37 | module bbtile_icache_tag_array_ext( input [5:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:55:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 55 | module bbtile_icache_data_arrays_0_ext( input [7:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:73:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 73 | module robOperands_ext( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:90:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 90 | module sram_ext( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 107 | module mem_ext( input [9:0] RW0_addr, + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:3:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3 | module axi_smoke_memory #( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_tx.sv:27:15: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.transmitter' + 27 | count <= DIVISOR - 1; + | ^~ + ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=5.050 + ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_tx.sv:32:13: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.transmitter' + 32 | count <= DIVISOR - 1; + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_rx.sv:23:55: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.receiver' + 23 | IDLE: if (!rx_sync) begin state <= START; count <= DIVISOR/2 - 1; end + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_rx.sv:26:57: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.receiver' + 26 | else begin state <= DATA; bit_index <= 0; count <= DIVISOR - 1; end + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_rx.sv:29:46: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.receiver' + 29 | shift[bit_index] <= rx_sync; count <= DIVISOR - 1; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:32:43: Operator ADD expects 33 bits on the RHS, but RHS's VARREF 'length' generates 16 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 32 | wire [32:0] end_address = {1'b0,address}+length; + | ^ + ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=5.050 + ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:35:38: Operator ADD expects 32 bits on the RHS, but RHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 35 | wire [31:0] byte_address = address + cursor; + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:67:32: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's SHIFTR generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 67 | 11,12,13,14:tx_data=RAM_BYTES >> ((reply_index-11)*8); + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:68:32: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's SHIFTR generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 68 | 15,16,17,18:tx_data=CLOCK_HZ >> ((reply_index-15)*8); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:73:28: Operator EQ expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 73 | else if(reply_index==7+reply_length) tx_data=crc[7:0]; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:64:23: Operator LT expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 64 | if(reply_index<7+reply_length) begin + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:119:20: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 119 | if(cursor+1==length) state<=CRC0; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:144:25: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 144 | else if(cursor+1==length) begin image_loaded<=1;state<=REPLY;end + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:152:20: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 152 | if(cursor+1==length) state<=REPLY; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:157:43: Operator LT expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 157 | if(reply_index>=2 && reply_index<7+reply_length) crc<=crc_next(crc,tx_data); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:158:25: Operator EQ expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 158 | if(reply_index==8+reply_length) state<=DRAIN; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:87:37: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'timeout_count' generates 22 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 87 | if((receiving && timeout_count==RX_TIMEOUT-1) || (receiving && rx_error)) begin + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:52:20: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'addr' generates 28 bits. + : ... note: In instance 'tb_board_cpu.memory' + 52 | offset=(addr & ~(LANES-1))-BASE; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:78:28: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'write_addr' generates 28 bits. + : ... note: In instance 'tb_board_cpu.memory' + 78 | offset=(write_addr & ~(LANES-1))-BASE; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:86:26: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'h600d600d' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 86 | if (w_bits_data==64'h600d600d) begin + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:91:66: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 91 | $fatal(1,"CPU smoke failed at stage %0d",w_bits_data & 64'hffff); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:90:28: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff0000' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:90:43: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'hbad00000' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_platform.sv:406:33: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's REDOR generates 1 bits. + : ... note: In instance 'tb_board_cpu.platform' + 406 | assign peripherals_b_bits_resp=|scu_bresp; + | ^ +make: Entering directory '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/obj' +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_timing.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_timing.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_threads.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_threads.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb_board_cpu__pch.h -o Vtb_board_cpu__pch.h.fast.gch +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb_board_cpu__pch.h -o Vtb_board_cpu__pch.h.slow.gch +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu__ConstPool__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__1__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__2__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__3__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu__Syms__Slow.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__0.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__1.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__2.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__3.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__4.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__5.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__6.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__7.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__8.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__9.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu__main.cpp +g++ verilated.o verilated_timing.o verilated_threads.o Vtb_board_cpu__ALL.a -pthread -lpthread -latomic -o Vtb_board_cpu +rm Vtb_board_cpu__ALL.verilator_deplist.tmp +make: Leaving directory '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/obj' +- V e r i l a t i o n R e p o r t: Verilator 5.050 2026-07-01 rev v5.050 +- Verilator: Built from 46.457 MB sources in 354 modules, into 26.450 MB in 19 C++ files needing 0.019 MB +- Verilator: Walltime 13.059 s (elab=0.532, cvt=3.209, bld=8.739); cpu 4.565 s on 8 threads; allocated 565.285 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/cpu/simulation.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/cpu/simulation.log new file mode 100644 index 0000000..a0088f8 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/cpu/simulation.log @@ -0,0 +1,5 @@ +PASS CPU Sv39/FPU/AMO/cache/interrupt through board AXI/SCU cycles=709434 +- /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:56: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 7ms; walltime 5.829 s; speed 1.217 ms/s +- Verilator: cpu 5.826 s on 1 threads; allocated 8 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/dma/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/dma/RESULT.json new file mode 100644 index 0000000..7f02844 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/dma/RESULT.json @@ -0,0 +1,9 @@ +{ + "result": "PASS", + "test": "dma", + "binary_sha256": "082965476d4dcc98cc556b8f79fa2fdf659cea501665e207d04349d40469e9d2", + "original_cpu_oracle": true, + "ddr_phy_simulated": false, + "physical_linux_boot_tested": false, + "cycles": 1914839 +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/dma/compile.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/dma/compile.log new file mode 100644 index 0000000..f2a9394 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/dma/compile.log @@ -0,0 +1,2197 @@ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:31:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 31 | module NonSyncResetSynchronizerPrimitiveShiftReg_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ + ... For warning description see https://verilator.org/warn/TIMESCALEMOD?v=5.050 + ... Use "/* verilator lint_off TIMESCALEMOD */" and lint_on around source to disable this message. +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:48:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 48 | module SynchronizerShiftReg_w1_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:61:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 61 | module IntSyncAsyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:74:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 74 | module AsyncResetRegVec_w1_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:103:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 103 | module IntSyncCrossingSource_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:118:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 118 | module FixedClockBroadcast_3( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:139:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 139 | module TLMonitor( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:987:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 987 | module TLMonitor_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:2434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 2434 | module TLXbar_sbus_i2_o3_a32d128s3k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:3195:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3195 | module TLMonitor_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4151 | module Repeater_TLBundleA_a28d128s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4218 | module TLWidthWidget16( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4386 | module TLInterconnectCoupler_sbus_to_bus_named_cbus( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4478:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4478 | module ram_2x58( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4497:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4497 | module Queue2_AXI4BundleAW( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4581:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4581 | module ram_2x73( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4600:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4600 | module Queue2_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4657:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4657 | module ram_2x4( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4676:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4676 | module Queue2_AXI4BundleB( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4729:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4729 | module Queue2_AXI4BundleAR( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4813:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4813 | module ram_2x69( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4832:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4832 | module Queue2_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4891:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4891 | module AXI4Buffer( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5067:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5067 | module ram_2x8( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5086:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5086 | module Queue2_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5143:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5143 | module Queue1_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5178 | module AXI4UserYanker( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5540:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5540 | module ram_8x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5559:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5559 | module Queue8_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5631 | module AXI4Deinterleaver( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:6073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6073 | module AXI4IdIndexer( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:6219:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6219 | module TLMonitor_3( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7048:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7048 | module Queue1_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7082:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7082 | module Queue1_AXI4BundleARW( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7148:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7148 | module TLToAXI4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7529:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7529 | module TLMonitor_4( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8396:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8396 | module Repeater_TLBundleA_a31d128s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8463 | module TLWidthWidget16_2( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8623:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8623 | module TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:9400:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 9400 | module SystemBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10050 | module FixedClockBroadcast_4( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10073 | module TLMonitor_5( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10975:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10975 | module TLXbar_cbus_out_i1_o4_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:11288:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +11288 | module TLMonitor_6( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12202:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12202 | module ram_2x114( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12221 | module Queue2_TLBundleA_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12301 | module ram_2x79( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12320:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12320 | module Queue2_TLBundleD_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12399:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12399 | module TLBuffer_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12534:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12534 | module TLMonitor_7( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:13449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13449 | module TLAtomicAutomata_cbus( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:13973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13973 | module TLMonitor_8( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14799 | module Queue1_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14846:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14846 | module TLError( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14953 | module TLMonitor_9( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15857 | module ram_2x100( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15876:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15876 | module Queue2_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15955:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15955 | module Queue2_TLBundleD_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16028 | module TLBuffer_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16155 | module ErrorDeviceWrapper( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16258 | module TLMonitor_10( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17017:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17017 | module Repeater_TLBundleA_a26d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17081:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17081 | module TLFragmenter_CLINT( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17261:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17261 | module TLInterconnectCoupler_cbus_to_clint( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17336:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17336 | module TLMonitor_11( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18106:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18106 | module Repeater_TLBundleA_a28d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18170:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18170 | module TLFragmenter_PLIC( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18350 | module TLInterconnectCoupler_cbus_to_plic( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18425:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18425 | module TLMonitor_12( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19040 | module Repeater_TLBundleA_a17d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19104:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19104 | module TLFragmenter_bootrom( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19263:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19263 | module TLInterconnectCoupler_cbus_to_bootrom( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19330:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19330 | module PeripheryBus_cbus( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19882 | module TLMonitor_13( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20610:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20610 | module ProbePicker( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20688:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20688 | module ram_2x10( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20707:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20707 | module Queue2_BundleMap_6( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20764:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20764 | module AXI4UserYanker_1( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:21713:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21713 | module AXI4IdIndexer_1( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:21859:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21859 | module TLMonitor_14( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22587:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22587 | module Queue1_AXI4BundleW_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22621 | module Queue1_AXI4BundleARW_1( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22687:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22687 | module TLToAXI4_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:23555:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +23555 | module TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:24031:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24031 | module MemoryBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:24349:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24349 | module TLMonitor_15( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25732:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25732 | module BroadcastFilter( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25756:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25756 | module ram_4x144( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25775:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25775 | module Queue4_TLBroadcastData( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25828:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25828 | module TLBroadcastTracker( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25964:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25964 | module TLBroadcastTracker_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:26100:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26100 | module TLBroadcast( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:26686:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26686 | module TLMonitor_16( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:27414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27414 | module BankBinder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:27491:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27491 | module CoherenceManagerWrapper( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:27669:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27669 | module TLMonitor_17( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29229:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29229 | module TLMonitor_18( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29635:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29635 | module TLXbar_MasterXbar_BBTile_i2_o1_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29898 | module IntXbar_i4_o1( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29918:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29918 | module WritebackUnit( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30014:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30014 | module ProbeUnit( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30154:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30154 | module Arbiter1_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30168:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30168 | module Arbiter1_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30191 | module Arbiter1_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30214 | module Arbiter1_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30249:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30249 | module Arbiter1_Bool( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30258 | module ram_16x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30277:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30277 | module Queue16_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30360:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30360 | module Queue1_TLBundleE_a32d128s1k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30388:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30388 | module MSHR( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30835:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30835 | module Arbiter1_HellaCacheResp( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30879:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30879 | module IOMSHR( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:31790:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31790 | module sdq_17x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:31809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31809 | module MSHRFile( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:32350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32350 | module OptimizationBarrier_TLBEntryData( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:32406:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32406 | module PMPChecker_s3( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:32691:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32691 | module PMAChecker( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:32731:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32731 | module DTLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:35923:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35923 | module L1MetadataArray( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:35990:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35990 | module Arbiter5_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36023:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36023 | module Arbiter2_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36055 | module DataArray( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36151 | module Arbiter4_L1DataReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36180:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36180 | module Arbiter2_L1DataWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36206:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36206 | module AMOALU( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36248:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36248 | module MaxPeriodFibonacciLFSR( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36342:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36342 | module Arbiter2_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36377:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36377 | module NonBlockingDCache( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:37660:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37660 | module ICache( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:37914:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37914 | module ShiftQueue( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:38054:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38054 | module PMPChecker_s2( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:38215:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38215 | module ITLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:41129:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41129 | module Frontend( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:41494:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41494 | module TLMonitor_19( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:42301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +42301 | module TLMonitor_20( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43108:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43108 | module TLXbar_i2_o1_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43343 | module TLMonitor_21( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43851:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43851 | module ram_2x116( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43870:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43870 | module Queue2_TLBundleA_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43947:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43947 | module ram_2x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43966:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43966 | module Queue2_TLBundleD_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44045:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44045 | module TLBuffer_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44158:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44158 | module TLMonitor_22( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44783 | module TLBuffer_a32d64s1k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44892:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44892 | module TLMonitor_23( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:45699:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45699 | module Repeater_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:45766:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45766 | module TLWidthWidget8_4( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:46074:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46074 | module TLMonitor_24( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:46882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46882 | module ram_2x117( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:46901:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46901 | module Queue2_TLBundleA_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:46981:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46981 | module ram_2x78( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47000:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47000 | module Queue2_TLBundleD_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47079:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47079 | module TLBuffer_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47214 | module HellaCacheArbiter( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47381 | module Arbiter3_Valid_PTWReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47419:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47419 | module OptimizationBarrier_UInt( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47427 | module OptimizationBarrier_PTE( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47459 | module PTW( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:48434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +48434 | module FPUDecoder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:49794:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49794 | module CompareRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:49824:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49824 | module RecFNToIN_e11_s53_i64( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:49873:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49873 | module RecFNToIN_e11_s53_i32( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:49912:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49912 | module FPToInt( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50375:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50375 | module RoundAnyRawFNToRecFN_ie7_is64_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50410:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50410 | module PipelinedINToRecFN( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50513:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50513 | module RoundAnyRawFNToRecFN_ie7_is64_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50539 | module PipelinedINToRecFN_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50614 | module RoundAnyRawFNToRecFN_ie7_is64_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50642:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50642 | module PipelinedINToRecFN_2( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50717 | module IntToFP( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51072:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51072 | module RoundAnyRawFNToRecFN_ie11_is53_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51199:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51199 | module RecFNToRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51221 | module RoundAnyRawFNToRecFN_ie11_is53_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51321:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51321 | module RecFNToRecFN_1( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51343 | module FPToFP( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51469:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51469 | module MulAddRecFNToRaw_preMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51569 | module MulAddRecFNToRaw_postMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51822:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51822 | module RoundAnyRawFNToRecFN_ie11_is55_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51953 | module RoundAnyRawFNToRecFN_ie11_is55_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52060:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52060 | module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52194:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52194 | module SharedMulAddRecFNPipe( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52551:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52551 | module FPUSharedFMAPipe( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52682:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52682 | module DivSqrtRawFN_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52852:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52852 | module DivSqrtRecFMToRaw_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52907:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52907 | module RoundAnyRawFNToRecFN_ie5_is13_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53039:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53039 | module RoundRawFNToRecFN_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53068:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53068 | module DivSqrtRecFM_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53128:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53128 | module DivSqrtRawFN_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53297:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53297 | module DivSqrtRecFMToRaw_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53352:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53352 | module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53456:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53456 | module RoundRawFNToRecFN_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53485:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53485 | module DivSqrtRecFM_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53545:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53545 | module DivSqrtRawFN_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53715:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53715 | module DivSqrtRecFMToRaw_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53770:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53770 | module RoundRawFNToRecFN_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53799 | module DivSqrtRecFM_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53860:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53860 | module regfile_32x65( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53905:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53905 | module FPU( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:54820:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +54820 | module RVCExpander( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:55183:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55183 | module IBuf( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:55307:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55307 | module CSRFile( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:57223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57223 | module RocketALU( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:57809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57809 | module MulDiv( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:58107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58107 | module Arbiter3_LLWB( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:58125:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58125 | module rf_31x64( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:58149:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58149 | module RocketBB( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62838:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62838 | module GlobalDecoder( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62928:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62928 | module BankAliasTable( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:64252:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64252 | module BankScoreboard( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:64627:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64627 | module GlobalROB( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68674:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68674 | module Arbiter3_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68717 | module ram_16x4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68736:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68736 | module Queue16_UInt4( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68782:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68782 | module SubROB( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:69357:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69357 | module Arbiter1_SubRobRow( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:69722:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69722 | module GlobalScheduler( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:70973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +70973 | module BootRom( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:71013:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71013 | module Frontend_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:71637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71637 | module PE( + | ^~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:71656:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71656 | module AlwaysOutTransposer( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:72411:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72411 | module MacUnit( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:72426:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72426 | module PE_64( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:72524:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72524 | module Tile( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:72571:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72571 | module Mesh( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76050 | module TagQueue( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76191 | module ram_6x7( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76210:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76210 | module Queue6_TagWithIdAndTotalRows( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76271:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76271 | module MeshWithDelays( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77318:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77318 | module ram_data_8x64( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77337 | module Queue8_SramReadResp( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77385:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77385 | module GemminiExCtrl( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79354:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79354 | module LoopMatmulUnroller( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79637 | module LoopConvAddrGen( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79690:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79690 | module LoopConvUnroller( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:80113:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80113 | module LoopCmdEncoder( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:80402:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80402 | module Arbiter2_LoopCmd( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:80598:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80598 | module GemminiBall( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:81783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81783 | module RRArbiter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:81857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81857 | module CmdRouter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:81985:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81985 | module BallCyclePMC( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:82095:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82095 | module BBus( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:82898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82898 | module BallDomainDecoder( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83028 | module ram_4x281( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83047:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83047 | module Queue4_BallReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83178 | module Arbiter1_BallRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83198:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83198 | module BallReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83328:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83328 | module BallDomain( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84141:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84141 | module MemDomainDecoder( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84300:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84300 | module ram_4x158( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84319:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84319 | module Queue4_MemReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84421:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84421 | module Arbiter3_MemRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84463 | module MemReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84631 | module MemLoader( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84869:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84869 | module MemStorer( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85122:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85122 | module MemCyclePMC( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85241:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85241 | module TLB( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85621 | module RRArbiter_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85649:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85649 | module BBTLBCluster( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85777 | module StreamReader( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86142:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86142 | module StreamWriter( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86223 | module ZeroLineGenerator( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86264:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86264 | module MemConfiger( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86433:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86433 | module RRArbiter_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86465:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86465 | module MemGroupQueryArbiter( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86543:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86543 | module MemFrontend( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:87160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87160 | module MemMidend( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:87621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87621 | module SramBank( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:87672:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87672 | module AccPipe( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:87781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87781 | module PrivateMemBackend( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:90777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +90777 | module MemBackend( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:91055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91055 | module MemDomain( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:91973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91973 | module Queue1_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:92008:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92008 | module GpDomain( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:92040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92040 | module ram_8x21( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:92059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92059 | module Queue8_BuckyballAccelerator_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:92123:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92123 | module BuckyballAccelerator( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93569 | module Queue3_UInt2( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93614 | module SimpleHellaCacheIFReplayQueue( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93667:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93667 | module Arbiter2_HellaCacheReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93678:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93678 | module SimpleHellaCacheIF( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93768:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93768 | module BarrierUnit( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93785:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93785 | module BBTile( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:95579:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +95579 | module TLMonitor_25( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:96427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +96427 | module TLMonitor_26( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98184:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98184 | module ram_2x189( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98203:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98203 | module Queue2_TLBundleA_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98283:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98283 | module ram_2x142( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98302:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98302 | module Queue2_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98381 | module Queue2_TLBundleA_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98459 | module Queue2_TLBundleD_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98539 | module ram_2x60( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98558:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98558 | module Queue2_TLBundleB_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98622:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98622 | module ram_2x173( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98641:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98641 | module Queue2_TLBundleC_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98716:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98716 | module ram_sink_2x1( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98735:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98735 | module Queue2_TLBundleE_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98781 | module TLBuffer_a32d128s2k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99162:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99162 | module IntSyncSyncCrossingSink_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99173:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99173 | module IntSyncSyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99181:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99181 | module TilePRCIDomain( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99589:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99589 | module BundleBridgeNexus_UInt1_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99597:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99597 | module TLMonitor_27( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100216:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100216 | module CLINT( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100337 | module AsyncResetRegVec_w2_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100366:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100366 | module IntSyncCrossingSource_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100386 | module CLINTClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100449 | module TLMonitor_28( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101080:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101080 | module LevelGateway( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101099:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101099 | module PLICFanIn( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101111:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101111 | module Queue1_RegMapperInput_i23_m8( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101160 | module TLPLIC( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101389:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101389 | module PLICClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101452:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101452 | module TLMonitor_29( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101973 | module TLROM( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:102530:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102530 | module bootromClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:102569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102569 | module ToyLinuxSystem( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:103817:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103817 | module ToyLinuxChip( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:103984:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103984 | module tag_array( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104007:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104007 | module array_0_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104034:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104034 | module array_0_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104059 | module array_2_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104084:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104084 | module array_2_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104109:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104109 | module bbtile_icache_tag_array( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104132:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104132 | module bbtile_icache_data_arrays_0( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104155 | module bbtile_icache_data_arrays_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104176:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104176 | module bbtile_icache_data_arrays_2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104197:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104197 | module bbtile_icache_data_arrays_3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104218 | module robOperands( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104243:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104243 | module sram( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104268:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104268 | module mem( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104301 | module plusarg_reader #( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104326:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104326 | module ITraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104404:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104404 | module FpgaDspMac(input [7:0] a, b, input [19:0] c, output [19:0] y); + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104414 | module PMCTraceDPI( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104464:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104464 | module MemPMCTraceDPI( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104514:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104514 | module MTraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:1:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 1 | module tag_array_ext( input [4:0] RW0_addr, + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 19 | module array_0_0_ext( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:37:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 37 | module bbtile_icache_tag_array_ext( input [5:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:55:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 55 | module bbtile_icache_data_arrays_0_ext( input [7:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:73:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 73 | module robOperands_ext( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:90:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 90 | module sram_ext( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 107 | module mem_ext( input [9:0] RW0_addr, + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:3:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3 | module axi_smoke_memory #( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_tx.sv:27:15: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.transmitter' + 27 | count <= DIVISOR - 1; + | ^~ + ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=5.050 + ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_tx.sv:32:13: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.transmitter' + 32 | count <= DIVISOR - 1; + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_rx.sv:23:55: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.receiver' + 23 | IDLE: if (!rx_sync) begin state <= START; count <= DIVISOR/2 - 1; end + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_rx.sv:26:57: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.receiver' + 26 | else begin state <= DATA; bit_index <= 0; count <= DIVISOR - 1; end + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_rx.sv:29:46: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.receiver' + 29 | shift[bit_index] <= rx_sync; count <= DIVISOR - 1; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:32:43: Operator ADD expects 33 bits on the RHS, but RHS's VARREF 'length' generates 16 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 32 | wire [32:0] end_address = {1'b0,address}+length; + | ^ + ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=5.050 + ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:35:38: Operator ADD expects 32 bits on the RHS, but RHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 35 | wire [31:0] byte_address = address + cursor; + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:67:32: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's SHIFTR generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 67 | 11,12,13,14:tx_data=RAM_BYTES >> ((reply_index-11)*8); + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:68:32: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's SHIFTR generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 68 | 15,16,17,18:tx_data=CLOCK_HZ >> ((reply_index-15)*8); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:73:28: Operator EQ expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 73 | else if(reply_index==7+reply_length) tx_data=crc[7:0]; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:64:23: Operator LT expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 64 | if(reply_index<7+reply_length) begin + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:119:20: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 119 | if(cursor+1==length) state<=CRC0; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:144:25: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 144 | else if(cursor+1==length) begin image_loaded<=1;state<=REPLY;end + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:152:20: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 152 | if(cursor+1==length) state<=REPLY; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:157:43: Operator LT expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 157 | if(reply_index>=2 && reply_index<7+reply_length) crc<=crc_next(crc,tx_data); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:158:25: Operator EQ expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 158 | if(reply_index==8+reply_length) state<=DRAIN; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:87:37: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'timeout_count' generates 22 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 87 | if((receiving && timeout_count==RX_TIMEOUT-1) || (receiving && rx_error)) begin + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:52:20: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'addr' generates 28 bits. + : ... note: In instance 'tb_board_cpu.memory' + 52 | offset=(addr & ~(LANES-1))-BASE; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:78:28: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'write_addr' generates 28 bits. + : ... note: In instance 'tb_board_cpu.memory' + 78 | offset=(write_addr & ~(LANES-1))-BASE; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:86:26: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'h600d600d' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 86 | if (w_bits_data==64'h600d600d) begin + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:91:66: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 91 | $fatal(1,"CPU smoke failed at stage %0d",w_bits_data & 64'hffff); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:90:28: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff0000' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:90:43: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'hbad00000' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_platform.sv:406:33: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's REDOR generates 1 bits. + : ... note: In instance 'tb_board_cpu.platform' + 406 | assign peripherals_b_bits_resp=|scu_bresp; + | ^ +make: Entering directory '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/obj' +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_timing.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_timing.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_threads.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_threads.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb_board_cpu__pch.h -o Vtb_board_cpu__pch.h.fast.gch +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb_board_cpu__pch.h -o Vtb_board_cpu__pch.h.slow.gch +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__0.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__1.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__2.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__3.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__4.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__5.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__6.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__7.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__8.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__9.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu__main.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu__ConstPool__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__1__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__2__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__3__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu__Syms__Slow.cpp +g++ verilated.o verilated_timing.o verilated_threads.o Vtb_board_cpu__ALL.a -pthread -lpthread -latomic -o Vtb_board_cpu +rm Vtb_board_cpu__ALL.verilator_deplist.tmp +make: Leaving directory '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/obj' +- V e r i l a t i o n R e p o r t: Verilator 5.050 2026-07-01 rev v5.050 +- Verilator: Built from 46.457 MB sources in 354 modules, into 26.450 MB in 19 C++ files needing 0.019 MB +- Verilator: Walltime 12.005 s (elab=0.530, cvt=3.142, bld=7.760); cpu 4.491 s on 8 threads; allocated 565.293 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/dma/simulation.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/dma/simulation.log new file mode 100644 index 0000000..283d53c --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/dma/simulation.log @@ -0,0 +1,5 @@ +PASS CPU Sv39/FPU/AMO/cache/interrupt through board AXI/SCU cycles=1914839 +- /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:56: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 19ms; walltime 14.201 s; speed 1.348 ms/s +- Verilator: cpu 14.194 s on 1 threads; allocated 8 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/gemmini/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/gemmini/RESULT.json new file mode 100644 index 0000000..e935317 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/gemmini/RESULT.json @@ -0,0 +1,9 @@ +{ + "result": "PASS", + "test": "gemmini", + "binary_sha256": "d6307d194aadb9f23e14edf695ce98ab1ea361881237576b15c251573af2826e", + "original_cpu_oracle": true, + "ddr_phy_simulated": false, + "physical_linux_boot_tested": false, + "cycles": 251063 +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/gemmini/compile.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/gemmini/compile.log new file mode 100644 index 0000000..03aa70f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/gemmini/compile.log @@ -0,0 +1,2197 @@ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:31:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 31 | module NonSyncResetSynchronizerPrimitiveShiftReg_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ + ... For warning description see https://verilator.org/warn/TIMESCALEMOD?v=5.050 + ... Use "/* verilator lint_off TIMESCALEMOD */" and lint_on around source to disable this message. +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:48:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 48 | module SynchronizerShiftReg_w1_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:61:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 61 | module IntSyncAsyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:74:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 74 | module AsyncResetRegVec_w1_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:103:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 103 | module IntSyncCrossingSource_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:118:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 118 | module FixedClockBroadcast_3( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:139:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 139 | module TLMonitor( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:987:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 987 | module TLMonitor_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:2434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 2434 | module TLXbar_sbus_i2_o3_a32d128s3k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:3195:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3195 | module TLMonitor_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4151 | module Repeater_TLBundleA_a28d128s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4218 | module TLWidthWidget16( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4386 | module TLInterconnectCoupler_sbus_to_bus_named_cbus( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4478:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4478 | module ram_2x58( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4497:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4497 | module Queue2_AXI4BundleAW( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4581:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4581 | module ram_2x73( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4600:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4600 | module Queue2_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4657:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4657 | module ram_2x4( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4676:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4676 | module Queue2_AXI4BundleB( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4729:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4729 | module Queue2_AXI4BundleAR( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4813:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4813 | module ram_2x69( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4832:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4832 | module Queue2_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4891:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4891 | module AXI4Buffer( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5067:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5067 | module ram_2x8( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5086:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5086 | module Queue2_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5143:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5143 | module Queue1_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5178 | module AXI4UserYanker( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5540:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5540 | module ram_8x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5559:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5559 | module Queue8_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5631 | module AXI4Deinterleaver( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:6073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6073 | module AXI4IdIndexer( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:6219:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6219 | module TLMonitor_3( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7048:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7048 | module Queue1_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7082:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7082 | module Queue1_AXI4BundleARW( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7148:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7148 | module TLToAXI4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7529:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7529 | module TLMonitor_4( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8396:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8396 | module Repeater_TLBundleA_a31d128s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8463 | module TLWidthWidget16_2( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8623:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8623 | module TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:9400:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 9400 | module SystemBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10050 | module FixedClockBroadcast_4( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10073 | module TLMonitor_5( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10975:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10975 | module TLXbar_cbus_out_i1_o4_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:11288:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +11288 | module TLMonitor_6( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12202:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12202 | module ram_2x114( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12221 | module Queue2_TLBundleA_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12301 | module ram_2x79( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12320:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12320 | module Queue2_TLBundleD_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12399:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12399 | module TLBuffer_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12534:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12534 | module TLMonitor_7( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:13449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13449 | module TLAtomicAutomata_cbus( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:13973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13973 | module TLMonitor_8( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14799 | module Queue1_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14846:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14846 | module TLError( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14953 | module TLMonitor_9( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15857 | module ram_2x100( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15876:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15876 | module Queue2_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15955:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15955 | module Queue2_TLBundleD_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16028 | module TLBuffer_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16155 | module ErrorDeviceWrapper( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16258 | module TLMonitor_10( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17017:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17017 | module Repeater_TLBundleA_a26d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17081:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17081 | module TLFragmenter_CLINT( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17261:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17261 | module TLInterconnectCoupler_cbus_to_clint( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17336:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17336 | module TLMonitor_11( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18106:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18106 | module Repeater_TLBundleA_a28d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18170:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18170 | module TLFragmenter_PLIC( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18350 | module TLInterconnectCoupler_cbus_to_plic( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18425:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18425 | module TLMonitor_12( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19040 | module Repeater_TLBundleA_a17d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19104:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19104 | module TLFragmenter_bootrom( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19263:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19263 | module TLInterconnectCoupler_cbus_to_bootrom( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19330:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19330 | module PeripheryBus_cbus( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19882 | module TLMonitor_13( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20610:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20610 | module ProbePicker( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20688:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20688 | module ram_2x10( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20707:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20707 | module Queue2_BundleMap_6( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20764:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20764 | module AXI4UserYanker_1( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:21713:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21713 | module AXI4IdIndexer_1( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:21859:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21859 | module TLMonitor_14( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22587:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22587 | module Queue1_AXI4BundleW_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22621 | module Queue1_AXI4BundleARW_1( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22687:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22687 | module TLToAXI4_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:23555:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +23555 | module TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:24031:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24031 | module MemoryBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:24349:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24349 | module TLMonitor_15( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25732:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25732 | module BroadcastFilter( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25756:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25756 | module ram_4x144( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25775:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25775 | module Queue4_TLBroadcastData( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25828:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25828 | module TLBroadcastTracker( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25964:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25964 | module TLBroadcastTracker_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:26100:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26100 | module TLBroadcast( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:26686:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26686 | module TLMonitor_16( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:27414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27414 | module BankBinder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:27491:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27491 | module CoherenceManagerWrapper( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:27669:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27669 | module TLMonitor_17( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29229:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29229 | module TLMonitor_18( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29635:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29635 | module TLXbar_MasterXbar_BBTile_i2_o1_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29898 | module IntXbar_i4_o1( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29918:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29918 | module WritebackUnit( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30014:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30014 | module ProbeUnit( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30154:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30154 | module Arbiter1_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30168:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30168 | module Arbiter1_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30191 | module Arbiter1_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30214 | module Arbiter1_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30249:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30249 | module Arbiter1_Bool( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30258 | module ram_16x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30277:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30277 | module Queue16_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30360:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30360 | module Queue1_TLBundleE_a32d128s1k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30388:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30388 | module MSHR( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30835:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30835 | module Arbiter1_HellaCacheResp( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30879:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30879 | module IOMSHR( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:31790:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31790 | module sdq_17x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:31809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31809 | module MSHRFile( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:32350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32350 | module OptimizationBarrier_TLBEntryData( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:32406:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32406 | module PMPChecker_s3( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:32691:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32691 | module PMAChecker( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:32731:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32731 | module DTLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:35923:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35923 | module L1MetadataArray( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:35990:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35990 | module Arbiter5_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36023:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36023 | module Arbiter2_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36055 | module DataArray( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36151 | module Arbiter4_L1DataReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36180:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36180 | module Arbiter2_L1DataWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36206:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36206 | module AMOALU( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36248:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36248 | module MaxPeriodFibonacciLFSR( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36342:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36342 | module Arbiter2_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36377:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36377 | module NonBlockingDCache( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:37660:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37660 | module ICache( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:37914:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37914 | module ShiftQueue( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:38054:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38054 | module PMPChecker_s2( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:38215:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38215 | module ITLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:41129:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41129 | module Frontend( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:41494:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41494 | module TLMonitor_19( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:42301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +42301 | module TLMonitor_20( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43108:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43108 | module TLXbar_i2_o1_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43343 | module TLMonitor_21( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43851:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43851 | module ram_2x116( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43870:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43870 | module Queue2_TLBundleA_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43947:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43947 | module ram_2x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43966:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43966 | module Queue2_TLBundleD_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44045:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44045 | module TLBuffer_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44158:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44158 | module TLMonitor_22( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44783 | module TLBuffer_a32d64s1k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44892:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44892 | module TLMonitor_23( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:45699:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45699 | module Repeater_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:45766:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45766 | module TLWidthWidget8_4( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:46074:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46074 | module TLMonitor_24( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:46882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46882 | module ram_2x117( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:46901:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46901 | module Queue2_TLBundleA_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:46981:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46981 | module ram_2x78( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47000:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47000 | module Queue2_TLBundleD_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47079:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47079 | module TLBuffer_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47214 | module HellaCacheArbiter( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47381 | module Arbiter3_Valid_PTWReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47419:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47419 | module OptimizationBarrier_UInt( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47427 | module OptimizationBarrier_PTE( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47459 | module PTW( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:48434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +48434 | module FPUDecoder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:49794:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49794 | module CompareRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:49824:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49824 | module RecFNToIN_e11_s53_i64( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:49873:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49873 | module RecFNToIN_e11_s53_i32( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:49912:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49912 | module FPToInt( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50375:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50375 | module RoundAnyRawFNToRecFN_ie7_is64_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50410:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50410 | module PipelinedINToRecFN( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50513:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50513 | module RoundAnyRawFNToRecFN_ie7_is64_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50539 | module PipelinedINToRecFN_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50614 | module RoundAnyRawFNToRecFN_ie7_is64_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50642:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50642 | module PipelinedINToRecFN_2( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50717 | module IntToFP( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51072:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51072 | module RoundAnyRawFNToRecFN_ie11_is53_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51199:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51199 | module RecFNToRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51221 | module RoundAnyRawFNToRecFN_ie11_is53_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51321:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51321 | module RecFNToRecFN_1( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51343 | module FPToFP( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51469:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51469 | module MulAddRecFNToRaw_preMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51569 | module MulAddRecFNToRaw_postMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51822:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51822 | module RoundAnyRawFNToRecFN_ie11_is55_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51953 | module RoundAnyRawFNToRecFN_ie11_is55_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52060:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52060 | module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52194:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52194 | module SharedMulAddRecFNPipe( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52551:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52551 | module FPUSharedFMAPipe( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52682:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52682 | module DivSqrtRawFN_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52852:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52852 | module DivSqrtRecFMToRaw_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52907:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52907 | module RoundAnyRawFNToRecFN_ie5_is13_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53039:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53039 | module RoundRawFNToRecFN_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53068:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53068 | module DivSqrtRecFM_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53128:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53128 | module DivSqrtRawFN_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53297:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53297 | module DivSqrtRecFMToRaw_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53352:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53352 | module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53456:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53456 | module RoundRawFNToRecFN_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53485:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53485 | module DivSqrtRecFM_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53545:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53545 | module DivSqrtRawFN_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53715:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53715 | module DivSqrtRecFMToRaw_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53770:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53770 | module RoundRawFNToRecFN_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53799 | module DivSqrtRecFM_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53860:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53860 | module regfile_32x65( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53905:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53905 | module FPU( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:54820:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +54820 | module RVCExpander( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:55183:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55183 | module IBuf( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:55307:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55307 | module CSRFile( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:57223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57223 | module RocketALU( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:57809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57809 | module MulDiv( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:58107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58107 | module Arbiter3_LLWB( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:58125:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58125 | module rf_31x64( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:58149:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58149 | module RocketBB( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62838:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62838 | module GlobalDecoder( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62928:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62928 | module BankAliasTable( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:64252:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64252 | module BankScoreboard( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:64627:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64627 | module GlobalROB( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68674:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68674 | module Arbiter3_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68717 | module ram_16x4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68736:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68736 | module Queue16_UInt4( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68782:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68782 | module SubROB( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:69357:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69357 | module Arbiter1_SubRobRow( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:69722:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69722 | module GlobalScheduler( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:70973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +70973 | module BootRom( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:71013:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71013 | module Frontend_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:71637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71637 | module PE( + | ^~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:71656:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71656 | module AlwaysOutTransposer( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:72411:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72411 | module MacUnit( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:72426:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72426 | module PE_64( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:72524:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72524 | module Tile( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:72571:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72571 | module Mesh( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76050 | module TagQueue( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76191 | module ram_6x7( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76210:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76210 | module Queue6_TagWithIdAndTotalRows( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76271:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76271 | module MeshWithDelays( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77318:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77318 | module ram_data_8x64( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77337 | module Queue8_SramReadResp( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77385:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77385 | module GemminiExCtrl( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79354:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79354 | module LoopMatmulUnroller( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79637 | module LoopConvAddrGen( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79690:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79690 | module LoopConvUnroller( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:80113:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80113 | module LoopCmdEncoder( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:80402:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80402 | module Arbiter2_LoopCmd( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:80598:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80598 | module GemminiBall( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:81783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81783 | module RRArbiter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:81857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81857 | module CmdRouter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:81985:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81985 | module BallCyclePMC( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:82095:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82095 | module BBus( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:82898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82898 | module BallDomainDecoder( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83028 | module ram_4x281( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83047:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83047 | module Queue4_BallReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83178 | module Arbiter1_BallRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83198:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83198 | module BallReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83328:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83328 | module BallDomain( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84141:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84141 | module MemDomainDecoder( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84300:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84300 | module ram_4x158( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84319:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84319 | module Queue4_MemReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84421:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84421 | module Arbiter3_MemRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84463 | module MemReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84631 | module MemLoader( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84869:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84869 | module MemStorer( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85122:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85122 | module MemCyclePMC( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85241:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85241 | module TLB( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85621 | module RRArbiter_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85649:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85649 | module BBTLBCluster( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85777 | module StreamReader( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86142:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86142 | module StreamWriter( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86223 | module ZeroLineGenerator( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86264:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86264 | module MemConfiger( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86433:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86433 | module RRArbiter_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86465:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86465 | module MemGroupQueryArbiter( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86543:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86543 | module MemFrontend( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:87160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87160 | module MemMidend( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:87621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87621 | module SramBank( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:87672:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87672 | module AccPipe( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:87781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87781 | module PrivateMemBackend( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:90777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +90777 | module MemBackend( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:91055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91055 | module MemDomain( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:91973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91973 | module Queue1_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:92008:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92008 | module GpDomain( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:92040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92040 | module ram_8x21( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:92059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92059 | module Queue8_BuckyballAccelerator_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:92123:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92123 | module BuckyballAccelerator( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93569 | module Queue3_UInt2( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93614 | module SimpleHellaCacheIFReplayQueue( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93667:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93667 | module Arbiter2_HellaCacheReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93678:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93678 | module SimpleHellaCacheIF( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93768:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93768 | module BarrierUnit( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93785:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93785 | module BBTile( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:95579:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +95579 | module TLMonitor_25( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:96427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +96427 | module TLMonitor_26( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98184:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98184 | module ram_2x189( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98203:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98203 | module Queue2_TLBundleA_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98283:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98283 | module ram_2x142( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98302:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98302 | module Queue2_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98381 | module Queue2_TLBundleA_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98459 | module Queue2_TLBundleD_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98539 | module ram_2x60( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98558:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98558 | module Queue2_TLBundleB_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98622:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98622 | module ram_2x173( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98641:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98641 | module Queue2_TLBundleC_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98716:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98716 | module ram_sink_2x1( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98735:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98735 | module Queue2_TLBundleE_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98781 | module TLBuffer_a32d128s2k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99162:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99162 | module IntSyncSyncCrossingSink_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99173:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99173 | module IntSyncSyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99181:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99181 | module TilePRCIDomain( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99589:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99589 | module BundleBridgeNexus_UInt1_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99597:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99597 | module TLMonitor_27( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100216:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100216 | module CLINT( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100337 | module AsyncResetRegVec_w2_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100366:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100366 | module IntSyncCrossingSource_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100386 | module CLINTClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100449 | module TLMonitor_28( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101080:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101080 | module LevelGateway( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101099:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101099 | module PLICFanIn( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101111:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101111 | module Queue1_RegMapperInput_i23_m8( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101160 | module TLPLIC( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101389:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101389 | module PLICClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101452:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101452 | module TLMonitor_29( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101973 | module TLROM( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:102530:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102530 | module bootromClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:102569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102569 | module ToyLinuxSystem( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:103817:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103817 | module ToyLinuxChip( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:103984:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103984 | module tag_array( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104007:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104007 | module array_0_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104034:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104034 | module array_0_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104059 | module array_2_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104084:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104084 | module array_2_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104109:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104109 | module bbtile_icache_tag_array( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104132:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104132 | module bbtile_icache_data_arrays_0( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104155 | module bbtile_icache_data_arrays_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104176:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104176 | module bbtile_icache_data_arrays_2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104197:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104197 | module bbtile_icache_data_arrays_3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104218 | module robOperands( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104243:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104243 | module sram( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104268:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104268 | module mem( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104301 | module plusarg_reader #( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104326:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104326 | module ITraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104404:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104404 | module FpgaDspMac(input [7:0] a, b, input [19:0] c, output [19:0] y); + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104414 | module PMCTraceDPI( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104464:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104464 | module MemPMCTraceDPI( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104514:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104514 | module MTraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:1:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 1 | module tag_array_ext( input [4:0] RW0_addr, + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 19 | module array_0_0_ext( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:37:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 37 | module bbtile_icache_tag_array_ext( input [5:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:55:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 55 | module bbtile_icache_data_arrays_0_ext( input [7:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:73:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 73 | module robOperands_ext( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:90:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 90 | module sram_ext( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 107 | module mem_ext( input [9:0] RW0_addr, + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:3:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3 | module axi_smoke_memory #( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_tx.sv:27:15: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.transmitter' + 27 | count <= DIVISOR - 1; + | ^~ + ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=5.050 + ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_tx.sv:32:13: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.transmitter' + 32 | count <= DIVISOR - 1; + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_rx.sv:23:55: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.receiver' + 23 | IDLE: if (!rx_sync) begin state <= START; count <= DIVISOR/2 - 1; end + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_rx.sv:26:57: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.receiver' + 26 | else begin state <= DATA; bit_index <= 0; count <= DIVISOR - 1; end + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_rx.sv:29:46: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.receiver' + 29 | shift[bit_index] <= rx_sync; count <= DIVISOR - 1; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:32:43: Operator ADD expects 33 bits on the RHS, but RHS's VARREF 'length' generates 16 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 32 | wire [32:0] end_address = {1'b0,address}+length; + | ^ + ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=5.050 + ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:35:38: Operator ADD expects 32 bits on the RHS, but RHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 35 | wire [31:0] byte_address = address + cursor; + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:67:32: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's SHIFTR generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 67 | 11,12,13,14:tx_data=RAM_BYTES >> ((reply_index-11)*8); + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:68:32: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's SHIFTR generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 68 | 15,16,17,18:tx_data=CLOCK_HZ >> ((reply_index-15)*8); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:73:28: Operator EQ expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 73 | else if(reply_index==7+reply_length) tx_data=crc[7:0]; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:64:23: Operator LT expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 64 | if(reply_index<7+reply_length) begin + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:119:20: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 119 | if(cursor+1==length) state<=CRC0; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:144:25: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 144 | else if(cursor+1==length) begin image_loaded<=1;state<=REPLY;end + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:152:20: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 152 | if(cursor+1==length) state<=REPLY; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:157:43: Operator LT expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 157 | if(reply_index>=2 && reply_index<7+reply_length) crc<=crc_next(crc,tx_data); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:158:25: Operator EQ expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 158 | if(reply_index==8+reply_length) state<=DRAIN; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:87:37: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'timeout_count' generates 22 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 87 | if((receiving && timeout_count==RX_TIMEOUT-1) || (receiving && rx_error)) begin + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:52:20: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'addr' generates 28 bits. + : ... note: In instance 'tb_board_cpu.memory' + 52 | offset=(addr & ~(LANES-1))-BASE; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:78:28: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'write_addr' generates 28 bits. + : ... note: In instance 'tb_board_cpu.memory' + 78 | offset=(write_addr & ~(LANES-1))-BASE; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:86:26: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'h600d600d' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 86 | if (w_bits_data==64'h600d600d) begin + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:91:66: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 91 | $fatal(1,"CPU smoke failed at stage %0d",w_bits_data & 64'hffff); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:90:28: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff0000' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:90:43: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'hbad00000' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_platform.sv:406:33: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's REDOR generates 1 bits. + : ... note: In instance 'tb_board_cpu.platform' + 406 | assign peripherals_b_bits_resp=|scu_bresp; + | ^ +make: Entering directory '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/obj' +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_timing.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_timing.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_threads.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_threads.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb_board_cpu__pch.h -o Vtb_board_cpu__pch.h.fast.gch +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb_board_cpu__pch.h -o Vtb_board_cpu__pch.h.slow.gch +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu__ConstPool__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__1__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__2__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__3__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu__Syms__Slow.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__0.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__1.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__2.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__3.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__4.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__5.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__6.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__7.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__8.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__9.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu__main.cpp +g++ verilated.o verilated_timing.o verilated_threads.o Vtb_board_cpu__ALL.a -pthread -lpthread -latomic -o Vtb_board_cpu +rm Vtb_board_cpu__ALL.verilator_deplist.tmp +make: Leaving directory '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/obj' +- V e r i l a t i o n R e p o r t: Verilator 5.050 2026-07-01 rev v5.050 +- Verilator: Built from 46.457 MB sources in 354 modules, into 26.450 MB in 19 C++ files needing 0.019 MB +- Verilator: Walltime 12.918 s (elab=0.578, cvt=3.278, bld=8.383); cpu 4.816 s on 8 threads; allocated 565.293 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/gemmini/simulation.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/gemmini/simulation.log new file mode 100644 index 0000000..63777f4 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/gemmini/simulation.log @@ -0,0 +1,5 @@ +PASS CPU Sv39/FPU/AMO/cache/interrupt through board AXI/SCU cycles=251063 +- /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:56: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 3ms; walltime 2.245 s; speed 1.118 ms/s +- Verilator: cpu 2.243 s on 1 threads; allocated 8 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/globalrob/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/globalrob/RESULT.json new file mode 100644 index 0000000..b5daff2 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/globalrob/RESULT.json @@ -0,0 +1,15 @@ +{ + "result": "PASS", + "cycle_equivalence": true, + "coverage": [ + "accepted operand integrity", + "ROB full", + "pointer wrap", + "issue backpressure", + "SubROB ownership stall", + "mid-flight resets", + "concurrent allocation/issue/completion", + "complete drain" + ], + "rtl_sha256": "e44723e3396d7e6421b9fae96a5d7b0b12ad0b4d55cc15128f21d7e048296fd0" +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/globalrob/compile.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/globalrob/compile.log new file mode 100644 index 0000000..3e1cfff --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/globalrob/compile.log @@ -0,0 +1,93 @@ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/globalrob-check/GlobalRobCheck.sim.sv:22:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 22 | module BankAliasTable( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/tb_globalrob.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ + ... For warning description see https://verilator.org/warn/TIMESCALEMOD?v=5.050 + ... Use "/* verilator lint_off TIMESCALEMOD */" and lint_on around source to disable this message. +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/globalrob-check/GlobalRobCheck.sim.sv:1346:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 1346 | module BankScoreboard( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/tb_globalrob.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/globalrob-check/GlobalRobCheck.sim.sv:1722:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 1722 | module robOperands_16x128( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/tb_globalrob.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/globalrob-check/GlobalRobCheck.sim.sv:1747:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 1747 | module GlobalROB( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/tb_globalrob.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/globalrob-check/GlobalRobCheck.sim.sv:6809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6809 | module GlobalROB_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/tb_globalrob.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/globalrob-check/GlobalRobCheck.sim.sv:11849:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +11849 | module ram_2x303( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/tb_globalrob.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/globalrob-check/GlobalRobCheck.sim.sv:11868:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +11868 | module Queue2_PostGDCmd( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/tb_globalrob.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/globalrob-check/GlobalRobCheck.sim.sv:11988:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +11988 | module ram_16x4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/tb_globalrob.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/globalrob-check/GlobalRobCheck.sim.sv:12007:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12007 | module Queue16_UInt4( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/tb_globalrob.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/globalrob-check/GlobalRobCheck.sim.sv:12055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12055 | module GlobalRobCheck( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/tb_globalrob.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/globalrob-check/GlobalRobCheck.sim.sv:13609:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13609 | module ITraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/tb_globalrob.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +make: Entering directory '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/globalrob-check/obj' +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_timing.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_timing.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_threads.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_threads.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb__pch.h -o Vtb__pch.h.fast.gch +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb__pch.h -o Vtb__pch.h.slow.gch +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__0.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__1.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__2.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb_BankAliasTable__0.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb_BankAliasTable__1.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb__main.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__1__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb_BankAliasTable__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb_BankAliasTable__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb__Syms__Slow.cpp +g++ verilated.o verilated_timing.o verilated_threads.o Vtb__ALL.a -pthread -lpthread -latomic -o Vtb +rm Vtb__ALL.verilator_deplist.tmp +make: Leaving directory '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/globalrob-check/obj' +- V e r i l a t i o n R e p o r t: Verilator 5.050 2026-07-01 rev v5.050 +- Verilator: Built from 1.310 MB sources in 13 modules, into 4.921 MB in 13 C++ files needing 0.004 MB +- Verilator: Walltime 23.503 s (elab=0.058, cvt=0.446, bld=21.284); cpu 7.107 s on 4 threads; allocated 389.180 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/globalrob/elaboration.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/globalrob/elaboration.log new file mode 100644 index 0000000..9cf0f3f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/globalrob/elaboration.log @@ -0,0 +1,90 @@ +[info] welcome to sbt 1.12.11 (N/A Java 17.0.20) +[info] loading project definition from /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/project +[info] loading settings for project root from build.sbt... +[info] set current project to toy-arty-a7-linux (in build file:/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/) +[info] compiling 213 Scala sources to /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/target/scala-2.13/classes ... +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/upstream/arch/src/main/scala/framework/gpdomain/sequencer/decoder/T1DecodePattern.scala:38:43: Auto-application to `()` is deprecated. Supply the empty argument list `()` explicitly to invoke method apply, +[warn] or remove the empty argument list from its definition (Java-defined methods are exempt). +[warn] In Scala 3, an unapplied method like this will be eta-expanded into a function. [quickfixable] +[warn] val attributes = IO(Output(Property[Seq[AnyClassType]])) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/upstream/arch/src/main/scala/framework/gpdomain/sequencer/decoder/T1DecodePattern.scala:40:42: Auto-application to `()` is deprecated. Supply the empty argument list `()` explicitly to invoke method apply, +[warn] or remove the empty argument list from its definition (Java-defined methods are exempt). +[warn] In Scala 3, an unapplied method like this will be eta-expanded into a function. [quickfixable] +[warn] val attributesIn = IO(Input(Property[Seq[AnyClassType]])) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/upstream/arch/src/main/scala/framework/gpdomain/sequencer/decoder/TableGenerator.scala:22:16: implicit conversion method bool2str should be enabled +[warn] by making the implicit value scala.language.implicitConversions visible. +[warn] This can be achieved by adding the import clause 'import scala.language.implicitConversions' +[warn] or by setting the compiler option -language:implicitConversions. +[warn] See the Scaladoc for value scala.language.implicitConversions for a discussion +[warn] why the feature should be explicitly enabled. +[warn] implicit def bool2str(b: Boolean): String = if (b) "b1" else "b0" +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/src/main/scala/ToyLinuxConfig.scala:72:24: method apply in class View is deprecated (since CDE 0.1): up(XYZ, site) is no longer necessary; remove the superfluous site argument +[warn] case SystemBusKey => up(SystemBusKey, site).copy(beatBytes = 16, dtsFrequency = Some(BigInt(50000000))) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/src/main/scala/ToyLinuxConfig.scala:73:24: method apply in class View is deprecated (since CDE 0.1): up(XYZ, site) is no longer necessary; remove the superfluous site argument +[warn] case MemoryBusKey => up(MemoryBusKey, site).copy(beatBytes = 16, dtsFrequency = Some(BigInt(50000000))) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/src/main/scala/ToyLinuxConfig.scala:74:27: method apply in class View is deprecated (since CDE 0.1): up(XYZ, site) is no longer necessary; remove the superfluous site argument +[warn] case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = Some(BigInt(50000000))) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/src/main/scala/ToyLinuxConfig.scala:75:25: method apply in class View is deprecated (since CDE 0.1): up(XYZ, site) is no longer necessary; remove the superfluous site argument +[warn] case ControlBusKey => up(ControlBusKey, site).copy(dtsFrequency = Some(BigInt(50000000))) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/src/main/scala/ToyLinuxConfig.scala:76:23: method apply in class View is deprecated (since CDE 0.1): up(XYZ, site) is no longer necessary; remove the superfluous site argument +[warn] case FrontBusKey => up(FrontBusKey, site).copy(dtsFrequency = Some(BigInt(50000000))) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/src/main/scala/ToyLinuxConfig.scala:78:37: method apply in class View is deprecated (since CDE 0.1): up(XYZ, site) is no longer necessary; remove the superfluous site argument +[warn] case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site).map { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/src/main/scala/ToyLinuxConfig.scala:116:5: method apply in class View is deprecated (since CDE 0.1): up(XYZ, site) is no longer necessary; remove the superfluous site argument +[warn] up(TilesLocated(InSubsystem), site).map { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/src/main/scala/ToyLinuxConfig.scala:135:17: method apply in class View is deprecated (since CDE 0.1): up(XYZ, site) is no longer necessary; remove the superfluous site argument +[warn] val cache = up(InclusiveCacheKey, site) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/src/main/scala/ToyLinuxConfig.scala:138:37: method apply in class View is deprecated (since CDE 0.1): up(XYZ, site) is no longer necessary; remove the superfluous site argument +[warn] case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site).map { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/src/main/scala/ToyLinuxConfig.scala:171:37: method apply in class View is deprecated (since CDE 0.1): up(XYZ, site) is no longer necessary; remove the superfluous site argument +[warn] case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site).map { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/upstream/arch/src/main/scala/framework/builtin/pipeline/Pipeline.scala:30:49: method zipped in class Ops is deprecated (since 2.13.0): Use xs.lazyZip(ys).lazyZip(zs) +[warn] (stalling.init, stalling.tail, valids.init).zipped.foreach { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/upstream/arch/src/main/scala/framework/builtin/pipeline/Pipeline.scala:41:34: method zipped in class Ops is deprecated (since 2.13.0): Use xs.lazyZip(ys) +[warn] (valids.init, stalling.tail).zipped.foreach { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/upstream/arch/src/main/scala/framework/builtin/pipeline/Pipeline.scala:51:32: method zipped in class Ops is deprecated (since 2.13.0): Use xs.lazyZip(ys) +[warn] (valids.tail, valids.init).zipped.foreach { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/upstream/arch/src/main/scala/framework/gpdomain/sequencer/decoder/TableGenerator.scala:13:35: type Traversable in package scala is deprecated (since 2.13.0): Use Iterable instead of Traversable +[warn] implicit class CrossAble[X](xs: Traversable[X]) { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/upstream/arch/src/main/scala/framework/gpdomain/sequencer/decoder/TableGenerator.scala:15:22: type Traversable in package scala is deprecated (since 2.13.0): Use Iterable instead of Traversable +[warn] def cross[Y](ys: Traversable[Y]): Traversable[(X, Y)] = for { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/upstream/arch/src/main/scala/framework/gpdomain/sequencer/decoder/TableGenerator.scala:15:39: type Traversable in package scala is deprecated (since 2.13.0): Use Iterable instead of Traversable +[warn] def cross[Y](ys: Traversable[Y]): Traversable[(X, Y)] = for { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/upstream/arch/src/main/scala/framework/system/tile/BBTile.scala:175:85: method apply in object TLClientParameters is deprecated: Use TLMasterParameters.v1 instead of TLClientParameters +[warn] if (bbPerCore(i).isDefined) Some(TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters( +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/upstream/arch/src/main/scala/framework/system/tile/BBTile.scala:183:85: method apply in object TLClientParameters is deprecated: Use TLMasterParameters.v1 instead of TLClientParameters +[warn] if (bbPerCore(i).isDefined) Some(TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters( +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/upstream/arch/src/main/scala/framework/system/tile/BBTile.scala:305:3: method DisableMonitors in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] DisableMonitors(implicit p => tlSlaveXbar.node :*= slaveNode) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/upstream/arch/src/main/scala/framework/system/tile/Configs.scala:59:40: method apply in class View is deprecated (since CDE 0.1): up(XYZ, site) is no longer necessary; remove the superfluous site argument +[warn] val prev = up(TilesLocated(`location`), site) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/upstream/arch/src/main/scala/framework/system/tile/Configs.scala:110:40: method apply in class View is deprecated (since CDE 0.1): up(XYZ, site) is no longer necessary; remove the superfluous site argument +[warn] val prev = up(TilesLocated(`location`), site) +[warn] ^ +[warn] 24 warnings found +[info] done compiling +[info] running fpga.arty.linux.EmitGlobalRobCheck +[success] Total time: 36 s, completed Oct 12, 2026, 7:47:43 PM diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/globalrob/simulation.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/globalrob/simulation.log new file mode 100644 index 0000000..c00fe2b --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/globalrob/simulation.log @@ -0,0 +1,5 @@ +PASS GLOBALROB RAM/register cycle comparison, payloads, wrap, stalls, resets cycles=8029 +- /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/tb_globalrob.sv:25: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 80us; walltime 0.027 s; speed 2.990 ms/s +- Verilator: cpu 0.027 s on 1 threads; allocated 7 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/linux-final/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/linux-final/RESULT.json new file mode 100644 index 0000000..962fe2b --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/linux-final/RESULT.json @@ -0,0 +1,17 @@ +{ + "result": "PASS_RTL_LINUX_USERSPACE", + "payload_sha256": "eb2ee34cc1a744498ac63b4e3fae425d4bb06be422ae6d41bd1ead696201134f", + "checks": [ + "OpenSBI", + "Linux version", + "PASS VM_COPY_ON_WRITE", + "PASS VM_PAGE_PROTECTION", + "PASS FP64_PROCESS_CONTEXT", + "PASS LINUX_TIMER", + "PASS LINUX_SYSTEM_CHECK", + "PASS BOARD_LINUX_USERSPACE" + ], + "physical_mig_simulated": false, + "physical_board_tested": false, + "uart_rx_command_tested": true +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/linux-final/compile.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/linux-final/compile.log new file mode 100644 index 0000000..4e5a7b6 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/linux-final/compile.log @@ -0,0 +1,2197 @@ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:31:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 31 | module NonSyncResetSynchronizerPrimitiveShiftReg_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ + ... For warning description see https://verilator.org/warn/TIMESCALEMOD?v=5.050 + ... Use "/* verilator lint_off TIMESCALEMOD */" and lint_on around source to disable this message. +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:48:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 48 | module SynchronizerShiftReg_w1_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:61:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 61 | module IntSyncAsyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:74:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 74 | module AsyncResetRegVec_w1_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:103:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 103 | module IntSyncCrossingSource_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:118:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 118 | module FixedClockBroadcast_3( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:139:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 139 | module TLMonitor( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:987:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 987 | module TLMonitor_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:2434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 2434 | module TLXbar_sbus_i2_o3_a32d128s3k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:3195:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3195 | module TLMonitor_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4151 | module Repeater_TLBundleA_a28d128s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4218 | module TLWidthWidget16( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4386 | module TLInterconnectCoupler_sbus_to_bus_named_cbus( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4478:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4478 | module ram_2x58( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4497:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4497 | module Queue2_AXI4BundleAW( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4581:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4581 | module ram_2x73( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4600:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4600 | module Queue2_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4657:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4657 | module ram_2x4( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4676:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4676 | module Queue2_AXI4BundleB( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4729:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4729 | module Queue2_AXI4BundleAR( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4813:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4813 | module ram_2x69( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4832:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4832 | module Queue2_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4891:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4891 | module AXI4Buffer( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5067:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5067 | module ram_2x8( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5086:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5086 | module Queue2_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5143:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5143 | module Queue1_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5178 | module AXI4UserYanker( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5540:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5540 | module ram_8x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5559:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5559 | module Queue8_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5631 | module AXI4Deinterleaver( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:6073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6073 | module AXI4IdIndexer( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:6219:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6219 | module TLMonitor_3( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7048:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7048 | module Queue1_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7082:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7082 | module Queue1_AXI4BundleARW( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7148:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7148 | module TLToAXI4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7529:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7529 | module TLMonitor_4( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8396:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8396 | module Repeater_TLBundleA_a31d128s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8463 | module TLWidthWidget16_2( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8623:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8623 | module TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:9400:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 9400 | module SystemBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10050 | module FixedClockBroadcast_4( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10073 | module TLMonitor_5( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10975:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10975 | module TLXbar_cbus_out_i1_o4_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:11288:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +11288 | module TLMonitor_6( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12202:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12202 | module ram_2x114( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12221 | module Queue2_TLBundleA_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12301 | module ram_2x79( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12320:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12320 | module Queue2_TLBundleD_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12399:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12399 | module TLBuffer_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12534:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12534 | module TLMonitor_7( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:13449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13449 | module TLAtomicAutomata_cbus( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:13973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13973 | module TLMonitor_8( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14799 | module Queue1_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14846:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14846 | module TLError( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14953 | module TLMonitor_9( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15857 | module ram_2x100( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15876:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15876 | module Queue2_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15955:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15955 | module Queue2_TLBundleD_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16028 | module TLBuffer_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16155 | module ErrorDeviceWrapper( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16258 | module TLMonitor_10( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17017:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17017 | module Repeater_TLBundleA_a26d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17081:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17081 | module TLFragmenter_CLINT( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17261:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17261 | module TLInterconnectCoupler_cbus_to_clint( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17336:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17336 | module TLMonitor_11( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18106:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18106 | module Repeater_TLBundleA_a28d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18170:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18170 | module TLFragmenter_PLIC( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18350 | module TLInterconnectCoupler_cbus_to_plic( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18425:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18425 | module TLMonitor_12( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19040 | module Repeater_TLBundleA_a17d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19104:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19104 | module TLFragmenter_bootrom( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19263:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19263 | module TLInterconnectCoupler_cbus_to_bootrom( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19330:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19330 | module PeripheryBus_cbus( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19882 | module TLMonitor_13( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20610:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20610 | module ProbePicker( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20688:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20688 | module ram_2x10( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20707:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20707 | module Queue2_BundleMap_6( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20764:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20764 | module AXI4UserYanker_1( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:21713:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21713 | module AXI4IdIndexer_1( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:21859:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21859 | module TLMonitor_14( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22587:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22587 | module Queue1_AXI4BundleW_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22621 | module Queue1_AXI4BundleARW_1( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22687:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22687 | module TLToAXI4_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:23555:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +23555 | module TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:24031:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24031 | module MemoryBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:24349:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24349 | module TLMonitor_15( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25732:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25732 | module BroadcastFilter( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25756:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25756 | module ram_4x144( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25775:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25775 | module Queue4_TLBroadcastData( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25828:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25828 | module TLBroadcastTracker( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25964:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25964 | module TLBroadcastTracker_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:26100:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26100 | module TLBroadcast( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:26686:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26686 | module TLMonitor_16( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:27414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27414 | module BankBinder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:27491:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27491 | module CoherenceManagerWrapper( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:27669:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27669 | module TLMonitor_17( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29229:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29229 | module TLMonitor_18( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29635:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29635 | module TLXbar_MasterXbar_BBTile_i2_o1_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29898 | module IntXbar_i4_o1( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29918:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29918 | module WritebackUnit( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30014:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30014 | module ProbeUnit( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30154:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30154 | module Arbiter1_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30168:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30168 | module Arbiter1_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30191 | module Arbiter1_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30214 | module Arbiter1_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30249:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30249 | module Arbiter1_Bool( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30258 | module ram_16x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30277:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30277 | module Queue16_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30360:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30360 | module Queue1_TLBundleE_a32d128s1k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30388:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30388 | module MSHR( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30835:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30835 | module Arbiter1_HellaCacheResp( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30879:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30879 | module IOMSHR( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:31790:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31790 | module sdq_17x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:31809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31809 | module MSHRFile( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:32350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32350 | module OptimizationBarrier_TLBEntryData( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:32406:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32406 | module PMPChecker_s3( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:32691:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32691 | module PMAChecker( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:32731:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32731 | module DTLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:35923:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35923 | module L1MetadataArray( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:35990:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35990 | module Arbiter5_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36023:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36023 | module Arbiter2_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36055 | module DataArray( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36151 | module Arbiter4_L1DataReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36180:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36180 | module Arbiter2_L1DataWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36206:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36206 | module AMOALU( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36248:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36248 | module MaxPeriodFibonacciLFSR( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36342:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36342 | module Arbiter2_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36377:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36377 | module NonBlockingDCache( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:37660:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37660 | module ICache( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:37914:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37914 | module ShiftQueue( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:38054:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38054 | module PMPChecker_s2( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:38215:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38215 | module ITLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:41129:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41129 | module Frontend( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:41494:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41494 | module TLMonitor_19( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:42301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +42301 | module TLMonitor_20( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43108:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43108 | module TLXbar_i2_o1_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43343 | module TLMonitor_21( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43851:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43851 | module ram_2x116( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43870:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43870 | module Queue2_TLBundleA_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43947:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43947 | module ram_2x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43966:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43966 | module Queue2_TLBundleD_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44045:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44045 | module TLBuffer_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44158:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44158 | module TLMonitor_22( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44783 | module TLBuffer_a32d64s1k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44892:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44892 | module TLMonitor_23( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:45699:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45699 | module Repeater_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:45766:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45766 | module TLWidthWidget8_4( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:46074:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46074 | module TLMonitor_24( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:46882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46882 | module ram_2x117( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:46901:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46901 | module Queue2_TLBundleA_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:46981:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46981 | module ram_2x78( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47000:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47000 | module Queue2_TLBundleD_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47079:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47079 | module TLBuffer_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47214 | module HellaCacheArbiter( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47381 | module Arbiter3_Valid_PTWReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47419:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47419 | module OptimizationBarrier_UInt( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47427 | module OptimizationBarrier_PTE( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47459 | module PTW( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:48434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +48434 | module FPUDecoder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:49794:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49794 | module CompareRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:49824:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49824 | module RecFNToIN_e11_s53_i64( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:49873:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49873 | module RecFNToIN_e11_s53_i32( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:49912:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49912 | module FPToInt( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50375:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50375 | module RoundAnyRawFNToRecFN_ie7_is64_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50410:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50410 | module PipelinedINToRecFN( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50513:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50513 | module RoundAnyRawFNToRecFN_ie7_is64_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50539 | module PipelinedINToRecFN_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50614 | module RoundAnyRawFNToRecFN_ie7_is64_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50642:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50642 | module PipelinedINToRecFN_2( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50717 | module IntToFP( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51072:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51072 | module RoundAnyRawFNToRecFN_ie11_is53_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51199:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51199 | module RecFNToRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51221 | module RoundAnyRawFNToRecFN_ie11_is53_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51321:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51321 | module RecFNToRecFN_1( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51343 | module FPToFP( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51469:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51469 | module MulAddRecFNToRaw_preMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51569 | module MulAddRecFNToRaw_postMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51822:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51822 | module RoundAnyRawFNToRecFN_ie11_is55_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51953 | module RoundAnyRawFNToRecFN_ie11_is55_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52060:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52060 | module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52194:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52194 | module SharedMulAddRecFNPipe( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52551:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52551 | module FPUSharedFMAPipe( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52682:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52682 | module DivSqrtRawFN_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52852:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52852 | module DivSqrtRecFMToRaw_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52907:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52907 | module RoundAnyRawFNToRecFN_ie5_is13_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53039:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53039 | module RoundRawFNToRecFN_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53068:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53068 | module DivSqrtRecFM_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53128:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53128 | module DivSqrtRawFN_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53297:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53297 | module DivSqrtRecFMToRaw_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53352:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53352 | module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53456:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53456 | module RoundRawFNToRecFN_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53485:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53485 | module DivSqrtRecFM_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53545:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53545 | module DivSqrtRawFN_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53715:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53715 | module DivSqrtRecFMToRaw_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53770:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53770 | module RoundRawFNToRecFN_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53799 | module DivSqrtRecFM_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53860:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53860 | module regfile_32x65( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53905:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53905 | module FPU( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:54820:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +54820 | module RVCExpander( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:55183:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55183 | module IBuf( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:55307:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55307 | module CSRFile( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:57223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57223 | module RocketALU( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:57809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57809 | module MulDiv( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:58107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58107 | module Arbiter3_LLWB( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:58125:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58125 | module rf_31x64( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:58149:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58149 | module RocketBB( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62838:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62838 | module GlobalDecoder( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62928:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62928 | module BankAliasTable( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:64252:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64252 | module BankScoreboard( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:64627:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64627 | module GlobalROB( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68674:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68674 | module Arbiter3_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68717 | module ram_16x4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68736:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68736 | module Queue16_UInt4( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68782:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68782 | module SubROB( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:69357:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69357 | module Arbiter1_SubRobRow( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:69722:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69722 | module GlobalScheduler( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:70973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +70973 | module BootRom( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:71013:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71013 | module Frontend_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:71637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71637 | module PE( + | ^~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:71656:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71656 | module AlwaysOutTransposer( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:72411:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72411 | module MacUnit( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:72426:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72426 | module PE_64( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:72524:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72524 | module Tile( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:72571:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72571 | module Mesh( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76050 | module TagQueue( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76191 | module ram_6x7( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76210:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76210 | module Queue6_TagWithIdAndTotalRows( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76271:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76271 | module MeshWithDelays( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77318:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77318 | module ram_data_8x64( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77337 | module Queue8_SramReadResp( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77385:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77385 | module GemminiExCtrl( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79354:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79354 | module LoopMatmulUnroller( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79637 | module LoopConvAddrGen( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79690:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79690 | module LoopConvUnroller( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:80113:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80113 | module LoopCmdEncoder( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:80402:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80402 | module Arbiter2_LoopCmd( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:80598:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80598 | module GemminiBall( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:81783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81783 | module RRArbiter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:81857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81857 | module CmdRouter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:81985:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81985 | module BallCyclePMC( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:82095:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82095 | module BBus( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:82898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82898 | module BallDomainDecoder( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83028 | module ram_4x281( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83047:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83047 | module Queue4_BallReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83178 | module Arbiter1_BallRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83198:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83198 | module BallReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83328:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83328 | module BallDomain( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84141:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84141 | module MemDomainDecoder( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84300:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84300 | module ram_4x158( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84319:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84319 | module Queue4_MemReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84421:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84421 | module Arbiter3_MemRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84463 | module MemReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84631 | module MemLoader( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84869:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84869 | module MemStorer( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85122:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85122 | module MemCyclePMC( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85241:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85241 | module TLB( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85621 | module RRArbiter_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85649:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85649 | module BBTLBCluster( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85777 | module StreamReader( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86142:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86142 | module StreamWriter( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86223 | module ZeroLineGenerator( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86264:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86264 | module MemConfiger( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86433:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86433 | module RRArbiter_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86465:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86465 | module MemGroupQueryArbiter( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86543:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86543 | module MemFrontend( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:87160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87160 | module MemMidend( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:87621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87621 | module SramBank( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:87672:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87672 | module AccPipe( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:87781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87781 | module PrivateMemBackend( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:90777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +90777 | module MemBackend( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:91055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91055 | module MemDomain( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:91973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91973 | module Queue1_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:92008:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92008 | module GpDomain( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:92040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92040 | module ram_8x21( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:92059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92059 | module Queue8_BuckyballAccelerator_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:92123:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92123 | module BuckyballAccelerator( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93569 | module Queue3_UInt2( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93614 | module SimpleHellaCacheIFReplayQueue( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93667:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93667 | module Arbiter2_HellaCacheReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93678:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93678 | module SimpleHellaCacheIF( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93768:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93768 | module BarrierUnit( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93785:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93785 | module BBTile( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:95579:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +95579 | module TLMonitor_25( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:96427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +96427 | module TLMonitor_26( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98184:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98184 | module ram_2x189( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98203:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98203 | module Queue2_TLBundleA_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98283:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98283 | module ram_2x142( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98302:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98302 | module Queue2_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98381 | module Queue2_TLBundleA_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98459 | module Queue2_TLBundleD_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98539 | module ram_2x60( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98558:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98558 | module Queue2_TLBundleB_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98622:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98622 | module ram_2x173( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98641:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98641 | module Queue2_TLBundleC_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98716:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98716 | module ram_sink_2x1( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98735:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98735 | module Queue2_TLBundleE_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98781 | module TLBuffer_a32d128s2k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99162:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99162 | module IntSyncSyncCrossingSink_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99173:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99173 | module IntSyncSyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99181:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99181 | module TilePRCIDomain( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99589:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99589 | module BundleBridgeNexus_UInt1_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99597:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99597 | module TLMonitor_27( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100216:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100216 | module CLINT( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100337 | module AsyncResetRegVec_w2_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100366:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100366 | module IntSyncCrossingSource_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100386 | module CLINTClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100449 | module TLMonitor_28( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101080:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101080 | module LevelGateway( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101099:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101099 | module PLICFanIn( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101111:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101111 | module Queue1_RegMapperInput_i23_m8( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101160 | module TLPLIC( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101389:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101389 | module PLICClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101452:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101452 | module TLMonitor_29( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101973 | module TLROM( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:102530:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102530 | module bootromClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:102569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102569 | module ToyLinuxSystem( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:103817:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103817 | module ToyLinuxChip( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:103984:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103984 | module tag_array( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104007:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104007 | module array_0_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104034:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104034 | module array_0_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104059 | module array_2_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104084:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104084 | module array_2_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104109:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104109 | module bbtile_icache_tag_array( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104132:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104132 | module bbtile_icache_data_arrays_0( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104155 | module bbtile_icache_data_arrays_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104176:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104176 | module bbtile_icache_data_arrays_2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104197:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104197 | module bbtile_icache_data_arrays_3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104218 | module robOperands( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104243:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104243 | module sram( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104268:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104268 | module mem( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104301 | module plusarg_reader #( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104326:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104326 | module ITraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104404:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104404 | module FpgaDspMac(input [7:0] a, b, input [19:0] c, output [19:0] y); + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104414 | module PMCTraceDPI( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104464:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104464 | module MemPMCTraceDPI( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104514:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104514 | module MTraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:1:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 1 | module tag_array_ext( input [4:0] RW0_addr, + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 19 | module array_0_0_ext( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:37:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 37 | module bbtile_icache_tag_array_ext( input [5:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:55:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 55 | module bbtile_icache_data_arrays_0_ext( input [7:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:73:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 73 | module robOperands_ext( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:90:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 90 | module sram_ext( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 107 | module mem_ext( input [9:0] RW0_addr, + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:3:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3 | module axi_smoke_memory #( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_tx.sv:27:15: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_linux.platform.transmitter' + 27 | count <= DIVISOR - 1; + | ^~ + ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=5.050 + ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_tx.sv:32:13: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_linux.platform.transmitter' + 32 | count <= DIVISOR - 1; + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_rx.sv:23:55: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_linux.platform.receiver' + 23 | IDLE: if (!rx_sync) begin state <= START; count <= DIVISOR/2 - 1; end + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_rx.sv:26:57: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_linux.platform.receiver' + 26 | else begin state <= DATA; bit_index <= 0; count <= DIVISOR - 1; end + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_rx.sv:29:46: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_linux.platform.receiver' + 29 | shift[bit_index] <= rx_sync; count <= DIVISOR - 1; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:32:43: Operator ADD expects 33 bits on the RHS, but RHS's VARREF 'length' generates 16 bits. + : ... note: In instance 'tb_board_linux.platform.loader' + 32 | wire [32:0] end_address = {1'b0,address}+length; + | ^ + ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=5.050 + ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:35:38: Operator ADD expects 32 bits on the RHS, but RHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_linux.platform.loader' + 35 | wire [31:0] byte_address = address + cursor; + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:67:32: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's SHIFTR generates 32 bits. + : ... note: In instance 'tb_board_linux.platform.loader' + 67 | 11,12,13,14:tx_data=RAM_BYTES >> ((reply_index-11)*8); + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:68:32: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's SHIFTR generates 32 bits. + : ... note: In instance 'tb_board_linux.platform.loader' + 68 | 15,16,17,18:tx_data=CLOCK_HZ >> ((reply_index-15)*8); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:73:28: Operator EQ expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_linux.platform.loader' + 73 | else if(reply_index==7+reply_length) tx_data=crc[7:0]; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:64:23: Operator LT expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_linux.platform.loader' + 64 | if(reply_index<7+reply_length) begin + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:119:20: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_linux.platform.loader' + 119 | if(cursor+1==length) state<=CRC0; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:144:25: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_linux.platform.loader' + 144 | else if(cursor+1==length) begin image_loaded<=1;state<=REPLY;end + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:152:20: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_linux.platform.loader' + 152 | if(cursor+1==length) state<=REPLY; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:157:43: Operator LT expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_linux.platform.loader' + 157 | if(reply_index>=2 && reply_index<7+reply_length) crc<=crc_next(crc,tx_data); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:158:25: Operator EQ expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_linux.platform.loader' + 158 | if(reply_index==8+reply_length) state<=DRAIN; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:87:37: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'timeout_count' generates 22 bits. + : ... note: In instance 'tb_board_linux.platform.loader' + 87 | if((receiving && timeout_count==RX_TIMEOUT-1) || (receiving && rx_error)) begin + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:52:20: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'addr' generates 28 bits. + : ... note: In instance 'tb_board_linux.memory' + 52 | offset=(addr & ~(LANES-1))-BASE; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:78:28: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'write_addr' generates 28 bits. + : ... note: In instance 'tb_board_linux.memory' + 78 | offset=(write_addr & ~(LANES-1))-BASE; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:86:26: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'h600d600d' generates 64 bits. + : ... note: In instance 'tb_board_linux.memory' + 86 | if (w_bits_data==64'h600d600d) begin + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:91:66: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff' generates 64 bits. + : ... note: In instance 'tb_board_linux.memory' + 91 | $fatal(1,"CPU smoke failed at stage %0d",w_bits_data & 64'hffff); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:90:28: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff0000' generates 64 bits. + : ... note: In instance 'tb_board_linux.memory' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:90:43: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'hbad00000' generates 64 bits. + : ... note: In instance 'tb_board_linux.memory' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_platform.sv:406:33: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's REDOR generates 1 bits. + : ... note: In instance 'tb_board_linux.platform' + 406 | assign peripherals_b_bits_resp=|scu_bresp; + | ^ +make: Entering directory '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/obj' +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_timing.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_timing.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_threads.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_threads.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb_board_linux__pch.h -o Vtb_board_linux__pch.h.fast.gch +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb_board_linux__pch.h -o Vtb_board_linux__pch.h.slow.gch +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.fast -c Vtb_board_linux.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.fast -c Vtb_board_linux___024root__0.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.fast -c Vtb_board_linux___024root__1.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.fast -c Vtb_board_linux___024root__2.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.fast -c Vtb_board_linux___024root__3.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.fast -c Vtb_board_linux___024root__4.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.fast -c Vtb_board_linux___024root__5.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.fast -c Vtb_board_linux___024root__6.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.fast -c Vtb_board_linux___024root__7.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.fast -c Vtb_board_linux___024root__8.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.fast -c Vtb_board_linux___024root__9.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.fast -c Vtb_board_linux__main.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.slow -c Vtb_board_linux__ConstPool__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.slow -c Vtb_board_linux___024root__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.slow -c Vtb_board_linux___024root__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.slow -c Vtb_board_linux___024root__1__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.slow -c Vtb_board_linux___024root__2__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.slow -c Vtb_board_linux___024root__3__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.slow -c Vtb_board_linux__Syms__Slow.cpp +g++ verilated.o verilated_timing.o verilated_threads.o Vtb_board_linux__ALL.a -pthread -lpthread -latomic -o Vtb_board_linux +rm Vtb_board_linux__ALL.verilator_deplist.tmp +make: Leaving directory '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/obj' +- V e r i l a t i o n R e p o r t: Verilator 5.050 2026-07-01 rev v5.050 +- Verilator: Built from 46.473 MB sources in 354 modules, into 26.897 MB in 19 C++ files needing 0.021 MB +- Verilator: Walltime 17.141 s (elab=0.576, cvt=3.206, bld=12.637); cpu 4.819 s on 8 threads; allocated 438.188 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/linux-final/simulation.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/linux-final/simulation.log new file mode 100644 index 0000000..fdcc27e --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/linux-final/simulation.log @@ -0,0 +1,172 @@ + +OpenSBI v1.9 + ____ _____ ____ _____ + / __ \ / ____| _ \_ _| + | | | |_ __ ___ _ __ | (___ | |_) || | + | | | | '_ \ / _ \ '_ \ \___ \| _ < | | + | |__| | |_) | __/ | | |____) | |_) || |_ + \____/| .__/ \___|_| |_|_____/|____/_____| + | | + |_| + +Platform Name : Buckyball +Platform Features : medeleg +Platform HART Count : 1 +Platform HART Protection : pmp +Platform IPI Device : aclint-mswi +Platform Timer Device : aclint-mtimer @ 500000Hz +Platform Console Device : buckyball-scu +Platform HSM Device : --- +Platform PMU Device : --- +Platform Reboot Device : buckyball-scu-reset +Platform Shutdown Device : buckyball-scu-reset +Platform Suspend Device : --- +Platform CPPC Device : --- +Firmware Base : 0x80000000 +Firmware Size : 312 KB +Firmware RW Offset : 0x40000 +Firmware RW Size : 56 KB +Firmware Heap Offset : 0x45000 +Firmware Heap Size : 36 KB (total), 0 KB (reserved), 12 KB (used), 23 KB (free) +Firmware Scratch Size : 4096 B (total), 496 B (used), 3600 B (free) +Runtime SBI Version : 3.0 +Standard SBI Extensions : time,rfnc,ipi,base,hsm,srst,pmu,dbcn,fwft,legacy,sse +Experimental SBI Extensions : none + +Domain0 Name : root +Domain0 Boot HART : 0 +Domain0 HARTs : 0x0* +Domain0 Region00 : 0x0000000080040000-0x000000008004ffff M: (F,R,W) S/U: () +Domain0 Region01 : 0x0000000080000000-0x000000008003ffff M: (F,R,X) S/U: () +Domain0 Region02 : 0x0000000002008000-0x000000000200bfff M: (I,R,W) S/U: () +Domain0 Region03 : 0x0000000002000000-0x0000000002007fff M: (I,R,W) S/U: () +Domain0 Region04 : 0x000000000c000000-0x000000000fffffff M: (I,R,W) S/U: (R,W) +Domain0 Region05 : 0x0000000000000000-0xffffffffffffffff M: () S/U: (R,W,X) +Domain0 Next Address : 0x0000000080200000 +Domain0 Next Arg1 : 0x0000000088000000 +Domain0 Next Mode : S-mode +Domain0 SysReset : yes +Domain0 SysSuspend : yes + +Boot HART ID : 0 +Boot HART Domain : root +Boot HART Priv Version : v1.12 +Boot HART Base ISA : rv64imafdcx +Boot HART ISA Extensions : sdtrig +Boot HART PMP Count : 8 +Boot HART PMP Granularity : 2 bits +Boot HART PMP Address Bits : 30 +Boot HART MHPM Info : 0 (0x00000000) +Boot HART Debug Triggers : 0 triggers +Boot HART MIDELEG : 0x0000000000000222 +Boot HART MEDELEG : 0x000000000000b109 +Linux version 6.6.0 (yys@amax) (riscv64-unknown-linux-gnu-gcc (GCC) 15.3.0, GNU ld (GNU Binutils) 2.46) #1 Sat Oct 10 16:24:07 CST 2026 +Machine model: ucb-bar,buckyball +Forcing kernel command line to: console=hvc0 earlycon=sbi loglevel=8 ignore_loglevel panic=1 mem=256M +SBI specification v3.0 detected +SBI implementation ID=0x1 Version=0x10009 +SBI TIME extension detected +SBI IPI extension detected +SBI RFENCE extension detected +SBI SRST extension detected +earlycon: sbi0 at I/O port 0x0 (options '') +printk: bootconsole [sbi0] enabled +printk: debug: ignoring loglevel setting. +Memory limited to 256MB +efi: UEFI not found. +OF: reserved mem: 0x0000000080000000..0x000000008003ffff (256 KiB) nomap non-reusable mmode_resv1@80000000 +OF: reserved mem: 0x0000000080040000..0x000000008004ffff (64 KiB) nomap non-reusable mmode_resv0@80040000 +Zone ranges: + DMA32 [mem 0x0000000080000000-0x000000008fffffff] + Normal empty +Movable zone start for each node +Early memory node ranges + node 0: [mem 0x0000000080000000-0x000000008004ffff] + node 0: [mem 0x0000000080050000-0x000000008fffffff] +Initmem setup node 0 [mem 0x0000000080000000-0x000000008fffffff] +Falling back to deprecated "riscv,isa" +riscv: base ISA extensions abcdfim +riscv: ELF capabilities acdfim +pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768 +pcpu-alloc: [0] 0 +Kernel command line: console=hvc0 earlycon=sbi loglevel=8 ignore_loglevel panic=1 mem=256M +Dentry cache hash table entries: 32768 (order: 6, 262144 bytes, linear) +Inode-cache hash table entries: 16384 (order: 5, 131072 bytes, linear) +Built 1 zonelists, mobility grouping on. Total pages: 64640 +mem auto-init: stack:all(zero), heap alloc:off, heap free:off +Memory: 241400K/262144K available (2126K kernel code, 4423K rwdata, 2048K rodata, 4385K init, 299K bss, 20744K reserved, 0K cma-reserved) +SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 +NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 +riscv-intc: 64 local interrupts mapped +plic: interrupt-controller@c000000: mapped 1 interrupts with 1 handlers for 2 contexts. +clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1d854df40, max_idle_ns: 7052723233920 ns +sched_clock: 64 bits at 500kHz, resolution 2000ns, wraps every 4398046511000ns +Console: colour dummy device 80x25 +printk: console [hvc0] enabled +printk: console [hvc0] enabled +printk: bootconsole [sbi0] disabled +printk: bootconsole [sbi0] disabled +Calibrating delay loop (skipped), value calculated using timer frequency.. 1.00 BogoMIPS (lpj=2000) +pid_max: default: 32768 minimum: 301 +Mount-cache hash table entries: 512 (order: 0, 4096 bytes, linear) +Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes, linear) +riscv: ELF compat mode unsupported +ASID allocator disabled (0 bits) +EFI services will not be available. +devtmpfs: initialized +clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns +futex hash table entries: 256 (order: 0, 6144 bytes, linear) +DMA: preallocated 128 KiB GFP_KERNEL pool for atomic allocations +DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations +cpu0: Ratio of byte access time to unaligned word access is 0.01, unaligned accesses are slow +clocksource: Switched to clocksource riscv_clocksource +workingset: timestamp_bits=62 max_order=16 bucket_order=0 +io scheduler mq-deadline registered +io scheduler kyber registered +clk: Disabling unused clocks +Freeing unused kernel image (initmem) memory: 4384K +Run /init as init process + with arguments: + /init + with environment: + HOME=/ + TERM=linux + + __ __ __ ____ + / / / /___ __ _____ ____ _ / /_ ____ _/ / / + / /_/ / __ `/ | / / _ \ / __ `/ / __ \/ __ `/ / / + / __ / /_/ /| |/ / __/ / /_/ / / /_/ / /_/ / / / + /_/ /_/\__,_/ |___/\___/ \__,_/ /_.___/\__,_/_/_/ + +/bin/sh: can't access tty; job control turned off +~ # +SIM_SHELL_PROMPT cycles=241934865 +/root/linux_system_check-linux +SIM_COMMAND_SENT cycles=249692645 overflow=0 framing=0 pending_rx=1 + +BEGIN LINUX_SYSTEM_CHECK +PASS VM_COPY_ON_WRITE +linux_system_ch[25]: unhandled signal 11 code 0x2 at 0x0000003f82c1a000 in linux_system_check-linux[10000+7a000] +CPU: 0 PID: 25 Comm: linux_system_ch Not tainted 6.6.0 #1 +Hardware name: ucb-bar,buckyball (DT) +epc : 00000000000105c6 ra : 000000000001041e sp : 0000003fe9ca4b50 + gp : 0000000000090078 tp : 0000000000096760 t0 : 0000000000000000 + t1 : 0000000000000000 t2 : 0000000000000000 s0 : 0000003fe9ca4bd0 + s1 : 0000003f82c19000 a0 : 0000000000000000 a1 : 0000000000000000 + a2 : 0000000000000000 a3 : 0000000000000000 a4 : 0000000000000000 + a5 : 0000000000000000 a6 : 0000000000000000 a7 : 0000000000000000 + s2 : 0000000000000042 s3 : 0000000000001000 s4 : 0000003f82c1a000 + s5 : 0000003fe9ca4d88 s6 : 0000000000000002 s7 : 00000000000106ba + s8 : 00000000000101e0 s9 : 000000000000003a s10: 0000000000094e28 + s11: 0000000000000000 t3 : 0000000000000000 t4 : 0000000000000000 + t5 : 0000000000000000 t6 : 0000000000000000 +status: 800000020001e020 badaddr: 0000003f82c1a000 cause: 000000000000000d +PASS VM_PAGE_PROTECTION +PASS FP64_PROCESS_CONTEXT +PASS LINUX_TIMER elapsed_ns=101252000 +PASS LINUX_SYSTEM_CHECK +PASS BOARD_LINUX_USERSPACE cycles=273506752 characters=7992 +- /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:99: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 11s; walltime 2078.418 s; speed 5.264 ms/s +- Verilator: cpu 2077.865 s on 1 threads; allocated 264 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/loop/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/loop/RESULT.json new file mode 100644 index 0000000..c426992 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/loop/RESULT.json @@ -0,0 +1,9 @@ +{ + "result": "PASS", + "test": "loop", + "binary_sha256": "bbe9646dc565ac9ac1188c6b3d53d24b1b37985ee158ee2ac918df04c3267ce2", + "original_cpu_oracle": true, + "ddr_phy_simulated": false, + "physical_linux_boot_tested": false, + "cycles": 684219 +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/loop/compile.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/loop/compile.log new file mode 100644 index 0000000..ebbfa19 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/loop/compile.log @@ -0,0 +1,2197 @@ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:31:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 31 | module NonSyncResetSynchronizerPrimitiveShiftReg_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ + ... For warning description see https://verilator.org/warn/TIMESCALEMOD?v=5.050 + ... Use "/* verilator lint_off TIMESCALEMOD */" and lint_on around source to disable this message. +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:48:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 48 | module SynchronizerShiftReg_w1_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:61:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 61 | module IntSyncAsyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:74:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 74 | module AsyncResetRegVec_w1_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:103:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 103 | module IntSyncCrossingSource_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:118:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 118 | module FixedClockBroadcast_3( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:139:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 139 | module TLMonitor( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:987:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 987 | module TLMonitor_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:2434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 2434 | module TLXbar_sbus_i2_o3_a32d128s3k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:3195:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3195 | module TLMonitor_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4151 | module Repeater_TLBundleA_a28d128s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4218 | module TLWidthWidget16( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4386 | module TLInterconnectCoupler_sbus_to_bus_named_cbus( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4478:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4478 | module ram_2x58( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4497:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4497 | module Queue2_AXI4BundleAW( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4581:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4581 | module ram_2x73( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4600:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4600 | module Queue2_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4657:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4657 | module ram_2x4( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4676:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4676 | module Queue2_AXI4BundleB( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4729:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4729 | module Queue2_AXI4BundleAR( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4813:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4813 | module ram_2x69( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4832:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4832 | module Queue2_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4891:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4891 | module AXI4Buffer( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5067:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5067 | module ram_2x8( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5086:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5086 | module Queue2_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5143:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5143 | module Queue1_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5178 | module AXI4UserYanker( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5540:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5540 | module ram_8x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5559:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5559 | module Queue8_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5631 | module AXI4Deinterleaver( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:6073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6073 | module AXI4IdIndexer( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:6219:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6219 | module TLMonitor_3( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7048:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7048 | module Queue1_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7082:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7082 | module Queue1_AXI4BundleARW( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7148:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7148 | module TLToAXI4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7529:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7529 | module TLMonitor_4( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8396:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8396 | module Repeater_TLBundleA_a31d128s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8463 | module TLWidthWidget16_2( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8623:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8623 | module TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:9400:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 9400 | module SystemBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10050 | module FixedClockBroadcast_4( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10073 | module TLMonitor_5( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10975:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10975 | module TLXbar_cbus_out_i1_o4_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:11288:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +11288 | module TLMonitor_6( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12202:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12202 | module ram_2x114( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12221 | module Queue2_TLBundleA_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12301 | module ram_2x79( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12320:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12320 | module Queue2_TLBundleD_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12399:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12399 | module TLBuffer_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12534:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12534 | module TLMonitor_7( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:13449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13449 | module TLAtomicAutomata_cbus( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:13973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13973 | module TLMonitor_8( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14799 | module Queue1_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14846:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14846 | module TLError( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14953 | module TLMonitor_9( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15857 | module ram_2x100( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15876:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15876 | module Queue2_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15955:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15955 | module Queue2_TLBundleD_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16028 | module TLBuffer_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16155 | module ErrorDeviceWrapper( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16258 | module TLMonitor_10( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17017:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17017 | module Repeater_TLBundleA_a26d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17081:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17081 | module TLFragmenter_CLINT( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17261:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17261 | module TLInterconnectCoupler_cbus_to_clint( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17336:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17336 | module TLMonitor_11( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18106:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18106 | module Repeater_TLBundleA_a28d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18170:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18170 | module TLFragmenter_PLIC( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18350 | module TLInterconnectCoupler_cbus_to_plic( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18425:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18425 | module TLMonitor_12( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19040 | module Repeater_TLBundleA_a17d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19104:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19104 | module TLFragmenter_bootrom( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19263:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19263 | module TLInterconnectCoupler_cbus_to_bootrom( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19330:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19330 | module PeripheryBus_cbus( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19882 | module TLMonitor_13( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20610:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20610 | module ProbePicker( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20688:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20688 | module ram_2x10( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20707:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20707 | module Queue2_BundleMap_6( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20764:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20764 | module AXI4UserYanker_1( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:21713:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21713 | module AXI4IdIndexer_1( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:21859:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21859 | module TLMonitor_14( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22587:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22587 | module Queue1_AXI4BundleW_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22621 | module Queue1_AXI4BundleARW_1( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22687:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22687 | module TLToAXI4_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:23555:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +23555 | module TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:24031:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24031 | module MemoryBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:24349:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24349 | module TLMonitor_15( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25732:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25732 | module BroadcastFilter( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25756:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25756 | module ram_4x144( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25775:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25775 | module Queue4_TLBroadcastData( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25828:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25828 | module TLBroadcastTracker( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25964:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25964 | module TLBroadcastTracker_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:26100:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26100 | module TLBroadcast( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:26686:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26686 | module TLMonitor_16( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:27414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27414 | module BankBinder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:27491:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27491 | module CoherenceManagerWrapper( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:27669:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27669 | module TLMonitor_17( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29229:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29229 | module TLMonitor_18( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29635:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29635 | module TLXbar_MasterXbar_BBTile_i2_o1_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29898 | module IntXbar_i4_o1( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29918:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29918 | module WritebackUnit( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30014:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30014 | module ProbeUnit( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30154:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30154 | module Arbiter1_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30168:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30168 | module Arbiter1_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30191 | module Arbiter1_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30214 | module Arbiter1_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30249:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30249 | module Arbiter1_Bool( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30258 | module ram_16x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30277:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30277 | module Queue16_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30360:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30360 | module Queue1_TLBundleE_a32d128s1k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30388:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30388 | module MSHR( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30835:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30835 | module Arbiter1_HellaCacheResp( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30879:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30879 | module IOMSHR( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:31790:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31790 | module sdq_17x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:31809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31809 | module MSHRFile( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:32350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32350 | module OptimizationBarrier_TLBEntryData( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:32406:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32406 | module PMPChecker_s3( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:32691:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32691 | module PMAChecker( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:32731:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32731 | module DTLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:35923:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35923 | module L1MetadataArray( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:35990:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35990 | module Arbiter5_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36023:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36023 | module Arbiter2_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36055 | module DataArray( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36151 | module Arbiter4_L1DataReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36180:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36180 | module Arbiter2_L1DataWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36206:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36206 | module AMOALU( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36248:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36248 | module MaxPeriodFibonacciLFSR( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36342:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36342 | module Arbiter2_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36377:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36377 | module NonBlockingDCache( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:37660:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37660 | module ICache( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:37914:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37914 | module ShiftQueue( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:38054:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38054 | module PMPChecker_s2( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:38215:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38215 | module ITLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:41129:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41129 | module Frontend( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:41494:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41494 | module TLMonitor_19( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:42301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +42301 | module TLMonitor_20( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43108:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43108 | module TLXbar_i2_o1_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43343 | module TLMonitor_21( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43851:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43851 | module ram_2x116( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43870:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43870 | module Queue2_TLBundleA_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43947:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43947 | module ram_2x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43966:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43966 | module Queue2_TLBundleD_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44045:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44045 | module TLBuffer_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44158:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44158 | module TLMonitor_22( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44783 | module TLBuffer_a32d64s1k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44892:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44892 | module TLMonitor_23( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:45699:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45699 | module Repeater_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:45766:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45766 | module TLWidthWidget8_4( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:46074:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46074 | module TLMonitor_24( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:46882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46882 | module ram_2x117( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:46901:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46901 | module Queue2_TLBundleA_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:46981:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46981 | module ram_2x78( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47000:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47000 | module Queue2_TLBundleD_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47079:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47079 | module TLBuffer_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47214 | module HellaCacheArbiter( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47381 | module Arbiter3_Valid_PTWReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47419:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47419 | module OptimizationBarrier_UInt( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47427 | module OptimizationBarrier_PTE( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47459 | module PTW( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:48434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +48434 | module FPUDecoder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:49794:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49794 | module CompareRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:49824:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49824 | module RecFNToIN_e11_s53_i64( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:49873:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49873 | module RecFNToIN_e11_s53_i32( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:49912:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49912 | module FPToInt( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50375:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50375 | module RoundAnyRawFNToRecFN_ie7_is64_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50410:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50410 | module PipelinedINToRecFN( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50513:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50513 | module RoundAnyRawFNToRecFN_ie7_is64_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50539 | module PipelinedINToRecFN_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50614 | module RoundAnyRawFNToRecFN_ie7_is64_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50642:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50642 | module PipelinedINToRecFN_2( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50717 | module IntToFP( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51072:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51072 | module RoundAnyRawFNToRecFN_ie11_is53_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51199:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51199 | module RecFNToRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51221 | module RoundAnyRawFNToRecFN_ie11_is53_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51321:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51321 | module RecFNToRecFN_1( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51343 | module FPToFP( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51469:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51469 | module MulAddRecFNToRaw_preMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51569 | module MulAddRecFNToRaw_postMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51822:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51822 | module RoundAnyRawFNToRecFN_ie11_is55_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51953 | module RoundAnyRawFNToRecFN_ie11_is55_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52060:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52060 | module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52194:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52194 | module SharedMulAddRecFNPipe( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52551:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52551 | module FPUSharedFMAPipe( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52682:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52682 | module DivSqrtRawFN_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52852:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52852 | module DivSqrtRecFMToRaw_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52907:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52907 | module RoundAnyRawFNToRecFN_ie5_is13_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53039:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53039 | module RoundRawFNToRecFN_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53068:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53068 | module DivSqrtRecFM_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53128:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53128 | module DivSqrtRawFN_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53297:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53297 | module DivSqrtRecFMToRaw_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53352:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53352 | module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53456:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53456 | module RoundRawFNToRecFN_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53485:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53485 | module DivSqrtRecFM_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53545:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53545 | module DivSqrtRawFN_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53715:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53715 | module DivSqrtRecFMToRaw_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53770:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53770 | module RoundRawFNToRecFN_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53799 | module DivSqrtRecFM_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53860:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53860 | module regfile_32x65( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53905:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53905 | module FPU( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:54820:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +54820 | module RVCExpander( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:55183:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55183 | module IBuf( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:55307:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55307 | module CSRFile( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:57223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57223 | module RocketALU( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:57809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57809 | module MulDiv( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:58107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58107 | module Arbiter3_LLWB( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:58125:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58125 | module rf_31x64( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:58149:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58149 | module RocketBB( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62838:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62838 | module GlobalDecoder( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62928:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62928 | module BankAliasTable( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:64252:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64252 | module BankScoreboard( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:64627:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64627 | module GlobalROB( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68674:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68674 | module Arbiter3_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68717 | module ram_16x4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68736:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68736 | module Queue16_UInt4( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68782:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68782 | module SubROB( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:69357:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69357 | module Arbiter1_SubRobRow( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:69722:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69722 | module GlobalScheduler( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:70973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +70973 | module BootRom( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:71013:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71013 | module Frontend_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:71637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71637 | module PE( + | ^~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:71656:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71656 | module AlwaysOutTransposer( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:72411:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72411 | module MacUnit( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:72426:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72426 | module PE_64( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:72524:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72524 | module Tile( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:72571:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72571 | module Mesh( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76050 | module TagQueue( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76191 | module ram_6x7( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76210:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76210 | module Queue6_TagWithIdAndTotalRows( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76271:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76271 | module MeshWithDelays( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77318:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77318 | module ram_data_8x64( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77337 | module Queue8_SramReadResp( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77385:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77385 | module GemminiExCtrl( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79354:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79354 | module LoopMatmulUnroller( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79637 | module LoopConvAddrGen( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79690:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79690 | module LoopConvUnroller( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:80113:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80113 | module LoopCmdEncoder( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:80402:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80402 | module Arbiter2_LoopCmd( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:80598:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80598 | module GemminiBall( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:81783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81783 | module RRArbiter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:81857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81857 | module CmdRouter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:81985:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81985 | module BallCyclePMC( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:82095:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82095 | module BBus( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:82898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82898 | module BallDomainDecoder( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83028 | module ram_4x281( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83047:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83047 | module Queue4_BallReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83178 | module Arbiter1_BallRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83198:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83198 | module BallReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83328:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83328 | module BallDomain( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84141:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84141 | module MemDomainDecoder( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84300:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84300 | module ram_4x158( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84319:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84319 | module Queue4_MemReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84421:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84421 | module Arbiter3_MemRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84463 | module MemReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84631 | module MemLoader( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84869:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84869 | module MemStorer( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85122:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85122 | module MemCyclePMC( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85241:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85241 | module TLB( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85621 | module RRArbiter_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85649:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85649 | module BBTLBCluster( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85777 | module StreamReader( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86142:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86142 | module StreamWriter( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86223 | module ZeroLineGenerator( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86264:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86264 | module MemConfiger( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86433:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86433 | module RRArbiter_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86465:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86465 | module MemGroupQueryArbiter( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86543:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86543 | module MemFrontend( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:87160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87160 | module MemMidend( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:87621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87621 | module SramBank( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:87672:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87672 | module AccPipe( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:87781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87781 | module PrivateMemBackend( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:90777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +90777 | module MemBackend( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:91055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91055 | module MemDomain( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:91973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91973 | module Queue1_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:92008:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92008 | module GpDomain( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:92040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92040 | module ram_8x21( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:92059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92059 | module Queue8_BuckyballAccelerator_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:92123:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92123 | module BuckyballAccelerator( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93569 | module Queue3_UInt2( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93614 | module SimpleHellaCacheIFReplayQueue( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93667:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93667 | module Arbiter2_HellaCacheReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93678:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93678 | module SimpleHellaCacheIF( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93768:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93768 | module BarrierUnit( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93785:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93785 | module BBTile( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:95579:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +95579 | module TLMonitor_25( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:96427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +96427 | module TLMonitor_26( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98184:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98184 | module ram_2x189( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98203:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98203 | module Queue2_TLBundleA_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98283:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98283 | module ram_2x142( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98302:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98302 | module Queue2_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98381 | module Queue2_TLBundleA_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98459 | module Queue2_TLBundleD_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98539 | module ram_2x60( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98558:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98558 | module Queue2_TLBundleB_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98622:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98622 | module ram_2x173( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98641:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98641 | module Queue2_TLBundleC_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98716:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98716 | module ram_sink_2x1( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98735:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98735 | module Queue2_TLBundleE_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98781 | module TLBuffer_a32d128s2k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99162:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99162 | module IntSyncSyncCrossingSink_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99173:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99173 | module IntSyncSyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99181:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99181 | module TilePRCIDomain( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99589:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99589 | module BundleBridgeNexus_UInt1_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99597:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99597 | module TLMonitor_27( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100216:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100216 | module CLINT( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100337 | module AsyncResetRegVec_w2_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100366:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100366 | module IntSyncCrossingSource_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100386 | module CLINTClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100449 | module TLMonitor_28( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101080:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101080 | module LevelGateway( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101099:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101099 | module PLICFanIn( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101111:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101111 | module Queue1_RegMapperInput_i23_m8( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101160 | module TLPLIC( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101389:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101389 | module PLICClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101452:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101452 | module TLMonitor_29( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101973 | module TLROM( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:102530:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102530 | module bootromClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:102569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102569 | module ToyLinuxSystem( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:103817:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103817 | module ToyLinuxChip( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:103984:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103984 | module tag_array( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104007:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104007 | module array_0_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104034:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104034 | module array_0_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104059 | module array_2_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104084:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104084 | module array_2_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104109:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104109 | module bbtile_icache_tag_array( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104132:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104132 | module bbtile_icache_data_arrays_0( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104155 | module bbtile_icache_data_arrays_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104176:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104176 | module bbtile_icache_data_arrays_2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104197:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104197 | module bbtile_icache_data_arrays_3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104218 | module robOperands( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104243:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104243 | module sram( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104268:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104268 | module mem( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104301 | module plusarg_reader #( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104326:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104326 | module ITraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104404:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104404 | module FpgaDspMac(input [7:0] a, b, input [19:0] c, output [19:0] y); + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104414 | module PMCTraceDPI( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104464:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104464 | module MemPMCTraceDPI( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104514:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104514 | module MTraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:1:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 1 | module tag_array_ext( input [4:0] RW0_addr, + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 19 | module array_0_0_ext( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:37:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 37 | module bbtile_icache_tag_array_ext( input [5:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:55:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 55 | module bbtile_icache_data_arrays_0_ext( input [7:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:73:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 73 | module robOperands_ext( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:90:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 90 | module sram_ext( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 107 | module mem_ext( input [9:0] RW0_addr, + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:3:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3 | module axi_smoke_memory #( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_tx.sv:27:15: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.transmitter' + 27 | count <= DIVISOR - 1; + | ^~ + ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=5.050 + ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_tx.sv:32:13: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.transmitter' + 32 | count <= DIVISOR - 1; + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_rx.sv:23:55: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.receiver' + 23 | IDLE: if (!rx_sync) begin state <= START; count <= DIVISOR/2 - 1; end + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_rx.sv:26:57: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.receiver' + 26 | else begin state <= DATA; bit_index <= 0; count <= DIVISOR - 1; end + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_rx.sv:29:46: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.receiver' + 29 | shift[bit_index] <= rx_sync; count <= DIVISOR - 1; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:32:43: Operator ADD expects 33 bits on the RHS, but RHS's VARREF 'length' generates 16 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 32 | wire [32:0] end_address = {1'b0,address}+length; + | ^ + ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=5.050 + ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:35:38: Operator ADD expects 32 bits on the RHS, but RHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 35 | wire [31:0] byte_address = address + cursor; + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:67:32: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's SHIFTR generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 67 | 11,12,13,14:tx_data=RAM_BYTES >> ((reply_index-11)*8); + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:68:32: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's SHIFTR generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 68 | 15,16,17,18:tx_data=CLOCK_HZ >> ((reply_index-15)*8); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:73:28: Operator EQ expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 73 | else if(reply_index==7+reply_length) tx_data=crc[7:0]; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:64:23: Operator LT expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 64 | if(reply_index<7+reply_length) begin + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:119:20: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 119 | if(cursor+1==length) state<=CRC0; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:144:25: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 144 | else if(cursor+1==length) begin image_loaded<=1;state<=REPLY;end + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:152:20: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 152 | if(cursor+1==length) state<=REPLY; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:157:43: Operator LT expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 157 | if(reply_index>=2 && reply_index<7+reply_length) crc<=crc_next(crc,tx_data); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:158:25: Operator EQ expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 158 | if(reply_index==8+reply_length) state<=DRAIN; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:87:37: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'timeout_count' generates 22 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 87 | if((receiving && timeout_count==RX_TIMEOUT-1) || (receiving && rx_error)) begin + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:52:20: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'addr' generates 28 bits. + : ... note: In instance 'tb_board_cpu.memory' + 52 | offset=(addr & ~(LANES-1))-BASE; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:78:28: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'write_addr' generates 28 bits. + : ... note: In instance 'tb_board_cpu.memory' + 78 | offset=(write_addr & ~(LANES-1))-BASE; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:86:26: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'h600d600d' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 86 | if (w_bits_data==64'h600d600d) begin + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:91:66: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 91 | $fatal(1,"CPU smoke failed at stage %0d",w_bits_data & 64'hffff); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:90:28: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff0000' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:90:43: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'hbad00000' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_platform.sv:406:33: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's REDOR generates 1 bits. + : ... note: In instance 'tb_board_cpu.platform' + 406 | assign peripherals_b_bits_resp=|scu_bresp; + | ^ +make: Entering directory '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/obj' +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_timing.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_timing.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_threads.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_threads.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb_board_cpu__pch.h -o Vtb_board_cpu__pch.h.fast.gch +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb_board_cpu__pch.h -o Vtb_board_cpu__pch.h.slow.gch +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__0.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__1.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__2.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__3.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__4.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__5.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__6.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__7.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__8.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__9.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu__main.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu__ConstPool__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__1__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__2__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__3__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu__Syms__Slow.cpp +g++ verilated.o verilated_timing.o verilated_threads.o Vtb_board_cpu__ALL.a -pthread -lpthread -latomic -o Vtb_board_cpu +rm Vtb_board_cpu__ALL.verilator_deplist.tmp +make: Leaving directory '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/obj' +- V e r i l a t i o n R e p o r t: Verilator 5.050 2026-07-01 rev v5.050 +- Verilator: Built from 46.457 MB sources in 354 modules, into 26.450 MB in 19 C++ files needing 0.019 MB +- Verilator: Walltime 12.360 s (elab=0.529, cvt=3.158, bld=7.971); cpu 4.683 s on 8 threads; allocated 437.324 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/loop/simulation.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/loop/simulation.log new file mode 100644 index 0000000..d8463e4 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/loop/simulation.log @@ -0,0 +1,5 @@ +PASS CPU Sv39/FPU/AMO/cache/interrupt through board AXI/SCU cycles=684219 +- /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:56: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 7ms; walltime 5.322 s; speed 1.286 ms/s +- Verilator: cpu 5.319 s on 1 threads; allocated 8 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/rob-board-regression.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/rob-board-regression.log new file mode 100644 index 0000000..fd3b723 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/rob-board-regression.log @@ -0,0 +1,31 @@ +PASS fullwidth AXI: sizes 8..128 bits, INCR/FIXED, strobes, concurrent R/W, stalls, IDs, range/4KiB rejection; read beats=90 +/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/tb_axi_fullwidth.sv:107: $finish called at 9270000 (1ps) +PASS SCU OpenSBI byte addresses, AXI lanes, RX pop/IRQ, TX backpressure, EXIT +/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/tb_axi_scu.sv:64: $finish called at 20580000 (1ps) +PASS: DDR UART loader CRC, 256-byte unaligned RAM roundtrip, rejected writes/RUN, timeout and boot +/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-unit/tb_ddr_loader.sv:116: $finish called at 78290000 (1ps) +PASS CPU Sv39/FPU/AMO/cache/interrupt through board AXI/SCU cycles=709434 +- /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:56: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 7ms; walltime 5.829 s; speed 1.217 ms/s +- Verilator: cpu 5.826 s on 1 threads; allocated 8 MB + +PASS CPU Sv39/FPU/AMO/cache/interrupt through board AXI/SCU cycles=251063 +- /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:56: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 3ms; walltime 2.245 s; speed 1.118 ms/s +- Verilator: cpu 2.243 s on 1 threads; allocated 8 MB + +PASS CPU Sv39/FPU/AMO/cache/interrupt through board AXI/SCU cycles=684219 +- /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:56: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 7ms; walltime 5.322 s; speed 1.286 ms/s +- Verilator: cpu 5.319 s on 1 threads; allocated 8 MB + +PASS CPU Sv39/FPU/AMO/cache/interrupt through board AXI/SCU cycles=1914839 +- /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:56: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 19ms; walltime 14.201 s; speed 1.348 ms/s +- Verilator: cpu 14.194 s on 1 threads; allocated 8 MB + +PASS BOARD_REGRESSION CPU/Gemmini/loop/DMA diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/rob-core-binding.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/rob-core-binding.log new file mode 100644 index 0000000..dab7e31 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/rob-core-binding.log @@ -0,0 +1,24 @@ +Bound 7 memory types, 20 instances +PASS RF adapter matches original port contract; only RF module body replaced +Final core SHA256: 31e7e07f94d08208dbb564edf9546240df26ff834935bfb646b71b541d875fb9 +{ + "result": "PREPARED_NOT_VALIDATED", + "architectural_profile_unchanged": true, + "existing_memory_geometry_unchanged": true, + "rob_operand_memory": { + "module_name": "robOperands_ext", + "depth": 16, + "width": 128, + "masked": false, + "read": 1, + "write": 1, + "readwrite": 0, + "extra_ports": [], + "hierarchy": [ + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.accelerators_0.frontend.scheduler.rob.robOperands.robOperands_ext" + ] + }, + "rob_operand_ram_style": "block", + "core_rtl_sha256": "31e7e07f94d08208dbb564edf9546240df26ff834935bfb646b71b541d875fb9", + "memory_rtl_sha256": "d5a37896aee19c8d4931c87dc9683861abf32f096a1c1441f4362370d3d7b054" +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/rob-core-elaboration.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/rob-core-elaboration.log new file mode 100644 index 0000000..0641156 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/rob-core-elaboration.log @@ -0,0 +1,390 @@ +[info] welcome to sbt 1.12.11 (N/A Java 17.0.20) +[info] loading project definition from /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/project +[info] loading settings for project root from build.sbt... +[info] set current project to toy-arty-a7-linux (in build file:/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/) +[info] running fpga.arty.linux.EmitToyLinux build/serial-raw --fpga-memories --serial-fpga +[warn] patches/buckyball/GemminiExCtrlPreloadStates.scala 67:15: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] op2Buf(xpose_row_cnt) := rdQueue0.io.deq.bits.data +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlPreloadStates.scala 83:51: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] VecInit((0 until DIM).map(i => op2Buf(i)(transpose_col))) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlStoreOps.scala 16:13: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] outBuf(outBufRows) := widenMeshToAcc(mesh.io.resp.bits.data) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlComputeFeedState.scala 46:17: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] op1Buf(xpose_row_cnt) := rdQueue0.io.deq.bits.data +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlComputeFeedState.scala 51:17: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] op2Buf(xpose_row_cnt) := rdQueue1.io.deq.bits.data +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlComputeFeedState.scala 68:65: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] val a_col_row = VecInit((0 until DIM).map(i => op1Buf(i)(feed_row_cnt))) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlComputeFeedState.scala 69:65: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] val x_col_row = VecInit((0 until DIM).map(i => op2Buf(i)(feed_row_cnt))) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlStoreOps.scala 27:15: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] outBuf(total_rows - 1.U - outBufCollected) := widenMeshToAcc( +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlStoreOps.scala 69:17: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] outBuf(outBufRows) := widenMeshToAcc(mesh.io.resp.bits.data) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlStoreOps.scala 100:31: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] val row = outBuf(rowIdx) +[warn] ^ +[warn] There were 10 warning(s) during hardware elaboration. +espresso is not found in your PATH: +/nix/store/2y0qz1r84ckgmmrnfvx9bbysnyn1zb61-openjdk-17.0.20+8/lib/openjdk/bin +/nix/store/2y0qz1r84ckgmmrnfvx9bbysnyn1zb61-openjdk-17.0.20+8/bin +/nix/store/ahvmb4byixykslwcxiay7c4ivhgpf8vg-sbt-1.8.2/bin +/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/bin +/nix/store/y8vkcyc8frd7ipcq0a6jix4xilgm93j7-riscv64-unknown-elf-gcc/bin +/nix/store/ywdz7hiyhb7hkp0vyzqfdx3fmrf1v8pa-yosys-0.67/bin +/home/yys/bin +/home/yys/bin +/home/yys/.nix-profile/bin +/nix/var/nix/profiles/default/bin +/usr/local/sbin +/usr/local/bin +/usr/sbin +/usr/bin +/sbin +/bin +/usr/games +/usr/local/games +/snap/bin +Interrupt map (2 harts 1 interrupts): + [1, 1] => system + +:52.18-57.5: Warning (simple_bus_reg): /soc/cbus_clock: missing or empty reg/ranges property +:68.28-71.5: Warning (simple_bus_reg): /soc/external-interrupts: missing or empty reg/ranges property +:72.18-77.5: Warning (simple_bus_reg): /soc/fbus_clock: missing or empty reg/ranges property +:88.18-93.5: Warning (simple_bus_reg): /soc/mbus_clock: missing or empty reg/ranges property +:100.18-105.5: Warning (simple_bus_reg): /soc/pbus_clock: missing or empty reg/ranges property +:111.18-116.5: Warning (simple_bus_reg): /soc/sbus_clock: missing or empty reg/ranges property +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ucb-bar,buckyball-dev"; + model = "ucb-bar,buckyball"; + L10: cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <1000000>; + L12: cpu@0 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <32>; + d-cache-size = <8192>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + hardware-exec-breakpoint-count = <0>; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <8192>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + next-level-cache = <&L16>; + reg = <0x0>; + riscv,isa = "rv64imafdcbzicsr_zifencei_zihpm_zfh_zba_zbb_zbs_xrocket"; + riscv,pmpgranularity = <4>; + riscv,pmpregions = <8>; + status = "okay"; + timebase-frequency = <1000000>; + tlb-split; + L6: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + L16: memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; + }; + L9: soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ucb-bar,buckyball-soc", "simple-bus"; + ranges; + L3: cbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "cbus_clock"; + compatible = "fixed-clock"; + }; + L13: clint@2000000 { + compatible = "riscv,clint0"; + interrupts-extended = <&L6 3 &L6 7>; + reg = <0x2000000 0x10000>; + reg-names = "control"; + }; + L4: error-device@3000 { + compatible = "sifive,error0"; + reg = <0x3000 0x1000>; + }; + L15: external-interrupts { + interrupt-parent = <&L14>; + interrupts = <1>; + }; + L2: fbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "fbus_clock"; + compatible = "fixed-clock"; + }; + L14: interrupt-controller@c000000 { + #interrupt-cells = <1>; + compatible = "riscv,plic0"; + interrupt-controller; + interrupts-extended = <&L6 11 &L6 9>; + reg = <0xc000000 0x4000000>; + reg-names = "control"; + riscv,max-priority = <1>; + riscv,ndev = <1>; + }; + L5: mbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "mbus_clock"; + compatible = "fixed-clock"; + }; + L17: mmio-port-axi4@60000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x60000000 0x60000000 0x10000000>; + }; + L1: pbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "pbus_clock"; + compatible = "fixed-clock"; + }; + L18: rom@10000 { + compatible = "sifive,rom0"; + reg = <0x10000 0x10000>; + reg-names = "mem"; + }; + L0: sbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "sbus_clock"; + compatible = "fixed-clock"; + }; + }; +}; + +Generated Address Map + 3000 - 4000 ARWX error-device@3000 + 10000 - 20000 R X rom@10000 + 2000000 - 2010000 ARW clint@2000000 + c000000 - 10000000 ARW interrupt-controller@c000000 + 60000000 - 70000000 RWX mmio-port-axi4@60000000 + 80000000 - 90000000 RWXC memory@80000000 + +[warn] thirdparty/rocket-chip/src/main/scala/rocket/NBDcache.scala 456:25: [W004] Dynamic index with width 1 is too wide for Vec of size 1 (expected index width 0). +[warn] io.refill := refillMux(io.mem_grant.bits.source) +[warn] ^ +[warn] There were 1 warning(s) during hardware elaboration. +[success] Total time: 130 s (0:02:10.0), completed Oct 12, 2026, 7:58:26 PM +[info] running fpga.arty.linux.EmitToyLinux build/serial-reference --serial-fpga +[warn] patches/buckyball/GemminiExCtrlPreloadStates.scala 67:15: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] op2Buf(xpose_row_cnt) := rdQueue0.io.deq.bits.data +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlPreloadStates.scala 83:51: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] VecInit((0 until DIM).map(i => op2Buf(i)(transpose_col))) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlStoreOps.scala 16:13: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] outBuf(outBufRows) := widenMeshToAcc(mesh.io.resp.bits.data) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlComputeFeedState.scala 46:17: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] op1Buf(xpose_row_cnt) := rdQueue0.io.deq.bits.data +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlComputeFeedState.scala 51:17: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] op2Buf(xpose_row_cnt) := rdQueue1.io.deq.bits.data +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlComputeFeedState.scala 68:65: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] val a_col_row = VecInit((0 until DIM).map(i => op1Buf(i)(feed_row_cnt))) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlComputeFeedState.scala 69:65: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] val x_col_row = VecInit((0 until DIM).map(i => op2Buf(i)(feed_row_cnt))) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlStoreOps.scala 27:15: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] outBuf(total_rows - 1.U - outBufCollected) := widenMeshToAcc( +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlStoreOps.scala 69:17: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] outBuf(outBufRows) := widenMeshToAcc(mesh.io.resp.bits.data) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlStoreOps.scala 100:31: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] val row = outBuf(rowIdx) +[warn] ^ +[warn] There were 10 warning(s) during hardware elaboration. +espresso is not found in your PATH: +/nix/store/2y0qz1r84ckgmmrnfvx9bbysnyn1zb61-openjdk-17.0.20+8/lib/openjdk/bin +/nix/store/2y0qz1r84ckgmmrnfvx9bbysnyn1zb61-openjdk-17.0.20+8/bin +/nix/store/ahvmb4byixykslwcxiay7c4ivhgpf8vg-sbt-1.8.2/bin +/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/bin +/nix/store/y8vkcyc8frd7ipcq0a6jix4xilgm93j7-riscv64-unknown-elf-gcc/bin +/nix/store/ywdz7hiyhb7hkp0vyzqfdx3fmrf1v8pa-yosys-0.67/bin +/home/yys/bin +/home/yys/bin +/home/yys/.nix-profile/bin +/nix/var/nix/profiles/default/bin +/usr/local/sbin +/usr/local/bin +/usr/sbin +/usr/bin +/sbin +/bin +/usr/games +/usr/local/games +/snap/bin +Interrupt map (2 harts 1 interrupts): + [1, 1] => system + +:52.18-57.5: Warning (simple_bus_reg): /soc/cbus_clock: missing or empty reg/ranges property +:68.28-71.5: Warning (simple_bus_reg): /soc/external-interrupts: missing or empty reg/ranges property +:72.18-77.5: Warning (simple_bus_reg): /soc/fbus_clock: missing or empty reg/ranges property +:88.18-93.5: Warning (simple_bus_reg): /soc/mbus_clock: missing or empty reg/ranges property +:100.18-105.5: Warning (simple_bus_reg): /soc/pbus_clock: missing or empty reg/ranges property +:111.18-116.5: Warning (simple_bus_reg): /soc/sbus_clock: missing or empty reg/ranges property +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ucb-bar,buckyball-dev"; + model = "ucb-bar,buckyball"; + L10: cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <1000000>; + L12: cpu@0 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <32>; + d-cache-size = <8192>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + hardware-exec-breakpoint-count = <0>; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <8192>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + next-level-cache = <&L16>; + reg = <0x0>; + riscv,isa = "rv64imafdcbzicsr_zifencei_zihpm_zfh_zba_zbb_zbs_xrocket"; + riscv,pmpgranularity = <4>; + riscv,pmpregions = <8>; + status = "okay"; + timebase-frequency = <1000000>; + tlb-split; + L6: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + L16: memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; + }; + L9: soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ucb-bar,buckyball-soc", "simple-bus"; + ranges; + L3: cbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "cbus_clock"; + compatible = "fixed-clock"; + }; + L13: clint@2000000 { + compatible = "riscv,clint0"; + interrupts-extended = <&L6 3 &L6 7>; + reg = <0x2000000 0x10000>; + reg-names = "control"; + }; + L4: error-device@3000 { + compatible = "sifive,error0"; + reg = <0x3000 0x1000>; + }; + L15: external-interrupts { + interrupt-parent = <&L14>; + interrupts = <1>; + }; + L2: fbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "fbus_clock"; + compatible = "fixed-clock"; + }; + L14: interrupt-controller@c000000 { + #interrupt-cells = <1>; + compatible = "riscv,plic0"; + interrupt-controller; + interrupts-extended = <&L6 11 &L6 9>; + reg = <0xc000000 0x4000000>; + reg-names = "control"; + riscv,max-priority = <1>; + riscv,ndev = <1>; + }; + L5: mbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "mbus_clock"; + compatible = "fixed-clock"; + }; + L17: mmio-port-axi4@60000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x60000000 0x60000000 0x10000000>; + }; + L1: pbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "pbus_clock"; + compatible = "fixed-clock"; + }; + L18: rom@10000 { + compatible = "sifive,rom0"; + reg = <0x10000 0x10000>; + reg-names = "mem"; + }; + L0: sbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "sbus_clock"; + compatible = "fixed-clock"; + }; + }; +}; + +Generated Address Map + 3000 - 4000 ARWX error-device@3000 + 10000 - 20000 R X rom@10000 + 2000000 - 2010000 ARW clint@2000000 + c000000 - 10000000 ARW interrupt-controller@c000000 + 60000000 - 70000000 RWX mmio-port-axi4@60000000 + 80000000 - 90000000 RWXC memory@80000000 + +[warn] thirdparty/rocket-chip/src/main/scala/rocket/NBDcache.scala 456:25: [W004] Dynamic index with width 1 is too wide for Vec of size 1 (expected index width 0). +[warn] io.refill := refillMux(io.mem_grant.bits.source) +[warn] ^ +[warn] There were 1 warning(s) during hardware elaboration. +[success] Total time: 61 s (0:01:01.0), completed Oct 12, 2026, 7:59:26 PM diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/rob-memory-regression.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/rob-memory-regression.log new file mode 100644 index 0000000..287eefc --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/rob-memory-regression.log @@ -0,0 +1,10 @@ +PASS sram_ext depth=8 width=1269 1R1W +PASS robOperands_ext depth=16 width=128 1R1W +PASS tag_array_ext: original RTL + scoreboard, full depth/mask/enable +PASS array_0_0_ext depth=128 width=128 1R1W +PASS bbtile_icache_tag_array_ext: original RTL + scoreboard, full depth/mask/enable +PASS bbtile_icache_data_arrays_0_ext: original RTL + scoreboard, full depth/mask/enable +PASS mem_ext: original RTL + scoreboard, full depth/mask/enable +PASS all memory bindings +build/serial-bound/tb_memories.sv:585: $finish called at 51147000 (1ps) + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/rob-optin-candidate.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/rob-optin-candidate.log new file mode 100644 index 0000000..2f8b9c6 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/rob-optin-candidate.log @@ -0,0 +1,194 @@ +[info] welcome to sbt 1.12.11 (N/A Java 17.0.20) +[info] loading project definition from /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/project +[info] loading settings for project root from build.sbt... +[info] set current project to toy-arty-a7-linux (in build file:/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/) +[info] running fpga.arty.linux.EmitToyLinux build/rob-optin-raw --fpga-memories --serial-fpga +[warn] patches/buckyball/GemminiExCtrlPreloadStates.scala 67:15: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] op2Buf(xpose_row_cnt) := rdQueue0.io.deq.bits.data +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlPreloadStates.scala 83:51: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] VecInit((0 until DIM).map(i => op2Buf(i)(transpose_col))) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlStoreOps.scala 16:13: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] outBuf(outBufRows) := widenMeshToAcc(mesh.io.resp.bits.data) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlComputeFeedState.scala 46:17: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] op1Buf(xpose_row_cnt) := rdQueue0.io.deq.bits.data +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlComputeFeedState.scala 51:17: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] op2Buf(xpose_row_cnt) := rdQueue1.io.deq.bits.data +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlComputeFeedState.scala 68:65: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] val a_col_row = VecInit((0 until DIM).map(i => op1Buf(i)(feed_row_cnt))) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlComputeFeedState.scala 69:65: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] val x_col_row = VecInit((0 until DIM).map(i => op2Buf(i)(feed_row_cnt))) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlStoreOps.scala 27:15: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] outBuf(total_rows - 1.U - outBufCollected) := widenMeshToAcc( +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlStoreOps.scala 69:17: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] outBuf(outBufRows) := widenMeshToAcc(mesh.io.resp.bits.data) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlStoreOps.scala 100:31: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] val row = outBuf(rowIdx) +[warn] ^ +[warn] There were 10 warning(s) during hardware elaboration. +espresso is not found in your PATH: +/nix/store/2y0qz1r84ckgmmrnfvx9bbysnyn1zb61-openjdk-17.0.20+8/lib/openjdk/bin +/nix/store/2y0qz1r84ckgmmrnfvx9bbysnyn1zb61-openjdk-17.0.20+8/bin +/nix/store/ahvmb4byixykslwcxiay7c4ivhgpf8vg-sbt-1.8.2/bin +/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/bin +/nix/store/y8vkcyc8frd7ipcq0a6jix4xilgm93j7-riscv64-unknown-elf-gcc/bin +/nix/store/ywdz7hiyhb7hkp0vyzqfdx3fmrf1v8pa-yosys-0.67/bin +/home/yys/bin +/usr/local/sbin +/usr/local/bin +/usr/sbin +/usr/bin +/sbin +/bin +/usr/games +/usr/local/games +/snap/bin +Interrupt map (2 harts 1 interrupts): + [1, 1] => system + +:52.18-57.5: Warning (simple_bus_reg): /soc/cbus_clock: missing or empty reg/ranges property +:68.28-71.5: Warning (simple_bus_reg): /soc/external-interrupts: missing or empty reg/ranges property +:72.18-77.5: Warning (simple_bus_reg): /soc/fbus_clock: missing or empty reg/ranges property +:88.18-93.5: Warning (simple_bus_reg): /soc/mbus_clock: missing or empty reg/ranges property +:100.18-105.5: Warning (simple_bus_reg): /soc/pbus_clock: missing or empty reg/ranges property +:111.18-116.5: Warning (simple_bus_reg): /soc/sbus_clock: missing or empty reg/ranges property +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ucb-bar,buckyball-dev"; + model = "ucb-bar,buckyball"; + L10: cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <1000000>; + L12: cpu@0 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <32>; + d-cache-size = <8192>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + hardware-exec-breakpoint-count = <0>; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <8192>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + next-level-cache = <&L16>; + reg = <0x0>; + riscv,isa = "rv64imafdcbzicsr_zifencei_zihpm_zfh_zba_zbb_zbs_xrocket"; + riscv,pmpgranularity = <4>; + riscv,pmpregions = <8>; + status = "okay"; + timebase-frequency = <1000000>; + tlb-split; + L6: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + L16: memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; + }; + L9: soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ucb-bar,buckyball-soc", "simple-bus"; + ranges; + L3: cbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "cbus_clock"; + compatible = "fixed-clock"; + }; + L13: clint@2000000 { + compatible = "riscv,clint0"; + interrupts-extended = <&L6 3 &L6 7>; + reg = <0x2000000 0x10000>; + reg-names = "control"; + }; + L4: error-device@3000 { + compatible = "sifive,error0"; + reg = <0x3000 0x1000>; + }; + L15: external-interrupts { + interrupt-parent = <&L14>; + interrupts = <1>; + }; + L2: fbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "fbus_clock"; + compatible = "fixed-clock"; + }; + L14: interrupt-controller@c000000 { + #interrupt-cells = <1>; + compatible = "riscv,plic0"; + interrupt-controller; + interrupts-extended = <&L6 11 &L6 9>; + reg = <0xc000000 0x4000000>; + reg-names = "control"; + riscv,max-priority = <1>; + riscv,ndev = <1>; + }; + L5: mbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "mbus_clock"; + compatible = "fixed-clock"; + }; + L17: mmio-port-axi4@60000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x60000000 0x60000000 0x10000000>; + }; + L1: pbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "pbus_clock"; + compatible = "fixed-clock"; + }; + L18: rom@10000 { + compatible = "sifive,rom0"; + reg = <0x10000 0x10000>; + reg-names = "mem"; + }; + L0: sbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "sbus_clock"; + compatible = "fixed-clock"; + }; + }; +}; + +Generated Address Map + 3000 - 4000 ARWX error-device@3000 + 10000 - 20000 R X rom@10000 + 2000000 - 2010000 ARW clint@2000000 + c000000 - 10000000 ARW interrupt-controller@c000000 + 60000000 - 70000000 RWX mmio-port-axi4@60000000 + 80000000 - 90000000 RWXC memory@80000000 + +[warn] thirdparty/rocket-chip/src/main/scala/rocket/NBDcache.scala 456:25: [W004] Dynamic index with width 1 is too wide for Vec of size 1 (expected index width 0). +[warn] io.refill := refillMux(io.mem_grant.bits.source) +[warn] ^ +[warn] There were 1 warning(s) during hardware elaboration. +[success] Total time: 14 s, completed Oct 12, 2026, 8:54:23 PM diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/rob-optin-default.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/rob-optin-default.log new file mode 100644 index 0000000..b38bf6e --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/rob-optin-default.log @@ -0,0 +1,196 @@ +[info] welcome to sbt 1.12.11 (N/A Java 17.0.20) +[info] loading project definition from /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/project +[info] loading settings for project root from build.sbt... +[info] set current project to toy-arty-a7-linux (in build file:/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/) +[info] compiling 1 Scala source to /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/target/scala-2.13/classes ... +[info] done compiling +[info] running fpga.arty.linux.EmitToyLinux build/rob-default-raw --fpga-memories --serial-fpga +[warn] patches/buckyball/GemminiExCtrlPreloadStates.scala 67:15: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] op2Buf(xpose_row_cnt) := rdQueue0.io.deq.bits.data +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlPreloadStates.scala 83:51: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] VecInit((0 until DIM).map(i => op2Buf(i)(transpose_col))) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlStoreOps.scala 16:13: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] outBuf(outBufRows) := widenMeshToAcc(mesh.io.resp.bits.data) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlComputeFeedState.scala 46:17: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] op1Buf(xpose_row_cnt) := rdQueue0.io.deq.bits.data +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlComputeFeedState.scala 51:17: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] op2Buf(xpose_row_cnt) := rdQueue1.io.deq.bits.data +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlComputeFeedState.scala 68:65: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] val a_col_row = VecInit((0 until DIM).map(i => op1Buf(i)(feed_row_cnt))) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlComputeFeedState.scala 69:65: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] val x_col_row = VecInit((0 until DIM).map(i => op2Buf(i)(feed_row_cnt))) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlStoreOps.scala 27:15: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] outBuf(total_rows - 1.U - outBufCollected) := widenMeshToAcc( +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlStoreOps.scala 69:17: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] outBuf(outBufRows) := widenMeshToAcc(mesh.io.resp.bits.data) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlStoreOps.scala 100:31: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] val row = outBuf(rowIdx) +[warn] ^ +[warn] There were 10 warning(s) during hardware elaboration. +espresso is not found in your PATH: +/nix/store/2y0qz1r84ckgmmrnfvx9bbysnyn1zb61-openjdk-17.0.20+8/lib/openjdk/bin +/nix/store/2y0qz1r84ckgmmrnfvx9bbysnyn1zb61-openjdk-17.0.20+8/bin +/nix/store/ahvmb4byixykslwcxiay7c4ivhgpf8vg-sbt-1.8.2/bin +/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/bin +/nix/store/y8vkcyc8frd7ipcq0a6jix4xilgm93j7-riscv64-unknown-elf-gcc/bin +/nix/store/ywdz7hiyhb7hkp0vyzqfdx3fmrf1v8pa-yosys-0.67/bin +/home/yys/bin +/usr/local/sbin +/usr/local/bin +/usr/sbin +/usr/bin +/sbin +/bin +/usr/games +/usr/local/games +/snap/bin +Interrupt map (2 harts 1 interrupts): + [1, 1] => system + +:52.18-57.5: Warning (simple_bus_reg): /soc/cbus_clock: missing or empty reg/ranges property +:68.28-71.5: Warning (simple_bus_reg): /soc/external-interrupts: missing or empty reg/ranges property +:72.18-77.5: Warning (simple_bus_reg): /soc/fbus_clock: missing or empty reg/ranges property +:88.18-93.5: Warning (simple_bus_reg): /soc/mbus_clock: missing or empty reg/ranges property +:100.18-105.5: Warning (simple_bus_reg): /soc/pbus_clock: missing or empty reg/ranges property +:111.18-116.5: Warning (simple_bus_reg): /soc/sbus_clock: missing or empty reg/ranges property +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ucb-bar,buckyball-dev"; + model = "ucb-bar,buckyball"; + L10: cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <1000000>; + L12: cpu@0 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <32>; + d-cache-size = <8192>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + hardware-exec-breakpoint-count = <0>; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <8192>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + next-level-cache = <&L16>; + reg = <0x0>; + riscv,isa = "rv64imafdcbzicsr_zifencei_zihpm_zfh_zba_zbb_zbs_xrocket"; + riscv,pmpgranularity = <4>; + riscv,pmpregions = <8>; + status = "okay"; + timebase-frequency = <1000000>; + tlb-split; + L6: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + L16: memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; + }; + L9: soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ucb-bar,buckyball-soc", "simple-bus"; + ranges; + L3: cbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "cbus_clock"; + compatible = "fixed-clock"; + }; + L13: clint@2000000 { + compatible = "riscv,clint0"; + interrupts-extended = <&L6 3 &L6 7>; + reg = <0x2000000 0x10000>; + reg-names = "control"; + }; + L4: error-device@3000 { + compatible = "sifive,error0"; + reg = <0x3000 0x1000>; + }; + L15: external-interrupts { + interrupt-parent = <&L14>; + interrupts = <1>; + }; + L2: fbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "fbus_clock"; + compatible = "fixed-clock"; + }; + L14: interrupt-controller@c000000 { + #interrupt-cells = <1>; + compatible = "riscv,plic0"; + interrupt-controller; + interrupts-extended = <&L6 11 &L6 9>; + reg = <0xc000000 0x4000000>; + reg-names = "control"; + riscv,max-priority = <1>; + riscv,ndev = <1>; + }; + L5: mbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "mbus_clock"; + compatible = "fixed-clock"; + }; + L17: mmio-port-axi4@60000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x60000000 0x60000000 0x10000000>; + }; + L1: pbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "pbus_clock"; + compatible = "fixed-clock"; + }; + L18: rom@10000 { + compatible = "sifive,rom0"; + reg = <0x10000 0x10000>; + reg-names = "mem"; + }; + L0: sbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "sbus_clock"; + compatible = "fixed-clock"; + }; + }; +}; + +Generated Address Map + 3000 - 4000 ARWX error-device@3000 + 10000 - 20000 R X rom@10000 + 2000000 - 2010000 ARW clint@2000000 + c000000 - 10000000 ARW interrupt-controller@c000000 + 60000000 - 70000000 RWX mmio-port-axi4@60000000 + 80000000 - 90000000 RWXC memory@80000000 + +[warn] thirdparty/rocket-chip/src/main/scala/rocket/NBDcache.scala 456:25: [W004] Dynamic index with width 1 is too wide for Vec of size 1 (expected index width 0). +[warn] io.refill := refillMux(io.mem_grant.bits.source) +[warn] ^ +[warn] There were 1 warning(s) during hardware elaboration. +[success] Total time: 19 s, completed Oct 12, 2026, 8:54:06 PM diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/MANIFEST.json b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/MANIFEST.json new file mode 100644 index 0000000..d01e75b --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/MANIFEST.json @@ -0,0 +1,364 @@ +{ + "files": { + "backpressure-mutation/new-test-compile.log": { + "sha256": "e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855", + "bytes": 0 + }, + "backpressure-mutation/new-test.log": { + "sha256": "a02db137d687a29f32c1b5e5a3e77dbf2f88997b873a50e7fc6cc611b1a942b2", + "bytes": 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"stale-baseline/sources/scripts/check_programming_scripts.py": { + "sha256": "b91b146da58df41b8453a61fd8eaf87e7314d56a8e8fff327270cb3dbed10f10", + "bytes": 2804 + } + } +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/REPORT.md b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/REPORT.md new file mode 100644 index 0000000..dfb271a --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/REPORT.md @@ -0,0 +1,48 @@ +# PR #10 新版自检报告 + +## 结论 + +自检基线为 `9fdcec6`。本轮未发现新增生产 RTL/Tcl/镜像校验的功能错误，发现并修正 +两处验证缺口。生产 RTL、烧录 Tcl、芯片配置和固件保持该基线字节；修改仅涉及测试、 +结果记录、文档及 CI。没有生成或烧录新位流，也没有取得新增实物验收。 + +## 自检发现与修正 + +| 发现 | 反证 | 修正 | +|---|---|---| +| 复跑失败可能保留旧 PASS | 给三个实际入口预置旧 PASS，再注入首个检查失败；旧版本均退出 1，但文件仍为 PASS | `offline_check.py` 在启动时写 RUNNING，异常时写 FAILED；三入口再次注入均得到 FAILED | +| 平台用例没有检查 BVALID 持续性 | 只在 build 副本将 SCU 的 BVALID 清除条件改成无视 BREADY；旧测试仍通过 | 每个背压周期检查 CPU 输入 BVALID/响应/ID，并检查握手后 BVALID 撤销；新测试在 valid=0 处失败 | + +“PASS_MUTATION_ORACLES”表示检错能力符合预期：旧测试漏检的反例应退出 0， +新测试拒绝错误应退出 1，不表示注入错误的 RTL 正确。错误副本不会替换生产源码。 + +## 本轮结果 + +- 四组接口回归通过：AXI fullwidth、SCU、平台响应、DDR UART loader。 +- 20 项 Tcl 返回值/异常/状态/备份检查、10 项普通/-O 镜像校验通过。 +- 三个实际检查入口的失败状态注入通过，复跑失败不再遗留 PASS。 +- 三项 RTL 注入反测符合预期；新增用例也再次抓住旧平台的 `10→01` 响应错误。 +- 原 2026-10-12 的 77 项评估档案、所有既有实现和实物档案保持原字节。 + +主要回归在服务器独立目录运行，总 timeout 为 600 秒；公开注入脚本另设外层 +180 秒和每个编译/仿真进程 60 秒。结果、输入摘要及范围在 `RESULT.json`，原文日志 +在各测试目录，实际输入快照在 `sources/`。`stale-baseline/` 保存旧版本的预期失败证据。 +这些都是离线验证，CPU 仅为端口 fixture，未模拟 CPU 行为、物理 MIG 或实际 Vivado +烧录过程；不能据此认定新位流已通过硬件验收。 + +## 复现 + +Linux 下安装 Python、Tcl 8.6、Icarus，在平台根目录执行： + +```bash +python3 scripts/check_board.py +python3 scripts/check_programming_scripts.py +python3 scripts/check_flash_guards.py +python3 scripts/check_runner_status.py +python3 scripts/check_platform_mutations.py +python3 scripts/verify_pr10_evidence.py +``` + +需要复现旧 PASS 问题时，确保 Git 本地包含 `9fdcec6`，执行 +`python3 scripts/check_runner_status.py --baseline-ref 9fdcec6`。这会使用旧入口的隔离副本， +不会改动当前入口。该命令会写入 runner-status-check，之后可再执行普通模式恢复当前检查结果。 diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/RESULT.json new file mode 100644 index 0000000..8071cdc --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/RESULT.json @@ -0,0 +1,53 @@ +{ + "result": "PASS_PR10_SELFCHECK", + "reviewed_parent": "9fdcec6941e75282f7c2e8318d347168e034c343", + "physical_hardware_tested": false, + "new_bitstream_generated": false, + "cpu_behavior_simulated": false, + "physical_mig_simulated": false, + "timeout_seconds": 600, + "interface_groups": 4, + "tcl_cases": 20, + "python_guard_cases": 10, + "runner_failure_cases": 3, + "mutation_cases": 3, + "historic_artifacts_unchanged": 279, + "production_sources_unchanged": { + "board/toy_a7_platform.sv": "f9bc06535b7de19a6b1b501f06effe90519fd43a78e669ab7425d301662540b8", + "board/axi_scu.sv": "ee77bf641d61811b4c1faea845752850c22461a63b4cdfd3d6f9cd223e6c2fc2", + "board/program_arty.tcl": "8af4c07627910536079eb4be647c6f0f447882950588c40588cdc571a72133ac", + "board/backup_flash.tcl": "fa9185afad3537bf15b4f2f0c952a4eebf9d6c5693619819ff5e57897ce6a86d", + "board/program_flash.tcl": "f9bf2b6fc6c9fdd268c308f417831c94707b464bbae75a5d2cc416f4c92bf424", + "host/flash.py": "83e366dab1dbf2c9cda3b3259a237bb970293742c13e3f7a5496d2478a1cbff1" + }, + "sources": { + "board/axi_fullwidth.sv": "bf07ae27724dbd0a361d732dfb57109f06beef207c47a066d400cb06d7f07d5a", + "board/axi_scu.sv": "ee77bf641d61811b4c1faea845752850c22461a63b4cdfd3d6f9cd223e6c2fc2", + "board/ddr_uart_loader.sv": "980f4cd2e3fa2a00b66143f879bc749ed952c2c1e54331460821bac0300c43d6", + "board/flash_spi_byte.sv": "4d1fac5238f31fb3a69a58d1aca9ccec722e833d788113b94d86c6a1b861045a", + "board/loader_axi.sv": "05609b0870054ea675aedb406f6215cd456f18db6d6428b461cbae03d9a662f4", + "board/toy_a7_platform.sv": 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+ "tests/mock_programming.tcl": "fd25ee00f3af89a3ec0416bd68a54f6cf7b3dac99c4a44f0c532cc36228312f1", + "tests/tb_axi_fullwidth.sv": "1d3964fab0eaa76a6f864f07a7dedf01639ba12a9400a15d0839e707ab73c4ed", + "tests/tb_axi_scu.sv": "5dfd1d6cac3201f0e5188e9b73e60ade27c4551570d4b00d387301713d9fbe97", + "tests/tb_platform_bresp.sv": "289875c2e92800307aa0b7fc5186c946ba127835473b30f626aef7baa67b4fe8" + } +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/backpressure-mutation/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/backpressure-mutation/RESULT.json new file mode 100644 index 0000000..4bc58dc --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/backpressure-mutation/RESULT.json @@ -0,0 +1,60 @@ +{ + "result": "PASS_MUTATION_ORACLES", + "physical_hardware_tested": false, + "cases": [ + { + "case": "old-test", + "exit_code": 0, + "expected_exit_code": 0, + "result": "PASS", + "sources": { + "board/toy_a7_platform.sv": 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"case": "new-test", + "exit_code": 1, + "expected_exit_code": 1, + "result": "PASS", + "sources": { + "board/toy_a7_platform.sv": "f9bc06535b7de19a6b1b501f06effe90519fd43a78e669ab7425d301662540b8", + "build/backpressure-mutation/scu-mutant.sv": "71386c725d8406dd15b8b4ee9c07d8b5d4f48ec9ffd5fc699b6d6da1f5127302", + "tests/tb_platform_bresp.sv": "289875c2e92800307aa0b7fc5186c946ba127835473b30f626aef7baa67b4fe8", + "board/axi_fullwidth.sv": "bf07ae27724dbd0a361d732dfb57109f06beef207c47a066d400cb06d7f07d5a", + "board/ddr_uart_loader.sv": "980f4cd2e3fa2a00b66143f879bc749ed952c2c1e54331460821bac0300c43d6", + "board/loader_axi.sv": "05609b0870054ea675aedb406f6215cd456f18db6d6428b461cbae03d9a662f4", + "board/uart_rx.sv": "0b35263884577324f146ff7fd516e5b561dcc8787e0d8ad599669bac1958406d", + "board/uart_tx.sv": "c20d420fc20be4f6313bdde5abc45ef0b9f8e93bf75350dd9951bc8868b3b65c", + "board/flash_spi_byte.sv": "4d1fac5238f31fb3a69a58d1aca9ccec722e833d788113b94d86c6a1b861045a", + "tests/ToyLinuxChipPorts.sv": "e4c06220cd7025972d432b06c452e85c62bd2cfccad618b2b993499b62e6621a" + } + }, + { + "case": "old-response", + "exit_code": 1, + "expected_exit_code": 1, + "result": "PASS", + "sources": { + "evidence/2026-10-12/pr10-review/old-platform.sv": "01fe1f8e2621a1a023ac3b8d91758868b190760f6e706ae1d34a67857b96d846", + "board/axi_scu.sv": "ee77bf641d61811b4c1faea845752850c22461a63b4cdfd3d6f9cd223e6c2fc2", + "tests/tb_platform_bresp.sv": "289875c2e92800307aa0b7fc5186c946ba127835473b30f626aef7baa67b4fe8", + "board/axi_fullwidth.sv": "bf07ae27724dbd0a361d732dfb57109f06beef207c47a066d400cb06d7f07d5a", + "board/ddr_uart_loader.sv": "980f4cd2e3fa2a00b66143f879bc749ed952c2c1e54331460821bac0300c43d6", + "board/loader_axi.sv": "05609b0870054ea675aedb406f6215cd456f18db6d6428b461cbae03d9a662f4", + "board/uart_rx.sv": "0b35263884577324f146ff7fd516e5b561dcc8787e0d8ad599669bac1958406d", + "board/uart_tx.sv": "c20d420fc20be4f6313bdde5abc45ef0b9f8e93bf75350dd9951bc8868b3b65c", + "board/flash_spi_byte.sv": "4d1fac5238f31fb3a69a58d1aca9ccec722e833d788113b94d86c6a1b861045a", + "tests/ToyLinuxChipPorts.sv": "e4c06220cd7025972d432b06c452e85c62bd2cfccad618b2b993499b62e6621a" + } + } + ] +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/backpressure-mutation/new-test-compile.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/backpressure-mutation/new-test-compile.log new file mode 100644 index 0000000..e69de29 diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/backpressure-mutation/new-test.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/backpressure-mutation/new-test.log new file mode 100644 index 0000000..0d43be6 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/backpressure-mutation/new-test.log @@ -0,0 +1,2 @@ +FATAL: /home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/tests/tb_platform_bresp.sv:28: Platform B response addr=60000000 valid=0 id=10 actual=00 expected=00 + Time: 90000 Scope: tb_platform_bresp.write_case diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/backpressure-mutation/old-response-compile.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/backpressure-mutation/old-response-compile.log new file mode 100644 index 0000000..e69de29 diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/backpressure-mutation/old-response.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/backpressure-mutation/old-response.log new file mode 100644 index 0000000..e83c9f2 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/backpressure-mutation/old-response.log @@ -0,0 +1,2 @@ +FATAL: /home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/tests/tb_platform_bresp.sv:28: Platform B response addr=60030000 valid=1 id=10 actual=01 expected=10 + Time: 170000 Scope: tb_platform_bresp.write_case diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/backpressure-mutation/old-test-compile.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/backpressure-mutation/old-test-compile.log new file mode 100644 index 0000000..e69de29 diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/backpressure-mutation/old-test.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/backpressure-mutation/old-test.log new file mode 100644 index 0000000..2bc0253 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/backpressure-mutation/old-test.log @@ -0,0 +1,2 @@ +PASS platform AXI B response: valid, invalid address, unaligned, burst, ID and backpressure +/home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/evidence/2026-10-12/pr10-review/sources/tests/tb_platform_bresp.sv:52: $finish called at 420000 (1ps) diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/board-unit/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/board-unit/RESULT.json new file mode 100644 index 0000000..6308a3a --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/board-unit/RESULT.json @@ -0,0 +1,20 @@ +{ + "result": "PASS", + "tests": 4, + "physical_mig_simulated": false, + "sources": { + "board/loader_axi.sv": "05609b0870054ea675aedb406f6215cd456f18db6d6428b461cbae03d9a662f4", + "board/flash_spi_byte.sv": "4d1fac5238f31fb3a69a58d1aca9ccec722e833d788113b94d86c6a1b861045a", + "board/uart_rx.sv": "0b35263884577324f146ff7fd516e5b561dcc8787e0d8ad599669bac1958406d", + "board/toy_a7_top.sv": "c8af97f543b8ae5d6dc21a85ba13b16a28fe3ba5bf93f8051c9e38c99f3350bd", + "board/ddr_uart_loader.sv": "980f4cd2e3fa2a00b66143f879bc749ed952c2c1e54331460821bac0300c43d6", + "board/axi_scu.sv": "ee77bf641d61811b4c1faea845752850c22461a63b4cdfd3d6f9cd223e6c2fc2", + "board/toy_a7_platform.sv": "f9bc06535b7de19a6b1b501f06effe90519fd43a78e669ab7425d301662540b8", + "board/axi_fullwidth.sv": "bf07ae27724dbd0a361d732dfb57109f06beef207c47a066d400cb06d7f07d5a", + "board/uart_tx.sv": "c20d420fc20be4f6313bdde5abc45ef0b9f8e93bf75350dd9951bc8868b3b65c", + "tests/tb_axi_fullwidth.sv": "1d3964fab0eaa76a6f864f07a7dedf01639ba12a9400a15d0839e707ab73c4ed", + "tests/tb_axi_scu.sv": "5dfd1d6cac3201f0e5188e9b73e60ade27c4551570d4b00d387301713d9fbe97", + "tests/ToyLinuxChipPorts.sv": "e4c06220cd7025972d432b06c452e85c62bd2cfccad618b2b993499b62e6621a", + "tests/tb_platform_bresp.sv": "289875c2e92800307aa0b7fc5186c946ba127835473b30f626aef7baa67b4fe8" + } +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/board-unit/tb_axi_fullwidth-compile.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/board-unit/tb_axi_fullwidth-compile.log new file mode 100644 index 0000000..e69de29 diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/board-unit/tb_axi_fullwidth.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/board-unit/tb_axi_fullwidth.log new file mode 100644 index 0000000..c44090b --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/board-unit/tb_axi_fullwidth.log @@ -0,0 +1,2 @@ +PASS fullwidth AXI: sizes 8..128 bits, INCR/FIXED, strobes, concurrent R/W, stalls, IDs, range/4KiB rejection; read beats=90 +/home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/tests/tb_axi_fullwidth.sv:107: $finish called at 9270000 (1ps) diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/board-unit/tb_axi_scu-compile.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/board-unit/tb_axi_scu-compile.log new file mode 100644 index 0000000..e69de29 diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/board-unit/tb_axi_scu.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/board-unit/tb_axi_scu.log new file mode 100644 index 0000000..6b18e86 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/board-unit/tb_axi_scu.log @@ -0,0 +1,2 @@ +PASS SCU OpenSBI byte addresses, AXI lanes, RX pop/IRQ, TX backpressure, EXIT +/home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/tests/tb_axi_scu.sv:64: $finish called at 20580000 (1ps) diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/board-unit/tb_ddr_loader-compile.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/board-unit/tb_ddr_loader-compile.log new file mode 100644 index 0000000..e69de29 diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/board-unit/tb_ddr_loader.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/board-unit/tb_ddr_loader.log new file mode 100644 index 0000000..1c6a004 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/board-unit/tb_ddr_loader.log @@ -0,0 +1,2 @@ +PASS: DDR UART loader CRC, 256-byte unaligned RAM roundtrip, rejected writes/RUN, timeout and boot +/home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/build/board-unit/tb_ddr_loader.sv:116: $finish called at 78290000 (1ps) diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/board-unit/tb_platform_bresp-compile.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/board-unit/tb_platform_bresp-compile.log new file mode 100644 index 0000000..e69de29 diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/board-unit/tb_platform_bresp.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/board-unit/tb_platform_bresp.log new file mode 100644 index 0000000..c0a4227 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/board-unit/tb_platform_bresp.log @@ -0,0 +1,2 @@ +PASS platform AXI B response: valid, invalid address, unaligned, burst, ID and backpressure +/home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/tests/tb_platform_bresp.sv:55: $finish called at 420000 (1ps) diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/flash-guard-check/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/flash-guard-check/RESULT.json new file mode 100644 index 0000000..f236658 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/flash-guard-check/RESULT.json @@ -0,0 +1,56 @@ +{ + "result": "PASS_FLASH_GUARDS_NORMAL_AND_OPTIMIZED", + "physical_hardware_tested": false, + "cases": [ + { + "optimized": false, + "field": "valid", + "result": "PASS" + }, + { + "optimized": false, + "field": "result", + "result": "PASS" + }, + { + "optimized": false, + "field": "bitstream_sha256", + "result": "PASS" + }, + { + "optimized": false, + "field": "packed_payload_sha256", + "result": "PASS" + }, + { + "optimized": false, + "field": "flash_image_sha256", + "result": "PASS" + }, + { + "optimized": true, + "field": "valid", + "result": "PASS" + }, + { + "optimized": true, + "field": "result", + "result": "PASS" + }, + { + "optimized": true, + "field": "bitstream_sha256", + "result": "PASS" + }, + { + "optimized": true, + "field": "packed_payload_sha256", + "result": "PASS" + }, + { + "optimized": true, + "field": "flash_image_sha256", + "result": "PASS" + } + ] +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/flash-guard-check/normal-bitstream_sha256.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/flash-guard-check/normal-bitstream_sha256.log new file mode 100644 index 0000000..743e348 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/flash-guard-check/normal-bitstream_sha256.log @@ -0,0 +1 @@ +PASS INVALID_IMAGE_BLOCKED Prepacked flash image bitstream hash mismatch diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/flash-guard-check/normal-flash_image_sha256.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/flash-guard-check/normal-flash_image_sha256.log new file mode 100644 index 0000000..ffaee7b --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/flash-guard-check/normal-flash_image_sha256.log @@ -0,0 +1 @@ +PASS INVALID_IMAGE_BLOCKED Prepacked flash image MCS hash mismatch diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/flash-guard-check/normal-packed_payload_sha256.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/flash-guard-check/normal-packed_payload_sha256.log new file mode 100644 index 0000000..7f5ad62 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/flash-guard-check/normal-packed_payload_sha256.log @@ -0,0 +1 @@ +PASS INVALID_IMAGE_BLOCKED Prepacked flash image payload hash mismatch diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/flash-guard-check/normal-result.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/flash-guard-check/normal-result.log new file mode 100644 index 0000000..c80dd16 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/flash-guard-check/normal-result.log @@ -0,0 +1 @@ +PASS INVALID_IMAGE_BLOCKED Prepacked flash image record did not pass packing diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/flash-guard-check/normal-valid.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/flash-guard-check/normal-valid.log new file mode 100644 index 0000000..3ace83b --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/flash-guard-check/normal-valid.log @@ -0,0 +1,32 @@ +USING_PREPACKED_FLASH_IMAGE bb7752b500cc85074635eb43d325bb3d1fdb575a8b76a6f8b77248923ce55774 +{ + "status": "FAILED", + "timeout_seconds": 3600, + "bitstream_sha256": "7bf8e955913c442ddd945fafdcc42d2a593f2e19477288bd98cc008062369335", + "packed_payload_sha256": "57312732d5af9cb3785067f8032a41a0c3d023b8ebe0a6a8cde1c1dff99714ff", + "part": "mt25ql128-spi-x1_x2_x4", + "port": "OFFLINE_NO_DEVICE", + "started_at": "2026-10-13T00:27:13.535617+08:00", + "commands": [ + null, + [ + "OFFLINE_NO_VIVADO", + "-mode", + "batch", + "-source", + "/home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/board/program_flash.tcl", + "-log", + "/home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/build/flash-guard-check/tmpigofq8q1/run/program.log", + "-journal", + "/home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/build/flash-guard-check/tmpigofq8q1/run/program.jou", + "-tclargs", + "/home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/build/flash-guard-check/tmpigofq8q1/run/toy_flash.mcs", + "mt25ql128-spi-x1_x2_x4", + "/home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/build/flash-guard-check/tmpigofq8q1/run/flash-before.bin" + ] + ], + "error": "Guard accepted the valid image", + "elapsed_seconds": 0.0, + "finished_at": "2026-10-13T00:27:13.535761+08:00" +} +PASS VALID_IMAGE_REACHED_OFFLINE_BOUNDARY diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/flash-guard-check/optimized-bitstream_sha256.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/flash-guard-check/optimized-bitstream_sha256.log new file mode 100644 index 0000000..743e348 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/flash-guard-check/optimized-bitstream_sha256.log @@ -0,0 +1 @@ +PASS INVALID_IMAGE_BLOCKED Prepacked flash image bitstream hash mismatch diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/flash-guard-check/optimized-flash_image_sha256.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/flash-guard-check/optimized-flash_image_sha256.log new file mode 100644 index 0000000..ffaee7b --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/flash-guard-check/optimized-flash_image_sha256.log @@ -0,0 +1 @@ +PASS INVALID_IMAGE_BLOCKED Prepacked flash image MCS hash mismatch diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/flash-guard-check/optimized-packed_payload_sha256.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/flash-guard-check/optimized-packed_payload_sha256.log new file mode 100644 index 0000000..7f5ad62 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/flash-guard-check/optimized-packed_payload_sha256.log @@ -0,0 +1 @@ +PASS INVALID_IMAGE_BLOCKED Prepacked flash image payload hash mismatch diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/flash-guard-check/optimized-result.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/flash-guard-check/optimized-result.log new file mode 100644 index 0000000..c80dd16 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/flash-guard-check/optimized-result.log @@ -0,0 +1 @@ +PASS INVALID_IMAGE_BLOCKED Prepacked flash image record did not pass packing diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/flash-guard-check/optimized-valid.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/flash-guard-check/optimized-valid.log new file mode 100644 index 0000000..8074a0c --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/flash-guard-check/optimized-valid.log @@ -0,0 +1,32 @@ +USING_PREPACKED_FLASH_IMAGE bb7752b500cc85074635eb43d325bb3d1fdb575a8b76a6f8b77248923ce55774 +{ + "status": "FAILED", + "timeout_seconds": 3600, + "bitstream_sha256": "7bf8e955913c442ddd945fafdcc42d2a593f2e19477288bd98cc008062369335", + "packed_payload_sha256": "57312732d5af9cb3785067f8032a41a0c3d023b8ebe0a6a8cde1c1dff99714ff", + "part": "mt25ql128-spi-x1_x2_x4", + "port": "OFFLINE_NO_DEVICE", + "started_at": "2026-10-13T00:27:13.924036+08:00", + "commands": [ + null, + [ + "OFFLINE_NO_VIVADO", + "-mode", + "batch", + "-source", + "/home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/board/program_flash.tcl", + "-log", + "/home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/build/flash-guard-check/tmpgcvju9tp/run/program.log", + "-journal", + "/home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/build/flash-guard-check/tmpgcvju9tp/run/program.jou", + "-tclargs", + "/home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/build/flash-guard-check/tmpgcvju9tp/run/toy_flash.mcs", + "mt25ql128-spi-x1_x2_x4", + "/home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/build/flash-guard-check/tmpgcvju9tp/run/flash-before.bin" + ] + ], + "error": "Guard accepted the valid image", + "elapsed_seconds": 0.0, + "finished_at": "2026-10-13T00:27:13.924173+08:00" +} +PASS VALID_IMAGE_REACHED_OFFLINE_BOUNDARY diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/RESULT.json new file mode 100644 index 0000000..aeac5b4 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/RESULT.json @@ -0,0 +1,106 @@ +{ + "result": "PASS_OFFLINE_TCL_CONTRACTS", + "physical_hardware_tested": false, + "cases": [ + { + "script": "program_arty.tcl", + "fault": "none", + "result": "PASS" + }, + { + "script": "program_arty.tcl", + "fault": "device_error", + "result": "PASS" + }, + { + "script": "program_arty.tcl", + "fault": "done_low", + "result": "PASS" + }, + { + "script": "program_arty.tcl", + "fault": "eos_low", + "result": "PASS" + }, + { + "script": "program_arty.tcl", + "fault": "crc_error", + "result": "PASS" + }, + { + "script": "backup_flash.tcl", + "fault": "none", + "result": "PASS" + }, + { + "script": "backup_flash.tcl", + "fault": "device_error", + "result": "PASS" + }, + { + "script": "backup_flash.tcl", + "fault": "done_low", + "result": "PASS" + }, + { + "script": "backup_flash.tcl", + "fault": "eos_low", + "result": "PASS" + }, + { + "script": "backup_flash.tcl", + "fault": "crc_error", + "result": "PASS" + }, + { + "script": "backup_flash.tcl", + "fault": "readback_error", + "result": "PASS" + }, + { + "script": "backup_flash.tcl", + "fault": "short_backup", + "result": "PASS" + }, + { + "script": "program_flash.tcl", + "fault": "none", + "result": "PASS" + }, + { + "script": "program_flash.tcl", + "fault": "device_error", + "result": "PASS" + }, + { + "script": "program_flash.tcl", + "fault": "done_low", + "result": "PASS" + }, + { + "script": "program_flash.tcl", + "fault": "eos_low", + "result": "PASS" + }, + { + "script": "program_flash.tcl", + "fault": "crc_error", + "result": "PASS" + }, + { + "script": "program_flash.tcl", + "fault": "readback_error", + "result": "PASS" + }, + { + "script": "program_flash.tcl", + "fault": "short_backup", + "result": "PASS" + }, + { + "script": "program_flash.tcl", + "fault": "cfgmem_error", + "result": "PASS" + } + ] +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/backup_flash.tcl-crc_error.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/backup_flash.tcl-crc_error.log new file mode 100644 index 0000000..fca1bae --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/backup_flash.tcl-crc_error.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device +MOCK_FAILURE SPI bridge configuration status rejected diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/backup_flash.tcl-device_error.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/backup_flash.tcl-device_error.log new file mode 100644 index 0000000..30ac2d8 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/backup_flash.tcl-device_error.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device +MOCK_FAILURE SPI bridge programming failed: injected programming exception diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/backup_flash.tcl-done_low.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/backup_flash.tcl-done_low.log new file mode 100644 index 0000000..fca1bae --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/backup_flash.tcl-done_low.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device +MOCK_FAILURE SPI bridge configuration status rejected diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/backup_flash.tcl-eos_low.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/backup_flash.tcl-eos_low.log new file mode 100644 index 0000000..fca1bae --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/backup_flash.tcl-eos_low.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device +MOCK_FAILURE SPI bridge configuration status rejected diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/backup_flash.tcl-none.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/backup_flash.tcl-none.log new file mode 100644 index 0000000..662f9ed --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/backup_flash.tcl-none.log @@ -0,0 +1,3 @@ +PASS FLASH_BACKUP: mt25ql128-spi-x1_x2_x4 /home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/build/programming-check/tmp9zli3jr_/backup.bin bytes=16777216 +MOCK_EVENTS program_device readback +MOCK_SUCCESS diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/backup_flash.tcl-readback_error.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/backup_flash.tcl-readback_error.log new file mode 100644 index 0000000..450c391 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/backup_flash.tcl-readback_error.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device readback +MOCK_FAILURE Flash readback failed: injected readback exception diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/backup_flash.tcl-short_backup.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/backup_flash.tcl-short_backup.log new file mode 100644 index 0000000..20502f0 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/backup_flash.tcl-short_backup.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device readback +MOCK_FAILURE Incomplete Flash backup diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/program_arty.tcl-crc_error.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/program_arty.tcl-crc_error.log new file mode 100644 index 0000000..728e8ba --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/program_arty.tcl-crc_error.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device +MOCK_FAILURE JTAG configuration status rejected: expected DONE/EOS high and CRC error clear diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/program_arty.tcl-device_error.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/program_arty.tcl-device_error.log new file mode 100644 index 0000000..a98384b --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/program_arty.tcl-device_error.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device +MOCK_FAILURE JTAG programming failed: injected programming exception diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/program_arty.tcl-done_low.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/program_arty.tcl-done_low.log new file mode 100644 index 0000000..728e8ba --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/program_arty.tcl-done_low.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device +MOCK_FAILURE JTAG configuration status rejected: expected DONE/EOS high and CRC error clear diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/program_arty.tcl-eos_low.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/program_arty.tcl-eos_low.log new file mode 100644 index 0000000..728e8ba --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/program_arty.tcl-eos_low.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device +MOCK_FAILURE JTAG configuration status rejected: expected DONE/EOS high and CRC error clear diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/program_arty.tcl-none.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/program_arty.tcl-none.log new file mode 100644 index 0000000..6309c42 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/program_arty.tcl-none.log @@ -0,0 +1,3 @@ +ARTY_JTAG_PROGRAMMED: /home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/build/programming-check/tmp45o_w1im/input.bit +MOCK_EVENTS program_device +MOCK_SUCCESS diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/program_flash.tcl-cfgmem_error.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/program_flash.tcl-cfgmem_error.log new file mode 100644 index 0000000..e3cd38f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/program_flash.tcl-cfgmem_error.log @@ -0,0 +1,3 @@ +PASS FLASH_BACKUP: /home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/build/programming-check/tmp7qvxfh88/backup.bin bytes=16777216 +MOCK_EVENTS program_device readback program_flash +MOCK_FAILURE Flash program/verify failed: injected Flash verify exception diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/program_flash.tcl-crc_error.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/program_flash.tcl-crc_error.log new file mode 100644 index 0000000..e18af32 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/program_flash.tcl-crc_error.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device +MOCK_FAILURE SPI bridge configuration status rejected; Flash programming cancelled diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/program_flash.tcl-device_error.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/program_flash.tcl-device_error.log new file mode 100644 index 0000000..30ac2d8 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/program_flash.tcl-device_error.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device +MOCK_FAILURE SPI bridge programming failed: injected programming exception diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/program_flash.tcl-done_low.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/program_flash.tcl-done_low.log new file mode 100644 index 0000000..e18af32 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/program_flash.tcl-done_low.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device +MOCK_FAILURE SPI bridge configuration status rejected; Flash programming cancelled diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/program_flash.tcl-eos_low.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/program_flash.tcl-eos_low.log new file mode 100644 index 0000000..e18af32 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/program_flash.tcl-eos_low.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device +MOCK_FAILURE SPI bridge configuration status rejected; Flash programming cancelled diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/program_flash.tcl-none.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/program_flash.tcl-none.log new file mode 100644 index 0000000..b9c8b15 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/program_flash.tcl-none.log @@ -0,0 +1,5 @@ +PASS FLASH_BACKUP: /home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/build/programming-check/tmpm886wmbp/backup.bin bytes=16777216 +PASS FLASH_PROGRAM_VERIFY: mt25ql128-spi-x1_x2_x4 /home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/build/programming-check/tmpm886wmbp/input.bit +FLASH_BOOT_CONFIG_STATUS DONE=1 EOS=1 CRC=0 +MOCK_EVENTS program_device readback program_flash boot +MOCK_SUCCESS diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/program_flash.tcl-readback_error.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/program_flash.tcl-readback_error.log new file mode 100644 index 0000000..8cc9ec4 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/program_flash.tcl-readback_error.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device readback +MOCK_FAILURE Flash backup failed; programming cancelled: injected readback exception diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/program_flash.tcl-short_backup.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/program_flash.tcl-short_backup.log new file mode 100644 index 0000000..2541aca --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/programming-check/program_flash.tcl-short_backup.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device readback +MOCK_FAILURE Incomplete backup; programming cancelled diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/runner-status-check/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/runner-status-check/RESULT.json new file mode 100644 index 0000000..487476f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/runner-status-check/RESULT.json @@ -0,0 +1,28 @@ +{ + "result": "PASS_RUNNER_FAILURE_STATUS", + "baseline_ref": null, + "physical_hardware_tested": false, + "cases": [ + { + "script": "check_board.py", + "source_sha256": "2c6cb06f301bfc4b98f66d21e5f34d7627a73b490ee60e385185bfaf2377711b", + "exit_code": 1, + "observed_result": "FAILED", + "result": "PASS" + }, + { + "script": "check_programming_scripts.py", + "source_sha256": "8bd486cc7b0dbb960984a6dadc1bd97eb5a2b393abbe55e9d99077817dbc02a5", + "exit_code": 1, + "observed_result": "FAILED", + "result": "PASS" + }, + { + "script": "check_flash_guards.py", + "source_sha256": "76bba3666d73a87aa698fa714933244f59dbdaa2260cb742462ad71505a10a5b", + "exit_code": 1, + "observed_result": "FAILED", + "result": "PASS" + } + ] +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/runner-status-check/check_board.py.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/runner-status-check/check_board.py.log new file mode 100644 index 0000000..1aa5eba --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/runner-status-check/check_board.py.log @@ -0,0 +1,10 @@ +Traceback (most recent call last): + File "/home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/build/runner-status-check/tmpji_mwrjk/scripts/check_board.py", line 77, in + run_check(main, OUT) + File "/home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/build/runner-status-check/tmpji_mwrjk/scripts/offline_check.py", line 19, in run_check + main() + File "/home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/build/runner-status-check/tmpji_mwrjk/scripts/check_board.py", line 28, in main + raise ValueError("CPU port fixture differs from its manifest") +ValueError: CPU port fixture differs from its manifest + +OBSERVED_RESULT {"result": "FAILED", "physical_hardware_tested": false, "error_type": "ValueError", "error": "CPU port fixture differs from its manifest"} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/runner-status-check/check_flash_guards.py.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/runner-status-check/check_flash_guards.py.log new file mode 100644 index 0000000..2033544 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/runner-status-check/check_flash_guards.py.log @@ -0,0 +1,12 @@ +Traceback (most recent call last): + File "/home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/build/runner-status-check/tmp66aiuusz/scripts/check_flash_guards.py", line 48, in + run_check(main, ROOT / "build/flash-guard-check") + File "/home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/build/runner-status-check/tmp66aiuusz/scripts/offline_check.py", line 19, in run_check + main() + File "/home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/build/runner-status-check/tmp66aiuusz/scripts/check_flash_guards.py", line 38, in main + result.check_returncode() + File "/usr/lib/python3.12/subprocess.py", line 502, in check_returncode + raise CalledProcessError(self.returncode, self.args, self.stdout, +subprocess.CalledProcessError: Command '['/usr/bin/python3', '/home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/build/runner-status-check/tmp66aiuusz/tests/flash_guard_probe.py', '/home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/build/runner-status-check/tmp66aiuusz/host/flash.py', '/home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/build/runner-status-check/tmp66aiuusz/build/flash-guard-check/tmpmivdvd_6/chip.bit', '/home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/build/runner-status-check/tmp66aiuusz/build/flash-guard-check/tmpmivdvd_6/payload.bin', '/home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/build/runner-status-check/tmp66aiuusz/build/flash-guard-check/tmpmivdvd_6/image.mcs', '/home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/build/runner-status-check/tmp66aiuusz/build/flash-guard-check/tmpmivdvd_6/run', 'accept']' returned non-zero exit status 1. + +OBSERVED_RESULT {"result": "FAILED", "physical_hardware_tested": false, "error_type": "CalledProcessError", "error": "Command '['/usr/bin/python3', '/home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/build/runner-status-check/tmp66aiuusz/tests/flash_guard_probe.py', '/home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/build/runner-status-check/tmp66aiuusz/host/flash.py', '/home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/build/runner-status-check/tmp66aiuusz/build/flash-guard-check/tmpmivdvd_6/chip.bit', '/home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/build/runner-status-check/tmp66aiuusz/build/flash-guard-check/tmpmivdvd_6/payload.bin', '/home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/build/runner-status-check/tmp66aiuusz/build/flash-guard-check/tmpmivdvd_6/image.mcs', '/home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/build/runner-status-check/tmp66aiuusz/build/flash-guard-check/tmpmivdvd_6/run', 'accept']' returned non-zero exit status 1."} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/runner-status-check/check_programming_scripts.py.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/runner-status-check/check_programming_scripts.py.log new file mode 100644 index 0000000..9dd679d --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/runner-status-check/check_programming_scripts.py.log @@ -0,0 +1,14 @@ +Traceback (most recent call last): + File "/home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/build/runner-status-check/tmp7hs1muus/scripts/check_programming_scripts.py", line 57, in + run_check(main, ROOT / "build/programming-check") + File "/home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/build/runner-status-check/tmp7hs1muus/scripts/offline_check.py", line 19, in run_check + main() + File "/home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/build/runner-status-check/tmp7hs1muus/scripts/check_programming_scripts.py", line 41, in main + raise ValueError(f"Documented success return rejected: {script}: {transcript}") +ValueError: Documented success return rejected: program_arty.tcl: Traceback (most recent call last): + File "/home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/build/runner-status-check/tmp7hs1muus/tests/mock_programming.tcl", line 1, in + raise RuntimeError('INJECTED_CHECK_FAILURE') +RuntimeError: INJECTED_CHECK_FAILURE + + +OBSERVED_RESULT {"result": "FAILED", "physical_hardware_tested": false, "error_type": "ValueError", "error": "Documented success return rejected: program_arty.tcl: Traceback (most recent call last):\n File \"/home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/build/runner-status-check/tmp7hs1muus/tests/mock_programming.tcl\", line 1, in \n raise RuntimeError('INJECTED_CHECK_FAILURE')\nRuntimeError: INJECTED_CHECK_FAILURE\n"} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/session.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/session.log new file mode 100644 index 0000000..10addc2 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/session.log @@ -0,0 +1,12 @@ +PASS fullwidth AXI: sizes 8..128 bits, INCR/FIXED, strobes, concurrent R/W, stalls, IDs, range/4KiB rejection; read beats=90 +/home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/tests/tb_axi_fullwidth.sv:107: $finish called at 9270000 (1ps) +PASS SCU OpenSBI byte addresses, AXI lanes, RX pop/IRQ, TX backpressure, EXIT +/home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/tests/tb_axi_scu.sv:64: $finish called at 20580000 (1ps) +PASS platform AXI B response: valid, invalid address, unaligned, burst, ID and backpressure +/home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/tests/tb_platform_bresp.sv:55: $finish called at 420000 (1ps) +PASS: DDR UART loader CRC, 256-byte unaligned RAM roundtrip, rejected writes/RUN, timeout and boot +/home/yys/codex-builds/arty-a7-pr10-selfcheck-20261013-d044483d/build/board-unit/tb_ddr_loader.sv:116: $finish called at 78290000 (1ps) +PASS programming scripts: 20 documented-return/status/error cases; no hardware +PASS Flash image guards: 10 normal/-O tamper/control cases; no hardware +PASS runner failure status: 3 actual entrypoints; baseline=current +PASS mutation oracles: old test misses premature BVALID drop; new test rejects it and old response bug diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/board/axi_fullwidth.sv b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/board/axi_fullwidth.sv new file mode 100644 index 0000000..a17053c --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/board/axi_fullwidth.sv @@ -0,0 +1,115 @@ +// Serialize each INCR/FIXED AXI beat into an aligned 128-bit MIG transaction. +// Lane positions/strobes and IDs are preserved. Narrow reads may overfetch DDR +// bytes but never MMIO. One read and one write burst can progress independently. +module axi_fullwidth ( + input wire clk, reset, + input wire [3:0] s_awid, s_arid, + input wire [31:0] s_awaddr, s_araddr, + input wire [7:0] s_awlen, s_arlen, + input wire [2:0] s_awsize, s_arsize, + input wire [1:0] s_awburst, s_arburst, + input wire s_awvalid, s_arvalid, s_wvalid, s_wlast, s_bready, s_rready, + output wire s_awready, s_arready, s_wready, + input wire [127:0] s_wdata, input wire [15:0] s_wstrb, + output reg [3:0] s_bid, s_rid, + output reg [1:0] s_bresp, s_rresp, + output reg s_bvalid, s_rvalid, s_rlast, output reg [127:0] s_rdata, + output wire [3:0] m_awid, m_arid, + output wire [27:0] m_awaddr, m_araddr, + output wire [7:0] m_awlen, m_arlen, + output wire [2:0] m_awsize, m_arsize, + output wire [1:0] m_awburst, m_arburst, + output wire m_awvalid, m_arvalid, m_wvalid, m_wlast, m_bready, m_rready, + input wire m_awready, m_arready, m_wready, + output wire [127:0] m_wdata, output wire [15:0] m_wstrb, + input wire [3:0] m_bid, m_rid, + input wire [1:0] m_bresp, m_rresp, + input wire m_bvalid, m_rvalid, m_rlast, input wire [127:0] m_rdata +); + localparam W_IDLE=0, W_DATA=1, W_SEND=2, W_RESP=3; + localparam R_IDLE=0, R_SEND=1, R_RESP=2, R_RETURN=3; + reg [1:0] ws, rs; + reg [31:0] wa, ra; + reg [7:0] wl, rl; + reg [2:0] wz, rz; + reg wi, ri, wbad, rbad, aw_sent, w_sent; + reg [127:0] wd; + reg [15:0] wm; + wire [32:0] wend = {1'b0,s_awaddr} + ({25'd0,s_awlen} << s_awsize); + wire [32:0] rend = {1'b0,s_araddr} + ({25'd0,s_arlen} << s_arsize); + wire wlegal = s_awaddr[31:28]==4'h8 && s_awsize<=4 && s_awburst<=1 && + (s_awaddr & ((32'd1<3 || awburst>1 || + (awaddr & ((31'd1<3 || arburst>1 || (araddr & ((31'd1<=3) rdata[47:40]<={5'd0,framing,overflow,count!=0}; + end else rresp<=2; + end + if(push) begin fifo[wp]<=rx_data;wp<=wp+1'b1;end + if(pop) rp<=rp+1'b1; + case({push,pop}) + 2'b10:count<=count+1'b1; + 2'b01:count<=count-1'b1; + default:count<=count; + endcase + if(rx_valid && !push) overflow<=1; + if(rx_error) framing<=1; + end + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/board/ddr_uart_loader.sv b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/board/ddr_uart_loader.sv new file mode 100644 index 0000000..9aa2dc9 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/board/ddr_uart_loader.sv @@ -0,0 +1,169 @@ +// Stop-and-wait serial boot protocol. Requests: A5 5A op seq addrLE32 lenLE16 +// [WRITE payload] crcLE16. CRC-16/CCITT-FALSE covers op through payload. +// Responses: 5A A5 (op|80) seq status lenLE16 [data] crcLE16. +// CRC is checked before any DDR write; CPU starts after the RUN reply drains. +module ddr_uart_loader #( + parameter integer RAM_BYTES = 268435456, + parameter integer CLOCK_HZ = 25000000, + parameter integer RX_TIMEOUT = CLOCK_HZ/10 +) ( + input wire clk, reset, + input wire rx_valid, input wire [7:0] rx_data, input wire rx_error, + output wire tx_valid, output reg [7:0] tx_data, input wire tx_ready, + output reg cpu_run, output reg error_seen, + output wire load_en, + output wire [$clog2(RAM_BYTES)-1:0] load_addr, + output reg [127:0] load_data, + output reg [15:0] load_mask, + input wire load_valid, load_error, input wire [127:0] load_result +); + localparam [3:0] SYNC0=0,SYNC1=1,HEADER=2,PAYLOAD=3,CRC0=4,CRC1=5, + EXECUTE=6,WRITE=7,READ_REQ=8,READ_WAIT=9,REPLY=10,DRAIN=11; + reg [3:0] state; + reg [7:0] operation, sequence_id, status; + reg [31:0] address; + reg [15:0] length, reply_length, crc, received_crc; + reg [8:0] cursor, reply_index; + reg [3:0] header_index; + (* ram_style="distributed" *) reg [7:0] payload [0:255]; + reg pending_run, image_loaded; + reg [$clog2(RX_TIMEOUT+1)-1:0] timeout_count; + wire receiving = state==SYNC1 || state==HEADER || state==PAYLOAD || state==CRC0 || state==CRC1; + wire [32:0] end_address = {1'b0,address}+length; + wire valid_range = length!=0 && length<=256 && address>=32'h80000000 && + end_address<=33'h080000000+RAM_BYTES; + wire [31:0] byte_address = address + cursor; + assign load_addr = byte_address[$clog2(RAM_BYTES)-1:0]; + assign load_en = !cpu_run && (state==WRITE || state==READ_REQ); + always @* begin + load_data=0;load_mask=0; + if(state==WRITE) begin + load_data[byte_address[3:0]*8 +: 8]=payload[cursor[7:0]]; + load_mask=16'b1<> ((reply_index-11)*8); + 15,16,17,18:tx_data=CLOCK_HZ >> ((reply_index-15)*8); + default:tx_data=0; + endcase + else tx_data=payload[(reply_index-7) & 255]; + end + else if(reply_index==7+reply_length) tx_data=crc[7:0]; + else tx_data=crc[15:8]; + end + endcase + end + always @(posedge clk) begin + if(reset) begin + state<=SYNC0;cpu_run<=0;error_seen<=0;image_loaded<=0;pending_run<=0; + operation<=0;sequence_id<=0;status<=0;address<=0;length<=0; + reply_length<=0;crc<=16'hffff;received_crc<=0;cursor<=0; + reply_index<=0;header_index<=0;timeout_count<=0; + end else if(!cpu_run) begin + if(!receiving || rx_valid) timeout_count<=0; + else timeout_count<=timeout_count+1'b1; + if((receiving && timeout_count==RX_TIMEOUT-1) || (receiving && rx_error)) begin + state<=SYNC0;error_seen<=1;timeout_count<=0; + end else case(state) + SYNC0: if(rx_valid && rx_data==8'ha5) state<=SYNC1; + SYNC1: if(rx_valid) begin + if(rx_data==8'h5a) begin + state<=HEADER;header_index<=0;crc<=16'hffff;length<=0;address<=0; + pending_run<=0;reply_index<=0;reply_length<=0;status<=0; + end else if(rx_data!=8'ha5) state<=SYNC0; + end + HEADER: if(rx_valid) begin + crc<=crc_next(crc,rx_data); + case(header_index) + 0:operation<=rx_data; + 1:sequence_id<=rx_data; + 2:address[7:0]<=rx_data; + 3:address[15:8]<=rx_data; + 4:address[23:16]<=rx_data; + 5:address[31:24]<=rx_data; + 6:length[7:0]<=rx_data; + 7:begin + length[15:8]<=rx_data;cursor<=0; + if({rx_data,length[7:0]}>256) begin state<=SYNC0;error_seen<=1;end + else if(operation==1 && {rx_data,length[7:0]}!=0) state<=PAYLOAD; + else state<=CRC0; + end + endcase + header_index<=header_index+1'b1; + end + PAYLOAD: if(rx_valid) begin + payload[cursor[7:0]]<=rx_data;crc<=crc_next(crc,rx_data); + cursor<=cursor+1'b1; + if(cursor+1==length) state<=CRC0; + end + CRC0: if(rx_valid) begin received_crc[7:0]<=rx_data;state<=CRC1;end + CRC1: if(rx_valid) begin + cursor<=0; + if({rx_data,received_crc[7:0]}!=crc) begin + status<=1;error_seen<=1;crc<=16'hffff;state<=REPLY; + end else state<=EXECUTE; + end + EXECUTE: begin + crc<=16'hffff; + if(operation==1 || operation==2) begin + if(!valid_range) begin status<=2;error_seen<=1;state<=REPLY;end + else if(operation==1) state<=WRITE; + else begin reply_length<=length;state<=READ_REQ;end + end else if(operation==3 && length==0 && address==32'h80000000) begin + if(!image_loaded) begin status<=5;error_seen<=1;end + else pending_run<=1; + state<=REPLY; + end else if(operation==4 && length==0 && address==0) begin + reply_length<=12;state<=REPLY; + end else begin status<=3;error_seen<=1;state<=REPLY;end + end + WRITE: if(load_valid) begin + if(load_error) begin status<=6;error_seen<=1;state<=REPLY;end + else if(cursor+1==length) begin image_loaded<=1;state<=REPLY;end + else cursor<=cursor+1'b1; + end + READ_REQ: state<=READ_WAIT; + READ_WAIT: if(load_valid) begin + if(load_error) begin status<=6;error_seen<=1;reply_length<=0;state<=REPLY;end + else begin + payload[cursor[7:0]]<=load_result[byte_address[3:0]*8 +: 8]; + if(cursor+1==length) state<=REPLY; + else begin cursor<=cursor+1'b1;state<=READ_REQ;end + end + end + REPLY: if(tx_ready) begin + if(reply_index>=2 && reply_index<7+reply_length) crc<=crc_next(crc,tx_data); + if(reply_index==8+reply_length) state<=DRAIN; + else reply_index<=reply_index+1'b1; + end + DRAIN: if(tx_ready) begin + if(pending_run) cpu_run<=1; + state<=SYNC0; + end + default:state<=SYNC0; + endcase + end + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/board/flash_spi_byte.sv b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/board/flash_spi_byte.sv new file mode 100644 index 0000000..1610a12 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/board/flash_spi_byte.sv @@ -0,0 +1,33 @@ +// Read-only boot software uses this mode-0 byte engine; no Flash writes in RTL. +// 25 MHz / (2 * 4) = 3.125 MHz. Two MISO synchronizers settle within a half bit. +module flash_spi_byte ( + input wire clk, reset, start, + input wire [7:0] tx_data, + input wire miso, + output reg busy, sck, + output wire mosi, + output reg [7:0] rx_data +); + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg miso_meta, miso_sync; + reg [7:0] shift_tx, shift_rx; + reg [2:0] bit_count; + reg [1:0] divider; + assign mosi=shift_tx[7]; + always @(posedge clk) begin + miso_meta<=miso;miso_sync<=miso_meta; + if(reset) begin + busy<=0;sck<=0;shift_tx<=0;shift_rx<=0;rx_data<=0;bit_count<=0;divider<=0; + end else if(!busy) begin + sck<=0; + if(start) begin busy<=1;shift_tx<=tx_data;shift_rx<=0;bit_count<=0;divider<=0;end + end else if(divider==3) begin + divider<=0;sck<=!sck; + if(!sck) shift_rx<={shift_rx[6:0],miso_sync}; + else begin + shift_tx<={shift_tx[6:0],1'b1}; + if(bit_count==7) begin busy<=0;rx_data<=shift_rx;end + else bit_count<=bit_count+1'b1; + end + end else divider<=divider+1'b1; + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/board/loader_axi.sv b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/board/loader_axi.sv new file mode 100644 index 0000000..096ddb0 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/board/loader_axi.sv @@ -0,0 +1,53 @@ +// Convert a held loader byte request into a completed AXI transaction. +// The loader advances only after B/R. A RELEASE cycle prevents resubmission +// while its synchronous state machine consumes the acknowledgement. +module loader_axi ( + input wire clk, reset, load_en, + input wire [27:0] load_addr, + input wire [127:0] load_data, input wire [15:0] load_mask, + output reg load_valid, load_error, output reg [127:0] load_result, + output wire [27:0] awaddr, araddr, + output wire awvalid, wvalid, arvalid, bready, rready, + input wire awready, wready, arready, bvalid, rvalid, + output wire [127:0] wdata, output wire [15:0] wstrb, + input wire [1:0] bresp, rresp, input wire [127:0] rdata +); + localparam IDLE=0, SEND_W=1, WAIT_B=2, SEND_R=3, WAIT_R=4, RELEASE=5; + reg [2:0] state; + reg [27:0] addr; + reg [127:0] data; + reg [15:0] mask; + reg sent_aw, sent_w; + assign awaddr=addr;assign araddr=addr; + assign wdata=data;assign wstrb=mask; + assign awvalid=!reset && state==SEND_W && !sent_aw; + assign wvalid=!reset && state==SEND_W && !sent_w; + assign arvalid=!reset && state==SEND_R; + assign bready=!reset && state==WAIT_B; + assign rready=!reset && state==WAIT_R; + always @(posedge clk) begin + load_valid<=0; + if(reset) begin + state<=IDLE;addr<=0;data<=0;mask<=0;sent_aw<=0;sent_w<=0; + load_valid<=0;load_error<=0;load_result<=0; + end else case(state) + IDLE:if(load_en) begin + addr<={load_addr[27:4],4'd0};data<=load_data;mask<=load_mask; + sent_aw<=0;sent_w<=0;load_error<=0; + state<=|load_mask ? SEND_W : SEND_R; + end + SEND_W:begin + if(awvalid && awready) sent_aw<=1; + if(wvalid && wready) sent_w<=1; + if((sent_aw || awready) && (sent_w || wready)) state<=WAIT_B; + end + WAIT_B:if(bvalid) begin load_valid<=1;load_error<=bresp!=0;state<=RELEASE;end + SEND_R:if(arready) state<=WAIT_R; + WAIT_R:if(rvalid) begin + load_valid<=1;load_error<=rresp!=0;load_result<=rdata;state<=RELEASE; + end + RELEASE:state<=IDLE; + default:state<=IDLE; + endcase + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/board/toy_a7_platform.sv b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/board/toy_a7_platform.sv new file mode 100644 index 0000000..ade0c4d --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/board/toy_a7_platform.sv @@ -0,0 +1,450 @@ +// Generated wiring; source CPU/accelerator RTL is byte-identical. +module toy_a7_platform #(parameter UART_DIVISOR=25, parameter FLASH_BOOT=0) ( + input wire clk, reset, uart_rx_in, + output wire uart_tx_out, cpu_run, exited, loader_error, + output wire [31:0] exit_code, + output wire [3:0] ddr_awid, + output wire [27:0] ddr_awaddr, + output wire [7:0] ddr_awlen, + output wire [2:0] ddr_awsize, + output wire [1:0] ddr_awburst, + output wire ddr_awvalid, + input wire ddr_awready, + output wire [127:0] ddr_wdata, + output wire [15:0] ddr_wstrb, + output wire ddr_wlast, + output wire ddr_wvalid, + input wire ddr_wready, + input wire [3:0] ddr_bid, + input wire [1:0] ddr_bresp, + input wire ddr_bvalid, + output wire ddr_bready, + output wire [3:0] ddr_arid, + output wire [27:0] ddr_araddr, + output wire [7:0] ddr_arlen, + output wire [2:0] ddr_arsize, + output wire [1:0] ddr_arburst, + output wire ddr_arvalid, + input wire ddr_arready, + input wire [3:0] ddr_rid, + input wire [127:0] ddr_rdata, + input wire [1:0] ddr_rresp, + input wire ddr_rlast, + input wire ddr_rvalid, + output wire ddr_rready, + input wire flash_miso, flash_recovery, + output wire flash_mosi, flash_sck, flash_cs_n +); + wire cpu_reset=reset || !cpu_run; + wire loader_cpu_run; + assign cpu_run=loader_cpu_run || (FLASH_BOOT && !flash_recovery); + wire irq; + wire rx_valid, rx_error, tx_ready, loader_tx_valid, mmio_tx_valid; + wire [7:0] rx_data, loader_tx_data, mmio_tx_data; + wire load_en, load_valid, load_error; wire [27:0] load_addr; + wire [127:0] load_data, load_result; wire [15:0] load_mask; + uart_rx #(.DIVISOR(UART_DIVISOR)) receiver (.clk(clk),.reset(reset),.rx(uart_rx_in), + .valid(rx_valid),.data(rx_data),.frame_error(rx_error)); + uart_tx #(.DIVISOR(UART_DIVISOR)) transmitter (.clk(clk),.reset(reset), + .valid(cpu_run ? mmio_tx_valid : loader_tx_valid),.data(cpu_run ? mmio_tx_data : loader_tx_data), + .ready(tx_ready),.tx(uart_tx_out)); + ddr_uart_loader loader (.clk(clk),.reset(reset),.rx_valid(rx_valid && !cpu_run),.rx_data(rx_data), + .rx_error(rx_error),.tx_valid(loader_tx_valid),.tx_data(loader_tx_data),.tx_ready(tx_ready), + .cpu_run(loader_cpu_run),.error_seen(loader_error),.load_en(load_en),.load_addr(load_addr), + .load_data(load_data),.load_mask(load_mask),.load_valid(load_valid),.load_error(load_error),.load_result(load_result)); + wire memory_aw_ready; + wire memory_aw_valid; + wire [3:0] memory_aw_bits_id; + wire [31:0] memory_aw_bits_addr; + wire [7:0] memory_aw_bits_len; + wire [2:0] memory_aw_bits_size; + wire [1:0] memory_aw_bits_burst; + wire memory_aw_bits_lock; + wire [3:0] memory_aw_bits_cache; + wire [2:0] memory_aw_bits_prot; + wire [3:0] memory_aw_bits_qos; + wire memory_w_ready; + wire memory_w_valid; + wire [127:0] memory_w_bits_data; + wire [15:0] memory_w_bits_strb; + wire memory_w_bits_last; + wire memory_b_ready; + wire memory_b_valid; + wire [3:0] memory_b_bits_id; + wire [1:0] memory_b_bits_resp; + wire memory_ar_ready; + wire memory_ar_valid; + wire [3:0] memory_ar_bits_id; + wire [31:0] memory_ar_bits_addr; + wire [7:0] memory_ar_bits_len; + wire [2:0] memory_ar_bits_size; + wire [1:0] memory_ar_bits_burst; + wire memory_ar_bits_lock; + wire [3:0] memory_ar_bits_cache; + wire [2:0] memory_ar_bits_prot; + wire [3:0] memory_ar_bits_qos; + wire memory_r_ready; + wire memory_r_valid; + wire [3:0] memory_r_bits_id; + wire [127:0] memory_r_bits_data; + wire [1:0] memory_r_bits_resp; + wire memory_r_bits_last; + wire peripherals_aw_ready; + wire peripherals_aw_valid; + wire [1:0] peripherals_aw_bits_id; + wire [30:0] peripherals_aw_bits_addr; + wire [7:0] peripherals_aw_bits_len; + wire [2:0] peripherals_aw_bits_size; + wire [1:0] peripherals_aw_bits_burst; + wire peripherals_aw_bits_lock; + wire [3:0] peripherals_aw_bits_cache; + wire [2:0] peripherals_aw_bits_prot; + wire [3:0] peripherals_aw_bits_qos; + wire peripherals_w_ready; + wire peripherals_w_valid; + wire [63:0] peripherals_w_bits_data; + wire [7:0] peripherals_w_bits_strb; + wire peripherals_w_bits_last; + wire peripherals_b_ready; + wire peripherals_b_valid; + wire [1:0] peripherals_b_bits_id; + wire [1:0] peripherals_b_bits_resp; + wire peripherals_ar_ready; + wire peripherals_ar_valid; + wire [1:0] peripherals_ar_bits_id; + wire [30:0] peripherals_ar_bits_addr; + wire [7:0] peripherals_ar_bits_len; + wire [2:0] peripherals_ar_bits_size; + wire [1:0] peripherals_ar_bits_burst; + wire peripherals_ar_bits_lock; + wire [3:0] peripherals_ar_bits_cache; + wire [2:0] peripherals_ar_bits_prot; + wire [3:0] peripherals_ar_bits_qos; + wire peripherals_r_ready; + wire peripherals_r_valid; + wire [1:0] peripherals_r_bits_id; + wire [63:0] peripherals_r_bits_data; + wire [1:0] peripherals_r_bits_resp; + wire peripherals_r_bits_last; + ToyLinuxChip chip ( + .clock(clk), + .reset(cpu_reset), + .interrupt(irq), + .memory_aw_ready(memory_aw_ready), + .memory_aw_valid(memory_aw_valid), + .memory_aw_bits_id(memory_aw_bits_id), + .memory_aw_bits_addr(memory_aw_bits_addr), + .memory_aw_bits_len(memory_aw_bits_len), + .memory_aw_bits_size(memory_aw_bits_size), + .memory_aw_bits_burst(memory_aw_bits_burst), + .memory_aw_bits_lock(memory_aw_bits_lock), + .memory_aw_bits_cache(memory_aw_bits_cache), + .memory_aw_bits_prot(memory_aw_bits_prot), + .memory_aw_bits_qos(memory_aw_bits_qos), + .memory_w_ready(memory_w_ready), + .memory_w_valid(memory_w_valid), + .memory_w_bits_data(memory_w_bits_data), + .memory_w_bits_strb(memory_w_bits_strb), + .memory_w_bits_last(memory_w_bits_last), + .memory_b_ready(memory_b_ready), + .memory_b_valid(memory_b_valid), + .memory_b_bits_id(memory_b_bits_id), + .memory_b_bits_resp(memory_b_bits_resp), + .memory_ar_ready(memory_ar_ready), + .memory_ar_valid(memory_ar_valid), + .memory_ar_bits_id(memory_ar_bits_id), + .memory_ar_bits_addr(memory_ar_bits_addr), + .memory_ar_bits_len(memory_ar_bits_len), + .memory_ar_bits_size(memory_ar_bits_size), + .memory_ar_bits_burst(memory_ar_bits_burst), + .memory_ar_bits_lock(memory_ar_bits_lock), + .memory_ar_bits_cache(memory_ar_bits_cache), + .memory_ar_bits_prot(memory_ar_bits_prot), + .memory_ar_bits_qos(memory_ar_bits_qos), + .memory_r_ready(memory_r_ready), + .memory_r_valid(memory_r_valid), + .memory_r_bits_id(memory_r_bits_id), + .memory_r_bits_data(memory_r_bits_data), + .memory_r_bits_resp(memory_r_bits_resp), + .memory_r_bits_last(memory_r_bits_last), + .peripherals_aw_ready(peripherals_aw_ready), + .peripherals_aw_valid(peripherals_aw_valid), + .peripherals_aw_bits_id(peripherals_aw_bits_id), + .peripherals_aw_bits_addr(peripherals_aw_bits_addr), + .peripherals_aw_bits_len(peripherals_aw_bits_len), + .peripherals_aw_bits_size(peripherals_aw_bits_size), + .peripherals_aw_bits_burst(peripherals_aw_bits_burst), + .peripherals_aw_bits_lock(peripherals_aw_bits_lock), + .peripherals_aw_bits_cache(peripherals_aw_bits_cache), + .peripherals_aw_bits_prot(peripherals_aw_bits_prot), + .peripherals_aw_bits_qos(peripherals_aw_bits_qos), + .peripherals_w_ready(peripherals_w_ready), + .peripherals_w_valid(peripherals_w_valid), + .peripherals_w_bits_data(peripherals_w_bits_data), + .peripherals_w_bits_strb(peripherals_w_bits_strb), + .peripherals_w_bits_last(peripherals_w_bits_last), + .peripherals_b_ready(peripherals_b_ready), + .peripherals_b_valid(peripherals_b_valid), + .peripherals_b_bits_id(peripherals_b_bits_id), + .peripherals_b_bits_resp(peripherals_b_bits_resp), + .peripherals_ar_ready(peripherals_ar_ready), + .peripherals_ar_valid(peripherals_ar_valid), + .peripherals_ar_bits_id(peripherals_ar_bits_id), + .peripherals_ar_bits_addr(peripherals_ar_bits_addr), + .peripherals_ar_bits_len(peripherals_ar_bits_len), + .peripherals_ar_bits_size(peripherals_ar_bits_size), + .peripherals_ar_bits_burst(peripherals_ar_bits_burst), + .peripherals_ar_bits_lock(peripherals_ar_bits_lock), + .peripherals_ar_bits_cache(peripherals_ar_bits_cache), + .peripherals_ar_bits_prot(peripherals_ar_bits_prot), + .peripherals_ar_bits_qos(peripherals_ar_bits_qos), + .peripherals_r_ready(peripherals_r_ready), + .peripherals_r_valid(peripherals_r_valid), + .peripherals_r_bits_id(peripherals_r_bits_id), + .peripherals_r_bits_data(peripherals_r_bits_data), + .peripherals_r_bits_resp(peripherals_r_bits_resp), + .peripherals_r_bits_last(peripherals_r_bits_last) + ); + wire [3:0] c_awid; + wire [27:0] c_awaddr; + wire [7:0] c_awlen; + wire [2:0] c_awsize; + wire [1:0] c_awburst; + wire c_awvalid; + wire c_awready; + wire [127:0] c_wdata; + wire [15:0] c_wstrb; + wire c_wlast; + wire c_wvalid; + wire c_wready; + wire [3:0] c_bid; + wire [1:0] c_bresp; + wire c_bvalid; + wire c_bready; + wire [3:0] c_arid; + wire [27:0] c_araddr; + wire [7:0] c_arlen; + wire [2:0] c_arsize; + wire [1:0] c_arburst; + wire c_arvalid; + wire c_arready; + wire [3:0] c_rid; + wire [127:0] c_rdata; + wire [1:0] c_rresp; + wire c_rlast; + wire c_rvalid; + wire c_rready; + wire [3:0] l_awid; + wire [27:0] l_awaddr; + wire [7:0] l_awlen; + wire [2:0] l_awsize; + wire [1:0] l_awburst; + wire l_awvalid; + wire l_awready; + wire [127:0] l_wdata; + wire [15:0] l_wstrb; + wire l_wlast; + wire l_wvalid; + wire l_wready; + wire [3:0] l_bid; + wire [1:0] l_bresp; + wire l_bvalid; + wire l_bready; + wire [3:0] l_arid; + wire [27:0] l_araddr; + wire [7:0] l_arlen; + wire [2:0] l_arsize; + wire [1:0] l_arburst; + wire l_arvalid; + wire l_arready; + wire [3:0] l_rid; + wire [127:0] l_rdata; + wire [1:0] l_rresp; + wire l_rlast; + wire l_rvalid; + wire l_rready; + axi_fullwidth normalizer ( + .clk(clk), + .reset(reset), + .s_awid(memory_aw_bits_id), + .m_awid(c_awid), + .s_awaddr(memory_aw_bits_addr), + .m_awaddr(c_awaddr), + .s_awlen(memory_aw_bits_len), + .m_awlen(c_awlen), + .s_awsize(memory_aw_bits_size), + .m_awsize(c_awsize), + .s_awburst(memory_aw_bits_burst), + .m_awburst(c_awburst), + .s_awvalid(memory_aw_valid), + .m_awvalid(c_awvalid), + .s_awready(memory_aw_ready), + .m_awready(c_awready), + .s_wdata(memory_w_bits_data), + .m_wdata(c_wdata), + .s_wstrb(memory_w_bits_strb), + .m_wstrb(c_wstrb), + .s_wlast(memory_w_bits_last), + .m_wlast(c_wlast), + .s_wvalid(memory_w_valid), + .m_wvalid(c_wvalid), + .s_wready(memory_w_ready), + .m_wready(c_wready), + .s_bid(memory_b_bits_id), + .m_bid(c_bid), + .s_bresp(memory_b_bits_resp), + .m_bresp(c_bresp), + .s_bvalid(memory_b_valid), + .m_bvalid(c_bvalid), + .s_bready(memory_b_ready), + .m_bready(c_bready), + .s_arid(memory_ar_bits_id), + .m_arid(c_arid), + .s_araddr(memory_ar_bits_addr), + .m_araddr(c_araddr), + .s_arlen(memory_ar_bits_len), + .m_arlen(c_arlen), + .s_arsize(memory_ar_bits_size), + .m_arsize(c_arsize), + .s_arburst(memory_ar_bits_burst), + .m_arburst(c_arburst), + .s_arvalid(memory_ar_valid), + .m_arvalid(c_arvalid), + .s_arready(memory_ar_ready), + .m_arready(c_arready), + .s_rid(memory_r_bits_id), + .m_rid(c_rid), + .s_rdata(memory_r_bits_data), + .m_rdata(c_rdata), + .s_rresp(memory_r_bits_resp), + .m_rresp(c_rresp), + .s_rlast(memory_r_bits_last), + .m_rlast(c_rlast), + .s_rvalid(memory_r_valid), + .m_rvalid(c_rvalid), + .s_rready(memory_r_ready), + .m_rready(c_rready) + ); + loader_axi load_bridge ( + .clk(clk), + .reset(reset), + .load_en(load_en), + .load_addr(load_addr), + .load_data(load_data), + .load_mask(load_mask), + .load_valid(load_valid), + .load_error(load_error), + .load_result(load_result), + .awaddr(l_awaddr), + .araddr(l_araddr), + .awvalid(l_awvalid), + .wvalid(l_wvalid), + .arvalid(l_arvalid), + .bready(l_bready), + .rready(l_rready), + .awready(l_awready), + .wready(l_wready), + .arready(l_arready), + .bvalid(l_bvalid), + .rvalid(l_rvalid), + .wdata(l_wdata), + .wstrb(l_wstrb), + .bresp(l_bresp), + .rresp(l_rresp), + .rdata(l_rdata) + ); + assign l_awid=0; + assign l_arid=0; + assign l_awlen=0; + assign l_arlen=0; + assign l_awsize=4; + assign l_arsize=4; + assign l_awburst=1; + assign l_arburst=1; + assign l_wlast=1; + assign ddr_awid=cpu_run ? c_awid : l_awid; + assign ddr_awaddr=cpu_run ? c_awaddr : l_awaddr; + assign ddr_awlen=cpu_run ? c_awlen : l_awlen; + assign ddr_awsize=cpu_run ? c_awsize : l_awsize; + assign ddr_awburst=cpu_run ? c_awburst : l_awburst; + assign ddr_awvalid=cpu_run ? c_awvalid : l_awvalid; + assign c_awready=ddr_awready && cpu_run; + assign l_awready=ddr_awready && !cpu_run; + assign ddr_wdata=cpu_run ? c_wdata : l_wdata; + assign ddr_wstrb=cpu_run ? c_wstrb : l_wstrb; + assign ddr_wlast=cpu_run ? c_wlast : l_wlast; + assign ddr_wvalid=cpu_run ? c_wvalid : l_wvalid; + assign c_wready=ddr_wready && cpu_run; + assign l_wready=ddr_wready && !cpu_run; + assign c_bid=ddr_bid; + assign l_bid=ddr_bid; + assign c_bresp=ddr_bresp; + assign l_bresp=ddr_bresp; + assign c_bvalid=ddr_bvalid && cpu_run; + assign l_bvalid=ddr_bvalid && !cpu_run; + assign ddr_bready=cpu_run ? c_bready : l_bready; + assign ddr_arid=cpu_run ? c_arid : l_arid; + assign ddr_araddr=cpu_run ? c_araddr : l_araddr; + assign ddr_arlen=cpu_run ? c_arlen : l_arlen; + assign ddr_arsize=cpu_run ? c_arsize : l_arsize; + assign ddr_arburst=cpu_run ? c_arburst : l_arburst; + assign ddr_arvalid=cpu_run ? c_arvalid : l_arvalid; + assign c_arready=ddr_arready && cpu_run; + assign l_arready=ddr_arready && !cpu_run; + assign c_rid=ddr_rid; + assign l_rid=ddr_rid; + assign c_rdata=ddr_rdata; + assign l_rdata=ddr_rdata; + assign c_rresp=ddr_rresp; + assign l_rresp=ddr_rresp; + assign c_rlast=ddr_rlast; + assign l_rlast=ddr_rlast; + assign c_rvalid=ddr_rvalid && cpu_run; + assign l_rvalid=ddr_rvalid && !cpu_run; + assign ddr_rready=cpu_run ? c_rready : l_rready; + wire [1:0] scu_bresp; + assign peripherals_b_bits_resp=scu_bresp; + axi_scu #(.FLASH_BOOT(FLASH_BOOT)) peripherals ( + .clk(clk), + .reset(cpu_reset), + .awid(peripherals_aw_bits_id), + .awaddr(peripherals_aw_bits_addr), + .awlen(peripherals_aw_bits_len), + .awsize(peripherals_aw_bits_size), + .awburst(peripherals_aw_bits_burst), + .awvalid(peripherals_aw_valid), + .awready(peripherals_aw_ready), + .wdata(peripherals_w_bits_data), + .wstrb(peripherals_w_bits_strb), + .wlast(peripherals_w_bits_last), + .wvalid(peripherals_w_valid), + .wready(peripherals_w_ready), + .bid(peripherals_b_bits_id), + .bresp(scu_bresp), + .bvalid(peripherals_b_valid), + .bready(peripherals_b_ready), + .arid(peripherals_ar_bits_id), + .araddr(peripherals_ar_bits_addr), + .arlen(peripherals_ar_bits_len), + .arsize(peripherals_ar_bits_size), + .arburst(peripherals_ar_bits_burst), + .arvalid(peripherals_ar_valid), + .arready(peripherals_ar_ready), + .rid(peripherals_r_bits_id), + .rdata(peripherals_r_bits_data), + .rresp(peripherals_r_bits_resp), + .rlast(peripherals_r_bits_last), + .rvalid(peripherals_r_valid), + .rready(peripherals_r_ready), + .rx_valid(rx_valid && cpu_run), + .rx_data(rx_data), + .rx_error(rx_error), + .tx_valid(mmio_tx_valid), + .tx_data(mmio_tx_data), + .tx_ready(tx_ready), + .exited(exited), + .exit_code(exit_code), + .interrupt(irq),.flash_miso(flash_miso),.flash_recovery(flash_recovery), + .flash_mosi(flash_mosi),.flash_sck(flash_sck),.flash_cs_n(flash_cs_n) + ); +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/board/toy_a7_top.sv b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/board/toy_a7_top.sv new file mode 100644 index 0000000..397a262 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/board/toy_a7_top.sv @@ -0,0 +1,305 @@ +module toy_a7_top #(parameter FLASH_BOOT=0) ( + input wire CLK100MHZ, btn0, uart_txd_in, output wire uart_rxd_out, output wire [3:0] led, + inout wire [15:0] ddr3_dq, inout wire [1:0] ddr3_dqs_n, ddr3_dqs_p, + output wire [13:0] ddr3_addr, output wire [2:0] ddr3_ba, + output wire ddr3_ras_n, ddr3_cas_n, ddr3_we_n, ddr3_reset_n, + output wire [0:0] ddr3_ck_p, ddr3_ck_n, ddr3_cke, ddr3_cs_n, ddr3_odt, output wire [1:0] ddr3_dm, + input wire sw0, flash_miso, + output wire flash_mosi, flash_cs_n, flash_wp_n, flash_hold_n +); + wire clk_in,fb,fb_buf,core_raw,sys_raw,ref_raw,clk,sys_clk,ref_clk,locked; + IBUF input_clock (.I(CLK100MHZ),.O(clk_in)); + MMCME2_BASE #(.CLKIN1_PERIOD(10.0),.DIVCLK_DIVIDE(1),.CLKFBOUT_MULT_F(10.0), + .CLKOUT0_DIVIDE_F(40.0),.CLKOUT1_DIVIDE(6),.CLKOUT2_DIVIDE(5)) clock_mmcm ( + .CLKIN1(clk_in),.CLKFBIN(fb_buf),.CLKFBOUT(fb),.CLKOUT0(core_raw), + .CLKOUT1(sys_raw),.CLKOUT2(ref_raw),.LOCKED(locked),.RST(1'b0),.PWRDWN(1'b0)); + BUFG fb_buffer (.I(fb),.O(fb_buf)); BUFG core_buffer (.I(core_raw),.O(clk)); + BUFG sys_buffer (.I(sys_raw),.O(sys_clk)); BUFG ref_buffer (.I(ref_raw),.O(ref_clk)); + wire ui_clk,ui_rst,mig_locked,calibrated; + wire flash_sck; + assign flash_wp_n=1;assign flash_hold_n=1; + generate if(FLASH_BOOT) begin : flash_clock + STARTUPE2 startup (.CLK(1'b0),.GSR(1'b0),.GTS(1'b0),.KEYCLEARB(1'b1),.PACK(1'b0), + .USRCCLKO(flash_sck),.USRCCLKTS(1'b0),.USRDONEO(1'b1),.USRDONETS(1'b1), + .CFGCLK(),.CFGMCLK(),.EOS(),.PREQ()); + end endgenerate + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg sw_meta=0,sw_sync=0; + reg flash_recovery=0; + always @(posedge clk) begin + sw_meta<=sw0;sw_sync<=sw_meta; + if(reset) flash_recovery<=sw_sync; + end + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg [2:0] lock_sync=7; + always @(posedge clk or negedge locked) if(!locked) lock_sync<=7;else lock_sync<={lock_sync[1:0],1'b0}; + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg btn_meta=0,btn_sync=0; + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg btn_ref_meta=0,btn_ref_sync=0; + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg [2:0] mig_resetn_pipe=0; + always @(posedge ref_clk) begin btn_ref_meta<=btn0;btn_ref_sync<=btn_ref_meta;end + always @(posedge ref_clk or negedge locked) if(!locked) mig_resetn_pipe<=0; + else mig_resetn_pipe<={mig_resetn_pipe[1:0],!btn_ref_sync}; + wire mig_resetn=mig_resetn_pipe[2]; + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg [1:0] calib_sync=0; + always @(posedge clk) begin btn_meta<=btn0;btn_sync<=btn_meta;calib_sync<={calib_sync[0],calibrated};end + reg [17:0] reset_count=0;wire reset=lock_sync[2] || btn_sync || !calib_sync[1] || !(&reset_count); + always @(posedge clk) if(lock_sync[2] || btn_sync || !calib_sync[1]) reset_count<=0; + else if(!(&reset_count)) reset_count<=reset_count+1'b1; + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg [2:0] ui_reset_pipe=7; + always @(posedge ui_clk or posedge ui_rst) if(ui_rst) ui_reset_pipe<=7; + else ui_reset_pipe<={ui_reset_pipe[1:0],1'b0}; + wire ui_aresetn=~ui_reset_pipe[2]; + wire cpu_run,exited,loader_error;wire [31:0] exit_code;reg [24:0] heartbeat=0; + always @(posedge clk) if(reset) heartbeat<=0;else heartbeat<=heartbeat+1'b1; + assign led={heartbeat[24],cpu_run && !reset,loader_error || (exited && exit_code!=0),calib_sync[1]}; + wire [3:0] ddr_awid; + wire [27:0] ddr_awaddr; + wire [7:0] ddr_awlen; + wire [2:0] ddr_awsize; + wire [1:0] ddr_awburst; + wire ddr_awvalid; + wire ddr_awready; + wire [127:0] ddr_wdata; + wire [15:0] ddr_wstrb; + wire ddr_wlast; + wire ddr_wvalid; + wire ddr_wready; + wire [3:0] ddr_bid; + wire [1:0] ddr_bresp; + wire ddr_bvalid; + wire ddr_bready; + wire [3:0] ddr_arid; + wire [27:0] ddr_araddr; + wire [7:0] ddr_arlen; + wire [2:0] ddr_arsize; + wire [1:0] ddr_arburst; + wire ddr_arvalid; + wire ddr_arready; + wire [3:0] ddr_rid; + wire [127:0] ddr_rdata; + wire [1:0] ddr_rresp; + wire ddr_rlast; + wire ddr_rvalid; + wire ddr_rready; + wire [3:0] ui_awid; + wire [27:0] ui_awaddr; + wire [7:0] ui_awlen; + wire [2:0] ui_awsize; + wire [1:0] ui_awburst; + wire ui_awvalid; + wire ui_awready; + wire [127:0] ui_wdata; + wire [15:0] ui_wstrb; + wire ui_wlast; + wire ui_wvalid; + wire ui_wready; + wire [3:0] ui_bid; + wire [1:0] ui_bresp; + wire ui_bvalid; + wire ui_bready; + wire [3:0] ui_arid; + wire [27:0] ui_araddr; + wire [7:0] ui_arlen; + wire [2:0] ui_arsize; + wire [1:0] ui_arburst; + wire ui_arvalid; + wire ui_arready; + wire [3:0] ui_rid; + wire [127:0] ui_rdata; + wire [1:0] ui_rresp; + wire ui_rlast; + wire ui_rvalid; + wire ui_rready; + toy_a7_platform #(.FLASH_BOOT(FLASH_BOOT)) platform ( + .clk(clk), + .reset(reset), + .uart_rx_in(uart_txd_in), + .uart_tx_out(uart_rxd_out), + .cpu_run(cpu_run), + .exited(exited), + .loader_error(loader_error), + .exit_code(exit_code), + .flash_miso(flash_miso),.flash_mosi(flash_mosi),.flash_sck(flash_sck), + .flash_cs_n(flash_cs_n),.flash_recovery(flash_recovery), + .ddr_awid(ddr_awid), + .ddr_awaddr(ddr_awaddr), + .ddr_awlen(ddr_awlen), + .ddr_awsize(ddr_awsize), + .ddr_awburst(ddr_awburst), + .ddr_awvalid(ddr_awvalid), + .ddr_awready(ddr_awready), + .ddr_wdata(ddr_wdata), + .ddr_wstrb(ddr_wstrb), + .ddr_wlast(ddr_wlast), + .ddr_wvalid(ddr_wvalid), + .ddr_wready(ddr_wready), + .ddr_bid(ddr_bid), + .ddr_bresp(ddr_bresp), + .ddr_bvalid(ddr_bvalid), + .ddr_bready(ddr_bready), + .ddr_arid(ddr_arid), + .ddr_araddr(ddr_araddr), + .ddr_arlen(ddr_arlen), + .ddr_arsize(ddr_arsize), + .ddr_arburst(ddr_arburst), + .ddr_arvalid(ddr_arvalid), + .ddr_arready(ddr_arready), + .ddr_rid(ddr_rid), + .ddr_rdata(ddr_rdata), + .ddr_rresp(ddr_rresp), + .ddr_rlast(ddr_rlast), + .ddr_rvalid(ddr_rvalid), + .ddr_rready(ddr_rready) + ); + toy_axi_cdc memory_cdc ( + .s_axi_aclk(clk), + .s_axi_aresetn(!reset), + .m_axi_aclk(ui_clk), + .m_axi_aresetn(ui_aresetn), + .s_axi_awid(ddr_awid), + .s_axi_awaddr(ddr_awaddr), + .s_axi_awlen(ddr_awlen), + .s_axi_awsize(ddr_awsize), + .s_axi_awburst(ddr_awburst), + .s_axi_awvalid(ddr_awvalid), + .s_axi_awready(ddr_awready), + .s_axi_wdata(ddr_wdata), + .s_axi_wstrb(ddr_wstrb), + .s_axi_wlast(ddr_wlast), + .s_axi_wvalid(ddr_wvalid), + .s_axi_wready(ddr_wready), + .s_axi_bid(ddr_bid), + .s_axi_bresp(ddr_bresp), + .s_axi_bvalid(ddr_bvalid), + .s_axi_bready(ddr_bready), + .s_axi_arid(ddr_arid), + .s_axi_araddr(ddr_araddr), + .s_axi_arlen(ddr_arlen), + .s_axi_arsize(ddr_arsize), + .s_axi_arburst(ddr_arburst), + .s_axi_arvalid(ddr_arvalid), + .s_axi_arready(ddr_arready), + .s_axi_rid(ddr_rid), + .s_axi_rdata(ddr_rdata), + .s_axi_rresp(ddr_rresp), + .s_axi_rlast(ddr_rlast), + .s_axi_rvalid(ddr_rvalid), + .s_axi_rready(ddr_rready), + .s_axi_awlock(1'b0), + .s_axi_arlock(1'b0), + .s_axi_awcache(4'b0011), + .s_axi_arcache(4'b0011), + .s_axi_awprot(3'd0), + .s_axi_arprot(3'd0), + .s_axi_awqos(4'd0), + .s_axi_arqos(4'd0), + .s_axi_awregion(4'd0), + .s_axi_arregion(4'd0), + .m_axi_awid(ui_awid), + .m_axi_awaddr(ui_awaddr), + .m_axi_awlen(ui_awlen), + .m_axi_awsize(ui_awsize), + .m_axi_awburst(ui_awburst), + .m_axi_awvalid(ui_awvalid), + .m_axi_awready(ui_awready), + .m_axi_wdata(ui_wdata), + .m_axi_wstrb(ui_wstrb), + .m_axi_wlast(ui_wlast), + .m_axi_wvalid(ui_wvalid), + .m_axi_wready(ui_wready), + .m_axi_bid(ui_bid), + .m_axi_bresp(ui_bresp), + .m_axi_bvalid(ui_bvalid), + .m_axi_bready(ui_bready), + .m_axi_arid(ui_arid), + .m_axi_araddr(ui_araddr), + .m_axi_arlen(ui_arlen), + .m_axi_arsize(ui_arsize), + .m_axi_arburst(ui_arburst), + .m_axi_arvalid(ui_arvalid), + .m_axi_arready(ui_arready), + .m_axi_rid(ui_rid), + .m_axi_rdata(ui_rdata), + .m_axi_rresp(ui_rresp), + .m_axi_rlast(ui_rlast), + .m_axi_rvalid(ui_rvalid), + .m_axi_rready(ui_rready), + .m_axi_awlock(), + .m_axi_arlock(), + .m_axi_awcache(), + .m_axi_arcache(), + .m_axi_awprot(), + .m_axi_arprot(), + .m_axi_awqos(), + .m_axi_arqos(), + .m_axi_awregion(), + .m_axi_arregion() + ); + arty_ddr3 ddr_controller ( + .ddr3_dq(ddr3_dq), + .ddr3_dqs_n(ddr3_dqs_n), + .ddr3_dqs_p(ddr3_dqs_p), + .ddr3_addr(ddr3_addr), + .ddr3_ba(ddr3_ba), + .ddr3_ras_n(ddr3_ras_n), + .ddr3_cas_n(ddr3_cas_n), + .ddr3_we_n(ddr3_we_n), + .ddr3_reset_n(ddr3_reset_n), + .ddr3_ck_p(ddr3_ck_p), + .ddr3_ck_n(ddr3_ck_n), + .ddr3_cke(ddr3_cke), + .ddr3_cs_n(ddr3_cs_n), + .ddr3_dm(ddr3_dm), + .ddr3_odt(ddr3_odt), + .sys_clk_i(sys_clk), + .clk_ref_i(ref_clk), + .sys_rst(mig_resetn), + .ui_clk(ui_clk), + .ui_clk_sync_rst(ui_rst), + .mmcm_locked(mig_locked), + .aresetn(ui_aresetn), + .init_calib_complete(calibrated), + .device_temp(), + .app_sr_req(1'b0), + .app_ref_req(1'b0), + .app_zq_req(1'b0), + .app_sr_active(), + .app_ref_ack(), + .app_zq_ack(), + .s_axi_awid(ui_awid), + .s_axi_awaddr(ui_awaddr), + .s_axi_awlen(ui_awlen), + .s_axi_awsize(ui_awsize), + .s_axi_awburst(ui_awburst), + .s_axi_awvalid(ui_awvalid), + .s_axi_awready(ui_awready), + .s_axi_wdata(ui_wdata), + .s_axi_wstrb(ui_wstrb), + .s_axi_wlast(ui_wlast), + .s_axi_wvalid(ui_wvalid), + .s_axi_wready(ui_wready), + .s_axi_bid(ui_bid), + .s_axi_bresp(ui_bresp), + .s_axi_bvalid(ui_bvalid), + .s_axi_bready(ui_bready), + .s_axi_arid(ui_arid), + .s_axi_araddr(ui_araddr), + .s_axi_arlen(ui_arlen), + .s_axi_arsize(ui_arsize), + .s_axi_arburst(ui_arburst), + .s_axi_arvalid(ui_arvalid), + .s_axi_arready(ui_arready), + .s_axi_rid(ui_rid), + .s_axi_rdata(ui_rdata), + .s_axi_rresp(ui_rresp), + .s_axi_rlast(ui_rlast), + .s_axi_rvalid(ui_rvalid), + .s_axi_rready(ui_rready), + .s_axi_awlock(1'b0), + .s_axi_arlock(1'b0), + .s_axi_awcache(4'b0011), + .s_axi_arcache(4'b0011), + .s_axi_awprot(3'd0), + .s_axi_arprot(3'd0), + .s_axi_awqos(4'd0), + .s_axi_arqos(4'd0) + ); +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/board/uart_rx.sv b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/board/uart_rx.sv new file mode 100644 index 0000000..567b8b4 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/board/uart_rx.sv @@ -0,0 +1,40 @@ +// 8-N-1 receiver. Data is sampled in the middle of each bit after a verified +// start bit. A held-low/broken line reports one framing error, then waits high. +module uart_rx #( + parameter integer DIVISOR = 434 +) ( + input wire clk, reset, rx, + output reg valid, + output reg [7:0] data, + output reg frame_error +); + (* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) reg rx_meta = 1, rx_sync = 1; + always @(posedge clk) begin rx_meta <= rx; rx_sync <= rx_meta; end + localparam integer WIDTH = $clog2(DIVISOR) < 1 ? 1 : $clog2(DIVISOR); + localparam [2:0] IDLE=0, START=1, DATA=2, STOP=3, WAIT_HIGH=4; + reg [2:0] state, bit_index; + reg [WIDTH-1:0] count; + reg [7:0] shift; + always @(posedge clk) begin + valid <= 0; frame_error <= 0; + if (reset) begin + state <= IDLE; bit_index <= 0; count <= 0; shift <= 0; data <= 0; + end else case (state) + IDLE: if (!rx_sync) begin state <= START; count <= DIVISOR/2 - 1; end + START: if (count != 0) count <= count - 1'b1; + else if (rx_sync) state <= IDLE; + else begin state <= DATA; bit_index <= 0; count <= DIVISOR - 1; end + DATA: if (count != 0) count <= count - 1'b1; + else begin + shift[bit_index] <= rx_sync; count <= DIVISOR - 1; + if (bit_index == 7) state <= STOP; + else bit_index <= bit_index + 1'b1; + end + STOP: if (count != 0) count <= count - 1'b1; + else if (rx_sync) begin data <= shift; valid <= 1; state <= IDLE; end + else begin frame_error <= 1; state <= WAIT_HIGH; end + WAIT_HIGH: if (rx_sync) state <= IDLE; + default: state <= IDLE; + endcase + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/board/uart_tx.sv b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/board/uart_tx.sv new file mode 100644 index 0000000..11f6e4a --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/board/uart_tx.sv @@ -0,0 +1,37 @@ +module uart_tx #( + parameter integer DIVISOR = 434 // 50 MHz / 115200, error < 0.01%. +) ( + input wire clk, + input wire reset, + input wire valid, + input wire [7:0] data, + output wire ready, + output wire tx +); + localparam integer COUNT_BITS = $clog2(DIVISOR) < 1 ? 1 : $clog2(DIVISOR); + reg [COUNT_BITS-1:0] count; + reg [9:0] shift; + reg [3:0] bits_left; + assign ready = bits_left == 0; + assign tx = shift[0]; + + always @(posedge clk) begin + if (reset) begin + count <= 0; + shift <= 10'h3ff; + bits_left <= 0; + end else if (ready) begin + if (valid) begin + shift <= {1'b1, data, 1'b0}; + bits_left <= 10; + count <= DIVISOR - 1; + end + end else if (count == 0) begin + shift <= {1'b1, shift[9:1]}; + bits_left <= bits_left - 1'b1; + count <= DIVISOR - 1; + end else begin + count <= count - 1'b1; + end + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/build/backpressure-mutation/scu-mutant.sv b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/build/backpressure-mutation/scu-mutant.sv new file mode 100644 index 0000000..feb65be --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/build/backpressure-mutation/scu-mutant.sv @@ -0,0 +1,109 @@ +// Single-hart SCU console used by the pinned Buckyball OpenSBI platform. +// EXIT 0x60000000, TX 0x60020000, RX 0x60020004, STATUS 0x60020005. +// Reads use AXI lane positions; RX pops only after its R response is accepted. +module axi_scu #(parameter FLASH_BOOT=0) ( + input wire clk, reset, + input wire [1:0] awid, arid, + input wire [30:0] awaddr, araddr, + input wire [7:0] awlen, arlen, + input wire [2:0] awsize, arsize, + input wire [1:0] awburst, arburst, + input wire awvalid, arvalid, wvalid, wlast, bready, rready, + output wire awready, arready, wready, + input wire [63:0] wdata, input wire [7:0] wstrb, + output reg [1:0] bid, rid, bresp, rresp, + output reg bvalid, rvalid, rlast, output reg [63:0] rdata, + input wire rx_valid, rx_error, input wire [7:0] rx_data, + output wire tx_valid, output wire [7:0] tx_data, input wire tx_ready, + output reg exited, output reg [31:0] exit_code, output wire interrupt, + input wire flash_miso, flash_recovery, + output wire flash_mosi, flash_sck, + output reg flash_cs_n +); + // SBI/HVC is polled. A paste may otherwise overflow a 16-byte FIFO before + // Linux's next console poll; use RAM-backed 256-byte buffering. + (* ram_style="distributed" *) reg [7:0] fifo[0:255]; + reg [7:0] rp, wp; + reg [8:0] count; + reg overflow, framing, pop_on_read, wa, bad; + reg [7:0] wr_left, rd_left; + reg [30:0] wr_addr; + wire pop=rvalid && rready && pop_on_read; + wire push=rx_valid && (count<256 || pop); + wire wr_tx=wr_addr==31'h60020000 && !bad && wstrb[0]; + wire wr_spi=FLASH_BOOT && wr_addr==31'h60020008 && !bad && wstrb[0]; + wire wr_cs=FLASH_BOOT && wr_addr==31'h6002000c && !bad && wstrb[4]; + wire spi_busy; + wire [7:0] spi_rx; + generate if(FLASH_BOOT) begin : spi_enabled + flash_spi_byte flash (.clk(clk),.reset(reset),.start(wvalid && wready && wr_spi), + .tx_data(wdata[7:0]),.miso(flash_miso),.mosi(flash_mosi),.sck(flash_sck), + .busy(spi_busy),.rx_data(spi_rx)); + end else begin + assign spi_busy=0;assign spi_rx=0;assign flash_mosi=0;assign flash_sck=0; + end endgenerate + assign awready=!reset && !wa && !bvalid; + assign arready=!reset && !rvalid; + assign wready=!reset && wa && (!wr_tx || tx_ready) && (!(wr_spi || wr_cs) || !spi_busy); + assign tx_valid=!reset && wa && wvalid && wr_tx; + assign tx_data=wdata[7:0]; + assign interrupt=count!=0; + always @(posedge clk) begin + if(reset) begin + rp<=0;wp<=0;count<=0;overflow<=0;framing<=0;pop_on_read<=0; + wa<=0;bad<=0;wr_left<=0;rd_left<=0;wr_addr<=0; + bid<=0;rid<=0;bresp<=0;rresp<=0;bvalid<=0;rvalid<=0;rlast<=0;rdata<=0; + exited<=0;exit_code<=0; + flash_cs_n<=1; + end else begin + if(bvalid) bvalid<=0; + if(awvalid && awready) begin + wa<=1;bid<=awid;wr_addr<=awaddr;wr_left<=awlen; + bad<=awlen!=0 || awsize>3 || awburst>1 || + (awaddr & ((31'd1<3 || arburst>1 || (araddr & ((31'd1<=3) rdata[47:40]<={5'd0,framing,overflow,count!=0}; + end else rresp<=2; + end + if(push) begin fifo[wp]<=rx_data;wp<=wp+1'b1;end + if(pop) rp<=rp+1'b1; + case({push,pop}) + 2'b10:count<=count+1'b1; + 2'b01:count<=count-1'b1; + default:count<=count; + endcase + if(rx_valid && !push) overflow<=1; + if(rx_error) framing<=1; + end + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/evidence/2026-10-12/pr10-review/old-platform.sv b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/evidence/2026-10-12/pr10-review/old-platform.sv new file mode 100644 index 0000000..e26d6dc --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/evidence/2026-10-12/pr10-review/old-platform.sv @@ -0,0 +1,450 @@ +// Generated wiring; source CPU/accelerator RTL is byte-identical. +module toy_a7_platform #(parameter UART_DIVISOR=25, parameter FLASH_BOOT=0) ( + input wire clk, reset, uart_rx_in, + output wire uart_tx_out, cpu_run, exited, loader_error, + output wire [31:0] exit_code, + output wire [3:0] ddr_awid, + output wire [27:0] ddr_awaddr, + output wire [7:0] ddr_awlen, + output wire [2:0] ddr_awsize, + output wire [1:0] ddr_awburst, + output wire ddr_awvalid, + input wire ddr_awready, + output wire [127:0] ddr_wdata, + output wire [15:0] ddr_wstrb, + output wire ddr_wlast, + output wire ddr_wvalid, + input wire ddr_wready, + input wire [3:0] ddr_bid, + input wire [1:0] ddr_bresp, + input wire ddr_bvalid, + output wire ddr_bready, + output wire [3:0] ddr_arid, + output wire [27:0] ddr_araddr, + output wire [7:0] ddr_arlen, + output wire [2:0] ddr_arsize, + output wire [1:0] ddr_arburst, + output wire ddr_arvalid, + input wire ddr_arready, + input wire [3:0] ddr_rid, + input wire [127:0] ddr_rdata, + input wire [1:0] ddr_rresp, + input wire ddr_rlast, + input wire ddr_rvalid, + output wire ddr_rready, + input wire flash_miso, flash_recovery, + output wire flash_mosi, flash_sck, flash_cs_n +); + wire cpu_reset=reset || !cpu_run; + wire loader_cpu_run; + assign cpu_run=loader_cpu_run || (FLASH_BOOT && !flash_recovery); + wire irq; + wire rx_valid, rx_error, tx_ready, loader_tx_valid, mmio_tx_valid; + wire [7:0] rx_data, loader_tx_data, mmio_tx_data; + wire load_en, load_valid, load_error; wire [27:0] load_addr; + wire [127:0] load_data, load_result; wire [15:0] load_mask; + uart_rx #(.DIVISOR(UART_DIVISOR)) receiver (.clk(clk),.reset(reset),.rx(uart_rx_in), + .valid(rx_valid),.data(rx_data),.frame_error(rx_error)); + uart_tx #(.DIVISOR(UART_DIVISOR)) transmitter (.clk(clk),.reset(reset), + .valid(cpu_run ? mmio_tx_valid : loader_tx_valid),.data(cpu_run ? mmio_tx_data : loader_tx_data), + .ready(tx_ready),.tx(uart_tx_out)); + ddr_uart_loader loader (.clk(clk),.reset(reset),.rx_valid(rx_valid && !cpu_run),.rx_data(rx_data), + .rx_error(rx_error),.tx_valid(loader_tx_valid),.tx_data(loader_tx_data),.tx_ready(tx_ready), + .cpu_run(loader_cpu_run),.error_seen(loader_error),.load_en(load_en),.load_addr(load_addr), + .load_data(load_data),.load_mask(load_mask),.load_valid(load_valid),.load_error(load_error),.load_result(load_result)); + wire memory_aw_ready; + wire memory_aw_valid; + wire [3:0] memory_aw_bits_id; + wire [31:0] memory_aw_bits_addr; + wire [7:0] memory_aw_bits_len; + wire [2:0] memory_aw_bits_size; + wire [1:0] memory_aw_bits_burst; + wire memory_aw_bits_lock; + wire [3:0] memory_aw_bits_cache; + wire [2:0] memory_aw_bits_prot; + wire [3:0] memory_aw_bits_qos; + wire memory_w_ready; + wire memory_w_valid; + wire [127:0] memory_w_bits_data; + wire [15:0] memory_w_bits_strb; + wire memory_w_bits_last; + wire memory_b_ready; + wire memory_b_valid; + wire [3:0] memory_b_bits_id; + wire [1:0] memory_b_bits_resp; + wire memory_ar_ready; + wire memory_ar_valid; + wire [3:0] memory_ar_bits_id; + wire [31:0] memory_ar_bits_addr; + wire [7:0] memory_ar_bits_len; + wire [2:0] memory_ar_bits_size; + wire [1:0] memory_ar_bits_burst; + wire memory_ar_bits_lock; + wire [3:0] memory_ar_bits_cache; + wire [2:0] memory_ar_bits_prot; + wire [3:0] memory_ar_bits_qos; + wire memory_r_ready; + wire memory_r_valid; + wire [3:0] memory_r_bits_id; + wire [127:0] memory_r_bits_data; + wire [1:0] memory_r_bits_resp; + wire memory_r_bits_last; + wire peripherals_aw_ready; + wire peripherals_aw_valid; + wire [1:0] peripherals_aw_bits_id; + wire [30:0] peripherals_aw_bits_addr; + wire [7:0] peripherals_aw_bits_len; + wire [2:0] peripherals_aw_bits_size; + wire [1:0] peripherals_aw_bits_burst; + wire peripherals_aw_bits_lock; + wire [3:0] peripherals_aw_bits_cache; + wire [2:0] peripherals_aw_bits_prot; + wire [3:0] peripherals_aw_bits_qos; + wire peripherals_w_ready; + wire peripherals_w_valid; + wire [63:0] peripherals_w_bits_data; + wire [7:0] peripherals_w_bits_strb; + wire peripherals_w_bits_last; + wire peripherals_b_ready; + wire peripherals_b_valid; + wire [1:0] peripherals_b_bits_id; + wire [1:0] peripherals_b_bits_resp; + wire peripherals_ar_ready; + wire peripherals_ar_valid; + wire [1:0] peripherals_ar_bits_id; + wire [30:0] peripherals_ar_bits_addr; + wire [7:0] peripherals_ar_bits_len; + wire [2:0] peripherals_ar_bits_size; + wire [1:0] peripherals_ar_bits_burst; + wire peripherals_ar_bits_lock; + wire [3:0] peripherals_ar_bits_cache; + wire [2:0] peripherals_ar_bits_prot; + wire [3:0] peripherals_ar_bits_qos; + wire peripherals_r_ready; + wire peripherals_r_valid; + wire [1:0] peripherals_r_bits_id; + wire [63:0] peripherals_r_bits_data; + wire [1:0] peripherals_r_bits_resp; + wire peripherals_r_bits_last; + ToyLinuxChip chip ( + .clock(clk), + .reset(cpu_reset), + .interrupt(irq), + .memory_aw_ready(memory_aw_ready), + .memory_aw_valid(memory_aw_valid), + .memory_aw_bits_id(memory_aw_bits_id), + .memory_aw_bits_addr(memory_aw_bits_addr), + .memory_aw_bits_len(memory_aw_bits_len), + .memory_aw_bits_size(memory_aw_bits_size), + .memory_aw_bits_burst(memory_aw_bits_burst), + .memory_aw_bits_lock(memory_aw_bits_lock), + .memory_aw_bits_cache(memory_aw_bits_cache), + .memory_aw_bits_prot(memory_aw_bits_prot), + .memory_aw_bits_qos(memory_aw_bits_qos), + .memory_w_ready(memory_w_ready), + .memory_w_valid(memory_w_valid), + .memory_w_bits_data(memory_w_bits_data), + .memory_w_bits_strb(memory_w_bits_strb), + .memory_w_bits_last(memory_w_bits_last), + .memory_b_ready(memory_b_ready), + .memory_b_valid(memory_b_valid), + .memory_b_bits_id(memory_b_bits_id), + .memory_b_bits_resp(memory_b_bits_resp), + .memory_ar_ready(memory_ar_ready), + .memory_ar_valid(memory_ar_valid), + .memory_ar_bits_id(memory_ar_bits_id), + .memory_ar_bits_addr(memory_ar_bits_addr), + .memory_ar_bits_len(memory_ar_bits_len), + .memory_ar_bits_size(memory_ar_bits_size), + .memory_ar_bits_burst(memory_ar_bits_burst), + .memory_ar_bits_lock(memory_ar_bits_lock), + .memory_ar_bits_cache(memory_ar_bits_cache), + .memory_ar_bits_prot(memory_ar_bits_prot), + .memory_ar_bits_qos(memory_ar_bits_qos), + .memory_r_ready(memory_r_ready), + .memory_r_valid(memory_r_valid), + .memory_r_bits_id(memory_r_bits_id), + .memory_r_bits_data(memory_r_bits_data), + .memory_r_bits_resp(memory_r_bits_resp), + .memory_r_bits_last(memory_r_bits_last), + .peripherals_aw_ready(peripherals_aw_ready), + .peripherals_aw_valid(peripherals_aw_valid), + .peripherals_aw_bits_id(peripherals_aw_bits_id), + .peripherals_aw_bits_addr(peripherals_aw_bits_addr), + .peripherals_aw_bits_len(peripherals_aw_bits_len), + .peripherals_aw_bits_size(peripherals_aw_bits_size), + .peripherals_aw_bits_burst(peripherals_aw_bits_burst), + .peripherals_aw_bits_lock(peripherals_aw_bits_lock), + .peripherals_aw_bits_cache(peripherals_aw_bits_cache), + .peripherals_aw_bits_prot(peripherals_aw_bits_prot), + .peripherals_aw_bits_qos(peripherals_aw_bits_qos), + .peripherals_w_ready(peripherals_w_ready), + .peripherals_w_valid(peripherals_w_valid), + .peripherals_w_bits_data(peripherals_w_bits_data), + .peripherals_w_bits_strb(peripherals_w_bits_strb), + .peripherals_w_bits_last(peripherals_w_bits_last), + .peripherals_b_ready(peripherals_b_ready), + .peripherals_b_valid(peripherals_b_valid), + .peripherals_b_bits_id(peripherals_b_bits_id), + .peripherals_b_bits_resp(peripherals_b_bits_resp), + .peripherals_ar_ready(peripherals_ar_ready), + .peripherals_ar_valid(peripherals_ar_valid), + .peripherals_ar_bits_id(peripherals_ar_bits_id), + .peripherals_ar_bits_addr(peripherals_ar_bits_addr), + .peripherals_ar_bits_len(peripherals_ar_bits_len), + .peripherals_ar_bits_size(peripherals_ar_bits_size), + .peripherals_ar_bits_burst(peripherals_ar_bits_burst), + .peripherals_ar_bits_lock(peripherals_ar_bits_lock), + .peripherals_ar_bits_cache(peripherals_ar_bits_cache), + .peripherals_ar_bits_prot(peripherals_ar_bits_prot), + .peripherals_ar_bits_qos(peripherals_ar_bits_qos), + .peripherals_r_ready(peripherals_r_ready), + .peripherals_r_valid(peripherals_r_valid), + .peripherals_r_bits_id(peripherals_r_bits_id), + .peripherals_r_bits_data(peripherals_r_bits_data), + .peripherals_r_bits_resp(peripherals_r_bits_resp), + .peripherals_r_bits_last(peripherals_r_bits_last) + ); + wire [3:0] c_awid; + wire [27:0] c_awaddr; + wire [7:0] c_awlen; + wire [2:0] c_awsize; + wire [1:0] c_awburst; + wire c_awvalid; + wire c_awready; + wire [127:0] c_wdata; + wire [15:0] c_wstrb; + wire c_wlast; + wire c_wvalid; + wire c_wready; + wire [3:0] c_bid; + wire [1:0] c_bresp; + wire c_bvalid; + wire c_bready; + wire [3:0] c_arid; + wire [27:0] c_araddr; + wire [7:0] c_arlen; + wire [2:0] c_arsize; + wire [1:0] c_arburst; + wire c_arvalid; + wire c_arready; + wire [3:0] c_rid; + wire [127:0] c_rdata; + wire [1:0] c_rresp; + wire c_rlast; + wire c_rvalid; + wire c_rready; + wire [3:0] l_awid; + wire [27:0] l_awaddr; + wire [7:0] l_awlen; + wire [2:0] l_awsize; + wire [1:0] l_awburst; + wire l_awvalid; + wire l_awready; + wire [127:0] l_wdata; + wire [15:0] l_wstrb; + wire l_wlast; + wire l_wvalid; + wire l_wready; + wire [3:0] l_bid; + wire [1:0] l_bresp; + wire l_bvalid; + wire l_bready; + wire [3:0] l_arid; + wire [27:0] l_araddr; + wire [7:0] l_arlen; + wire [2:0] l_arsize; + wire [1:0] l_arburst; + wire l_arvalid; + wire l_arready; + wire [3:0] l_rid; + wire [127:0] l_rdata; + wire [1:0] l_rresp; + wire l_rlast; + wire l_rvalid; + wire l_rready; + axi_fullwidth normalizer ( + .clk(clk), + .reset(reset), + .s_awid(memory_aw_bits_id), + .m_awid(c_awid), + .s_awaddr(memory_aw_bits_addr), + .m_awaddr(c_awaddr), + .s_awlen(memory_aw_bits_len), + .m_awlen(c_awlen), + .s_awsize(memory_aw_bits_size), + .m_awsize(c_awsize), + .s_awburst(memory_aw_bits_burst), + .m_awburst(c_awburst), + .s_awvalid(memory_aw_valid), + .m_awvalid(c_awvalid), + .s_awready(memory_aw_ready), + .m_awready(c_awready), + .s_wdata(memory_w_bits_data), + .m_wdata(c_wdata), + .s_wstrb(memory_w_bits_strb), + .m_wstrb(c_wstrb), + .s_wlast(memory_w_bits_last), + .m_wlast(c_wlast), + .s_wvalid(memory_w_valid), + .m_wvalid(c_wvalid), + .s_wready(memory_w_ready), + .m_wready(c_wready), + .s_bid(memory_b_bits_id), + .m_bid(c_bid), + .s_bresp(memory_b_bits_resp), + .m_bresp(c_bresp), + .s_bvalid(memory_b_valid), + .m_bvalid(c_bvalid), + .s_bready(memory_b_ready), + .m_bready(c_bready), + .s_arid(memory_ar_bits_id), + .m_arid(c_arid), + .s_araddr(memory_ar_bits_addr), + .m_araddr(c_araddr), + .s_arlen(memory_ar_bits_len), + .m_arlen(c_arlen), + .s_arsize(memory_ar_bits_size), + .m_arsize(c_arsize), + .s_arburst(memory_ar_bits_burst), + .m_arburst(c_arburst), + .s_arvalid(memory_ar_valid), + .m_arvalid(c_arvalid), + .s_arready(memory_ar_ready), + .m_arready(c_arready), + .s_rid(memory_r_bits_id), + .m_rid(c_rid), + .s_rdata(memory_r_bits_data), + .m_rdata(c_rdata), + .s_rresp(memory_r_bits_resp), + .m_rresp(c_rresp), + .s_rlast(memory_r_bits_last), + .m_rlast(c_rlast), + .s_rvalid(memory_r_valid), + .m_rvalid(c_rvalid), + .s_rready(memory_r_ready), + .m_rready(c_rready) + ); + loader_axi load_bridge ( + .clk(clk), + .reset(reset), + .load_en(load_en), + .load_addr(load_addr), + .load_data(load_data), + .load_mask(load_mask), + .load_valid(load_valid), + .load_error(load_error), + .load_result(load_result), + .awaddr(l_awaddr), + .araddr(l_araddr), + .awvalid(l_awvalid), + .wvalid(l_wvalid), + .arvalid(l_arvalid), + .bready(l_bready), + .rready(l_rready), + .awready(l_awready), + .wready(l_wready), + .arready(l_arready), + .bvalid(l_bvalid), + .rvalid(l_rvalid), + .wdata(l_wdata), + .wstrb(l_wstrb), + .bresp(l_bresp), + .rresp(l_rresp), + .rdata(l_rdata) + ); + assign l_awid=0; + assign l_arid=0; + assign l_awlen=0; + assign l_arlen=0; + assign l_awsize=4; + assign l_arsize=4; + assign l_awburst=1; + assign l_arburst=1; + assign l_wlast=1; + assign ddr_awid=cpu_run ? c_awid : l_awid; + assign ddr_awaddr=cpu_run ? c_awaddr : l_awaddr; + assign ddr_awlen=cpu_run ? c_awlen : l_awlen; + assign ddr_awsize=cpu_run ? c_awsize : l_awsize; + assign ddr_awburst=cpu_run ? c_awburst : l_awburst; + assign ddr_awvalid=cpu_run ? c_awvalid : l_awvalid; + assign c_awready=ddr_awready && cpu_run; + assign l_awready=ddr_awready && !cpu_run; + assign ddr_wdata=cpu_run ? c_wdata : l_wdata; + assign ddr_wstrb=cpu_run ? c_wstrb : l_wstrb; + assign ddr_wlast=cpu_run ? c_wlast : l_wlast; + assign ddr_wvalid=cpu_run ? c_wvalid : l_wvalid; + assign c_wready=ddr_wready && cpu_run; + assign l_wready=ddr_wready && !cpu_run; + assign c_bid=ddr_bid; + assign l_bid=ddr_bid; + assign c_bresp=ddr_bresp; + assign l_bresp=ddr_bresp; + assign c_bvalid=ddr_bvalid && cpu_run; + assign l_bvalid=ddr_bvalid && !cpu_run; + assign ddr_bready=cpu_run ? c_bready : l_bready; + assign ddr_arid=cpu_run ? c_arid : l_arid; + assign ddr_araddr=cpu_run ? c_araddr : l_araddr; + assign ddr_arlen=cpu_run ? c_arlen : l_arlen; + assign ddr_arsize=cpu_run ? c_arsize : l_arsize; + assign ddr_arburst=cpu_run ? c_arburst : l_arburst; + assign ddr_arvalid=cpu_run ? c_arvalid : l_arvalid; + assign c_arready=ddr_arready && cpu_run; + assign l_arready=ddr_arready && !cpu_run; + assign c_rid=ddr_rid; + assign l_rid=ddr_rid; + assign c_rdata=ddr_rdata; + assign l_rdata=ddr_rdata; + assign c_rresp=ddr_rresp; + assign l_rresp=ddr_rresp; + assign c_rlast=ddr_rlast; + assign l_rlast=ddr_rlast; + assign c_rvalid=ddr_rvalid && cpu_run; + assign l_rvalid=ddr_rvalid && !cpu_run; + assign ddr_rready=cpu_run ? c_rready : l_rready; + wire [1:0] scu_bresp; + assign peripherals_b_bits_resp=|scu_bresp; + axi_scu #(.FLASH_BOOT(FLASH_BOOT)) peripherals ( + .clk(clk), + .reset(cpu_reset), + .awid(peripherals_aw_bits_id), + .awaddr(peripherals_aw_bits_addr), + .awlen(peripherals_aw_bits_len), + .awsize(peripherals_aw_bits_size), + .awburst(peripherals_aw_bits_burst), + .awvalid(peripherals_aw_valid), + .awready(peripherals_aw_ready), + .wdata(peripherals_w_bits_data), + .wstrb(peripherals_w_bits_strb), + .wlast(peripherals_w_bits_last), + .wvalid(peripherals_w_valid), + .wready(peripherals_w_ready), + .bid(peripherals_b_bits_id), + .bresp(scu_bresp), + .bvalid(peripherals_b_valid), + .bready(peripherals_b_ready), + .arid(peripherals_ar_bits_id), + .araddr(peripherals_ar_bits_addr), + .arlen(peripherals_ar_bits_len), + .arsize(peripherals_ar_bits_size), + .arburst(peripherals_ar_bits_burst), + .arvalid(peripherals_ar_valid), + .arready(peripherals_ar_ready), + .rid(peripherals_r_bits_id), + .rdata(peripherals_r_bits_data), + .rresp(peripherals_r_bits_resp), + .rlast(peripherals_r_bits_last), + .rvalid(peripherals_r_valid), + .rready(peripherals_r_ready), + .rx_valid(rx_valid && cpu_run), + .rx_data(rx_data), + .rx_error(rx_error), + .tx_valid(mmio_tx_valid), + .tx_data(mmio_tx_data), + .tx_ready(tx_ready), + .exited(exited), + .exit_code(exit_code), + .interrupt(irq),.flash_miso(flash_miso),.flash_recovery(flash_recovery), + .flash_mosi(flash_mosi),.flash_sck(flash_sck),.flash_cs_n(flash_cs_n) + ); +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/evidence/2026-10-12/pr10-review/sources/tests/tb_platform_bresp.sv b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/evidence/2026-10-12/pr10-review/sources/tests/tb_platform_bresp.sv new file mode 100644 index 0000000..d45f79d --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/evidence/2026-10-12/pr10-review/sources/tests/tb_platform_bresp.sv @@ -0,0 +1,55 @@ +`timescale 1ns/1ps +module tb_platform_bresp; + reg clk=0; + always #5 clk=~clk; + reg reset=1; + reg [30:0] address=0; + reg [2:0] size=2; + reg [7:0] length=0; + reg awvalid=0,wvalid=0,last=1,bready=0; + toy_a7_platform dut(.clk(clk),.reset(reset),.uart_rx_in(1'b1), + .ddr_awready(1'b1),.ddr_wready(1'b1),.ddr_bid(4'd0),.ddr_bresp(2'd0),.ddr_bvalid(1'b0), + .ddr_arready(1'b1),.ddr_rid(4'd0),.ddr_rdata(128'd0),.ddr_rresp(2'd0),.ddr_rlast(1'b1),.ddr_rvalid(1'b0), + .flash_miso(1'b0),.flash_recovery(1'b0)); + task automatic write_case(input [30:0] addr,input [2:0] width,input [7:0] len,input [1:0] expected); + @(negedge clk);address=addr;size=width;length=len;awvalid=1; + do @(posedge clk);while(!dut.peripherals_aw_ready); + @(negedge clk);awvalid=0; + for(integer beat=0;beat<=len;beat=beat+1) begin + wvalid=1;last=beat==len; + do @(posedge clk);while(!dut.peripherals_w_ready); + @(negedge clk);wvalid=0; + end + while(!dut.peripherals_b_valid) @(negedge clk); + repeat(5) begin + // Observe the CPU input, through actual platform wiring and real SCU. + if(dut.chip.peripherals_b_bits_resp!==expected || dut.chip.peripherals_b_bits_id!==2) + $fatal(1,"Platform B response addr=%h actual=%b expected=%b",addr,dut.chip.peripherals_b_bits_resp,expected); + @(negedge clk); + end + bready=1;@(negedge clk);bready=0; + endtask + initial begin + force dut.cpu_run=1; + force dut.peripherals_aw_valid=awvalid; + force dut.peripherals_aw_bits_addr=address; + force dut.peripherals_aw_bits_size=size; + force dut.peripherals_aw_bits_len=length; + force dut.peripherals_aw_bits_id=2; + force dut.peripherals_aw_bits_burst=1; + force dut.peripherals_w_valid=wvalid; + force dut.peripherals_w_bits_last=last; + force dut.peripherals_w_bits_data=64'h13572468; + force dut.peripherals_w_bits_strb=8'h0f; + force dut.peripherals_b_ready=bready; + repeat(5) @(negedge clk);reset=0; + write_case(31'h60000000,2,0,0); + if(!dut.exited || dut.exit_code!==32'h13572468) $fatal(1,"Valid MMIO changed"); + write_case(31'h60030000,2,0,2); + write_case(31'h60000002,2,0,2); + write_case(31'h60000000,2,1,2); + $display("PASS platform AXI B response: valid, invalid address, unaligned, burst, ID and backpressure"); + $finish; + end + initial begin #100000;$fatal(1,"Platform response watchdog");end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/host/flash.py b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/host/flash.py new file mode 100644 index 0000000..6c518ab --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/host/flash.py @@ -0,0 +1,168 @@ +"""Back up/program/verify Flash and check automatic Linux startup, within 1 hour.""" + +import argparse +from datetime import datetime +import hashlib +import json +from pathlib import Path +import subprocess +import shutil +import time + +from observe_flash_boot import Observer + +ROOT = Path(__file__).resolve().parents[1] + + +def sha(path): + return hashlib.sha256(path.read_bytes()).hexdigest() + + +def main(): + p = argparse.ArgumentParser(description=__doc__) + p.add_argument("--vivado", default="vivado") + p.add_argument("--bitstream", type=Path, required=True) + p.add_argument( + "--payload", + type=Path, + required=True, + help="Packed TOYFLZ4 software, not the raw image", + ) + p.add_argument("--part", required=True) + p.add_argument( + "--mcs", + type=Path, + help="Existing Vivado-packed image if the programming host lacks Artix build support", + ) + p.add_argument("--port", required=True) + p.add_argument("--out", type=Path) + args = p.parse_args() + bit = args.bitstream.resolve() + payload = args.payload.resolve() + out = args.out or ROOT / "build" / ( + "flash-program-" + datetime.now().strftime("%Y%m%d-%H%M%S") + ) + out = out.resolve() + out.mkdir(parents=True, exist_ok=False) + image = out / "toy_flash.mcs" + backup = out / "flash-before.bin" + commands = [ + [ + args.vivado, + "-mode", + "batch", + "-source", + str(ROOT / "board/make_flash_image.tcl"), + "-log", + str(out / "image.log"), + "-journal", + str(out / "image.jou"), + "-tclargs", + str(bit), + str(payload), + str(image), + ], + [ + args.vivado, + "-mode", + "batch", + "-source", + str(ROOT / "board/program_flash.tcl"), + "-log", + str(out / "program.log"), + "-journal", + str(out / "program.jou"), + "-tclargs", + str(image), + args.part, + str(backup), + ], + ] + if args.mcs: + packed_record = json.loads( + args.mcs.with_suffix(args.mcs.suffix + ".json").read_text() + ) + if packed_record["result"] != "PASS_VIVADO_FLASH_PACK": + raise ValueError("Prepacked flash image record did not pass packing") + if packed_record["bitstream_sha256"] != sha(bit): + raise ValueError("Prepacked flash image bitstream hash mismatch") + if packed_record["packed_payload_sha256"] != sha(payload): + raise ValueError("Prepacked flash image payload hash mismatch") + if packed_record["flash_image_sha256"] != sha(args.mcs): + raise ValueError("Prepacked flash image MCS hash mismatch") + shutil.copy2(args.mcs.resolve(), image) + commands[0] = None + record = dict( + status="RUNNING", + timeout_seconds=3600, + bitstream_sha256=sha(bit), + packed_payload_sha256=sha(payload), + part=args.part, + port=args.port, + started_at=datetime.now().astimezone().isoformat(), + commands=commands, + ) + result = out / "RESULT.json" + result.write_text(json.dumps(record, indent=2) + "\n") + started = time.monotonic() + watcher = None + try: + for i, command in enumerate(commands): + if command is None: + print("USING_PREPACKED_FLASH_IMAGE", sha(image), flush=True) + continue + if i == 1: + watcher = Observer(args.port, out / "linux-console.log", timeout=3600) + watcher.start() + with (out / f"command-{i}.log").open("w") as log: + proc = subprocess.Popen( + command, cwd=ROOT, stdout=log, stderr=subprocess.STDOUT + ) + try: + code = proc.wait( + timeout=max(1, 3600 - (time.monotonic() - started)) + ) + except subprocess.TimeoutExpired: + if __import__("os").name == "nt": + subprocess.run( + ["taskkill", "/PID", str(proc.pid), "/T", "/F"], + capture_output=True, + ) + else: + proc.kill() + proc.wait() + raise + if code: + raise RuntimeError( + f"Vivado command {i} failed with {code}; inspect {out}" + ) + print("PASS FLASH_STAGE", i, flush=True) + # Program completion may precede CPU decompression; cap the remaining wait. + watcher.thread.join(timeout=max(1, 3600 - (time.monotonic() - started))) + if watcher.thread.is_alive(): + raise TimeoutError("One-hour Flash/Linux timeout") + hardware = watcher.finish() + record.update( + status="PASS", + hardware=hardware, + backup_sha256=sha(backup), + backup_bytes=backup.stat().st_size, + flash_image_sha256=sha(image), + ) + except Exception as error: + record.update(status="FAILED", error=str(error)) + raise + finally: + if watcher is not None: + watcher.stop.set() + watcher.thread.join(timeout=6) + record.update( + elapsed_seconds=round(time.monotonic() - started, 3), + finished_at=datetime.now().astimezone().isoformat(), + ) + result.write_text(json.dumps(record, indent=2) + "\n") + print(json.dumps(record, indent=2), flush=True) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/scripts/check_board.py b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/scripts/check_board.py new file mode 100644 index 0000000..1d064ba --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/scripts/check_board.py @@ -0,0 +1,77 @@ +"""Test the exact board loader, AXI normalizer and OpenSBI SCU with stalls.""" +import hashlib +import json +from pathlib import Path +import subprocess +from offline_check import run_check + +ROOT=Path(__file__).resolve().parents[1] +OUT=ROOT/"build/board-unit" + + +def run(name, files, marker): + executable=OUT/name + command=["iverilog","-g2012","-s",name,"-o",str(executable)]+[str(f) for f in files] + compiled=subprocess.run(command,capture_output=True,text=True,timeout=60) + (OUT/(name+"-compile.log")).write_text(compiled.stdout+compiled.stderr) + compiled.check_returncode() + result=subprocess.run(["vvp",str(executable)],capture_output=True,text=True,timeout=60) + (OUT/(name+".log")).write_text(result.stdout+result.stderr) + print(result.stdout,end="") + result.check_returncode() + assert marker in result.stdout + + +def main(): + fixture=json.loads((ROOT/"tests/PLATFORM_PORTS_MANIFEST.json").read_text()) + if hashlib.sha256((ROOT/"tests/ToyLinuxChipPorts.sv").read_bytes()).hexdigest()!=fixture["stub_sha256"]: + raise ValueError("CPU port fixture differs from its manifest") + OUT.mkdir(parents=True,exist_ok=True) + run("tb_axi_fullwidth",[ROOT/"board/axi_fullwidth.sv",ROOT/"tests/axi_smoke_memory.sv",ROOT/"tests/tb_axi_fullwidth.sv"],"PASS fullwidth AXI") + run("tb_axi_scu",[ROOT/"board/axi_scu.sv",ROOT/"tests/tb_axi_scu.sv"],"PASS SCU") + platform_files=[ROOT/"board"/name for name in + ("toy_a7_platform.sv","axi_fullwidth.sv","axi_scu.sv","ddr_uart_loader.sv", + "loader_axi.sv","uart_rx.sv","uart_tx.sv","flash_spi_byte.sv")] + run("tb_platform_bresp",platform_files+[ROOT/"tests/ToyLinuxChipPorts.sv",ROOT/"tests/tb_platform_bresp.sv"], + "PASS platform AXI B response") + # Retain the CRC/range/timeout/rejected RUN oracle from the earlier loader, + # but connect its new acknowledgement boundary to AXI, not zero-latency RAM. + template=(ROOT/"tests/board_loader_template.sv").read_text() + template=template.replace("module tb_uart_loader", "module tb_ddr_loader") + template=template.replace("uart_loader #", "ddr_uart_loader #") + template=template.replace("32'h01374150", "32'h02374154") + template=template.replace("axi_bram #(.WORDS(256)) memory(", "/* legacy memory removed\naxi_bram #(.WORDS(256)) memory(") + template=template.replace(" always @(posedge clk) begin\n", "*/\n"+LOADER_MEMORY+"\n always @(posedge clk) begin\n",1) + template=template.replace("wire cpu_run,error_seen,load_en,load_valid;", "wire cpu_run,error_seen,load_en,load_valid,load_error;") + template=template.replace("PASS: UART loader", "PASS: DDR UART loader") + (OUT/"tb_ddr_loader.sv").write_text(template) + run("tb_ddr_loader",[ROOT/"board/ddr_uart_loader.sv",ROOT/"board/loader_axi.sv",ROOT/"tests/axi_smoke_memory.sv",OUT/"tb_ddr_loader.sv"],"PASS: DDR UART loader") + files=[p for p in (ROOT/"board").glob("*.sv")]+[ROOT/"tests/tb_axi_fullwidth.sv",ROOT/"tests/tb_axi_scu.sv"] + files += [ROOT/"tests/ToyLinuxChipPorts.sv",ROOT/"tests/tb_platform_bresp.sv"] + record=dict(result="PASS",tests=4,physical_mig_simulated=False, + sources={str(p.relative_to(ROOT)):hashlib.sha256(p.read_bytes()).hexdigest() for p in files}) + (OUT/"RESULT.json").write_text(json.dumps(record,indent=2)+"\n") + + +LOADER_MEMORY=""" + wire [27:0] awaddr,araddr; + wire awvalid,wvalid,arvalid,bready,rready,awready,wready,arready,bvalid,rvalid; + wire [127:0] wdata,rdata; + wire [15:0] wstrb; + wire [1:0] bresp,rresp; + loader_axi bridge(.clk(clk),.reset(reset),.load_en(load_en),.load_addr({16'd0,load_addr}), + .load_data(load_data),.load_mask(load_mask),.load_valid(load_valid),.load_error(load_error),.load_result(load_result), + .awaddr(awaddr),.araddr(araddr),.awvalid(awvalid),.wvalid(wvalid),.arvalid(arvalid), + .bready(bready),.rready(rready),.awready(awready),.wready(wready),.arready(arready), + .bvalid(bvalid),.rvalid(rvalid),.wdata(wdata),.wstrb(wstrb),.bresp(bresp),.rresp(rresp),.rdata(rdata)); + axi_smoke_memory #(.ADDR_BITS(28),.BASE(0),.CAPACITY(4096)) memory ( + .clock(clk),.reset(reset),.aw_bits_id(4'd0),.aw_bits_addr(awaddr),.aw_bits_len(8'd0),.aw_bits_size(3'd4),.aw_bits_burst(2'd1), + .aw_valid(awvalid),.aw_ready(awready),.w_bits_data(wdata),.w_bits_strb(wstrb),.w_bits_last(1'b1),.w_valid(wvalid),.w_ready(wready), + .b_ready(bready),.b_valid(bvalid),.b_bits_id(),.b_bits_resp(bresp), + .ar_bits_id(4'd0),.ar_bits_addr(araddr),.ar_bits_len(8'd0),.ar_bits_size(3'd4),.ar_bits_burst(2'd1),.ar_valid(arvalid),.ar_ready(arready), + .r_ready(rready),.r_valid(rvalid),.r_bits_id(),.r_bits_data(rdata),.r_bits_resp(rresp),.r_bits_last()); +""" + + +if __name__=="__main__": + run_check(main, OUT) diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/scripts/check_flash_guards.py b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/scripts/check_flash_guards.py new file mode 100644 index 0000000..ce63561 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/scripts/check_flash_guards.py @@ -0,0 +1,48 @@ +"""验证普通模式与 python -O 下四项预打包镜像校验均有效。""" + +import hashlib +import json +from pathlib import Path +import subprocess +import sys +import tempfile +from offline_check import run_check + +ROOT = Path(__file__).resolve().parents[1] + + +def main(): + out = ROOT / "build/flash-guard-check" + out.mkdir(parents=True, exist_ok=True) + cases = [] + for optimized in [False, True]: + for field in [None, "result", "bitstream_sha256", "packed_payload_sha256", "flash_image_sha256"]: + with tempfile.TemporaryDirectory(dir=out) as directory: + work = Path(directory) + bit, payload, mcs = [work / name for name in ["chip.bit", "payload.bin", "image.mcs"]] + for path in [bit, payload, mcs]: + path.write_bytes(path.name.encode()) + sha = lambda path: hashlib.sha256(path.read_bytes()).hexdigest() + record = {"result": "PASS_VIVADO_FLASH_PACK", "bitstream_sha256": sha(bit), + "packed_payload_sha256": sha(payload), "flash_image_sha256": sha(mcs)} + if field: + record[field] = "FAILED" if field == "result" else "0" * 64 + mcs.with_suffix(".mcs.json").write_text(json.dumps(record)) + expected = "reject" if field else "accept" + command = [sys.executable] + (["-O"] if optimized else []) + command += [str(ROOT / "tests/flash_guard_probe.py"), str(ROOT / "host/flash.py"), + str(bit), str(payload), str(mcs), str(work / "run"), expected] + result = subprocess.run(command, capture_output=True, text=True, timeout=20) + name = f"{'optimized' if optimized else 'normal'}-{field or 'valid'}" + (out / f"{name}.log").write_text(result.stdout + result.stderr, encoding="utf-8") + result.check_returncode() + if ("PASS INVALID_IMAGE_BLOCKED" if field else "PASS VALID_IMAGE_REACHED_OFFLINE_BOUNDARY") not in result.stdout: + raise ValueError("Missing guard oracle") + cases.append({"optimized": optimized, "field": field or "valid", "result": "PASS"}) + (out / "RESULT.json").write_text(json.dumps({"result": "PASS_FLASH_GUARDS_NORMAL_AND_OPTIMIZED", + "physical_hardware_tested": False, "cases": cases}, indent=2) + "\n") + print(f"PASS Flash image guards: {len(cases)} normal/-O tamper/control cases; no hardware") + + +if __name__ == "__main__": + run_check(main, ROOT / "build/flash-guard-check") diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/scripts/check_platform_mutations.py b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/scripts/check_platform_mutations.py new file mode 100644 index 0000000..203194c --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/scripts/check_platform_mutations.py @@ -0,0 +1,56 @@ +"""只在 build 中注入 RTL 错误，核验 AXI 用例的检错能力；不改生产源码。""" + +import hashlib +import json +from pathlib import Path +import subprocess +from offline_check import run_check + +ROOT = Path(__file__).resolve().parents[1] +OUT = ROOT / "build/backpressure-mutation" +OLD = ROOT / "evidence/2026-10-12/pr10-review" + + +def main(): + original = (ROOT / "board/axi_scu.sv").read_text() + condition = "if(bvalid && bready) bvalid<=0;" + if original.count(condition) != 1: + raise ValueError("SCU mutation target changed; review this oracle") + mutant = OUT / "scu-mutant.sv" + mutant.write_text(original.replace(condition, "if(bvalid) bvalid<=0;")) + common = [ROOT / "board" / name for name in + ["axi_fullwidth.sv", "ddr_uart_loader.sv", "loader_axi.sv", + "uart_rx.sv", "uart_tx.sv", "flash_spi_byte.sv"]] + common += [ROOT / "tests/ToyLinuxChipPorts.sv"] + cases = [] + inputs = [("old-test", ROOT / "board/toy_a7_platform.sv", mutant, + OLD / "sources/tests/tb_platform_bresp.sv", 0), + ("new-test", ROOT / "board/toy_a7_platform.sv", mutant, + ROOT / "tests/tb_platform_bresp.sv", 1), + ("old-response", OLD / "old-platform.sv", ROOT / "board/axi_scu.sv", + ROOT / "tests/tb_platform_bresp.sv", 1)] + for label, platform, scu, bench, expected in inputs: + executable = OUT / label + sources = [platform, scu, bench] + common + compiled = subprocess.run(["iverilog", "-g2012", "-s", "tb_platform_bresp", "-o", + str(executable)] + [str(path) for path in sources], + capture_output=True, text=True, timeout=60) + (OUT / (label + "-compile.log")).write_text(compiled.stdout + compiled.stderr) + compiled.check_returncode() + result = subprocess.run(["vvp", str(executable)], capture_output=True, text=True, timeout=60) + log = result.stdout + result.stderr + (OUT / (label + ".log")).write_text(log) + marker = {"old-test": "PASS platform AXI B response", "new-test": "valid=0", + "old-response": "actual=01 expected=10"}[label] + if result.returncode != expected or marker not in log: + raise ValueError(f"Mutation oracle failed: {label}: {log}") + cases.append({"case": label, "exit_code": result.returncode, "expected_exit_code": expected, + "result": "PASS", "sources": {path.relative_to(ROOT).as_posix(): + hashlib.sha256(path.read_bytes()).hexdigest() for path in sources}}) + record = {"result": "PASS_MUTATION_ORACLES", "physical_hardware_tested": False, "cases": cases} + (OUT / "RESULT.json").write_text(json.dumps(record, indent=2) + "\n") + print("PASS mutation oracles: old test misses premature BVALID drop; new test rejects it and old response bug") + + +if __name__ == "__main__": + run_check(main, OUT) diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/scripts/check_programming_scripts.py b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/scripts/check_programming_scripts.py new file mode 100644 index 0000000..9e248c0 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/scripts/check_programming_scripts.py @@ -0,0 +1,57 @@ +"""离线注入 Vivado API 返回值、异常与配置状态，检查实际 Tcl 入口。""" + +import argparse +import json +from pathlib import Path +import shutil +import subprocess +import tempfile +from offline_check import run_check + +ROOT = Path(__file__).resolve().parents[1] + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--tclsh", default=shutil.which("tclsh")) + args = parser.parse_args() + if not args.tclsh: + raise RuntimeError("Install Tcl or supply --tclsh") + out = ROOT / "build/programming-check" + out.mkdir(parents=True, exist_ok=True) + cases = [] + for script in ["program_arty.tcl", "backup_flash.tcl", "program_flash.tcl"]: + faults = ["none", "device_error", "done_low", "eos_low", "crc_error"] + if script != "program_arty.tcl": + faults += ["readback_error", "short_backup"] + if script == "program_flash.tcl": + faults += ["cfgmem_error"] + for fault in faults: + with tempfile.TemporaryDirectory(dir=out) as directory: + work = Path(directory) + bit = work / "input.bit" + bit.write_bytes(b"offline fixture") + command = [args.tclsh, str(ROOT / "tests/mock_programming.tcl"), + str(ROOT / "board" / script), fault, str(bit), str(work / "backup.bin")] + result = subprocess.run(command, capture_output=True, text=True, timeout=20) + transcript = result.stdout + result.stderr + (out / f"{script}-{fault}.log").write_text(transcript, encoding="utf-8") + if fault == "none": + if result.returncode or "MOCK_SUCCESS" not in transcript: + raise ValueError(f"Documented success return rejected: {script}: {transcript}") + else: + if result.returncode == 0 or "MOCK_FAILURE" not in transcript: + raise ValueError(f"Injected failure accepted: {script}/{fault}") + if "PASS FLASH_PROGRAM_VERIFY" in transcript or "ARTY_JTAG_PROGRAMMED:" in transcript: + raise ValueError("False success marker") + if fault != "cfgmem_error" and "program_flash" in transcript.split("MOCK_EVENTS", 1)[1].splitlines()[0]: + raise ValueError("Flash programming reached after an earlier failure") + cases.append({"script": script, "fault": fault, "result": "PASS"}) + record = {"result": "PASS_OFFLINE_TCL_CONTRACTS", "physical_hardware_tested": False, + "cases": cases} + (out / "RESULT.json").write_text(json.dumps(record, indent=2) + "\n") + print(f"PASS programming scripts: {len(cases)} documented-return/status/error cases; no hardware") + + +if __name__ == "__main__": + run_check(main, ROOT / "build/programming-check") diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/scripts/check_runner_status.py b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/scripts/check_runner_status.py new file mode 100644 index 0000000..14846cb --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/scripts/check_runner_status.py @@ -0,0 +1,71 @@ +"""注入检查失败，验证三种实际入口不会遗留上次 PASS；不连接硬件。""" + +import argparse +import hashlib +import json +from pathlib import Path +import shutil +import subprocess +import sys +import tempfile +from offline_check import run_check + +ROOT = Path(__file__).resolve().parents[1] +OUT = ROOT / "build/runner-status-check" + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--baseline-ref", help="仅用旧源码反测，预期复现遗留 PASS") + args = parser.parse_args() + OUT.mkdir(parents=True, exist_ok=True) + cases = [] + runners = [("check_board.py", "board-unit", "PASS"), + ("check_programming_scripts.py", "programming-check", "PASS_OFFLINE_TCL_CONTRACTS"), + ("check_flash_guards.py", "flash-guard-check", "PASS_FLASH_GUARDS_NORMAL_AND_OPTIMIZED")] + for script, directory, old_pass in runners: + source = ROOT / "scripts" / script + data = source.read_bytes() if not args.baseline_ref else subprocess.check_output( + ["git", "show", f"{args.baseline_ref}:platforms/arty-a7-toy/scripts/{script}"], cwd=ROOT) + with tempfile.TemporaryDirectory(dir=OUT) as temporary: + work = Path(temporary) + (work / "scripts").mkdir() + (work / "tests").mkdir() + (work / "scripts" / script).write_bytes(data) + helper = ROOT / "scripts/offline_check.py" + if helper.exists(): + shutil.copy2(helper, work / "scripts/offline_check.py") + result_file = work / "build" / directory / "RESULT.json" + result_file.parent.mkdir(parents=True) + result_file.write_text(json.dumps({"result": old_pass})) + if script == "check_board.py": + (work / "tests/PLATFORM_PORTS_MANIFEST.json").write_text(json.dumps({"stub_sha256": "0" * 64})) + (work / "tests/ToyLinuxChipPorts.sv").write_text("// injected fixture mismatch\n") + extra = [] + elif script == "check_programming_scripts.py": + # A child fails before any hardware operation; Python is the injected interpreter. + (work / "tests/mock_programming.tcl").write_text("raise RuntimeError('INJECTED_CHECK_FAILURE')\n") + extra = ["--tclsh", sys.executable] + else: + (work / "tests/flash_guard_probe.py").write_text("raise RuntimeError('INJECTED_CHECK_FAILURE')\n") + extra = [] + process = subprocess.run([sys.executable, str(work / "scripts" / script)] + extra, + capture_output=True, text=True, timeout=30) + status = json.loads(result_file.read_text()) + log = process.stdout + process.stderr + "\nOBSERVED_RESULT " + json.dumps(status) + "\n" + (OUT / (script + ".log")).write_text(log, encoding="utf-8") + if process.returncode == 0: + raise ValueError("Failure injection did not reach the actual runner") + expected = old_pass if args.baseline_ref else "FAILED" + if status["result"] != expected: + raise ValueError(f"{script}: expected {expected}, got {status}") + cases.append({"script": script, "source_sha256": hashlib.sha256(data).hexdigest(), + "exit_code": process.returncode, "observed_result": status["result"], "result": "PASS"}) + record = {"result": "PASS_EXPECTED_STALE_BASELINE" if args.baseline_ref else "PASS_RUNNER_FAILURE_STATUS", + "baseline_ref": args.baseline_ref, "physical_hardware_tested": False, "cases": cases} + (OUT / "RESULT.json").write_text(json.dumps(record, indent=2) + "\n") + print(f"PASS runner failure status: {len(cases)} actual entrypoints; baseline={args.baseline_ref or 'current'}") + + +if __name__ == "__main__": + run_check(main, OUT) diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/scripts/offline_check.py b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/scripts/offline_check.py new file mode 100644 index 0000000..2b02125 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/scripts/offline_check.py @@ -0,0 +1,23 @@ +"""离线检查启动时撤销旧 PASS，失败时保存本轮状态。""" + +import json +from pathlib import Path + + +def run_check(main, directory): + directory = Path(directory) + directory.mkdir(parents=True, exist_ok=True) + result = directory / "RESULT.json" + + def publish(record): + temporary = result.with_suffix(".tmp") + temporary.write_text(json.dumps(record, indent=2) + "\n", encoding="utf-8") + temporary.replace(result) + + publish({"result": "RUNNING", "physical_hardware_tested": False}) + try: + main() + except (Exception, KeyboardInterrupt) as error: + publish({"result": "FAILED", "physical_hardware_tested": False, + "error_type": type(error).__name__, "error": str(error)}) + raise diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/tests/PLATFORM_PORTS_MANIFEST.json b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/tests/PLATFORM_PORTS_MANIFEST.json new file mode 100644 index 0000000..3c892d5 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/tests/PLATFORM_PORTS_MANIFEST.json @@ -0,0 +1,7 @@ +{ + "source_core_sha256": "31e7e07f94d08208dbb564edf9546240df26ff834935bfb646b71b541d875fb9", + "port_header_sha256": "3329804932f5a7632f78bbe56797f9bff35fb6f94910f0a474c59a9a0a90bf5d", + "stub_sha256": "e4c06220cd7025972d432b06c452e85c62bd2cfccad618b2b993499b62e6621a", + "cpu_behavior_included": false, + "port_header_hash_encoding": "UTF-8 with LF newlines" +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/tests/ToyLinuxChipPorts.sv b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/tests/ToyLinuxChipPorts.sv new file mode 100644 index 0000000..6e07c67 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/tests/ToyLinuxChipPorts.sv @@ -0,0 +1,134 @@ +// Port-only fixture from the Chisel-generated core; no CPU behavior. +// Outputs idle at zero. The testbench drives the real platform AXI port. +module ToyLinuxChip( + input clock, + reset, + interrupt, + memory_aw_ready, + output memory_aw_valid, + output [3:0] memory_aw_bits_id, + output [31:0] memory_aw_bits_addr, + output [7:0] memory_aw_bits_len, + output [2:0] memory_aw_bits_size, + output [1:0] memory_aw_bits_burst, + output memory_aw_bits_lock, + output [3:0] memory_aw_bits_cache, + output [2:0] memory_aw_bits_prot, + output [3:0] memory_aw_bits_qos, + input memory_w_ready, + output memory_w_valid, + output [127:0] memory_w_bits_data, + output [15:0] memory_w_bits_strb, + output memory_w_bits_last, + memory_b_ready, + input memory_b_valid, + input [3:0] memory_b_bits_id, + input [1:0] memory_b_bits_resp, + input memory_ar_ready, + output memory_ar_valid, + output [3:0] memory_ar_bits_id, + output [31:0] memory_ar_bits_addr, + output [7:0] memory_ar_bits_len, + output [2:0] memory_ar_bits_size, + output [1:0] memory_ar_bits_burst, + output memory_ar_bits_lock, + output [3:0] memory_ar_bits_cache, + output [2:0] memory_ar_bits_prot, + output [3:0] memory_ar_bits_qos, + output memory_r_ready, + input memory_r_valid, + input [3:0] memory_r_bits_id, + input [127:0] memory_r_bits_data, + input [1:0] memory_r_bits_resp, + input memory_r_bits_last, + peripherals_aw_ready, + output peripherals_aw_valid, + output [1:0] peripherals_aw_bits_id, + output [30:0] peripherals_aw_bits_addr, + output [7:0] peripherals_aw_bits_len, + output [2:0] peripherals_aw_bits_size, + output [1:0] peripherals_aw_bits_burst, + output peripherals_aw_bits_lock, + output [3:0] peripherals_aw_bits_cache, + output [2:0] peripherals_aw_bits_prot, + output [3:0] peripherals_aw_bits_qos, + input peripherals_w_ready, + output peripherals_w_valid, + output [63:0] peripherals_w_bits_data, + output [7:0] peripherals_w_bits_strb, + output peripherals_w_bits_last, + peripherals_b_ready, + input peripherals_b_valid, + input [1:0] peripherals_b_bits_id, + peripherals_b_bits_resp, + input peripherals_ar_ready, + output peripherals_ar_valid, + output [1:0] peripherals_ar_bits_id, + output [30:0] peripherals_ar_bits_addr, + output [7:0] peripherals_ar_bits_len, + output [2:0] peripherals_ar_bits_size, + output [1:0] peripherals_ar_bits_burst, + output peripherals_ar_bits_lock, + output [3:0] peripherals_ar_bits_cache, + output [2:0] peripherals_ar_bits_prot, + output [3:0] peripherals_ar_bits_qos, + output peripherals_r_ready, + input peripherals_r_valid, + input [1:0] peripherals_r_bits_id, + input [63:0] peripherals_r_bits_data, + input [1:0] peripherals_r_bits_resp, + input peripherals_r_bits_last +); + assign memory_aw_valid = '0; + assign memory_aw_bits_id = '0; + assign memory_aw_bits_addr = '0; + assign memory_aw_bits_len = '0; + assign memory_aw_bits_size = '0; + assign memory_aw_bits_burst = '0; + assign memory_aw_bits_lock = '0; + assign memory_aw_bits_cache = '0; + assign memory_aw_bits_prot = '0; + assign memory_aw_bits_qos = '0; + assign memory_w_valid = '0; + assign memory_w_bits_data = '0; + assign memory_w_bits_strb = '0; + assign memory_w_bits_last = '0; + assign memory_b_ready = '0; + assign memory_ar_valid = '0; + assign memory_ar_bits_id = '0; + assign memory_ar_bits_addr = '0; + assign memory_ar_bits_len = '0; + assign memory_ar_bits_size = '0; + assign memory_ar_bits_burst = '0; + assign memory_ar_bits_lock = '0; + assign memory_ar_bits_cache = '0; + assign memory_ar_bits_prot = '0; + assign memory_ar_bits_qos = '0; + assign memory_r_ready = '0; + assign peripherals_aw_valid = '0; + assign peripherals_aw_bits_id = '0; + assign peripherals_aw_bits_addr = '0; + assign peripherals_aw_bits_len = '0; + assign peripherals_aw_bits_size = '0; + assign peripherals_aw_bits_burst = '0; + assign peripherals_aw_bits_lock = '0; + assign peripherals_aw_bits_cache = '0; + assign peripherals_aw_bits_prot = '0; + assign peripherals_aw_bits_qos = '0; + assign peripherals_w_valid = '0; + assign peripherals_w_bits_data = '0; + assign peripherals_w_bits_strb = '0; + assign peripherals_w_bits_last = '0; + assign peripherals_b_ready = '0; + assign peripherals_ar_valid = '0; + assign peripherals_ar_bits_id = '0; + assign peripherals_ar_bits_addr = '0; + assign peripherals_ar_bits_len = '0; + assign peripherals_ar_bits_size = '0; + assign peripherals_ar_bits_burst = '0; + assign peripherals_ar_bits_lock = '0; + assign peripherals_ar_bits_cache = '0; + assign peripherals_ar_bits_prot = '0; + assign peripherals_ar_bits_qos = '0; + assign peripherals_r_ready = '0; +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/tests/axi_smoke_memory.sv b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/tests/axi_smoke_memory.sv new file mode 100644 index 0000000..f8e7dc6 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/tests/axi_smoke_memory.sv @@ -0,0 +1,115 @@ +// Single outstanding read and write, with independent AXI channels. +// Backpressure is legal: W is accepted after AW; R/B are held until accepted. +module axi_smoke_memory #( + parameter DATA_BITS=128, ID_BITS=4, ADDR_BITS=32, + parameter BASE=32'h80000000, CAPACITY=262144, + parameter IMAGE="", parameter MONITOR=0, + parameter TEST_LABEL="whole Toy CPU smoke" +) ( + input clock, reset, + output aw_ready, input aw_valid, + input [ID_BITS-1:0] aw_bits_id, + input [ADDR_BITS-1:0] aw_bits_addr, + input [7:0] aw_bits_len, input [2:0] aw_bits_size, + input [1:0] aw_bits_burst, + output w_ready, input w_valid, + input [DATA_BITS-1:0] w_bits_data, + input [DATA_BITS/8-1:0] w_bits_strb, input w_bits_last, + input b_ready, output reg b_valid, + output reg [ID_BITS-1:0] b_bits_id, output [1:0] b_bits_resp, + output ar_ready, input ar_valid, + input [ID_BITS-1:0] ar_bits_id, + input [ADDR_BITS-1:0] ar_bits_addr, + input [7:0] ar_bits_len, input [2:0] ar_bits_size, + input [1:0] ar_bits_burst, + input r_ready, output reg r_valid, + output reg [ID_BITS-1:0] r_bits_id, + output reg [DATA_BITS-1:0] r_bits_data, + output [1:0] r_bits_resp, output reg r_bits_last +); + localparam LANES=DATA_BITS/8; + reg [7:0] mem [0:CAPACITY-1]; + reg write_active; + reg [ADDR_BITS-1:0] write_addr, read_addr; + reg [7:0] write_remaining, read_remaining; + reg [2:0] write_size, read_size; + reg [3:0] stall_cycle; + integer read_bursts, write_bursts; + assign aw_ready = !write_active && !b_valid && stall_cycle[1:0]!=0; + assign w_ready = write_active && !b_valid && stall_cycle[2:0]!=0; + assign ar_ready = !r_valid && stall_cycle[1:0]!=1; + assign b_bits_resp = 0; + assign r_bits_resp = 0; + + initial begin + for (integer i=0; iCAPACITY) + $fatal(1,"AXI read out of range: %h",addr); + for (integer lane=0; laneCAPACITY) + $fatal(1,"AXI write out of range: %h",write_addr); + if (w_bits_last != (write_remaining==0)) $fatal(1,"WLAST mismatch"); + for (integer lane=0; lane=0;n=n-1) c=(c<<1)^((c[15]^value[n]) ? 16'h1021 : 16'd0); + crc_step=c; + end + endfunction + task automatic byte_send(input [7:0] value); + begin @(negedge clk);rx_data=value;rx_valid=1;@(negedge clk);rx_valid=0;end + endtask + task automatic request(input [7:0] op,input [31:0] address,input [15:0] length,input bit corrupt); + reg [15:0] crc; + reg [7:0] value; + begin + received=0;crc=16'hffff; + byte_send(8'ha5);byte_send(8'h5a); + byte_send(op);crc=crc_step(crc,op); + byte_send(8'h37);crc=crc_step(crc,8'h37); + for(integer n=0;n<4;n=n+1) begin + value=address>>(n*8);byte_send(value);crc=crc_step(crc,value); + end + byte_send(length[7:0]);crc=crc_step(crc,length[7:0]); + byte_send(length[15:8]);crc=crc_step(crc,length[15:8]); + if(op==1) for(integer n=0;n>(addr[2:0]*8) & 255)!==expected) + $fatal(1,"SCU read addr=%h data=%h resp=%h",addr,rdata,rresp); + @(negedge clk); + end + rready=1;@(negedge clk);rready=0; + end + endtask + initial begin + repeat(4) @(negedge clk);reset=0; + @(negedge clk);rx_data=8'h71;rx_valid=1;@(negedge clk);rx_valid=0; + read_byte(31'h60020005,1,0); + if(!interrupt) $fatal(1,"RX IRQ missing"); + read_byte(31'h60020004,8'h71,0); + if(interrupt) $fatal(1,"RX not popped exactly once"); + read_byte(31'h60020005,0,0); + // A whole pasted command must survive a long interval between SBI polls. + for(integer j=0;j<200;j=j+1) begin + @(negedge clk);rx_data=j;rx_valid=1;@(negedge clk);rx_valid=0; + end + if(dut.overflow) $fatal(1,"FIFO overflow on a 200-byte paste"); + for(integer j=0;j<200;j=j+1) read_byte(31'h60020004,j[7:0],0); + if(interrupt) $fatal(1,"FIFO not drained after paste"); + read_byte(31'h60030000,0,2); + @(negedge clk);awaddr=31'h60020000;awid=3;awvalid=1; + @(negedge clk);awvalid=0;wdata=64'h53;wstrb=1;wvalid=1; + repeat(10) begin @(negedge clk);if(wready || bvalid) $fatal(1,"SCU lost TX backpressure");end + tx_ready=1;@(negedge clk);wvalid=0; + repeat(4) @(negedge clk); + if(!bvalid || bid!==3 || bresp!==0 || tx_count!=1) $fatal(1,"SCU TX response/count"); + bready=1;@(negedge clk);bready=0; + awaddr=31'h60000000;awsize=2;awvalid=1;@(negedge clk);awvalid=0; + wdata=64'h12345678;wstrb=15;wvalid=1;@(negedge clk);wvalid=0; + if(!exited || exit_code!==32'h12345678) $fatal(1,"SCU EXIT decode"); + $display("PASS SCU OpenSBI byte addresses, AXI lanes, RX pop/IRQ, TX backpressure, EXIT");$finish; + end + initial begin #100000;$fatal(1,"SCU watchdog");end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/tests/tb_platform_bresp.sv b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/tests/tb_platform_bresp.sv new file mode 100644 index 0000000..f3c0490 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/sources/tests/tb_platform_bresp.sv @@ -0,0 +1,58 @@ +`timescale 1ns/1ps +module tb_platform_bresp; + reg clk=0; + always #5 clk=~clk; + reg reset=1; + reg [30:0] address=0; + reg [2:0] size=2; + reg [7:0] length=0; + reg awvalid=0,wvalid=0,last=1,bready=0; + toy_a7_platform dut(.clk(clk),.reset(reset),.uart_rx_in(1'b1), + .ddr_awready(1'b1),.ddr_wready(1'b1),.ddr_bid(4'd0),.ddr_bresp(2'd0),.ddr_bvalid(1'b0), + .ddr_arready(1'b1),.ddr_rid(4'd0),.ddr_rdata(128'd0),.ddr_rresp(2'd0),.ddr_rlast(1'b1),.ddr_rvalid(1'b0), + .flash_miso(1'b0),.flash_recovery(1'b0)); + task automatic write_case(input [30:0] addr,input [2:0] width,input [7:0] len,input [1:0] expected); + @(negedge clk);address=addr;size=width;length=len;awvalid=1; + do @(posedge clk);while(!dut.peripherals_aw_ready); + @(negedge clk);awvalid=0; + for(integer beat=0;beat<=len;beat=beat+1) begin + wvalid=1;last=beat==len; + do @(posedge clk);while(!dut.peripherals_w_ready); + @(negedge clk);wvalid=0; + end + while(!dut.peripherals_b_valid) @(negedge clk); + repeat(5) begin + // Observe the CPU input, through actual platform wiring and real SCU. + if(dut.chip.peripherals_b_valid!==1 || dut.chip.peripherals_b_bits_resp!==expected || + dut.chip.peripherals_b_bits_id!==2) + $fatal(1,"Platform B response addr=%h valid=%b id=%b actual=%b expected=%b",addr, + dut.chip.peripherals_b_valid,dut.chip.peripherals_b_bits_id,dut.chip.peripherals_b_bits_resp,expected); + @(negedge clk); + end + bready=1;@(negedge clk);bready=0; + if(dut.chip.peripherals_b_valid!==0) $fatal(1,"BVALID not cleared after handshake"); + endtask + initial begin + force dut.cpu_run=1; + force dut.peripherals_aw_valid=awvalid; + force dut.peripherals_aw_bits_addr=address; + force dut.peripherals_aw_bits_size=size; + force dut.peripherals_aw_bits_len=length; + force dut.peripherals_aw_bits_id=2; + force dut.peripherals_aw_bits_burst=1; + force dut.peripherals_w_valid=wvalid; + force dut.peripherals_w_bits_last=last; + force dut.peripherals_w_bits_data=64'h13572468; + force dut.peripherals_w_bits_strb=8'h0f; + force dut.peripherals_b_ready=bready; + repeat(5) @(negedge clk);reset=0; + write_case(31'h60000000,2,0,0); + if(!dut.exited || dut.exit_code!==32'h13572468) $fatal(1,"Valid MMIO changed"); + write_case(31'h60030000,2,0,2); + write_case(31'h60000002,2,0,2); + write_case(31'h60000000,2,1,2); + $display("PASS platform AXI B response: valid, invalid address, unaligned, burst, ID and backpressure"); + $finish; + end + initial begin #100000;$fatal(1,"Platform response watchdog");end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/stale-baseline/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/stale-baseline/RESULT.json new file mode 100644 index 0000000..f1bd18b --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/stale-baseline/RESULT.json @@ -0,0 +1,28 @@ +{ + "result": "PASS_EXPECTED_STALE_BASELINE", + "baseline_ref": "9fdcec6941e75282f7c2e8318d347168e034c343", + "physical_hardware_tested": false, + "cases": [ + { + "script": "check_board.py", + "source_sha256": "e3618121401bd811eac50c017a016d3a548cdc004f8a47b01ae74466f02a786c", + "exit_code": 1, + "observed_result": "PASS", + "result": "PASS" + }, + { + "script": "check_programming_scripts.py", + "source_sha256": "b91b146da58df41b8453a61fd8eaf87e7314d56a8e8fff327270cb3dbed10f10", + "exit_code": 1, + "observed_result": "PASS_OFFLINE_TCL_CONTRACTS", + "result": "PASS" + }, + { + "script": "check_flash_guards.py", + "source_sha256": "42129a0be9f1399fac294799294fea791a83004463f9391f77b18c3d828e2535", + "exit_code": 1, + "observed_result": "PASS_FLASH_GUARDS_NORMAL_AND_OPTIMIZED", + "result": "PASS" + } + ] +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/stale-baseline/check_board.py.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/stale-baseline/check_board.py.log new file mode 100644 index 0000000..b6cf6b4 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/stale-baseline/check_board.py.log @@ -0,0 +1,8 @@ +Traceback (most recent call last): + File "D:\Verilog_Dev\fpga-arty-a7-pr10-review\platforms\arty-a7-toy\build\runner-status-check\tmprr247ah_\scripts\check_board.py", line 76, in + main() + File "D:\Verilog_Dev\fpga-arty-a7-pr10-review\platforms\arty-a7-toy\build\runner-status-check\tmprr247ah_\scripts\check_board.py", line 27, in main + raise ValueError("CPU port fixture differs from its manifest") +ValueError: CPU port fixture differs from its manifest + +OBSERVED_RESULT {"result": "PASS"} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/stale-baseline/check_flash_guards.py.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/stale-baseline/check_flash_guards.py.log new file mode 100644 index 0000000..a1b3f9c --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/stale-baseline/check_flash_guards.py.log @@ -0,0 +1,10 @@ +Traceback (most recent call last): + File "D:\Verilog_Dev\fpga-arty-a7-pr10-review\platforms\arty-a7-toy\build\runner-status-check\tmpkggxjhnt\scripts\check_flash_guards.py", line 47, in + main() + File "D:\Verilog_Dev\fpga-arty-a7-pr10-review\platforms\arty-a7-toy\build\runner-status-check\tmpkggxjhnt\scripts\check_flash_guards.py", line 37, in main + result.check_returncode() + File "D:\python\lib\subprocess.py", line 457, in check_returncode + raise CalledProcessError(self.returncode, self.args, self.stdout, +subprocess.CalledProcessError: Command '['D:\\python\\python.exe', 'D:\\Verilog_Dev\\fpga-arty-a7-pr10-review\\platforms\\arty-a7-toy\\build\\runner-status-check\\tmpkggxjhnt\\tests\\flash_guard_probe.py', 'D:\\Verilog_Dev\\fpga-arty-a7-pr10-review\\platforms\\arty-a7-toy\\build\\runner-status-check\\tmpkggxjhnt\\host\\flash.py', 'D:\\Verilog_Dev\\fpga-arty-a7-pr10-review\\platforms\\arty-a7-toy\\build\\runner-status-check\\tmpkggxjhnt\\build\\flash-guard-check\\tmpjayzjn7t\\chip.bit', 'D:\\Verilog_Dev\\fpga-arty-a7-pr10-review\\platforms\\arty-a7-toy\\build\\runner-status-check\\tmpkggxjhnt\\build\\flash-guard-check\\tmpjayzjn7t\\payload.bin', 'D:\\Verilog_Dev\\fpga-arty-a7-pr10-review\\platforms\\arty-a7-toy\\build\\runner-status-check\\tmpkggxjhnt\\build\\flash-guard-check\\tmpjayzjn7t\\image.mcs', 'D:\\Verilog_Dev\\fpga-arty-a7-pr10-review\\platforms\\arty-a7-toy\\build\\runner-status-check\\tmpkggxjhnt\\build\\flash-guard-check\\tmpjayzjn7t\\run', 'accept']' returned non-zero exit status 1. + +OBSERVED_RESULT {"result": "PASS_FLASH_GUARDS_NORMAL_AND_OPTIMIZED"} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/stale-baseline/check_programming_scripts.py.log b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/stale-baseline/check_programming_scripts.py.log new file mode 100644 index 0000000..696200f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/stale-baseline/check_programming_scripts.py.log @@ -0,0 +1,12 @@ +Traceback (most recent call last): + File "D:\Verilog_Dev\fpga-arty-a7-pr10-review\platforms\arty-a7-toy\build\runner-status-check\tmpyiwyqd9q\scripts\check_programming_scripts.py", line 56, in + main() + File "D:\Verilog_Dev\fpga-arty-a7-pr10-review\platforms\arty-a7-toy\build\runner-status-check\tmpyiwyqd9q\scripts\check_programming_scripts.py", line 40, in main + raise ValueError(f"Documented success return rejected: {script}: {transcript}") +ValueError: Documented success return rejected: program_arty.tcl: Traceback (most recent call last): + File "D:\Verilog_Dev\fpga-arty-a7-pr10-review\platforms\arty-a7-toy\build\runner-status-check\tmpyiwyqd9q\tests\mock_programming.tcl", line 1, in + raise RuntimeError('INJECTED_CHECK_FAILURE') +RuntimeError: INJECTED_CHECK_FAILURE + + +OBSERVED_RESULT {"result": "PASS_OFFLINE_TCL_CONTRACTS"} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/stale-baseline/sources/scripts/check_board.py b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/stale-baseline/sources/scripts/check_board.py new file mode 100644 index 0000000..e6ceeaf --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/stale-baseline/sources/scripts/check_board.py @@ -0,0 +1,76 @@ +"""Test the exact board loader, AXI normalizer and OpenSBI SCU with stalls.""" +import hashlib +import json +from pathlib import Path +import subprocess + +ROOT=Path(__file__).resolve().parents[1] +OUT=ROOT/"build/board-unit" + + +def run(name, files, marker): + executable=OUT/name + command=["iverilog","-g2012","-s",name,"-o",str(executable)]+[str(f) for f in files] + compiled=subprocess.run(command,capture_output=True,text=True,timeout=60) + (OUT/(name+"-compile.log")).write_text(compiled.stdout+compiled.stderr) + compiled.check_returncode() + result=subprocess.run(["vvp",str(executable)],capture_output=True,text=True,timeout=60) + (OUT/(name+".log")).write_text(result.stdout+result.stderr) + print(result.stdout,end="") + result.check_returncode() + assert marker in result.stdout + + +def main(): + fixture=json.loads((ROOT/"tests/PLATFORM_PORTS_MANIFEST.json").read_text()) + if hashlib.sha256((ROOT/"tests/ToyLinuxChipPorts.sv").read_bytes()).hexdigest()!=fixture["stub_sha256"]: + raise ValueError("CPU port fixture differs from its manifest") + OUT.mkdir(parents=True,exist_ok=True) + run("tb_axi_fullwidth",[ROOT/"board/axi_fullwidth.sv",ROOT/"tests/axi_smoke_memory.sv",ROOT/"tests/tb_axi_fullwidth.sv"],"PASS fullwidth AXI") + run("tb_axi_scu",[ROOT/"board/axi_scu.sv",ROOT/"tests/tb_axi_scu.sv"],"PASS SCU") + platform_files=[ROOT/"board"/name for name in + ("toy_a7_platform.sv","axi_fullwidth.sv","axi_scu.sv","ddr_uart_loader.sv", + "loader_axi.sv","uart_rx.sv","uart_tx.sv","flash_spi_byte.sv")] + run("tb_platform_bresp",platform_files+[ROOT/"tests/ToyLinuxChipPorts.sv",ROOT/"tests/tb_platform_bresp.sv"], + "PASS platform AXI B response") + # Retain the CRC/range/timeout/rejected RUN oracle from the earlier loader, + # but connect its new acknowledgement boundary to AXI, not zero-latency RAM. + template=(ROOT/"tests/board_loader_template.sv").read_text() + template=template.replace("module tb_uart_loader", "module tb_ddr_loader") + template=template.replace("uart_loader #", "ddr_uart_loader #") + template=template.replace("32'h01374150", "32'h02374154") + template=template.replace("axi_bram #(.WORDS(256)) memory(", "/* legacy memory removed\naxi_bram #(.WORDS(256)) memory(") + template=template.replace(" always @(posedge clk) begin\n", "*/\n"+LOADER_MEMORY+"\n always @(posedge clk) begin\n",1) + template=template.replace("wire cpu_run,error_seen,load_en,load_valid;", "wire cpu_run,error_seen,load_en,load_valid,load_error;") + template=template.replace("PASS: UART loader", "PASS: DDR UART loader") + (OUT/"tb_ddr_loader.sv").write_text(template) + run("tb_ddr_loader",[ROOT/"board/ddr_uart_loader.sv",ROOT/"board/loader_axi.sv",ROOT/"tests/axi_smoke_memory.sv",OUT/"tb_ddr_loader.sv"],"PASS: DDR UART loader") + files=[p for p in (ROOT/"board").glob("*.sv")]+[ROOT/"tests/tb_axi_fullwidth.sv",ROOT/"tests/tb_axi_scu.sv"] + files += [ROOT/"tests/ToyLinuxChipPorts.sv",ROOT/"tests/tb_platform_bresp.sv"] + record=dict(result="PASS",tests=4,physical_mig_simulated=False, + sources={str(p.relative_to(ROOT)):hashlib.sha256(p.read_bytes()).hexdigest() for p in files}) + (OUT/"RESULT.json").write_text(json.dumps(record,indent=2)+"\n") + + +LOADER_MEMORY=""" + wire [27:0] awaddr,araddr; + wire awvalid,wvalid,arvalid,bready,rready,awready,wready,arready,bvalid,rvalid; + wire [127:0] wdata,rdata; + wire [15:0] wstrb; + wire [1:0] bresp,rresp; + loader_axi bridge(.clk(clk),.reset(reset),.load_en(load_en),.load_addr({16'd0,load_addr}), + .load_data(load_data),.load_mask(load_mask),.load_valid(load_valid),.load_error(load_error),.load_result(load_result), + .awaddr(awaddr),.araddr(araddr),.awvalid(awvalid),.wvalid(wvalid),.arvalid(arvalid), + .bready(bready),.rready(rready),.awready(awready),.wready(wready),.arready(arready), + .bvalid(bvalid),.rvalid(rvalid),.wdata(wdata),.wstrb(wstrb),.bresp(bresp),.rresp(rresp),.rdata(rdata)); + axi_smoke_memory #(.ADDR_BITS(28),.BASE(0),.CAPACITY(4096)) memory ( + .clock(clk),.reset(reset),.aw_bits_id(4'd0),.aw_bits_addr(awaddr),.aw_bits_len(8'd0),.aw_bits_size(3'd4),.aw_bits_burst(2'd1), + .aw_valid(awvalid),.aw_ready(awready),.w_bits_data(wdata),.w_bits_strb(wstrb),.w_bits_last(1'b1),.w_valid(wvalid),.w_ready(wready), + .b_ready(bready),.b_valid(bvalid),.b_bits_id(),.b_bits_resp(bresp), + .ar_bits_id(4'd0),.ar_bits_addr(araddr),.ar_bits_len(8'd0),.ar_bits_size(3'd4),.ar_bits_burst(2'd1),.ar_valid(arvalid),.ar_ready(arready), + .r_ready(rready),.r_valid(rvalid),.r_bits_id(),.r_bits_data(rdata),.r_bits_resp(rresp),.r_bits_last()); +""" + + +if __name__=="__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/stale-baseline/sources/scripts/check_flash_guards.py b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/stale-baseline/sources/scripts/check_flash_guards.py new file mode 100644 index 0000000..6fcd597 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/stale-baseline/sources/scripts/check_flash_guards.py @@ -0,0 +1,47 @@ +"""验证普通模式与 python -O 下四项预打包镜像校验均有效。""" + +import hashlib +import json +from pathlib import Path +import subprocess +import sys +import tempfile + +ROOT = Path(__file__).resolve().parents[1] + + +def main(): + out = ROOT / "build/flash-guard-check" + out.mkdir(parents=True, exist_ok=True) + cases = [] + for optimized in [False, True]: + for field in [None, "result", "bitstream_sha256", "packed_payload_sha256", "flash_image_sha256"]: + with tempfile.TemporaryDirectory(dir=out) as directory: + work = Path(directory) + bit, payload, mcs = [work / name for name in ["chip.bit", "payload.bin", "image.mcs"]] + for path in [bit, payload, mcs]: + path.write_bytes(path.name.encode()) + sha = lambda path: hashlib.sha256(path.read_bytes()).hexdigest() + record = {"result": "PASS_VIVADO_FLASH_PACK", "bitstream_sha256": sha(bit), + "packed_payload_sha256": sha(payload), "flash_image_sha256": sha(mcs)} + if field: + record[field] = "FAILED" if field == "result" else "0" * 64 + mcs.with_suffix(".mcs.json").write_text(json.dumps(record)) + expected = "reject" if field else "accept" + command = [sys.executable] + (["-O"] if optimized else []) + command += [str(ROOT / "tests/flash_guard_probe.py"), str(ROOT / "host/flash.py"), + str(bit), str(payload), str(mcs), str(work / "run"), expected] + result = subprocess.run(command, capture_output=True, text=True, timeout=20) + name = f"{'optimized' if optimized else 'normal'}-{field or 'valid'}" + (out / f"{name}.log").write_text(result.stdout + result.stderr, encoding="utf-8") + result.check_returncode() + if ("PASS INVALID_IMAGE_BLOCKED" if field else "PASS VALID_IMAGE_REACHED_OFFLINE_BOUNDARY") not in result.stdout: + raise ValueError("Missing guard oracle") + cases.append({"optimized": optimized, "field": field or "valid", "result": "PASS"}) + (out / "RESULT.json").write_text(json.dumps({"result": "PASS_FLASH_GUARDS_NORMAL_AND_OPTIMIZED", + "physical_hardware_tested": False, "cases": cases}, indent=2) + "\n") + print(f"PASS Flash image guards: {len(cases)} normal/-O tamper/control cases; no hardware") + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/stale-baseline/sources/scripts/check_programming_scripts.py b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/stale-baseline/sources/scripts/check_programming_scripts.py new file mode 100644 index 0000000..b64d6f2 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/pr10-selfcheck/stale-baseline/sources/scripts/check_programming_scripts.py @@ -0,0 +1,56 @@ +"""离线注入 Vivado API 返回值、异常与配置状态，检查实际 Tcl 入口。""" + +import argparse +import json +from pathlib import Path +import shutil +import subprocess +import tempfile + +ROOT = Path(__file__).resolve().parents[1] + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--tclsh", default=shutil.which("tclsh")) + args = parser.parse_args() + if not args.tclsh: + raise RuntimeError("Install Tcl or supply --tclsh") + out = ROOT / "build/programming-check" + out.mkdir(parents=True, exist_ok=True) + cases = [] + for script in ["program_arty.tcl", "backup_flash.tcl", "program_flash.tcl"]: + faults = ["none", "device_error", "done_low", "eos_low", "crc_error"] + if script != "program_arty.tcl": + faults += ["readback_error", "short_backup"] + if script == "program_flash.tcl": + faults += ["cfgmem_error"] + for fault in faults: + with tempfile.TemporaryDirectory(dir=out) as directory: + work = Path(directory) + bit = work / "input.bit" + bit.write_bytes(b"offline fixture") + command = [args.tclsh, str(ROOT / "tests/mock_programming.tcl"), + str(ROOT / "board" / script), fault, str(bit), str(work / "backup.bin")] + result = subprocess.run(command, capture_output=True, text=True, timeout=20) + transcript = result.stdout + result.stderr + (out / f"{script}-{fault}.log").write_text(transcript, encoding="utf-8") + if fault == "none": + if result.returncode or "MOCK_SUCCESS" not in transcript: + raise ValueError(f"Documented success return rejected: {script}: {transcript}") + else: + if result.returncode == 0 or "MOCK_FAILURE" not in transcript: + raise ValueError(f"Injected failure accepted: {script}/{fault}") + if "PASS FLASH_PROGRAM_VERIFY" in transcript or "ARTY_JTAG_PROGRAMMED:" in transcript: + raise ValueError("False success marker") + if fault != "cfgmem_error" and "program_flash" in transcript.split("MOCK_EVENTS", 1)[1].splitlines()[0]: + raise ValueError("Flash programming reached after an earlier failure") + cases.append({"script": script, "fault": fault, "result": "PASS"}) + record = {"result": "PASS_OFFLINE_TCL_CONTRACTS", "physical_hardware_tested": False, + "cases": cases} + (out / "RESULT.json").write_text(json.dumps(record, indent=2) + "\n") + print(f"PASS programming scripts: {len(cases)} documented-return/status/error cases; no hardware") + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/BOARD_REGRESSION.json b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/BOARD_REGRESSION.json new file mode 100644 index 0000000..79e2fd2 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/BOARD_REGRESSION.json @@ -0,0 +1,41 @@ +{ + "result": "PASS", + "tests": { + "cpu": { + "result": "PASS", + "test": "cpu", + "binary_sha256": "3bbf33f7bf2b6bb0f3888ab4a649a11272de3f74458f6ea36b266f9670df75f5", + "original_cpu_oracle": true, + "ddr_phy_simulated": false, + "physical_linux_boot_tested": false, + "cycles": 709434 + }, + "gemmini": { + "result": "PASS", + "test": "gemmini", + "binary_sha256": "d6307d194aadb9f23e14edf695ce98ab1ea361881237576b15c251573af2826e", + "original_cpu_oracle": true, + "ddr_phy_simulated": false, + "physical_linux_boot_tested": false, + "cycles": 251063 + }, + "loop": { + "result": "PASS", + "test": "loop", + "binary_sha256": "bbe9646dc565ac9ac1188c6b3d53d24b1b37985ee158ee2ac918df04c3267ce2", + "original_cpu_oracle": true, + "ddr_phy_simulated": false, + "physical_linux_boot_tested": false, + "cycles": 684219 + }, + "dma": { + "result": "PASS", + "test": "dma", + "binary_sha256": "082965476d4dcc98cc556b8f79fa2fdf659cea501665e207d04349d40469e9d2", + "original_cpu_oracle": true, + "ddr_phy_simulated": false, + "physical_linux_boot_tested": false, + "cycles": 1914839 + } + } +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/INPUTS.json b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/INPUTS.json new file mode 100644 index 0000000..ad63b47 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/INPUTS.json @@ -0,0 +1,180 @@ +{ + "source_commit": "5d20e94e6c85cce7f09424749cb9d0117023e000", + "files": { + "UPSTREAM_MANIFEST.json": "c4a96343e318c452420cf86b34d6008140560eeffa91cd85b4b87b229717c9be", + "board/README.md": "5a7f01460107df0c5c40d2a2b18c68648ca2d7b20c914c788b880ec1b9f6f95b", + "board/SOURCE_MANIFEST.json": "03d99f1f43bbf68d92df61db52bdee0019723e2e194ee5f9c12a5ac6d4c5a105", + "board/arty_a7.xdc": "f13869ba386038557084adabafeb5255943d0b67f1db4b88fd907e4f095d016f", + "board/axi_fullwidth.sv": "bf07ae27724dbd0a361d732dfb57109f06beef207c47a066d400cb06d7f07d5a", + "board/axi_scu.sv": "ee77bf641d61811b4c1faea845752850c22461a63b4cdfd3d6f9cd223e6c2fc2", + "board/backup_flash.tcl": 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"read_latency": 0, + "same_address_write_priority": "W1", + "added_cycles": 0, + "adapter_sha256": "bbc9ad168c94204a946b3e107115fae7f6042fd6c7f95807d7af367449e28950" + } + ] +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/REPORT.md b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/REPORT.md new file mode 100644 index 0000000..d21839c --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/REPORT.md @@ -0,0 +1,66 @@ +# ROB 优化与 PR10 修复：完整实现和 RTL 验证 + +## 结果与产物 + +本轮采用用户选择的 **ROB 操作数 BRAM + PR10 接口/烧录修复**。两个分支在 +`61f4b02` 合并，实际构建输入提交为 `5d20e94`。Chisel 重新生成的核心和存储器 +分别与已测 ROB 候选的 `31e7…fb9`、`d5a3…054` 摘要一致；板级源码使用新响应修复。 +完整实现和下列 RTL 回归通过，位流为 UART/JTAG **工程预发布**。 + +| 项目 | 布线后结果 | +|---|---:| +| 物理 LUT / FF | 53,929 / 33,943 | +| Slice | 15,579 / 15,850（98.29%） | +| BRAM tile / DSP | 31 / 117 | +| WNS / WHS | +1.276 ns / +0.012 ns | +| TNS / THS、布线错误 | 0 / 0、0 | +| Error/Critical DRC、Critical CDC | 0、0 | +| 普通 DRC | 360 项，保留原文 | + +整板用 Vivado 2024.1，原 25 MHz 约束、原综合/布线策略，不降低 DRC 等级。 +实现 1,415.052 秒；timeout 3,600 秒，15 秒强制终止宽限。其他长阶段也有一小时上限， +编译/仿真子进程另设更短超时。资源、周期及警告与旧记录分别比较，不混用 UART/Flash 目标。 + +位流 SHA256：`9f6f684361c049527fda09818cc8aa464f1067b75f3762305a27c5c738295942`。 +软件采用原标准 Linux/Gemmini 镜像，25,797,640 字节，SHA256： +`e2282b5a7ddf1aa01579919aa92df483ed79e739bf5d39530e07532e164118b0`。 +下载入口见平台根目录的 [下载说明](../../../ROB_PR10_DOWNLOADS.md)。 + +## 功能验证 + +- ROB RAM/寄存器逐周期比较；七类存储器与原 Chisel 模块、独立 scoreboard 全深度/掩码比较。 +- PE 原版/LUT/DSP 逐周期比较及量化器形式证明；FMA 三精度原管对照；舍入移位、FPU RF、 + 并发 group query、SubROB 流式行与路由检查通过。 +- 真实 CPU 全芯片回归：CPU、原 13 项 Gemmini、OS/WS 分块循环、非对齐/跨页 DMA、两组 + 各 64 项舍入/移位边界，以及 1,536 项 H/S/D 浮点向量；独立 FMA 基线比较也通过。 +- 真实板级 AXI/SCU 的 CPU/Gemmini/loop/DMA 周期分别为 709,434、251,063、684,219、 + 1,914,839，与旧 ROB 同条件基线一致。 +- UART RTL 不预加载 DDR、不强制释放 CPU，完整加载/读回 110,592 字节后验证 RUN， + 再执行原 CPU 程序，61,853,990 周期通过。 +- 最新标准镜像启动 OpenSBI/Linux，UART 输入命令，COW、页面保护、FP64 进程上下文、 + 定时器、系统检查通过，340,774,843 周期。镜像大于旧 ROB Linux RTL 用例，不据此比较性能。 +- 实际 Xilinx AXI Clock Converter IP 仿真通过 90 个读 beat 及不同大小、并发、背压和边界。 + 四组接口、20 项 Tcl、10 项普通/-O 镜像校验、入口失败状态及 RTL 注入反测再次通过。 + +## MMIO 观察与验收边界 + +补充用例由真实 CPU 发起非法 MMIO 读写，检查 SLVERR 完整传到 CPU AXI 输入；旧平台 +反测按预期失败。该用例观察到 **0 个同步 trap**。现有 Rocket 非阻塞缓存不保证把外设 +总线错误转为同步访问异常，不能将两位响应修复等同于完整物理总线错误保护。此行为 +与 Linux 已验证的虚拟内存页面保护路径不同；没有为通过测试而修改缓存或放宽总线断言。 + +用户确认本轮无法接板卡，选择先上传实现/RTL 验证的工程预发布。因此没有本轮实物、 +真实 DDR PHY 或 Flash 冷启动资格，旧硬件记录保持历史原字节，不继承其结论。 +Xilinx FIFO 行为模型不模拟真实同步延迟；静态 CDC 与 IP 功能仿真不能替代实物验证。 +整模型推理、长期 DDR 压力和环境稳定性尚未验收。 + +## 复现和证据 + +`RESULT.json` 汇总精确摘要、范围、资源和时间；`INPUTS.json`/`sources/` 绑定实际输入， +`implementation/` 保存全部实现原文，`tests/` 保存成功回归及有用的预期失败反例。 +最新软件源与构建记录仍在原 Linux/Gemmini 档案。生成的大型 RTL/位流提供于下载包， +Linux 的 payload.hex 可从固定摘要的二进制重新生成，避免重复存入 Git。 + +`run-fullcheck.sh` 是本次实际命令顺序，`toolchain.sh` 记录已安装工具路径；换机器时 +配置同版本工具，并用脚本的 `--repository`、`--baseline-core` 参数指定自己的只读输入。 +使用 `scripts/elaborate_rob_candidate.sh` 显式启用 RAM；默认生成仍保留原寄存器配置。 diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/RESULT.json new file mode 100644 index 0000000..56df9fd --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/RESULT.json @@ -0,0 +1,90 @@ +{ + "result": "PASS_ROB_PR10_FULL_VALIDATION", + "source_commit": "5d20e94e6c85cce7f09424749cb9d0117023e000", + "part": "xc7a100tcsg324-1", + "profile": "ROB_OPERAND_BRAM_WITH_PR10_FIXES", + "core_clock_hz": 25000000, + "uart_baud": 1000000, + "core_rtl_sha256": "31e7e07f94d08208dbb564edf9546240df26ff834935bfb646b71b541d875fb9", + "memory_rtl_sha256": "d5a37896aee19c8d4931c87dc9683861abf32f096a1c1441f4362370d3d7b054", + "bitstream_sha256": "9f6f684361c049527fda09818cc8aa464f1067b75f3762305a27c5c738295942", + "payload_sha256": "e2282b5a7ddf1aa01579919aa92df483ed79e739bf5d39530e07532e164118b0", + "payload_bytes": 25797640, + "routed_resources": { + "LUT": 53929.0, + "FF": 33943.0, + "Slice": 15579.0, + "BRAM_tiles": 31.0, + "DSP": 117.0 + }, + "timing": { + "wns_ns": 1.276, + "whs_ns": 0.012, + "tns_ns": 0.0, + "ths_ns": 0.0 + }, + "route_errors": 0, + "critical_drc": 0, + "critical_cdc": 0, + "ordinary_drc_violations": 360, + "implementation_seconds": 1415.051698583, + "build_timeout_seconds": 3600, + "board_sources": { + "board/make_flash_image.tcl": "69a70d18a519f8fa156981e9ab024dce5c7bc91733c5b6cf3b9045658415334b", + "board/SOURCE_MANIFEST.json": "03d99f1f43bbf68d92df61db52bdee0019723e2e194ee5f9c12a5ac6d4c5a105", + "board/loader_axi.sv": "05609b0870054ea675aedb406f6215cd456f18db6d6428b461cbae03d9a662f4", + "board/flash_spi_byte.sv": "4d1fac5238f31fb3a69a58d1aca9ccec722e833d788113b94d86c6a1b861045a", + "board/README.md": "5a7f01460107df0c5c40d2a2b18c68648ca2d7b20c914c788b880ec1b9f6f95b", + "board/uart_rx.sv": "0b35263884577324f146ff7fd516e5b561dcc8787e0d8ad599669bac1958406d", + "board/program_arty.tcl": "8af4c07627910536079eb4be647c6f0f447882950588c40588cdc571a72133ac", + "board/arty_a7.xdc": "f13869ba386038557084adabafeb5255943d0b67f1db4b88fd907e4f095d016f", + "board/toy_a7_top.sv": "c8af97f543b8ae5d6dc21a85ba13b16a28fe3ba5bf93f8051c9e38c99f3350bd", + "board/backup_flash.tcl": "fa9185afad3537bf15b4f2f0c952a4eebf9d6c5693619819ff5e57897ce6a86d", + "board/ddr_uart_loader.sv": "980f4cd2e3fa2a00b66143f879bc749ed952c2c1e54331460821bac0300c43d6", + "board/program_flash.tcl": "f9bf2b6fc6c9fdd268c308f417831c94707b464bbae75a5d2cc416f4c92bf424", + "board/axi_scu.sv": "ee77bf641d61811b4c1faea845752850c22461a63b4cdfd3d6f9cd223e6c2fc2", + "board/build_board.tcl": "04f25ca8f6da06b37aec7156ec47def13da0bac88294466b08fb838bc462ba8d", + "board/toy_a7_platform.sv": "f9bc06535b7de19a6b1b501f06effe90519fd43a78e669ab7425d301662540b8", + "board/axi_fullwidth.sv": "bf07ae27724dbd0a361d732dfb57109f06beef207c47a066d400cb06d7f07d5a", + "board/flash_boot.xdc": "bbf9e250ae28dcc4f54d00effd918811f723a7563b4ceacb7b1d03a29151f4ea", + "board/uart_tx.sv": "c20d420fc20be4f6313bdde5abc45ef0b9f8e93bf75350dd9951bc8868b3b65c", + "board/vendor/License.txt": "28a42137bb9c77a6aa931c5ca670134620f448051dbd708a05921280a7b277ba", + "board/vendor/mig.prj": "914a9e4bb1b3002837592944cdf49f8dfbaf4d112552dd8b5be48602ff1ac329", + "board/vendor/preset.xml": "ff95b9b976323fefa588873588dfa2bdce1673759c0a9e91c12ee9f2a2955bce", + "board/vendor/part0_pins.xml": "50aa844aa9c78af6342de68ae3c980f7618716447b28282878d5a106f86fed31", + "board/vendor/board.xml": "5bd9a7ca97ccb2fef617515a14401166464b45a06684d663c0be1a06b02a86df", + "board/vendor/MANIFEST.json": "3fbfac2499bc99a23356873a5d81e0f87d32f02ec1b7929ead51a15f33d9af85" + }, + "physical_hardware_tested": false, + "physical_mig_simulated": false, + "flash_boot_tested": false, + "engineering_prerelease": true, + "linux_cycles": 340774843, + "mmio_observation": { + "result": "PASS_CPU_MMIO_SLVERR", + "physical_hardware_tested": false, + "synchronous_traps_observed": 0, + "synchronous_trap_guaranteed": false, + "invalid_address": "0x60030000", + "required_read_write_response": "10", + "binary_sha256": "d1951159e9fe5dc05adfdb2b35eed6ff37eae04c5c255c1e07c853c9c1fa2247" + }, + "fpu_baseline_rtl": { + "FpgaMemories.sv": "8307d252185ba71a4516d1932d235a5a188816f84a5ed237bb5f3c1281d4b580", + "ToyLinuxChip.sv": "81fb5cbe38d2feb3a9498b0a25f695f2d32468f7ee3fd3368426b079358eb35f" + }, + "checks": { + "interfaces": 4, + "tcl": 20, + "python_guards": 10, + "runner_failure_status": 3, + "mutation_oracles": 3, + "core_units": 6, + "upstream_gemmini_workloads": 13, + "fpu_cpu_vectors": 1536, + "whole_chip_board_regressions": 4, + "linux_system_checks": 5, + "real_cpu_mmio": true, + "real_xilinx_cdc": true + } +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/ROB_RAM_PREPARED.json b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/ROB_RAM_PREPARED.json new file mode 100644 index 0000000..a49e085 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/ROB_RAM_PREPARED.json @@ -0,0 +1,21 @@ +{ + "result": "PREPARED_NOT_VALIDATED", + "architectural_profile_unchanged": true, + "existing_memory_geometry_unchanged": true, + "rob_operand_memory": { + "module_name": "robOperands_ext", + "depth": 16, + "width": 128, + "masked": false, + "read": 1, + "write": 1, + "readwrite": 0, + "extra_ports": [], + "hierarchy": [ + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.accelerators_0.frontend.scheduler.rob.robOperands.robOperands_ext" + ] + }, + "rob_operand_ram_style": "block", + "core_rtl_sha256": "31e7e07f94d08208dbb564edf9546240df26ff834935bfb646b71b541d875fb9", + "memory_rtl_sha256": "d5a37896aee19c8d4931c87dc9683861abf32f096a1c1441f4362370d3d7b054" +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/ToyLinuxChip.profile.json b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/ToyLinuxChip.profile.json new file mode 100644 index 0000000..8207768 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/ToyLinuxChip.profile.json @@ -0,0 +1,73 @@ +{ + "serial_fpga": true, + "gemmini_only_balls": true, + "ball_count": 1, + "ball_names": [ + "GemminiBall" + ], + "ball_ids": [ + 0 + ], + "ball_funct7": [ + 2, + 3, + 53, + 66, + 67, + 80, + 81, + 82, + 83, + 84, + 85, + 86, + 87, + 96, + 97, + 98, + 99, + 100, + 101, + 102, + 103, + 104, + 105 + ], + "ball_read_ports": 2, + "ball_write_ports": 4, + "accelerator_mmio_scale_pool": false, + "compact_caches": true, + "btb_enabled": false, + "icache_bytes": 8192, + "icache_ways": 2, + "dcache_bytes": 8192, + "dcache_mshrs": 1, + "l2_ways": 0, + "coherence_manager": "broadcast", + "rob_entries": 16, + "sub_rob_depth": 8, + "dma_n_xacts": 2, + "dma_max_in_flight": 4, + "tma_read_channels": 1, + "tma_write_channels": 1, + "cpu_mul_unroll": 8, + "gemmini_rows": 8, + "gemmini_columns": 8, + "virtual_bank_count": 16, + "trimmed_optional_peripherals": true, + "scratchpad_bytes": 0, + "cpu_use_debug": false, + "cpu_breakpoints": 0, + "extra_hpm_counters": 0, + "basic_counters": true, + "use_vm": true, + "fpu_shared_fma": true, + "fpu_sfma_latency": 6, + "fpu_dfma_latency": 6, + "fpu_min_flen": 16, + "fpu_flen": 64, + "bank_count": 8, + "bank_rows": 1024, + "bank_width": 64, + "bank_channels": 7 +} \ No newline at end of file diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/RUN.json b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/RUN.json new file mode 100644 index 0000000..3b1a05f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/RUN.json @@ -0,0 +1,71 @@ +{ + "status": "COMPLETED", + "optimization": "ROB_OPERAND_BRAM", + "timeout_seconds": 3600, + "termination_grace_seconds": 15, + "part": "xc7a100tcsg324-1", + "core_sha256": "31e7e07f94d08208dbb564edf9546240df26ff834935bfb646b71b541d875fb9", + "memory_sha256": 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"timeout", + "--signal=TERM", + "--kill-after=15s", + "3600s", + "vivado", + "-mode", + "batch", + "-source", + "/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/build_board.tcl", + "-log", + "/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/vivado.log", + "-journal", + "/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/vivado.jou", + "-tclargs", + "/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921" + ], + "worker_pid": 533570, + "timeout_process_pid": 533573, + "exit_code": 0, + "elapsed_seconds": 1415.051698583, + "finished_at": "2026-10-13T01:32:56.557692+08:00", + "core_unchanged": false, + "bitstream_generated": true, + "candidate_core_unchanged": true, + "candidate_memory_unchanged": true +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/bus-skew.rpt b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/bus-skew.rpt new file mode 100644 index 0000000..fdb0a06 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/bus-skew.rpt @@ -0,0 +1,1380 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Tue Oct 13 01:32:13 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_bus_skew -return_string +| Design : toy_a7_top +| Device : 7a100t-csg324 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +| Design State : Routed +--------------------------------------------------------------------------------------------------------------------------------------------- + +Bus Skew Report + +Table of Contents +----------------- +1. Bus Skew Report Summary +2. Bus Skew Report Per Constraint + +1. Bus Skew Report Summary +-------------------------- + +Id Position From To Corner Requirement(ns) Actual(ns) Slack(ns) +-- -------- ------------------------------ ------------------------------ ------ --------------- ---------- --------- +1 31 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 0.873 11.127 +2 33 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} 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{memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 0.779 11.221 +5 39 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 0.489 11.511 +6 41 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 0.698 11.302 +7 43 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 1.078 10.922 +8 45 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 1.026 10.974 +9 47 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 0.763 11.237 +10 49 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 0.781 11.219 + + +2. Bus Skew Report Per Constraint +--------------------------------- + +Id: 1 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +core_raw clk_pll_i memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + Slow 0.873 11.127 + + +Slack (MET) : 11.127ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: -0.562ns + Reference Relative Delay: -1.878ns + Relative CRPR: 0.444ns + Actual Bus Skew: 0.873ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.613 -0.927 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X53Y80 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X53Y80 FDRE (Prop_fdre_C_Q) 0.419 -0.508 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.747 0.239 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[1] + SLICE_X49Y78 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.498 0.671 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X49Y78 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C + clock pessimism 0.395 1.066 + SLICE_X49Y78 FDRE (Setup_fdre_C_D) -0.265 0.801 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + ------------------------------------------------------------------- + data arrival 0.239 + clock arrival 0.801 + ------------------------------------------------------------------- + relative delay -0.562 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=35517, routed) 1.489 -1.531 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X55Y76 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X55Y76 FDRE (Prop_fdre_C_Q) 0.367 -1.164 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.489 -0.675 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[2] + SLICE_X57Y76 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.606 1.428 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X57Y76 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C + clock pessimism -0.395 1.033 + SLICE_X57Y76 FDRE (Hold_fdre_C_D) 0.170 1.203 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2] + ------------------------------------------------------------------- + data arrival -0.675 + clock arrival 1.203 + ------------------------------------------------------------------- + relative delay -1.878 + + + +Id: 2 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +core_raw clk_pll_i memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + Slow 0.653 11.347 + + +Slack (MET) : 11.347ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: -0.897ns + Reference Relative Delay: -2.108ns + Relative CRPR: 0.558ns + Actual Bus Skew: 0.653ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.633 -0.907 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X68Y94 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X68Y94 FDRE (Prop_fdre_C_Q) 0.456 -0.451 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.535 0.085 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[0] + SLICE_X69Y94 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.509 0.682 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X69Y94 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C + clock pessimism 0.395 1.077 + SLICE_X69Y94 FDRE (Setup_fdre_C_D) -0.095 0.982 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + ------------------------------------------------------------------- + data arrival 0.085 + clock arrival 0.982 + ------------------------------------------------------------------- + relative delay -0.897 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=35517, routed) 1.512 -1.508 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X68Y94 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X68Y94 FDRE (Prop_fdre_C_Q) 0.367 -1.141 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.260 -0.882 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[2] + SLICE_X68Y92 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.630 1.452 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X68Y92 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C + clock pessimism -0.395 1.057 + SLICE_X68Y92 FDRE (Hold_fdre_C_D) 0.169 1.226 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2] + ------------------------------------------------------------------- + data arrival -0.882 + clock arrival 1.226 + ------------------------------------------------------------------- + relative delay -2.108 + + + +Id: 3 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +clk_pll_i core_raw memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + Slow 0.964 11.036 + + +Slack (MET) : 11.036ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: 3.903ns + Reference Relative Delay: 2.440ns + Relative CRPR: 0.499ns + Actual Bus Skew: 0.964ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.630 1.452 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X67Y92 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y92 FDRE (Prop_fdre_C_Q) 0.456 1.908 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.787 2.695 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[0] + SLICE_X64Y93 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=35517, routed) 1.512 -1.508 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X64Y93 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C + clock pessimism 0.395 -1.113 + SLICE_X64Y93 FDRE (Setup_fdre_C_D) -0.095 -1.208 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + ------------------------------------------------------------------- + data arrival 2.695 + clock arrival -1.208 + ------------------------------------------------------------------- + relative delay 3.903 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.508 0.681 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X68Y92 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X68Y92 FDRE (Prop_fdre_C_Q) 0.367 1.048 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.260 1.307 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[3] + SLICE_X68Y94 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.633 -0.907 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X68Y94 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C + clock pessimism -0.395 -1.302 + SLICE_X68Y94 FDRE (Hold_fdre_C_D) 0.169 -1.133 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3] + ------------------------------------------------------------------- + data arrival 1.307 + clock arrival -1.133 + ------------------------------------------------------------------- + relative delay 2.440 + + + +Id: 4 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +core_raw clk_pll_i memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + Slow 0.779 11.221 + + +Slack (MET) : 11.221ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: -0.747ns + Reference Relative Delay: -2.080ns + Relative CRPR: 0.554ns + Actual Bus Skew: 0.779ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.714 -0.826 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X87Y109 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X87Y109 FDRE (Prop_fdre_C_Q) 0.419 -0.407 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.607 0.199 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[3] + SLICE_X88Y109 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.597 0.769 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X88Y109 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C + clock pessimism 0.395 1.164 + SLICE_X88Y109 FDRE (Setup_fdre_C_D) -0.218 0.946 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3] + ------------------------------------------------------------------- + data arrival 0.199 + clock arrival 0.946 + ------------------------------------------------------------------- + relative delay -0.747 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=35517, routed) 1.594 -1.427 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X87Y109 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X87Y109 FDRE (Prop_fdre_C_Q) 0.367 -1.060 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.293 -0.767 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[2] + SLICE_X86Y109 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.716 1.538 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X86Y109 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C + clock pessimism -0.395 1.143 + SLICE_X86Y109 FDRE (Hold_fdre_C_D) 0.170 1.313 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2] + ------------------------------------------------------------------- + data arrival -0.767 + clock arrival 1.313 + ------------------------------------------------------------------- + relative delay -2.080 + + + +Id: 5 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +clk_pll_i core_raw memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + Slow 0.489 11.511 + + +Slack (MET) : 11.511ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: 3.567ns + Reference Relative Delay: 2.548ns + Relative CRPR: 0.529ns + Actual Bus Skew: 0.489ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.717 1.539 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X89Y108 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X89Y108 FDRE (Prop_fdre_C_Q) 0.456 1.995 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.445 2.440 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[0] + SLICE_X87Y109 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=35517, routed) 1.594 -1.427 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X87Y109 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C + clock pessimism 0.395 -1.032 + SLICE_X87Y109 FDRE (Setup_fdre_C_D) -0.095 -1.127 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + ------------------------------------------------------------------- + data arrival 2.440 + clock arrival -1.127 + ------------------------------------------------------------------- + relative delay 3.567 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.594 0.766 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X89Y114 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X89Y114 FDRE (Prop_fdre_C_Q) 0.367 1.133 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.360 1.493 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[3] + SLICE_X87Y114 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.711 -0.829 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X87Y114 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C + clock pessimism -0.395 -1.224 + SLICE_X87Y114 FDRE (Hold_fdre_C_D) 0.169 -1.055 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3] + ------------------------------------------------------------------- + data arrival 1.493 + clock arrival -1.055 + ------------------------------------------------------------------- + relative delay 2.548 + + + +Id: 6 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +clk_pll_i core_raw memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + Slow 0.698 11.302 + + +Slack (MET) : 11.302ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: 3.743ns + Reference Relative Delay: 2.489ns + Relative CRPR: 0.556ns + Actual Bus Skew: 0.698ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.715 1.537 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X76Y94 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X76Y94 FDRE (Prop_fdre_C_Q) 0.478 2.015 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.432 2.448 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[1] + SLICE_X75Y94 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=35517, routed) 1.597 -1.423 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X75Y94 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C + clock pessimism 0.395 -1.028 + SLICE_X75Y94 FDRE (Setup_fdre_C_D) -0.267 -1.295 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + ------------------------------------------------------------------- + data arrival 2.448 + clock arrival -1.295 + ------------------------------------------------------------------- + relative delay 3.743 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.594 0.767 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X76Y94 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X76Y94 FDRE (Prop_fdre_C_Q) 0.418 1.185 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.255 1.440 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[2] + SLICE_X77Y93 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.717 -0.823 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X77Y93 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C + clock pessimism -0.395 -1.218 + SLICE_X77Y93 FDRE (Hold_fdre_C_D) 0.169 -1.049 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2] + ------------------------------------------------------------------- + data arrival 1.440 + clock arrival -1.049 + ------------------------------------------------------------------- + relative delay 2.489 + + + +Id: 7 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +core_raw clk_pll_i memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + Slow 1.078 10.922 + + +Slack (MET) : 10.922ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: -0.584ns + Reference Relative Delay: -2.177ns + Relative CRPR: 0.515ns + Actual Bus Skew: 1.078ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.717 -0.823 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X76Y93 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X76Y93 FDRE (Prop_fdre_C_Q) 0.518 -0.305 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.813 0.509 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[2] + SLICE_X73Y93 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.592 0.765 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X73Y93 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C + clock pessimism 0.395 1.160 + SLICE_X73Y93 FDRE (Setup_fdre_C_D) -0.067 1.093 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2] + ------------------------------------------------------------------- + data arrival 0.509 + clock arrival 1.093 + ------------------------------------------------------------------- + relative delay -0.584 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=35517, routed) 1.597 -1.423 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X75Y94 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X75Y94 FDRE (Prop_fdre_C_Q) 0.367 -1.056 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.254 -0.802 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[3] + SLICE_X74Y93 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.715 1.537 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X74Y93 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C + clock pessimism -0.395 1.142 + SLICE_X74Y93 FDRE (Hold_fdre_C_D) 0.233 1.375 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3] + ------------------------------------------------------------------- + data arrival -0.802 + clock arrival 1.375 + ------------------------------------------------------------------- + relative delay -2.177 + + + +Id: 8 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +core_raw clk_pll_i memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + Slow 1.026 10.974 + + +Slack (MET) : 10.974ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: -0.551ns + Reference Relative Delay: -2.004ns + Relative CRPR: 0.427ns + Actual Bus Skew: 1.026ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.613 -0.927 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X53Y80 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X53Y80 FDRE (Prop_fdre_C_Q) 0.419 -0.508 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.746 0.238 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[1] + SLICE_X48Y80 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.499 0.672 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X48Y80 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C + clock pessimism 0.395 1.067 + SLICE_X48Y80 FDRE (Setup_fdre_C_D) -0.278 0.789 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + ------------------------------------------------------------------- + data arrival 0.238 + clock arrival 0.789 + ------------------------------------------------------------------- + relative delay -0.551 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=35517, routed) 1.495 -1.525 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X57Y81 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X57Y81 FDRE (Prop_fdre_C_Q) 0.367 -1.158 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.367 -0.791 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[2] + SLICE_X57Y84 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.617 1.439 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X57Y84 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C + clock pessimism -0.395 1.044 + SLICE_X57Y84 FDRE (Hold_fdre_C_D) 0.169 1.213 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2] + ------------------------------------------------------------------- + data arrival -0.791 + clock arrival 1.213 + ------------------------------------------------------------------- + relative delay -2.004 + + + +Id: 9 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +clk_pll_i core_raw memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + Slow 0.763 11.237 + + +Slack (MET) : 11.237ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: 3.721ns + Reference Relative Delay: 2.442ns + Relative CRPR: 0.516ns + Actual Bus Skew: 0.763ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.612 1.434 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X57Y80 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X57Y80 FDRE (Prop_fdre_C_Q) 0.456 1.890 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.606 2.496 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[0] + SLICE_X57Y81 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=35517, routed) 1.495 -1.525 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X57Y81 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C + clock pessimism 0.395 -1.130 + SLICE_X57Y81 FDRE (Setup_fdre_C_D) -0.095 -1.225 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + ------------------------------------------------------------------- + data arrival 2.496 + clock arrival -1.225 + ------------------------------------------------------------------- + relative delay 3.721 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.487 0.660 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X57Y76 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X57Y76 FDRE (Prop_fdre_C_Q) 0.367 1.027 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.257 1.284 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[2] + SLICE_X55Y76 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.607 -0.933 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X55Y76 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C + clock pessimism -0.395 -1.328 + SLICE_X55Y76 FDRE (Hold_fdre_C_D) 0.169 -1.159 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2] + ------------------------------------------------------------------- + data arrival 1.284 + clock arrival -1.159 + ------------------------------------------------------------------- + relative delay 2.442 + + + +Id: 10 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +clk_pll_i core_raw memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + Slow 0.781 11.219 + + +Slack (MET) : 11.219ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: 3.898ns + Reference Relative Delay: 2.579ns + Relative CRPR: 0.539ns + Actual Bus Skew: 0.781ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.614 1.436 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X59Y78 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X59Y78 FDRE (Prop_fdre_C_Q) 0.419 1.855 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.646 2.501 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[1] + SLICE_X59Y79 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=35517, routed) 1.498 -1.522 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X59Y79 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C + clock pessimism 0.395 -1.127 + SLICE_X59Y79 FDRE (Setup_fdre_C_D) -0.270 -1.397 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + ------------------------------------------------------------------- + data arrival 2.501 + clock arrival -1.397 + ------------------------------------------------------------------- + relative delay 3.898 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.494 0.667 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X59Y78 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X59Y78 FDRE (Prop_fdre_C_Q) 0.367 1.034 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.391 1.425 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[0] + SLICE_X55Y78 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.611 -0.929 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X55Y78 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C + clock pessimism -0.395 -1.324 + SLICE_X55Y78 FDRE (Hold_fdre_C_D) 0.170 -1.154 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + ------------------------------------------------------------------- + data arrival 1.425 + clock arrival -1.154 + ------------------------------------------------------------------- + relative delay 2.579 + + + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/cdc.rpt b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/cdc.rpt new file mode 100644 index 0000000..89919b2 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/cdc.rpt @@ -0,0 +1,93 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Tue Oct 13 01:32:08 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_cdc -details -return_string +| Design : toy_a7_top +| Device : 7a100t-csg324 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +| Design State : Routed +--------------------------------------------------------------------------------------------------------------------------------------------- + +CDC Report + +ID Severity Count Description +------ -------- ----- ------------------------------------------------------- +CDC-3 Info 17 1-bit synchronized with ASYNC_REG property +CDC-9 Info 10 Asynchronous reset synchronized with ASYNC_REG property +CDC-15 Warning 3 Clock enable controlled CDC structure detected + +Source Clock: core_raw +Destination Clock: clk_pll_i +CDC Type: Safely Timed + +Row ID Severity Description Depth Exception Source (From) Destination (To) +--- ------ -------- ------------------------------------------------------- ----- ---------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + 1 CDC-15 Warning Clock enable controlled CDC structure detected 0 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_60_60/DP/CLK memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[60]/D + 2 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path reset_count_reg[9]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + 3 CDC-3 Info 1-bit synchronized with ASYNC_REG property 7 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd/syncstages_ff_reg[0]/D + 4 CDC-3 Info 1-bit synchronized with ASYNC_REG property 6 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr/syncstages_ff_reg[0]/D + 5 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path reset_count_reg[9]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + 6 CDC-15 Warning Clock enable controlled CDC structure detected 0 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_60_60/DP/CLK memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[60]/D + 7 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path reset_count_reg[9]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + 8 CDC-3 Info 1-bit synchronized with ASYNC_REG property 7 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd/syncstages_ff_reg[0]/D + 9 CDC-15 Warning Clock enable controlled CDC structure detected 0 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_144_144/DP/CLK memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[144]/D + 10 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path reset_count_reg[9]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + 11 CDC-3 Info 1-bit synchronized with ASYNC_REG property 7 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd/syncstages_ff_reg[0]/D + 12 CDC-3 Info 1-bit synchronized with ASYNC_REG property 6 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr/syncstages_ff_reg[0]/D + 13 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path reset_count_reg[9]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + +Source Clock: mem_refclk +Destination Clock: clk_pll_i +CDC Type: User Ignored + +Row ID Severity Description Depth Exception Source (From) Destination (To) +--- ----- -------- ------------------------------------------ ----- ---------- -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------------------------------- + 1 CDC-3 Info 1-bit synchronized with ASYNC_REG property 3 False Path ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/MEMREFCLK ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[2]/D + 2 CDC-3 Info 1-bit synchronized with ASYNC_REG property 3 False Path ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/MEMREFCLK ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[3]/D + +Source Clock: clk_pll_i +Destination Clock: core_raw +CDC Type: Safely Timed + +Row ID Severity Description Depth Exception Source (From) Destination (To) +--- ----- -------- ------------------------------------------------------- ----- ---------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + 1 CDC-3 Info 1-bit synchronized with ASYNC_REG property 2 False Path ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/init_calib_complete_reg/C calib_sync_reg[0]/D + 2 CDC-3 Info 1-bit synchronized with ASYNC_REG property 6 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr/syncstages_ff_reg[0]/D + 3 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path ui_reset_pipe_reg[2]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + 4 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path ui_reset_pipe_reg[2]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + 5 CDC-3 Info 1-bit synchronized with ASYNC_REG property 7 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd/syncstages_ff_reg[0]/D + 6 CDC-3 Info 1-bit synchronized with ASYNC_REG property 6 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr/syncstages_ff_reg[0]/D + 7 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path ui_reset_pipe_reg[2]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + 8 CDC-3 Info 1-bit synchronized with ASYNC_REG property 6 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr/syncstages_ff_reg[0]/D + 9 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path ui_reset_pipe_reg[2]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + 10 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path ui_reset_pipe_reg[2]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + 11 CDC-3 Info 1-bit synchronized with ASYNC_REG property 7 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd/syncstages_ff_reg[0]/D + +Source Clock: input port clock +Destination Clock: core_raw +CDC Type: No Common Primary Clock + +Row ID Severity Description Depth Exception Source (From) Destination (To) +--- ----- -------- ------------------------------------------ ----- ---------- ------------- ------------------------------- + 1 CDC-3 Info 1-bit synchronized with ASYNC_REG property 2 False Path btn0 btn_meta_reg/D + 2 CDC-3 Info 1-bit synchronized with ASYNC_REG property 2 False Path uart_txd_in platform/receiver/rx_meta_reg/D + +Source Clock: clk_pll_i +Destination Clock: ref_raw +CDC Type: Safely Timed + +Row ID Severity Description Depth Exception Source (From) Destination (To) +--- ----- -------- ------------------------------------------ ----- ----------------------- ------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------ + 1 CDC-3 Info 1-bit synchronized with ASYNC_REG property 2 Max Delay Datapath Only ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg/D + +Source Clock: input port clock +Destination Clock: ref_raw +CDC Type: No Common Primary Clock + +Row ID Severity Description Depth Exception Source (From) Destination (To) +--- ----- -------- ------------------------------------------ ----- ---------- ------------- ------------------ + 1 CDC-3 Info 1-bit synchronized with ASYNC_REG property 2 False Path btn0 btn_ref_meta_reg/D + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/check-timing.rpt b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/check-timing.rpt new file mode 100644 index 0000000..a4288ef --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/check-timing.rpt @@ -0,0 +1,108 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Tue Oct 13 01:32:27 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : check_timing -verbose -file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/check-timing.rpt +| Design : toy_a7_top +| Device : 7a100t-csg324 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +| Design State : Routed +-------------------------------------------------------------------------------------------------------------------------------------------------------------------- + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock (0) +2. checking constant_clock (0) +3. checking pulse_width_clock (0) +4. checking unconstrained_internal_endpoints (0) +5. checking no_input_delay (2) +6. checking no_output_delay (6) +7. checking multiple_clock (0) +8. checking generated_clocks (0) +9. checking loops (0) +10. checking partial_input_delay (0) +11. checking partial_output_delay (0) +12. checking latch_loops (0) + +1. checking no_clock (0) +------------------------ + There are 0 register/latch pins with no clock. + + +2. checking constant_clock (0) +------------------------------ + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock (0) +--------------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints (0) +------------------------------------------------ + There are 0 pins that are not constrained for maximum delay. + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay (2) +------------------------------ + There are 0 input ports with no input delay specified. + + There are 2 input ports with no input delay but user has a false path constraint. (MEDIUM) + +btn0 +uart_txd_in + + +6. checking no_output_delay (6) +------------------------------- + There are 0 ports with no output delay specified. + + There are 6 ports with no output delay but user has a false path constraint (MEDIUM) + +ddr3_reset_n +led[0] +led[1] +led[2] +led[3] +uart_rxd_out + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock (0) +------------------------------ + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks (0) +-------------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops (0) +--------------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay (0) +------------------------------------ + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay (0) +------------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops (0) +---------------------------- + There are 0 combinational latch loops in the design through latch input + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/clocks.rpt b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/clocks.rpt new file mode 100644 index 0000000..eac8c71 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/clocks.rpt @@ -0,0 +1,203 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Tue Oct 13 01:32:25 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_clocks -file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/clocks.rpt +| Design : toy_a7_top +| Device : 7a100t-csg324 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +| Design State : Routed +------------------------------------------------------------------------------------------------------------------------------------------------------ + +Clock Report + + +Attributes + P: Propagated + G: Generated + A: Auto-derived + R: Renamed + V: Virtual + I: Inverted + S: Pin phase-shifted with Latency mode + +Clock Period(ns) Waveform(ns) Attributes Sources +board_clk 10.000 {0.000 5.000} P {CLK100MHZ} +clk_pll_i 12.000 {0.000 6.000} P,G,A {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT} +core_raw 40.000 {0.000 20.000} P,G,A {clock_mmcm/CLKOUT0} +fb 10.000 {0.000 5.000} P,G,A {clock_mmcm/CLKFBOUT} +freq_refclk 1.500 {0.000 0.750} P,G,A {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0} +iserdes_clkdiv 12.000 {0.000 6.000} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV} +iserdes_clkdiv_1 12.000 {0.000 6.000} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV} +mem_refclk 3.000 {0.000 1.500} P,G,A {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1} +oserdes_clk 3.000 {0.000 1.500} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK} +oserdes_clk_1 3.000 {0.000 1.500} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK} +oserdes_clk_2 3.000 {0.000 1.500} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK} +oserdes_clk_3 3.000 {0.000 1.500} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK} +oserdes_clkdiv 12.000 {0.000 6.000} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV} +oserdes_clkdiv_1 12.000 {0.000 6.000} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV} +oserdes_clkdiv_2 6.000 {0.000 3.000} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV} +oserdes_clkdiv_3 6.000 {0.000 3.000} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV} +pll_clk3_out 12.000 {0.000 6.000} P,G,A {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3} +pll_clkfbout 6.000 {0.000 3.000} P,G,A {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT} +ref_raw 5.000 {0.000 2.500} P,G,A {clock_mmcm/CLKOUT2} +sync_pulse 48.000 {1.312 4.312} P,G,A {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2} +sys_raw 6.000 {0.000 3.000} P,G,A {clock_mmcm/CLKOUT1} +u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk 3.000 {0.000 1.500} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK} +u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk 3.000 {0.000 1.500} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK} + + +==================================================== +Generated Clocks +==================================================== + +Generated Clock : clk_pll_i +Master Source : ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKIN1 +Master Clock : pll_clk3_out +Multiply By : 1 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT} + +Generated Clock : core_raw +Master Source : clock_mmcm/CLKIN1 +Master Clock : board_clk +Edges : {1 2 3} +Edge Shifts(ns) : {0.000 15.000 30.000} +Generated Sources : {clock_mmcm/CLKOUT0} + +Generated Clock : fb +Master Source : clock_mmcm/CLKIN1 +Master Clock : board_clk +Multiply By : 1 +Generated Sources : {clock_mmcm/CLKFBOUT} + +Generated Clock : freq_refclk +Master Source : ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 +Master Clock : sys_raw +Multiply By : 4 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0} + +Generated Clock : iserdes_clkdiv +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK +Master Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk +Divide By : 4 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV} + +Generated Clock : iserdes_clkdiv_1 +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK +Master Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk +Divide By : 4 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV} + +Generated Clock : mem_refclk +Master Source : ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 +Master Clock : sys_raw +Multiply By : 2 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1} + +Generated Clock : oserdes_clk +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/MEMREFCLK +Master Clock : mem_refclk +Divide By : 1 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK} + +Generated Clock : oserdes_clk_1 +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/MEMREFCLK +Master Clock : mem_refclk +Divide By : 1 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK} + +Generated Clock : oserdes_clk_2 +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/MEMREFCLK +Master Clock : mem_refclk +Divide By : 1 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK} + +Generated Clock : oserdes_clk_3 +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/MEMREFCLK +Master Clock : mem_refclk +Divide By : 1 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK} + +Generated Clock : oserdes_clkdiv +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK +Master Clock : oserdes_clk +Divide By : 4 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV} + +Generated Clock : oserdes_clkdiv_1 +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK +Master Clock : oserdes_clk_1 +Divide By : 4 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV} + +Generated Clock : oserdes_clkdiv_2 +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK +Master Clock : oserdes_clk_2 +Divide By : 2 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV} + +Generated Clock : oserdes_clkdiv_3 +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK +Master Clock : oserdes_clk_3 +Divide By : 2 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV} + +Generated Clock : pll_clk3_out +Master Source : ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 +Master Clock : sys_raw +Edges : {1 2 3} +Edge Shifts(ns) : {0.000 3.000 6.000} +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3} + +Generated Clock : pll_clkfbout +Master Source : ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 +Master Clock : sys_raw +Multiply By : 1 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT} + +Generated Clock : ref_raw +Master Source : clock_mmcm/CLKIN1 +Master Clock : board_clk +Multiply By : 2 +Generated Sources : {clock_mmcm/CLKOUT2} + +Generated Clock : sync_pulse +Master Source : ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 +Master Clock : sys_raw +Edges : {1 2 3} +Edge Shifts(ns) : {1.312 1.313 43.312} +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2} + +Generated Clock : sys_raw +Master Source : clock_mmcm/CLKIN1 +Master Clock : board_clk +Edges : {1 2 3} +Edge Shifts(ns) : {0.000 -2.000 -4.000} +Generated Sources : {clock_mmcm/CLKOUT1} + +Generated Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/FREQREFCLK +Master Clock : freq_refclk +Divide By : 2 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK} + +Generated Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/FREQREFCLK +Master Clock : freq_refclk +Divide By : 2 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK} + + + +==================================================== +User Uncertainty +==================================================== + + + +==================================================== +User Jitter +==================================================== + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/console.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/console.log new file mode 100644 index 0000000..855e6fc --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/console.log @@ -0,0 +1,5784 @@ + +****** Vivado v2024.1 (64-bit) + **** SW Build 5076996 on Wed May 22 18:36:09 MDT 2024 + **** IP Build 5075265 on Wed May 22 21:45:21 MDT 2024 + **** SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024 + **** Start of session at: Tue Oct 13 01:09:22 2026 + ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. + ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. + +source /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/build_board.tcl +# set root [file dirname [file dirname [file normalize [info script]]]] +# cd $root +# if {[llength $argv]<1 || [llength $argv]>2} {error "Usage: build_board.tcl OUTPUT_DIRECTORY ?flash?"} +# set flash 0 +# if {[llength $argv]==2} { +# if {[lindex $argv 1] ne "flash"} {error "Second argument must be flash"} +# set flash 1 +# } +# set out [file normalize [lindex $argv 0]] +# file mkdir $out +# file mkdir $out/ip +# proc phase {name} { +# global out +# set f [open $out/phase.txt w];puts $f $name;close $f +# puts "BOARD_PHASE $name" +# } +# set_param general.maxThreads 8 +# phase CREATE_IP +BOARD_PHASE CREATE_IP +# create_project -in_memory -part xc7a100tcsg324-1 +# set_property target_language Verilog [current_project] +# create_ip -name mig_7series -vendor xilinx.com -library ip -version 4.2 -module_name arty_ddr3 -dir $out/ip +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data0/tools/Xilinx/Vivado/2024.1/data/ip'. +# set_property CONFIG.XML_INPUT_FILE $root/board/vendor/mig.prj [get_ips arty_ddr3] +INFO: [IP_Flow 19-3484] Absolute path of file '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/vendor/mig.prj' provided. It will be converted relative to IP Instance files '../../../../board/vendor/mig.prj' +INFO: [Device 21-403] Loading part xc7a100tcsg324-1 +INFO: [Device 21-9227] Part: xc7a100tcsg324-1 does not have CEAM library. +# create_ip -name axi_clock_converter -vendor xilinx.com -library ip -version 2.1 -module_name toy_axi_cdc -dir $out/ip +# set_property -dict {CONFIG.PROTOCOL AXI4 CONFIG.ADDR_WIDTH 28 CONFIG.DATA_WIDTH 128 CONFIG.ID_WIDTH 4 CONFIG.ACLK_ASYNC 1 CONFIG.SYNCHRONIZATION_STAGES 3} [get_ips toy_axi_cdc] +# generate_target all [get_ips] +INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'arty_ddr3'... +INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'arty_ddr3'... +INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'arty_ddr3'... +INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'arty_ddr3'... +INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'arty_ddr3'... +INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'toy_axi_cdc'... +INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'toy_axi_cdc'... +WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_ooc.xdc' +INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'toy_axi_cdc'... +INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'toy_axi_cdc'... +INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'toy_axi_cdc'... +generate_target: Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 2220.156 ; gain = 272.484 ; free physical = 194785 ; free virtual = 543731 +# report_ip_status -file $out/ip-status.rpt +# phase SYNTH_IP +BOARD_PHASE SYNTH_IP +# synth_ip [get_ips] +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data0/tools/Xilinx/Vivado/2024.1/data/ip'. +WARNING: [Vivado 12-13650] The IP file '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3.xci' has been moved from its original location, as a result the outputs for this IP will now be generated in '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3'. Alternatively a copy of the IP can be imported into the project using one of the 'import_ip' or 'import_files' commands. +Command: synth_design -top arty_ddr3 -part xc7a100tcsg324-1 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. +INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes +INFO: [Synth 8-7075] Helper process launched with PID 535585 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2658.754 ; gain = 416.715 ; free physical = 194057 ; free virtual = 543005 +--------------------------------------------------------------------------------- +WARNING: [Synth 8-10515] begin/end is required for generate-for in this mode of Verilog [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v:253] +INFO: [Synth 8-11241] undeclared symbol 'dbg_sel_po_incdec', assumed default net type 'wire' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:1223] +INFO: [Synth 8-11241] undeclared symbol 'dbg_po_f_inc', assumed default net type 'wire' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:1227] +INFO: [Synth 8-11241] undeclared symbol 'dbg_po_f_stg23_sel', assumed default net type 'wire' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:1228] +INFO: [Synth 8-11241] undeclared symbol 'dbg_po_f_dec', assumed default net type 'wire' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:1229] +INFO: [Synth 8-6157] synthesizing module 'arty_ddr3' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3.v:70] +INFO: [Synth 8-6157] synthesizing module 'arty_ddr3_mig' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:75] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_tempmon' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v:69] + Parameter TCQ bound to: 100 - type: integer + Parameter TEMP_MON_CONTROL bound to: INTERNAL - type: string + Parameter XADC_CLK_PERIOD bound to: 5000 - type: integer + Parameter tTEMPSAMPLE bound to: 10000000 - type: integer +INFO: [Synth 8-6157] synthesizing module 'XADC' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:143027] + Parameter INIT_40 bound to: 16'b0001000000000000 + Parameter INIT_41 bound to: 16'b0010111111111111 + Parameter INIT_42 bound to: 16'b0000100000000000 + Parameter INIT_48 bound to: 16'b0000000100000001 + Parameter INIT_49 bound to: 16'b0000000000000000 + Parameter INIT_4A bound to: 16'b0000000100000000 + Parameter INIT_4B bound to: 16'b0000000000000000 + Parameter INIT_4C bound to: 16'b0000000000000000 + Parameter INIT_4D bound to: 16'b0000000000000000 + Parameter INIT_4E bound to: 16'b0000000000000000 + Parameter INIT_4F bound to: 16'b0000000000000000 + Parameter INIT_50 bound to: 16'b1011010111101101 + Parameter INIT_51 bound to: 16'b0101011111100100 + Parameter INIT_52 bound to: 16'b1010000101000111 + Parameter INIT_53 bound to: 16'b1100101000110011 + Parameter INIT_54 bound to: 16'b1010100100111010 + Parameter INIT_55 bound to: 16'b0101001011000110 + Parameter INIT_56 bound to: 16'b1001010101010101 + Parameter INIT_57 bound to: 16'b1010111001001110 + Parameter INIT_58 bound to: 16'b0101100110011001 + Parameter INIT_5C bound to: 16'b0101000100010001 + Parameter SIM_DEVICE bound to: 7SERIES - type: string +INFO: [Synth 8-6155] done synthesizing module 'XADC' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:143027] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_tempmon' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v:69] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_iodelay_ctrl' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_iodelay_ctrl.v:80] + Parameter TCQ bound to: 100 - type: integer + Parameter IODELAY_GRP0 bound to: ARTY_DDR3_IODELAY_MIG0 - type: string + Parameter IODELAY_GRP1 bound to: ARTY_DDR3_IODELAY_MIG1 - type: string + Parameter REFCLK_TYPE bound to: NO_BUFFER - type: string + Parameter SYSCLK_TYPE bound to: NO_BUFFER - type: string + Parameter SYS_RST_PORT bound to: FALSE - type: string + Parameter RST_ACT_LOW bound to: 1 - type: integer + Parameter DIFF_TERM_REFCLK bound to: TRUE - type: string + Parameter FPGA_SPEED_GRADE bound to: 1 - type: integer + Parameter REF_CLK_MMCM_IODELAY_CTRL bound to: FALSE - type: string +INFO: [Synth 8-6157] synthesizing module 'IDELAYCTRL' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:75739] +INFO: [Synth 8-6155] done synthesizing module 'IDELAYCTRL' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:75739] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_iodelay_ctrl' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_iodelay_ctrl.v:80] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_clk_ibuf' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_clk_ibuf.v:68] + Parameter SYSCLK_TYPE bound to: NO_BUFFER - type: string + Parameter DIFF_TERM_SYSCLK bound to: TRUE - type: string +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_clk_ibuf' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_clk_ibuf.v:68] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_infrastructure' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:78] + Parameter TCQ bound to: 100 - type: integer + Parameter CLKIN_PERIOD bound to: 6000 - type: integer + Parameter nCK_PER_CLK bound to: 4 - type: integer + Parameter SYSCLK_TYPE bound to: NO_BUFFER - type: string + Parameter CLKFBOUT_MULT bound to: 8 - type: integer + Parameter DIVCLK_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT0_DIVIDE bound to: 2 - type: integer + Parameter CLKOUT1_DIVIDE bound to: 4 - type: integer + Parameter CLKOUT2_DIVIDE bound to: 64 - type: integer + Parameter CLKOUT3_DIVIDE bound to: 16 - type: integer + Parameter MMCM_VCO bound to: 666 - type: integer + Parameter MMCM_MULT_F bound to: 8 - type: integer + Parameter MMCM_DIVCLK_DIVIDE bound to: 1 - type: integer + Parameter RST_ACT_LOW bound to: 1 - type: integer + Parameter tCK bound to: 3000 - type: integer + Parameter MEM_TYPE bound to: DDR3 - type: string +INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82388] + Parameter BANDWIDTH bound to: HIGH - type: string + Parameter CLKFBOUT_MULT_F bound to: 8.000000 - type: double + Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double + Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKIN1_PERIOD bound to: 12.000000 - type: double + Parameter CLKOUT0_DIVIDE_F bound to: 16.000000 - type: double + Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT0_USE_FINE_PS bound to: TRUE - type: string + Parameter CLKOUT1_DIVIDE bound to: 4 - type: integer + Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT4_CASCADE bound to: FALSE - type: string + Parameter COMPENSATION bound to: BUF_IN - type: string + Parameter DIVCLK_DIVIDE bound to: 1 - type: integer + Parameter REF_JITTER1 bound to: 0.000000 - type: double + Parameter STARTUP_WAIT bound to: FALSE - type: string +INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82388] +INFO: [Synth 8-6157] synthesizing module 'BUFG' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951] +INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951] +INFO: [Synth 8-6157] synthesizing module 'PLLE2_ADV' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114750] + Parameter BANDWIDTH bound to: OPTIMIZED - type: string + Parameter CLKFBOUT_MULT bound to: 8 - type: integer + Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double + Parameter CLKIN1_PERIOD bound to: 6.000000 - type: double + Parameter CLKOUT0_DIVIDE bound to: 2 - type: integer + Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT1_DIVIDE bound to: 4 - type: integer + Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT2_DIVIDE bound to: 64 - type: integer + Parameter CLKOUT2_DUTY_CYCLE bound to: 0.062500 - type: double + Parameter CLKOUT2_PHASE bound to: 9.843750 - type: double + Parameter CLKOUT3_DIVIDE bound to: 16 - type: integer + Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT3_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT4_DIVIDE bound to: 8 - type: integer + Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT4_PHASE bound to: 168.750000 - type: double + Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT5_PHASE bound to: 0.000000 - type: double + Parameter COMPENSATION bound to: INTERNAL - type: string + Parameter DIVCLK_DIVIDE bound to: 1 - type: integer + Parameter REF_JITTER1 bound to: 0.010000 - type: double + Parameter REF_JITTER2 bound to: 0.010000 - type: double + Parameter STARTUP_WAIT bound to: FALSE - type: string +INFO: [Synth 8-6155] done synthesizing module 'PLLE2_ADV' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114750] +INFO: [Synth 8-6157] synthesizing module 'BUFH' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:2199] +INFO: [Synth 8-6155] done synthesizing module 'BUFH' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:2199] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_infrastructure' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:78] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_memc_ui_top_axi' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_memc_ui_top_axi.v:71] + Parameter TCQ bound to: 100 - type: integer + Parameter DDR3_VDD_OP_VOLT bound to: 135 - type: string + Parameter PAYLOAD_WIDTH bound to: 16 - type: integer + Parameter ADDR_CMD_MODE bound to: 1T - type: string + Parameter AL bound to: 0 - type: string + Parameter BANK_WIDTH bound to: 3 - type: integer + Parameter BM_CNT_WIDTH bound to: 2 - type: integer + Parameter BURST_MODE bound to: 8 - type: string + Parameter BURST_TYPE bound to: SEQ - type: string + Parameter CA_MIRROR bound to: OFF - type: string + Parameter CK_WIDTH bound to: 1 - type: integer + Parameter CL bound to: 5 - type: integer + Parameter COL_WIDTH bound to: 10 - type: integer + Parameter CMD_PIPE_PLUS1 bound to: ON - type: string + Parameter CS_WIDTH bound to: 1 - type: integer + Parameter CKE_WIDTH bound to: 1 - type: integer + Parameter CWL bound to: 5 - type: integer + Parameter DATA_WIDTH bound to: 16 - type: integer + Parameter DATA_BUF_ADDR_WIDTH bound to: 5 - type: integer + Parameter DM_WIDTH bound to: 2 - type: integer + Parameter DQ_CNT_WIDTH bound to: 4 - type: integer + Parameter DQ_WIDTH bound to: 16 - type: integer + Parameter DQS_CNT_WIDTH bound to: 1 - type: integer + Parameter DQS_WIDTH bound to: 2 - type: integer + Parameter DRAM_TYPE bound to: DDR3 - type: string + Parameter DRAM_WIDTH bound to: 8 - type: integer + Parameter ECC bound to: OFF - type: string + Parameter ECC_WIDTH bound to: 0 - type: integer + Parameter ECC_TEST bound to: OFF - type: string + Parameter MC_ERR_ADDR_WIDTH bound to: 28 - type: integer + Parameter MASTER_PHY_CTL bound to: 0 - type: integer + Parameter nAL bound to: 0 - type: integer + Parameter nBANK_MACHS bound to: 4 - type: integer + Parameter nCK_PER_CLK bound to: 4 - type: integer + Parameter nCS_PER_RANK bound to: 1 - type: integer + Parameter ORDERING bound to: NORM - type: string + Parameter IBUF_LPWR_MODE bound to: OFF - type: string + Parameter BANK_TYPE bound to: HR_IO - type: string + Parameter DATA_IO_PRIM_TYPE bound to: HR_LP - type: string + Parameter DATA_IO_IDLE_PWRDWN bound to: ON - type: string + Parameter IODELAY_GRP0 bound to: ARTY_DDR3_IODELAY_MIG0 - type: string + Parameter IODELAY_GRP1 bound to: ARTY_DDR3_IODELAY_MIG1 - type: string + Parameter FPGA_SPEED_GRADE bound to: 1 - type: integer + Parameter OUTPUT_DRV bound to: LOW - type: string + Parameter REG_CTRL bound to: OFF - type: string + Parameter RTT_NOM bound to: 40 - type: string + Parameter RTT_WR bound to: OFF - type: string + Parameter STARVE_LIMIT bound to: 2 - type: integer + Parameter tCK bound to: 3000 - type: integer + Parameter tCKE bound to: 5625 - type: integer + Parameter tFAW bound to: 45000 - type: integer + Parameter tPRDI bound to: 1000000 - type: integer + Parameter tRAS bound to: 36000 - type: integer + Parameter tRCD bound to: 13500 - type: integer + Parameter tREFI bound to: 7800000 - type: integer + Parameter tRFC bound to: 160000 - type: integer + Parameter tRP bound to: 13500 - type: integer + Parameter tRRD bound to: 7500 - type: integer + Parameter tRTP bound to: 7500 - type: integer + Parameter tWTR bound to: 7500 - type: integer + Parameter tZQI bound to: 128000000 - type: integer + Parameter tZQCS bound to: 64 - type: integer + Parameter USER_REFRESH bound to: OFF - type: string + Parameter TEMP_MON_EN bound to: ON - type: string + Parameter WRLVL bound to: ON - type: string + Parameter DEBUG_PORT bound to: OFF - type: string + Parameter CAL_WIDTH bound to: HALF - type: string + Parameter RANK_WIDTH bound to: 1 - type: integer + Parameter RANKS bound to: 1 - type: integer + Parameter ODT_WIDTH bound to: 1 - type: integer + Parameter ROW_WIDTH bound to: 14 - type: integer + Parameter ADDR_WIDTH bound to: 28 - type: integer + Parameter APP_MASK_WIDTH bound to: 16 - type: integer + Parameter APP_DATA_WIDTH bound to: 128 - type: integer + Parameter BYTE_LANES_B0 bound to: 4'b1111 + Parameter BYTE_LANES_B1 bound to: 4'b0000 + Parameter BYTE_LANES_B2 bound to: 4'b0000 + Parameter BYTE_LANES_B3 bound to: 4'b0000 + Parameter BYTE_LANES_B4 bound to: 4'b0000 + Parameter DATA_CTL_B0 bound to: 4'b1100 + Parameter DATA_CTL_B1 bound to: 4'b0000 + Parameter DATA_CTL_B2 bound to: 4'b0000 + Parameter DATA_CTL_B3 bound to: 4'b0000 + Parameter DATA_CTL_B4 bound to: 4'b0000 + Parameter PHY_0_BITLANES bound to: 48'b001111111110001111111110111111111111101111111111 + Parameter PHY_1_BITLANES bound to: 48'b000000000000000000000000000000000000000000000000 + Parameter PHY_2_BITLANES bound to: 48'b000000000000000000000000000000000000000000000000 + Parameter CK_BYTE_MAP bound to: 144'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter ADDR_MAP bound to: 192'b000000000000000000000000000000000000000000000010000000000100000000001001000000000111000000000001000000000101000000000110000000000011000000010000000000010010000000010100000000010001000000011010 + Parameter BANK_MAP bound to: 36'b000000011011000000010111000000010011 + Parameter CAS_MAP bound to: 12'b000000010101 + Parameter CKE_ODT_BYTE_MAP bound to: 8'b00000000 + Parameter CKE_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011001 + Parameter ODT_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000 + Parameter CKE_ODT_AUX bound to: FALSE - type: string + Parameter CS_MAP bound to: 120'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001011 + Parameter PARITY_MAP bound to: 12'b000000000000 + Parameter RAS_MAP bound to: 12'b000000010110 + Parameter WE_MAP bound to: 12'b000000011000 + Parameter DQS_BYTE_MAP bound to: 144'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000011 + Parameter DATA0_MAP bound to: 96'b000000110100000000110010000000111000000000110101000000110001000000110111000000110110000000110011 + Parameter DATA1_MAP bound to: 96'b000000100011000000100110000000100010000000101000000000100101000000100111000000100001000000100100 + Parameter DATA2_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA3_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA4_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA5_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA6_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA7_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA8_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA9_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA10_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA11_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA12_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA13_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA14_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA15_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA16_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA17_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter MASK0_MAP bound to: 108'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101001000000111001 + Parameter MASK1_MAP bound to: 108'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter SLOT_0_CONFIG bound to: 8'b00000001 + Parameter SLOT_1_CONFIG bound to: 8'b00000000 + Parameter MEM_ADDR_ORDER bound to: BANK_ROW_COLUMN - type: string + Parameter CALIB_ROW_ADD bound to: 16'b0000000000000000 + Parameter CALIB_COL_ADD bound to: 12'b000000000000 + Parameter CALIB_BA_ADD bound to: 3'b000 + Parameter SIM_BYPASS_INIT_CAL bound to: OFF - type: string + Parameter REFCLK_FREQ bound to: 200.000000 - type: double + Parameter USE_CS_PORT bound to: 1 - type: integer + Parameter USE_DM_PORT bound to: 1 - type: integer + Parameter USE_ODT_PORT bound to: 1 - type: integer + Parameter IDELAY_ADJ bound to: OFF - type: string + Parameter FINE_PER_BIT bound to: OFF - type: string + Parameter CENTER_COMP_MODE bound to: OFF - type: string + Parameter PI_VAL_ADJ bound to: OFF - type: string + Parameter SKIP_CALIB bound to: FALSE - type: string + Parameter TAPSPERKCLK bound to: 112 - type: integer + Parameter C_S_AXI_ID_WIDTH bound to: 4 - type: integer + Parameter C_S_AXI_ADDR_WIDTH bound to: 28 - type: integer + Parameter C_S_AXI_DATA_WIDTH bound to: 128 - type: integer + Parameter C_S_AXI_SUPPORTS_NARROW_BURST bound to: 0 - type: integer + Parameter C_RD_WR_ARB_ALGORITHM bound to: RD_PRI_REG - type: string + Parameter C_S_AXI_REG_EN0 bound to: 20'b00000000000000000000 + Parameter C_S_AXI_REG_EN1 bound to: 20'b00000000000000000000 + Parameter C_S_AXI_CTRL_ADDR_WIDTH bound to: 32 - type: integer + Parameter C_S_AXI_CTRL_DATA_WIDTH bound to: 32 - type: integer + Parameter C_S_AXI_BASEADDR bound to: 0 - type: integer + Parameter C_ECC_ONOFF_RESET_VALUE bound to: 1 - type: integer + Parameter C_ECC_CE_COUNTER_WIDTH bound to: 8 - type: integer + Parameter FPGA_VOLT_TYPE bound to: N - type: string +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_mem_intfc' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_mem_intfc.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_mc' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v:73] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_rank_mach' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_mach.v:71] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_rank_cntrl' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v:79] +INFO: [Synth 8-6157] synthesizing module 'SRLC32E' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:137412] +INFO: [Synth 8-6155] done synthesizing module 'SRLC32E' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:137412] +WARNING: [Synth 8-567] referenced signal 'periodic_rd_generation.periodic_rd_timer_one' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v:509] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_rank_cntrl' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v:79] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_rank_common' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_common.v:72] +WARNING: [Synth 8-567] referenced signal 'zq_cntrl.zq_tick' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_common.v:172] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_round_robin_arb' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_round_robin_arb' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_round_robin_arb__parameterized0' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_round_robin_arb__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_rank_common' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_common.v:72] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_rank_mach' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_mach.v:71] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_mach' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_mach.v:72] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_compare' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v:74] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_compare' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v:74] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_state' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_queue' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_cntrl' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized0' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state__parameterized0' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_state__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue__parameterized0' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_queue__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized1' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state__parameterized1' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_state__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue__parameterized1' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_queue__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized2' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state__parameterized2' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_state__parameterized2' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue__parameterized2' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_queue__parameterized2' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized2' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_common' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_common.v:73] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_common' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_common.v:73] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_arb_mux' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_mux.v:69] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_arb_row_col' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v:83] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_round_robin_arb__parameterized1' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_round_robin_arb__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_arb_row_col' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v:83] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_arb_select' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:75] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_arb_select' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:75] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_arb_mux' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_mux.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_mach' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_mach.v:72] +WARNING: [Synth 8-7071] port 'idle' of module 'mig_7series_v4_2_bank_mach' is unconnected for instance 'bank_mach0' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v:670] +WARNING: [Synth 8-7023] instance 'bank_mach0' of module 'mig_7series_v4_2_bank_mach' has 74 connections declared, but only 73 given [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v:670] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_col_mach' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_col_mach.v:88] +INFO: [Synth 8-6157] synthesizing module 'RAM32M' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:129077] +INFO: [Synth 8-6155] done synthesizing module 'RAM32M' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:129077] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_col_mach' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_col_mach.v:88] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_mc' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v:73] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_top' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_top.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_mc_phy_wrapper' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:71] +INFO: [Synth 8-6157] synthesizing module 'OBUF' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96458] +INFO: [Synth 8-6155] done synthesizing module 'OBUF' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96458] +INFO: [Synth 8-6157] synthesizing module 'OBUFT' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96846] +INFO: [Synth 8-6155] done synthesizing module 'OBUFT' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96846] +INFO: [Synth 8-6157] synthesizing module 'IOBUF_INTERMDISABLE' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:79002] +INFO: [Synth 8-6155] done synthesizing module 'IOBUF_INTERMDISABLE' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:79002] +INFO: [Synth 8-6157] synthesizing module 'IOBUFDS_INTERMDISABLE' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:78516] +INFO: [Synth 8-6155] done synthesizing module 'IOBUFDS_INTERMDISABLE' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:78516] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +WARNING: [Synth 8-7071] port 'afull' of module 'mig_7series_v4_2_ddr_of_pre_fifo' is unconnected for instance 'phy_ctl_pre_fifo_0' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1428] +WARNING: [Synth 8-7023] instance 'phy_ctl_pre_fifo_0' of module 'mig_7series_v4_2_ddr_of_pre_fifo' has 8 connections declared, but only 7 given [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1428] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo__parameterized0' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +WARNING: [Synth 8-7071] port 'afull' of module 'mig_7series_v4_2_ddr_of_pre_fifo' is unconnected for instance 'phy_ctl_pre_fifo_1' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1445] +WARNING: [Synth 8-7023] instance 'phy_ctl_pre_fifo_1' of module 'mig_7series_v4_2_ddr_of_pre_fifo' has 8 connections declared, but only 7 given [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1445] +WARNING: [Synth 8-7071] port 'afull' of module 'mig_7series_v4_2_ddr_of_pre_fifo' is unconnected for instance 'phy_ctl_pre_fifo_2' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1462] +WARNING: [Synth 8-7023] instance 'phy_ctl_pre_fifo_2' of module 'mig_7series_v4_2_ddr_of_pre_fifo' has 8 connections declared, but only 7 given [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1462] +WARNING: [Synth 8-5974] attribute "use_dsp48" has been deprecated, please use "use_dsp" instead +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_mc_phy' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_4lanes' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:72] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo__parameterized1' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +INFO: [Synth 8-6157] synthesizing module 'ODDR' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100102] +INFO: [Synth 8-6155] done synthesizing module 'ODDR' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100102] +INFO: [Synth 8-6157] synthesizing module 'OBUFDS' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96472] +INFO: [Synth 8-6155] done synthesizing module 'OBUFDS' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96472] +INFO: [Synth 8-6157] synthesizing module 'PHASER_OUT_PHY' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114573] +INFO: [Synth 8-6155] done synthesizing module 'PHASER_OUT_PHY' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114573] +INFO: [Synth 8-6157] synthesizing module 'OUT_FIFO' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100824] +INFO: [Synth 8-6155] done synthesizing module 'OUT_FIFO' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100824] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_group_io' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6157] synthesizing module 'OSERDESE2' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6155] done synthesizing module 'OSERDESE2' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_group_io' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized0' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized0' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized1' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_if_post_fifo' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v:68] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v:110] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_if_post_fifo' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v:68] +INFO: [Synth 8-6157] synthesizing module 'PHASER_IN_PHY' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114436] +INFO: [Synth 8-6155] done synthesizing module 'PHASER_IN_PHY' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114436] +INFO: [Synth 8-6157] synthesizing module 'IN_FIFO' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:78141] +INFO: [Synth 8-6155] done synthesizing module 'IN_FIFO' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:78141] +INFO: [Synth 8-6157] synthesizing module 'PHASER_OUT_PHY__parameterized0' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114573] +INFO: [Synth 8-6155] done synthesizing module 'PHASER_OUT_PHY__parameterized0' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114573] +INFO: [Synth 8-6157] synthesizing module 'OUT_FIFO__parameterized0' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100824] +INFO: [Synth 8-6155] done synthesizing module 'OUT_FIFO__parameterized0' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100824] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized1' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6157] synthesizing module 'IDELAYE2' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:75752] +INFO: [Synth 8-6155] done synthesizing module 'IDELAYE2' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:75752] +INFO: [Synth 8-6157] synthesizing module 'ISERDESE2' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:80773] +INFO: [Synth 8-6155] done synthesizing module 'ISERDESE2' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:80773] +INFO: [Synth 8-6157] synthesizing module 'OSERDESE2__parameterized0' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6155] done synthesizing module 'OSERDESE2__parameterized0' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6157] synthesizing module 'OSERDESE2__parameterized1' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6155] done synthesizing module 'OSERDESE2__parameterized1' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized2' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized2' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'BUFIO' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:2224] +INFO: [Synth 8-6155] done synthesizing module 'BUFIO' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:2224] +INFO: [Synth 8-6157] synthesizing module 'PHY_CONTROL' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114664] +INFO: [Synth 8-6155] done synthesizing module 'PHY_CONTROL' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114664] +INFO: [Synth 8-226] default block is never used [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:1557] +INFO: [Synth 8-6157] synthesizing module 'PHASER_REF' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114648] +INFO: [Synth 8-6155] done synthesizing module 'PHASER_REF' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114648] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_4lanes' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:72] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_mc_phy' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy.v:70] +WARNING: [Synth 8-689] width (12) of port connection 'pi_dqs_found_lanes' does not match port width (4) of module 'mig_7series_v4_2_ddr_mc_phy' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1671] +WARNING: [Synth 8-689] width (12) of port connection 'pi_phase_locked_lanes' does not match port width (4) of module 'mig_7series_v4_2_ddr_mc_phy' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1679] +WARNING: [Synth 8-7071] port 'of_data_a_full' of module 'mig_7series_v4_2_ddr_mc_phy' is unconnected for instance 'u_ddr_mc_phy' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1579] +WARNING: [Synth 8-7023] instance 'u_ddr_mc_phy' of module 'mig_7series_v4_2_ddr_mc_phy' has 89 connections declared, but only 88 given [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1579] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_mc_phy_wrapper' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:71] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_calib_top' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:82] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_wrlvl' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:90] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:797] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_wrlvl' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:90] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v:68] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v:68] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_dqs_found_cal_hr' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:79] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_dqs_found_cal_hr' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:79] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_rdlvl' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:79] +WARNING: [Synth 8-5974] attribute "use_dsp48" has been deprecated, please use "use_dsp" instead +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2746] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_rdlvl' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:79] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_prbs_gen' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:92] +WARNING: [Synth 8-7186] Applying attribute ram_style = "distributed" is ignored, object 'rd_addr' is not inferred as ram due to incorrect usage [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:203] +WARNING: [Synth 8-7186] Applying attribute ram_style = "distributed" is ignored, object 'mem_out' is not inferred as ram due to incorrect usage [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:205] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_prbs_gen' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:92] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_init' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:89] +INFO: [Synth 8-226] default block is never used [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:5273] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_init' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:89] +WARNING: [Synth 8-7071] port 'complex_oclk_prech_req' of module 'mig_7series_v4_2_ddr_phy_init' is unconnected for instance 'u_ddr_phy_init' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:1367] +WARNING: [Synth 8-7023] instance 'u_ddr_phy_init' of module 'mig_7series_v4_2_ddr_phy_init' has 131 connections declared, but only 130 given [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:1367] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_wrcal' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:77] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:1130] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_wrcal' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:77] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_tempmon' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_tempmon' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_calib_top' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:82] +WARNING: [Synth 8-689] width (12) of port connection 'pi_dqs_found_lanes' does not match port width (4) of module 'mig_7series_v4_2_ddr_calib_top' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_top.v:1340] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_top' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_top.v:70] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_mem_intfc' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_mem_intfc.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ui_top' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_top.v:71] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ui_cmd' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_cmd.v:70] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ui_cmd' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_cmd.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ui_wr_data' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v:131] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v:342] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v:380] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ui_wr_data' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v:131] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ui_rd_data' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:140] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:406] +WARNING: [Synth 8-567] referenced signal 'not_strict_mode.occ_cnt_r' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403] +WARNING: [Synth 8-567] referenced signal 'not_strict_mode.free_rd_buf' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403] +WARNING: [Synth 8-567] referenced signal 'not_strict_mode.occ_minus_one' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403] +WARNING: [Synth 8-567] referenced signal 'not_strict_mode.occ_plus_one' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403] +WARNING: [Synth 8-567] referenced signal 'not_strict_mode.rd_data_buf_addr_r_lcl' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:432] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ui_rd_data' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:140] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ui_top' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_top.v:71] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_axi_mc' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc.v:90] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_axi_register_slice' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axi_register_slice.v:63] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized0' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized1' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized2' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized2' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_axi_register_slice' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axi_register_slice.v:63] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_axi_mc_aw_channel' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_aw_channel.v:57] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_axi_mc_cmd_translator' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_cmd_translator.v:62] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_axi_mc_incr_cmd' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_incr_cmd.v:64] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_incr_cmd' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_incr_cmd.v:64] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_axi_mc_wrap_cmd' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wrap_cmd.v:97] +INFO: [Common 17-14] Message 'Synth 8-6157' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_wrap_cmd' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wrap_cmd.v:97] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_cmd_translator' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_cmd_translator.v:62] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_wr_cmd_fsm' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wr_cmd_fsm.v:76] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_aw_channel' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_aw_channel.v:57] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_w_channel' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_w_channel.v:64] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_fifo' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_fifo.v:70] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_b_channel' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_b_channel.v:83] +INFO: [Common 17-14] Message 'Synth 8-6155' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [Synth 8-589] replacing case/wildcard equality operator === with logical equality operator == [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_r_channel.v:189] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_r_channel.v:315] +WARNING: [Synth 8-3848] Net ui_addn_clk_0 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:140] +WARNING: [Synth 8-3848] Net ui_addn_clk_1 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:141] +WARNING: [Synth 8-3848] Net ui_addn_clk_2 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:142] +WARNING: [Synth 8-3848] Net ui_addn_clk_3 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:143] +WARNING: [Synth 8-3848] Net ui_addn_clk_4 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:144] +WARNING: [Synth 8-6014] Unused sequential element periodic_rd_generation.read_this_rank_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v:487] +WARNING: [Synth 8-3936] Found unconnected internal register 'dbl_req_reg' and it is trimmed from '6' to '5' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:145] +WARNING: [Synth 8-3936] Found unconnected internal register 'dbl_last_master_ns_reg' and it is trimmed from '6' to '4' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:143] +WARNING: [Synth 8-6014] Unused sequential element last_master_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:181] +WARNING: [Synth 8-3848] Net channel[0].inh_group in module/entity mig_7series_v4_2_round_robin_arb__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:153] +WARNING: [Synth 8-3936] Found unconnected internal register 'col_addr_template_reg' and it is trimmed from '16' to '14' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v:251] +WARNING: [Synth 8-3936] Found unconnected internal register 'dbl_req_reg' and it is trimmed from '8' to '7' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:145] +WARNING: [Synth 8-3936] Found unconnected internal register 'dbl_last_master_ns_reg' and it is trimmed from '8' to '6' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:143] +WARNING: [Synth 8-6014] Unused sequential element sent_row_or_maint_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v:357] +WARNING: [Synth 8-6014] Unused sequential element mc_aux_out_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:680] +WARNING: [Synth 8-6014] Unused sequential element mc_aux_out_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:681] +WARNING: [Synth 8-3848] Net col_mux.col_row_r in module/entity mig_7series_v4_2_arb_select does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:390] +WARNING: [Synth 8-3936] Found unconnected internal register 'read_fifo.fifo_out_data_r_reg' and it is trimmed from '12' to '8' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_col_mach.v:396] +WARNING: [Synth 8-3848] Net oserdes_dqts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:143] +WARNING: [Synth 8-3848] Net oserdes_dqs_buf in module/entity mig_7series_v4_2_ddr_byte_group_io does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:144] +WARNING: [Synth 8-3848] Net oserdes_dqsts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:145] +WARNING: [Synth 8-3848] Net iserdes_dout in module/entity mig_7series_v4_2_ddr_byte_group_io does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:92] +WARNING: [Synth 8-6014] Unused sequential element ififo_rst_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:307] +WARNING: [Synth 8-3848] Net rclk in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:147] +WARNING: [Synth 8-3848] Net pi_iserdes_rst in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:193] +WARNING: [Synth 8-3848] Net pi_fine_overflow in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:195] +WARNING: [Synth 8-3848] Net pi_counter_read_val_w in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:431] +WARNING: [Synth 8-3848] Net dqs_out_of_range in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:198] +WARNING: [Synth 8-3848] Net iserdes_clk in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:275] +WARNING: [Synth 8-3848] Net iserdes_clkdiv in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:276] +WARNING: [Synth 8-3848] Net oserdes_dqts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:143] +WARNING: [Synth 8-3848] Net oserdes_dqs_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:144] +WARNING: [Synth 8-3848] Net oserdes_dqsts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:145] +WARNING: [Synth 8-3848] Net iserdes_dout in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:92] +WARNING: [Synth 8-6014] Unused sequential element ififo_rst_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:307] +WARNING: [Synth 8-3848] Net rclk in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:147] +WARNING: [Synth 8-3848] Net pi_iserdes_rst in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:193] +WARNING: [Synth 8-3848] Net pi_fine_overflow in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:195] +WARNING: [Synth 8-3848] Net pi_counter_read_val_w in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:431] +WARNING: [Synth 8-3848] Net dqs_out_of_range in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:198] +WARNING: [Synth 8-3848] Net iserdes_clk in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:275] +WARNING: [Synth 8-3848] Net iserdes_clkdiv in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:276] +WARNING: [Synth 8-6014] Unused sequential element fine_delay_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:185] +WARNING: [Synth 8-3848] Net dummy_i5 in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized1 does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:269] +WARNING: [Synth 8-3848] Net dummy_i6 in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized1 does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:270] +WARNING: [Synth 8-3848] Net dummy_i5 in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized2 does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:269] +WARNING: [Synth 8-3848] Net dummy_i6 in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized2 does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:270] +WARNING: [Synth 8-6014] Unused sequential element B_rst_primitives_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:737] +WARNING: [Synth 8-6014] Unused sequential element C_rst_primitives_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:738] +WARNING: [Synth 8-6014] Unused sequential element D_rst_primitives_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:739] +WARNING: [Synth 8-3936] Found unconnected internal register 'byte_sel_data_map_reg' and it is trimmed from '96' to '88' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:731] +WARNING: [Synth 8-3848] Net phy_data_full in module/entity mig_7series_v4_2_ddr_mc_phy_wrapper does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:227] +WARNING: [Synth 8-6014] Unused sequential element fast_cal_fine_cnt_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:790] +WARNING: [Synth 8-6014] Unused sequential element fast_cal_coarse_cnt_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:791] +WARNING: [Synth 8-6014] Unused sequential element final_corse_dec_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:792] +WARNING: [Synth 8-6014] Unused sequential element add_smallest_reg[1] was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:516] +WARNING: [Synth 8-6014] Unused sequential element add_largest_reg[0] was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:517] +WARNING: [Synth 8-6014] Unused sequential element add_largest_reg[1] was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:517] +WARNING: [Synth 8-6014] Unused sequential element dqs_wl_po_en_stg2_c_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:628] +WARNING: [Synth 8-6014] Unused sequential element po_en_stg2_c_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v:162] +WARNING: [Synth 8-6014] Unused sequential element rank_final_loop[0].final_do_max_reg[0] was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:1116] +WARNING: [Synth 8-6014] Unused sequential element rank_final_loop[0].final_do_index_reg[0] was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:1146] +WARNING: [Synth 8-6014] Unused sequential element dqsfound_retry_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:690] +WARNING: [Synth 8-3848] Net dqsfound_retry_done in module/entity mig_7series_v4_2_ddr_phy_dqs_found_cal_hr does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:131] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[0].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[1].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[2].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[3].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[4].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[5].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[6].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[7].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_stg1_done_int_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:686] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_stg1_done_int_r2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:687] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_stg1_done_int_r3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:688] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_last_byte_done_int_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:689] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_last_byte_done_int_r2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:690] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_last_byte_done_int_r3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:691] +WARNING: [Synth 8-6014] Unused sequential element fine_dly_dec_done_r3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:940] +WARNING: [Synth 8-6014] Unused sequential element fine_dly_dec_done_r4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:941] +WARNING: [Synth 8-6014] Unused sequential element regl_rank_done_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:1044] +WARNING: [Synth 8-6014] Unused sequential element cal1_state_r2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2696] +WARNING: [Synth 8-6014] Unused sequential element cal1_state_r3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2697] +WARNING: [Synth 8-6014] Unused sequential element cal1_cnt_cpt_timing_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:610] +WARNING: [Synth 8-6014] Unused sequential element sample_cnt_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:156] +WARNING: [Synth 8-6014] Unused sequential element reseed_prbs_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:157] +WARNING: [Synth 8-6014] Unused sequential element lfsr_q_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:174] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.phy_tmp_cs1_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4271] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.phy_tmp_odt_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4273] +WARNING: [Synth 8-6014] Unused sequential element wrlvl_final_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1421] +WARNING: [Synth 8-6014] Unused sequential element wrlvl_rank_cntr_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1539] +WARNING: [Synth 8-6014] Unused sequential element cnt_pwron_cke_done_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1781] +WARNING: [Synth 8-6014] Unused sequential element cnt_init_pre_wait_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1814] +WARNING: [Synth 8-6014] Unused sequential element cnt_init_pre_wait_done_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1815] +WARNING: [Synth 8-6014] Unused sequential element rnk_ref_cnt_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1941] +WARNING: [Synth 8-6014] Unused sequential element read_calib_int_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:2720] +WARNING: [Synth 8-6014] Unused sequential element read_calib_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:2727] +WARNING: [Synth 8-6014] Unused sequential element pi_dqs_found_rank_done_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:2778] +WARNING: [Synth 8-6014] Unused sequential element pi_dqs_found_all_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:2783] +WARNING: [Synth 8-6014] Unused sequential element complex_row0_rd_done_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:3339] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_wr_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:3632] +WARNING: [Synth 8-6014] Unused sequential element extend_cal_pat_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:3638] +WARNING: [Synth 8-6014] Unused sequential element cnt_init_data_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:3714] +WARNING: [Synth 8-6014] Unused sequential element victim_byte_cnt_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:818] +WARNING: [Synth 8-3936] Found unconnected internal register 'rdlvl_start_dly0_r_reg' and it is trimmed from '16' to '15' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1228] +WARNING: [Synth 8-3936] Found unconnected internal register 'wrcal_start_dly_r_reg' and it is trimmed from '16' to '15' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1230] +WARNING: [Synth 8-3936] Found unconnected internal register 'oclkdelay_start_dly_r_reg' and it is trimmed from '16' to '15' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1232] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr2_r_reg[1] was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4265] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr2_r_reg[2] was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4265] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr2_r_reg[3] was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4265] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr1_r_reg[1] was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4268] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr1_r_reg[2] was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4268] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr1_r_reg[3] was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4268] +WARNING: [Synth 8-6014] Unused sequential element prech_done_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1303] +WARNING: [Synth 8-6014] Unused sequential element calib_cmd_wren_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4229] +WARNING: [Synth 8-3848] Net calib_aux_out in module/entity mig_7series_v4_2_ddr_phy_init does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:276] +WARNING: [Synth 8-6014] Unused sequential element rd_active_r4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:534] +WARNING: [Synth 8-6014] Unused sequential element rd_active_r5_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:535] +WARNING: [Synth 8-6014] Unused sequential element pat1_detect_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:1124] +WARNING: [Synth 8-6014] Unused sequential element early1_detect_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:1125] +WARNING: [Synth 8-6014] Unused sequential element rd_mux_sel_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:438] +WARNING: [Synth 8-3848] Net i in module/entity mig_7series_v4_2_ddr_phy_wrcal does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:155] +WARNING: [Synth 8-6014] Unused sequential element calib_complete_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v:182] +WARNING: [Synth 8-6014] Unused sequential element sample_en_cnt_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v:188] +WARNING: [Synth 8-6014] Unused sequential element device_temp_capture_102_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v:290] +WARNING: [Synth 8-6014] Unused sequential element tempmon_sel_pi_incdec_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:883] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:898] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:899] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:900] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:901] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r5_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:902] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r6_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:903] +WARNING: [Synth 8-6014] Unused sequential element skip_calib_tap_off.skip_cal_tempmon_samp_en_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:2262] +WARNING: [Synth 8-6014] Unused sequential element wrlvl_final_mux_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:834] +WARNING: [Synth 8-3848] Net dbg_skip_cal in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:673] +WARNING: [Synth 8-3848] Net coarse_dec_err in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:662] +WARNING: [Synth 8-3848] Net dbg_poc in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:335] +WARNING: [Synth 8-3848] Net fine_delay_incdec_pb in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:341] +WARNING: [Synth 8-3848] Net fine_delay_sel in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:342] +WARNING: [Synth 8-3848] Net lim_done in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:620] +WARNING: [Synth 8-3848] Net lim2init_write_request in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:619] +WARNING: [Synth 8-3848] Net complex_ocal_num_samples_done_r in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:533] +WARNING: [Synth 8-3848] Net complex_ocal_rd_victim_sel in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:534] +WARNING: [Synth 8-3848] Net complex_victim_inc in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:592] +WARNING: [Synth 8-3848] Net rd_victim_sel in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:588] +WARNING: [Synth 8-3848] Net oclkdelay_center_calib_start in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:597] +WARNING: [Synth 8-3848] Net oclk_center_write_resume in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:615] +WARNING: [Synth 8-3848] Net oclkdelay_center_calib_done in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:616] +WARNING: [Synth 8-6014] Unused sequential element app_wdf_rdy_r_copy4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v:268] +WARNING: [Synth 8-6014] Unused sequential element int_next_pending_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_incr_cmd.v:191] +WARNING: [Synth 8-6014] Unused sequential element sel_first_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_incr_cmd.v:220] +WARNING: [Synth 8-6014] Unused sequential element int_next_pending_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wrap_cmd.v:221] +WARNING: [Synth 8-6014] Unused sequential element sel_first_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wrap_cmd.v:239] +WARNING: [Synth 8-3848] Net cmd_wr_bytes in module/entity mig_7series_v4_2_axi_mc_w_channel does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_w_channel.v:96] +WARNING: [Synth 8-6014] Unused sequential element rd_last_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_r_channel.v:216] +WARNING: [Synth 8-3848] Net error in module/entity mig_7series_v4_2_memc_ui_top_axi does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_memc_ui_top_axi.v:555] +WARNING: [Synth 8-3848] Net app_correct_en_i in module/entity mig_7series_v4_2_memc_ui_top_axi does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_memc_ui_top_axi.v:500] +WARNING: [Synth 8-3848] Net s_axi_ctrl_awvalid in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:754] +WARNING: [Synth 8-3848] Net s_axi_ctrl_awaddr in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:756] +WARNING: [Synth 8-3848] Net s_axi_ctrl_wvalid in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:758] +WARNING: [Synth 8-3848] Net s_axi_ctrl_wdata in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:760] +WARNING: [Synth 8-3848] Net s_axi_ctrl_bready in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:763] +WARNING: [Synth 8-3848] Net s_axi_ctrl_arvalid in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:766] +WARNING: [Synth 8-3848] Net s_axi_ctrl_araddr in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:768] +WARNING: [Synth 8-3848] Net s_axi_ctrl_rready in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:771] +WARNING: [Synth 8-3848] Net device_temp_i in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:784] +WARNING: [Synth 8-7129] Port mc_app_rd_last in module mig_7series_v4_2_axi_mc_r_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port axlen[7] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axlen[6] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axlen[5] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axlen[4] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[2] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[1] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[0] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[2] in module mig_7series_v4_2_axi_mc_incr_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[1] in module mig_7series_v4_2_axi_mc_incr_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[0] in module mig_7series_v4_2_axi_mc_incr_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axburst[0] in module mig_7series_v4_2_axi_mc_cmd_translator is either unconnected or has no load +WARNING: [Synth 8-7129] Port arlock[1] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arlock[0] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arcache[3] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arcache[2] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arcache[1] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arcache[0] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arprot[2] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arprot[1] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arprot[0] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port b_resp_rdy in module mig_7series_v4_2_axi_mc_b_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port cmd_wr_bytes in module mig_7series_v4_2_axi_mc_w_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awvalid in module mig_7series_v4_2_axi_mc_w_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port w_ignore_begin in module mig_7series_v4_2_axi_mc_w_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port w_ignore_end in module mig_7series_v4_2_axi_mc_w_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awlock[1] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awlock[0] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awcache[3] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awcache[2] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awcache[1] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awcache[0] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awprot[2] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awprot[1] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awprot[0] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port cmd_wr_bytes in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice__parameterized1 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice__parameterized1 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice__parameterized0 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice__parameterized0 is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_AWUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_WUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_ARUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port M_AXI_BUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port M_AXI_RUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[7] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[6] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[5] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[4] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[3] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[2] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[1] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[0] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[7] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[6] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[5] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[4] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[3] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[2] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[1] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[0] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[7] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[6] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[5] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[4] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[3] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[2] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[1] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[0] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port wr_data_addr[4] in module mig_7series_v4_2_ui_top is either unconnected or has no load +WARNING: [Synth 8-7129] Port accept in module mig_7series_v4_2_ui_top is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[11] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[10] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[9] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[8] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[7] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[6] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[5] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[4] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[3] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[2] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[1] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[0] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[99] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[98] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[97] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[96] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[95] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[94] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[93] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[16] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[15] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[14] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[12] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[11] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[10] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2910.293 ; gain = 668.254 ; free physical = 193728 ; free virtual = 542682 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2910.293 ; gain = 668.254 ; free physical = 193715 ; free virtual = 542669 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2910.293 ; gain = 668.254 ; free physical = 193715 ; free virtual = 542669 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.2 . Memory (MB): peak = 2910.293 ; gain = 0.000 ; free physical = 193740 ; free virtual = 542692 +INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3_ooc.xdc] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3_ooc.xdc] +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] +WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc:346] +WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc:353] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/arty_ddr3_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/arty_ddr3_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +INFO: [Timing 38-2] Deriving generated clocks +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.137 ; gain = 0.000 ; free physical = 193624 ; free virtual = 542576 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 70 instances were transformed. + IOBUFDS_INTERMDISABLE => IOBUFDS_INTERMDISABLE (IBUFDS_INTERMDISABLE_INT(x2), INV, OBUFTDS(x2)): 2 instances + IOBUF_INTERMDISABLE => IOBUF_INTERMDISABLE (IBUF_INTERMDISABLE, OBUFT): 16 instances + OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 1 instance + RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 51 instances + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.19 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3019.137 ; gain = 0.000 ; free physical = 193629 ; free virtual = 542581 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 3019.137 ; gain = 777.098 ; free physical = 193667 ; free virtual = 542623 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a100tcsg324-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 3027.141 ; gain = 785.102 ; free physical = 193667 ; free virtual = 542623 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_ck_n[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc, line 27). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_ck_p[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc, line 28). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:14 . Memory (MB): peak = 3027.141 ; gain = 785.102 ; free physical = 193677 ; free virtual = 542633 +--------------------------------------------------------------------------------- +INFO: [Synth 8-802] inferred FSM for state register 'xadc_supplied_temperature.tempmon_state_reg' in module 'mig_7series_v4_2_tempmon' +INFO: [Synth 8-802] inferred FSM for state register 'wl_state_r_reg' in module 'mig_7series_v4_2_ddr_phy_wrlvl' +INFO: [Synth 8-802] inferred FSM for state register 'fine_adj_state_r_reg' in module 'mig_7series_v4_2_ddr_phy_dqs_found_cal_hr' +INFO: [Synth 8-802] inferred FSM for state register 'cal1_state_r_reg' in module 'mig_7series_v4_2_ddr_phy_rdlvl' +INFO: [Synth 8-802] inferred FSM for state register 'tempmon_state_reg' in module 'mig_7series_v4_2_ddr_phy_tempmon' +INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'mig_7series_v4_2_axi_mc_r_channel' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + INIT_IDLE | 0001 | 000 + REQUEST_READ_TEMP | 1000 | 001 + WAIT_FOR_READ | 0100 | 010 + READ | 0010 | 011 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'xadc_supplied_temperature.tempmon_state_reg' using encoding 'one-hot' in module 'mig_7series_v4_2_tempmon' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + WL_IDLE | 01110 | 00000 + WL_INIT | 10010 | 00001 + WL_INIT_FINE_INC | 01100 | 00010 + WL_INIT_FINE_INC_WAIT1 | 01000 | 00011 + WL_INIT_FINE_INC_WAIT | 01001 | 00100 + WL_INIT_FINE_DEC | 11001 | 00101 + WL_INIT_FINE_DEC_WAIT1 | 10111 | 11001 + WL_INIT_FINE_DEC_WAIT | 11000 | 00110 + WL_WAIT | 00110 | 01000 + WL_EDGE_CHECK | 11011 | 01001 + WL_DQS_CNT | 10100 | 01011 + WL_FINE_DEC | 00000 | 01110 + WL_FINE_DEC_WAIT1 | 00001 | 11010 + WL_FINE_DEC_WAIT | 10001 | 01111 + WL_CORSE_DEC | 10110 | 10100 + WL_CORSE_DEC_WAIT | 11010 | 10101 + WL_CORSE_DEC_WAIT1 | 10101 | 10110 + WL_2RANK_DQS_CNT | 00010 | 01101 + WL_DQS_CHECK | 00011 | 01010 + WL_FINE_INC | 01101 | 00111 + WL_FINE_INC_WAIT | 10011 | 10111 + WL_2RANK_FINAL_TAP | 01111 | 11000 + WL_CORSE_INC | 01011 | 10000 + WL_CORSE_INC_WAIT_TMP | 10000 | 11011 + WL_CORSE_INC_WAIT | 01010 | 10001 + WL_CORSE_INC_WAIT1 | 00111 | 10010 + WL_CORSE_INC_WAIT2 | 00101 | 10011 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'wl_state_r_reg' using encoding 'sequential' in module 'mig_7series_v4_2_ddr_phy_wrlvl' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + FINE_ADJ_IDLE | 0000 | 0000 + RST_WAIT | 0001 | 0011 + FINE_ADJ_DONE | 0010 | 1111 + RST_POSTWAIT | 0011 | 0001 + RST_POSTWAIT1 | 0100 | 0010 + FINE_ADJ_INIT | 0101 | 0100 + FINE_INC | 0110 | 0101 + FINE_INC_WAIT | 0111 | 0110 + FINE_INC_PREWAIT | 1000 | 0111 + DETECT_PREWAIT | 1001 | 1000 + DETECT_DQSFOUND | 1010 | 1001 + FINE_DEC | 1011 | 1011 + FINE_DEC_WAIT | 1100 | 1100 + FINE_DEC_PREWAIT | 1101 | 1101 + FINAL_WAIT | 1110 | 1110 + PRECH_WAIT | 1111 | 1010 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'fine_adj_state_r_reg' using encoding 'sequential' in module 'mig_7series_v4_2_ddr_phy_dqs_found_cal_hr' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + CAL1_IDLE | 00000000000000000000000000010000000 | 000000 + CAL1_NEW_DQS_WAIT | 00000000000000000000010000000000000 | 000001 + CAL1_STORE_FIRST_WAIT | 00000000000000000010000000000000000 | 000010 + CAL1_PAT_DETECT | 00000000000000100000000000000000000 | 000011 + CAL1_DQ_IDEL_TAP_INC | 00000000000000000000000000000000100 | 000100 +CAL1_DQ_IDEL_TAP_INC_WAIT | 00000000000000000000000000000001000 | 000101 + CAL1_MPR_PAT_DETECT | 00000000000000000000000010000000000 | 011111 + CAL1_VALID_WAIT | 10000000000000000000000000000000000 | 011110 + CAL1_DETECT_EDGE | 00000000000001000000000000000000000 | 001000 + CAL1_CALC_IDEL | 00000100000000000000000000000000000 | 001011 + CAL1_CENTER_WAIT | 00000000000000000000000000000000001 | 100010 + CAL1_IDEL_DEC_CPT | 00000000000000000000000000000000010 | 001100 + CAL1_DQ_IDEL_TAP_DEC | 00000000000000000001000000000000000 | 000110 +CAL1_DQ_IDEL_TAP_DEC_WAIT | 00100000000000000000000000000000000 | 000111 + CAL1_NEXT_DQS | 00000000000000000000000000000010000 | 001110 + CAL1_REGL_LOAD | 00000000000000000000000000001000000 | 011011 + CAL1_DONE | 00000000000000000000000000000100000 | 001111 + CAL1_NEW_DQS_PREWAIT | 00000000000000000000000000100000000 | 100000 + CAL1_MPR_NEW_DQS_WAIT | 00000000000000000000000001000000000 | 011101 + CAL1_IDEL_DEC_CPT_WAIT | 00000000000000000000100000000000000 | 001101 + CAL1_RD_STOP_FOR_PI_INC | 00000000000000000000000100000000000 | 100001 + CAL1_IDEL_INC_CPT | 00000000000000000000001000000000000 | 001001 + CAL1_IDEL_INC_CPT_WAIT | 00010000000000000000000000000000000 | 001010 + CAL1_RDLVL_ERR | 00000000000010000000000000000000000 | 011100 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'cal1_state_r_reg' using encoding 'one-hot' in module 'mig_7series_v4_2_ddr_phy_rdlvl' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 00000000001 | 00000000001 + INIT | 00000000010 | 00000000010 + NEUTRAL | 00001000000 | 00001000000 + ONE_DEC | 00010000000 | 00010000000 + TWO_DEC | 00100000000 | 00100000000 + THREE_DEC | 01000000000 | 01000000000 + FOUR_DEC | 10000000000 | 10000000000 + ONE_INC | 00000100000 | 00000100000 + TWO_INC | 00000010000 | 00000010000 + THREE_INC | 00000001000 | 00000001000 + FOUR_INC | 00000000100 | 00000000100 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'tempmon_state_reg' in module 'mig_7series_v4_2_ddr_phy_tempmon' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + ZERO | 11 | 10 + ONE | 01 | 11 + TWO | 00 | 01 + iSTATE | 10 | 00 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'mig_7series_v4_2_axi_mc_r_channel' +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:20 ; elapsed = 00:00:19 . Memory (MB): peak = 3027.141 ; gain = 785.102 ; free physical = 193714 ; free virtual = 542673 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 4 Input 32 Bit Adders := 2 + 3 Input 32 Bit Adders := 1 + 2 Input 28 Bit Adders := 2 + 2 Input 13 Bit Adders := 1 + 2 Input 12 Bit Adders := 15 + 2 Input 11 Bit Adders := 1 + 2 Input 10 Bit Adders := 6 + 2 Input 9 Bit Adders := 4 + 2 Input 8 Bit Adders := 8 + 3 Input 7 Bit Adders := 2 + 2 Input 7 Bit Adders := 1 + 2 Input 6 Bit Adders := 30 + 3 Input 6 Bit Adders := 3 + 2 Input 5 Bit Adders := 37 + 2 Input 4 Bit Adders := 34 + 2 Input 3 Bit Adders := 20 + 3 Input 3 Bit Adders := 1 + 2 Input 2 Bit Adders := 51 + 3 Input 2 Bit Adders := 3 + 4 Input 2 Bit Adders := 5 + 5 Input 2 Bit Adders := 1 + 8 Input 2 Bit Adders := 1 + 2 Input 1 Bit Adders := 5 + 3 Input 1 Bit Adders := 1 + 4 Input 1 Bit Adders := 1 + 5 Input 1 Bit Adders := 1 + 6 Input 1 Bit Adders := 1 + 7 Input 1 Bit Adders := 1 + 8 Input 1 Bit Adders := 1 + 9 Input 1 Bit Adders := 1 ++---XORs : + 2 Input 1 Bit XORs := 1 ++---Registers : + 144 Bit Registers := 1 + 128 Bit Registers := 5 + 88 Bit Registers := 1 + 80 Bit Registers := 3 + 56 Bit Registers := 1 + 32 Bit Registers := 3 + 30 Bit Registers := 1 + 28 Bit Registers := 6 + 16 Bit Registers := 13 + 15 Bit Registers := 4 + 14 Bit Registers := 6 + 13 Bit Registers := 1 + 12 Bit Registers := 33 + 11 Bit Registers := 1 + 10 Bit Registers := 4 + 9 Bit Registers := 12 + 8 Bit Registers := 15 + 7 Bit Registers := 5 + 6 Bit Registers := 59 + 5 Bit Registers := 46 + 4 Bit Registers := 82 + 3 Bit Registers := 47 + 2 Bit Registers := 66 + 1 Bit Registers := 1542 ++---Muxes : + 2 Input 128 Bit Muxes := 10 + 4 Input 128 Bit Muxes := 1 + 2 Input 127 Bit Muxes := 1 + 2 Input 80 Bit Muxes := 6 + 2 Input 56 Bit Muxes := 1 + 24 Input 35 Bit Muxes := 1 + 2 Input 35 Bit Muxes := 22 + 2 Input 32 Bit Muxes := 1 + 2 Input 30 Bit Muxes := 12 + 4 Input 30 Bit Muxes := 4 + 2 Input 28 Bit Muxes := 11 + 2 Input 21 Bit Muxes := 8 + 2 Input 16 Bit Muxes := 8 + 3 Input 16 Bit Muxes := 1 + 3 Input 14 Bit Muxes := 1 + 2 Input 14 Bit Muxes := 8 + 4 Input 14 Bit Muxes := 1 + 2 Input 12 Bit Muxes := 5 + 12 Input 11 Bit Muxes := 1 + 2 Input 11 Bit Muxes := 1 + 2 Input 10 Bit Muxes := 7 + 4 Input 9 Bit Muxes := 6 + 2 Input 9 Bit Muxes := 18 + 2 Input 8 Bit Muxes := 61 + 5 Input 8 Bit Muxes := 1 + 2 Input 7 Bit Muxes := 64 + 3 Input 7 Bit Muxes := 1 + 4 Input 7 Bit Muxes := 1 + 5 Input 7 Bit Muxes := 2 + 2 Input 6 Bit Muxes := 81 + 4 Input 6 Bit Muxes := 8 + 27 Input 6 Bit Muxes := 4 + 5 Input 6 Bit Muxes := 2 + 16 Input 6 Bit Muxes := 1 + 24 Input 6 Bit Muxes := 5 + 3 Input 6 Bit Muxes := 2 + 2 Input 5 Bit Muxes := 35 + 8 Input 5 Bit Muxes := 2 + 27 Input 5 Bit Muxes := 1 + 58 Input 5 Bit Muxes := 1 + 24 Input 5 Bit Muxes := 1 + 4 Input 5 Bit Muxes := 2 + 3 Input 5 Bit Muxes := 4 + 2 Input 4 Bit Muxes := 67 + 32 Input 4 Bit Muxes := 1 + 8 Input 4 Bit Muxes := 1 + 7 Input 4 Bit Muxes := 1 + 2 Input 3 Bit Muxes := 69 + 27 Input 3 Bit Muxes := 6 + 3 Input 3 Bit Muxes := 1 + 4 Input 3 Bit Muxes := 3 + 8 Input 3 Bit Muxes := 1 + 2 Input 2 Bit Muxes := 101 + 4 Input 2 Bit Muxes := 7 + 3 Input 2 Bit Muxes := 9 + 8 Input 2 Bit Muxes := 4 + 27 Input 2 Bit Muxes := 1 + 24 Input 2 Bit Muxes := 2 + 5 Input 2 Bit Muxes := 1 + 10 Input 2 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 491 + 3 Input 1 Bit Muxes := 12 + 8 Input 1 Bit Muxes := 4 + 4 Input 1 Bit Muxes := 204 + 27 Input 1 Bit Muxes := 27 + 5 Input 1 Bit Muxes := 1 + 16 Input 1 Bit Muxes := 21 + 24 Input 1 Bit Muxes := 30 + 10 Input 1 Bit Muxes := 17 + 12 Input 1 Bit Muxes := 4 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 240 (col length:80) +BRAMs: 270 (col length: RAMB18 80 RAMB36 40) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +WARNING: [Synth 8-7080] Parallel synthesis criteria is not met +WARNING: [Synth 8-3936] Found unconnected internal register 'byte_sel_data_map_reg' and it is trimmed from '88' to '4' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:731] +WARNING: [Synth 8-3936] Found unconnected internal register 'oclkdelay_start_dly_r_reg' and it is trimmed from '15' to '14' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1232] +WARNING: [Synth 8-3936] Found unconnected internal register 'wrcal_start_dly_r_reg' and it is trimmed from '15' to '14' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1230] +WARNING: [Synth 8-3332] Sequential element (FSM_onehot_cal1_state_r_reg[33]) is unused and will be removed from module mig_7series_v4_2_ddr_phy_rdlvl. +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:18 ; elapsed = 00:01:18 . Memory (MB): peak = 3299.703 ; gain = 1057.664 ; free physical = 191400 ; free virtual = 540545 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +ROM: Preliminary Mapping Report ++------------------------------+------------+---------------+----------------+ +|Module Name | RTL Object | Depth x Width | Implemented As | ++------------------------------+------------+---------------+----------------+ +|mig_7series_v4_2_ddr_prbs_gen | mem_out | 256x18 | LUT | +|mig_7series_v4_2_ddr_prbs_gen | mem_out | 256x18 | LUT | ++------------------------------+------------+---------------+----------------+ + + +Distributed RAM: Preliminary Mapping Report (see note below) ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ +|arty_ddr3 | of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ + +Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +WARNING: [Synth 8-3321] set_false_path : Empty through list for constraint at line 359 of /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc:359] +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:22 ; elapsed = 00:01:22 . Memory (MB): peak = 3299.703 ; gain = 1057.664 ; free physical = 196036 ; free virtual = 545183 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:01:22 ; elapsed = 00:01:23 . Memory (MB): peak = 3299.703 ; gain = 1057.664 ; free physical = 196091 ; free virtual = 545237 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Distributed RAM: Final Mapping Report ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ +|arty_ddr3 | of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:01:25 ; elapsed = 00:01:25 . Memory (MB): peak = 3299.703 ; gain = 1057.664 ; free physical = 195925 ; free virtual = 545073 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:01:28 ; elapsed = 00:01:28 . Memory (MB): peak = 3299.703 ; gain = 1057.664 ; free physical = 195750 ; free virtual = 544898 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:01:28 ; elapsed = 00:01:28 . Memory (MB): peak = 3299.703 ; gain = 1057.664 ; free physical = 195750 ; free virtual = 544898 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:29 ; elapsed = 00:01:29 . Memory (MB): peak = 3299.703 ; gain = 1057.664 ; free physical = 195852 ; free virtual = 544999 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:01:29 ; elapsed = 00:01:29 . Memory (MB): peak = 3299.703 ; gain = 1057.664 ; free physical = 195852 ; free virtual = 544999 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:01:29 ; elapsed = 00:01:29 . Memory (MB): peak = 3299.703 ; gain = 1057.664 ; free physical = 195852 ; free virtual = 544999 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:01:29 ; elapsed = 00:01:29 . Memory (MB): peak = 3299.703 ; gain = 1057.664 ; free physical = 195852 ; free virtual = 544999 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Static Shift Register Report: ++------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ +|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | ++------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/rclk_delay_reg[11] | 12 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/rst_r4_reg | 4 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/phy_ctl_ready_r5_reg | 5 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay/delay_done_r4_reg | 4 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/init_dqsfound_done_r5_reg | 3 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrlvl_rank_done_r7_reg | 6 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prech_done_reg | 17 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_start_dly_r_reg[5] | 6 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg[14] | 15 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_pat_match_div4.pat_data_match_valid_r_reg | 3 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] | 3 | 4 | NO | NO | YES | 4 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/wrcal_pat_resume_reg | 3 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/reset_if_r9_reg | 9 | 1 | NO | NO | YES | 1 | 0 | ++------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ + + +Dynamic Shift Register Report: ++------------+----------------+--------+------------+--------+---------+--------+--------+--------+ +|Module Name | RTL Name | Length | Data Width | SRL16E | SRLC32E | Mux F7 | Mux F8 | Mux F9 | ++------------+----------------+--------+------------+--------+---------+--------+--------+--------+ +|dsrl | memory_reg[7] | 4 | 4 | 4 | 0 | 0 | 0 | 0 | +|dsrl__1 | memory_reg[31] | 129 | 129 | 0 | 129 | 0 | 0 | 0 | +|dsrl__2 | memory_reg[29] | 7 | 7 | 0 | 7 | 0 | 0 | 0 | ++------------+----------------+--------+------------+--------+---------+--------+--------+--------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+----------------------+------+ +| |Cell |Count | ++------+----------------------+------+ +|1 |BUFG | 3| +|2 |BUFH | 1| +|3 |BUFIO | 1| +|4 |CARRY4 | 124| +|5 |IDELAYCTRL | 1| +|6 |IDELAYE2 | 16| +|7 |IN_FIFO | 2| +|8 |ISERDESE2 | 16| +|9 |LUT1 | 375| +|10 |LUT2 | 438| +|11 |LUT3 | 1023| +|12 |LUT4 | 905| +|13 |LUT5 | 1361| +|14 |LUT6 | 1262| +|15 |MMCME2_ADV | 1| +|16 |MUXF7 | 28| +|17 |ODDR | 5| +|18 |OSERDESE2 | 43| +|21 |OUT_FIFO | 4| +|23 |PHASER_IN_PHY | 2| +|24 |PHASER_OUT_PHY | 4| +|26 |PHASER_REF | 1| +|27 |PHY_CONTROL | 1| +|28 |PLLE2_ADV | 1| +|29 |RAM32M | 112| +|30 |RAM32X1D | 2| +|31 |SRL16E | 20| +|32 |SRLC32E | 134| +|33 |XADC | 1| +|34 |FDCE | 2| +|35 |FDPE | 73| +|36 |FDRE | 3995| +|37 |FDSE | 123| +|38 |IOBUFDS_INTERMDISABLE | 2| +|39 |IOBUF_INTERMDISABLE | 16| +|40 |OBUF | 24| +|41 |OBUFDS | 1| +|42 |OBUFT | 2| ++------+----------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:01:29 ; elapsed = 00:01:29 . Memory (MB): peak = 3299.703 ; gain = 1057.664 ; free physical = 195852 ; free virtual = 544999 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 6 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:01:25 ; elapsed = 00:01:26 . Memory (MB): peak = 3299.703 ; gain = 948.820 ; free physical = 195852 ; free virtual = 544999 +Synthesis Optimization Complete : Time (s): cpu = 00:01:29 ; elapsed = 00:01:29 . Memory (MB): peak = 3299.711 ; gain = 1057.664 ; free physical = 195852 ; free virtual = 544999 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.13 . Memory (MB): peak = 3299.711 ; gain = 0.000 ; free physical = 196176 ; free virtual = 545323 +INFO: [Netlist 29-17] Analyzing 325 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3_ooc.xdc] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3_ooc.xdc] +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] +INFO: [Opt 31-138] Pushed 2 inverter(s) to 16 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3355.730 ; gain = 0.000 ; free physical = 196204 ; free virtual = 545351 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 133 instances were transformed. + IOBUFDS_INTERMDISABLE => IOBUFDS_INTERMDISABLE (IBUFDS_INTERMDISABLE_INT(x2), INV, OBUFTDS(x2)): 2 instances + IOBUF_INTERMDISABLE => IOBUF_INTERMDISABLE (IBUF_INTERMDISABLE, OBUFT): 16 instances + OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 1 instance + RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 112 instances + RAM32X1D => RAM32X1D (RAMD32(x2)): 2 instances + +Synth Design complete | Checksum: cc6d6f52 +INFO: [Common 17-83] Releasing license: Synthesis +249 Infos, 303 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:01:34 ; elapsed = 00:01:31 . Memory (MB): peak = 3355.730 ; gain = 1119.629 ; free physical = 196197 ; free virtual = 545343 +INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 3064.380; main = 2772.867; forked = 443.080 +INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 4342.293; main = 3355.734; forked = 1042.586 +INFO: [Coretcl 2-1174] Renamed 88 cell refs. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-2] Deriving generated clocks +INFO: [Timing 38-480] Writing timing data to binary archive. +Write ShapeDB Complete: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3419.746 ; gain = 0.000 ; free physical = 195973 ; free virtual = 545119 +Wrote PlaceDB: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3419.746 ; gain = 0.000 ; free physical = 195965 ; free virtual = 545111 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3419.746 ; gain = 0.000 ; free physical = 195965 ; free virtual = 545111 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3419.746 ; gain = 0.000 ; free physical = 195965 ; free virtual = 545111 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3419.746 ; gain = 0.000 ; free physical = 195965 ; free virtual = 545111 +Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3419.746 ; gain = 0.000 ; free physical = 195957 ; free virtual = 545104 +Write Physdb Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3419.746 ; gain = 0.000 ; free physical = 195957 ; free virtual = 545104 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3.dcp' has been generated. +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data0/tools/Xilinx/Vivado/2024.1/data/ip'. +WARNING: [Vivado 12-13650] The IP file '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc.xci' has been moved from its original location, as a result the outputs for this IP will now be generated in '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc'. Alternatively a copy of the IP can be imported into the project using one of the 'import_ip' or 'import_files' commands. +Command: synth_design -top toy_axi_cdc -part xc7a100tcsg324-1 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 3419.746 ; gain = 0.000 ; free physical = 194787 ; free virtual = 543940 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'toy_axi_cdc' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/synth/toy_axi_cdc.v:53] +INFO: [Synth 8-6157] synthesizing module 'axi_clock_converter_v2_1_30_axi_clock_converter' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/hdl/axi_clock_converter_v2_1_vl_rfs.v:650] +INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_single' [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:152] +INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_single' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:152] +INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_async_rst' [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1175] +INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_async_rst' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1175] +INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_single__parameterized1' [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:152] +INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_single__parameterized1' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:152] +INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray' [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:283] +INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:283] +INFO: [Synth 8-6155] done synthesizing module 'axi_clock_converter_v2_1_30_axi_clock_converter' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/hdl/axi_clock_converter_v2_1_vl_rfs.v:650] +INFO: [Synth 8-6155] done synthesizing module 'toy_axi_cdc' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/synth/toy_axi_cdc.v:53] +WARNING: [Synth 8-7129] Port ALMOST_FULL_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ALMOST_EMPTY_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_ACK_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port VALID_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port OVERFLOW_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port UNDERFLOW_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DATA_COUNT_I[4] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DATA_COUNT_I[3] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DATA_COUNT_I[2] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DATA_COUNT_I[1] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DATA_COUNT_I[0] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[4] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[3] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[2] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[1] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[0] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[4] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[3] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[2] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[1] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[0] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port SBITERR_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DBITERR_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_RST in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port SAFETY_CKT_WR_RST in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[3] in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[2] in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[1] in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[0] in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module wr_bin_cntr is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_EN_INTO_LOGIC in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_RST_INTO_LOGIC in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_EN in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST_FULL_FF in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_RST_BUSY in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port EMPTY in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RAM_RD_EN in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port ALMOST_EMPTY in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[3] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[2] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[1] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[0] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[3] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[2] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[1] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[0] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_NEGATE[3] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_NEGATE[2] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_NEGATE[1] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_NEGATE[0] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module rd_fwft is either unconnected or has no load +WARNING: [Synth 8-7129] Port SAFETY_CKT_RD_RST in module rd_fwft is either unconnected or has no load +WARNING: [Synth 8-7129] Port RAM_ALMOST_EMPTY in module rd_fwft is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port SAFETY_CKT_RD_RST in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_PNTR_PLUS2[3] in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_PNTR_PLUS2[2] in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_PNTR_PLUS2[1] in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_PNTR_PLUS2[0] in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module rd_bin_cntr is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_EN_INTO_LOGIC in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_RST_INTO_LOGIC in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_RST_BUSY in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RAM_WR_EN in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RST_FULL_FF in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port ALMOST_FULL_FB in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port FULL in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS1_RD[3] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS1_RD[2] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS1_RD[1] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS1_RD[0] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[3] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[2] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[1] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[0] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_ASSERT[3] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_ASSERT[2] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_ASSERT[1] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_ASSERT[0] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_NEGATE[3] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_NEGATE[2] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_NEGATE[1] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_NEGATE[0] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_RST in module clk_x_pntrs is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_RST in module clk_x_pntrs is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module dmem__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FAB_REGOUT_EN in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port SFT_RST in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port SAFETY_CKT_RD_RST in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port SLEEP in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port INJECTDBITERR in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port INJECTSBITERR in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port CLK in module input_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port INT_CLK in module input_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[3] in module input_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[2] in module input_blk__parameterized2 is either unconnected or has no load +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 3419.746 ; gain = 0.000 ; free physical = 194544 ; free virtual = 543693 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 3419.746 ; gain = 0.000 ; free physical = 194544 ; free virtual = 543693 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 3419.746 ; gain = 0.000 ; free physical = 194544 ; free virtual = 543693 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3419.746 ; gain = 0.000 ; free physical = 194545 ; free virtual = 543695 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_ooc.xdc] for cell 'inst' +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_ooc.xdc] for cell 'inst' +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/toy_axi_cdc_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/toy_axi_cdc_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/toy_axi_cdc_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/toy_axi_cdc_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +INFO: [Project 1-1714] 33 XPM XDC files have been applied to the design. +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3465.559 ; gain = 0.000 ; free physical = 194063 ; free virtual = 543212 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3465.559 ; gain = 0.000 ; free physical = 194063 ; free virtual = 543212 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 3465.559 ; gain = 45.812 ; free physical = 194088 ; free virtual = 543238 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a100tcsg324-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 3465.559 ; gain = 45.812 ; free physical = 194088 ; free virtual = 543238 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property KEEP_HIERARCHY = SOFT for inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.cdc_wr_rst_busy_ic_3.xpm_cdc_single_inst3 . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.cdc_wr_rst_busy_ic_1.xpm_cdc_single_inst1 . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.cdc_wr_rst_busy_ic_2.xpm_cdc_single_inst2 . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 3465.559 ; gain = 45.812 ; free physical = 194098 ; free virtual = 543248 +--------------------------------------------------------------------------------- +INFO: [Synth 8-802] inferred FSM for state register 'gpregsm1.curr_fwft_state_reg' in module 'rd_fwft' +INFO: [Synth 8-6159] Found Keep on FSM register 'gpregsm1.curr_fwft_state_reg' in module 'rd_fwft', re-encoding will not be performed +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + invalid | 00 | 00 + stage1_valid | 10 | 10 + both_stages_valid | 11 | 11 + stage2_valid | 01 | 01 +--------------------------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 3465.559 ; gain = 45.812 ; free physical = 194087 ; free virtual = 543238 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 10 ++---XORs : + 2 Input 4 Bit XORs := 10 + 2 Input 1 Bit XORs := 110 ++---Registers : + 145 Bit Registers := 2 + 135 Bit Registers := 2 + 61 Bit Registers := 4 + 6 Bit Registers := 2 + 5 Bit Registers := 10 + 4 Bit Registers := 83 + 2 Bit Registers := 15 + 1 Bit Registers := 88 ++---Muxes : + 4 Input 2 Bit Muxes := 5 + 2 Input 2 Bit Muxes := 50 + 5 Input 2 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 5 + 2 Input 1 Bit Muxes := 15 + 4 Input 1 Bit Muxes := 10 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 240 (col length:80) +BRAMs: 270 (col length: RAMB18 80 RAMB36 40) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +WARNING: [Synth 8-7080] Parallel synthesis criteria is not met +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 3465.559 ; gain = 45.812 ; free physical = 194083 ; free virtual = 543235 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Distributed RAM: Preliminary Mapping Report (see note below) ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 61 | RAM32M x 11 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 145 | RAM32M x 25 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 6 | RAM32M x 1 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 61 | RAM32M x 11 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 135 | RAM32M x 23 | ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ + +Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 3465.559 ; gain = 45.812 ; free physical = 193992 ; free virtual = 543142 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 3465.559 ; gain = 45.812 ; free physical = 193967 ; free virtual = 543117 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Distributed RAM: Final Mapping Report ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 61 | RAM32M x 11 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 145 | RAM32M x 25 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 6 | RAM32M x 1 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 61 | RAM32M x 11 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 135 | RAM32M x 23 | ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 3465.559 ; gain = 45.812 ; free physical = 193950 ; free virtual = 543100 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 3465.559 ; gain = 45.812 ; free physical = 193959 ; free virtual = 543110 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 3465.559 ; gain = 45.812 ; free physical = 193959 ; free virtual = 543110 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 3465.559 ; gain = 45.812 ; free physical = 193959 ; free virtual = 543110 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 3465.559 ; gain = 45.812 ; free physical = 193959 ; free virtual = 543110 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 3465.559 ; gain = 45.812 ; free physical = 193962 ; free virtual = 543112 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 3465.559 ; gain = 45.812 ; free physical = 193962 ; free virtual = 543112 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+---------+------+ +| |Cell |Count | ++------+---------+------+ +|1 |LUT1 | 76| +|2 |LUT2 | 66| +|3 |LUT3 | 35| +|4 |LUT4 | 65| +|5 |LUT5 | 10| +|6 |LUT6 | 25| +|7 |RAM32M | 68| +|8 |RAM32X1D | 3| +|9 |FDCE | 130| +|10 |FDPE | 115| +|11 |FDRE | 1081| ++------+---------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 3465.559 ; gain = 45.812 ; free physical = 193962 ; free virtual = 543112 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 206 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3465.559 ; gain = 0.000 ; free physical = 193962 ; free virtual = 543113 +Synthesis Optimization Complete : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 3465.566 ; gain = 45.812 ; free physical = 193962 ; free virtual = 543113 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3465.566 ; gain = 0.000 ; free physical = 194257 ; free virtual = 543408 +INFO: [Netlist 29-17] Analyzing 71 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_ooc.xdc] for cell 'inst' +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_ooc.xdc] for cell 'inst' +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc] for cell 'inst' +INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:16] +WARNING: [Vivado_Tcl 4-2057] Waiver ID 'LUTAR-1' object list specifies likely unusable hierarchical instance 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi'. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:30] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:35] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:35] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:35] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:39] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:39] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:42] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:42] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:45] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:45] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:45] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:49] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:49] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:52] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:52] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:52] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:56] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:56] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:56] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:60] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:60] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:63] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:63] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:66] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:66] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:66] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:70] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:70] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc] for cell 'inst' +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3465.566 ; gain = 0.000 ; free physical = 194271 ; free virtual = 543421 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 71 instances were transformed. + RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 68 instances + RAM32X1D => RAM32X1D (RAMD32(x2)): 3 instances + +Synth Design complete | Checksum: ed94db3a +INFO: [Common 17-83] Releasing license: Synthesis +33 Infos, 130 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:25 . Memory (MB): peak = 3465.566 ; gain = 45.820 ; free physical = 194271 ; free virtual = 543421 +INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 3109.458; main = 2816.219; forked = 442.133 +INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 4507.152; main = 3465.562; forked = 1041.590 +INFO: [Coretcl 2-1174] Renamed 101 cell refs. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-480] Writing timing data to binary archive. +Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3473.562 ; gain = 0.000 ; free physical = 194272 ; free virtual = 543423 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc.dcp' has been generated. +INFO: [Vivado 12-3441] generate_netlist_ip - operation complete +synth_ip: Time (s): cpu = 00:02:09 ; elapsed = 00:02:04 . Memory (MB): peak = 3473.562 ; gain = 1253.406 ; free physical = 194261 ; free virtual = 543413 +INFO: [Common 17-2834] synth_ip peak Physical Memory [PSS] (MB): overall = 3109.458; main = 2816.242; forked = 442.133 +INFO: [Common 17-2834] synth_ip peak Virtual Memory [VSS] (MB): overall = 4507.152; main = 3473.566; forked = 1041.590 +# phase SYNTH_BOARD +BOARD_PHASE SYNTH_BOARD +# if {$flash} {read_verilog -sv $root/build/flash-boot/ToyLinuxChip.sv} else { +# read_verilog -sv $root/build/serial-bound/ToyLinuxChip.sv +# } +# read_verilog -sv $root/build/serial-bound/FpgaMemories.sv +# foreach f [glob $root/board/*.sv] {read_verilog -sv $f} +# set_property verilog_define {SYNTHESIS BUCKYBALL_DISABLE_DPI} [current_fileset] +# read_xdc $root/board/arty_a7.xdc +# read_xdc $root/board/flash_boot.xdc +# synth_design -top toy_a7_top -part xc7a100tcsg324-1 -flatten_hierarchy rebuilt -directive AreaOptimized_high -resource_sharing on -generic FLASH_BOOT=$flash +Command: synth_design -top toy_a7_top -part xc7a100tcsg324-1 -flatten_hierarchy rebuilt -directive AreaOptimized_high -resource_sharing on -generic FLASH_BOOT=0 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 3473.684 ; gain = 0.000 ; free physical = 193905 ; free virtual = 543055 +--------------------------------------------------------------------------------- +WARNING: [Synth 8-6901] identifier 'reset' is used before its declaration [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/toy_a7_top.sv:30] +INFO: [Synth 8-6157] synthesizing module 'toy_a7_top' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/toy_a7_top.sv:1] + Parameter FLASH_BOOT bound to: 0 - type: integer +INFO: [Synth 8-6157] synthesizing module 'IBUF' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:73643] +INFO: [Synth 8-6155] done synthesizing module 'IBUF' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:73643] +INFO: [Synth 8-6157] synthesizing module 'MMCME2_BASE' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82508] + Parameter CLKFBOUT_MULT_F bound to: 10.000000 - type: double + Parameter CLKIN1_PERIOD bound to: 10.000000 - type: double + Parameter CLKOUT0_DIVIDE_F bound to: 40.000000 - type: double + Parameter CLKOUT1_DIVIDE bound to: 6 - type: integer + Parameter CLKOUT2_DIVIDE bound to: 5 - type: integer + Parameter DIVCLK_DIVIDE bound to: 1 - type: integer +INFO: [Synth 8-6155] done synthesizing module 'MMCME2_BASE' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82508] +WARNING: [Synth 8-7071] port 'CLKFBOUTB' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT0B' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT1B' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT2B' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT3' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT3B' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT4' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT5' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT6' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7023] instance 'clock_mmcm' of module 'MMCME2_BASE' has 18 connections declared, but only 9 given [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/toy_a7_top.sv:13] +INFO: [Synth 8-6157] synthesizing module 'BUFG' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951] +INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951] +INFO: [Synth 8-6157] synthesizing module 'toy_a7_platform' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/toy_a7_platform.sv:2] + Parameter FLASH_BOOT bound to: 0 - type: integer +INFO: [Synth 8-6157] synthesizing module 'uart_rx' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_rx.sv:3] + Parameter DIVISOR bound to: 25 - type: integer +INFO: [Synth 8-6155] done synthesizing module 'uart_rx' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_rx.sv:3] +INFO: [Synth 8-6157] synthesizing module 'uart_tx' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_tx.sv:1] + Parameter DIVISOR bound to: 25 - type: integer +INFO: [Synth 8-6155] done synthesizing module 'uart_tx' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_tx.sv:1] +INFO: [Synth 8-6157] synthesizing module 'ddr_uart_loader' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:5] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:99] +INFO: [Synth 8-6155] done synthesizing module 'ddr_uart_loader' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:5] +INFO: [Synth 8-6157] synthesizing module 'ToyLinuxChip' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103817] +INFO: [Synth 8-6157] synthesizing module 'ToyLinuxSystem' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:102569] +INFO: [Synth 8-6157] synthesizing module 'IntSyncAsyncCrossingSink_n1x1' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:61] +INFO: [Synth 8-6157] synthesizing module 'SynchronizerShiftReg_w1_d3' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:48] +INFO: [Synth 8-6157] synthesizing module 'NonSyncResetSynchronizerPrimitiveShiftReg_d3' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31] +INFO: [Synth 8-6155] done synthesizing module 'NonSyncResetSynchronizerPrimitiveShiftReg_d3' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31] +INFO: [Synth 8-6155] done synthesizing module 'SynchronizerShiftReg_w1_d3' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:48] +INFO: [Synth 8-6155] done synthesizing module 'IntSyncAsyncCrossingSink_n1x1' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:61] +INFO: [Synth 8-6157] synthesizing module 'IntSyncCrossingSource_n1x1' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103] +INFO: [Synth 8-6157] synthesizing module 'AsyncResetRegVec_w1_i0' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:74] +INFO: [Synth 8-6155] done synthesizing module 'AsyncResetRegVec_w1_i0' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:74] +INFO: [Synth 8-6155] done synthesizing module 'IntSyncCrossingSource_n1x1' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103] +INFO: [Synth 8-6157] synthesizing module 'SystemBus' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:9400] +INFO: [Synth 8-6157] synthesizing module 'FixedClockBroadcast_3' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:118] +INFO: [Synth 8-6155] done synthesizing module 'FixedClockBroadcast_3' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:118] +INFO: [Synth 8-6157] synthesizing module 'TLXbar_sbus_i2_o3_a32d128s3k1z4c' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:2434] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:3011] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:139] +INFO: [Synth 8-6157] synthesizing module 'plusarg_reader' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104301] + Parameter FORMAT bound to: tilelink_timeout=%d - type: string + Parameter WIDTH bound to: 32 - type: integer + Parameter DEFAULT bound to: 32'b00000000000000000000000000000000 +INFO: [Synth 8-6155] done synthesizing module 'plusarg_reader' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104301] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:139] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:3033] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_1' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:987] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_1' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:987] +INFO: [Synth 8-6155] done synthesizing module 'TLXbar_sbus_i2_o3_a32d128s3k1z4c' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:2434] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_sbus_to_bus_named_cbus' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4386] +INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget16' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4218] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4310] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_2' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:3195] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_2' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:3195] +INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a28d128s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4151] +INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a28d128s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4151] +INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget16' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4218] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_sbus_to_bus_named_cbus' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4386] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8623] +INFO: [Synth 8-6157] synthesizing module 'AXI4Buffer' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4891] +INFO: [Synth 8-6157] synthesizing module 'Queue2_AXI4BundleAW' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4497] +INFO: [Synth 8-6157] synthesizing module 'ram_2x58' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4478] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x58' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4478] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_AXI4BundleAW' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4497] +INFO: [Synth 8-6157] synthesizing module 'Queue2_AXI4BundleW' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4600] +INFO: [Synth 8-6157] synthesizing module 'ram_2x73' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4581] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x73' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4581] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_AXI4BundleW' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4600] +INFO: [Synth 8-6157] synthesizing module 'Queue2_AXI4BundleB' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4676] +INFO: [Synth 8-6157] synthesizing module 'ram_2x4' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4657] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x4' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4657] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_AXI4BundleB' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4676] +INFO: [Synth 8-6157] synthesizing module 'Queue2_AXI4BundleAR' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4729] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_AXI4BundleAR' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4729] +INFO: [Synth 8-6157] synthesizing module 'Queue2_AXI4BundleR' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4832] +INFO: [Synth 8-6157] synthesizing module 'ram_2x69' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4813] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x69' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4813] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_AXI4BundleR' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4832] +INFO: [Synth 8-6155] done synthesizing module 'AXI4Buffer' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4891] +INFO: [Synth 8-6157] synthesizing module 'AXI4UserYanker' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5178] +INFO: [Synth 8-6157] synthesizing module 'Queue2_BundleMap' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5086] +INFO: [Synth 8-6157] synthesizing module 'ram_2x8' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5067] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x8' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5067] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_BundleMap' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5086] +INFO: [Synth 8-6157] synthesizing module 'Queue1_BundleMap' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5143] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_BundleMap' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5143] +INFO: [Synth 8-6155] done synthesizing module 'AXI4UserYanker' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5178] +INFO: [Synth 8-6157] synthesizing module 'AXI4Deinterleaver' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5631] +INFO: [Synth 8-6157] synthesizing module 'Queue8_AXI4BundleR' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5559] +INFO: [Synth 8-6157] synthesizing module 'ram_8x77' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5540] +INFO: [Synth 8-6155] done synthesizing module 'ram_8x77' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5540] +INFO: [Synth 8-6155] done synthesizing module 'Queue8_AXI4BundleR' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5559] +INFO: [Synth 8-6155] done synthesizing module 'AXI4Deinterleaver' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5631] +INFO: [Synth 8-6157] synthesizing module 'AXI4IdIndexer' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:6073] +INFO: [Synth 8-6155] done synthesizing module 'AXI4IdIndexer' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:6073] +INFO: [Synth 8-6157] synthesizing module 'TLToAXI4' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7148] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7423] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_3' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:6219] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_3' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:6219] +INFO: [Synth 8-6157] synthesizing module 'Queue1_AXI4BundleW' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7048] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_AXI4BundleW' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7048] +INFO: [Synth 8-6157] synthesizing module 'Queue1_AXI4BundleARW' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7082] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_AXI4BundleARW' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7082] +INFO: [Synth 8-6155] done synthesizing module 'TLToAXI4' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7148] +INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget16_2' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8463] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8551] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_4' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7529] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_4' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7529] +INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a31d128s3k1z3u' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8396] +INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a31d128s3k1z3u' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8396] +INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget16_2' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8463] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8623] +INFO: [Synth 8-6155] done synthesizing module 'SystemBus' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:9400] +INFO: [Synth 8-6157] synthesizing module 'PeripheryBus_cbus' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19330] +INFO: [Synth 8-6157] synthesizing module 'FixedClockBroadcast_4' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10050] +INFO: [Synth 8-6155] done synthesizing module 'FixedClockBroadcast_4' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10050] +INFO: [Synth 8-6157] synthesizing module 'TLXbar_cbus_out_i1_o4_a28d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10975] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:11207] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_5' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10073] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_5' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10073] +INFO: [Synth 8-6155] done synthesizing module 'TLXbar_cbus_out_i1_o4_a28d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10975] +INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a28d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12399] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12453] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_6' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:11288] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_6' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:11288] +INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleA_a28d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12221] +INFO: [Synth 8-6157] synthesizing module 'ram_2x114' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12202] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x114' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12202] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleA_a28d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12221] +INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleD_a28d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12320] +INFO: [Synth 8-6157] synthesizing module 'ram_2x79' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12301] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x79' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12301] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleD_a28d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12320] +INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a28d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12399] +INFO: [Synth 8-6157] synthesizing module 'TLAtomicAutomata_cbus' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:13449] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:13829] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_7' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12534] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_7' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12534] +INFO: [Synth 8-6155] done synthesizing module 'TLAtomicAutomata_cbus' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:13449] +INFO: [Synth 8-6157] synthesizing module 'ErrorDeviceWrapper' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16155] +INFO: [Synth 8-6157] synthesizing module 'TLError' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14846] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14907] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_8' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:13973] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_8' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:13973] +INFO: [Synth 8-6157] synthesizing module 'Queue1_TLBundleA_a14d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14799] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_TLBundleA_a14d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14799] +INFO: [Synth 8-6155] done synthesizing module 'TLError' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14846] +INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a14d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16028] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16078] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_9' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14953] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_9' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14953] +INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleA_a14d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15876] +INFO: [Synth 8-6157] synthesizing module 'ram_2x100' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15857] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x100' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15857] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleA_a14d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15876] +INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleD_a14d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15955] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleD_a14d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15955] +INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a14d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16028] +INFO: [Synth 8-6155] done synthesizing module 'ErrorDeviceWrapper' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16155] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_clint' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17261] +INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_CLINT' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17081] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17199] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_10' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16258] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_10' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16258] +INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a26d64s3k1z3u' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17017] +INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a26d64s3k1z3u' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17017] +INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_CLINT' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17081] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_clint' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17261] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_plic' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18350] +INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_PLIC' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18170] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18288] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_11' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17336] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_11' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17336] +INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a28d64s3k1z3u' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18106] +INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a28d64s3k1z3u' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18106] +INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_PLIC' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18170] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_plic' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18350] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_bootrom' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19263] +INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_bootrom' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19104] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19205] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_12' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18425] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19035] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_12' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18425] +INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a17d64s3k1z3u' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19040] +INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a17d64s3k1z3u' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19040] +INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_bootrom' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19104] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_bootrom' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19263] +INFO: [Synth 8-6155] done synthesizing module 'PeripheryBus_cbus' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19330] +INFO: [Synth 8-6157] synthesizing module 'MemoryBus' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:24031] +INFO: [Synth 8-6157] synthesizing module 'ProbePicker' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20610] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20649] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_13' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19882] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_13' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19882] +INFO: [Synth 8-6155] done synthesizing module 'ProbePicker' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20610] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:23555] +INFO: [Synth 8-6157] synthesizing module 'AXI4UserYanker_1' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20764] +INFO: [Synth 8-6157] synthesizing module 'Queue2_BundleMap_6' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20707] +INFO: [Synth 8-6157] synthesizing module 'ram_2x10' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20688] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x10' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20688] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_BundleMap_6' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20707] +INFO: [Synth 8-6155] done synthesizing module 'AXI4UserYanker_1' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20764] +INFO: [Synth 8-6157] synthesizing module 'AXI4IdIndexer_1' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:21713] +INFO: [Synth 8-6155] done synthesizing module 'AXI4IdIndexer_1' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:21713] +INFO: [Synth 8-6157] synthesizing module 'TLToAXI4_1' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22687] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:23450] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_14' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:21859] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_14' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:21859] +INFO: [Synth 8-6157] synthesizing module 'Queue1_AXI4BundleW_1' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22587] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_AXI4BundleW_1' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22587] +INFO: [Synth 8-6157] synthesizing module 'Queue1_AXI4BundleARW_1' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22621] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_AXI4BundleARW_1' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22621] +INFO: [Synth 8-6155] done synthesizing module 'TLToAXI4_1' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22687] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:23555] +INFO: [Synth 8-6155] done synthesizing module 'MemoryBus' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:24031] +INFO: [Synth 8-6157] synthesizing module 'CoherenceManagerWrapper' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27491] +INFO: [Synth 8-6157] synthesizing module 'TLBroadcast' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:26100] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:26482] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_15' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:24349] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_15' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:24349] +INFO: [Synth 8-6157] synthesizing module 'BroadcastFilter' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25732] +INFO: [Common 17-14] Message 'Synth 8-6157' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-6155] done synthesizing module 'BroadcastFilter' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25732] +INFO: [Synth 8-6155] done synthesizing module 'ram_4x144' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25756] +INFO: [Synth 8-6155] done synthesizing module 'Queue4_TLBroadcastData' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25775] +INFO: [Synth 8-6155] done synthesizing module 'TLBroadcastTracker' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25828] +INFO: [Synth 8-6155] done synthesizing module 'TLBroadcastTracker_1' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25964] +INFO: [Synth 8-6155] done synthesizing module 'TLBroadcast' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:26100] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27453] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_16' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:26686] +INFO: [Common 17-14] Message 'Synth 8-6155' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29794] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29834] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43249] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43271] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44089] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44825] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:45961] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47133] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68592] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68606] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68620] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:82885] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:82084] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86970] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85223] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85231] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:90541] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:90573] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:90605] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:90637] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:90669] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:90701] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:90733] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98928] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98950] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99569] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99575] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99581] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100308] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101303] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:102505] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101968] + Parameter FLASH_BOOT bound to: 0 - type: integer +WARNING: [Synth 8-6014] Unused sequential element rmPost_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52403] +WARNING: [Synth 8-6014] Unused sequential element rmPost_pipe_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52405] +WARNING: [Synth 8-6014] Unused sequential element rm_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52416] +WARNING: [Synth 8-6014] Unused sequential element rm_pipe_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52418] +WARNING: [Synth 8-6014] Unused sequential element rm_pipe_pipe_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52420] +WARNING: [Synth 8-6014] Unused sequential element tag_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52422] +WARNING: [Synth 8-6014] Unused sequential element tag_pipe_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52424] +WARNING: [Synth 8-6014] Unused sequential element tag_pipe_pipe_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52426] +WARNING: [Synth 8-6014] Unused sequential element ex_ctrl_rxs1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:61288] +WARNING: [Synth 8-6014] Unused sequential element ex_ctrl_rfs1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62163] +WARNING: [Synth 8-6014] Unused sequential element ex_ctrl_rfs2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62183] +WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rxs2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62375] +WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rxs1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62376] +WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rfs1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62378] +WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rfs2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62379] +WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rxs2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62390] +WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rxs1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62391] +WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rfs1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62393] +WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rfs2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62394] +WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd0val_REG_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62497] +WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd0val_REG_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62498] +WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd1val_REG_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62499] +WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd1val_REG_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62500] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:63220] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:63221] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:63222] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:63223] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:63224] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_5_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:63225] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_6_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:63226] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_7_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:63227] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_8_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:63228] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_9_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:63229] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_10_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:63230] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_11_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:63231] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_12_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:63232] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_13_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:63233] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_14_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:63234] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_15_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:63235] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_2_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76912] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_2_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76914] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76916] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76919] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76922] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76926] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76930] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76935] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76940] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76946] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76952] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76959] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_2_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76968] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76970] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76973] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76977] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76982] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76988] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_84_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77024] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_85_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77026] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_87_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77029] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_90_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77033] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_94_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77038] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_99_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77044] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_105_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77052] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_106_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77054] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_108_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77057] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_111_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77061] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_115_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77066] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_120_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77072] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_dataflow_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76917] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_propagate_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76920] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_dataflow_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76923] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_dataflow_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76924] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_propagate_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76927] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_propagate_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76928] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_dataflow_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76931] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_dataflow_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76932] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_dataflow_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76933] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_propagate_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76936] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_propagate_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76937] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_propagate_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76938] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_dataflow_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76941] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_dataflow_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76942] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_dataflow_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76943] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_dataflow_r_4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76944] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_propagate_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76947] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_propagate_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76948] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_propagate_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76949] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_propagate_r_4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76950] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76953] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76954] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76955] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76956] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_5_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76957] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76960] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76961] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76962] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76963] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_5_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76964] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_shift_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76971] +INFO: [Common 17-14] Message 'Synth 8-6014' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [Synth 8-3936] Found unconnected internal register 's2_req_tag_reg' and it is trimmed from '8' to '6' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93740] +WARNING: [Synth 8-3917] design toy_a7_top has port flash_wp_n driven by constant 1 +WARNING: [Synth 8-3917] design toy_a7_top has port flash_hold_n driven by constant 1 +WARNING: [Synth 8-7129] Port wdata[63] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[62] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[61] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[60] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[59] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[58] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[57] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[56] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[55] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[54] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[53] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[52] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[51] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[50] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[49] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[48] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[47] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[46] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[45] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[44] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[43] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[42] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[41] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[40] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[39] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[38] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[37] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[36] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[35] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[34] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[33] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[32] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wstrb[7] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wstrb[6] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wstrb[5] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wstrb[4] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port flash_miso in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port flash_recovery in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port load_addr[3] in module loader_axi is either unconnected or has no load +WARNING: [Synth 8-7129] Port load_addr[2] in module loader_axi is either unconnected or has no load +WARNING: [Synth 8-7129] Port load_addr[1] in module loader_axi is either unconnected or has no load +WARNING: [Synth 8-7129] Port load_addr[0] in module loader_axi is either unconnected or has no load +WARNING: [Synth 8-7129] Port clock in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port reset in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_ready in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_valid in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_opcode[2] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_opcode[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_opcode[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_param[2] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_param[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_param[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_size[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_size[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[6] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[5] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[4] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[3] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[2] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[16] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[15] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[14] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[13] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[12] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[11] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[10] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[9] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[8] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[7] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[6] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[5] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[4] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[3] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[2] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[7] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[6] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[5] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[4] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[3] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[2] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_corrupt in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_ready in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_valid in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_size[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_size[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_source[6] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_source[5] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_source[4] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_source[3] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_source[2] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_source[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_source[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port clock in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port reset in module TLMonitor_28 is either unconnected or has no load +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 3814.555 ; gain = 340.871 ; free physical = 193375 ; free virtual = 542534 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 3829.398 ; gain = 355.715 ; free physical = 193432 ; free virtual = 542590 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 3829.398 ; gain = 355.715 ; free physical = 193432 ; free virtual = 542590 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 3829.398 ; gain = 0.000 ; free physical = 193267 ; free virtual = 542422 +INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc] for cell 'ddr_controller' +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc] for cell 'ddr_controller' +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc/toy_axi_cdc_in_context.xdc] for cell 'memory_cdc' +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc/toy_axi_cdc_in_context.xdc] for cell 'memory_cdc' +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/arty_a7.xdc] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/arty_a7.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/arty_a7.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/toy_a7_top_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/toy_a7_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/flash_boot.xdc] +CRITICAL WARNING: [Designutils 20-1307] Command 'if' is not supported in the xdc constraint file. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/flash_boot.xdc:11] +CRITICAL WARNING: [Designutils 20-1307] Command 'if' is not supported in the xdc constraint file. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/flash_boot.xdc:15] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/flash_boot.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/flash_boot.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/toy_a7_top_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/toy_a7_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +INFO: [Timing 38-2] Deriving generated clocks +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4001.055 ; gain = 0.000 ; free physical = 193330 ; free virtual = 542485 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 1 instances were transformed. + MMCME2_BASE => MMCME2_ADV: 1 instance + +INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'uart_rx' +WARNING: [Synth 8-3936] Found unconnected internal register 'cam_a_0_bits_opcode_reg' and it is trimmed from '3' to '1' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:13813] +WARNING: [Synth 8-3936] Found unconnected internal register 'ram_reg' and it is trimmed from '100' to '13' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14825] +WARNING: [Synth 8-3936] Found unconnected internal register 'req_addr_reg' and it is trimmed from '40' to '32' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30468] +WARNING: [Synth 8-3936] Found unconnected internal register 'r_raddr_reg' and it is trimmed from '11' to '4' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36089] +WARNING: [Synth 8-3936] Found unconnected internal register 'in_fmt_reg' and it is trimmed from '2' to '1' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50199] +WARNING: [Synth 8-3936] Found unconnected internal register 'mem_reg_inst_reg' and it is trimmed from '32' to '12' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:54509] +WARNING: [Synth 8-3936] Found unconnected internal register 'ex_reg_inst_reg' and it is trimmed from '32' to '28' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:54256] +WARNING: [Synth 8-3936] Found unconnected internal register 'reg_mcounteren_reg' and it is trimmed from '32' to '3' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:55509] +WARNING: [Synth 8-3936] Found unconnected internal register 'reg_scounteren_reg' and it is trimmed from '32' to '3' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:55511] +WARNING: [Synth 8-3936] Found unconnected internal register 'reg_mideleg_reg' and it is trimmed from '64' to '14' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:55493] +WARNING: [Synth 8-3936] Found unconnected internal register 'reg_medeleg_reg' and it is trimmed from '64' to '16' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:55497] +WARNING: [Synth 8-3936] Found unconnected internal register 'wb_reg_raw_inst_reg' and it is trimmed from '32' to '16' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62407] +WARNING: [Synth 8-3936] Found unconnected internal register 'mem_reg_raw_inst_reg' and it is trimmed from '32' to '16' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62407] +WARNING: [Synth 8-3936] Found unconnected internal register 'ex_reg_raw_inst_reg' and it is trimmed from '32' to '16' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62438] +WARNING: [Synth 8-3936] Found unconnected internal register 'iter_reg_reg' and it is trimmed from '34' to '29' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84823] +WARNING: [Synth 8-3936] Found unconnected internal register 'iter_cmd_reg' and it is trimmed from '34' to '29' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84821] +WARNING: [Synth 8-3936] Found unconnected internal register 'reqReg_vaddr_reg' and it is trimmed from '64' to '39' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86206] +INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'MemConfiger' +INFO: [Synth 8-802] inferred FSM for state register 'ws_reg' in module 'axi_fullwidth' +INFO: [Synth 8-802] inferred FSM for state register 'rs_reg' in module 'axi_fullwidth' +INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'loader_axi' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + IDLE | 000 | 000 + START | 001 | 001 + DATA | 010 | 010 + STOP | 011 | 011 + WAIT_HIGH | 100 | 100 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'uart_rx' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + iSTATE3 | 00000001 | 000 + iSTATE2 | 00000010 | 001 + iSTATE6 | 00000100 | 010 + iSTATE4 | 00010000 | 011 + iSTATE1 | 00100000 | 100 + iSTATE5 | 00001000 | 101 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'MemConfiger' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + P_DA814840 | 00 | 00 + P_DA814540 | 01 | 01 + P_DA814930 | 10 | 10 + P_DA7E9800 | 11 | 11 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'ws_reg' using encoding 'sequential' in module 'axi_fullwidth' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + R_IDLE | 00 | 00 + R_SEND | 01 | 01 + R_RESP | 10 | 10 + R_RETURN | 11 | 11 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'rs_reg' using encoding 'sequential' in module 'axi_fullwidth' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + IDLE | 000001 | 000 + SEND_W | 100000 | 001 + WAIT_B | 010000 | 010 + SEND_R | 001000 | 011 + WAIT_R | 000100 | 100 + RELEASE | 000010 | 101 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'loader_axi' +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:47 ; elapsed = 00:00:44 . Memory (MB): peak = 4004.973 ; gain = 531.289 ; free physical = 188316 ; free virtual = 537474 +--------------------------------------------------------------------------------- +INFO: [Synth 8-223] decloning instance 'platform/chip/system/sbus/system_bus_xbar/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/sbus/system_bus_xbar/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/sbus/system_bus_xbar/monitor_1/plusarg_reader' (plusarg_reader) to 'platform/chip/system/sbus/system_bus_xbar/monitor_1/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/sbus/coupler_to_bus_named_cbus/widget/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/sbus/coupler_to_bus_named_cbus/widget/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/sbus/coupler_to_port_named_mmio_port_axi4/tl2axi4/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/sbus/coupler_to_port_named_mmio_port_axi4/tl2axi4/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/sbus/coupler_to_port_named_mmio_port_axi4/widget/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/sbus/coupler_to_port_named_mmio_port_axi4/widget/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/out_xbar/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/out_xbar/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/buffer/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/buffer/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/atomics/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/atomics/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/wrapped_error_device/error/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/wrapped_error_device/error/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/wrapped_error_device/buffer/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/wrapped_error_device/buffer/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/coupler_to_clint/fragmenter/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/coupler_to_clint/fragmenter/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/coupler_to_plic/fragmenter/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/coupler_to_plic/fragmenter/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/coupler_to_bootrom/fragmenter/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/coupler_to_bootrom/fragmenter/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/mbus/picker/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/mbus/picker/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/mbus/coupler_to_memory_controller_port_named_axi4/tl2axi4/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/mbus/coupler_to_memory_controller_port_named_axi4/tl2axi4/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/coh_wrapper/broadcast_1/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/coh_wrapper/broadcast_1/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/coh_wrapper/binder/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/coh_wrapper/binder/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/tlMasterXbar/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/tlMasterXbar/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/tlMasterXbar/monitor_1/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/tlMasterXbar/monitor_1/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/dtlb/mpu_ppn_barrier' (OptimizationBarrier_TLBEntryData) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/dtlb/entries_barrier_12' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/tlb/mpu_ppn_barrier' (OptimizationBarrier_TLBEntryData) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/tlb/entries_barrier_12' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/xbar/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/xbar/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/xbar/monitor_1/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/xbar/monitor_1/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer_1/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer_1/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/widget_3/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/widget_3/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer_2/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer_2/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/buffer/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/buffer/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/buffer/monitor_1/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/buffer/monitor_1/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/intsource' (IntSyncCrossingSource_n1x1) to 'platform/chip/system/tile_prci_domain/intsource_2' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/clint_domain/clint/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/clint_domain/clint/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/plic_domain/plic/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/plic_domain/plic/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/bootrom_domain/bootrom/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/bootrom_domain/bootrom/monitor/plusarg_reader_1' +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 109 Bit Adders := 1 + 2 Input 107 Bit Adders := 1 + 2 Input 73 Bit Adders := 1 + 3 Input 65 Bit Adders := 1 + 2 Input 64 Bit Adders := 21 + 3 Input 64 Bit Adders := 2 + 3 Input 58 Bit Adders := 1 + 2 Input 58 Bit Adders := 2 + 2 Input 55 Bit Adders := 4 + 2 Input 48 Bit Adders := 1 + 2 Input 40 Bit Adders := 3 + 3 Input 39 Bit Adders := 5 + 2 Input 39 Bit Adders := 3 + 2 Input 37 Bit Adders := 1 + 2 Input 34 Bit Adders := 1 + 2 Input 33 Bit Adders := 3 + 2 Input 32 Bit Adders := 18 + 3 Input 32 Bit Adders := 1 + 2 Input 30 Bit Adders := 8 + 3 Input 29 Bit Adders := 1 + 2 Input 28 Bit Adders := 1 + 2 Input 26 Bit Adders := 4 + 2 Input 20 Bit Adders := 64 + 2 Input 19 Bit Adders := 2 + 2 Input 17 Bit Adders := 2 + 3 Input 16 Bit Adders := 1 + 2 Input 16 Bit Adders := 12 + 2 Input 15 Bit Adders := 4 + 2 Input 14 Bit Adders := 7 + 4 Input 14 Bit Adders := 1 + 2 Input 13 Bit Adders := 6 + 3 Input 13 Bit Adders := 2 + 2 Input 12 Bit Adders := 12 + 3 Input 12 Bit Adders := 1 + 2 Input 11 Bit Adders := 4 + 2 Input 10 Bit Adders := 7 + 4 Input 10 Bit Adders := 1 + 3 Input 10 Bit Adders := 1 + 2 Input 9 Bit Adders := 14 + 3 Input 9 Bit Adders := 4 + 2 Input 8 Bit Adders := 16 + 3 Input 8 Bit Adders := 8 + 2 Input 7 Bit Adders := 6 + 3 Input 7 Bit Adders := 1 + 2 Input 6 Bit Adders := 13 + 3 Input 6 Bit Adders := 2 + 2 Input 5 Bit Adders := 9 + 2 Input 4 Bit Adders := 60 + 5 Input 4 Bit Adders := 1 + 4 Input 4 Bit Adders := 4 + 2 Input 3 Bit Adders := 65 + 3 Input 3 Bit Adders := 7 + 2 Input 2 Bit Adders := 70 + 3 Input 2 Bit Adders := 5 + 4 Input 2 Bit Adders := 1 + 3 Input 1 Bit Adders := 3 + 2 Input 1 Bit Adders := 126 + 4 Input 1 Bit Adders := 39 ++---XORs : + 2 Input 65 Bit XORs := 1 + 2 Input 64 Bit XORs := 5 + 2 Input 32 Bit XORs := 8 + 2 Input 29 Bit XORs := 8 + 2 Input 27 Bit XORs := 6 + 2 Input 25 Bit XORs := 16 + 2 Input 20 Bit XORs := 8 + 2 Input 18 Bit XORs := 8 + 2 Input 16 Bit XORs := 18 + 2 Input 11 Bit XORs := 8 + 2 Input 10 Bit XORs := 3 + 2 Input 4 Bit XORs := 3 + 2 Input 3 Bit XORs := 11 + 2 Input 2 Bit XORs := 8 + 2 Input 1 Bit XORs := 14 + 3 Input 1 Bit XORs := 2 + 4 Input 1 Bit XORs := 2 ++---Registers : + 1269 Bit Registers := 1 + 145 Bit Registers := 1 + 130 Bit Registers := 1 + 128 Bit Registers := 9 + 107 Bit Registers := 1 + 106 Bit Registers := 3 + 105 Bit Registers := 1 + 73 Bit Registers := 1 + 72 Bit Registers := 1 + 67 Bit Registers := 1 + 65 Bit Registers := 14 + 64 Bit Registers := 184 + 62 Bit Registers := 2 + 58 Bit Registers := 2 + 56 Bit Registers := 1 + 55 Bit Registers := 5 + 53 Bit Registers := 3 + 44 Bit Registers := 5 + 42 Bit Registers := 74 + 40 Bit Registers := 21 + 39 Bit Registers := 19 + 34 Bit Registers := 2 + 32 Bit Registers := 115 + 31 Bit Registers := 2 + 30 Bit Registers := 8 + 29 Bit Registers := 2 + 28 Bit Registers := 5 + 27 Bit Registers := 34 + 26 Bit Registers := 4 + 24 Bit Registers := 1 + 23 Bit Registers := 4 + 21 Bit Registers := 8 + 20 Bit Registers := 293 + 19 Bit Registers := 2 + 17 Bit Registers := 2 + 16 Bit Registers := 54 + 14 Bit Registers := 1 + 13 Bit Registers := 8 + 12 Bit Registers := 1 + 11 Bit Registers := 1 + 10 Bit Registers := 140 + 9 Bit Registers := 12 + 8 Bit Registers := 434 + 7 Bit Registers := 27 + 6 Bit Registers := 11 + 5 Bit Registers := 113 + 4 Bit Registers := 193 + 3 Bit Registers := 234 + 2 Bit Registers := 127 + 1 Bit Registers := 1664 ++---Multipliers : + 53x53 Multipliers := 1 + 73x73 Multipliers := 1 + 16x32 Multipliers := 6 + 16x39 Multipliers := 2 + 16x37 Multipliers := 1 ++---RAMs : + 64K Bit (1024 X 64 bit) RAMs := 8 + 8K Bit (256 X 32 bit) RAMs := 8 + 8K Bit (128 X 64 bit) RAMs := 8 + 2K Bit (16 X 128 bit) RAMs := 1 ++---Muxes : + 2 Input 130 Bit Muxes := 4 + 2 Input 128 Bit Muxes := 34 + 4 Input 128 Bit Muxes := 1 + 2 Input 109 Bit Muxes := 1 + 2 Input 108 Bit Muxes := 1 + 2 Input 65 Bit Muxes := 33 + 4 Input 65 Bit Muxes := 4 + 2 Input 64 Bit Muxes := 303 + 3 Input 64 Bit Muxes := 2 + 4 Input 64 Bit Muxes := 26 + 8 Input 64 Bit Muxes := 3 + 2 Input 62 Bit Muxes := 1 + 2 Input 61 Bit Muxes := 2 + 2 Input 58 Bit Muxes := 2 + 2 Input 56 Bit Muxes := 9 + 2 Input 55 Bit Muxes := 11 + 2 Input 54 Bit Muxes := 3 + 2 Input 53 Bit Muxes := 2 + 2 Input 52 Bit Muxes := 10 + 2 Input 51 Bit Muxes := 2 + 2 Input 48 Bit Muxes := 2 + 4 Input 44 Bit Muxes := 1 + 2 Input 44 Bit Muxes := 6 + 4 Input 42 Bit Muxes := 16 + 2 Input 40 Bit Muxes := 25 + 2 Input 39 Bit Muxes := 19 + 5 Input 39 Bit Muxes := 1 + 3 Input 39 Bit Muxes := 1 + 2 Input 38 Bit Muxes := 1 + 2 Input 34 Bit Muxes := 57 + 2 Input 33 Bit Muxes := 1 + 2 Input 32 Bit Muxes := 129 + 3 Input 32 Bit Muxes := 2 + 4 Input 32 Bit Muxes := 4 + 13 Input 32 Bit Muxes := 2 + 10 Input 32 Bit Muxes := 1 + 8 Input 32 Bit Muxes := 1 + 2 Input 31 Bit Muxes := 4 + 2 Input 30 Bit Muxes := 8 + 2 Input 29 Bit Muxes := 5 + 2 Input 28 Bit Muxes := 13 + 2 Input 27 Bit Muxes := 5 + 2 Input 26 Bit Muxes := 15 + 2 Input 25 Bit Muxes := 6 + 2 Input 24 Bit Muxes := 2 + 2 Input 23 Bit Muxes := 11 + 2 Input 22 Bit Muxes := 388 + 2 Input 21 Bit Muxes := 6 + 2 Input 20 Bit Muxes := 621 + 2 Input 19 Bit Muxes := 11 + 4 Input 18 Bit Muxes := 1 + 2 Input 17 Bit Muxes := 1 + 4 Input 16 Bit Muxes := 1 + 2 Input 16 Bit Muxes := 134 + 13 Input 16 Bit Muxes := 3 + 10 Input 16 Bit Muxes := 1 + 8 Input 16 Bit Muxes := 1 + 2 Input 14 Bit Muxes := 12 + 2 Input 13 Bit Muxes := 23 + 2 Input 12 Bit Muxes := 21 + 5 Input 12 Bit Muxes := 1 + 2 Input 11 Bit Muxes := 8 + 2 Input 10 Bit Muxes := 53 + 2 Input 9 Bit Muxes := 41 + 4 Input 9 Bit Muxes := 1 + 13 Input 9 Bit Muxes := 2 + 2 Input 8 Bit Muxes := 370 + 6 Input 8 Bit Muxes := 1 + 3 Input 8 Bit Muxes := 1 + 5 Input 8 Bit Muxes := 1 + 13 Input 8 Bit Muxes := 3 + 4 Input 8 Bit Muxes := 2 + 2 Input 7 Bit Muxes := 28 + 4 Input 7 Bit Muxes := 1 + 7 Input 7 Bit Muxes := 2 + 6 Input 7 Bit Muxes := 1 + 2 Input 6 Bit Muxes := 32 + 4 Input 6 Bit Muxes := 1 + 5 Input 6 Bit Muxes := 1 + 6 Input 6 Bit Muxes := 1 + 2 Input 5 Bit Muxes := 103 + 4 Input 5 Bit Muxes := 1 + 5 Input 5 Bit Muxes := 1 + 3 Input 5 Bit Muxes := 1 + 4 Input 4 Bit Muxes := 10 + 2 Input 4 Bit Muxes := 198 + 3 Input 4 Bit Muxes := 5 + 5 Input 4 Bit Muxes := 1 + 8 Input 4 Bit Muxes := 4 + 6 Input 4 Bit Muxes := 1 + 13 Input 4 Bit Muxes := 1 + 2 Input 3 Bit Muxes := 225 + 8 Input 3 Bit Muxes := 6 + 3 Input 3 Bit Muxes := 7 + 4 Input 3 Bit Muxes := 11 + 5 Input 3 Bit Muxes := 5 + 6 Input 3 Bit Muxes := 2 + 2 Input 2 Bit Muxes := 257 + 4 Input 2 Bit Muxes := 16 + 3 Input 2 Bit Muxes := 9 + 5 Input 2 Bit Muxes := 2 + 16 Input 2 Bit Muxes := 5 + 2 Input 1 Bit Muxes := 1279 + 8 Input 1 Bit Muxes := 6 + 6 Input 1 Bit Muxes := 12 + 4 Input 1 Bit Muxes := 33 + 3 Input 1 Bit Muxes := 2 + 5 Input 1 Bit Muxes := 6 + 13 Input 1 Bit Muxes := 10 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 240 (col length:80) +BRAMs: 270 (col length: RAMB18 80 RAMB36 40) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +WARNING: [Synth 8-3936] Found unconnected internal register 'subRob/sram/sram_ext/lanes[0].R0_data_reg' and it is trimmed from '1269' to '1262' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:103] +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +WARNING: [Synth 8-3917] design toy_a7_top has port flash_wp_n driven by constant 1 +WARNING: [Synth 8-3917] design toy_a7_top has port flash_hold_n driven by constant 1 +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 10 [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52365] +DSP Report: Generating DSP product_pipe_b0, operation Mode is: A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b0, operation Mode is: PCIN+A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b_reg, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +DSP Report: Generating DSP product_pipe_b0, operation Mode is: A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b0, operation Mode is: PCIN+A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b_reg, operation Mode is: (PCIN+A2*B2)'. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +DSP Report: Generating DSP product_pipe_b0, operation Mode is: A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b0, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b_reg, operation Mode is: (PCIN+A2*B2)'. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +INFO: [Synth 8-4471] merging register 'cfg_max_j_reg[15:0]' into 'cfg_max_j_reg[15:0]' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79428] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79511] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79576] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79605] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79627] +DSP Report: Generating DSP _GEN_363, operation Mode is: A2*B2. +DSP Report: register cfg_max_j_reg is absorbed into DSP _GEN_363. +DSP Report: register cfg_max_i_reg is absorbed into DSP _GEN_363. +DSP Report: operator _GEN_363 is absorbed into DSP _GEN_363. +DSP Report: Generating DSP _GEN_362, operation Mode is: A*B2. +DSP Report: register _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: operator _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: operator _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: Generating DSP _GEN_362, operation Mode is: (PCIN>>17)+A2*B. +DSP Report: register _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: operator _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: operator _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: Generating DSP io_cmd_bits_slots_0_bits_dram_addr5, operation Mode is: A2*B2. +DSP Report: register io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: register io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: operator io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: operator io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: Generating DSP io_cmd_bits_slots_0_bits_dram_addr5, operation Mode is: (PCIN>>17)+A2*B. +DSP Report: register io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: operator io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: operator io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: Generating DSP io_cmd_bits_slots_1_bits_dram_addr4, operation Mode is: A2*B. +DSP Report: register io_cmd_bits_slots_1_bits_dram_addr4 is absorbed into DSP io_cmd_bits_slots_1_bits_dram_addr4. +DSP Report: operator io_cmd_bits_slots_1_bits_dram_addr4 is absorbed into DSP io_cmd_bits_slots_1_bits_dram_addr4. +DSP Report: operator io_cmd_bits_slots_1_bits_dram_addr4 is absorbed into DSP io_cmd_bits_slots_1_bits_dram_addr4. +DSP Report: Generating DSP io_cmd_bits_slots_1_bits_dram_addr4, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_cmd_bits_slots_1_bits_dram_addr4 is absorbed into DSP io_cmd_bits_slots_1_bits_dram_addr4. +DSP Report: operator io_cmd_bits_slots_1_bits_dram_addr4 is absorbed into DSP io_cmd_bits_slots_1_bits_dram_addr4. +DSP Report: Generating DSP io_cmd_bits_slots_2_bits_dram_addr2, operation Mode is: A2*B. +DSP Report: register io_cmd_bits_slots_2_bits_dram_addr2 is absorbed into DSP io_cmd_bits_slots_2_bits_dram_addr2. +DSP Report: operator io_cmd_bits_slots_2_bits_dram_addr2 is absorbed into DSP io_cmd_bits_slots_2_bits_dram_addr2. +DSP Report: operator io_cmd_bits_slots_2_bits_dram_addr2 is absorbed into DSP io_cmd_bits_slots_2_bits_dram_addr2. +DSP Report: Generating DSP io_cmd_bits_slots_2_bits_dram_addr2, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_cmd_bits_slots_2_bits_dram_addr2 is absorbed into DSP io_cmd_bits_slots_2_bits_dram_addr2. +DSP Report: operator io_cmd_bits_slots_2_bits_dram_addr2 is absorbed into DSP io_cmd_bits_slots_2_bits_dram_addr2. +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79673] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79673] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79677] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79681] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79681] +DSP Report: Generating DSP _irow_T_7, operation Mode is: C+A*B. +DSP Report: operator _irow_T_7 is absorbed into DSP _irow_T_7. +DSP Report: operator _irow_T_71 is absorbed into DSP _irow_T_7. +DSP Report: Generating DSP io_inputAddr4, operation Mode is: A*B. +DSP Report: operator io_inputAddr4 is absorbed into DSP io_inputAddr4. +DSP Report: Generating DSP io_inputAddr5, operation Mode is: A*B. +DSP Report: operator io_inputAddr5 is absorbed into DSP io_inputAddr5. +DSP Report: Generating DSP io_inputAddr4, operation Mode is: A*B. +DSP Report: operator io_inputAddr4 is absorbed into DSP io_inputAddr4. +DSP Report: operator io_inputAddr4 is absorbed into DSP io_inputAddr4. +DSP Report: Generating DSP io_inputAddr4, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_inputAddr4 is absorbed into DSP io_inputAddr4. +DSP Report: operator io_inputAddr4 is absorbed into DSP io_inputAddr4. +DSP Report: Generating DSP _icol_T_7, operation Mode is: C+A*B. +DSP Report: operator _icol_T_7 is absorbed into DSP _icol_T_7. +DSP Report: operator _icol_T_71 is absorbed into DSP _icol_T_7. +DSP Report: Generating DSP io_inputAddr2, operation Mode is: PCIN+A:B+C. +DSP Report: operator io_inputAddr2 is absorbed into DSP io_inputAddr2. +DSP Report: Generating DSP io_inputAddr1, operation Mode is: A*B. +DSP Report: operator io_inputAddr1 is absorbed into DSP io_inputAddr1. +DSP Report: operator io_inputAddr1 is absorbed into DSP io_inputAddr1. +DSP Report: Generating DSP io_inputAddr1, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_inputAddr1 is absorbed into DSP io_inputAddr1. +DSP Report: operator io_inputAddr1 is absorbed into DSP io_inputAddr1. +DSP Report: Generating DSP io_weightAddr4, operation Mode is: C+A*B. +DSP Report: operator io_weightAddr4 is absorbed into DSP io_weightAddr4. +DSP Report: operator io_weightAddr5 is absorbed into DSP io_weightAddr4. +DSP Report: Generating DSP io_weightAddr2, operation Mode is: C+A*B. +DSP Report: operator io_weightAddr2 is absorbed into DSP io_weightAddr2. +DSP Report: operator io_weightAddr3 is absorbed into DSP io_weightAddr2. +DSP Report: Generating DSP io_weightAddr1, operation Mode is: A*B. +DSP Report: operator io_weightAddr1 is absorbed into DSP io_weightAddr1. +DSP Report: operator io_weightAddr1 is absorbed into DSP io_weightAddr1. +DSP Report: Generating DSP io_weightAddr1, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_weightAddr1 is absorbed into DSP io_weightAddr1. +DSP Report: operator io_weightAddr1 is absorbed into DSP io_weightAddr1. +DSP Report: Generating DSP io_outputAddr4, operation Mode is: A*B. +DSP Report: operator io_outputAddr4 is absorbed into DSP io_outputAddr4. +DSP Report: Generating DSP io_outputAddr5, operation Mode is: A*B. +DSP Report: operator io_outputAddr5 is absorbed into DSP io_outputAddr5. +DSP Report: Generating DSP io_outputAddr4, operation Mode is: A*B. +DSP Report: operator io_outputAddr4 is absorbed into DSP io_outputAddr4. +DSP Report: operator io_outputAddr4 is absorbed into DSP io_outputAddr4. +DSP Report: Generating DSP io_outputAddr4, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_outputAddr4 is absorbed into DSP io_outputAddr4. +DSP Report: operator io_outputAddr4 is absorbed into DSP io_outputAddr4. +DSP Report: Generating DSP io_outputAddr2, operation Mode is: PCIN+(A:0x0):B+C. +DSP Report: operator io_outputAddr2 is absorbed into DSP io_outputAddr2. +DSP Report: Generating DSP io_outputAddr1, operation Mode is: A*B. +DSP Report: operator io_outputAddr1 is absorbed into DSP io_outputAddr1. +DSP Report: operator io_outputAddr1 is absorbed into DSP io_outputAddr1. +DSP Report: Generating DSP io_outputAddr1, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_outputAddr1 is absorbed into DSP io_outputAddr1. +DSP Report: operator io_outputAddr1 is absorbed into DSP io_outputAddr1. +WARNING: [Synth 8-3936] Found unconnected internal register 'cfg_input_stride_reg' and it is trimmed from '32' to '22' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79776] +WARNING: [Synth 8-3936] Found unconnected internal register 'cfg_output_stride_reg' and it is trimmed from '32' to '24' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79780] +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_domain_id[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_domain_id[2] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_funct[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[63] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[62] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[61] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[60] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[59] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[58] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_domain_id[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_domain_id[2] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_funct[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[63] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[62] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[61] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[60] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[59] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[58] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_domain_id[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_domain_id[2] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_funct[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[63] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[62] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[61] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[60] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[59] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[58] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[4] driven by constant 0 +INFO: [Synth 8-4471] merging register 'reqReg_pixel_bytes_reg[9:0]' into 'reqReg_pixel_bytes_reg[9:0]' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86013] +DSP Report: Generating DSP rowSkip_reg, operation Mode is: (A*B)'. +DSP Report: register rowSkip_reg is absorbed into DSP rowSkip_reg. +DSP Report: operator rowSkip0 is absorbed into DSP rowSkip_reg. +DSP Report: Generating DSP readVaddr1, operation Mode is: A*B2. +DSP Report: register reqReg_pixel_bytes_reg is absorbed into DSP readVaddr1. +DSP Report: operator readVaddr1 is absorbed into DSP readVaddr1. +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 17 [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:58083] +DSP Report: Generating DSP remainder1, operation Mode is: A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [Synth 8-6430] The Block RAM "dcache/mshrs/sdq_ext/Memory_reg" may get memory collision error if read and write address collide. Use attribute (* rw_addr_collision= "yes" *) to avoid collision +WARNING: [Synth 8-3917] design BBTile__GCB2 has port io_requestor_1_resp_bits_tag[7] driven by constant 0 +WARNING: [Synth 8-3917] design BBTile__GCB2 has port io_requestor_1_resp_bits_tag[6] driven by constant 0 +WARNING: [Synth 8-3917] design BBTile__GCB2 has port io_requestor_2_resp_bits_tag[7] driven by constant 0 +WARNING: [Synth 8-3917] design BBTile__GCB2 has port io_requestor_2_resp_bits_tag[6] driven by constant 0 +WARNING: [Synth 8-3917] design BBTile__GCB2 has port auto_buffer_out_1_c_bits_source[1] driven by constant 0 +RAM Pipeline Warning: Read Address Register Found For RAM sdq_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance. +RAM Pipeline Warning: Read Address Register Found For RAM sdq_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance. +RAM Pipeline Warning: Read Address Register Found For RAM sdq_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance. +WARNING: [Synth 8-6430] The Block RAM "dcache/mshrs/sdq_ext/Memory_reg" may get memory collision error if read and write address collide. Use attribute (* rw_addr_collision= "yes" *) to avoid collision +RAM Pipeline Warning: Read Address Register Found For RAM sdq_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance. +--------------------------------------------------------------------------------- +Start Pre Area Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Iterative Area Optimization +--------------------------------------------------------------------------------- +INFO: [Synth 8-3333] propagating constant 0 across sequential element (fpmu/\io_out_pipe_b_exc_reg[3] ) +INFO: [Synth 8-3886] merging instance 'wb_toint_exc_reg[1]' (FDE) to 'wb_toint_exc_reg[3]' +INFO: [Synth 8-3886] merging instance 'wb_toint_exc_reg[2]' (FDE) to 'wb_toint_exc_reg[3]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\wb_toint_exc_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (sharedFma/\io_out_pipe_b_exc_reg[3] ) +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[47]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[46]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[45]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[44]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[43]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[42]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[41]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[40]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[39]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[38]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[37]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[36]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[35]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[34]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[33]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[32]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[31]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[30]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[29]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[28]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[27]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[26]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[25]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[24]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[23]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[22]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[21]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[47]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[46]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[45]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[44]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[43]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[42]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[41]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[40]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[39]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[38]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[37]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[36]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[35]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[34]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[33]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[32]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[31]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[30]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[29]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[28]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[27]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[26]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[25]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[24]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[23]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[22]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[21]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[20]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[19]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[18]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[17]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[47]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[46]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[45]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[44]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[43]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[42]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[41]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[40]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[39]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[38]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[37]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[36]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[35]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[34]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[33]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[32]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[31]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[30]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[29]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[28]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[27]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[26]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[25]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[24]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[23]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[22]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[21]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[20]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[19]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[18]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[17]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_15_reg[9]' (FDRE) to 'bat/entNewAlias_15_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_15_reg[6]' (FDRE) to 'bat/entNewAlias_15_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_15_reg[7]' (FDRE) to 'bat/entNewAlias_15_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_15_reg[8]' (FDRE) to 'bat/entNewAlias_15_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_15_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_14_reg[9]' (FDRE) to 'bat/entNewAlias_14_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_14_reg[6]' (FDRE) to 'bat/entNewAlias_14_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_14_reg[7]' (FDRE) to 'bat/entNewAlias_14_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_14_reg[8]' (FDRE) to 'bat/entNewAlias_14_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_14_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_13_reg[9]' (FDRE) to 'bat/entNewAlias_13_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_13_reg[6]' (FDRE) to 'bat/entNewAlias_13_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_13_reg[7]' (FDRE) to 'bat/entNewAlias_13_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_13_reg[8]' (FDRE) to 'bat/entNewAlias_13_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_13_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_12_reg[9]' (FDRE) to 'bat/entNewAlias_12_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_12_reg[6]' (FDRE) to 'bat/entNewAlias_12_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_12_reg[7]' (FDRE) to 'bat/entNewAlias_12_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_12_reg[8]' (FDRE) to 'bat/entNewAlias_12_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_12_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_11_reg[9]' (FDRE) to 'bat/entNewAlias_11_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_11_reg[6]' (FDRE) to 'bat/entNewAlias_11_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_11_reg[7]' (FDRE) to 'bat/entNewAlias_11_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_11_reg[8]' (FDRE) to 'bat/entNewAlias_11_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_11_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_10_reg[9]' (FDRE) to 'bat/entNewAlias_10_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_10_reg[6]' (FDRE) to 'bat/entNewAlias_10_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_10_reg[7]' (FDRE) to 'bat/entNewAlias_10_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_10_reg[8]' (FDRE) to 'bat/entNewAlias_10_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_10_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_9_reg[9]' (FDRE) to 'bat/entNewAlias_9_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_9_reg[6]' (FDRE) to 'bat/entNewAlias_9_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_9_reg[7]' (FDRE) to 'bat/entNewAlias_9_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_9_reg[8]' (FDRE) to 'bat/entNewAlias_9_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_9_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_8_reg[9]' (FDRE) to 'bat/entNewAlias_8_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_8_reg[6]' (FDRE) to 'bat/entNewAlias_8_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_8_reg[7]' (FDRE) to 'bat/entNewAlias_8_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_8_reg[8]' (FDRE) to 'bat/entNewAlias_8_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_8_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_7_reg[9]' (FDRE) to 'bat/entNewAlias_7_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_7_reg[6]' (FDRE) to 'bat/entNewAlias_7_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_7_reg[7]' (FDRE) to 'bat/entNewAlias_7_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_7_reg[8]' (FDRE) to 'bat/entNewAlias_7_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_7_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_6_reg[9]' (FDRE) to 'bat/entNewAlias_6_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_6_reg[6]' (FDRE) to 'bat/entNewAlias_6_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_6_reg[7]' (FDRE) to 'bat/entNewAlias_6_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_6_reg[8]' (FDRE) to 'bat/entNewAlias_6_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_6_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_5_reg[9]' (FDRE) to 'bat/entNewAlias_5_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_5_reg[6]' (FDRE) to 'bat/entNewAlias_5_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_5_reg[7]' (FDRE) to 'bat/entNewAlias_5_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_5_reg[8]' (FDRE) to 'bat/entNewAlias_5_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_5_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_4_reg[9]' (FDRE) to 'bat/entNewAlias_4_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_4_reg[6]' (FDRE) to 'bat/entNewAlias_4_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_4_reg[7]' (FDRE) to 'bat/entNewAlias_4_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_4_reg[8]' (FDRE) to 'bat/entNewAlias_4_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_4_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_3_reg[9]' (FDRE) to 'bat/entNewAlias_3_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_3_reg[6]' (FDRE) to 'bat/entNewAlias_3_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_3_reg[7]' (FDRE) to 'bat/entNewAlias_3_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_3_reg[8]' (FDRE) to 'bat/entNewAlias_3_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_3_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_2_reg[9]' (FDRE) to 'bat/entNewAlias_2_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_2_reg[6]' (FDRE) to 'bat/entNewAlias_2_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_2_reg[7]' (FDRE) to 'bat/entNewAlias_2_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_2_reg[8]' (FDRE) to 'bat/entNewAlias_2_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_2_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_1_reg[9]' (FDRE) to 'bat/entNewAlias_1_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_1_reg[6]' (FDRE) to 'bat/entNewAlias_1_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_1_reg[7]' (FDRE) to 'bat/entNewAlias_1_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_1_reg[8]' (FDRE) to 'bat/entNewAlias_1_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_1_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_0_reg[9]' (FDRE) to 'bat/entNewAlias_0_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_0_reg[6]' (FDRE) to 'bat/entNewAlias_0_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_0_reg[7]' (FDRE) to 'bat/entNewAlias_0_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_0_reg[8]' (FDRE) to 'bat/entNewAlias_0_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_0_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/v2a_15_reg[9]' (FDRE) to 'bat/v2a_15_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_14_reg[9]' (FDRE) to 'bat/v2a_14_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_13_reg[9]' (FDRE) to 'bat/v2a_13_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_12_reg[9]' (FDRE) to 'bat/v2a_12_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_11_reg[9]' (FDRE) to 'bat/v2a_11_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_10_reg[9]' (FDRE) to 'bat/v2a_10_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_9_reg[9]' (FDRE) to 'bat/v2a_9_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_8_reg[9]' (FDRE) to 'bat/v2a_8_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_7_reg[9]' (FDRE) to 'bat/v2a_7_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_6_reg[9]' (FDRE) to 'bat/v2a_6_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_5_reg[9]' (FDRE) to 'bat/v2a_5_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_4_reg[9]' (FDRE) to 'bat/v2a_4_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_3_reg[9]' (FDRE) to 'bat/v2a_3_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_2_reg[9]' (FDRE) to 'bat/v2a_2_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_1_reg[9]' (FDRE) to 'bat/v2a_1_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_0_reg[9]' (FDRE) to 'bat/v2a_0_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_15_reg[6]' (FDRE) to 'bat/v2a_15_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_14_reg[6]' (FDRE) to 'bat/v2a_14_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_13_reg[6]' (FDRE) to 'bat/v2a_13_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_12_reg[6]' (FDRE) to 'bat/v2a_12_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_11_reg[6]' (FDRE) to 'bat/v2a_11_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_10_reg[6]' (FDRE) to 'bat/v2a_10_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_9_reg[6]' (FDRE) to 'bat/v2a_9_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_8_reg[6]' (FDRE) to 'bat/v2a_8_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_7_reg[6]' (FDRE) to 'bat/v2a_7_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_6_reg[6]' (FDRE) to 'bat/v2a_6_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_5_reg[6]' (FDRE) to 'bat/v2a_5_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_4_reg[6]' (FDRE) to 'bat/v2a_4_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_3_reg[6]' (FDRE) to 'bat/v2a_3_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_2_reg[6]' (FDRE) to 'bat/v2a_2_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_1_reg[6]' (FDRE) to 'bat/v2a_1_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_0_reg[6]' (FDRE) to 'bat/v2a_0_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_15_reg[7]' (FDRE) to 'bat/v2a_15_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_14_reg[7]' (FDRE) to 'bat/v2a_14_reg[8]' +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_15_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_14_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_13_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_12_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_11_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_10_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_9_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_8_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_7_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_6_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_5_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_4_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_3_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_2_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_1_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_0_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_15_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_14_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_13_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_12_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_11_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_10_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_9_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_8_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_7_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_6_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_5_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_4_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_3_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_2_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_1_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_0_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_15_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_0_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_1_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_2_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_3_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_4_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_5_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_6_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_7_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_8_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_9_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_10_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_11_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_12_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_13_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_14_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [Synth 8-3332] Sequential element (FSM_onehot_state_reg[7]) is unused and will be removed from module MemConfiger. +WARNING: [Synth 8-3332] Sequential element (FSM_onehot_state_reg[6]) is unused and will be removed from module MemConfiger. +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\roccMemIF/s1_req_tag_reg[0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/\ex_reg_cause_reg[7] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_mie_reg[38] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_mcountinhibit_reg[1] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\roccMemIF/io_cache_s1_data_r_data_reg[63] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/reg_singleStepped_reg) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_satp_mode_reg[2] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[40] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[41] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[42] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[43] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[44] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[45] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[46] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[47] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[48] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[49] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[50] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[51] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[52] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[53] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[54] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[55] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[56] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[57] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[58] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[59] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[60] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[61] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[62] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (cores_0/csr/\reg_misa_reg[63] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[7] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[10] ) +INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_114_115 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_108_113 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_102_107 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_96_101 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_90_95 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_84_89 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_78_83 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_72_77 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_66_71 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_60_65 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_54_59 from module BBTile__GCB1 due to constant propagation +INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_114_115 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_72_77 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_66_71 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_60_65 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_54_59 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_48_53 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_42_47 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_36_41 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_30_35 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_24_29 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_18_23 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_72_77 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_10/buffer_1/nodeOut_a_q/ram_ext/Memory_reg_0_1_6_11 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_4/coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_r_deq_q/ram_ext/Memory_reg_0_1_60_65 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_4/coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_r_deq_q/ram_ext/Memory_reg_0_1_54_59 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_4/coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_r_deq_q/ram_ext/Memory_reg_0_1_48_53 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_11/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_0/ram_ext/Memory_reg_0_7_60_65 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_12/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_1/ram_ext/Memory_reg_0_7_60_65 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_13/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_2/ram_ext/Memory_reg_0_7_60_65 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_14/i_0/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_3/ram_ext/Memory_reg_0_7_60_65 from module extram__53 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_11/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_0/ram_ext/Memory_reg_0_7_54_59 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_12/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_1/ram_ext/Memory_reg_0_7_60_65 from module SystemBus due to constant propagation +--------------------------------------------------------------------------------- +Start Post Area Optimization : Time (s): cpu = 00:12:10 ; elapsed = 00:12:45 . Memory (MB): peak = 6506.914 ; gain = 3033.230 ; free physical = 170883 ; free virtual = 522372 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:12:16 ; elapsed = 00:12:51 . Memory (MB): peak = 6506.914 ; gain = 3033.230 ; free physical = 170933 ; free virtual = 522423 +--------------------------------------------------------------------------------- + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_0 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_0 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_10 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_10 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_11 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_12 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_13 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_14 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_15 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_16 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_17 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_18 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_19 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1a : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1b : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1c : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1d : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1e : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1f : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_2 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_20 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_21 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_22 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_23 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_24 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_25 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_26 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_27 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_28 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_29 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2a : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2b : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2c : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2d : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2e : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2f : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_3 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_3 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_30 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_4 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_4 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_5 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_5 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_6 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_6 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_7 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_7 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_8 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_8 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_9 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_9 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_a : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_a : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_b : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_b : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_c : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_c : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_d : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_d : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_e : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_e : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_f : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_f : 0 0 : 519 519 : Used 1 time 100 + Sort Area is BBTile__GCB0 remainder1_8 : 0 0 : 3475 13938 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_8 : 0 1 : 3494 13938 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_8 : 0 2 : 3475 13938 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_8 : 0 3 : 3494 13938 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_6 : 0 0 : 3137 13243 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_6 : 0 1 : 3475 13243 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_6 : 0 2 : 3494 13243 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_6 : 0 3 : 3137 13243 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_4 : 0 0 : 3137 12905 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_4 : 0 1 : 3137 12905 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_4 : 0 2 : 3494 12905 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_4 : 0 3 : 3137 12905 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_0 : 0 0 : 3137 12586 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_0 : 0 1 : 3156 12586 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_0 : 0 2 : 3137 12586 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_0 : 0 3 : 3156 12586 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_8 : 0 0 : 3274 9889 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_8 : 0 1 : 3274 9889 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_8 : 0 2 : 3341 9889 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_4 : 0 0 : 3274 9733 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_4 : 0 1 : 3137 9733 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_4 : 0 2 : 3322 9733 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_0 : 0 0 : 3137 9478 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_0 : 0 1 : 3156 9478 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_0 : 0 2 : 3185 9478 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr1_15 : 0 0 : 2588 5929 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr1_15 : 0 1 : 3341 5929 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_weightAddr1_1b : 0 0 : 2588 5929 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_weightAddr1_1b : 0 1 : 3341 5929 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr1_20 : 0 0 : 2588 5807 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr1_20 : 0 1 : 3219 5807 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_0_bits_dram_addr5_5 : 0 0 : 3052 5790 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_0_bits_dram_addr5_5 : 0 1 : 2738 5790 : Used 1 time 0 + Sort Area is GemminiBall__GC0 _GEN_362_2 : 0 0 : 3034 5772 : Used 1 time 0 + Sort Area is GemminiBall__GC0 _GEN_362_2 : 0 1 : 2738 5772 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_1_bits_dram_addr4_7 : 0 0 : 3035 5756 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_1_bits_dram_addr4_7 : 0 1 : 2721 5756 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_2_bits_dram_addr2_a : 0 0 : 3035 5756 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_2_bits_dram_addr2_a : 0 1 : 2721 5756 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr4_f : 0 0 : 2588 5309 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr4_f : 0 1 : 2721 5309 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr4_1d : 0 0 : 2588 5309 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr4_1d : 0 1 : 2721 5309 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr4_12 : 0 0 : 2722 2987 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr4_12 : 0 1 : 265 2987 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_weightAddr2_19 : 0 0 : 2838 2838 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr4_1e : 0 0 : 1946 2168 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr4_1e : 0 1 : 222 2168 : Used 1 time 0 + Sort Area is GemminiBall__GC0 _GEN_363_0 : 0 0 : 1978 1978 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr5_d : 0 0 : 1946 1946 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr5_1c : 0 0 : 1946 1946 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_a : 0 0 : 1207 1207 : Used 1 time 0 + Sort Area is GemminiBall__GC0 _icol_T_7_b : 0 0 : 949 949 : Used 1 time 0 + Sort Area is GemminiBall__GC0 _irow_T_7_11 : 0 0 : 949 949 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_weightAddr4_17 : 0 0 : 949 949 : Used 1 time 0 + Sort Area is MemFrontend rowSkip_reg_0 : 0 0 : 768 768 : Used 1 time 0 + Sort Area is MemFrontend readVaddr1_2 : 0 0 : 733 733 : Used 1 time 0 +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Block RAM: Preliminary Mapping Report (see note below) ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|GlobalROB__GB1 | robOperands/robOperands_ext/lanes[0].ram_reg | 16 x 128(READ_FIRST) | W | | 16 x 128(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_0 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_1 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_2 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_3 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_4 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_5 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_6 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_7 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|dcache/mshrs | sdq_ext/Memory_reg | 17 x 64(READ_FIRST) | W | | 17 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_0/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_0/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_1/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_1/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_0/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_0/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_1/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_1/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ + +Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once. + +Distributed RAM: Preliminary Mapping Report (see note below) ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ +|regfile_ext | bank0_reg | User Attribute | 32 x 65 | RAM32M x 33 | +|regfile_ext | bank1_reg | User Attribute | 32 x 65 | RAM32M x 33 | +|toy_a7_top | completeQueue/ram_ext/Memory_reg | Implied | 16 x 4 | RAM32M x 1 | +|toy_a7_top | subRob/sram/sram_ext/lanes[0].ram_reg | User Attribute | 8 x 1262 | RAM32M x 211 | +|toy_a7_top | total_rows_q/ram_ext/Memory_reg | Implied | 8 x 7 | RAM32M x 2 | +|GemminiExCtrl__GC0 | rdQueue0/ram_data_ext/Memory_reg | Implied | 8 x 64 | RAM32M x 11 | +|GemminiExCtrl__GC0 | rdQueue1/ram_data_ext/Memory_reg | Implied | 8 x 64 | RAM32M x 11 | +|toy_a7_top | ballRs/fifo/ram_ext/Memory_reg | Implied | 4 x 281 | RAM32M x 47 | +|memRs | fifo/ram_ext/Memory_reg | Implied | 4 x 158 | RAM32M x 27 | +|toy_a7_top | bankReadReqQ_q/ram_ext/Memory_reg | Implied | 8 x 21 | RAM32M x 4 | +|toy_a7_top | bankReadReqQ_q_1/ram_ext/Memory_reg | Implied | 8 x 21 | RAM32M x 4 | +|cores_0 | rf_ext/Memory_reg | Implied | 32 x 64 | RAM32M x 22 | +|BBTile__GCB0 | buffer_2/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 117 | RAM32M x 20 | +|BBTile__GCB0 | buffer_2/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 78 | RAM32M x 13 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_tag_array/bbtile_icache_tag_array_ext/lanes[0].ram_reg | User Attribute | 64 x 21 | RAM64X1S x 21 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_tag_array/bbtile_icache_tag_array_ext/lanes[1].ram_reg | User Attribute | 64 x 21 | RAM64X1S x 21 | +|BBTile__GCB1 | buffer_1/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 116 | RAM32M x 20 | +|BBTile__GCB1 | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 116 | RAM32M x 20 | +|BBTile__GCB1 | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 76 | RAM32M x 13 | +|dcache/mshrs | mshrs_0/rpq/ram_ext/Memory_reg | Implied | 16 x 64 | RAM32M x 11 | +|dcache/meta | tag_array/tag_array_ext/lanes[0].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[1].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[2].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[3].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|toy_a7_top | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 189 | RAM32M x 32 | +|toy_a7_top | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 142 | RAM32M x 24 | +|toy_a7_top | buffer/nodeOut_a_q_1/ram_ext/Memory_reg | Implied | 2 x 188 | RAM32M x 32 | +|toy_a7_top | buffer/nodeIn_d_q_1/ram_ext/Memory_reg | Implied | 2 x 142 | RAM32M x 24 | +|toy_a7_top | buffer/nodeIn_b_q/ram_ext/Memory_reg | Implied | 2 x 60 | RAM32M x 10 | +|toy_a7_top | buffer/nodeOut_c_q/ram_ext/Memory_reg | Implied | 2 x 172 | RAM32M x 29 | +|toy_a7_top | buffer/nodeOut_e_q/ram_sink_ext/Memory_reg | Implied | 2 x 1 | RAM16X1D x 1 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_aw_deq_q/ram_ext/Memory_reg | Implied | 2 x 58 | RAM32M x 10 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_w_deq_q/ram_ext/Memory_reg | Implied | 2 x 73 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_b_deq_q/ram_ext/Memory_reg | Implied | 2 x 4 | RAM32M x 1 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_ar_deq_q/ram_ext/Memory_reg | Implied | 2 x 58 | RAM32M x 10 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_r_deq_q/ram_ext/Memory_reg | Implied | 2 x 69 | RAM32M x 12 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_1/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_2/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_3/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_4/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_5/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_0/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_1/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_2/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_3/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|cbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 114 | RAM32M x 19 | +|cbus | wrapped_error_device/buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 100 | RAM32M x 17 | +|cbus | wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 79 | RAM32M x 14 | +|cbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 79 | RAM32M x 14 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_1/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_2/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_3/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_4/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_5/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_6/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_7/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_8/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_9/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_10/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_11/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_12/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_13/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_14/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_15/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_16/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_17/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_18/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_19/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_20/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_21/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_22/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_23/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_24/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_25/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_26/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_27/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_28/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_29/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_30/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_31/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|coh_wrapper | broadcast_1/TLBroadcastTracker/o_data_q/ram_ext/Memory_reg | Implied | 4 x 144 | RAM32M x 24 | +|coh_wrapper | broadcast_1/TLBroadcastTracker_1/o_data_q/ram_ext/Memory_reg | Implied | 4 x 144 | RAM32M x 24 | +|platformi_21/loader | payload_reg | User Attribute | 256 x 8 | RAM128X1D x 16 | +|platformi_21/peripherals | fifo_reg | User Attribute | 256 x 8 | RAM64M x 12 | ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ + +Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. + +DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set) ++----------------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ +|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | ++----------------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | A2*B2 | 20 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | PCIN+A2*B2 | 20 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN>>17)+A2*B2 | 20 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 1 | +|SharedMulAddRecFNPipe | A2*B2 | 20 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN+A2*B2)' | 20 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 1 | +|SharedMulAddRecFNPipe | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN>>17)+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN+A2*B2)' | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 1 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopMatmulUnroller | A2*B2 | 16 | 16 | - | - | 32 | 1 | 1 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A*B2 | 18 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | (PCIN>>17)+A2*B | 17 | 16 | - | - | 48 | 1 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A2*B2 | 18 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | (PCIN>>17)+A2*B | 17 | 16 | - | - | 48 | 1 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A2*B | 18 | 17 | - | - | 48 | 1 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | (PCIN>>17)+A*B | 17 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A2*B | 18 | 17 | - | - | 48 | 1 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | (PCIN>>17)+A*B | 17 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | C+A*B | 16 | 8 | 24 | - | 24 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 24 | 16 | - | - | 40 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 16 | 16 | - | - | 32 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 18 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | (PCIN>>17)+A*B | 17 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | C+A*B | 16 | 8 | 24 | - | 24 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN+A:B+C | 6 | 18 | 39 | - | -1 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 18 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | (PCIN>>17)+A*B | 23 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | C+A*B | 16 | 8 | 16 | - | 24 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | C+A*B | 24 | 16 | 16 | - | 39 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 18 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | (PCIN>>17)+A*B | 23 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 16 | 16 | - | - | 32 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 16 | 16 | - | - | 32 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 18 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | (PCIN>>17)+A*B | 17 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN+(A:0x0):B+C | 30 | 16 | 37 | - | -1 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 18 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | (PCIN>>17)+A*B | 21 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|StreamReader | (A*B)' | 19 | 6 | - | - | 25 | 0 | 0 | - | - | - | 1 | 0 | +|StreamReader | A*B2 | 10 | 10 | - | - | 20 | 0 | 1 | - | - | - | 0 | 0 | +|MulDiv | A2*B2 | 23 | 6 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | ++----------------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ + +Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once. +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:12:23 ; elapsed = 00:12:58 . Memory (MB): peak = 6506.914 ; gain = 3033.230 ; free physical = 170809 ; free virtual = 522399 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:12:37 ; elapsed = 00:13:12 . Memory (MB): peak = 6506.914 ; gain = 3033.230 ; free physical = 170923 ; free virtual = 522495 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Block RAM: Final Mapping Report ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|GlobalROB__GB1 | robOperands/robOperands_ext/lanes[0].ram_reg | 16 x 128(READ_FIRST) | W | | 16 x 128(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_0 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_1 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_2 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_3 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_4 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_5 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_6 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_7 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|dcache/mshrs | sdq_ext/Memory_reg | 17 x 64(READ_FIRST) | W | | 17 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_0/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_0/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_1/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_1/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_0/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_0/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_1/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_1/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ + + +Distributed RAM: Final Mapping Report ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ +|regfile_ext | bank0_reg | User Attribute | 32 x 65 | RAM32M x 33 | +|regfile_ext | bank1_reg | User Attribute | 32 x 65 | RAM32M x 33 | +|toy_a7_top | total_rows_q/ram_ext/Memory_reg | Implied | 8 x 7 | RAM32M x 2 | +|GemminiExCtrl__GC0 | rdQueue0/ram_data_ext/Memory_reg | Implied | 8 x 64 | RAM32M x 11 | +|GemminiExCtrl__GC0 | rdQueue1/ram_data_ext/Memory_reg | Implied | 8 x 64 | RAM32M x 11 | +|toy_a7_top | ballRs/fifo/ram_ext/Memory_reg | Implied | 4 x 281 | RAM32M x 47 | +|memRs | fifo/ram_ext/Memory_reg | Implied | 4 x 158 | RAM32M x 27 | +|toy_a7_top | bankReadReqQ_q/ram_ext/Memory_reg | Implied | 8 x 21 | RAM32M x 4 | +|toy_a7_top | bankReadReqQ_q_1/ram_ext/Memory_reg | Implied | 8 x 21 | RAM32M x 4 | +|toy_a7_top | completeQueue/ram_ext/Memory_reg | Implied | 16 x 4 | RAM32M x 1 | +|toy_a7_top | subRob/sram/sram_ext/lanes[0].ram_reg | User Attribute | 8 x 1262 | RAM32M x 211 | +|cores_0 | rf_ext/Memory_reg | Implied | 32 x 64 | RAM32M x 22 | +|BBTile__GCB0 | buffer_2/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 117 | RAM32M x 20 | +|BBTile__GCB0 | buffer_2/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 78 | RAM32M x 13 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_tag_array/bbtile_icache_tag_array_ext/lanes[0].ram_reg | User Attribute | 64 x 21 | RAM64X1S x 21 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_tag_array/bbtile_icache_tag_array_ext/lanes[1].ram_reg | User Attribute | 64 x 21 | RAM64X1S x 21 | +|BBTile__GCB1 | buffer_1/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 116 | RAM32M x 20 | +|BBTile__GCB1 | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 116 | RAM32M x 20 | +|BBTile__GCB1 | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 76 | RAM32M x 13 | +|dcache/mshrs | mshrs_0/rpq/ram_ext/Memory_reg | Implied | 16 x 64 | RAM32M x 11 | +|dcache/meta | tag_array/tag_array_ext/lanes[0].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[1].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[2].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[3].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|toy_a7_top | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 189 | RAM32M x 32 | +|toy_a7_top | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 142 | RAM32M x 24 | +|toy_a7_top | buffer/nodeOut_a_q_1/ram_ext/Memory_reg | Implied | 2 x 188 | RAM32M x 32 | +|toy_a7_top | buffer/nodeIn_d_q_1/ram_ext/Memory_reg | Implied | 2 x 142 | RAM32M x 24 | +|toy_a7_top | buffer/nodeIn_b_q/ram_ext/Memory_reg | Implied | 2 x 60 | RAM32M x 10 | +|toy_a7_top | buffer/nodeOut_c_q/ram_ext/Memory_reg | Implied | 2 x 172 | RAM32M x 29 | +|toy_a7_top | buffer/nodeOut_e_q/ram_sink_ext/Memory_reg | Implied | 2 x 1 | RAM16X1D x 1 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_aw_deq_q/ram_ext/Memory_reg | Implied | 2 x 58 | RAM32M x 10 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_w_deq_q/ram_ext/Memory_reg | Implied | 2 x 73 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_b_deq_q/ram_ext/Memory_reg | Implied | 2 x 4 | RAM32M x 1 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_ar_deq_q/ram_ext/Memory_reg | Implied | 2 x 58 | RAM32M x 10 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_r_deq_q/ram_ext/Memory_reg | Implied | 2 x 69 | RAM32M x 12 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_1/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_2/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_3/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_4/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_5/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_0/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_1/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_2/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_3/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|cbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 114 | RAM32M x 19 | +|cbus | wrapped_error_device/buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 100 | RAM32M x 17 | +|cbus | wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 79 | RAM32M x 14 | +|cbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 79 | RAM32M x 14 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_1/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_2/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_3/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_4/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_5/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_6/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_7/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_8/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_9/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_10/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_11/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_12/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_13/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_14/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_15/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_16/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_17/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_18/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_19/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_20/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_21/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_22/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_23/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_24/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_25/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_26/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_27/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_28/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_29/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_30/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_31/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|coh_wrapper | broadcast_1/TLBroadcastTracker/o_data_q/ram_ext/Memory_reg | Implied | 4 x 144 | RAM32M x 24 | +|coh_wrapper | broadcast_1/TLBroadcastTracker_1/o_data_q/ram_ext/Memory_reg | Implied | 4 x 144 | RAM32M x 24 | +|platformi_21/loader | payload_reg | User Attribute | 256 x 8 | RAM128X1D x 16 | +|platformi_21/peripherals | fifo_reg | User Attribute | 256 x 8 | RAM64M x 12 | ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_0/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_0/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_1/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_1/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_2/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_2/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_3/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_3/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_4/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_4/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_5/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_5/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_6/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_6/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_7/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_7/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/mshrs/sdq_ext/Memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_0/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_0/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_1/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_1/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_0/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_0/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_1/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_1/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:12:55 ; elapsed = 00:13:31 . Memory (MB): peak = 6518.840 ; gain = 3045.156 ; free physical = 170749 ; free virtual = 522355 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_0/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_0/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_1/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_1/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_2/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_2/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_3/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_3/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_4/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_4/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_5/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_5/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_6/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_6/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_7/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_7/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/mshrs/sdq_ext/Memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_0/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_0/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_1/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_1/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_0/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_0/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_1/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_1/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/frontend/scheduler/rob/itraceComp of module ITraceDPI__1 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/frontend/scheduler/rob/itraceIssue of module ITraceDPI__2 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/frontend/scheduler/rob/itraceAlloc of module ITraceDPI having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/pmc/pmcTraces_0 of module PMCTraceDPI having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/pmc/ldPmcTrace of module MemPMCTraceDPI__1 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/pmc/stPmcTrace of module MemPMCTraceDPI having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_0 of module MTraceDPI__1 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_1 of module MTraceDPI__2 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_2 of module MTraceDPI__3 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_3 of module MTraceDPI__4 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_4 of module MTraceDPI__5 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_5 of module MTraceDPI__6 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_6 of module MTraceDPI having unconnected or no output ports +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:13:05 ; elapsed = 00:13:41 . Memory (MB): peak = 6518.840 ; gain = 3045.156 ; free physical = 170337 ; free virtual = 522368 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:13:05 ; elapsed = 00:13:41 . Memory (MB): peak = 6518.840 ; gain = 3045.156 ; free physical = 170329 ; free virtual = 522361 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:13:19 ; elapsed = 00:13:55 . Memory (MB): peak = 6518.840 ; gain = 3045.156 ; free physical = 170611 ; free virtual = 522358 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:13:20 ; elapsed = 00:13:55 . Memory (MB): peak = 6518.840 ; gain = 3045.156 ; free physical = 170598 ; free virtual = 522342 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:13:21 ; elapsed = 00:13:57 . Memory (MB): peak = 6518.840 ; gain = 3045.156 ; free physical = 170527 ; free virtual = 522271 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:13:21 ; elapsed = 00:13:57 . Memory (MB): peak = 6518.840 ; gain = 3045.156 ; free physical = 170524 ; free virtual = 522269 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Static Shift Register Report: ++------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ +|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | ++------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/out_matmul_id_RegShifted_0_0_reg[2] | 16 | 3 | NO | NO | YES | 3 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_0_0_reg[19] | 7 | 20 | NO | NO | YES | 20 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_1_6_0_reg[19] | 6 | 20 | NO | NO | YES | 20 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_2_6_0_reg[19] | 5 | 20 | NO | NO | YES | 20 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_3_6_0_reg[19] | 4 | 20 | NO | NO | YES | 20 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_4_6_0_reg[19] | 3 | 20 | NO | NO | YES | 20 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/out_last_RegShifted_0_0_reg | 16 | 1 | NO | NO | YES | 1 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_3_0_reg[7] | 3 | 8 | NO | NO | YES | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_4_0_reg[7] | 4 | 8 | NO | NO | YES | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_5_0_reg[7] | 5 | 8 | NO | NO | YES | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_6_0_reg[7] | 6 | 8 | NO | NO | YES | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_7_0_reg[7] | 7 | 8 | NO | NO | YES | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_3_1_0_reg[7] | 3 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_4_1_0_reg[7] | 4 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_5_1_0_reg[7] | 5 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_6_1_0_reg[7] | 6 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_7_1_0_reg[7] | 7 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_3_2_0_reg[7] | 3 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_4_2_0_reg[7] | 4 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_5_2_0_reg[7] | 5 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_6_2_0_reg[7] | 6 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_7_2_0_reg[7] | 7 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/ibus_intsink/chain/output_chain/sync_0_reg | 3 | 1 | NO | NO | YES | 1 | 0 | ++------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +DSP Final Report (the ' indicates corresponding REG is set) ++----------------------+--------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ +|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | ++----------------------+--------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ +|LoopConvAddrGen | C'+A'*B'' | 16 | 8 | 24 | - | 24 | 1 | 2 | 2 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 24 | 16 | - | - | 40 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A'*B'' | 16 | 16 | - | - | 32 | 1 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN>>17+A''*B | 16 | 15 | - | - | 48 | 2 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | C'+A'*B'' | 16 | 8 | 24 | - | 24 | 1 | 2 | 2 | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN+A:B+C | 6 | 18 | - | - | 39 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN>>17+A*B'' | 22 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | C'+A'*B'' | 16 | 8 | 16 | - | 24 | 1 | 2 | 2 | - | - | 0 | 0 | +|LoopConvAddrGen | C'+A*B'' | 24 | 16 | 16 | - | 39 | 0 | 2 | 2 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN>>17+A*B'' | 22 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A'*B'' | 16 | 16 | - | - | 32 | 1 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A'*B'' | 16 | 16 | - | - | 32 | 1 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN>>17+A''*B | 16 | 15 | - | - | 48 | 2 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN+A:B'+C | 0 | 16 | - | - | 37 | 0 | 1 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN>>17+A*B'' | 20 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|FpgaDspMac | C+A'*B | 30 | 18 | 48 | - | 20 | 1 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|LoopMatmulUnroller | A''*B'' | 16 | 16 | - | - | 32 | 2 | 2 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | PCIN>>17+A''*B | 16 | 15 | - | - | 48 | 2 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A''*B' | 17 | 16 | - | - | 48 | 2 | 1 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | PCIN>>17+A'*B'' | 16 | 15 | - | - | 48 | 1 | 2 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A''*B | 17 | 16 | - | - | 48 | 2 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | PCIN>>17+A*B'' | 16 | 15 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A''*B | 17 | 16 | - | - | 48 | 2 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | PCIN>>17+A*B'' | 16 | 15 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|StreamReader | (A*B')' | 19 | 4 | - | - | 25 | 0 | 1 | - | - | - | 0 | 1 | +|StreamReader | A*B' | 10 | 10 | - | - | 20 | 0 | 1 | - | - | - | 0 | 0 | +|MulDiv | A'*B' | 22 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A'*B' | 17 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A'*B' | 22 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN>>17+A'*B' | 22 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A'*B' | 17 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN>>17+A'*B' | 22 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN>>17+A'*B' | 17 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN>>17+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | A'*B' | 19 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | PCIN+A'*B'' | 19 | 17 | - | - | 48 | 1 | 2 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN>>17+A'*B'')' | 19 | 17 | - | - | 48 | 1 | 2 | - | - | - | 0 | 1 | +|SharedMulAddRecFNPipe | A'*B' | 19 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | PCIN+A'*B'' | 17 | 17 | - | - | 0 | 1 | 2 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN+A'*B'')' | 19 | 17 | - | - | 48 | 1 | 2 | - | - | - | 0 | 1 | +|SharedMulAddRecFNPipe | A'*B'' | 17 | 17 | - | - | 48 | 1 | 2 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | PCIN>>17+A'*B'' | 17 | 17 | - | - | 0 | 1 | 2 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN+A'*B'')' | 17 | 17 | - | - | 48 | 1 | 2 | - | - | - | 0 | 1 | ++----------------------+--------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ + + +Report BlackBoxes: ++------+--------------+----------+ +| |BlackBox name |Instances | ++------+--------------+----------+ +|1 |toy_axi_cdc | 1| +|2 |arty_ddr3 | 1| ++------+--------------+----------+ + +Report Cell Usage: ++------+------------+------+ +| |Cell |Count | ++------+------------+------+ +|1 |arty_ddr3 | 1| +|2 |toy_axi_cdc | 1| +|3 |BUFG | 4| +|4 |CARRY4 | 1950| +|5 |DSP48E1 | 117| +|18 |LUT1 | 817| +|19 |LUT2 | 4360| +|20 |LUT3 | 12197| +|21 |LUT4 | 10130| +|22 |LUT5 | 12422| +|23 |LUT6 | 18450| +|24 |MMCME2_BASE | 1| +|25 |MUXF7 | 629| +|26 |MUXF8 | 112| +|27 |RAM128X1D | 16| +|28 |RAM16X1D | 1| +|29 |RAM32M | 665| +|30 |RAM32X1D | 21| +|31 |RAM32X1S | 92| +|32 |RAM64M | 12| +|33 |RAM64X1S | 42| +|34 |RAMB18E1 | 8| +|35 |RAMB36E1 | 27| +|38 |SRL16E | 225| +|39 |FDCE | 8| +|40 |FDPE | 6| +|41 |FDRE | 28184| +|42 |FDSE | 457| +|43 |IBUF | 4| +|44 |OBUF | 9| ++------+------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:13:22 ; elapsed = 00:13:57 . Memory (MB): peak = 6518.840 ; gain = 3045.156 ; free physical = 170526 ; free virtual = 522271 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 553 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:13:08 ; elapsed = 00:13:50 . Memory (MB): peak = 6518.840 ; gain = 2869.582 ; free physical = 178430 ; free virtual = 530175 +Synthesis Optimization Complete : Time (s): cpu = 00:13:24 ; elapsed = 00:14:01 . Memory (MB): peak = 6518.840 ; gain = 3045.156 ; free physical = 178452 ; free virtual = 530179 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Project 1-454] Reading design checkpoint '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc.dcp' for cell 'memory_cdc' +INFO: [Project 1-454] Reading design checkpoint '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3.dcp' for cell 'ddr_controller' +Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 6518.840 ; gain = 0.000 ; free physical = 178422 ; free virtual = 530148 +INFO: [Netlist 29-17] Analyzing 4089 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2024.1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] for cell 'ddr_controller' +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] for cell 'ddr_controller' +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/arty_a7.xdc] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/arty_a7.xdc] +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/flash_boot.xdc] +CRITICAL WARNING: [Designutils 20-1307] Command 'if' is not supported in the xdc constraint file. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/flash_boot.xdc:11] +CRITICAL WARNING: [Designutils 20-1307] Command 'if' is not supported in the xdc constraint file. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/flash_boot.xdc:15] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/flash_boot.xdc] +INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3.dcp' +INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc.dcp' +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc] for cell 'memory_cdc/inst' +INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:16] +INFO: [Timing 38-2] Deriving generated clocks [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:16] +all_fanout: Time (s): cpu = 00:00:14 ; elapsed = 00:00:06 . Memory (MB): peak = 6518.840 ; gain = 0.000 ; free physical = 178304 ; free virtual = 530036 +WARNING: [Vivado_Tcl 4-2057] Waiver ID 'LUTAR-1' object list specifies likely unusable hierarchical instance 'memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi'. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:30] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:35] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:39] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:42] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:45] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:49] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:52] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:56] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:60] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:63] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:66] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:70] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc] for cell 'memory_cdc/inst' +INFO: [Project 1-1714] 33 XPM XDC files have been applied to the design. +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-1687] 16 scoped IP constraints or related sub-commands were skipped due to synthesis logic optimizations usually triggered by constant connectivity or unconnected output pins. To review the skipped constraints and messages, run the command 'set_param netlist.IPMsgFiltering false' before opening the design. +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6518.840 ; gain = 0.000 ; free physical = 178332 ; free virtual = 530063 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 1054 instances were transformed. + IOBUFDS_INTERMDISABLE => IOBUFDS_INTERMDISABLE (IBUFDS_INTERMDISABLE_INT(x2), INV, OBUFTDS(x2)): 2 instances + IOBUF_INTERMDISABLE => IOBUF_INTERMDISABLE (IBUF_INTERMDISABLE, OBUFT): 16 instances + MMCME2_BASE => MMCME2_ADV: 1 instance + OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 1 instance + RAM128X1D => RAM128X1D (MUXF7(x2), RAMD64E(x4)): 16 instances + RAM16X1D => RAM32X1D (RAMD32(x2)): 1 instance + RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 845 instances + RAM32X1D => RAM32X1D (RAMD32(x2)): 26 instances + RAM32X1S => RAM32X1S (RAMS32): 92 instances + RAM64M => RAM64M (RAMD64E(x4)): 12 instances + RAM64X1S => RAM64X1S (RAMS64E): 42 instances + +Synth Design complete | Checksum: a9a9e22e +INFO: [Common 17-83] Releasing license: Synthesis +608 Infos, 466 Warnings, 4 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:13:57 ; elapsed = 00:14:23 . Memory (MB): peak = 6518.840 ; gain = 3045.277 ; free physical = 178297 ; free virtual = 530027 +INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 13719.642; main = 5860.059; forked = 8257.207 +INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 19170.168; main = 6514.926; forked = 12655.242 +# write_checkpoint -force $out/synthesized.dcp +INFO: [Timing 38-480] Writing timing data to binary archive. +Wrote PlaceDB: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6538.930 ; gain = 0.000 ; free physical = 178297 ; free virtual = 530027 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6538.930 ; gain = 0.000 ; free physical = 178297 ; free virtual = 530027 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.02 . Memory (MB): peak = 6538.930 ; gain = 0.000 ; free physical = 178297 ; free virtual = 530028 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6538.930 ; gain = 0.000 ; free physical = 178297 ; free virtual = 530028 +Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 6538.930 ; gain = 0.000 ; free physical = 178297 ; free virtual = 530029 +Write Physdb Complete: Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.03 . Memory (MB): peak = 6538.930 ; gain = 0.000 ; free physical = 178297 ; free virtual = 530029 +Write ShapeDB Complete: Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.11 . Memory (MB): peak = 6538.930 ; gain = 0.000 ; free physical = 178289 ; free virtual = 530027 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/synthesized.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 6538.930 ; gain = 20.090 ; free physical = 178342 ; free virtual = 530142 +# report_utilization -file $out/synth-utilization.rpt +# report_utilization -hierarchical -file $out/synth-hierarchy.rpt +# report_timing_summary -delay_type min_max -file $out/synth-timing.rpt +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. +report_timing_summary: Time (s): cpu = 00:00:21 ; elapsed = 00:00:07 . Memory (MB): peak = 6538.930 ; gain = 0.000 ; free physical = 178359 ; free virtual = 530163 +# set unresolved [get_cells -hier -quiet -filter {IS_BLACKBOX == 1}] +# if {[llength $unresolved]} {error "Unresolved black boxes: $unresolved"} +# phase OPTIMIZE +BOARD_PHASE OPTIMIZE +# opt_design -directive ExploreArea +Command: opt_design -directive ExploreArea +INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: ExploreArea +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 8 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.78 . Memory (MB): peak = 6570.945 ; gain = 32.016 ; free physical = 178367 ; free virtual = 530173 + +Starting Logic Optimization Task + +Phase 1 Initialization + +Phase 1.1 Core Generation And Design Setup +Phase 1.1 Core Generation And Design Setup | Checksum: 2c6ce0b9c + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 178365 ; free virtual = 530172 + +Phase 1.2 Setup Constraints And Sort Netlist +Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 2c6ce0b9c + +Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.04 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 178365 ; free virtual = 530172 +Phase 1 Initialization | Checksum: 2c6ce0b9c + +Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 178365 ; free virtual = 530172 + +Phase 2 Timer Update And Timing Data Collection + +Phase 2.1 Timer Update +Phase 2.1 Timer Update | Checksum: 2c6ce0b9c + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 178371 ; free virtual = 530178 + +Phase 2.2 Timing Data Collection +Phase 2.2 Timing Data Collection | Checksum: 2c6ce0b9c + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 178375 ; free virtual = 530182 +Phase 2 Timer Update And Timing Data Collection | Checksum: 2c6ce0b9c + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 178375 ; free virtual = 530182 + +Phase 3 Retarget +INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0 +INFO: [Opt 31-1566] Pulled 311 inverters resulting in an inversion of 2868 pins +INFO: [Opt 31-138] Pushed 8 inverter(s) to 9 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 3 Retarget | Checksum: 295d70cd1 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 178347 ; free virtual = 530154 +Retarget | Checksum: 295d70cd1 +INFO: [Opt 31-389] Phase Retarget created 97 cells and removed 603 cells +INFO: [Opt 31-1021] In phase Retarget, 52 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 4 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 4 Constant propagation | Checksum: 256694385 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 178293 ; free virtual = 530101 +Constant propagation | Checksum: 256694385 +INFO: [Opt 31-389] Phase Constant propagation created 12 cells and removed 19 cells +INFO: [Opt 31-1021] In phase Constant propagation, 30 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 5 Sweep +Phase 5 Sweep | Checksum: 25a775b40 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 178233 ; free virtual = 530041 +Sweep | Checksum: 25a775b40 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 333 cells +INFO: [Opt 31-1021] In phase Sweep, 150 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 6 BUFG optimization +Phase 6 BUFG optimization | Checksum: 2e91af07d + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 178234 ; free virtual = 530042 +BUFG optimization | Checksum: 2e91af07d +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. + +Phase 7 Shift Register Optimization +INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs +Phase 7 Shift Register Optimization | Checksum: 2e91af07d + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:05 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 178234 ; free virtual = 530042 +Shift Register Optimization | Checksum: 2e91af07d +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells +INFO: [Opt 31-1555] control_set_opt supports Versal devices only, and device 7a100t is unsupported + +Phase 8 Resynthesis +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Opt 31-74] Optimized 105 modules. +INFO: [Opt 31-75] Optimized module 'AccPipe'. +INFO: [Opt 31-75] Optimized module 'AccPipe_11'. +INFO: [Opt 31-75] Optimized module 'AccPipe_12'. +INFO: [Opt 31-75] Optimized module 'AccPipe_13'. +INFO: [Opt 31-75] Optimized module 'AccPipe_14'. +INFO: [Opt 31-75] Optimized module 'AccPipe_15'. +INFO: [Opt 31-75] Optimized module 'AccPipe_16'. +INFO: [Opt 31-75] Optimized module 'BankScoreboard'. +INFO: [Opt 31-75] Optimized module 'DTLB'. +INFO: [Opt 31-75] Optimized module 'DivSqrtRawFN_small_e8_s24'. +INFO: [Opt 31-75] Optimized module 'FPToInt'. +INFO: [Opt 31-75] Optimized module 'GemminiExCtrl'. +INFO: [Opt 31-75] Optimized module 'IBuf'. +INFO: [Opt 31-75] Optimized module 'ICache'. +INFO: [Opt 31-75] Optimized module 'ITLB'. +INFO: [Opt 31-75] Optimized module 'LoopConvUnroller'. +INFO: [Opt 31-75] Optimized module 'MaxPeriodFibonacciLFSR_3'. +INFO: [Opt 31-75] Optimized module 'MemConfiger'. +INFO: [Opt 31-75] Optimized module 'MemMidend'. +INFO: [Opt 31-75] Optimized module 'MeshWithDelays'. +INFO: [Opt 31-75] Optimized module 'NonBlockingDCache'. +INFO: [Opt 31-75] Optimized module 'PE_64_186'. +INFO: [Opt 31-75] Optimized module 'PE_64_189'. +INFO: [Opt 31-75] Optimized module 'PE_64_192'. +INFO: [Opt 31-75] Optimized module 'PE_64_195'. +INFO: [Opt 31-75] Optimized module 'PE_64_198'. +INFO: [Opt 31-75] Optimized module 'PE_64_201'. +INFO: [Opt 31-75] Optimized module 'PE_64_204'. +INFO: [Opt 31-75] Optimized module 'PE_64_207'. +INFO: [Opt 31-75] Optimized module 'PE_64_210'. +INFO: [Opt 31-75] Optimized module 'PE_64_213'. +INFO: [Opt 31-75] Optimized module 'PE_64_216'. +INFO: [Opt 31-75] Optimized module 'PE_64_219'. +INFO: [Opt 31-75] Optimized module 'PE_64_222'. +INFO: [Opt 31-75] Optimized module 'PE_64_225'. +INFO: [Opt 31-75] Optimized module 'PE_64_228'. +INFO: [Opt 31-75] Optimized module 'PE_64_231'. +INFO: [Opt 31-75] Optimized module 'PE_64_234'. +INFO: [Opt 31-75] Optimized module 'PE_64_237'. +INFO: [Opt 31-75] Optimized module 'PE_64_240'. +INFO: [Opt 31-75] Optimized module 'PE_64_243'. +INFO: [Opt 31-75] Optimized module 'PE_64_246'. +INFO: [Opt 31-75] Optimized module 'PE_64_249'. +INFO: [Opt 31-75] Optimized module 'PE_64_252'. +INFO: [Opt 31-75] Optimized module 'PE_64_255'. +INFO: [Opt 31-75] Optimized module 'PE_64_258'. +INFO: [Opt 31-75] Optimized module 'PE_64_261'. +INFO: [Opt 31-75] Optimized module 'PE_64_264'. +INFO: [Opt 31-75] Optimized module 'PE_64_267'. +INFO: [Opt 31-75] Optimized module 'PE_64_270'. +INFO: [Opt 31-75] Optimized module 'PE_64_273'. +INFO: [Opt 31-75] Optimized module 'PE_64_276'. +INFO: [Opt 31-75] Optimized module 'PE_64_279'. +INFO: [Opt 31-75] Optimized module 'PE_64_282'. +INFO: [Opt 31-75] Optimized module 'PE_64_285'. +INFO: [Opt 31-75] Optimized module 'PE_64_288'. +INFO: [Opt 31-75] Optimized module 'PE_64_291'. +INFO: [Opt 31-75] Optimized module 'PE_64_294'. +INFO: [Opt 31-75] Optimized module 'PE_64_297'. +INFO: [Opt 31-75] Optimized module 'PE_64_300'. +INFO: [Opt 31-75] Optimized module 'PE_64_303'. +INFO: [Opt 31-75] Optimized module 'PE_64_306'. +INFO: [Opt 31-75] Optimized module 'PE_64_309'. +INFO: [Opt 31-75] Optimized module 'PE_64_312'. +INFO: [Opt 31-75] Optimized module 'PE_64_315'. +INFO: [Opt 31-75] Optimized module 'PE_64_318'. +INFO: [Opt 31-75] Optimized module 'PE_64_321'. +INFO: [Opt 31-75] Optimized module 'PE_64_324'. +INFO: [Opt 31-75] Optimized module 'PE_64_327'. +INFO: [Opt 31-75] Optimized module 'PE_64_330'. +INFO: [Opt 31-75] Optimized module 'PE_64_333'. +INFO: [Opt 31-75] Optimized module 'PE_64_336'. +INFO: [Opt 31-75] Optimized module 'PE_64_339'. +INFO: [Opt 31-75] Optimized module 'PE_64_342'. +INFO: [Opt 31-75] Optimized module 'PE_64_345'. +INFO: [Opt 31-75] Optimized module 'PE_64_348'. +INFO: [Opt 31-75] Optimized module 'PE_64_351'. +INFO: [Opt 31-75] Optimized module 'PE_64_354'. +INFO: [Opt 31-75] Optimized module 'Queue16_ReplayInternal'. +INFO: [Opt 31-75] Optimized module 'Queue1_RegMapperInput_i23_m8'. +INFO: [Opt 31-75] Optimized module 'Queue4_TLBroadcastData'. +INFO: [Opt 31-75] Optimized module 'Queue8_SramReadResp_39'. +INFO: [Opt 31-75] Optimized module 'Repeater_TLBundleA_a17d64s3k1z3u'. +INFO: [Opt 31-75] Optimized module 'ShiftQueue'. +INFO: [Opt 31-75] Optimized module 'SubROB'. +INFO: [Opt 31-75] Optimized module 'TLB'. +INFO: [Opt 31-75] Optimized module 'TLXbar_sbus_i2_o3_a32d128s3k1z4c'. +INFO: [Opt 31-75] Optimized module 'TagQueue'. +INFO: [Opt 31-75] Optimized module 'WritebackUnit'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_axi_mc_wr_cmd_fsm'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_bank_state__parameterized2'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_ddr_if_post_fifo'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_ddr_phy_rdlvl'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_ddr_phy_wrcal'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_rank_common'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_round_robin_arb'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_tempmon'. +INFO: [Opt 31-75] Optimized module 'axi_fullwidth'. +INFO: [Opt 31-75] Optimized module 'ram_2x58'. +INFO: [Opt 31-75] Optimized module 'ram_2x58_376'. +INFO: [Common 17-14] Message 'Opt 31-75' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Opt 31-1566] Pulled 2280 inverters resulting in an inversion of 7908 pins +INFO: [Opt 31-138] Pushed 4 inverter(s) to 19 load pin(s). +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 8 Resynthesis | Checksum: 1c3bf1ef2 + +Time (s): cpu = 00:02:49 ; elapsed = 00:00:55 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 177969 ; free virtual = 529776 +Resynthesis | Checksum: 1c3bf1ef2 +INFO: [Opt 31-389] Phase Resynthesis created 19062 cells and removed 19811 cells +INFO: [Opt 31-1021] In phase Resynthesis, 151 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 9 Post Processing Netlist +Phase 9 Post Processing Netlist | Checksum: 1c3bf1ef2 + +Time (s): cpu = 00:02:49 ; elapsed = 00:00:55 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 177974 ; free virtual = 529782 +Post Processing Netlist | Checksum: 1c3bf1ef2 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells +INFO: [Opt 31-1021] In phase Post Processing Netlist, 45 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 10 Finalization + +Phase 10.1 Finalizing Design Cores and Updating Shapes +Phase 10.1 Finalizing Design Cores and Updating Shapes | Checksum: 2249eaaa7 + +Time (s): cpu = 00:02:50 ; elapsed = 00:00:56 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 177981 ; free virtual = 529788 + +Phase 10.2 Verifying Netlist Connectivity + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.14 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 177982 ; free virtual = 529789 +Phase 10.2 Verifying Netlist Connectivity | Checksum: 2249eaaa7 + +Time (s): cpu = 00:02:50 ; elapsed = 00:00:57 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 177982 ; free virtual = 529789 +Phase 10 Finalization | Checksum: 2249eaaa7 + +Time (s): cpu = 00:02:50 ; elapsed = 00:00:57 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 177982 ; free virtual = 529789 +Opt_design Change Summary +========================= + + +------------------------------------------------------------------------------------------------------------------------- +| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | +------------------------------------------------------------------------------------------------------------------------- +| Retarget | 97 | 603 | 52 | +| Constant propagation | 12 | 19 | 30 | +| Sweep | 0 | 333 | 150 | +| BUFG optimization | 0 | 0 | 0 | +| Shift Register Optimization | 0 | 0 | 0 | +| Resynthesis | 19062 | 19811 | 151 | +| Post Processing Netlist | 0 | 0 | 45 | +------------------------------------------------------------------------------------------------------------------------- + + +Ending Logic Optimization Task | Checksum: 2249eaaa7 + +Time (s): cpu = 00:02:50 ; elapsed = 00:00:57 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 177982 ; free virtual = 529789 + +Starting Netlist Obfuscation Task +Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 177982 ; free virtual = 529789 +Ending Netlist Obfuscation Task | Checksum: 2249eaaa7 + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 177982 ; free virtual = 529789 +INFO: [Common 17-83] Releasing license: Implementation +131 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:02:54 ; elapsed = 00:01:00 . Memory (MB): peak = 6570.945 ; gain = 32.016 ; free physical = 177982 ; free virtual = 529789 +# write_checkpoint -force $out/optimized.dcp +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-480] Writing timing data to binary archive. +Wrote PlaceDB: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.02 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 177974 ; free virtual = 529780 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 177974 ; free virtual = 529780 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 177973 ; free virtual = 529780 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 177973 ; free virtual = 529780 +Wrote Device Cache: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 177973 ; free virtual = 529781 +Write Physdb Complete: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.04 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 177973 ; free virtual = 529781 +Write ShapeDB Complete: Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.12 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 177961 ; free virtual = 529778 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/optimized.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:18 ; elapsed = 00:00:12 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 177791 ; free virtual = 529665 +# report_utilization -file $out/opt-utilization.rpt +# phase PLACE +BOARD_PHASE PLACE +# place_design -directive Explore +Command: place_design -directive Explore +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-83] Releasing license: Implementation +INFO: [DRC 23-27] Running DRC with 8 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +INFO: [Vivado_Tcl 4-2302] The placer was invoked with the 'Explore' directive. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 8 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs + +Starting Placer Task + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 177799 ; free virtual = 529674 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 14f5d1a2b + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 177799 ; free virtual = 529674 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 177799 ; free virtual = 529674 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 17dfc4ae4 + +Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 177823 ; free virtual = 529697 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 189c2ca53 + +Time (s): cpu = 00:00:26 ; elapsed = 00:00:13 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 177656 ; free virtual = 529528 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 189c2ca53 + +Time (s): cpu = 00:00:27 ; elapsed = 00:00:13 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 177661 ; free virtual = 529532 +Phase 1 Placer Initialization | Checksum: 189c2ca53 + +Time (s): cpu = 00:00:27 ; elapsed = 00:00:13 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 177677 ; free virtual = 529549 + +Phase 2 Global Placement + +Phase 2.1 Floorplanning +Phase 2.1 Floorplanning | Checksum: 20bb1dab5 + +Time (s): cpu = 00:00:36 ; elapsed = 00:00:16 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 177664 ; free virtual = 529535 + +Phase 2.2 Update Timing before SLR Path Opt +Phase 2.2 Update Timing before SLR Path Opt | Checksum: 2286fe973 + +Time (s): cpu = 00:00:43 ; elapsed = 00:00:18 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 177631 ; free virtual = 529502 + +Phase 2.3 Post-Processing in Floorplanning +Phase 2.3 Post-Processing in Floorplanning | Checksum: 2286fe973 + +Time (s): cpu = 00:00:43 ; elapsed = 00:00:19 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 177627 ; free virtual = 529498 + +Phase 2.4 Global Placement Core + +Phase 2.4.1 UpdateTiming Before Physical Synthesis +Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 1a630b68c + +Time (s): cpu = 00:02:09 ; elapsed = 00:00:50 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 177186 ; free virtual = 529050 + +Phase 2.4.2 Physical Synthesis In Placer +INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 5152 LUT instances to create LUTNM shape +INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0 +INFO: [Physopt 32-1138] End 1 Pass. Optimized 2204 nets or LUTs. Breaked 0 LUT, combined 2204 existing LUTs and moved 0 existing LUT +INFO: [Physopt 32-65] No nets found for high-fanout optimization. +INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. +INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed. +INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. +INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. +INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed. +INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 177179 ; free virtual = 529043 + +Summary of Physical Synthesis Optimizations +============================================ + + +----------------------------------------------------------------------------------------------------------------------------------------------------------- +| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | +----------------------------------------------------------------------------------------------------------------------------------------------------------- +| LUT Combining | 0 | 2204 | 2204 | 0 | 1 | 00:00:02 | +| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Total | 0 | 2204 | 2204 | 0 | 4 | 00:00:03 | +----------------------------------------------------------------------------------------------------------------------------------------------------------- + + +Phase 2.4.2 Physical Synthesis In Placer | Checksum: 2a3298b58 + +Time (s): cpu = 00:02:20 ; elapsed = 00:00:56 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 177189 ; free virtual = 529055 +Phase 2.4 Global Placement Core | Checksum: 28e960a12 + +Time (s): cpu = 00:02:31 ; elapsed = 00:01:01 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 177310 ; free virtual = 529173 +Phase 2 Global Placement | Checksum: 28e960a12 + +Time (s): cpu = 00:02:31 ; elapsed = 00:01:01 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 177310 ; free virtual = 529173 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 2ba6ea6d8 + +Time (s): cpu = 00:02:38 ; elapsed = 00:01:03 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 177217 ; free virtual = 529080 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 2733bb972 + +Time (s): cpu = 00:02:51 ; elapsed = 00:01:08 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 177178 ; free virtual = 529039 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 27d09f09c + +Time (s): cpu = 00:02:52 ; elapsed = 00:01:09 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 177154 ; free virtual = 529016 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 280076c81 + +Time (s): cpu = 00:02:52 ; elapsed = 00:01:09 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 177163 ; free virtual = 529026 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 274e2b06e + +Time (s): cpu = 00:03:13 ; elapsed = 00:01:28 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 171132 ; free virtual = 528577 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 2462932d4 + +Time (s): cpu = 00:03:16 ; elapsed = 00:01:31 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 168560 ; free virtual = 528495 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 3265b2010 + +Time (s): cpu = 00:03:16 ; elapsed = 00:01:31 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 168074 ; free virtual = 528507 +Phase 3 Detail Placement | Checksum: 3265b2010 + +Time (s): cpu = 00:03:17 ; elapsed = 00:01:32 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 167522 ; free virtual = 528552 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Phase 4.1.1 Post Placement Optimization +Post Placement Optimization Initialization | Checksum: 260892d3c + +Phase 4.1.1.1 BUFG Insertion + +Starting Physical Synthesis Task + +Phase 1 Physical Synthesis Initialization +INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=1.277 | TNS=0.000 | +Phase 1 Physical Synthesis Initialization | Checksum: 19563dd38 + +Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 158247 ; free virtual = 528472 +INFO: [Place 46-33] Processed net platform/loader/SR[0], BUFG insertion was skipped due to placement/routing conflicts. +INFO: [Place 46-56] BUFG insertion identified 1 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 1, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. +Ending Physical Synthesis Task | Checksum: 27bd8317e + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 158117 ; free virtual = 528343 +Phase 4.1.1.1 BUFG Insertion | Checksum: 260892d3c + +Time (s): cpu = 00:03:49 ; elapsed = 00:01:44 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 158114 ; free virtual = 528340 + +Phase 4.1.1.2 Post Placement Timing Optimization +INFO: [Place 30-746] Post Placement Timing Summary WNS=1.277. For the most accurate timing information please run report_timing. +Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 29d6b1f6b + +Time (s): cpu = 00:03:51 ; elapsed = 00:01:44 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 158244 ; free virtual = 528470 + +Time (s): cpu = 00:03:51 ; elapsed = 00:01:44 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 158244 ; free virtual = 528470 +Phase 4.1 Post Commit Optimization | Checksum: 29d6b1f6b + +Time (s): cpu = 00:03:51 ; elapsed = 00:01:45 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 158244 ; free virtual = 528470 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 29d6b1f6b + +Time (s): cpu = 00:03:52 ; elapsed = 00:01:45 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 158264 ; free virtual = 528490 + +Phase 4.3 Placer Reporting + +Phase 4.3.1 Print Estimated Congestion +INFO: [Place 30-612] Post-Placement Estimated Congestion + ____________________________________________________ +| | Global Congestion | Short Congestion | +| Direction | Region Size | Region Size | +|___________|___________________|___________________| +| North| 1x1| 8x8| +|___________|___________________|___________________| +| South| 2x2| 8x8| +|___________|___________________|___________________| +| East| 2x2| 8x8| +|___________|___________________|___________________| +| West| 1x1| 2x2| +|___________|___________________|___________________| + +Phase 4.3.1 Print Estimated Congestion | Checksum: 29d6b1f6b + +Time (s): cpu = 00:03:53 ; elapsed = 00:01:46 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 158277 ; free virtual = 528503 +Phase 4.3 Placer Reporting | Checksum: 29d6b1f6b + +Time (s): cpu = 00:03:53 ; elapsed = 00:01:46 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 158276 ; free virtual = 528503 + +Phase 4.4 Final Placement Cleanup +Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 158276 ; free virtual = 528502 + +Time (s): cpu = 00:03:53 ; elapsed = 00:01:46 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 158276 ; free virtual = 528502 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 2e4b25a14 + +Time (s): cpu = 00:03:54 ; elapsed = 00:01:47 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 158228 ; free virtual = 528455 +Ending Placer Task | Checksum: 1eddddbab + +Time (s): cpu = 00:03:54 ; elapsed = 00:01:47 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 158251 ; free virtual = 528478 +30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +place_design: Time (s): cpu = 00:03:59 ; elapsed = 00:01:49 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 158247 ; free virtual = 528474 +# write_checkpoint -force $out/placed.dcp +INFO: [Timing 38-480] Writing timing data to binary archive. +Write ShapeDB Complete: Time (s): cpu = 00:00:00.78 ; elapsed = 00:00:00.17 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 158237 ; free virtual = 528481 +Wrote PlaceDB: Time (s): cpu = 00:00:08 ; elapsed = 00:00:03 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 158231 ; free virtual = 528563 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 158231 ; free virtual = 528563 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 158223 ; free virtual = 528556 +Wrote Netlist Cache: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.1 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 158232 ; free virtual = 528573 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 158232 ; free virtual = 528574 +Write Physdb Complete: Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 158232 ; free virtual = 528574 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/placed.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:16 ; elapsed = 00:00:11 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 158468 ; free virtual = 528777 +# phase PHYS_OPT +BOARD_PHASE PHYS_OPT +# phys_opt_design -directive Explore +Command: phys_opt_design -directive Explore +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: Explore + +Starting Initial Update Timing Task + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:05 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 158586 ; free virtual = 528895 +INFO: [Vivado_Tcl 4-2279] Estimated Timing Summary | WNS= 1.277 | TNS= 0.000 | +INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. All physical synthesis setup optimizations will be skipped. +INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified. +INFO: [Common 17-83] Releasing license: Implementation +6 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +phys_opt_design completed successfully +phys_opt_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:05 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 158586 ; free virtual = 528895 +# phase ROUTE +BOARD_PHASE ROUTE +# route_design -directive Explore +Command: route_design -directive Explore +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 8 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-270] Using Router directive 'Explore'. +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs + +Phase 1 Build RT Design +Checksum: PlaceDB: ee9480ea ConstDB: 0 ShapeSum: 4d76fb2b RouteDB: b1d25f96 +Post Restoration Checksum: NetGraph: 241726a8 | NumContArr: 5afb29d9 | Constraints: c2a8fa9d | Timing: c2a8fa9d +Phase 1 Build RT Design | Checksum: 2046445bb + +Time (s): cpu = 00:00:31 ; elapsed = 00:00:14 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 158879 ; free virtual = 529183 + +Phase 2 Router Initialization + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 2046445bb + +Time (s): cpu = 00:00:32 ; elapsed = 00:00:15 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 158875 ; free virtual = 529179 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 2046445bb + +Time (s): cpu = 00:00:32 ; elapsed = 00:00:15 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 158883 ; free virtual = 529188 + Number of Nodes with overlaps = 0 + +Phase 2.3 Update Timing +Phase 2.3 Update Timing | Checksum: 35e0f5c98 + +Time (s): cpu = 00:01:01 ; elapsed = 00:00:24 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 158963 ; free virtual = 529266 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.274 | TNS=0.000 | WHS=-1.411 | THS=-707.878| + + +Phase 2.4 Update Timing for Bus Skew + +Phase 2.4.1 Update Timing +Phase 2.4.1 Update Timing | Checksum: 2c11b980e + +Time (s): cpu = 00:01:22 ; elapsed = 00:00:29 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 159024 ; free virtual = 529325 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.274 | TNS=0.000 | WHS=-2.372 | THS=-68.356| + +Phase 2.4 Update Timing for Bus Skew | Checksum: 2d1538f6d + +Time (s): cpu = 00:01:22 ; elapsed = 00:00:29 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 159024 ; free virtual = 529325 + +Router Utilization Summary + Global Vertical Routing Utilization = 0 % + Global Horizontal Routing Utilization = 0 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 93600 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 93600 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Phase 2 Router Initialization | Checksum: 3833990d1 + +Time (s): cpu = 00:01:24 ; elapsed = 00:00:30 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 159025 ; free virtual = 529326 + +Phase 3 Global Routing +Phase 3 Global Routing | Checksum: 3833990d1 + +Time (s): cpu = 00:01:24 ; elapsed = 00:00:30 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 159025 ; free virtual = 529326 + +Phase 4 Initial Routing + +Phase 4.1 Initial Net Routing Pass +Phase 4.1 Initial Net Routing Pass | Checksum: 29558e5a8 + +Time (s): cpu = 00:01:38 ; elapsed = 00:00:33 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 159062 ; free virtual = 529363 +Phase 4 Initial Routing | Checksum: 29558e5a8 + +Time (s): cpu = 00:01:38 ; elapsed = 00:00:33 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 159062 ; free virtual = 529364 + +Phase 5 Rip-up And Reroute + +Phase 5.1 Global Iteration 0 + Number of Nodes with overlaps = 14471 + Number of Nodes with overlaps = 1519 + Number of Nodes with overlaps = 378 + Number of Nodes with overlaps = 101 + Number of Nodes with overlaps = 31 + Number of Nodes with overlaps = 9 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 0 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.274 | TNS=0.000 | WHS=N/A | THS=N/A | + +Phase 5.1 Global Iteration 0 | Checksum: 1bcb17191 + +Time (s): cpu = 00:02:48 ; elapsed = 00:01:12 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 158636 ; free virtual = 529127 + +Phase 5.2 Global Iteration 1 + Number of Nodes with overlaps = 10 + Number of Nodes with overlaps = 13 + Number of Nodes with overlaps = 12 + Number of Nodes with overlaps = 7 + Number of Nodes with overlaps = 4 + Number of Nodes with overlaps = 0 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.274 | TNS=0.000 | WHS=N/A | THS=N/A | + +Phase 5.2 Global Iteration 1 | Checksum: 28fd5ecfa + +Time (s): cpu = 00:03:00 ; elapsed = 00:01:18 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 157226 ; free virtual = 527719 +Phase 5 Rip-up And Reroute | Checksum: 28fd5ecfa + +Time (s): cpu = 00:03:00 ; elapsed = 00:01:18 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 157211 ; free virtual = 527698 + +Phase 6 Delay and Skew Optimization + +Phase 6.1 Delay CleanUp + +Phase 6.1.1 Update Timing +Phase 6.1.1 Update Timing | Checksum: 2fec1ab35 + +Time (s): cpu = 00:03:09 ; elapsed = 00:01:21 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 157210 ; free virtual = 527697 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.274 | TNS=0.000 | WHS=N/A | THS=N/A | + +Phase 6.1 Delay CleanUp | Checksum: 216e3ec42 + +Time (s): cpu = 00:03:10 ; elapsed = 00:01:21 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 157202 ; free virtual = 527689 + +Phase 6.2 Clock Skew Optimization +Phase 6.2 Clock Skew Optimization | Checksum: 216e3ec42 + +Time (s): cpu = 00:03:10 ; elapsed = 00:01:21 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 157186 ; free virtual = 527674 +Phase 6 Delay and Skew Optimization | Checksum: 216e3ec42 + +Time (s): cpu = 00:03:10 ; elapsed = 00:01:21 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 157195 ; free virtual = 527683 + +Phase 7 Post Hold Fix + +Phase 7.1 Hold Fix Iter +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.274 | TNS=0.000 | WHS=0.010 | THS=0.000 | + +Phase 7.1 Hold Fix Iter | Checksum: 22ae53d4c + +Time (s): cpu = 00:03:20 ; elapsed = 00:01:23 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 157080 ; free virtual = 527568 +Phase 7 Post Hold Fix | Checksum: 22ae53d4c + +Time (s): cpu = 00:03:20 ; elapsed = 00:01:23 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 157072 ; free virtual = 527560 + +Phase 8 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 21.9441 % + Global Horizontal Routing Utilization = 26.5389 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Phase 8 Route finalize | Checksum: 22ae53d4c + +Time (s): cpu = 00:03:21 ; elapsed = 00:01:23 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 157048 ; free virtual = 527536 + +Phase 9 Verifying routed nets + + Verification completed successfully +Phase 9 Verifying routed nets | Checksum: 22ae53d4c + +Time (s): cpu = 00:03:22 ; elapsed = 00:01:24 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 157055 ; free virtual = 527542 + +Phase 10 Depositing Routes +Phase 10 Depositing Routes | Checksum: 1f66f8eea + +Time (s): cpu = 00:03:28 ; elapsed = 00:01:27 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 156293 ; free virtual = 526781 + +Phase 11 Post Process Routing +Phase 11 Post Process Routing | Checksum: 1f66f8eea + +Time (s): cpu = 00:03:28 ; elapsed = 00:01:27 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 156291 ; free virtual = 526779 + +Phase 12 Post Router Timing +INFO: [Route 35-20] Post Routing Timing Summary | WNS=1.276 | TNS=0.000 | WHS=0.012 | THS=0.000 | + +Phase 12 Post Router Timing | Checksum: 1e1452a1b + +Time (s): cpu = 00:03:54 ; elapsed = 00:01:33 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 156752 ; free virtual = 527434 +INFO: [Route 35-61] The design met the timing requirement. +Total Elapsed time in route_design: 93.29 secs + +Phase 13 Post-Route Event Processing +Phase 13 Post-Route Event Processing | Checksum: 171b86a1b + +Time (s): cpu = 00:03:55 ; elapsed = 00:01:34 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 156327 ; free virtual = 526927 +INFO: [Route 35-16] Router Completed Successfully +Ending Routing Task | Checksum: 171b86a1b + +Time (s): cpu = 00:03:56 ; elapsed = 00:01:35 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 156233 ; free virtual = 526777 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +16 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:04:02 ; elapsed = 00:01:38 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 156296 ; free virtual = 526902 +# write_checkpoint -force $out/routed.dcp +INFO: [Timing 38-480] Writing timing data to binary archive. +Write ShapeDB Complete: Time (s): cpu = 00:00:00.78 ; elapsed = 00:00:00.17 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 155980 ; free virtual = 526683 +Wrote PlaceDB: Time (s): cpu = 00:00:08 ; elapsed = 00:00:03 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 155746 ; free virtual = 526530 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 155746 ; free virtual = 526530 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00.98 ; elapsed = 00:00:00.61 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 155799 ; free virtual = 526599 +Wrote Netlist Cache: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.09 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 155785 ; free virtual = 526593 +Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 155785 ; free virtual = 526594 +Write Physdb Complete: Time (s): cpu = 00:00:09 ; elapsed = 00:00:04 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 155785 ; free virtual = 526594 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/routed.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:25 ; elapsed = 00:00:14 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 156308 ; free virtual = 527072 +# phase REPORT +BOARD_PHASE REPORT +# report_utilization -file $out/routed-utilization.rpt +# report_utilization -hierarchical -file $out/routed-hierarchy.rpt +# report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -file $out/routed-timing.rpt +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. +report_timing_summary: Time (s): cpu = 00:00:24 ; elapsed = 00:00:06 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 157307 ; free virtual = 528071 +# report_route_status -file $out/route-status.rpt +# report_drc -file $out/drc.rpt +Command: report_drc -file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/drc.rpt +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 8 threads +INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/drc.rpt. +report_drc completed successfully +INFO: [Timing 38-91] UpdateTimingParams: No interconnect No Cell Dly, Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +INFO: [Timing 38-314] The report_cdc command only analyzes and reports clock domain crossing paths where clocks have been defined on both source and destination sides. Ports with no input delay constraint are skipped. Please run check_timing to verify there are no missing clock definitions in your design, nor any unconstrained input port. +# set cdc [report_cdc -details -return_string] +# set f [open $out/cdc.rpt w] +# puts $f $cdc +# close $f +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +# set skew [report_bus_skew -return_string] +# set f [open $out/bus-skew.rpt w] +# puts $f $skew +# close $f +# report_methodology -file $out/methodology.rpt +Command: report_methodology -file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/methodology.rpt +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 8 threads +INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/methodology.rpt. +report_methodology completed successfully +report_methodology: Time (s): cpu = 00:00:32 ; elapsed = 00:00:10 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 158293 ; free virtual = 529054 +# report_io -file $out/io.rpt +report_io: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.26 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 158297 ; free virtual = 529059 +# report_clocks -file $out/clocks.rpt +INFO: [Timing 38-35] Done setting XDC timing constraints. +# check_timing -verbose -file $out/check-timing.rpt +# if {[regexp {CDC-[0-9]+\s+Critical} $cdc]} {error "Critical CDC findings; see cdc.rpt"} +# if {[string match *VIOLATED* $skew]} {error "Bus skew failed; see bus-skew.rpt"} +# foreach kind {max min} { +# set paths [get_timing_paths -delay_type $kind -max_paths 1] +# if {[llength $paths]==0} {error "Missing $kind timing paths"} +# if {[get_property SLACK [lindex $paths 0]]<0} {error "$kind timing failed"} +# } +# if {![report_route_status -boolean_check ROUTED_FULLY]} {error "Routing incomplete"} +# if {[report_route_status -boolean_check ERRORS_IN_ROUTES]} {error "Routing errors"} +# set errors [get_drc_violations -quiet -filter {SEVERITY == Error || SEVERITY == {Critical Warning}}] +# if {[llength $errors]} {error "DRC errors/critical warnings: $errors"} +# phase BITSTREAM +BOARD_PHASE BITSTREAM +# set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +# write_bitstream -force $out/toy_a7.bit +Command: write_bitstream -force /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/toy_a7.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +Running DRC as a precondition to command write_bitstream +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 8 threads +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +INFO: [Common 17-14] Message 'DRC DPIP-1' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +INFO: [Common 17-14] Message 'DRC DPOP-1' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/rowSkip_reg multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/rowSkip_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +INFO: [Common 17-14] Message 'DRC DPOP-2' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [DRC REQP-1709] Clock output buffering: PLLE2_ADV connectivity violation. The signal ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out on the ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 pin of ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i does not drive the same kind of BUFFER load as the other CLKOUT pins. Routing from the different buffer types will not be phase aligned. +WARNING: [DRC RTSTAT-10] No routable loads: 45 net(s) have no routable loads. The problem bus(es) and/or net(s) are memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0]... and (the first 15 of 25 listed). +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 360 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Bitstream compression saved 7411584 bits. +Writing bitstream /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/toy_a7.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-83] Releasing license: Implementation +12 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:45 ; elapsed = 00:00:25 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 158516 ; free virtual = 529274 +# phase COMPLETE +BOARD_PHASE COMPLETE +# puts "PASS BOARD_PLACE_ROUTE_TIMING_BITSTREAM: engineering Rev E target; flash=$flash; this build does not validate physical boot" +PASS BOARD_PLACE_ROUTE_TIMING_BITSTREAM: engineering Rev E target; flash=0; this build does not validate physical boot +INFO: [Common 17-206] Exiting Vivado at Tue Oct 13 01:32:55 2026... diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/drc.rpt b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/drc.rpt new file mode 100644 index 0000000..1c86437 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/drc.rpt @@ -0,0 +1,1855 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Tue Oct 13 01:32:07 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_drc -file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/drc.rpt +| Design : toy_a7_top +| Device : xc7a100tcsg324-1 +| Speed File : -1 +| Design State : Fully Routed +------------------------------------------------------------------------------------------------------------------------------------------------ + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: toy_a7_top + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 360 ++-----------+----------+------------------------+------------+ +| Rule | Severity | Description | Violations | ++-----------+----------+------------------------+------------+ +| DPIP-1 | Warning | Input pipelining | 152 | +| DPOP-1 | Warning | PREG Output pipelining | 102 | +| DPOP-2 | Warning | MREG Output pipelining | 104 | +| REQP-1709 | Warning | Clock output buffering | 1 | +| RTSTAT-10 | Warning | No routable loads | 1 | ++-----------+----------+------------------------+------------+ + +2. REPORT DETAILS +----------------- +DPIP-1#1 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#2 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#3 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#4 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#5 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#6 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#7 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#8 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#9 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#10 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#11 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#12 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#13 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#14 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#15 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#16 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#17 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#18 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#19 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#20 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#21 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#22 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#23 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#24 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#25 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#26 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#27 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#28 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#29 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#30 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#31 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#32 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#33 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#34 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#35 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#36 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#37 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#38 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#39 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#40 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#41 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#42 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#43 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#44 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#45 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#46 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#47 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#48 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#49 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#50 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#51 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#52 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#53 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#54 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#55 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#56 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#57 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#58 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#59 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#60 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#61 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#62 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#63 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#64 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#65 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#66 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#67 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#68 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#69 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#70 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#71 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#72 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#73 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#74 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#75 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#76 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#77 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#78 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#79 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#80 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#81 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#82 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#83 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#84 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#85 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#86 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#87 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#88 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#89 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#90 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#91 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#92 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#93 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#94 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#95 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#96 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#97 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#98 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#99 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#100 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#101 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#102 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#103 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#104 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#105 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#106 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#107 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#108 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#109 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#110 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#111 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#112 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#113 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#114 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#115 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#116 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#117 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#118 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#119 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#120 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#121 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#122 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#123 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#124 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#125 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#126 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#127 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#128 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#129 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#130 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#131 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#132 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#133 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#134 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#135 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#136 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#137 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#138 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#139 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#140 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#141 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#142 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#143 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#144 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#145 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#146 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#147 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#148 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#149 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#150 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#151 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#152 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/rowSkip_reg input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/rowSkip_reg/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPOP-1#1 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#2 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#3 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#4 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#5 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#6 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#7 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#8 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#9 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#10 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#11 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#12 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#13 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#14 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#15 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#16 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#17 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#18 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#19 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#20 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#21 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#22 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#23 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#24 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#25 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#26 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#27 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#28 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#29 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#30 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#31 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#32 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#33 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#34 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#35 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#36 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#37 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#38 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#39 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#40 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#41 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#42 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#43 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#44 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#45 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#46 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#47 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#48 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#49 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#50 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#51 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#52 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#53 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#54 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#55 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#56 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#57 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#58 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#59 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#60 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#61 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#62 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#63 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#64 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#65 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#66 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#67 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#68 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#69 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#70 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#71 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#72 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#73 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#74 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#75 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#76 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#77 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#78 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#79 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#80 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#81 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#82 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#83 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#84 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#85 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#86 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#87 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#88 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#89 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#90 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#91 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#92 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#93 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#94 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#95 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#96 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#97 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#98 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#99 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#100 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#101 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#102 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__3 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__3/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-2#1 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#2 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#3 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#4 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#5 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#6 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#7 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#8 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#9 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#10 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#11 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#12 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#13 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#14 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#15 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#16 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#17 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#18 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#19 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#20 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#21 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#22 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#23 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#24 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#25 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#26 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#27 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#28 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#29 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#30 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#31 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#32 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#33 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#34 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#35 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#36 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#37 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#38 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#39 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#40 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#41 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#42 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#43 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#44 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#45 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#46 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#47 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#48 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#49 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#50 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#51 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#52 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#53 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#54 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#55 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#56 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#57 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#58 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#59 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#60 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#61 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#62 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#63 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#64 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#65 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#66 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#67 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#68 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#69 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#70 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#71 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#72 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#73 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#74 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#75 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#76 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#77 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#78 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#79 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#80 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#81 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#82 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#83 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#84 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#85 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#86 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#87 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#88 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#89 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#90 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#91 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/rowSkip_reg multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/rowSkip_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#92 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#93 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#94 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#95 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#96 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#97 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#98 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#99 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#100 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#101 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__3 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__3/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#102 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#103 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#104 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +REQP-1709#1 Warning +Clock output buffering +PLLE2_ADV connectivity violation. The signal ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out on the ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 pin of ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i does not drive the same kind of BUFFER load as the other CLKOUT pins. Routing from the different buffer types will not be phase aligned. +Related violations: + +RTSTAT-10#1 Warning +No routable loads +45 net(s) have no routable loads. The problem bus(es) and/or net(s) are memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0] + (the first 15 of 25 listed). +Related violations: + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/io.rpt b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/io.rpt new file mode 100644 index 0000000..260d4d3 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/io.rpt @@ -0,0 +1,366 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Tue Oct 13 01:32:23 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_io -file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/io.rpt +| Design : toy_a7_top +| Device : xc7a100t +| Speed File : -1 +| Package : csg324 +| Package Version : FINAL 2012-07-17 +| Package Pin Delay Version : VERS. 2.0 2012-07-17 +----------------------------------------------------------------------------------------------------------------------------------------------------------- + +IO Information + +Table of Contents +----------------- +1. Summary +2. IO Assignments by Package Pin + +1. Summary +---------- + ++---------------+ +| Total User IO | ++---------------+ +| 62 | ++---------------+ + + +2. IO Assignments by Package Pin +-------------------------------- + ++------------+---------------+------------+------------------------------+-------------+--------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+----------+------------------+--------------+-------------------+--------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization | ++------------+---------------+------------+------------------------------+-------------+--------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+----------+------------------+--------------+-------------------+--------------+ +| A1 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A3 | | High Range | IO_L8N_T1_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A4 | | High Range | IO_L8P_T1_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | | +| A5 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A6 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | | +| A7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| A8 | sw0 | High Range | IO_L12N_T1_MRCC_16 | INPUT | LVCMOS33 | 16 | | | | NONE | | FIXED | | | | NONE | | | | +| A9 | uart_txd_in | High Range | IO_L14N_T2_SRCC_16 | INPUT | LVCMOS33 | 16 | | | | NONE | | FIXED | | | | NONE | | | | +| A10 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A11 | | High Range | IO_L4N_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A13 | | High Range | IO_L9P_T1_DQS_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | | +| A14 | | High Range | IO_L9N_T1_DQS_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A15 | | High Range | IO_L8P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | | +| A16 | | High Range | IO_L8N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| A18 | | High Range | IO_L10N_T1_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B1 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B2 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B3 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B4 | | High Range | IO_L7N_T1_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B6 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B7 | | High Range | IO_L2P_T0_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B8 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B9 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B10 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | | +| B11 | | High Range | IO_L4P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| B12 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B13 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B14 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B16 | | High Range | IO_L7P_T1_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B17 | | High Range | IO_L7N_T1_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B18 | | High Range | IO_L10P_T1_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C1 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| C2 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| C3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| C4 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | | +| C5 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | | +| C6 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | | +| C7 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| C8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C9 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C10 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C11 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C12 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C13 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| C14 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | | +| C15 | | High Range | IO_L12N_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| C16 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | | +| C17 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | | +| C18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D2 | | High Range | IO_L14N_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D3 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D4 | | High Range | IO_L11N_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D5 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D6 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| D7 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| D8 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| D9 | btn0 | High Range | IO_L6N_T0_VREF_16 | INPUT | LVCMOS33 | 16 | | | | NONE | | FIXED | | | | NONE | | | | +| D10 | uart_rxd_out | High Range | IO_L19N_T3_VREF_16 | OUTPUT | LVCMOS33 | 16 | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| D11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D12 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| D13 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| D14 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | | +| D15 | | High Range | IO_L12P_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| D16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| D17 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | | +| D18 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | | +| E1 | | High Range | IO_L18N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| E2 | | High Range | IO_L14P_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| E3 | CLK100MHZ | High Range | IO_L12P_T1_MRCC_35 | INPUT | LVCMOS33 | 35 | | | | NONE | | FIXED | | | | NONE | | | | +| E4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E5 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | | +| E6 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | | +| E7 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| E8 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | | +| E9 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | | +| E10 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | | +| E11 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | | +| E12 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | | +| E13 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | | +| E14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E15 | | High Range | IO_L11P_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| E16 | | High Range | IO_L11N_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| E17 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | | +| E18 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| F1 | | High Range | IO_L18P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| F2 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| F3 | | High Range | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| F4 | | High Range | IO_L13P_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| F5 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | | +| F6 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| F9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F10 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| F11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| F13 | | High Range | IO_L5P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | | +| F14 | | High Range | IO_L5N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | | +| F15 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| F16 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| F17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F18 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | | +| G1 | | High Range | IO_L17N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| G2 | | High Range | IO_L15N_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| G3 | | High Range | IO_L20N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| G4 | | High Range | IO_L20P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| G5 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| G6 | | High Range | IO_L19P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| G7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G13 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | | +| G14 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| G15 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| G16 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| G17 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | | +| G18 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | | +| H1 | | High Range | IO_L17P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| H2 | | High Range | IO_L15P_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| H3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H4 | | High Range | IO_L21N_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| H5 | led[0] | High Range | IO_L24N_T3_35 | OUTPUT | LVCMOS33 | 35 | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| H6 | | High Range | IO_L24P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| H9 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| H10 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| H13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H14 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| H15 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| H16 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| H17 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | | +| H18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| J1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| J2 | | High Range | IO_L22N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| J3 | | High Range | IO_L22P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| J4 | | High Range | IO_L21P_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| J5 | led[1] | High Range | IO_25_35 | OUTPUT | LVCMOS33 | 35 | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| J6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J9 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | | +| J10 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | | +| J11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J13 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | | +| J14 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | | | | | +| J15 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | | +| J16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J17 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| J18 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| K1 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| K2 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| K3 | ddr3_dq[2] | High Range | IO_L2P_T0_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| K4 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.35 | | | | | | | | | +| K5 | ddr3_dq[0] | High Range | IO_L5P_T0_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| K6 | ddr3_reset_n | High Range | IO_0_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| K9 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | | +| K10 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | | +| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| K13 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | | +| K14 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| K15 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | | +| K16 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | | +| K17 | flash_mosi | High Range | IO_L1P_T0_D00_MOSI_14 | OUTPUT | LVCMOS33 | 14 | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| K18 | flash_miso | High Range | IO_L1N_T0_D01_DIN_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| L1 | ddr3_dm[0] | High Range | IO_L1P_T0_34 | TRISTATE | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| L2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L3 | ddr3_dq[1] | High Range | IO_L2N_T0_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| L4 | ddr3_dq[6] | High Range | IO_L5N_T0_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| L5 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| L6 | ddr3_dq[3] | High Range | IO_L6P_T0_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| L7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L9 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| L10 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| L11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L13 | flash_cs_n | High Range | IO_L6P_T0_FCS_B_14 | OUTPUT | LVCMOS33 | 14 | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| L14 | flash_wp_n | High Range | IO_L2P_T0_D02_14 | OUTPUT | LVCMOS33 | 14 | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| L15 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| L16 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | | +| L17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| L18 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | | +| M1 | ddr3_dq[5] | High Range | IO_L1N_T0_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| M2 | ddr3_dq[7] | High Range | IO_L4N_T0_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| M3 | ddr3_dq[4] | High Range | IO_L4P_T0_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| M4 | ddr3_cas_n | High Range | IO_L16P_T2_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| M5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M6 | ddr3_addr[1] | High Range | IO_L18P_T2_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| M13 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| M14 | flash_hold_n | High Range | IO_L2N_T0_D03_14 | OUTPUT | LVCMOS33 | 14 | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| M15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M16 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | | +| M17 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | | +| M18 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | | +| N1 | ddr3_dqs_n[0] | High Range | IO_L3N_T0_DQS_34 | BIDIR | DIFF_SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| N2 | ddr3_dqs_p[0] | High Range | IO_L3P_T0_DQS_34 | BIDIR | DIFF_SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| N3 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.35 | | | | | | | | | +| N4 | ddr3_addr[2] | High Range | IO_L16N_T2_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| N5 | ddr3_cke[0] | High Range | IO_L13P_T2_MRCC_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| N6 | ddr3_addr[4] | High Range | IO_L18N_T2_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| N7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| N14 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | | +| N15 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N16 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N17 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| N18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P2 | ddr3_ba[2] | High Range | IO_L15P_T2_DQS_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| P3 | ddr3_ras_n | High Range | IO_L14N_T2_SRCC_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| P4 | ddr3_ba[1] | High Range | IO_L14P_T2_SRCC_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| P5 | ddr3_we_n | High Range | IO_L13N_T2_MRCC_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| P6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.35 | | | | | | | | | +| P7 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | | +| P8 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | 3.30 | | | | | | | | | +| P9 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | | +| P10 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | | +| P11 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | | +| P12 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | | +| P13 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | | +| P14 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | | +| P15 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| P16 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| P17 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| P18 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | | +| R1 | ddr3_ba[0] | High Range | IO_L17P_T2_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| R2 | ddr3_addr[0] | High Range | IO_L15N_T2_DQS_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| R3 | ddr3_dq[15] | High Range | IO_L11P_T1_SRCC_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| R4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R5 | ddr3_odt[0] | High Range | IO_L19N_T3_VREF_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| R6 | ddr3_addr[10] | High Range | IO_L19P_T3_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| R7 | ddr3_addr[5] | High Range | IO_L23P_T3_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| R8 | ddr3_addr[8] | High Range | IO_L24P_T3_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| R9 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | 3.30 | | | | | | | | | +| R10 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | | +| R11 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | | +| R12 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | | +| R13 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | | +| R14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R15 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| R16 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| R17 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| R18 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | | +| T1 | ddr3_addr[3] | High Range | IO_L17N_T2_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| T2 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.35 | | | | | | | | | +| T3 | ddr3_dq[13] | High Range | IO_L11N_T1_SRCC_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| T4 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T5 | ddr3_dq[9] | High Range | IO_L12P_T1_MRCC_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| T6 | ddr3_addr[12] | High Range | IO_L23N_T3_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T8 | ddr3_addr[13] | High Range | IO_L24N_T3_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| T9 | led[2] | High Range | IO_L24P_T3_A01_D17_14 | OUTPUT | LVCMOS33 | 14 | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| T10 | led[3] | High Range | IO_L24N_T3_A00_D16_14 | OUTPUT | LVCMOS33 | 14 | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| T11 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | | +| T12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| T13 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | | +| T14 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| T15 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| T16 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T18 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | | +| U1 | ddr3_dm[1] | High Range | IO_L7P_T1_34 | TRISTATE | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U2 | ddr3_dqs_p[1] | High Range | IO_L9P_T1_DQS_34 | BIDIR | DIFF_SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U3 | ddr3_dq[14] | High Range | IO_L8N_T1_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| U4 | ddr3_dq[10] | High Range | IO_L8P_T1_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| U5 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.35 | | | | | | | | | +| U6 | ddr3_addr[11] | High Range | IO_L22N_T3_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U7 | ddr3_addr[7] | High Range | IO_L22P_T3_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U8 | ddr3_cs_n[0] | High Range | IO_25_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U9 | ddr3_ck_p[0] | High Range | IO_L21P_T3_DQS_34 | OUTPUT | DIFF_SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U11 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| U12 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | | +| U13 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | | +| U14 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | | +| U15 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| U16 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | | +| U17 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | | +| U18 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | | +| V1 | ddr3_dq[12] | High Range | IO_L7N_T1_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| V2 | ddr3_dqs_n[1] | High Range | IO_L9N_T1_DQS_34 | BIDIR | DIFF_SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| V3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V4 | ddr3_dq[8] | High Range | IO_L10N_T1_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| V5 | ddr3_dq[11] | High Range | IO_L10P_T1_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| V6 | ddr3_addr[6] | High Range | IO_L20N_T3_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| V7 | ddr3_addr[9] | High Range | IO_L20P_T3_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| V8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.35 | | | | | | | | | +| V9 | ddr3_ck_n[0] | High Range | IO_L21N_T3_DQS_34 | OUTPUT | DIFF_SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| V10 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| V11 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | | +| V12 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | | +| V13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V14 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | | +| V15 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| V16 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | | +| V17 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | | +| V18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | ++------------+---------------+------------+------------------------------+-------------+--------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+----------+------------------+--------------+-------------------+--------------+ +* Default value +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/ip-status.rpt b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/ip-status.rpt new file mode 100644 index 0000000..c7cc607 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/ip-status.rpt @@ -0,0 +1,33 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Tue Oct 13 01:09:57 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_ip_status +--------------------------------------------------------------------------------------------------------------------------------------------- + +IP Status Summary + +1. Project IP Status +-------------------- +Your project uses 2 IP. Some of these IP may have undergone changes in this release of the software. Please review the recommended actions. + +More information on the Xilinx versioning policy is available at www.xilinx.com. + +Project IP Instances ++---------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| Instance Name | Status | Recommendation | Change | IP Name | IP | New Version | New | Original Part | +| | | | Log | | Version | | License | | ++---------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| arty_ddr3 | Up-to-date | No changes required | *(1) | Memory Interface | 4.2 | 4.2 (Rev. 1) | Included | xc7a100tcsg324-1 | +| | | | | Generator (MIG 7 | (Rev. | | | | +| | | | | Series) | 1) | | | | ++---------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| toy_axi_cdc | Up-to-date | No changes required | *(2) | AXI Clock | 2.1 | 2.1 (Rev. 30) | Included | xc7a100tcsg324-1 | +| | | | | Converter | (Rev. | | | | +| | | | | | 30) | | | | ++---------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +*(1) /data0/tools/Xilinx/Vivado/2024.1/data/ip/xilinx/mig_7series_v4_2/doc/mig_7series_v4_2_changelog.txt +*(2) /data0/tools/Xilinx/Vivado/2024.1/data/ip/xilinx/axi_clock_converter_v2_1/doc/axi_clock_converter_v2_1_changelog.txt + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/launcher.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/launcher.log new file mode 100644 index 0000000..e69de29 diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/methodology.rpt b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/methodology.rpt new file mode 100644 index 0000000..77d8799 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/methodology.rpt @@ -0,0 +1,389 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Tue Oct 13 01:32:23 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_methodology -file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/methodology.rpt +| Design : toy_a7_top +| Device : xc7a100tcsg324-1 +| Speed File : -1 +| Design State : Fully Routed +---------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Report Methodology + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: toy_a7_top + Floorplan: design_1 + Design limits: + Max violations: + Violations found: 65 ++-----------+----------+-----------------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++-----------+----------+-----------------------------------------------------------+------------+ +| LUTAR-1 | Warning | LUT drives async reset alert | 2 | +| SYNTH-5 | Warning | Mapped onto distributed RAM because of timing constraints | 16 | +| SYNTH-9 | Warning | Small multiplier | 5 | +| SYNTH-10 | Warning | Wide multiplier | 21 | +| SYNTH-16 | Warning | Address collision | 1 | +| TIMING-10 | Warning | Missing property on synchronizer | 1 | +| ULMTCS-1 | Warning | Control Sets use limits recommend reduction | 1 | +| XDCB-5 | Warning | Runtime inefficient way to find pin objects | 2 | +| REQP-1959 | Advisory | connects_SERDES_RST_driver_not_FF | 16 | ++-----------+----------+-----------------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +LUTAR-1#1 Warning +LUT drives async reset alert +LUT cell ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rstdiv2_sync_r[11]_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__7/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__8/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__9/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[0]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[10]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[11]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[1]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[2]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[3]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[4]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[5]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[6]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[7]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[8]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[9]/PRE + (the first 15 of 32 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#2 Warning +LUT drives async reset alert +LUT cell platform/loader/in_pipe_v_i_1__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) platform/chip/system/clint_domain/intsource/reg_0/reg_0_reg[0]/CLR, +platform/chip/system/clint_domain/intsource/reg_0/reg_0_reg[1]/CLR, +platform/chip/system/ibus_intsource/reg_0__0/reg_0_reg/CLR, +platform/chip/system/plic_domain/intsource/reg_0/reg_0_reg/CLR +platform/chip/system/plic_domain/intsource_1/reg_0/reg_0_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +SYNTH-5#1 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_0_127_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#2 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_0_127_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#3 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_0_127_2_2 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#4 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_0_127_3_3 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#5 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_0_127_4_4 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#6 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_0_127_5_5 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#7 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_0_127_6_6 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#8 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_0_127_7_7 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#9 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_128_255_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#10 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_128_255_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#11 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_128_255_2_2 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#12 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_128_255_3_3 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#13 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_128_255_4_4 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#14 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_128_255_5_5 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#15 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_128_255_6_6 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#16 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_128_255_7_7 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-9#1 Warning +Small multiplier +Detected multiplier at sharedFma/fma/product_pipe_b_reg[11]_i_1 of size 20x3, it is implemented as LUTs due to its small size. To force the multiplier onto a DSP block, use the USE_DSP48 attribute. +Related violations: + +SYNTH-9#2 Warning +Small multiplier +Detected multiplier at sharedFma/fma/product_pipe_b_reg[15]_i_1 of size 20x3, it is implemented as LUTs due to its small size. To force the multiplier onto a DSP block, use the USE_DSP48 attribute. +Related violations: + +SYNTH-9#3 Warning +Small multiplier +Detected multiplier at sharedFma/fma/product_pipe_b_reg[19]_i_1 of size 20x3, it is implemented as LUTs due to its small size. To force the multiplier onto a DSP block, use the USE_DSP48 attribute. +Related violations: + +SYNTH-9#4 Warning +Small multiplier +Detected multiplier at sharedFma/fma/product_pipe_b_reg[3]_i_1 of size 20x3, it is implemented as LUTs due to its small size. To force the multiplier onto a DSP block, use the USE_DSP48 attribute. +Related violations: + +SYNTH-9#5 Warning +Small multiplier +Detected multiplier at sharedFma/fma/product_pipe_b_reg[7]_i_1 of size 20x3, it is implemented as LUTs due to its small size. To force the multiplier onto a DSP block, use the USE_DSP48 attribute. +Related violations: + +SYNTH-10#1 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1 of size 23x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#2 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__0 of size 18x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#3 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1 of size 23x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#4 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10 of size 18x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#5 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11 of size 18x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#6 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__2 of size 18x23, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#7 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3 of size 18x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#8 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__4 of size 18x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#9 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5 of size 18x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#10 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__6 of size 18x23, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#11 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7 of size 18x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#12 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8 of size 18x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#13 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__9 of size 18x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#14 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0 of size 18x20, it is decomposed from a wide multipler into 10 DSP blocks. +Related violations: + +SYNTH-10#15 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__0 of size 20x18, it is decomposed from a wide multipler into 10 DSP blocks. +Related violations: + +SYNTH-10#16 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__1 of size 18x20, it is decomposed from a wide multipler into 10 DSP blocks. +Related violations: + +SYNTH-10#17 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__2 of size 18x18, it is decomposed from a wide multipler into 10 DSP blocks. +Related violations: + +SYNTH-10#18 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__3 of size 18x18, it is decomposed from a wide multipler into 10 DSP blocks. +Related violations: + +SYNTH-10#19 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__4 of size 18x18, it is decomposed from a wide multipler into 10 DSP blocks. +Related violations: + +SYNTH-10#20 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg__0 of size 20x18, it is decomposed from a wide multipler into 10 DSP blocks. +Related violations: + +SYNTH-10#21 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg__1 of size 18x18, it is decomposed from a wide multipler into 10 DSP blocks. +Related violations: + +SYNTH-16#1 Warning +Address collision +Block RAM platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/mshrs/sdq_ext/Memory_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended. +Related violations: + +TIMING-10#1 Warning +Missing property on synchronizer +One or more logic synchronizer has been detected between 2 clock domains but the synchronizer does not have the property ASYNC_REG defined on one or both registers. It is recommended to run report_cdc for a complete and detailed CDC coverage +Related violations: + +ULMTCS-1#1 Warning +Control Sets use limits recommend reduction +This design uses 1256 control sets (vs. available limit of 15850, determined by 1 control set per CLB). This exceeds the control set use guideline of 7.5 percent. This is at a level where reduction is RECOMMENDED (see UG949). Use report_control_sets to get more details. +Related violations: + +XDCB-5#1 Warning +Runtime inefficient way to find pin objects +The option '-to : [get_pins -hier -filter {NAME =~ *rx_meta_reg/D}]' of constraint 'set_false_path' uses inefficient query to find pin objects (see constraint position '12' in the Timing Constraint window in Vivado IDE). To reduce runtime, it is recommended to get the pins through the cell objects. Please refer to Using Constraints Guide (Constraints Efficiency). An example of optimal query is: get_pins -filter {REF_PIN_NAME=~yy*} -of_objects [get_cells -hierarchical xx*]. +Current XDC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/arty_a7.xdc (Line: 18) +Related violations: + +XDCB-5#2 Warning +Runtime inefficient way to find pin objects +The option '-to : [get_pins -hier -include_replicated_objects -filter {NAME =~ *temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[*]/D}]' of constraint 'set_max_delay' uses inefficient query to find pin objects (see constraint position '6' in the Timing Constraint window in Vivado IDE). To reduce runtime, it is recommended to get the pins through the cell objects. Please refer to Using Constraints Guide (Constraints Efficiency). An example of optimal query is: get_pins -filter {REF_PIN_NAME=~yy*} -of_objects [get_cells -hierarchical xx*]. +Current XDC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc (Line: 356) +Related violations: + +REQP-1959#1 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#2 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#3 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[3].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#4 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[4].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#5 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[5].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#6 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[6].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#7 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[7].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#8 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#9 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#10 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#11 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[3].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#12 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[4].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#13 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[5].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#14 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[6].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#15 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[7].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#16 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/opt-utilization.rpt b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/opt-utilization.rpt new file mode 100644 index 0000000..c0c1ecf --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/opt-utilization.rpt @@ -0,0 +1,233 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Tue Oct 13 01:27:55 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_utilization -file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/opt-utilization.rpt +| Design : toy_a7_top +| Device : xc7a100tcsg324-1 +| Speed File : -1 +| Design State : Optimized +-------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++----------------------------+-------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++----------------------------+-------+-------+------------+-----------+-------+ +| Slice LUTs* | 56386 | 0 | 0 | 63400 | 88.94 | +| LUT as Logic | 52343 | 0 | 0 | 63400 | 82.56 | +| LUT as Memory | 4043 | 0 | 0 | 19000 | 21.28 | +| LUT as Distributed RAM | 3664 | 0 | | | | +| LUT as Shift Register | 379 | 0 | | | | +| Slice Registers | 33943 | 0 | 0 | 126800 | 26.77 | +| Register as Flip Flop | 33943 | 0 | 0 | 126800 | 26.77 | +| Register as Latch | 0 | 0 | 0 | 126800 | 0.00 | +| F7 Muxes | 689 | 0 | 0 | 31700 | 2.17 | +| F8 Muxes | 112 | 0 | 0 | 15850 | 0.71 | ++----------------------------+-------+-------+------------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. +Warning! LUT value is adjusted to account for LUT combining. +Warning! For any ECO changes, please run place_design if there are unplaced instances + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 163 | Yes | - | Set | +| 140 | Yes | - | Reset | +| 562 | Yes | Set | - | +| 33078 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++-------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------------+------+-------+------------+-----------+-------+ +| Block RAM Tile | 31 | 0 | 0 | 135 | 22.96 | +| RAMB36/FIFO* | 27 | 0 | 0 | 135 | 20.00 | +| RAMB36E1 only | 27 | | | | | +| RAMB18 | 8 | 0 | 0 | 270 | 2.96 | +| RAMB18E1 only | 8 | | | | | ++-------------------+------+-------+------------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++----------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++----------------+------+-------+------------+-----------+-------+ +| DSPs | 117 | 0 | 0 | 240 | 48.75 | +| DSP48E1 only | 117 | | | | | ++----------------+------+-------+------------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-----------------------------+------+-------+------------+-----------+-------+ +| Bonded IOB | 60 | 60 | 0 | 210 | 28.57 | +| IOB Master Pads | 29 | | | | | +| IOB Slave Pads | 28 | | | | | +| Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 | +| PHY_CONTROL | 1 | 1 | 0 | 6 | 16.67 | +| PHASER_REF | 1 | 1 | 0 | 6 | 16.67 | +| OUT_FIFO | 4 | 4 | 0 | 24 | 16.67 | +| IN_FIFO | 2 | 2 | 0 | 24 | 8.33 | +| IDELAYCTRL | 1 | 0 | 0 | 6 | 16.67 | +| IBUFDS | 0 | 0 | 0 | 202 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 4 | 4 | 0 | 24 | 16.67 | +| PHASER_OUT_PHY only | 4 | 4 | | | | +| PHASER_IN/PHASER_IN_PHY | 2 | 2 | 0 | 24 | 8.33 | +| PHASER_IN_PHY only | 2 | 2 | | | | +| IDELAYE2/IDELAYE2_FINEDELAY | 16 | 16 | 0 | 300 | 5.33 | +| IDELAYE2 only | 16 | 16 | | | | +| ILOGIC | 16 | 16 | 0 | 210 | 7.62 | +| ISERDES | 16 | 16 | 0 | 210 | | +| OLOGIC | 46 | 46 | 0 | 210 | 21.90 | +| OUTFF_ODDR_Register | 3 | 3 | | | | +| TFF_ODDR_Register | 2 | 2 | | | | +| OSERDES | 43 | 43 | 0 | 210 | | ++-----------------------------+------+-------+------------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++------------+------+-------+------------+-----------+-------+ +| BUFGCTRL | 5 | 0 | 0 | 32 | 15.63 | +| BUFIO | 0 | 0 | 0 | 24 | 0.00 | +| MMCME2_ADV | 2 | 1 | 0 | 6 | 33.33 | +| PLLE2_ADV | 1 | 1 | 0 | 6 | 16.67 | +| BUFMRCE | 0 | 0 | 0 | 12 | 0.00 | +| BUFHCE | 1 | 0 | 0 | 96 | 1.04 | +| BUFR | 0 | 0 | 0 | 24 | 0.00 | ++------------+------+-------+------------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+------------+-----------+--------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------+------+-------+------------+-----------+--------+ +| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 | +| XADC | 1 | 0 | 0 | 1 | 100.00 | ++-------------+------+-------+------------+-----------+--------+ + + +7. Primitives +------------- + ++--------------------------+-------+---------------------+ +| Ref Name | Used | Functional Category | ++--------------------------+-------+---------------------+ +| FDRE | 33078 | Flop & Latch | +| LUT6 | 20391 | LUT | +| LUT3 | 13504 | LUT | +| LUT5 | 12689 | LUT | +| LUT4 | 10385 | LUT | +| RAMD32 | 5100 | Distributed Memory | +| LUT2 | 4885 | LUT | +| CARRY4 | 2073 | CarryLogic | +| RAMS32 | 1774 | Distributed Memory | +| LUT1 | 811 | LUT | +| MUXF7 | 689 | MuxFx | +| FDSE | 562 | Flop & Latch | +| SRL16E | 246 | Distributed Memory | +| FDPE | 163 | Flop & Latch | +| FDCE | 140 | Flop & Latch | +| SRLC32E | 133 | Distributed Memory | +| DSP48E1 | 117 | Block Arithmetic | +| RAMD64E | 112 | Distributed Memory | +| MUXF8 | 112 | MuxFx | +| OSERDESE2 | 43 | IO | +| RAMS64E | 42 | Distributed Memory | +| OBUF | 33 | IO | +| RAMB36E1 | 27 | Block Memory | +| OBUFT | 18 | IO | +| ISERDESE2 | 16 | IO | +| IDELAYE2 | 16 | IO | +| IBUF_INTERMDISABLE | 16 | IO | +| RAMB18E1 | 8 | Block Memory | +| ODDR | 5 | IO | +| BUFG | 5 | Clock | +| PHASER_OUT_PHY | 4 | IO | +| OUT_FIFO | 4 | IO | +| OBUFTDS | 4 | IO | +| IBUFDS_INTERMDISABLE_INT | 4 | IO | +| INV | 3 | LUT | +| IBUF | 3 | IO | +| PHASER_IN_PHY | 2 | IO | +| OBUFDS | 2 | IO | +| MMCME2_ADV | 2 | Clock | +| IN_FIFO | 2 | IO | +| XADC | 1 | Others | +| PLLE2_ADV | 1 | Clock | +| PHY_CONTROL | 1 | IO | +| PHASER_REF | 1 | IO | +| IDELAYCTRL | 1 | IO | +| BUFH | 1 | Clock | ++--------------------------+-------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++-------------+------+ +| Ref Name | Used | ++-------------+------+ +| toy_axi_cdc | 1 | +| arty_ddr3 | 1 | ++-------------+------+ + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/phase.txt b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/phase.txt new file mode 100644 index 0000000..569f0b3 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/phase.txt @@ -0,0 +1 @@ +COMPLETE diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/route-status.rpt b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/route-status.rpt new file mode 100644 index 0000000..d85abf0 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/route-status.rpt @@ -0,0 +1,12 @@ +Design Route Status + : # nets : + ------------------------------------------- : ----------- : + # of logical nets.......................... : 119398 : + # of nets not needing routing.......... : 25764 : + # of internally routed nets........ : 23639 : + # of nets with no loads............ : 2125 : + # of routable nets..................... : 93634 : + # of fully routed nets............. : 93634 : + # of nets with routing errors.......... : 0 : + ------------------------------------------- : ----------- : + diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/routed-hierarchy.rpt b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/routed-hierarchy.rpt new file mode 100644 index 0000000..6e08749 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/routed-hierarchy.rpt @@ -0,0 +1,1150 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Tue Oct 13 01:31:56 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_utilization -hierarchical -file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/routed-hierarchy.rpt +| Design : toy_a7_top +| Device : xc7a100tcsg324-1 +| Speed File : -1 +| Design State : Routed +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Utilization by Hierarchy + +1. Utilization by Hierarchy +--------------------------- + ++----------------------------------------------------------------------------------------+-----------------------------------------------------------------+------------+------------+---------+------+-------+--------+--------+------------+ +| Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP Blocks | ++----------------------------------------------------------------------------------------+-----------------------------------------------------------------+------------+------------+---------+------+-------+--------+--------+------------+ +| toy_a7_top | (top) | 53929 | 50007 | 3644 | 278 | 33943 | 27 | 8 | 117 | +| (toy_a7_top) | (top) | 5 | 5 | 0 | 0 | 63 | 0 | 0 | 0 | +| ddr_controller | arty_ddr3 | 4569 | 3965 | 450 | 154 | 4081 | 0 | 0 | 0 | +| (ddr_controller) | arty_ddr3 | 216 | 0 | 216 | 0 | 0 | 0 | 0 | 0 | +| u_arty_ddr3_mig | arty_ddr3_mig | 4353 | 3965 | 234 | 154 | 4081 | 0 | 0 | 0 | +| temp_mon_enabled.u_tempmon | arty_ddr3mig_7series_v4_2_tempmon | 38 | 38 | 0 | 0 | 122 | 0 | 0 | 0 | +| u_ddr3_clk_ibuf | arty_ddr3mig_7series_v4_2_clk_ibuf | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| u_ddr3_infrastructure | arty_ddr3mig_7series_v4_2_infrastructure | 6 | 6 | 0 | 0 | 32 | 0 | 0 | 0 | +| u_iodelay_ctrl | arty_ddr3mig_7series_v4_2_iodelay_ctrl | 1 | 1 | 0 | 0 | 15 | 0 | 0 | 0 | +| u_memc_ui_top_axi | arty_ddr3mig_7series_v4_2_memc_ui_top_axi | 4310 | 3922 | 234 | 154 | 3912 | 0 | 0 | 0 | +| (u_memc_ui_top_axi) | arty_ddr3mig_7series_v4_2_memc_ui_top_axi | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem_intfc0 | arty_ddr3mig_7series_v4_2_mem_intfc | 3342 | 3287 | 38 | 17 | 2828 | 0 | 0 | 0 | +| ddr_phy_top0 | arty_ddr3mig_7series_v4_2_ddr_phy_top | 2738 | 2692 | 30 | 16 | 2301 | 0 | 0 | 0 | +| (ddr_phy_top0) | arty_ddr3mig_7series_v4_2_ddr_phy_top | 3 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | +| u_ddr_calib_top | arty_ddr3mig_7series_v4_2_ddr_calib_top | 2242 | 2228 | 0 | 14 | 1980 | 0 | 0 | 0 | +| (u_ddr_calib_top) | arty_ddr3mig_7series_v4_2_ddr_calib_top | 95 | 94 | 0 | 1 | 29 | 0 | 0 | 0 | +| ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl | arty_ddr3mig_7series_v4_2_ddr_phy_rdlvl | 527 | 527 | 0 | 0 | 872 | 0 | 0 | 0 | +| ddr_phy_tempmon_0 | arty_ddr3mig_7series_v4_2_ddr_phy_tempmon | 257 | 257 | 0 | 0 | 229 | 0 | 0 | 0 | +| dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr | arty_ddr3mig_7series_v4_2_ddr_phy_dqs_found_cal_hr | 146 | 145 | 0 | 1 | 91 | 0 | 0 | 0 | +| mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay | arty_ddr3mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay | 17 | 16 | 0 | 1 | 16 | 0 | 0 | 0 | +| mb_wrlvl_inst.u_ddr_phy_wrlvl | arty_ddr3mig_7series_v4_2_ddr_phy_wrlvl | 264 | 263 | 0 | 1 | 160 | 0 | 0 | 0 | +| u_ddr_phy_init | arty_ddr3mig_7series_v4_2_ddr_phy_init | 794 | 790 | 0 | 4 | 279 | 0 | 0 | 0 | +| u_ddr_phy_wrcal | arty_ddr3mig_7series_v4_2_ddr_phy_wrcal | 159 | 153 | 0 | 6 | 304 | 0 | 0 | 0 | +| u_ddr_mc_phy_wrapper | arty_ddr3mig_7series_v4_2_ddr_mc_phy_wrapper | 496 | 464 | 30 | 2 | 321 | 0 | 0 | 0 | +| (u_ddr_mc_phy_wrapper) | arty_ddr3mig_7series_v4_2_ddr_mc_phy_wrapper | 0 | 0 | 0 | 0 | 24 | 0 | 0 | 0 | +| u_ddr_mc_phy | arty_ddr3mig_7series_v4_2_ddr_mc_phy | 496 | 464 | 30 | 2 | 297 | 0 | 0 | 0 | +| (u_ddr_mc_phy) | arty_ddr3mig_7series_v4_2_ddr_mc_phy | 0 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | +| ddr_phy_4lanes_0.u_ddr_phy_4lanes | arty_ddr3mig_7series_v4_2_ddr_phy_4lanes | 496 | 464 | 30 | 2 | 281 | 0 | 0 | 0 | +| (ddr_phy_4lanes_0.u_ddr_phy_4lanes) | arty_ddr3mig_7series_v4_2_ddr_phy_4lanes | 6 | 5 | 0 | 1 | 20 | 0 | 0 | 0 | +| ddr_byte_lane_A.ddr_byte_lane_A | arty_ddr3mig_7series_v4_2_ddr_byte_lane | 51 | 21 | 30 | 0 | 20 | 0 | 0 | 0 | +| (ddr_byte_lane_A.ddr_byte_lane_A) | arty_ddr3mig_7series_v4_2_ddr_byte_lane | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | +| ddr_byte_group_io | arty_ddr3mig_7series_v4_2_ddr_byte_group_io | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| of_pre_fifo_gen.u_ddr_of_pre_fifo | arty_ddr3mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_14 | 50 | 20 | 30 | 0 | 19 | 0 | 0 | 0 | +| ddr_byte_lane_B.ddr_byte_lane_B | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized0 | 24 | 24 | 0 | 0 | 19 | 0 | 0 | 0 | +| (ddr_byte_lane_B.ddr_byte_lane_B) | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized0 | 9 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | +| ddr_byte_group_io | arty_ddr3mig_7series_v4_2_ddr_byte_group_io__parameterized0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| of_pre_fifo_gen.u_ddr_of_pre_fifo | arty_ddr3mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_13 | 15 | 15 | 0 | 0 | 19 | 0 | 0 | 0 | +| ddr_byte_lane_C.ddr_byte_lane_C | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized1 | 210 | 210 | 0 | 0 | 111 | 0 | 0 | 0 | +| (ddr_byte_lane_C.ddr_byte_lane_C) | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized1 | 7 | 7 | 0 | 0 | 69 | 0 | 0 | 0 | +| ddr_byte_group_io | arty_ddr3mig_7series_v4_2_ddr_byte_group_io__parameterized1_10 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo | arty_ddr3mig_7series_v4_2_ddr_if_post_fifo_11 | 181 | 181 | 0 | 0 | 17 | 0 | 0 | 0 | +| of_pre_fifo_gen.u_ddr_of_pre_fifo | arty_ddr3mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_12 | 22 | 22 | 0 | 0 | 24 | 0 | 0 | 0 | +| ddr_byte_lane_D.ddr_byte_lane_D | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized2 | 206 | 205 | 0 | 1 | 111 | 0 | 0 | 0 | +| (ddr_byte_lane_D.ddr_byte_lane_D) | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized2 | 0 | 0 | 0 | 0 | 69 | 0 | 0 | 0 | +| ddr_byte_group_io | arty_ddr3mig_7series_v4_2_ddr_byte_group_io__parameterized1 | 2 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | +| dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo | arty_ddr3mig_7series_v4_2_ddr_if_post_fifo | 183 | 183 | 0 | 0 | 17 | 0 | 0 | 0 | +| of_pre_fifo_gen.u_ddr_of_pre_fifo | arty_ddr3mig_7series_v4_2_ddr_of_pre_fifo__parameterized1 | 21 | 21 | 0 | 0 | 24 | 0 | 0 | 0 | +| mc0 | arty_ddr3mig_7series_v4_2_mc | 608 | 599 | 8 | 1 | 527 | 0 | 0 | 0 | +| (mc0) | arty_ddr3mig_7series_v4_2_mc | 6 | 6 | 0 | 0 | 73 | 0 | 0 | 0 | +| bank_mach0 | arty_ddr3mig_7series_v4_2_bank_mach | 495 | 495 | 0 | 0 | 362 | 0 | 0 | 0 | +| arb_mux0 | arty_ddr3mig_7series_v4_2_arb_mux | 195 | 195 | 0 | 0 | 45 | 0 | 0 | 0 | +| arb_row_col0 | arty_ddr3mig_7series_v4_2_arb_row_col | 195 | 195 | 0 | 0 | 40 | 0 | 0 | 0 | +| (arb_row_col0) | arty_ddr3mig_7series_v4_2_arb_row_col | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | +| col_arb0 | arty_ddr3mig_7series_v4_2_round_robin_arb__parameterized1 | 65 | 65 | 0 | 0 | 8 | 0 | 0 | 0 | +| config_arb0 | arty_ddr3mig_7series_v4_2_round_robin_arb__parameterized1_6 | 17 | 17 | 0 | 0 | 8 | 0 | 0 | 0 | +| pre_4_1_1T_arb.pre_arb0 | arty_ddr3mig_7series_v4_2_round_robin_arb__parameterized1_7 | 47 | 47 | 0 | 0 | 8 | 0 | 0 | 0 | +| row_arb0 | arty_ddr3mig_7series_v4_2_round_robin_arb__parameterized1_8 | 65 | 65 | 0 | 0 | 8 | 0 | 0 | 0 | +| arb_select0 | arty_ddr3mig_7series_v4_2_arb_select | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| bank_cntrl[0].bank0 | arty_ddr3mig_7series_v4_2_bank_cntrl | 71 | 71 | 0 | 0 | 75 | 0 | 0 | 0 | +| bank_compare0 | arty_ddr3mig_7series_v4_2_bank_compare_5 | 8 | 8 | 0 | 0 | 35 | 0 | 0 | 0 | +| bank_queue0 | arty_ddr3mig_7series_v4_2_bank_queue | 41 | 41 | 0 | 0 | 18 | 0 | 0 | 0 | +| bank_state0 | arty_ddr3mig_7series_v4_2_bank_state | 23 | 23 | 0 | 0 | 22 | 0 | 0 | 0 | +| bank_cntrl[1].bank0 | arty_ddr3mig_7series_v4_2_bank_cntrl__parameterized0 | 69 | 69 | 0 | 0 | 73 | 0 | 0 | 0 | +| bank_compare0 | arty_ddr3mig_7series_v4_2_bank_compare_4 | 13 | 13 | 0 | 0 | 35 | 0 | 0 | 0 | +| bank_queue0 | arty_ddr3mig_7series_v4_2_bank_queue__parameterized0 | 36 | 36 | 0 | 0 | 18 | 0 | 0 | 0 | +| bank_state0 | arty_ddr3mig_7series_v4_2_bank_state__parameterized0 | 21 | 21 | 0 | 0 | 20 | 0 | 0 | 0 | +| bank_cntrl[2].bank0 | arty_ddr3mig_7series_v4_2_bank_cntrl__parameterized1 | 71 | 71 | 0 | 0 | 74 | 0 | 0 | 0 | +| bank_compare0 | arty_ddr3mig_7series_v4_2_bank_compare_3 | 10 | 10 | 0 | 0 | 35 | 0 | 0 | 0 | +| bank_queue0 | arty_ddr3mig_7series_v4_2_bank_queue__parameterized1 | 33 | 33 | 0 | 0 | 18 | 0 | 0 | 0 | +| bank_state0 | arty_ddr3mig_7series_v4_2_bank_state__parameterized1 | 28 | 28 | 0 | 0 | 21 | 0 | 0 | 0 | +| bank_cntrl[3].bank0 | arty_ddr3mig_7series_v4_2_bank_cntrl__parameterized2 | 71 | 71 | 0 | 0 | 73 | 0 | 0 | 0 | +| bank_compare0 | arty_ddr3mig_7series_v4_2_bank_compare | 14 | 14 | 0 | 0 | 35 | 0 | 0 | 0 | +| bank_queue0 | arty_ddr3mig_7series_v4_2_bank_queue__parameterized2 | 33 | 33 | 0 | 0 | 18 | 0 | 0 | 0 | +| bank_state0 | arty_ddr3mig_7series_v4_2_bank_state__parameterized2 | 25 | 25 | 0 | 0 | 20 | 0 | 0 | 0 | +| bank_common0 | arty_ddr3mig_7series_v4_2_bank_common | 26 | 26 | 0 | 0 | 22 | 0 | 0 | 0 | +| col_mach0 | arty_ddr3mig_7series_v4_2_col_mach | 26 | 18 | 8 | 0 | 26 | 0 | 0 | 0 | +| rank_mach0 | arty_ddr3mig_7series_v4_2_rank_mach | 81 | 80 | 0 | 1 | 66 | 0 | 0 | 0 | +| rank_cntrl[0].rank_cntrl0 | arty_ddr3mig_7series_v4_2_rank_cntrl | 10 | 9 | 0 | 1 | 13 | 0 | 0 | 0 | +| rank_common0 | arty_ddr3mig_7series_v4_2_rank_common | 71 | 71 | 0 | 0 | 53 | 0 | 0 | 0 | +| (rank_common0) | arty_ddr3mig_7series_v4_2_rank_common | 59 | 59 | 0 | 0 | 47 | 0 | 0 | 0 | +| maintenance_request.maint_arb0 | arty_ddr3mig_7series_v4_2_round_robin_arb | 12 | 12 | 0 | 0 | 6 | 0 | 0 | 0 | +| u_axi_mc | arty_ddr3mig_7series_v4_2_axi_mc | 599 | 462 | 0 | 137 | 532 | 0 | 0 | 0 | +| (u_axi_mc) | arty_ddr3mig_7series_v4_2_axi_mc | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| axi_mc_ar_channel_0 | arty_ddr3mig_7series_v4_2_axi_mc_ar_channel | 122 | 122 | 0 | 0 | 87 | 0 | 0 | 0 | +| (axi_mc_ar_channel_0) | arty_ddr3mig_7series_v4_2_axi_mc_ar_channel | 1 | 1 | 0 | 0 | 45 | 0 | 0 | 0 | +| ar_cmd_fsm_0 | arty_ddr3mig_7series_v4_2_axi_mc_cmd_fsm | 80 | 80 | 0 | 0 | 1 | 0 | 0 | 0 | +| axi_mc_cmd_translator_0 | arty_ddr3mig_7series_v4_2_axi_mc_cmd_translator_0 | 43 | 43 | 0 | 0 | 41 | 0 | 0 | 0 | +| axi_mc_incr_cmd_0 | arty_ddr3mig_7series_v4_2_axi_mc_incr_cmd_1 | 35 | 35 | 0 | 0 | 33 | 0 | 0 | 0 | +| axi_mc_wrap_cmd_0 | arty_ddr3mig_7series_v4_2_axi_mc_wrap_cmd_2 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| axi_mc_aw_channel_0 | arty_ddr3mig_7series_v4_2_axi_mc_aw_channel | 125 | 125 | 0 | 0 | 85 | 0 | 0 | 0 | +| (axi_mc_aw_channel_0) | arty_ddr3mig_7series_v4_2_axi_mc_aw_channel | 0 | 0 | 0 | 0 | 43 | 0 | 0 | 0 | +| aw_cmd_fsm_0 | arty_ddr3mig_7series_v4_2_axi_mc_wr_cmd_fsm | 79 | 79 | 0 | 0 | 1 | 0 | 0 | 0 | +| axi_mc_cmd_translator_0 | arty_ddr3mig_7series_v4_2_axi_mc_cmd_translator | 47 | 47 | 0 | 0 | 41 | 0 | 0 | 0 | +| axi_mc_incr_cmd_0 | arty_ddr3mig_7series_v4_2_axi_mc_incr_cmd | 39 | 39 | 0 | 0 | 33 | 0 | 0 | 0 | +| axi_mc_wrap_cmd_0 | arty_ddr3mig_7series_v4_2_axi_mc_wrap_cmd | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| axi_mc_b_channel_0 | arty_ddr3mig_7series_v4_2_axi_mc_b_channel | 11 | 7 | 0 | 4 | 9 | 0 | 0 | 0 | +| (axi_mc_b_channel_0) | arty_ddr3mig_7series_v4_2_axi_mc_b_channel | 1 | 1 | 0 | 0 | 5 | 0 | 0 | 0 | +| bid_fifo_0 | arty_ddr3mig_7series_v4_2_axi_mc_fifo | 11 | 7 | 0 | 4 | 4 | 0 | 0 | 0 | +| axi_mc_cmd_arbiter_0 | arty_ddr3mig_7series_v4_2_axi_mc_cmd_arbiter | 33 | 33 | 0 | 0 | 31 | 0 | 0 | 0 | +| axi_mc_r_channel_0 | arty_ddr3mig_7series_v4_2_axi_mc_r_channel | 160 | 27 | 0 | 133 | 24 | 0 | 0 | 0 | +| (axi_mc_r_channel_0) | arty_ddr3mig_7series_v4_2_axi_mc_r_channel | 0 | 0 | 0 | 0 | 12 | 0 | 0 | 0 | +| rd_data_fifo_0 | arty_ddr3mig_7series_v4_2_axi_mc_fifo__parameterized0 | 141 | 13 | 0 | 128 | 6 | 0 | 0 | 0 | +| transaction_fifo_0 | arty_ddr3mig_7series_v4_2_axi_mc_fifo__parameterized1 | 19 | 14 | 0 | 5 | 6 | 0 | 0 | 0 | +| axi_mc_w_channel_0 | arty_ddr3mig_7series_v4_2_axi_mc_w_channel | 147 | 147 | 0 | 0 | 294 | 0 | 0 | 0 | +| u_ui_top | arty_ddr3mig_7series_v4_2_ui_top | 391 | 195 | 196 | 0 | 550 | 0 | 0 | 0 | +| ui_cmd0 | arty_ddr3mig_7series_v4_2_ui_cmd | 38 | 38 | 0 | 0 | 54 | 0 | 0 | 0 | +| ui_rd_data0 | arty_ddr3mig_7series_v4_2_ui_rd_data | 118 | 26 | 92 | 0 | 163 | 0 | 0 | 0 | +| ui_wr_data0 | arty_ddr3mig_7series_v4_2_ui_wr_data | 235 | 131 | 104 | 0 | 333 | 0 | 0 | 0 | +| memory_cdc | toy_axi_cdc | 452 | 190 | 262 | 0 | 1212 | 0 | 0 | 0 | +| inst | toy_axi_cdcaxi_clock_converter_v2_1_30_axi_clock_converter | 452 | 190 | 262 | 0 | 1212 | 0 | 0 | 0 | +| (inst) | toy_axi_cdcaxi_clock_converter_v2_1_30_axi_clock_converter | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | +| gen_clock_conv.gen_async_conv.asyncfifo_axi | toy_axi_cdcfifo_generator_v13_2_10 | 451 | 189 | 262 | 0 | 1212 | 0 | 0 | 0 | +| inst_fifo_gen | toy_axi_cdcfifo_generator_v13_2_10_synth | 451 | 189 | 262 | 0 | 1212 | 0 | 0 | 0 | +| gaxi_full_lite.gread_ch.grach2.axi_rach | toy_axi_cdcfifo_generator_top | 73 | 39 | 34 | 0 | 174 | 0 | 0 | 0 | +| grf.rf | toy_axi_cdcfifo_generator_ramfifo | 73 | 39 | 34 | 0 | 174 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gcx.clkx | toy_axi_cdcclk_x_pntrs__xdcDup__4 | 12 | 12 | 0 | 0 | 40 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.gcx.clkx) | toy_axi_cdcclk_x_pntrs__xdcDup__4 | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | +| rd_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__17 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| wr_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__16 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.rd | toy_axi_cdcrd_logic_21 | 13 | 13 | 0 | 0 | 18 | 0 | 0 | 0 | +| gr1.gr1_int.rfwft | toy_axi_cdcrd_fwft_27 | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| gras.rsts | toy_axi_cdcrd_status_flags_as_28 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpntr | toy_axi_cdcrd_bin_cntr_29 | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.wr | toy_axi_cdcwr_logic_22 | 7 | 7 | 0 | 0 | 14 | 0 | 0 | 0 | +| gwas.wsts | toy_axi_cdcwr_status_flags_as_25 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| wpntr | toy_axi_cdcwr_bin_cntr_26 | 5 | 5 | 0 | 0 | 12 | 0 | 0 | 0 | +| gntv_or_sync_fifo.mem | toy_axi_cdcmemory_23 | 34 | 0 | 34 | 0 | 76 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.mem) | toy_axi_cdcmemory_23 | 0 | 0 | 0 | 0 | 38 | 0 | 0 | 0 | +| gdm.dm_gen.dm | toy_axi_cdcdmem_24 | 34 | 0 | 34 | 0 | 38 | 0 | 0 | 0 | +| rstblk | toy_axi_cdcreset_blk_ramfifo__xdcDup__4 | 7 | 7 | 0 | 0 | 26 | 0 | 0 | 0 | +| (rstblk) | toy_axi_cdcreset_blk_ramfifo__xdcDup__4 | 7 | 7 | 0 | 0 | 12 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__12 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | toy_axi_cdcxpm_cdc_single__parameterized1__17 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | toy_axi_cdcxpm_cdc_single__parameterized1__16 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__11 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gaxi_full_lite.gread_ch.grdch2.axi_rdch | toy_axi_cdcfifo_generator_top__parameterized2 | 131 | 39 | 92 | 0 | 368 | 0 | 0 | 0 | +| grf.rf | toy_axi_cdcfifo_generator_ramfifo__parameterized2 | 131 | 39 | 92 | 0 | 368 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gcx.clkx | toy_axi_cdcclk_x_pntrs | 12 | 12 | 0 | 0 | 40 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.gcx.clkx) | toy_axi_cdcclk_x_pntrs | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | +| rd_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| wr_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__18 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.rd | toy_axi_cdcrd_logic_14 | 13 | 13 | 0 | 0 | 18 | 0 | 0 | 0 | +| gr1.gr1_int.rfwft | toy_axi_cdcrd_fwft_18 | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| gras.rsts | toy_axi_cdcrd_status_flags_as_19 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpntr | toy_axi_cdcrd_bin_cntr_20 | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.wr | toy_axi_cdcwr_logic_15 | 7 | 7 | 0 | 0 | 14 | 0 | 0 | 0 | +| gwas.wsts | toy_axi_cdcwr_status_flags_as_16 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| wpntr | toy_axi_cdcwr_bin_cntr_17 | 5 | 5 | 0 | 0 | 12 | 0 | 0 | 0 | +| gntv_or_sync_fifo.mem | toy_axi_cdcmemory__parameterized2 | 92 | 0 | 92 | 0 | 270 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.mem) | toy_axi_cdcmemory__parameterized2 | 0 | 0 | 0 | 0 | 135 | 0 | 0 | 0 | +| gdm.dm_gen.dm | toy_axi_cdcdmem__parameterized2 | 92 | 0 | 92 | 0 | 135 | 0 | 0 | 0 | +| rstblk | toy_axi_cdcreset_blk_ramfifo | 7 | 7 | 0 | 0 | 26 | 0 | 0 | 0 | +| (rstblk) | toy_axi_cdcreset_blk_ramfifo | 7 | 7 | 0 | 0 | 12 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | toy_axi_cdcxpm_cdc_async_rst | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | toy_axi_cdcxpm_cdc_single__parameterized1 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | toy_axi_cdcxpm_cdc_single__parameterized1__18 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__13 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gaxi_full_lite.gwrite_ch.gwach2.axi_wach | toy_axi_cdcfifo_generator_top__xdcDup__1 | 71 | 37 | 34 | 0 | 174 | 0 | 0 | 0 | +| grf.rf | toy_axi_cdcfifo_generator_ramfifo__xdcDup__1 | 71 | 37 | 34 | 0 | 174 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gcx.clkx | toy_axi_cdcclk_x_pntrs__xdcDup__1 | 10 | 10 | 0 | 0 | 40 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.gcx.clkx) | toy_axi_cdcclk_x_pntrs__xdcDup__1 | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | +| rd_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__11 | 4 | 4 | 0 | 0 | 20 | 0 | 0 | 0 | +| wr_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__10 | 4 | 4 | 0 | 0 | 20 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.rd | toy_axi_cdcrd_logic_7 | 13 | 13 | 0 | 0 | 18 | 0 | 0 | 0 | +| gr1.gr1_int.rfwft | toy_axi_cdcrd_fwft_11 | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| gras.rsts | toy_axi_cdcrd_status_flags_as_12 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpntr | toy_axi_cdcrd_bin_cntr_13 | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.wr | toy_axi_cdcwr_logic_8 | 7 | 7 | 0 | 0 | 14 | 0 | 0 | 0 | +| gwas.wsts | toy_axi_cdcwr_status_flags_as_9 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| wpntr | toy_axi_cdcwr_bin_cntr_10 | 5 | 5 | 0 | 0 | 12 | 0 | 0 | 0 | +| gntv_or_sync_fifo.mem | toy_axi_cdcmemory | 34 | 0 | 34 | 0 | 76 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.mem) | toy_axi_cdcmemory | 0 | 0 | 0 | 0 | 38 | 0 | 0 | 0 | +| gdm.dm_gen.dm | toy_axi_cdcdmem | 34 | 0 | 34 | 0 | 38 | 0 | 0 | 0 | +| rstblk | toy_axi_cdcreset_blk_ramfifo__xdcDup__1 | 7 | 7 | 0 | 0 | 26 | 0 | 0 | 0 | +| (rstblk) | toy_axi_cdcreset_blk_ramfifo__xdcDup__1 | 7 | 7 | 0 | 0 | 12 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__6 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | toy_axi_cdcxpm_cdc_single__parameterized1__11 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | toy_axi_cdcxpm_cdc_single__parameterized1__10 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__5 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch | toy_axi_cdcfifo_generator_top__parameterized0 | 136 | 38 | 98 | 0 | 386 | 0 | 0 | 0 | +| grf.rf | toy_axi_cdcfifo_generator_ramfifo__parameterized0 | 136 | 38 | 98 | 0 | 386 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gcx.clkx | toy_axi_cdcclk_x_pntrs__xdcDup__2 | 11 | 11 | 0 | 0 | 40 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.gcx.clkx) | toy_axi_cdcclk_x_pntrs__xdcDup__2 | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | +| rd_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__13 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| wr_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__12 | 4 | 4 | 0 | 0 | 20 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.rd | toy_axi_cdcrd_logic_0 | 13 | 13 | 0 | 0 | 18 | 0 | 0 | 0 | +| gr1.gr1_int.rfwft | toy_axi_cdcrd_fwft_4 | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| gras.rsts | toy_axi_cdcrd_status_flags_as_5 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpntr | toy_axi_cdcrd_bin_cntr_6 | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.wr | toy_axi_cdcwr_logic_1 | 7 | 7 | 0 | 0 | 14 | 0 | 0 | 0 | +| gwas.wsts | toy_axi_cdcwr_status_flags_as_2 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| wpntr | toy_axi_cdcwr_bin_cntr_3 | 5 | 5 | 0 | 0 | 12 | 0 | 0 | 0 | +| gntv_or_sync_fifo.mem | toy_axi_cdcmemory__parameterized0 | 98 | 0 | 98 | 0 | 288 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.mem) | toy_axi_cdcmemory__parameterized0 | 0 | 0 | 0 | 0 | 144 | 0 | 0 | 0 | +| gdm.dm_gen.dm | toy_axi_cdcdmem__parameterized0 | 98 | 0 | 98 | 0 | 144 | 0 | 0 | 0 | +| rstblk | toy_axi_cdcreset_blk_ramfifo__xdcDup__2 | 7 | 7 | 0 | 0 | 26 | 0 | 0 | 0 | +| (rstblk) | toy_axi_cdcreset_blk_ramfifo__xdcDup__2 | 7 | 7 | 0 | 0 | 12 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__8 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | toy_axi_cdcxpm_cdc_single__parameterized1__13 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | toy_axi_cdcxpm_cdc_single__parameterized1__12 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__7 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch | toy_axi_cdcfifo_generator_top__parameterized1 | 41 | 37 | 4 | 0 | 110 | 0 | 0 | 0 | +| grf.rf | toy_axi_cdcfifo_generator_ramfifo__parameterized1 | 41 | 37 | 4 | 0 | 110 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gcx.clkx | toy_axi_cdcclk_x_pntrs__xdcDup__3 | 10 | 10 | 0 | 0 | 40 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.gcx.clkx) | toy_axi_cdcclk_x_pntrs__xdcDup__3 | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | +| rd_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__15 | 4 | 4 | 0 | 0 | 20 | 0 | 0 | 0 | +| wr_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__14 | 4 | 4 | 0 | 0 | 20 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.rd | toy_axi_cdcrd_logic | 13 | 13 | 0 | 0 | 18 | 0 | 0 | 0 | +| gr1.gr1_int.rfwft | toy_axi_cdcrd_fwft | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| gras.rsts | toy_axi_cdcrd_status_flags_as | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpntr | toy_axi_cdcrd_bin_cntr | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.wr | toy_axi_cdcwr_logic | 7 | 7 | 0 | 0 | 14 | 0 | 0 | 0 | +| gwas.wsts | toy_axi_cdcwr_status_flags_as | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| wpntr | toy_axi_cdcwr_bin_cntr | 5 | 5 | 0 | 0 | 12 | 0 | 0 | 0 | +| gntv_or_sync_fifo.mem | toy_axi_cdcmemory__parameterized1 | 4 | 0 | 4 | 0 | 12 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.mem) | toy_axi_cdcmemory__parameterized1 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | +| gdm.dm_gen.dm | toy_axi_cdcdmem__parameterized1 | 4 | 0 | 4 | 0 | 6 | 0 | 0 | 0 | +| rstblk | toy_axi_cdcreset_blk_ramfifo__xdcDup__3 | 7 | 7 | 0 | 0 | 26 | 0 | 0 | 0 | +| (rstblk) | toy_axi_cdcreset_blk_ramfifo__xdcDup__3 | 7 | 7 | 0 | 0 | 12 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__10 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | toy_axi_cdcxpm_cdc_single__parameterized1__15 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | toy_axi_cdcxpm_cdc_single__parameterized1__14 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__9 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| platform | toy_a7_platform | 48907 | 45851 | 2932 | 124 | 28587 | 27 | 8 | 117 | +| chip | ToyLinuxChip | 47912 | 44968 | 2820 | 124 | 27535 | 27 | 8 | 117 | +| system | ToyLinuxSystem | 47912 | 44968 | 2820 | 124 | 27535 | 27 | 8 | 117 | +| (system) | ToyLinuxSystem | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | +| bootrom_domain | bootromClockSinkDomain | 462 | 462 | 0 | 0 | 0 | 0 | 0 | 0 | +| bootrom | TLROM | 462 | 462 | 0 | 0 | 0 | 0 | 0 | 0 | +| cbus | PeripheryBus_cbus | 969 | 815 | 154 | 0 | 364 | 0 | 0 | 0 | +| atomics | TLAtomicAutomata_cbus | 377 | 377 | 0 | 0 | 203 | 0 | 0 | 0 | +| buffer | TLBuffer_a28d64s3k1z4u | 263 | 133 | 130 | 0 | 6 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a28d64s3k1z4u | 111 | 57 | 54 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q) | Queue2_TLBundleD_a28d64s3k1z4u | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x79_445 | 107 | 53 | 54 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a28d64s3k1z4u | 152 | 76 | 76 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a28d64s3k1z4u | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x114 | 151 | 75 | 76 | 0 | 0 | 0 | 0 | 0 | +| coupler_to_bootrom | TLInterconnectCoupler_cbus_to_bootrom | 74 | 74 | 0 | 0 | 29 | 0 | 0 | 0 | +| fragmenter | TLFragmenter_bootrom | 74 | 74 | 0 | 0 | 29 | 0 | 0 | 0 | +| (fragmenter) | TLFragmenter_bootrom | 1 | 1 | 0 | 0 | 9 | 0 | 0 | 0 | +| repeater | Repeater_TLBundleA_a17d64s3k1z3u | 73 | 73 | 0 | 0 | 20 | 0 | 0 | 0 | +| coupler_to_clint | TLInterconnectCoupler_cbus_to_clint | 79 | 79 | 0 | 0 | 32 | 0 | 0 | 0 | +| fragmenter | TLFragmenter_CLINT | 79 | 79 | 0 | 0 | 32 | 0 | 0 | 0 | +| (fragmenter) | TLFragmenter_CLINT | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | +| repeater | Repeater_TLBundleA_a26d64s3k1z3u | 79 | 79 | 0 | 0 | 23 | 0 | 0 | 0 | +| coupler_to_plic | TLInterconnectCoupler_cbus_to_plic | 24 | 24 | 0 | 0 | 42 | 0 | 0 | 0 | +| fragmenter | TLFragmenter_PLIC | 24 | 24 | 0 | 0 | 42 | 0 | 0 | 0 | +| (fragmenter) | TLFragmenter_PLIC | 3 | 3 | 0 | 0 | 9 | 0 | 0 | 0 | +| repeater | Repeater_TLBundleA_a28d64s3k1z3u | 21 | 21 | 0 | 0 | 33 | 0 | 0 | 0 | +| out_xbar | TLXbar_cbus_out_i1_o4_a28d64s3k1z4u | 81 | 81 | 0 | 0 | 17 | 0 | 0 | 0 | +| wrapped_error_device | ErrorDeviceWrapper | 77 | 53 | 24 | 0 | 35 | 0 | 0 | 0 | +| buffer | TLBuffer_a14d64s3k1z4u | 40 | 16 | 24 | 0 | 6 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a14d64s3k1z4u | 25 | 13 | 12 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q) | Queue2_TLBundleD_a14d64s3k1z4u | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x79 | 21 | 9 | 12 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a14d64s3k1z4u | 15 | 3 | 12 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a14d64s3k1z4u | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x100 | 13 | 1 | 12 | 0 | 0 | 0 | 0 | 0 | +| error | TLError | 37 | 37 | 0 | 0 | 29 | 0 | 0 | 0 | +| (error) | TLError | 7 | 7 | 0 | 0 | 18 | 0 | 0 | 0 | +| a_q | Queue1_TLBundleA_a14d64s3k1z4u | 30 | 30 | 0 | 0 | 11 | 0 | 0 | 0 | +| clint_domain | CLINTClockSinkDomain | 70 | 70 | 0 | 0 | 131 | 0 | 0 | 0 | +| clint | CLINT | 70 | 70 | 0 | 0 | 129 | 0 | 0 | 0 | +| intsource | IntSyncCrossingSource_n1x2 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| reg_0 | AsyncResetRegVec_w2_i0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| coh_wrapper | CoherenceManagerWrapper | 539 | 347 | 192 | 0 | 142 | 0 | 0 | 0 | +| broadcast_1 | TLBroadcast | 539 | 347 | 192 | 0 | 142 | 0 | 0 | 0 | +| (broadcast_1) | TLBroadcast | 16 | 16 | 0 | 0 | 44 | 0 | 0 | 0 | +| TLBroadcastTracker | TLBroadcastTracker | 379 | 283 | 96 | 0 | 49 | 0 | 0 | 0 | +| (TLBroadcastTracker) | TLBroadcastTracker | 20 | 20 | 0 | 0 | 44 | 0 | 0 | 0 | +| o_data_q | Queue4_TLBroadcastData_443 | 360 | 264 | 96 | 0 | 5 | 0 | 0 | 0 | +| (o_data_q) | Queue4_TLBroadcastData_443 | 99 | 99 | 0 | 0 | 5 | 0 | 0 | 0 | +| ram_ext | ram_4x144_444 | 261 | 165 | 96 | 0 | 0 | 0 | 0 | 0 | +| TLBroadcastTracker_1 | TLBroadcastTracker_1 | 147 | 51 | 96 | 0 | 49 | 0 | 0 | 0 | +| (TLBroadcastTracker_1) | TLBroadcastTracker_1 | 32 | 32 | 0 | 0 | 44 | 0 | 0 | 0 | +| o_data_q | Queue4_TLBroadcastData | 115 | 19 | 96 | 0 | 5 | 0 | 0 | 0 | +| (o_data_q) | Queue4_TLBroadcastData | 14 | 14 | 0 | 0 | 5 | 0 | 0 | 0 | +| ram_ext | ram_4x144 | 101 | 5 | 96 | 0 | 0 | 0 | 0 | 0 | +| ibus_intsink | IntSyncAsyncCrossingSink_n1x1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | +| chain | SynchronizerShiftReg_w1_d3 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | +| output_chain | NonSyncResetSynchronizerPrimitiveShiftReg_d3 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | +| ibus_intsource | IntSyncCrossingSource_n1x1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| reg_0__0 | AsyncResetRegVec_w1_i0_442 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| mbus | MemoryBus | 719 | 463 | 256 | 0 | 330 | 0 | 0 | 0 | +| coupler_to_memory_controller_port_named_axi4 | TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4 | 719 | 463 | 256 | 0 | 330 | 0 | 0 | 0 | +| axi4yank | AXI4UserYanker_1 | 439 | 183 | 256 | 0 | 96 | 0 | 0 | 0 | +| Queue2_BundleMap | Queue2_BundleMap_6 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap) | Queue2_BundleMap_6 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_441 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_1 | Queue2_BundleMap_6_380 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_1) | Queue2_BundleMap_6_380 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_440 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_10 | Queue2_BundleMap_6_381 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_10) | Queue2_BundleMap_6_381 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_439 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_11 | Queue2_BundleMap_6_382 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_11) | Queue2_BundleMap_6_382 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_438 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_12 | Queue2_BundleMap_6_383 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_12) | Queue2_BundleMap_6_383 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_437 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_13 | Queue2_BundleMap_6_384 | 9 | 1 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_13) | Queue2_BundleMap_6_384 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_436 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_14 | Queue2_BundleMap_6_385 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_14) | Queue2_BundleMap_6_385 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_435 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_15 | Queue2_BundleMap_6_386 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_15) | Queue2_BundleMap_6_386 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_434 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_16 | Queue2_BundleMap_6_387 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_16) | Queue2_BundleMap_6_387 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_433 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_17 | Queue2_BundleMap_6_388 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_17) | Queue2_BundleMap_6_388 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_432 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_18 | Queue2_BundleMap_6_389 | 14 | 6 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_18) | Queue2_BundleMap_6_389 | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_431 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_19 | Queue2_BundleMap_6_390 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_19) | Queue2_BundleMap_6_390 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_430 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_2 | Queue2_BundleMap_6_391 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_2) | Queue2_BundleMap_6_391 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_429 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_20 | Queue2_BundleMap_6_392 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_20) | Queue2_BundleMap_6_392 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_428 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_21 | Queue2_BundleMap_6_393 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_21) | Queue2_BundleMap_6_393 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_427 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_22 | Queue2_BundleMap_6_394 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_22) | Queue2_BundleMap_6_394 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_426 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_23 | Queue2_BundleMap_6_395 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_23) | Queue2_BundleMap_6_395 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_425 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_24 | Queue2_BundleMap_6_396 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_24) | Queue2_BundleMap_6_396 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_424 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_25 | Queue2_BundleMap_6_397 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_25) | Queue2_BundleMap_6_397 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_423 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_26 | Queue2_BundleMap_6_398 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_26) | Queue2_BundleMap_6_398 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_422 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_27 | Queue2_BundleMap_6_399 | 43 | 35 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_27) | Queue2_BundleMap_6_399 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_421 | 42 | 34 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_28 | Queue2_BundleMap_6_400 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_28) | Queue2_BundleMap_6_400 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_420 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_29 | Queue2_BundleMap_6_401 | 9 | 1 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_29) | Queue2_BundleMap_6_401 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_419 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_3 | Queue2_BundleMap_6_402 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_3) | Queue2_BundleMap_6_402 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_418 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_30 | Queue2_BundleMap_6_403 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_30) | Queue2_BundleMap_6_403 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_417 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_31 | Queue2_BundleMap_6_404 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_31) | Queue2_BundleMap_6_404 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_416 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_4 | Queue2_BundleMap_6_405 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_4) | Queue2_BundleMap_6_405 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_415 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_5 | Queue2_BundleMap_6_406 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_5) | Queue2_BundleMap_6_406 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_414 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_6 | Queue2_BundleMap_6_407 | 13 | 5 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_6) | Queue2_BundleMap_6_407 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_413 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_7 | Queue2_BundleMap_6_408 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_7) | Queue2_BundleMap_6_408 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_412 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_8 | Queue2_BundleMap_6_409 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_8) | Queue2_BundleMap_6_409 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_411 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_9 | Queue2_BundleMap_6_410 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_9) | Queue2_BundleMap_6_410 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| tl2axi4 | TLToAXI4_1 | 293 | 293 | 0 | 0 | 234 | 0 | 0 | 0 | +| (tl2axi4) | TLToAXI4_1 | 3 | 3 | 0 | 0 | 41 | 0 | 0 | 0 | +| nodeOut_w_deq_q | Queue1_AXI4BundleW_1 | 83 | 83 | 0 | 0 | 146 | 0 | 0 | 0 | +| queue_arw_deq_q | Queue1_AXI4BundleARW_1 | 208 | 208 | 0 | 0 | 47 | 0 | 0 | 0 | +| plic_domain | PLICClockSinkDomain | 33 | 33 | 0 | 0 | 52 | 0 | 0 | 0 | +| intsource | IntSyncCrossingSource_n1x1_377 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| reg_0 | AsyncResetRegVec_w1_i0_379 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| intsource_1 | IntSyncCrossingSource_n1x1_378 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| reg_0 | AsyncResetRegVec_w1_i0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| plic | TLPLIC | 33 | 33 | 0 | 0 | 50 | 0 | 0 | 0 | +| (plic) | TLPLIC | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | +| gateways_gateway | LevelGateway | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| out_back_front_q | Queue1_RegMapperInput_i23_m8 | 28 | 28 | 0 | 0 | 41 | 0 | 0 | 0 | +| sbus | SystemBus | 1370 | 1036 | 334 | 0 | 608 | 0 | 0 | 0 | +| coupler_to_bus_named_cbus | TLInterconnectCoupler_sbus_to_bus_named_cbus | 143 | 143 | 0 | 0 | 191 | 0 | 0 | 0 | +| widget | TLWidthWidget16 | 143 | 143 | 0 | 0 | 191 | 0 | 0 | 0 | +| (widget) | TLWidthWidget16 | 64 | 64 | 0 | 0 | 68 | 0 | 0 | 0 | +| repeated_repeater | Repeater_TLBundleA_a28d128s3k1z4u | 79 | 79 | 0 | 0 | 123 | 0 | 0 | 0 | +| coupler_to_port_named_mmio_port_axi4 | TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4 | 740 | 406 | 334 | 0 | 353 | 0 | 0 | 0 | +| axi4buf | AXI4Buffer | 204 | 66 | 138 | 0 | 15 | 0 | 0 | 0 | +| nodeIn_b_deq_q | Queue2_AXI4BundleB | 18 | 14 | 4 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_b_deq_q) | Queue2_AXI4BundleB | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x4 | 13 | 9 | 4 | 0 | 0 | 0 | 0 | 0 | +| nodeIn_r_deq_q | Queue2_AXI4BundleR | 42 | 6 | 36 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_r_deq_q) | Queue2_AXI4BundleR | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x69 | 39 | 3 | 36 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_ar_deq_q | Queue2_AXI4BundleAR | 59 | 27 | 32 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_ar_deq_q) | Queue2_AXI4BundleAR | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x58_376 | 55 | 23 | 32 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_aw_deq_q | Queue2_AXI4BundleAW | 47 | 15 | 32 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_aw_deq_q) | Queue2_AXI4BundleAW | 6 | 6 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x58 | 41 | 9 | 32 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_w_deq_q | Queue2_AXI4BundleW | 38 | 4 | 34 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_w_deq_q) | Queue2_AXI4BundleW | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x73 | 36 | 2 | 34 | 0 | 0 | 0 | 0 | 0 | +| axi4deint | AXI4Deinterleaver | 276 | 116 | 160 | 0 | 47 | 0 | 0 | 0 | +| (axi4deint) | AXI4Deinterleaver | 0 | 0 | 0 | 0 | 19 | 0 | 0 | 0 | +| qs_queue_0 | Queue8_AXI4BundleR | 51 | 11 | 40 | 0 | 7 | 0 | 0 | 0 | +| (qs_queue_0) | Queue8_AXI4BundleR | 8 | 8 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x77_375 | 43 | 3 | 40 | 0 | 0 | 0 | 0 | 0 | +| qs_queue_1 | Queue8_AXI4BundleR_370 | 73 | 33 | 40 | 0 | 7 | 0 | 0 | 0 | +| (qs_queue_1) | Queue8_AXI4BundleR_370 | 6 | 6 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x77_374 | 67 | 27 | 40 | 0 | 0 | 0 | 0 | 0 | +| qs_queue_2 | Queue8_AXI4BundleR_371 | 49 | 9 | 40 | 0 | 7 | 0 | 0 | 0 | +| (qs_queue_2) | Queue8_AXI4BundleR_371 | 6 | 6 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x77_373 | 43 | 3 | 40 | 0 | 0 | 0 | 0 | 0 | +| qs_queue_3 | Queue8_AXI4BundleR_372 | 104 | 64 | 40 | 0 | 7 | 0 | 0 | 0 | +| (qs_queue_3) | Queue8_AXI4BundleR_372 | 6 | 6 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x77 | 98 | 58 | 40 | 0 | 0 | 0 | 0 | 0 | +| axi4yank | AXI4UserYanker | 76 | 40 | 36 | 0 | 34 | 0 | 0 | 0 | +| Queue1_BundleMap | Queue1_BundleMap | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| Queue1_BundleMap_1 | Queue1_BundleMap_359 | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| Queue2_BundleMap | Queue2_BundleMap | 12 | 6 | 6 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap) | Queue2_BundleMap | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8_369 | 8 | 2 | 6 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_1 | Queue2_BundleMap_360 | 11 | 5 | 6 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_1) | Queue2_BundleMap_360 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8_368 | 8 | 2 | 6 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_2 | Queue2_BundleMap_361 | 12 | 6 | 6 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_2) | Queue2_BundleMap_361 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8_367 | 9 | 3 | 6 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_3 | Queue2_BundleMap_362 | 12 | 6 | 6 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_3) | Queue2_BundleMap_362 | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8_366 | 8 | 2 | 6 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_4 | Queue2_BundleMap_363 | 9 | 3 | 6 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_4) | Queue2_BundleMap_363 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8_365 | 8 | 2 | 6 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_5 | Queue2_BundleMap_364 | 9 | 3 | 6 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_5) | Queue2_BundleMap_364 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8 | 8 | 2 | 6 | 0 | 0 | 0 | 0 | 0 | +| tl2axi4 | TLToAXI4 | 86 | 86 | 0 | 0 | 114 | 0 | 0 | 0 | +| (tl2axi4) | TLToAXI4 | 22 | 22 | 0 | 0 | 17 | 0 | 0 | 0 | +| nodeOut_w_deq_q | Queue1_AXI4BundleW | 33 | 33 | 0 | 0 | 50 | 0 | 0 | 0 | +| queue_arw_deq_q | Queue1_AXI4BundleARW | 31 | 31 | 0 | 0 | 47 | 0 | 0 | 0 | +| widget | TLWidthWidget16_2 | 101 | 101 | 0 | 0 | 143 | 0 | 0 | 0 | +| (widget) | TLWidthWidget16_2 | 45 | 45 | 0 | 0 | 48 | 0 | 0 | 0 | +| repeated_repeater | Repeater_TLBundleA_a31d128s3k1z3u | 56 | 56 | 0 | 0 | 95 | 0 | 0 | 0 | +| system_bus_xbar | TLXbar_sbus_i2_o3_a32d128s3k1z4c | 490 | 490 | 0 | 0 | 64 | 0 | 0 | 0 | +| tile_prci_domain | TilePRCIDomain | 43756 | 41749 | 1884 | 123 | 25900 | 27 | 8 | 117 | +| buffer | TLBuffer_a32d128s2k1z4u_1 | 1208 | 624 | 584 | 0 | 21 | 0 | 0 | 0 | +| nodeIn_b_q | Queue2_TLBundleB_a32d128s2k1z4c | 28 | 4 | 24 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_b_q) | Queue2_TLBundleB_a32d128s2k1z4c | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x60 | 25 | 1 | 24 | 0 | 0 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a32d128s2k1z4u | 101 | 5 | 96 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q) | Queue2_TLBundleD_a32d128s2k1z4u | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x142_358 | 97 | 1 | 96 | 0 | 0 | 0 | 0 | 0 | +| nodeIn_d_q_1 | Queue2_TLBundleD_a32d128s2k1z4c | 158 | 62 | 96 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q_1) | Queue2_TLBundleD_a32d128s2k1z4c | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x142 | 156 | 60 | 96 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a32d128s2k1z4u | 144 | 16 | 128 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a32d128s2k1z4u | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x189_357 | 142 | 14 | 128 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q_1 | Queue2_TLBundleA_a32d128s2k1z4c | 644 | 518 | 126 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q_1) | Queue2_TLBundleA_a32d128s2k1z4c | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x189 | 641 | 515 | 126 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_c_q | Queue2_TLBundleC_a32d128s2k1z4c | 127 | 15 | 112 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_c_q) | Queue2_TLBundleC_a32d128s2k1z4c | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x173 | 125 | 13 | 112 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_e_q | Queue2_TLBundleE_a32d128s2k1z4c | 6 | 4 | 2 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_e_q) | Queue2_TLBundleE_a32d128s2k1z4c | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_sink_ext | ram_sink_2x1 | 3 | 1 | 2 | 0 | 0 | 0 | 0 | 0 | +| element_reset_domain_bbtile | BBTile | 42551 | 41128 | 1300 | 123 | 25879 | 27 | 8 | 117 | +| (element_reset_domain_bbtile) | BBTile | 24 | 0 | 24 | 0 | 0 | 0 | 0 | 0 | +| accelerators_0 | BuckyballAccelerator | 22610 | 21977 | 510 | 123 | 15033 | 18 | 0 | 95 | +| ballDomain | BallDomain | 13143 | 12830 | 190 | 123 | 10879 | 0 | 0 | 93 | +| ballRs | BallReservationStation | 144 | 48 | 96 | 0 | 5 | 0 | 0 | 0 | +| fifo | Queue4_BallReservationStation_Anon | 144 | 48 | 96 | 0 | 5 | 0 | 0 | 0 | +| (fifo) | Queue4_BallReservationStation_Anon | 3 | 3 | 0 | 0 | 5 | 0 | 0 | 0 | +| ram_ext | ram_4x281 | 141 | 45 | 96 | 0 | 0 | 0 | 0 | 0 | +| bbus | BBus | 13000 | 12783 | 94 | 123 | 10874 | 0 | 0 | 93 | +| (bbus) | BBus | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | +| balls_0 | GemminiBall | 13000 | 12783 | 94 | 123 | 10864 | 0 | 0 | 93 | +| (balls_0) | GemminiBall | 1 | 1 | 0 | 0 | 470 | 0 | 0 | 0 | +| convUnroller | LoopConvUnroller | 476 | 476 | 0 | 0 | 375 | 0 | 0 | 20 | +| (convUnroller) | LoopConvUnroller | 33 | 33 | 0 | 0 | 375 | 0 | 0 | 0 | +| addrGen | LoopConvAddrGen | 446 | 446 | 0 | 0 | 0 | 0 | 0 | 20 | +| exCtrl | GemminiExCtrl | 11897 | 11680 | 94 | 123 | 9717 | 0 | 0 | 64 | +| (exCtrl) | GemminiExCtrl | 1310 | 1310 | 0 | 0 | 2444 | 0 | 0 | 0 | +| mesh | MeshWithDelays | 10211 | 10082 | 6 | 123 | 7259 | 0 | 0 | 64 | +| (mesh) | MeshWithDelays | 530 | 407 | 0 | 123 | 557 | 0 | 0 | 0 | +| mesh | Mesh | 9035 | 9035 | 0 | 0 | 6098 | 0 | 0 | 64 | +| (mesh) | Mesh | 225 | 225 | 0 | 0 | 3530 | 0 | 0 | 0 | +| mesh_0_0 | Tile | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_354 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_354 | 92 | 92 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_355 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_356 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_1 | Tile_104 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_351 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_351 | 92 | 92 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_352 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_353 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_2 | Tile_105 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_348 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_348 | 92 | 92 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_349 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_350 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_3 | Tile_106 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_345 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_345 | 92 | 92 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_346 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_347 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_4 | Tile_107 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_342 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_342 | 92 | 92 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_343 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_344 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_5 | Tile_108 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_339 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_339 | 92 | 92 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_340 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_341 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_6 | Tile_109 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_336 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_336 | 92 | 92 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_337 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_338 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_7 | Tile_110 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_333 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_333 | 92 | 92 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_334 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_335 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_0 | Tile_111 | 137 | 137 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_330 | 137 | 137 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_330 | 88 | 88 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_331 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_332 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_1 | Tile_112 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_327 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_327 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_328 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_329 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_2 | Tile_113 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_324 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_324 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_325 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_326 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_3 | Tile_114 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_321 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_321 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_322 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_323 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_4 | Tile_115 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_318 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_318 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_319 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_320 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_5 | Tile_116 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_315 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_315 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_316 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_317 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_6 | Tile_117 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_312 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_312 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_313 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_314 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_7 | Tile_118 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_309 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_309 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_310 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_311 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_0 | Tile_119 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_306 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_306 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_307 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_308 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_1 | Tile_120 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_303 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_303 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_304 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_305 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_2 | Tile_121 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_300 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_300 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_301 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_302 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_3 | Tile_122 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_297 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_297 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_298 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_299 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_4 | Tile_123 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_294 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_294 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_295 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_296 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_5 | Tile_124 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_291 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_291 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_292 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_293 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_6 | Tile_125 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_288 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_288 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_289 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_290 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_7 | Tile_126 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_285 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_285 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_286 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_287 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_0 | Tile_127 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_282 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_282 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_283 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_284 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_1 | Tile_128 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_279 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_279 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_280 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_281 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_2 | Tile_129 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_276 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_276 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_277 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_278 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_3 | Tile_130 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_273 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_273 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_274 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_275 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_4 | Tile_131 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_270 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_270 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_271 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_272 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_5 | Tile_132 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_267 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_267 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_268 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_269 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_6 | Tile_133 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_264 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_264 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_265 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_266 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_7 | Tile_134 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_261 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_261 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_262 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_263 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_0 | Tile_135 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_258 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_258 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_259 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_260 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_1 | Tile_136 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_255 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_255 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_256 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_257 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_2 | Tile_137 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_252 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_252 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_253 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_254 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_3 | Tile_138 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_249 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_249 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_250 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_251 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_4 | Tile_139 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_246 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_246 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_247 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_248 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_5 | Tile_140 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_243 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_243 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_244 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_245 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_6 | Tile_141 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_240 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_240 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_241 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_242 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_7 | Tile_142 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_237 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_237 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_238 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_239 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_0 | Tile_143 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_234 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_234 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_235 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_236 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_1 | Tile_144 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_231 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_231 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_232 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_233 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_2 | Tile_145 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_228 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_228 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_229 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_230 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_3 | Tile_146 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_225 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_225 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_226 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_227 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_4 | Tile_147 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_222 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_222 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_223 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_224 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_5 | Tile_148 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_219 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_219 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_220 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_221 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_6 | Tile_149 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_216 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_216 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_217 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_218 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_7 | Tile_150 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_213 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_213 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_214 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_215 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_0 | Tile_151 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_210 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_210 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_211 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_212 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_1 | Tile_152 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_207 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_207 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_208 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_209 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_2 | Tile_153 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_204 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_204 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_205 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_206 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_3 | Tile_154 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_201 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_201 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_202 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_203 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_4 | Tile_155 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_198 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_198 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_199 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_200 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_5 | Tile_156 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_195 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_195 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_196 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_197 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_6 | Tile_157 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_192 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_192 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_193 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_194 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_7 | Tile_158 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_189 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_189 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_190 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_191 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_0 | Tile_159 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_186 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_186 | 95 | 95 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_187 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_188 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_1 | Tile_160 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_183 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_183 | 96 | 96 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_184 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_185 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_2 | Tile_161 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_180 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_180 | 96 | 96 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_181 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_182 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_3 | Tile_162 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_177 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_177 | 96 | 96 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_178 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_179 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_4 | Tile_163 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_174 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_174 | 96 | 96 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_175 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_176 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_5 | Tile_164 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_171 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_171 | 96 | 96 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_172 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_173 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_6 | Tile_165 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_168 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_168 | 96 | 96 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_169 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_170 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_7 | Tile_166 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_167 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_167 | 96 | 96 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| tagq | TagQueue | 106 | 106 | 0 | 0 | 75 | 0 | 0 | 0 | +| total_rows_q | Queue6_TagWithIdAndTotalRows | 30 | 24 | 6 | 0 | 7 | 0 | 0 | 0 | +| (total_rows_q) | Queue6_TagWithIdAndTotalRows | 5 | 5 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_6x7 | 25 | 19 | 6 | 0 | 0 | 0 | 0 | 0 | +| transposer | AlwaysOutTransposer | 511 | 511 | 0 | 0 | 522 | 0 | 0 | 0 | +| (transposer) | AlwaysOutTransposer | 5 | 5 | 0 | 0 | 10 | 0 | 0 | 0 | +| pes_0_0 | PE | 17 | 17 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_1 | PE_41 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_2 | PE_42 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_3 | PE_43 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_4 | PE_44 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_5 | PE_45 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_6 | PE_46 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_7 | PE_47 | 32 | 32 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_0 | PE_48 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_1 | PE_49 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_2 | PE_50 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_3 | PE_51 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_4 | PE_52 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_5 | PE_53 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_6 | PE_54 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_7 | PE_55 | 13 | 13 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_0 | PE_56 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_1 | PE_57 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_2 | PE_58 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_3 | PE_59 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_4 | PE_60 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_5 | PE_61 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_6 | PE_62 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_7 | PE_63 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_0 | PE_64 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_1 | PE_65 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_2 | PE_66 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_3 | PE_67 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_4 | PE_68 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_5 | PE_69 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_6 | PE_70 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_7 | PE_71 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_0 | PE_72 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_1 | PE_73 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_2 | PE_74 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_3 | PE_75 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_4 | PE_76 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_5 | PE_77 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_6 | PE_78 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_7 | PE_79 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_0 | PE_80 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_1 | PE_81 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_2 | PE_82 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_3 | PE_83 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_4 | PE_84 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_5 | PE_85 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_6 | PE_86 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_7 | PE_87 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_0 | PE_88 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_1 | PE_89 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_2 | PE_90 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_3 | PE_91 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_4 | PE_92 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_5 | PE_93 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_6 | PE_94 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_7 | PE_95 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_0 | PE_96 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_1 | PE_97 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_2 | PE_98 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_3 | PE_99 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_4 | PE_100 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_5 | PE_101 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_6 | PE_102 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_7 | PE_103 | 16 | 16 | 0 | 0 | 8 | 0 | 0 | 0 | +| rdQueue0 | Queue8_SramReadResp | 305 | 261 | 44 | 0 | 7 | 0 | 0 | 0 | +| (rdQueue0) | Queue8_SramReadResp | 100 | 100 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_data_ext | ram_data_8x64_40 | 206 | 162 | 44 | 0 | 0 | 0 | 0 | 0 | +| rdQueue1 | Queue8_SramReadResp_39 | 83 | 39 | 44 | 0 | 7 | 0 | 0 | 0 | +| (rdQueue1) | Queue8_SramReadResp_39 | 38 | 38 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_data_ext | ram_data_8x64 | 46 | 2 | 44 | 0 | 0 | 0 | 0 | 0 | +| matmulUnroller | LoopMatmulUnroller | 626 | 626 | 0 | 0 | 302 | 0 | 0 | 9 | +| cmdRouter | CmdRouter | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| bankReadReqQ_q | Queue8_BuckyballAccelerator_Anon | 32 | 16 | 16 | 0 | 7 | 0 | 0 | 0 | +| (bankReadReqQ_q) | Queue8_BuckyballAccelerator_Anon | 6 | 6 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x21_38 | 26 | 10 | 16 | 0 | 0 | 0 | 0 | 0 | +| bankReadReqQ_q_1 | Queue8_BuckyballAccelerator_Anon_10 | 34 | 18 | 16 | 0 | 7 | 0 | 0 | 0 | +| (bankReadReqQ_q_1) | Queue8_BuckyballAccelerator_Anon_10 | 5 | 5 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x21 | 29 | 13 | 16 | 0 | 0 | 0 | 0 | 0 | +| frontend | Frontend_1 | 5105 | 4909 | 196 | 0 | 2205 | 2 | 0 | 0 | +| boot | BootRom | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 | +| scheduler | GlobalScheduler | 5096 | 4900 | 196 | 0 | 2199 | 2 | 0 | 0 | +| (scheduler) | GlobalScheduler | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | +| completeQueue | Queue16_UInt4 | 34 | 30 | 4 | 0 | 9 | 0 | 0 | 0 | +| (completeQueue) | Queue16_UInt4 | 10 | 10 | 0 | 0 | 9 | 0 | 0 | 0 | +| ram_ext | ram_16x4 | 24 | 20 | 4 | 0 | 0 | 0 | 0 | 0 | +| rob | GlobalROB | 4572 | 4572 | 0 | 0 | 1668 | 2 | 0 | 0 | +| (rob) | GlobalROB | 1439 | 1439 | 0 | 0 | 1476 | 0 | 0 | 0 | +| bat | BankAliasTable | 1006 | 1006 | 0 | 0 | 176 | 0 | 0 | 0 | +| robOperands | robOperands | 1721 | 1721 | 0 | 0 | 0 | 2 | 0 | 0 | +| robOperands_ext | robOperands_ext | 1721 | 1721 | 0 | 0 | 0 | 2 | 0 | 0 | +| scoreboard | BankScoreboard | 421 | 421 | 0 | 0 | 16 | 0 | 0 | 0 | +| subRob | SubROB | 492 | 300 | 192 | 0 | 519 | 0 | 0 | 0 | +| (subRob) | SubROB | 299 | 299 | 0 | 0 | 273 | 0 | 0 | 0 | +| sram | sram | 195 | 3 | 192 | 0 | 246 | 0 | 0 | 0 | +| sram_ext | sram_ext | 195 | 3 | 192 | 0 | 246 | 0 | 0 | 0 | +| gpDomain | GpDomain | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | +| completeQ | Queue1_GlobalSchedComplete | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | +| memDomain | MemDomain | 4300 | 4208 | 92 | 0 | 1928 | 16 | 0 | 2 | +| backend | MemBackend | 2149 | 2149 | 0 | 0 | 472 | 16 | 0 | 0 | +| privateBackend | PrivateMemBackend | 2149 | 2149 | 0 | 0 | 472 | 16 | 0 | 0 | +| (privateBackend) | PrivateMemBackend | 200 | 200 | 0 | 0 | 243 | 0 | 0 | 0 | +| accPipes_0 | AccPipe | 285 | 285 | 0 | 0 | 67 | 0 | 0 | 0 | +| accPipes_1 | AccPipe_11 | 265 | 265 | 0 | 0 | 67 | 0 | 0 | 0 | +| accPipes_2 | AccPipe_12 | 57 | 57 | 0 | 0 | 3 | 0 | 0 | 0 | +| accPipes_3 | AccPipe_13 | 282 | 282 | 0 | 0 | 3 | 0 | 0 | 0 | +| accPipes_4 | AccPipe_14 | 325 | 325 | 0 | 0 | 3 | 0 | 0 | 0 | +| accPipes_5 | AccPipe_15 | 508 | 508 | 0 | 0 | 3 | 0 | 0 | 0 | +| accPipes_6 | AccPipe_16 | 227 | 227 | 0 | 0 | 67 | 0 | 0 | 0 | +| banks_0 | SramBank | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_0) | SramBank | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_36 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_37 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_1 | SramBank_17 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_1) | SramBank_17 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_34 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_35 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_2 | SramBank_18 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_2) | SramBank_18 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_32 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_33 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_3 | SramBank_19 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_3) | SramBank_19 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_30 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_31 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_4 | SramBank_20 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_4) | SramBank_20 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_28 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_29 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_5 | SramBank_21 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_5) | SramBank_21 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_26 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_27 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_6 | SramBank_22 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_6) | SramBank_22 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_24 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_25 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_7 | SramBank_23 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_7) | SramBank_23 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| frontend | MemFrontend | 2117 | 2025 | 92 | 0 | 1446 | 0 | 0 | 2 | +| (frontend) | MemFrontend | 574 | 574 | 0 | 0 | 2 | 0 | 0 | 0 | +| configer | MemConfiger | 133 | 133 | 0 | 0 | 63 | 0 | 0 | 0 | +| (configer) | MemConfiger | 95 | 95 | 0 | 0 | 29 | 0 | 0 | 0 | +| zeroLines | ZeroLineGenerator | 39 | 39 | 0 | 0 | 34 | 0 | 0 | 0 | +| groupQuery | MemGroupQueryArbiter | 7 | 7 | 0 | 0 | 12 | 0 | 0 | 0 | +| (groupQuery) | MemGroupQueryArbiter | 7 | 7 | 0 | 0 | 11 | 0 | 0 | 0 | +| arbiter | RRArbiter_2 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| memLoader | MemLoader | 240 | 240 | 0 | 0 | 242 | 0 | 0 | 0 | +| memRs | MemReservationStation | 164 | 72 | 92 | 0 | 5 | 0 | 0 | 0 | +| fifo | Queue4_MemReservationStation_Anon | 164 | 72 | 92 | 0 | 5 | 0 | 0 | 0 | +| (fifo) | Queue4_MemReservationStation_Anon | 3 | 3 | 0 | 0 | 5 | 0 | 0 | 0 | +| ram_ext | ram_4x158 | 161 | 69 | 92 | 0 | 0 | 0 | 0 | 0 | +| memStorer | MemStorer | 380 | 380 | 0 | 0 | 447 | 0 | 0 | 0 | +| reader | StreamReader | 542 | 542 | 0 | 0 | 304 | 0 | 0 | 2 | +| tlbCluster | BBTLBCluster | 142 | 142 | 0 | 0 | 261 | 0 | 0 | 0 | +| (tlbCluster) | BBTLBCluster | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| tlb | TLB | 142 | 142 | 0 | 0 | 259 | 0 | 0 | 0 | +| tlbArb | RRArbiter_1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| writer | StreamWriter | 5 | 5 | 0 | 0 | 110 | 0 | 0 | 0 | +| midend | MemMidend | 38 | 38 | 0 | 0 | 10 | 0 | 0 | 0 | +| barrierUnit | BarrierUnit | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | +| buffer | TLBuffer_a32d64s1k1z4u | 127 | 49 | 78 | 0 | 6 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a32d64s1k1z4u_7 | 93 | 41 | 52 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q) | Queue2_TLBundleD_a32d64s1k1z4u_7 | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x77 | 90 | 38 | 52 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a32d64s1k1z4u_8 | 34 | 8 | 26 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a32d64s1k1z4u_8 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x116_9 | 31 | 5 | 26 | 0 | 0 | 0 | 0 | 0 | +| buffer_1 | TLBuffer_a32d64s1k1z4u_1 | 111 | 41 | 70 | 0 | 6 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a32d64s1k1z4u | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a32d64s1k1z4u | 107 | 37 | 70 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a32d64s1k1z4u | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x116 | 104 | 34 | 70 | 0 | 0 | 0 | 0 | 0 | +| buffer_2 | TLBuffer_a32d64s2k1z4u | 237 | 105 | 132 | 0 | 6 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a32d64s2k1z4u | 56 | 4 | 52 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q) | Queue2_TLBundleD_a32d64s2k1z4u | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x78 | 53 | 1 | 52 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a32d64s2k1z4u | 181 | 101 | 80 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a32d64s2k1z4u | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x117 | 180 | 100 | 80 | 0 | 0 | 0 | 0 | 0 | +| cores_0 | RocketBB | 5905 | 5817 | 88 | 0 | 1895 | 0 | 0 | 13 | +| (cores_0) | RocketBB | 2332 | 2332 | 0 | 0 | 753 | 0 | 0 | 0 | +| csr | CSRFile | 1828 | 1828 | 0 | 0 | 869 | 0 | 0 | 0 | +| div | MulDiv | 1530 | 1530 | 0 | 0 | 214 | 0 | 0 | 13 | +| ibuf | IBuf | 101 | 101 | 0 | 0 | 59 | 0 | 0 | 0 | +| rf_ext | rf_31x64 | 119 | 31 | 88 | 0 | 0 | 0 | 0 | 0 | +| dcache | NonBlockingDCache | 2954 | 2862 | 92 | 0 | 3330 | 9 | 0 | 0 | +| (dcache) | NonBlockingDCache | 514 | 514 | 0 | 0 | 1150 | 0 | 0 | 0 | +| data | DataArray | 192 | 192 | 0 | 0 | 2 | 8 | 0 | 0 | +| (data) | DataArray | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| array_0_0 | array_0_0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_0_0_ext | array_0_0_ext_6 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_0_1 | array_0_1 | 64 | 64 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_0_0_ext | array_0_0_ext_5 | 64 | 64 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_2_0 | array_2_0 | 64 | 64 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_0_0_ext | array_0_0_ext_4 | 64 | 64 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_2_1 | array_2_1 | 128 | 128 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_0_0_ext | array_0_0_ext | 128 | 128 | 0 | 0 | 0 | 2 | 0 | 0 | +| dtlb | DTLB | 1147 | 1147 | 0 | 0 | 1692 | 0 | 0 | 0 | +| lfsr_prng | MaxPeriodFibonacciLFSR_3 | 12 | 12 | 0 | 0 | 16 | 0 | 0 | 0 | +| meta | L1MetadataArray | 129 | 37 | 92 | 0 | 98 | 0 | 0 | 0 | +| (meta) | L1MetadataArray | 3 | 3 | 0 | 0 | 6 | 0 | 0 | 0 | +| tag_array | tag_array | 126 | 34 | 92 | 0 | 92 | 0 | 0 | 0 | +| tag_array_ext | tag_array_ext | 126 | 34 | 92 | 0 | 92 | 0 | 0 | 0 | +| mshrs | MSHRFile | 632 | 632 | 0 | 0 | 292 | 1 | 0 | 0 | +| (mshrs) | MSHRFile | 2 | 2 | 0 | 0 | 26 | 0 | 0 | 0 | +| mmios_0 | IOMSHR | 261 | 261 | 0 | 0 | 180 | 0 | 0 | 0 | +| mshrs_0 | MSHR | 297 | 297 | 0 | 0 | 86 | 0 | 0 | 0 | +| (mshrs_0) | MSHR | 117 | 117 | 0 | 0 | 75 | 0 | 0 | 0 | +| grantackq | Queue1_TLBundleE_a32d128s1k1z4c | 72 | 72 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpq | Queue16_ReplayInternal | 109 | 109 | 0 | 0 | 9 | 0 | 0 | 0 | +| sdq_ext | sdq_17x64 | 77 | 77 | 0 | 0 | 0 | 1 | 0 | 0 | +| prober | ProbeUnit | 78 | 78 | 0 | 0 | 40 | 0 | 0 | 0 | +| wb | WritebackUnit | 256 | 256 | 0 | 0 | 40 | 0 | 0 | 0 | +| dcacheArb | HellaCacheArbiter | 15 | 15 | 0 | 0 | 4 | 0 | 0 | 0 | +| fpuOpts_0 | FPU | 7790 | 7526 | 264 | 0 | 2618 | 0 | 0 | 9 | +| (fpuOpts_0) | FPU | 26 | 26 | 0 | 0 | 193 | 0 | 0 | 0 | +| divSqrt | DivSqrtRecFM_small_e5_s11 | 150 | 150 | 0 | 0 | 60 | 0 | 0 | 0 | +| divSqrtRecFNToRaw | DivSqrtRecFMToRaw_small_e5_s11 | 150 | 150 | 0 | 0 | 60 | 0 | 0 | 0 | +| divSqrtRawFN | DivSqrtRawFN_small_e5_s11 | 150 | 150 | 0 | 0 | 60 | 0 | 0 | 0 | +| roundRawFNToRecFN | RoundRawFNToRecFN_e5_s11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie5_is13_oe5_os11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| divSqrt_1 | DivSqrtRecFM_small_e8_s24 | 316 | 316 | 0 | 0 | 103 | 0 | 0 | 0 | +| divSqrtRecFNToRaw | DivSqrtRecFMToRaw_small_e8_s24 | 312 | 312 | 0 | 0 | 103 | 0 | 0 | 0 | +| divSqrtRawFN | DivSqrtRawFN_small_e8_s24 | 312 | 312 | 0 | 0 | 103 | 0 | 0 | 0 | +| roundRawFNToRecFN | RoundRawFNToRecFN_e8_s24 | 5 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie8_is26_oe8_os24 | 5 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | +| divSqrt_2 | DivSqrtRecFM_small_e11_s53 | 844 | 844 | 0 | 0 | 195 | 0 | 0 | 0 | +| divSqrtRecFNToRaw | DivSqrtRecFMToRaw_small_e11_s53 | 835 | 835 | 0 | 0 | 195 | 0 | 0 | 0 | +| divSqrtRawFN | DivSqrtRawFN_small_e11_s53 | 835 | 835 | 0 | 0 | 195 | 0 | 0 | 0 | +| roundRawFNToRecFN | RoundRawFNToRecFN_e11_s53 | 9 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie11_is55_oe11_os53 | 9 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | +| fpiu | FPToInt | 1020 | 1020 | 0 | 0 | 140 | 0 | 0 | 0 | +| (fpiu) | FPToInt | 970 | 970 | 0 | 0 | 140 | 0 | 0 | 0 | +| dcmp | CompareRecFN | 51 | 51 | 0 | 0 | 0 | 0 | 0 | 0 | +| fpmu | FPToFP | 418 | 418 | 0 | 0 | 208 | 0 | 0 | 0 | +| (fpmu) | FPToFP | 83 | 83 | 0 | 0 | 208 | 0 | 0 | 0 | +| narrower | RecFNToRecFN | 125 | 125 | 0 | 0 | 0 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie11_is53_oe5_os11 | 125 | 125 | 0 | 0 | 0 | 0 | 0 | 0 | +| narrower_1 | RecFNToRecFN_1 | 215 | 215 | 0 | 0 | 0 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie11_is53_oe8_os24 | 215 | 215 | 0 | 0 | 0 | 0 | 0 | 0 | +| ifpu | IntToFP | 1520 | 1520 | 0 | 0 | 695 | 0 | 0 | 0 | +| (ifpu) | IntToFP | 61 | 61 | 0 | 0 | 140 | 0 | 0 | 0 | +| i2f_0 | PipelinedINToRecFN | 779 | 779 | 0 | 0 | 281 | 0 | 0 | 0 | +| (i2f_0) | PipelinedINToRecFN | 753 | 753 | 0 | 0 | 281 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie7_is64_oe5_os11 | 27 | 27 | 0 | 0 | 0 | 0 | 0 | 0 | +| i2f_1 | PipelinedINToRecFN_1 | 344 | 344 | 0 | 0 | 137 | 0 | 0 | 0 | +| (i2f_1) | PipelinedINToRecFN_1 | 316 | 316 | 0 | 0 | 137 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie7_is64_oe8_os24 | 28 | 28 | 0 | 0 | 0 | 0 | 0 | 0 | +| i2f_2 | PipelinedINToRecFN_2 | 342 | 342 | 0 | 0 | 137 | 0 | 0 | 0 | +| (i2f_2) | PipelinedINToRecFN_2 | 301 | 301 | 0 | 0 | 137 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie7_is64_oe11_os53 | 41 | 41 | 0 | 0 | 0 | 0 | 0 | 0 | +| regfile_ext | regfile_32x65 | 1066 | 802 | 264 | 0 | 32 | 0 | 0 | 0 | +| sharedFma | FPUSharedFMAPipe | 2442 | 2442 | 0 | 0 | 992 | 0 | 0 | 9 | +| (sharedFma) | FPUSharedFMAPipe | 15 | 15 | 0 | 0 | 238 | 0 | 0 | 0 | +| fma | SharedMulAddRecFNPipe | 2428 | 2428 | 0 | 0 | 754 | 0 | 0 | 9 | +| frontend | Frontend | 2041 | 1999 | 42 | 0 | 2221 | 0 | 8 | 0 | +| (frontend) | Frontend | 3 | 3 | 0 | 0 | 90 | 0 | 0 | 0 | +| fq | ShiftQueue | 746 | 746 | 0 | 0 | 375 | 0 | 0 | 0 | +| icache | ICache | 545 | 503 | 42 | 0 | 294 | 0 | 8 | 0 | +| (icache) | ICache | 264 | 264 | 0 | 0 | 236 | 0 | 0 | 0 | +| bbtile_icache_data_arrays_0 | bbtile_icache_data_arrays_0 | 2 | 2 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_0_ext | bbtile_icache_data_arrays_0_ext_2 | 2 | 2 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_1 | bbtile_icache_data_arrays_1 | 43 | 43 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_0_ext | bbtile_icache_data_arrays_0_ext_1 | 43 | 43 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_2 | bbtile_icache_data_arrays_2 | 2 | 2 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_0_ext | bbtile_icache_data_arrays_0_ext_0 | 2 | 2 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_3 | bbtile_icache_data_arrays_3 | 45 | 45 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_0_ext | bbtile_icache_data_arrays_0_ext | 45 | 45 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_tag_array | bbtile_icache_tag_array | 63 | 21 | 42 | 0 | 42 | 0 | 0 | 0 | +| bbtile_icache_tag_array_ext | bbtile_icache_tag_array_ext | 63 | 21 | 42 | 0 | 42 | 0 | 0 | 0 | +| repl_way_v0_prng | MaxPeriodFibonacciLFSR | 129 | 129 | 0 | 0 | 16 | 0 | 0 | 0 | +| tlb | ITLB | 750 | 750 | 0 | 0 | 1462 | 0 | 0 | 0 | +| ptw | PTW | 678 | 678 | 0 | 0 | 567 | 0 | 0 | 0 | +| roccMemIF | SimpleHellaCacheIF | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| (roccMemIF) | SimpleHellaCacheIF | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| replayq | SimpleHellaCacheIFReplayQueue | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 | +| (replayq) | SimpleHellaCacheIFReplayQueue | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| nackq | Queue3_UInt2 | 8 | 8 | 0 | 0 | 5 | 0 | 0 | 0 | +| tlMasterXbar | TLXbar_MasterXbar_BBTile_i2_o1_a32d128s2k1z4c | 42 | 42 | 0 | 0 | 11 | 0 | 0 | 0 | +| widget_3 | TLWidthWidget8_4 | 78 | 78 | 0 | 0 | 160 | 0 | 0 | 0 | +| (widget_3) | TLWidthWidget8_4 | 1 | 1 | 0 | 0 | 81 | 0 | 0 | 0 | +| repeated_repeater | Repeater_TLBundleD_a32d128s2k1z4u | 77 | 77 | 0 | 0 | 79 | 0 | 0 | 0 | +| xbar | TLXbar_i2_o1_a32d64s2k1z4u | 60 | 60 | 0 | 0 | 13 | 0 | 0 | 0 | +| load_bridge | loader_axi | 41 | 41 | 0 | 0 | 306 | 0 | 0 | 0 | +| loader | ddr_uart_loader | 435 | 371 | 64 | 0 | 159 | 0 | 0 | 0 | +| normalizer | axi_fullwidth | 330 | 330 | 0 | 0 | 376 | 0 | 0 | 0 | +| peripherals | axi_scu | 147 | 99 | 48 | 0 | 162 | 0 | 0 | 0 | +| receiver | uart_rx | 37 | 37 | 0 | 0 | 31 | 0 | 0 | 0 | +| transmitter | uart_tx | 13 | 13 | 0 | 0 | 18 | 0 | 0 | 0 | ++----------------------------------------------------------------------------------------+-----------------------------------------------------------------+------------+------------+---------+------+-------+--------+--------+------------+ +* Note: The sum of lower-level cells may be larger than their parent cells total, due to cross-hierarchy LUT combining + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/routed-timing.rpt b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/routed-timing.rpt new file mode 100644 index 0000000..6038c29 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/routed-timing.rpt @@ -0,0 +1,6695 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Tue Oct 13 01:32:03 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/routed-timing.rpt +| Design : toy_a7_top +| Device : 7a100t-csg324 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +| Design State : Routed +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : No + Borrow Time for Max Delay Exceptions : Yes + Merge Timing Exceptions : Yes + Inter-SLR Compensation : Conservative + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + +------------------------------------------------------------------------------------------------ +| Report Methodology +| ------------------ +------------------------------------------------------------------------------------------------ + +No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations. + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock (0) +2. checking constant_clock (0) +3. checking pulse_width_clock (0) +4. checking unconstrained_internal_endpoints (0) +5. checking no_input_delay (2) +6. checking no_output_delay (6) +7. checking multiple_clock (0) +8. checking generated_clocks (0) +9. checking loops (0) +10. checking partial_input_delay (0) +11. checking partial_output_delay (0) +12. checking latch_loops (0) + +1. checking no_clock (0) +------------------------ + There are 0 register/latch pins with no clock. + + +2. checking constant_clock (0) +------------------------------ + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock (0) +--------------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints (0) +------------------------------------------------ + There are 0 pins that are not constrained for maximum delay. + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay (2) +------------------------------ + There are 0 input ports with no input delay specified. + + There are 2 input ports with no input delay but user has a false path constraint. (MEDIUM) + +btn0 +uart_txd_in + + +6. checking no_output_delay (6) +------------------------------- + There are 0 ports with no output delay specified. + + There are 6 ports with no output delay but user has a false path constraint (MEDIUM) + +ddr3_reset_n +led[0] +led[1] +led[2] +led[3] +uart_rxd_out + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock (0) +------------------------------ + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks (0) +-------------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops (0) +--------------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay (0) +------------------------------------ + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay (0) +------------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops (0) +---------------------------- + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + 1.276 0.000 0 107738 0.012 0.000 0 107696 0.187 0.000 0 41738 + + +All user specified timing constraints are met. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + +Clock Waveform(ns) Period(ns) Frequency(MHz) +----- ------------ ---------- -------------- +board_clk {0.000 5.000} 10.000 100.000 + core_raw {0.000 20.000} 40.000 25.000 + fb {0.000 5.000} 10.000 100.000 + ref_raw {0.000 2.500} 5.000 200.000 + sys_raw {0.000 3.000} 6.000 166.667 + freq_refclk {0.000 0.750} 1.500 666.667 + u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk {0.000 1.500} 3.000 333.333 + iserdes_clkdiv {0.000 6.000} 12.000 83.333 + u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk {0.000 1.500} 3.000 333.333 + iserdes_clkdiv_1 {0.000 6.000} 12.000 83.333 + mem_refclk {0.000 1.500} 3.000 333.333 + oserdes_clk {0.000 1.500} 3.000 333.333 + oserdes_clkdiv {0.000 6.000} 12.000 83.333 + oserdes_clk_1 {0.000 1.500} 3.000 333.333 + oserdes_clkdiv_1 {0.000 6.000} 12.000 83.333 + oserdes_clk_2 {0.000 1.500} 3.000 333.333 + oserdes_clkdiv_2 {0.000 3.000} 6.000 166.667 + oserdes_clk_3 {0.000 1.500} 3.000 333.333 + oserdes_clkdiv_3 {0.000 3.000} 6.000 166.667 + pll_clk3_out {0.000 6.000} 12.000 83.333 + clk_pll_i {0.000 6.000} 12.000 83.333 + pll_clkfbout {0.000 3.000} 6.000 166.667 + sync_pulse {1.312 4.313} 48.000 20.833 + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- +board_clk 3.000 0.000 0 1 + core_raw 8.604 0.000 0 92342 0.012 0.000 0 92342 18.750 0.000 0 35501 + fb 7.845 0.000 0 3 + ref_raw 1.756 0.000 0 130 0.122 0.000 0 130 0.264 0.000 0 69 + sys_raw 1.500 0.000 0 3 + freq_refclk 0.187 0.000 0 8 + u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk 1.333 0.000 0 16 + iserdes_clkdiv 9.974 0.000 0 33 0.071 0.000 0 33 3.850 0.000 0 9 + u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk 1.333 0.000 0 16 + iserdes_clkdiv_1 9.843 0.000 0 33 0.071 0.000 0 33 3.850 0.000 0 9 + mem_refclk 1.842 0.000 0 1 0.336 0.000 0 1 0.875 0.000 0 8 + oserdes_clk 1.333 0.000 0 12 + oserdes_clkdiv 10.051 0.000 0 44 0.090 0.000 0 44 3.850 0.000 0 12 + oserdes_clk_1 1.333 0.000 0 12 + oserdes_clkdiv_1 10.574 0.000 0 48 0.094 0.000 0 48 3.850 0.000 0 13 + oserdes_clk_2 1.423 0.000 0 4 0.413 0.000 0 4 1.333 0.000 0 12 + oserdes_clkdiv_2 4.245 0.000 0 36 0.092 0.000 0 36 0.850 0.000 0 11 + oserdes_clk_3 1.439 0.000 0 4 0.408 0.000 0 4 1.333 0.000 0 12 + oserdes_clkdiv_3 4.597 0.000 0 36 0.086 0.000 0 36 0.850 0.000 0 11 + pll_clk3_out 3.000 0.000 0 3 + clk_pll_i 2.959 0.000 0 14674 0.027 0.000 0 14674 3.850 0.000 0 5987 + pll_clkfbout 4.751 0.000 0 2 + sync_pulse 1.750 0.000 0 8 + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- +clk_pll_i core_raw 10.662 0.000 0 20 +clk_pll_i ref_raw 17.427 0.000 0 1 +clk_pll_i u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk 10.088 0.000 0 8 45.348 0.000 0 8 +clk_pll_i u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk 8.404 0.000 0 8 46.023 0.000 0 8 +sync_pulse mem_refclk 1.276 0.000 0 1 0.909 0.000 0 1 +oserdes_clk oserdes_clkdiv 2.105 0.000 0 12 0.095 0.000 0 12 +oserdes_clk_1 oserdes_clkdiv_1 2.105 0.000 0 13 0.095 0.000 0 13 +oserdes_clk_2 oserdes_clkdiv_2 2.105 0.000 0 15 0.095 0.000 0 15 +oserdes_clk_3 oserdes_clkdiv_3 2.105 0.000 0 15 0.095 0.000 0 15 +core_raw clk_pll_i 38.557 0.000 0 20 +ref_raw clk_pll_i 16.737 0.000 0 12 0.112 0.000 0 12 + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- +**async_default** clk_pll_i clk_pll_i 8.929 0.000 0 111 0.176 0.000 0 111 +**async_default** core_raw core_raw 24.453 0.000 0 116 0.154 0.000 0 116 +**default** clk_pll_i 1.969 0.000 0 1 + + +------------------------------------------------------------------------------------------------ +| User Ignored Path Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock +---------- ---------- -------- +(none) clk_pll_i +(none) core_raw +(none) clk_pll_i clk_pll_i +(none) core_raw clk_pll_i +(none) mem_refclk clk_pll_i +(none) ref_raw clk_pll_i +(none) core_raw +(none) clk_pll_i core_raw +(none) core_raw core_raw +(none) ref_raw +(none) clk_pll_i ref_raw +(none) ref_raw ref_raw + + +------------------------------------------------------------------------------------------------ +| Unconstrained Path Table +| ------------------------ +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock +---------- ---------- -------- +(none) clk_pll_i +(none) fb +(none) freq_refclk +(none) pll_clkfbout +(none) ref_raw +(none) clk_pll_i + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + +--------------------------------------------------------------------------------------------------- +From Clock: board_clk + To Clock: board_clk + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 3.000ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: board_clk +Waveform(ns): { 0.000 5.000 } +Period(ns): 10.000 +Sources: { CLK100MHZ } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a MMCME2_ADV/CLKIN1 n/a 1.249 10.000 8.751 MMCME2_ADV_X1Y2 clock_mmcm/CLKIN1 +Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 10.000 90.000 MMCME2_ADV_X1Y2 clock_mmcm/CLKIN1 +Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y2 clock_mmcm/CLKIN1 +High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y2 clock_mmcm/CLKIN1 + + + +--------------------------------------------------------------------------------------------------- +From Clock: core_raw + To Clock: core_raw + +Setup : 0 Failing Endpoints, Worst Slack 8.604ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.012ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 18.750ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 8.604ns (required time - arrival time) + Source: platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/s2_tag_match_way_reg[1]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[6]/D + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: core_raw + Path Type: Setup (Max at Slow Process Corner) + Requirement: 40.000ns (core_raw rise@40.000ns - core_raw rise@0.000ns) + Data Path Delay: 31.308ns (logic 8.022ns (25.623%) route 23.286ns (74.377%)) + Logic Levels: 34 (CARRY4=3 LUT2=6 LUT3=3 LUT4=8 LUT5=9 LUT6=5) + Clock Path Skew: -0.026ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.360ns = ( 38.640 - 40.000 ) + Source Clock Delay (SCD): -0.846ns + Clock Pessimism Removal (CPR): 0.488ns + Clock Uncertainty: 0.091ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.694 -0.846 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/clk + SLICE_X81Y128 FDRE r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/s2_tag_match_way_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X81Y128 FDRE (Prop_fdre_C_Q) 0.419 -0.427 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/s2_tag_match_way_reg[1]/Q + net (fo=166, routed) 1.312 0.885 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/p_0_in + SLICE_X82Y128 LUT6 (Prop_lut6_I1_O) 0.296 1.181 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/NonBlockingDCac_LUT6_24/O + net (fo=1, routed) 0.513 1.693 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/NonBlockingDCac_net_49 + SLICE_X81Y128 LUT5 (Prop_lut5_I4_O) 0.124 1.817 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/NonBlockingDCac_LUT5_49/O + net (fo=8, routed) 1.107 2.924 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/NonBlockingDCac_net_114 + SLICE_X68Y129 LUT5 (Prop_lut5_I4_O) 0.124 3.048 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/load_wb_data[31]_i_3/O + net (fo=5, routed) 0.910 3.958 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/_dcacheArb_io_requestor_1_resp_bits_data_word_bypass[31] + SLICE_X59Y137 LUT4 (Prop_lut4_I3_O) 0.124 4.082 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/NonBlockingDCac_LUT4_25/O + net (fo=33, routed) 0.914 4.997 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/NonBlockingDCac_net_232 + SLICE_X59Y135 LUT4 (Prop_lut4_I3_O) 0.152 5.149 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/in_pipe_b_in1[48]_i_3/O + net (fo=2, routed) 1.645 6.793 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/_dcacheArb_io_requestor_1_resp_bits_data_word_bypass[48] + SLICE_X48Y161 LUT5 (Prop_lut5_I0_O) 0.332 7.125 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/in_pipe_b_in1[48]_i_2/O + net (fo=1, routed) 0.971 8.096 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/in_pipe_b_in1[48]_i_2_n_0 + SLICE_X44Y161 LUT3 (Prop_lut3_I0_O) 0.150 8.246 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/in_pipe_b_in1[48]_i_1/O + net (fo=7, routed) 1.229 9.476 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/_cores_0_io_fpu_fromint_data[48] + SLICE_X41Y179 LUT4 (Prop_lut4_I3_O) 0.358 9.834 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[50]_i_9/O + net (fo=2, routed) 0.614 10.448 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[50]_i_9_n_0 + SLICE_X41Y178 LUT6 (Prop_lut6_I0_O) 0.332 10.780 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[50]_i_7/O + net (fo=11, routed) 0.816 11.596 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[50]_i_7_n_0 + SLICE_X45Y174 LUT4 (Prop_lut4_I3_O) 0.119 11.715 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_217/O + net (fo=3, routed) 0.591 12.306 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_217_n_0 + SLICE_X45Y178 LUT2 (Prop_lut2_I1_O) 0.332 12.638 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_213/O + net (fo=5, routed) 0.610 13.248 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_213_n_0 + SLICE_X43Y178 LUT3 (Prop_lut3_I0_O) 0.124 13.372 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_227/O + net (fo=3, routed) 0.811 14.182 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_227_n_0 + SLICE_X45Y178 LUT2 (Prop_lut2_I0_O) 0.149 14.331 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_223/O + net (fo=3, routed) 0.600 14.931 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_223_n_0 + SLICE_X41Y177 LUT2 (Prop_lut2_I0_O) 0.332 15.263 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_229/O + net (fo=2, routed) 0.277 15.540 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_229_n_0 + SLICE_X41Y177 LUT2 (Prop_lut2_I0_O) 0.124 15.664 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_220/O + net (fo=5, routed) 0.659 16.323 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_220_n_0 + SLICE_X46Y180 LUT3 (Prop_lut3_I0_O) 0.124 16.447 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_262/O + net (fo=3, routed) 0.602 17.049 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_262_n_0 + SLICE_X45Y180 LUT2 (Prop_lut2_I0_O) 0.149 17.198 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_259/O + net (fo=3, routed) 0.668 17.866 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_259_n_0 + SLICE_X45Y180 LUT2 (Prop_lut2_I0_O) 0.332 18.198 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_257/O + net (fo=4, routed) 0.733 18.931 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_257_n_0 + SLICE_X45Y177 LUT5 (Prop_lut5_I3_O) 0.124 19.055 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_264/O + net (fo=4, routed) 0.606 19.661 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_264_n_0 + SLICE_X45Y181 LUT6 (Prop_lut6_I0_O) 0.124 19.785 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_251/O + net (fo=1, routed) 0.626 20.412 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_251_n_0 + SLICE_X44Y181 CARRY4 (Prop_carry4_DI[0]_O[2]) + 0.556 20.968 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[2]_i_185/O[2] + net (fo=1, routed) 0.292 21.259 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/alu/_popc_in_T_1370[63] + SLICE_X43Y181 LUT4 (Prop_lut4_I0_O) 0.302 21.561 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_134/O + net (fo=3, routed) 0.825 22.386 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_134_n_0 + SLICE_X41Y181 LUT4 (Prop_lut4_I2_O) 0.124 22.510 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_115/O + net (fo=4, routed) 0.671 23.181 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_115_n_0 + SLICE_X40Y179 LUT4 (Prop_lut4_I1_O) 0.124 23.305 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_66/O + net (fo=2, routed) 1.035 24.340 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_66_n_0 + SLICE_X41Y171 LUT5 (Prop_lut5_I4_O) 0.152 24.492 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_61/O + net (fo=2, routed) 0.684 25.177 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_61_n_0 + SLICE_X41Y171 LUT5 (Prop_lut5_I3_O) 0.360 25.537 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_56/O + net (fo=2, routed) 0.451 25.987 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_56_n_0 + SLICE_X41Y171 LUT5 (Prop_lut5_I3_O) 0.326 26.313 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_39/O + net (fo=2, routed) 0.507 26.820 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_39_n_0 + SLICE_X40Y171 LUT6 (Prop_lut6_I5_O) 0.124 26.944 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_30/O + net (fo=1, routed) 0.000 26.944 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_30_n_0 + SLICE_X40Y171 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.401 27.345 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[2]_i_13/CO[3] + net (fo=1, routed) 0.000 27.345 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[2]_i_13_n_0 + SLICE_X40Y172 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 27.573 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[4]_i_14/CO[2] + net (fo=2, routed) 0.583 28.156 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/alu/data5[6] + SLICE_X43Y170 LUT4 (Prop_lut4_I3_O) 0.307 28.463 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[6]_i_13/O + net (fo=1, routed) 0.508 28.972 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[6]_i_13_n_0 + SLICE_X46Y170 LUT6 (Prop_lut6_I3_O) 0.326 29.298 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[6]_i_5/O + net (fo=1, routed) 0.423 29.721 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[6]_i_5_n_0 + SLICE_X48Y169 LUT5 (Prop_lut5_I0_O) 0.124 29.845 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[6]_i_2/O + net (fo=1, routed) 0.493 30.338 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[6]_i_2_n_0 + SLICE_X48Y169 LUT5 (Prop_lut5_I0_O) 0.124 30.462 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[6]_i_1/O + net (fo=1, routed) 0.000 30.462 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/_alu_io_out[6] + SLICE_X48Y169 FDRE r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[6]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 40.000 40.000 r + E3 0.000 40.000 r CLK100MHZ (IN) + net (fo=0) 0.000 40.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r input_clock/O + net (fo=1, routed) 1.162 42.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 35.249 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 36.888 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 36.979 r core_buffer/O + net (fo=35517, routed) 1.660 38.640 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/clk + SLICE_X48Y169 FDRE r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[6]/C + clock pessimism 0.488 39.128 + clock uncertainty -0.091 39.037 + SLICE_X48Y169 FDRE (Setup_fdre_C_D) 0.029 39.066 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[6] + ------------------------------------------------------------------- + required time 39.066 + arrival time -30.462 + ------------------------------------------------------------------- + slack 8.604 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.012ns (arrival time - required time) + Source: platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/memStorer/dma_data_reg[56]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/writer/reqReg_data_reg[56]/D + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: core_raw + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (core_raw rise@0.000ns - core_raw rise@0.000ns) + Data Path Delay: 0.285ns (logic 0.128ns (44.914%) route 0.157ns (55.086%)) + Logic Levels: 0 + Clock Path Skew: 0.261ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.847ns + Source Clock Delay (SCD): -0.604ns + Clock Pessimism Removal (CPR): -0.504ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.379 -1.689 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.499 -1.190 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.164 r core_buffer/O + net (fo=35517, routed) 0.560 -0.604 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/memStorer/clk + SLICE_X51Y66 FDRE r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/memStorer/dma_data_reg[56]/C + ------------------------------------------------------------------- ------------------- + SLICE_X51Y66 FDRE (Prop_fdre_C_Q) 0.128 -0.476 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/memStorer/dma_data_reg[56]/Q + net (fo=1, routed) 0.157 -0.319 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/writer/reqReg_data_reg[63]_1[56] + SLICE_X52Y67 FDRE r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/writer/reqReg_data_reg[56]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.163 -2.245 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.544 -1.702 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.673 r core_buffer/O + net (fo=35517, routed) 0.826 -0.847 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/writer/clk + SLICE_X52Y67 FDRE r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/writer/reqReg_data_reg[56]/C + clock pessimism 0.504 -0.343 + SLICE_X52Y67 FDRE (Hold_fdre_C_D) 0.012 -0.331 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/writer/reqReg_data_reg[56] + ------------------------------------------------------------------- + required time 0.331 + arrival time -0.319 + ------------------------------------------------------------------- + slack 0.012 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: core_raw +Waveform(ns): { 0.000 20.000 } +Period(ns): 40.000 +Sources: { clock_mmcm/CLKOUT0 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a DSP48E1/CLK n/a 3.884 40.000 36.116 DSP48_X0Y69 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg/CLK +Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 40.000 173.360 MMCME2_ADV_X1Y2 clock_mmcm/CLKOUT0 +Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X58Y81 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_12_17/RAMA/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X58Y81 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_12_17/RAMA/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: fb + To Clock: fb + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 7.845ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: fb +Waveform(ns): { 0.000 5.000 } +Period(ns): 10.000 +Sources: { clock_mmcm/CLKFBOUT } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFG/I n/a 2.155 10.000 7.845 BUFGCTRL_X0Y19 fb_buffer/I +Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 10.000 90.000 MMCME2_ADV_X1Y2 clock_mmcm/CLKFBIN + + + +--------------------------------------------------------------------------------------------------- +From Clock: ref_raw + To Clock: ref_raw + +Setup : 0 Failing Endpoints, Worst Slack 1.756ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.122ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 0.264ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.756ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r2_reg/C + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.sample_timer_reg[1]/R + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: ref_raw + Path Type: Setup (Max at Slow Process Corner) + Requirement: 5.000ns (ref_raw rise@5.000ns - ref_raw rise@0.000ns) + Data Path Delay: 2.724ns (logic 0.716ns (26.281%) route 2.008ns (73.719%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: -0.024ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.519ns = ( 3.481 - 5.000 ) + Source Clock Delay (SCD): -0.935ns + Clock Pessimism Removal (CPR): 0.560ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.070 -4.355 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.719 -2.636 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r ref_buffer/O + net (fo=67, routed) 1.605 -0.935 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/clk_ref_i + SLICE_X32Y125 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r2_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X32Y125 FDRE (Prop_fdre_C_Q) 0.419 -0.516 r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r2_reg/Q + net (fo=32, routed) 0.876 0.360 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r2 + SLICE_X32Y131 LUT2 (Prop_lut2_I0_O) 0.297 0.657 r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/arty_ddr3mig_7s_LUT2_2/O + net (fo=11, routed) 1.132 1.789 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.sample_timer0__20 + SLICE_X28Y138 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.sample_timer_reg[1]/R + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 5.000 5.000 r + E3 0.000 5.000 r CLK100MHZ (IN) + net (fo=0) 0.000 5.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 6.411 r input_clock/O + net (fo=1, routed) 1.162 7.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.324 0.249 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.639 1.888 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 1.979 r ref_buffer/O + net (fo=67, routed) 1.502 3.481 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/clk_ref_i + SLICE_X28Y138 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.sample_timer_reg[1]/C + clock pessimism 0.560 4.041 + clock uncertainty -0.067 3.974 + SLICE_X28Y138 FDRE (Setup_fdre_C_R) -0.429 3.545 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.sample_timer_reg[1] + ------------------------------------------------------------------- + required time 3.545 + arrival time -1.789 + ------------------------------------------------------------------- + slack 1.756 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.122ns (arrival time - required time) + Source: btn_ref_meta_reg/C + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: btn_ref_sync_reg/D + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: ref_raw + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (ref_raw rise@0.000ns - ref_raw rise@0.000ns) + Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.849ns + Source Clock Delay (SCD): -0.609ns + Clock Pessimism Removal (CPR): -0.240ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -2.379 -1.689 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.499 -1.190 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r ref_buffer/O + net (fo=67, routed) 0.555 -0.609 ref_clk + SLICE_X67Y74 FDRE r btn_ref_meta_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y74 FDRE (Prop_fdre_C_Q) 0.141 -0.468 r btn_ref_meta_reg/Q + net (fo=1, routed) 0.056 -0.412 btn_ref_meta + SLICE_X67Y74 FDRE r btn_ref_sync_reg/D + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -3.163 -2.245 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.544 -1.702 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r ref_buffer/O + net (fo=67, routed) 0.824 -0.849 ref_clk + SLICE_X67Y74 FDRE r btn_ref_sync_reg/C + clock pessimism 0.240 -0.609 + SLICE_X67Y74 FDRE (Hold_fdre_C_D) 0.075 -0.534 btn_ref_sync_reg + ------------------------------------------------------------------- + required time 0.534 + arrival time -0.412 + ------------------------------------------------------------------- + slack 0.122 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: ref_raw +Waveform(ns): { 0.000 2.500 } +Period(ns): 5.000 +Sources: { clock_mmcm/CLKOUT2 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a XADC/DCLK n/a 4.000 5.000 1.000 XADC_X0Y0 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.XADC_inst/DCLK +Max Period n/a IDELAYCTRL/REFCLK n/a 5.264 5.000 0.264 IDELAYCTRL_X1Y1 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/u_idelayctrl_200/REFCLK +Low Pulse Width Slow FDRE/C n/a 0.500 2.500 2.000 SLICE_X67Y74 btn_ref_meta_reg/C +High Pulse Width Slow FDRE/C n/a 0.500 2.500 2.000 SLICE_X67Y74 btn_ref_meta_reg/C + + + +--------------------------------------------------------------------------------------------------- +From Clock: sys_raw + To Clock: sys_raw + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.500ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: sys_raw +Waveform(ns): { 0.000 3.000 } +Period(ns): 6.000 +Sources: { clock_mmcm/CLKOUT1 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFG/I n/a 2.155 6.000 3.845 BUFGCTRL_X0Y17 sys_buffer/I +Max Period n/a PLLE2_ADV/CLKIN1 n/a 52.633 6.000 46.633 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 +Low Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 1.500 3.000 1.500 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 +High Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 1.500 3.000 1.500 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 + + + +--------------------------------------------------------------------------------------------------- +From Clock: freq_refclk + To Clock: freq_refclk + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 0.187ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: freq_refclk +Waveform(ns): { 0.000 0.750 } +Period(ns): 1.500 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a PHASER_OUT_PHY/FREQREFCLK n/a 1.250 1.500 0.250 PHASER_OUT_PHY_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/FREQREFCLK +Max Period n/a PHASER_OUT_PHY/FREQREFCLK n/a 2.500 1.500 1.000 PHASER_OUT_PHY_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/FREQREFCLK +Low Pulse Width Slow PHASER_REF/CLKIN n/a 0.562 0.750 0.188 PHASER_REF_X1Y1 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i/CLKIN +High Pulse Width Slow PHASER_OUT_PHY/FREQREFCLK n/a 0.563 0.750 0.187 PHASER_OUT_PHY_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/FREQREFCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk + To Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a ISERDESE2/CLK n/a 1.667 3.000 1.333 ILOGIC_X1Y76 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: iserdes_clkdiv + To Clock: iserdes_clkdiv + +Setup : 0 Failing Endpoints, Worst Slack 9.974ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.071ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 3.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 9.974ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLKDIVP + (rising edge-triggered cell ISERDESE2 clocked by iserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/D1[3] + (rising edge-triggered cell IN_FIFO clocked by iserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: iserdes_clkdiv + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (iserdes_clkdiv rise@12.000ns - iserdes_clkdiv rise@0.000ns) + Data Path Delay: 0.954ns (logic 0.425ns (44.547%) route 0.529ns (55.453%)) + Logic Levels: 0 + Clock Path Skew: -0.450ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.970ns = ( 12.970 - 12.000 ) + Source Clock Delay (SCD): 2.107ns + Clock Pessimism Removal (CPR): 0.686ns + Clock Uncertainty: 0.051ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.073ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock iserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.607 -0.179 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.662 1.484 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.173 1.657 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, routed) 0.450 2.107 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/iserdes_clkdiv + ILOGIC_X1Y76 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLKDIVP + ------------------------------------------------------------------- ------------------- + ILOGIC_X1Y76 ISERDESE2 (Prop_iserdese2_CLKDIVP_Q1) + 0.425 2.532 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/Q1 + net (fo=1, routed) 0.529 3.061 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/if_d1[3] + IN_FIFO_X1Y6 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/D1[3] + ------------------------------------------------------------------- ------------------- + + (clock iserdes_clkdiv rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.576 11.183 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.624 12.807 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.163 12.970 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, routed) 0.000 12.970 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clkdiv + IN_FIFO_X1Y6 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK + clock pessimism 0.686 13.657 + clock uncertainty -0.051 13.606 + IN_FIFO_X1Y6 IN_FIFO (Setup_in_fifo_WRCLK_D1[3]) + -0.571 13.035 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo + ------------------------------------------------------------------- + required time 13.035 + arrival time -3.061 + ------------------------------------------------------------------- + slack 9.974 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.071ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV + (rising edge-triggered cell PHASER_IN_PHY clocked by iserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WREN + (rising edge-triggered cell IN_FIFO clocked by iserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: iserdes_clkdiv + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (iserdes_clkdiv rise@0.000ns - iserdes_clkdiv rise@0.000ns) + Data Path Delay: 0.058ns (logic 0.058ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.908ns + Source Clock Delay (SCD): 1.095ns + Clock Pessimism Removal (CPR): -0.187ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock iserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.197 -0.351 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.357 1.005 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.090 1.095 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV + ------------------------------------------------------------------- ------------------- + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_ICLKDIV_WRENABLE) + 0.058 1.153 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/WRENABLE + net (fo=1, routed) 0.000 1.153 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ififo_wr_enable + IN_FIFO_X1Y6 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WREN + ------------------------------------------------------------------- ------------------- + + (clock iserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.217 -0.568 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.381 0.812 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.096 0.908 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, routed) 0.000 0.908 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clkdiv + IN_FIFO_X1Y6 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK + clock pessimism 0.187 1.095 + IN_FIFO_X1Y6 IN_FIFO (Hold_in_fifo_WRCLK_WREN) + -0.013 1.082 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo + ------------------------------------------------------------------- + required time -1.082 + arrival time 1.153 + ------------------------------------------------------------------- + slack 0.071 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: iserdes_clkdiv +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a IN_FIFO/WRCLK n/a 5.000 12.000 7.000 IN_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK +Low Pulse Width Slow IN_FIFO/WRCLK n/a 2.150 6.000 3.850 IN_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK +High Pulse Width Slow IN_FIFO/WRCLK n/a 2.150 6.000 3.850 IN_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk + To Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a ISERDESE2/CLK n/a 1.667 3.000 1.333 ILOGIC_X1Y88 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: iserdes_clkdiv_1 + To Clock: iserdes_clkdiv_1 + +Setup : 0 Failing Endpoints, Worst Slack 9.843ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.071ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 3.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 9.843ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq/CLKDIVP + (rising edge-triggered cell ISERDESE2 clocked by iserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/D2[0] + (rising edge-triggered cell IN_FIFO clocked by iserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: iserdes_clkdiv_1 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (iserdes_clkdiv_1 rise@12.000ns - iserdes_clkdiv_1 rise@0.000ns) + Data Path Delay: 1.117ns (logic 0.425ns (38.045%) route 0.692ns (61.955%)) + Logic Levels: 0 + Clock Path Skew: -0.465ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.960ns = ( 12.960 - 12.000 ) + Source Clock Delay (SCD): 2.112ns + Clock Pessimism Removal (CPR): 0.686ns + Clock Uncertainty: 0.051ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.073ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock iserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.597 -0.189 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.662 1.474 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.173 1.647 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, routed) 0.465 2.112 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/iserdes_clkdiv + ILOGIC_X1Y89 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq/CLKDIVP + ------------------------------------------------------------------- ------------------- + ILOGIC_X1Y89 ISERDESE2 (Prop_iserdese2_CLKDIVP_Q4) + 0.425 2.537 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq/Q4 + net (fo=1, routed) 0.692 3.229 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/if_d2[0] + IN_FIFO_X1Y7 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/D2[0] + ------------------------------------------------------------------- ------------------- + + (clock iserdes_clkdiv_1 rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.566 11.173 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.624 12.797 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.163 12.960 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, routed) 0.000 12.960 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clkdiv + IN_FIFO_X1Y7 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK + clock pessimism 0.686 13.647 + clock uncertainty -0.051 13.596 + IN_FIFO_X1Y7 IN_FIFO (Setup_in_fifo_WRCLK_D2[0]) + -0.524 13.072 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo + ------------------------------------------------------------------- + required time 13.072 + arrival time -3.229 + ------------------------------------------------------------------- + slack 9.843 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.071ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV + (rising edge-triggered cell PHASER_IN_PHY clocked by iserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WREN + (rising edge-triggered cell IN_FIFO clocked by iserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: iserdes_clkdiv_1 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (iserdes_clkdiv_1 rise@0.000ns - iserdes_clkdiv_1 rise@0.000ns) + Data Path Delay: 0.058ns (logic 0.058ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.902ns + Source Clock Delay (SCD): 1.089ns + Clock Pessimism Removal (CPR): -0.187ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock iserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.191 -0.357 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.357 0.999 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.090 1.089 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV + ------------------------------------------------------------------- ------------------- + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_ICLKDIV_WRENABLE) + 0.058 1.147 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/WRENABLE + net (fo=1, routed) 0.000 1.147 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ififo_wr_enable + IN_FIFO_X1Y7 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WREN + ------------------------------------------------------------------- ------------------- + + (clock iserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.211 -0.574 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.381 0.806 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.096 0.902 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, routed) 0.000 0.902 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clkdiv + IN_FIFO_X1Y7 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK + clock pessimism 0.187 1.089 + IN_FIFO_X1Y7 IN_FIFO (Hold_in_fifo_WRCLK_WREN) + -0.013 1.076 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo + ------------------------------------------------------------------- + required time -1.076 + arrival time 1.147 + ------------------------------------------------------------------- + slack 0.071 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: iserdes_clkdiv_1 +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a IN_FIFO/WRCLK n/a 5.000 12.000 7.000 IN_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK +Low Pulse Width Slow IN_FIFO/WRCLK n/a 2.150 6.000 3.850 IN_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK +High Pulse Width Slow IN_FIFO/WRCLK n/a 2.150 6.000 3.850 IN_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: mem_refclk + To Clock: mem_refclk + +Setup : 0 Failing Endpoints, Worst Slack 1.842ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.336ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 0.875ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.842ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLMSTREMPTY + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: mem_refclk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (mem_refclk rise@3.000ns - mem_refclk rise@0.000ns) + Data Path Delay: 1.093ns (logic 0.622ns (56.908%) route 0.471ns (43.092%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.804ns = ( 2.196 - 3.000 ) + Source Clock Delay (SCD): -0.165ns + Clock Pessimism Removal (CPR): 0.639ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.621 -0.165 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + ------------------------------------------------------------------- ------------------- + PHY_CONTROL_X1Y1 PHY_CONTROL (Prop_phy_control_MEMREFCLK_PHYCTLEMPTY) + 0.622 0.457 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLEMPTY + net (fo=1, routed) 0.471 0.928 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i_n_1 + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLMSTREMPTY + ------------------------------------------------------------------- ------------------- + + (clock mem_refclk rise edge) + 3.000 3.000 r + E3 0.000 3.000 r CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 4.411 r input_clock/O + net (fo=1, routed) 1.162 5.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -1.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -0.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -0.021 r sys_buffer/O + net (fo=1, routed) 1.544 1.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 1.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.589 2.196 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + clock pessimism 0.639 2.835 + clock uncertainty -0.054 2.781 + PHY_CONTROL_X1Y1 PHY_CONTROL (Setup_phy_control_MEMREFCLK_PHYCTLMSTREMPTY) + -0.011 2.770 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i + ------------------------------------------------------------------- + required time 2.770 + arrival time -0.928 + ------------------------------------------------------------------- + slack 1.842 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.336ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLMSTREMPTY + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: mem_refclk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mem_refclk rise@0.000ns - mem_refclk rise@0.000ns) + Data Path Delay: 0.459ns (logic 0.313ns (68.192%) route 0.146ns (31.808%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.570ns + Source Clock Delay (SCD): -0.353ns + Clock Pessimism Removal (CPR): -0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.195 -0.353 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + ------------------------------------------------------------------- ------------------- + PHY_CONTROL_X1Y1 PHY_CONTROL (Prop_phy_control_MEMREFCLK_PHYCTLEMPTY) + 0.313 -0.040 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLEMPTY + net (fo=1, routed) 0.146 0.106 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i_n_1 + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLMSTREMPTY + ------------------------------------------------------------------- ------------------- + + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.215 -0.570 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + clock pessimism 0.217 -0.353 + PHY_CONTROL_X1Y1 PHY_CONTROL (Hold_phy_control_MEMREFCLK_PHYCTLMSTREMPTY) + 0.123 -0.230 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i + ------------------------------------------------------------------- + required time 0.230 + arrival time 0.106 + ------------------------------------------------------------------- + slack 0.336 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: mem_refclk +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a PHY_CONTROL/MEMREFCLK n/a 1.475 3.000 1.525 PHY_CONTROL_X1Y1 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK +Max Period n/a PLLE2_ADV/CLKOUT1 n/a 160.000 3.000 157.000 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 +Low Pulse Width Slow PHY_CONTROL/MEMREFCLK n/a 0.625 1.500 0.875 PHY_CONTROL_X1Y1 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK +High Pulse Width Slow PHY_CONTROL/MEMREFCLK n/a 0.625 1.500 0.875 PHY_CONTROL_X1Y1 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk + To Clock: oserdes_clk + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clk +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OSERDESE2/CLK n/a 1.667 3.000 1.333 OLOGIC_X1Y51 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[0].oserdes_dq_.sdr.oserdes_dq_i/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clkdiv + To Clock: oserdes_clkdiv + +Setup : 0 Failing Endpoints, Worst Slack 10.051ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.090ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 3.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 10.051ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[11].oserdes_dq_.sdr.oserdes_dq_i/D4 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (oserdes_clkdiv rise@12.000ns - oserdes_clkdiv rise@0.000ns) + Data Path Delay: 1.681ns (logic 0.674ns (40.087%) route 1.007ns (59.913%)) + Logic Levels: 0 + Clock Path Skew: 0.412ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.119ns = ( 14.119 - 12.000 ) + Source Clock Delay (SCD): 2.419ns + Clock Pessimism Removal (CPR): 0.712ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.614 -0.172 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 2.262 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.157 2.419 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, routed) 0.000 2.419 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/oserdes_clkdiv + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y4 OUT_FIFO (Prop_out_fifo_RDCLK_Q6[7]) + 0.674 3.093 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/Q6[7] + net (fo=1, routed) 1.007 4.101 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/oserdes_dq[43] + OLOGIC_X1Y50 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[11].oserdes_dq_.sdr.oserdes_dq_i/D4 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.582 11.189 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 13.559 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 13.707 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, routed) 0.412 14.119 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y50 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[11].oserdes_dq_.sdr.oserdes_dq_i/CLKDIV + clock pessimism 0.712 14.831 + clock uncertainty -0.054 14.777 + OLOGIC_X1Y50 OSERDESE2 (Setup_oserdese2_CLKDIV_D4) + -0.625 14.152 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[11].oserdes_dq_.sdr.oserdes_dq_i + ------------------------------------------------------------------- + required time 14.152 + arrival time -4.101 + ------------------------------------------------------------------- + slack 10.051 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.090ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/D2 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv rise@0.000ns - oserdes_clkdiv rise@0.000ns) + Data Path Delay: 0.288ns (logic 0.138ns (47.866%) route 0.150ns (52.134%)) + Logic Levels: 0 + Clock Path Skew: 0.179ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.840ns + Source Clock Delay (SCD): 1.824ns + Clock Pessimism Removal (CPR): -0.163ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.197 -0.351 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.741 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.083 1.824 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, routed) 0.000 1.824 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/oserdes_clkdiv + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y4 OUT_FIFO (Prop_out_fifo_RDCLK_Q2[1]) + 0.138 1.962 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/Q2[1] + net (fo=1, routed) 0.150 2.112 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/oserdes_dq[9] + OLOGIC_X1Y53 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/D2 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.218 -0.567 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.573 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.661 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, routed) 0.179 1.840 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y53 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/CLKDIV + clock pessimism 0.163 2.003 + OLOGIC_X1Y53 OSERDESE2 (Hold_oserdese2_CLKDIV_D2) + 0.019 2.022 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i + ------------------------------------------------------------------- + required time -2.022 + arrival time 2.112 + ------------------------------------------------------------------- + slack 0.090 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clkdiv +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OUT_FIFO/RDCLK n/a 5.000 12.000 7.000 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK +Low Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK +High Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_1 + To Clock: oserdes_clk_1 + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clk_1 +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OSERDESE2/CLK n/a 1.667 3.000 1.333 OLOGIC_X1Y63 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[0].oserdes_dq_.sdr.oserdes_dq_i/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clkdiv_1 + To Clock: oserdes_clkdiv_1 + +Setup : 0 Failing Endpoints, Worst Slack 10.574ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.094ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 3.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 10.574ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[10].oserdes_dq_.sdr.oserdes_dq_i/D1 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv_1 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (oserdes_clkdiv_1 rise@12.000ns - oserdes_clkdiv_1 rise@0.000ns) + Data Path Delay: 1.142ns (logic 0.674ns (59.004%) route 0.468ns (40.996%)) + Logic Levels: 0 + Clock Path Skew: 0.396ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.093ns = ( 14.093 - 12.000 ) + Source Clock Delay (SCD): 2.408ns + Clock Pessimism Removal (CPR): 0.711ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.603 -0.183 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 2.251 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.157 2.408 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, routed) 0.000 2.408 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/oserdes_clkdiv + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y5 OUT_FIFO (Prop_out_fifo_RDCLK_Q5[4]) + 0.674 3.082 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/Q5[4] + net (fo=1, routed) 0.468 3.551 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/oserdes_dq[40] + OLOGIC_X1Y69 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[10].oserdes_dq_.sdr.oserdes_dq_i/D1 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_1 rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.572 11.179 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 13.549 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 13.697 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, routed) 0.396 14.093 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y69 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[10].oserdes_dq_.sdr.oserdes_dq_i/CLKDIV + clock pessimism 0.711 14.804 + clock uncertainty -0.054 14.750 + OLOGIC_X1Y69 OSERDESE2 (Setup_oserdese2_CLKDIV_D1) + -0.625 14.125 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[10].oserdes_dq_.sdr.oserdes_dq_i + ------------------------------------------------------------------- + required time 14.125 + arrival time -3.551 + ------------------------------------------------------------------- + slack 10.574 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.094ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/D2 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv_1 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_1 rise@0.000ns - oserdes_clkdiv_1 rise@0.000ns) + Data Path Delay: 0.288ns (logic 0.138ns (47.866%) route 0.150ns (52.134%)) + Logic Levels: 0 + Clock Path Skew: 0.175ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.827ns + Source Clock Delay (SCD): 1.817ns + Clock Pessimism Removal (CPR): -0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.190 -0.358 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.734 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.083 1.817 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, routed) 0.000 1.817 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/oserdes_clkdiv + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y5 OUT_FIFO (Prop_out_fifo_RDCLK_Q2[1]) + 0.138 1.955 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/Q2[1] + net (fo=1, routed) 0.150 2.105 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/oserdes_dq[9] + OLOGIC_X1Y65 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/D2 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.209 -0.576 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.564 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.652 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, routed) 0.175 1.827 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y65 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/CLKDIV + clock pessimism 0.165 1.992 + OLOGIC_X1Y65 OSERDESE2 (Hold_oserdese2_CLKDIV_D2) + 0.019 2.011 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i + ------------------------------------------------------------------- + required time -2.011 + arrival time 2.105 + ------------------------------------------------------------------- + slack 0.094 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clkdiv_1 +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OUT_FIFO/RDCLK n/a 5.000 12.000 7.000 OUT_FIFO_X1Y5 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK +Low Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y5 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK +High Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y5 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_2 + To Clock: oserdes_clk_2 + +Setup : 0 Failing Endpoints, Worst Slack 1.423ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.413ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.423ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqsts/D1 + (rising edge-triggered cell ODDR clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: oserdes_clk_2 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clk_2 rise@3.000ns - oserdes_clk_2 rise@0.000ns) + Data Path Delay: 1.037ns (logic 0.562ns (54.177%) route 0.475ns (45.823%)) + Logic Levels: 0 + Clock Path Skew: 0.400ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.698ns = ( 5.698 - 3.000 ) + Source Clock Delay (SCD): 3.046ns + Clock Pessimism Removal (CPR): 0.748ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.614 -0.172 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 2.262 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.784 3.046 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLKDELAYED_CTSBUS[0]) + 0.562 3.608 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/CTSBUS[0] + net (fo=2, routed) 0.475 4.084 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/CTSBUS[0] + OLOGIC_X1Y82 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqsts/D1 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clk_2 rise edge) + 3.000 3.000 r + E3 0.000 3.000 r CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 4.411 r input_clock/O + net (fo=1, routed) 1.162 5.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -1.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -0.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -0.021 r sys_buffer/O + net (fo=1, routed) 1.544 1.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 1.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.582 2.189 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 4.559 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.739 5.298 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + net (fo=2, routed) 0.400 5.698 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/oserdes_clk_delayed + OLOGIC_X1Y82 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqsts/C + clock pessimism 0.748 6.446 + clock uncertainty -0.054 6.392 + OLOGIC_X1Y82 ODDR (Setup_oddr_C_D1) -0.885 5.507 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqsts + ------------------------------------------------------------------- + required time 5.507 + arrival time -4.084 + ------------------------------------------------------------------- + slack 1.423 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.413ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqs/D2 + (rising edge-triggered cell ODDR clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: oserdes_clk_2 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clk_2 rise@0.000ns - oserdes_clk_2 rise@0.000ns) + Data Path Delay: 0.496ns (logic 0.346ns (69.715%) route 0.150ns (30.285%)) + Logic Levels: 0 + Clock Path Skew: 0.176ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 2.419ns + Source Clock Delay (SCD): 2.371ns + Clock Pessimism Removal (CPR): -0.128ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.197 -0.351 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.741 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.630 2.371 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLKDELAYED_DQSBUS[1]) + 0.346 2.717 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/DQSBUS[1] + net (fo=1, routed) 0.150 2.868 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/DQSBUS[1] + OLOGIC_X1Y82 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqs/D2 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clk_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.218 -0.567 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.573 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.670 2.243 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + net (fo=2, routed) 0.176 2.419 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/oserdes_clk_delayed + OLOGIC_X1Y82 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqs/C + clock pessimism 0.128 2.547 + OLOGIC_X1Y82 ODDR (Hold_oddr_C_D2) -0.093 2.454 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqs + ------------------------------------------------------------------- + required time -2.454 + arrival time 2.868 + ------------------------------------------------------------------- + slack 0.413 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clk_2 +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OSERDESE2/CLK n/a 1.667 3.000 1.333 OLOGIC_X1Y76 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[1].oserdes_dq_.ddr.oserdes_dq_i/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clkdiv_2 + To Clock: oserdes_clkdiv_2 + +Setup : 0 Failing Endpoints, Worst Slack 4.245ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.092ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 0.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 4.245ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D2 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_2 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 6.000ns (oserdes_clkdiv_2 rise@6.000ns - oserdes_clkdiv_2 rise@0.000ns) + Data Path Delay: 1.483ns (logic 0.674ns (45.456%) route 0.809ns (54.544%)) + Logic Levels: 0 + Clock Path Skew: 0.407ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.114ns = ( 8.114 - 6.000 ) + Source Clock Delay (SCD): 2.419ns + Clock Pessimism Removal (CPR): 0.712ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.614 -0.172 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 2.262 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.157 2.419 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, routed) 0.000 2.419 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/oserdes_clkdiv + OUT_FIFO_X1Y6 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y6 OUT_FIFO (Prop_out_fifo_RDCLK_Q2[1]) + 0.674 3.093 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/Q2[1] + net (fo=1, routed) 0.809 3.902 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/of_dqbus[5] + OLOGIC_X1Y77 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D2 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_2 rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, routed) 1.162 8.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 1.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 2.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 2.979 r sys_buffer/O + net (fo=1, routed) 1.544 4.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 4.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.582 5.189 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 7.559 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 7.707 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, routed) 0.407 8.114 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y77 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV + clock pessimism 0.712 8.826 + clock uncertainty -0.054 8.772 + OLOGIC_X1Y77 OSERDESE2 (Setup_oserdese2_CLKDIV_D2) + -0.625 8.147 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i + ------------------------------------------------------------------- + required time 8.147 + arrival time -3.902 + ------------------------------------------------------------------- + slack 4.245 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.092ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D3 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_2 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_2 rise@0.000ns - oserdes_clkdiv_2 rise@0.000ns) + Data Path Delay: 0.288ns (logic 0.138ns (47.866%) route 0.150ns (52.134%)) + Logic Levels: 0 + Clock Path Skew: 0.177ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.838ns + Source Clock Delay (SCD): 1.824ns + Clock Pessimism Removal (CPR): -0.163ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.197 -0.351 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.741 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.083 1.824 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, routed) 0.000 1.824 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/oserdes_clkdiv + OUT_FIFO_X1Y6 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y6 OUT_FIFO (Prop_out_fifo_RDCLK_Q2[2]) + 0.138 1.962 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/Q2[2] + net (fo=1, routed) 0.150 2.112 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/of_dqbus[6] + OLOGIC_X1Y77 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D3 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.218 -0.567 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.573 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.661 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, routed) 0.177 1.838 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y77 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV + clock pessimism 0.163 2.001 + OLOGIC_X1Y77 OSERDESE2 (Hold_oserdese2_CLKDIV_D3) + 0.019 2.020 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i + ------------------------------------------------------------------- + required time -2.020 + arrival time 2.112 + ------------------------------------------------------------------- + slack 0.092 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clkdiv_2 +Waveform(ns): { 0.000 3.000 } +Period(ns): 6.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OUT_FIFO/RDCLK n/a 5.000 6.000 1.000 OUT_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK +Low Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 3.000 0.850 OUT_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK +High Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 3.000 0.850 OUT_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_3 + To Clock: oserdes_clk_3 + +Setup : 0 Failing Endpoints, Worst Slack 1.439ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.408ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.439ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqsts/D1 + (rising edge-triggered cell ODDR clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: oserdes_clk_3 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clk_3 rise@3.000ns - oserdes_clk_3 rise@0.000ns) + Data Path Delay: 1.037ns (logic 0.562ns (54.177%) route 0.475ns (45.823%)) + Logic Levels: 0 + Clock Path Skew: 0.416ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.704ns = ( 5.704 - 3.000 ) + Source Clock Delay (SCD): 3.035ns + Clock Pessimism Removal (CPR): 0.747ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.603 -0.183 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 2.251 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.784 3.035 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLKDELAYED_CTSBUS[0]) + 0.562 3.597 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/CTSBUS[0] + net (fo=2, routed) 0.475 4.073 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/CTSBUS[0] + OLOGIC_X1Y94 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqsts/D1 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clk_3 rise edge) + 3.000 3.000 r + E3 0.000 3.000 r CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 4.411 r input_clock/O + net (fo=1, routed) 1.162 5.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -1.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -0.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -0.021 r sys_buffer/O + net (fo=1, routed) 1.544 1.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 1.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.572 2.179 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 4.549 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.739 5.288 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + net (fo=2, routed) 0.416 5.704 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/oserdes_clk_delayed + OLOGIC_X1Y94 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqsts/C + clock pessimism 0.747 6.451 + clock uncertainty -0.054 6.397 + OLOGIC_X1Y94 ODDR (Setup_oddr_C_D1) -0.885 5.512 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqsts + ------------------------------------------------------------------- + required time 5.512 + arrival time -4.073 + ------------------------------------------------------------------- + slack 1.439 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.408ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqs/D2 + (rising edge-triggered cell ODDR clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: oserdes_clk_3 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clk_3 rise@0.000ns - oserdes_clk_3 rise@0.000ns) + Data Path Delay: 0.496ns (logic 0.346ns (69.715%) route 0.150ns (30.285%)) + Logic Levels: 0 + Clock Path Skew: 0.181ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 2.415ns + Source Clock Delay (SCD): 2.364ns + Clock Pessimism Removal (CPR): -0.130ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.190 -0.358 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.734 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.630 2.364 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLKDELAYED_DQSBUS[1]) + 0.346 2.710 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/DQSBUS[1] + net (fo=1, routed) 0.150 2.861 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/DQSBUS[1] + OLOGIC_X1Y94 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqs/D2 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clk_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.209 -0.576 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.564 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.670 2.234 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + net (fo=2, routed) 0.181 2.415 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/oserdes_clk_delayed + OLOGIC_X1Y94 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqs/C + clock pessimism 0.130 2.545 + OLOGIC_X1Y94 ODDR (Hold_oddr_C_D2) -0.093 2.452 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqs + ------------------------------------------------------------------- + required time -2.452 + arrival time 2.861 + ------------------------------------------------------------------- + slack 0.408 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clk_3 +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OSERDESE2/CLK n/a 1.667 3.000 1.333 OLOGIC_X1Y88 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[1].oserdes_dq_.ddr.oserdes_dq_i/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clkdiv_3 + To Clock: oserdes_clkdiv_3 + +Setup : 0 Failing Endpoints, Worst Slack 4.597ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.086ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 0.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 4.597ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/D1 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_3 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 6.000ns (oserdes_clkdiv_3 rise@6.000ns - oserdes_clkdiv_3 rise@0.000ns) + Data Path Delay: 1.142ns (logic 0.674ns (59.004%) route 0.468ns (40.996%)) + Logic Levels: 0 + Clock Path Skew: 0.419ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.116ns = ( 8.116 - 6.000 ) + Source Clock Delay (SCD): 2.408ns + Clock Pessimism Removal (CPR): 0.711ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.603 -0.183 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 2.251 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.157 2.408 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, routed) 0.000 2.408 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/oserdes_clkdiv + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y7 OUT_FIFO (Prop_out_fifo_RDCLK_Q6[0]) + 0.674 3.082 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/Q6[0] + net (fo=1, routed) 0.468 3.551 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/of_dqbus[20] + OLOGIC_X1Y95 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/D1 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_3 rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, routed) 1.162 8.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 1.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 2.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 2.979 r sys_buffer/O + net (fo=1, routed) 1.544 4.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 4.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.572 5.179 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 7.549 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 7.697 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, routed) 0.419 8.116 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y95 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV + clock pessimism 0.711 8.827 + clock uncertainty -0.054 8.773 + OLOGIC_X1Y95 OSERDESE2 (Setup_oserdese2_CLKDIV_D1) + -0.625 8.148 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i + ------------------------------------------------------------------- + required time 8.148 + arrival time -3.551 + ------------------------------------------------------------------- + slack 4.597 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.086ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D2 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_3 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_3 rise@0.000ns - oserdes_clkdiv_3 rise@0.000ns) + Data Path Delay: 0.288ns (logic 0.138ns (47.866%) route 0.150ns (52.134%)) + Logic Levels: 0 + Clock Path Skew: 0.183ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.835ns + Source Clock Delay (SCD): 1.817ns + Clock Pessimism Removal (CPR): -0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.190 -0.358 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.734 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.083 1.817 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, routed) 0.000 1.817 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/oserdes_clkdiv + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y7 OUT_FIFO (Prop_out_fifo_RDCLK_Q2[1]) + 0.138 1.955 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/Q2[1] + net (fo=1, routed) 0.150 2.105 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/of_dqbus[5] + OLOGIC_X1Y89 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D2 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.209 -0.576 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.564 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.652 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, routed) 0.183 1.835 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y89 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV + clock pessimism 0.165 2.000 + OLOGIC_X1Y89 OSERDESE2 (Hold_oserdese2_CLKDIV_D2) + 0.019 2.019 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i + ------------------------------------------------------------------- + required time -2.019 + arrival time 2.105 + ------------------------------------------------------------------- + slack 0.086 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clkdiv_3 +Waveform(ns): { 0.000 3.000 } +Period(ns): 6.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OUT_FIFO/RDCLK n/a 5.000 6.000 1.000 OUT_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK +Low Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 3.000 0.850 OUT_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK +High Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 3.000 0.850 OUT_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: pll_clk3_out + To Clock: pll_clk3_out + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 3.000ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: pll_clk3_out +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFH/I n/a 2.155 12.000 9.845 BUFHCE_X1Y12 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/I +Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 12.000 88.000 MMCME2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKIN1 +Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 3.000 6.000 3.000 MMCME2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKIN1 +High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 3.000 6.000 3.000 MMCME2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKIN1 + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_pll_i + To Clock: clk_pll_i + +Setup : 0 Failing Endpoints, Worst Slack 2.959ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.027ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 3.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 2.959ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_w_channel_0/wready_reg/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[24]/CE + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: clk_pll_i + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (clk_pll_i rise@12.000ns - clk_pll_i rise@0.000ns) + Data Path Delay: 8.555ns (logic 0.715ns (8.357%) route 7.840ns (91.643%)) + Logic Levels: 1 (LUT4=1) + Clock Path Skew: -0.214ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.671ns = ( 12.671 - 12.000 ) + Source Clock Delay (SCD): 1.534ns + Clock Pessimism Removal (CPR): 0.649ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.712 1.534 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_w_channel_0/wready_reg_rep__0_0 + SLICE_X77Y88 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_w_channel_0/wready_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X77Y88 FDRE (Prop_fdre_C_Q) 0.419 1.953 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_w_channel_0/wready_reg/Q + net (fo=145, routed) 4.243 6.196 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/m_axi_wready + SLICE_X89Y111 LUT4 (Prop_lut4_I1_O) 0.296 6.492 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gc0.count_d1[3]_i_1__2/O + net (fo=152, routed) 3.598 10.090 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[0]_0[0] + SLICE_X68Y106 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[24]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 11.812 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 11.893 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 12.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 9.442 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 11.081 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 11.172 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.499 12.671 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/m_aclk + SLICE_X68Y106 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[24]/C + clock pessimism 0.649 13.321 + clock uncertainty -0.067 13.254 + SLICE_X68Y106 FDRE (Setup_fdre_C_CE) -0.205 13.049 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[24] + ------------------------------------------------------------------- + required time 13.049 + arrival time -10.090 + ------------------------------------------------------------------- + slack 2.959 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.027ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/smallest_reg[0][4]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/gen_final_tap[0].final_val_reg[0][4]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: clk_pll_i + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_pll_i rise@0.000ns - clk_pll_i rise@0.000ns) + Data Path Delay: 0.302ns (logic 0.128ns (42.423%) route 0.174ns (57.577%)) + Logic Levels: 0 + Clock Path Skew: 0.266ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.192ns + Source Clock Delay (SCD): 0.136ns + Clock Pessimism Removal (CPR): -0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 -0.154 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 -0.134 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 -0.949 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 -0.450 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.424 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.560 0.136 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/dqs_count_r_reg[0]_rep_0 + SLICE_X53Y60 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/smallest_reg[0][4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X53Y60 FDRE (Prop_fdre_C_Q) 0.128 0.264 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/smallest_reg[0][4]/Q + net (fo=2, routed) 0.174 0.437 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/smallest_reg[0]_4[4] + SLICE_X50Y61 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/gen_final_tap[0].final_val_reg[0][4]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.437 -0.348 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.043 -0.305 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.494 0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.400 -1.211 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.544 -0.668 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -0.639 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.831 0.192 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/dqs_count_r_reg[0]_rep_0 + SLICE_X50Y61 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/gen_final_tap[0].final_val_reg[0][4]/C + clock pessimism 0.210 0.402 + SLICE_X50Y61 FDRE (Hold_fdre_C_D) 0.009 0.411 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/gen_final_tap[0].final_val_reg[0][4] + ------------------------------------------------------------------- + required time -0.411 + arrival time 0.437 + ------------------------------------------------------------------- + slack 0.027 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: clk_pll_i +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OUT_FIFO/WRCLK n/a 5.000 12.000 7.000 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/WRCLK +Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 12.000 88.000 MMCME2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBIN +Low Pulse Width Slow OUT_FIFO/WRCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/WRCLK +High Pulse Width Slow OUT_FIFO/WRCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/WRCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: pll_clkfbout + To Clock: pll_clkfbout + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 4.751ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: pll_clkfbout +Waveform(ns): { 0.000 3.000 } +Period(ns): 6.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a PLLE2_ADV/CLKFBOUT n/a 1.249 6.000 4.751 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT +Max Period n/a PLLE2_ADV/CLKFBIN n/a 52.633 6.000 46.633 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBIN + + + +--------------------------------------------------------------------------------------------------- +From Clock: sync_pulse + To Clock: sync_pulse + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.750ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: sync_pulse +Waveform(ns): { 1.312 4.312 } +Period(ns): 48.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a PLLE2_ADV/CLKOUT2 n/a 1.249 48.000 46.751 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 +Max Period n/a PLLE2_ADV/CLKOUT2 n/a 160.000 48.000 112.000 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 +High Pulse Width Slow PHASER_OUT_PHY/SYNCIN n/a 1.250 3.000 1.750 PHASER_OUT_PHY_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/SYNCIN + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_pll_i + To Clock: core_raw + +Setup : 0 Failing Endpoints, Worst Slack 10.662ns, Total Violation 0.000ns +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 10.662ns (required time - arrival time) + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: core_raw + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (MaxDelay Path 12.000ns) + Data Path Delay: 1.243ns (logic 0.456ns (36.683%) route 0.787ns (63.317%)) + Logic Levels: 0 + Timing Exception: MaxDelay Path 12.000ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + SLICE_X67Y92 0.000 0.000 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C + SLICE_X67Y92 FDRE (Prop_fdre_C_Q) 0.456 0.456 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.787 1.243 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[0] + SLICE_X64Y93 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + ------------------------------------------------------------------- ------------------- + + max delay 12.000 12.000 + SLICE_X64Y93 FDRE (Setup_fdre_C_D) -0.095 11.905 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + ------------------------------------------------------------------- + required time 11.905 + arrival time -1.243 + ------------------------------------------------------------------- + slack 10.662 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_pll_i + To Clock: ref_raw + +Setup : 0 Failing Endpoints, Worst Slack 17.427ns, Total Violation 0.000ns +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 17.427ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg/D + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: ref_raw + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (MaxDelay Path 20.000ns) + Data Path Delay: 2.492ns (logic 0.456ns (18.300%) route 2.036ns (81.700%)) + Logic Levels: 0 + Timing Exception: MaxDelay Path 20.000ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + SLICE_X69Y117 0.000 0.000 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + SLICE_X69Y117 FDPE (Prop_fdpe_C_Q) 0.456 0.456 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/Q + net (fo=50, routed) 2.036 2.492 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg_0 + SLICE_X32Y125 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg/D + ------------------------------------------------------------------- ------------------- + + max delay 20.000 20.000 + SLICE_X32Y125 FDRE (Setup_fdre_C_D) -0.081 19.919 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg + ------------------------------------------------------------------- + required time 19.919 + arrival time -2.492 + ------------------------------------------------------------------- + slack 17.427 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_pll_i + To Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk + +Setup : 0 Failing Endpoints, Worst Slack 10.088ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 45.348ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 10.088ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq/DDLY + (falling edge-triggered cell ISERDESE2 clocked by u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 16.500ns (u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk fall@16.500ns - clk_pll_i rise@0.000ns) + Data Path Delay: 6.328ns (logic 3.867ns (61.105%) route 2.461ns (38.895%)) + Logic Levels: 2 (IBUF_INTERMDISABLE=1 IDELAYE2=1) + Clock Path Skew: 0.301ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.219ns = ( 2.719 - 1.500 ) + Source Clock Delay (SCD): 1.525ns + Clock Pessimism Removal (CPR): 0.607ns + Clock Uncertainty: 0.220ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.154ns + Timing Exception: MultiCycle Path Setup -end 6 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.703 1.525 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/last_master_r_reg[2] + SLICE_X75Y69 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X75Y69 FDRE (Prop_fdre_C_Q) 0.456 1.981 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/Q + net (fo=40, routed) 2.461 4.443 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[12].u_iobuf_dq/IBUFDISABLE + V1 IBUF_INTERMDISABLE (Prop_ibuf_intermdisable_IBUFDISABLE_O) + 2.596 7.039 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[12].u_iobuf_dq/IBUF/O + net (fo=2, routed) 0.000 7.039 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/mem_dq_in[7] + IDELAY_X1Y85 IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT) + 0.815 7.854 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.idelay_dq.idelaye2/DATAOUT + net (fo=1, routed) 0.000 7.854 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/data_in_dly_8 + ILOGIC_X1Y85 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq/DDLY + ------------------------------------------------------------------- ------------------- + + (clock u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk fall edge) + 16.500 16.500 f + E3 0.000 16.500 f CLK100MHZ (IN) + net (fo=0) 0.000 16.500 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 17.911 f input_clock/O + net (fo=1, routed) 1.162 19.073 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 11.749 f clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 13.388 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 13.479 f sys_buffer/O + net (fo=1, routed) 1.544 15.024 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.083 15.107 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.576 15.683 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.624 17.307 f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + net (fo=16, routed) 0.412 17.719 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/CLKB0 + ILOGIC_X1Y85 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq/CLKB (IS_INVERTED) + clock pessimism 0.607 18.327 + clock uncertainty -0.220 18.107 + ILOGIC_X1Y85 ISERDESE2 (Setup_iserdese2_CLKB_DDLY) + -0.165 17.942 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq + ------------------------------------------------------------------- + required time 17.942 + arrival time -7.854 + ------------------------------------------------------------------- + slack 10.088 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 45.348ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq/DDLY + (rising edge-triggered cell ISERDESE2 clocked by u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: -45.000ns (u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk rise@15.000ns - clk_pll_i rise@60.000ns) + Data Path Delay: 1.688ns (logic 1.068ns (63.257%) route 0.620ns (36.743%)) + Logic Levels: 2 (IBUF_INTERMDISABLE=1 IDELAYE2=1) + Clock Path Skew: 1.065ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.990ns + Source Clock Delay (SCD): 0.163ns + Clock Pessimism Removal (CPR): -0.237ns + Clock Uncertainty: 0.220ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.154ns + Timing Exception: MultiCycle Path Setup -end 6 Hold -start 5 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 60.000 60.000 r + E3 0.000 60.000 r CLK100MHZ (IN) + net (fo=0) 0.000 60.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 60.250 r input_clock/O + net (fo=1, routed) 0.440 60.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 58.311 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 58.810 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 58.836 r sys_buffer/O + net (fo=1, routed) 0.566 59.402 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 59.452 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 59.846 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 59.866 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 60.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 59.051 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 59.550 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 59.576 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.587 60.163 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/last_master_r_reg[2] + SLICE_X75Y69 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X75Y69 FDRE (Prop_fdre_C_Q) 0.141 60.304 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/Q + net (fo=40, routed) 0.620 60.924 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[13].u_iobuf_dq/IBUFDISABLE + T3 IBUF_INTERMDISABLE (Prop_ibuf_intermdisable_IBUFDISABLE_O) + 0.684 61.608 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[13].u_iobuf_dq/IBUF/O + net (fo=2, routed) 0.000 61.608 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/mem_dq_in[1] + IDELAY_X1Y77 IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT) + 0.243 61.851 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[2].iserdes_dq_.idelay_dq.idelaye2/DATAOUT + net (fo=1, routed) 0.000 61.851 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/data_in_dly_2 + ILOGIC_X1Y77 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq/DDLY + ------------------------------------------------------------------- ------------------- + + (clock u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk rise edge) + 15.000 15.000 r + E3 0.000 15.000 r CLK100MHZ (IN) + net (fo=0) 0.000 15.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 15.438 r input_clock/O + net (fo=1, routed) 0.480 15.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 12.755 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 13.298 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 13.327 r sys_buffer/O + net (fo=1, routed) 0.835 14.162 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.053 14.215 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.217 14.432 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.381 15.812 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + net (fo=16, routed) 0.178 15.990 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq_0 + ILOGIC_X1Y77 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq/CLK + clock pessimism 0.237 16.227 + clock uncertainty 0.220 16.447 + ILOGIC_X1Y77 ISERDESE2 (Hold_iserdese2_CLK_DDLY) + 0.056 16.503 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq + ------------------------------------------------------------------- + required time -16.503 + arrival time 61.851 + ------------------------------------------------------------------- + slack 45.348 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_pll_i + To Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk + +Setup : 0 Failing Endpoints, Worst Slack 8.404ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 46.023ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 8.404ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq/DDLY + (falling edge-triggered cell ISERDESE2 clocked by u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 16.500ns (u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk fall@16.500ns - clk_pll_i rise@0.000ns) + Data Path Delay: 8.019ns (logic 3.867ns (48.222%) route 4.152ns (51.778%)) + Logic Levels: 2 (IBUF_INTERMDISABLE=1 IDELAYE2=1) + Clock Path Skew: 0.308ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.226ns = ( 2.726 - 1.500 ) + Source Clock Delay (SCD): 1.525ns + Clock Pessimism Removal (CPR): 0.607ns + Clock Uncertainty: 0.220ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.154ns + Timing Exception: MultiCycle Path Setup -end 6 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.703 1.525 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/last_master_r_reg[2] + SLICE_X75Y69 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X75Y69 FDRE (Prop_fdre_C_Q) 0.456 1.981 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/Q + net (fo=40, routed) 4.152 6.133 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[5].u_iobuf_dq/IBUFDISABLE + M1 IBUF_INTERMDISABLE (Prop_ibuf_intermdisable_IBUFDISABLE_O) + 2.596 8.729 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[5].u_iobuf_dq/IBUF/O + net (fo=2, routed) 0.000 8.729 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/mem_dq_in[7] + IDELAY_X1Y97 IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT) + 0.815 9.544 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.idelay_dq.idelaye2/DATAOUT + net (fo=1, routed) 0.000 9.544 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/data_in_dly_8 + ILOGIC_X1Y97 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq/DDLY + ------------------------------------------------------------------- ------------------- + + (clock u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk fall edge) + 16.500 16.500 f + E3 0.000 16.500 f CLK100MHZ (IN) + net (fo=0) 0.000 16.500 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 17.911 f input_clock/O + net (fo=1, routed) 1.162 19.073 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 11.749 f clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 13.388 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 13.479 f sys_buffer/O + net (fo=1, routed) 1.544 15.024 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.083 15.107 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.566 15.673 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.624 17.297 f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + net (fo=16, routed) 0.429 17.726 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/CLKB0_4 + ILOGIC_X1Y97 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq/CLKB (IS_INVERTED) + clock pessimism 0.607 18.334 + clock uncertainty -0.220 18.114 + ILOGIC_X1Y97 ISERDESE2 (Setup_iserdese2_CLKB_DDLY) + -0.165 17.949 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq + ------------------------------------------------------------------- + required time 17.949 + arrival time -9.544 + ------------------------------------------------------------------- + slack 8.404 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 46.023ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/DDLY + (rising edge-triggered cell ISERDESE2 clocked by u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: -45.000ns (u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk rise@15.000ns - clk_pll_i rise@60.000ns) + Data Path Delay: 2.362ns (logic 1.068ns (45.210%) route 1.294ns (54.790%)) + Logic Levels: 2 (IBUF_INTERMDISABLE=1 IDELAYE2=1) + Clock Path Skew: 1.064ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.989ns + Source Clock Delay (SCD): 0.163ns + Clock Pessimism Removal (CPR): -0.237ns + Clock Uncertainty: 0.220ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.154ns + Timing Exception: MultiCycle Path Setup -end 6 Hold -start 5 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 60.000 60.000 r + E3 0.000 60.000 r CLK100MHZ (IN) + net (fo=0) 0.000 60.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 60.250 r input_clock/O + net (fo=1, routed) 0.440 60.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 58.311 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 58.810 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 58.836 r sys_buffer/O + net (fo=1, routed) 0.566 59.402 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 59.452 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 59.846 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 59.866 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 60.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 59.051 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 59.550 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 59.576 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.587 60.163 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/last_master_r_reg[2] + SLICE_X75Y69 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X75Y69 FDRE (Prop_fdre_C_Q) 0.141 60.304 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/Q + net (fo=40, routed) 1.294 61.598 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[3].u_iobuf_dq/IBUFDISABLE + L6 IBUF_INTERMDISABLE (Prop_ibuf_intermdisable_IBUFDISABLE_O) + 0.684 62.282 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[3].u_iobuf_dq/IBUF/O + net (fo=2, routed) 0.000 62.282 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/mem_dq_in[0] + IDELAY_X1Y88 IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT) + 0.243 62.525 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.idelay_dq.idelaye2/DATAOUT + net (fo=1, routed) 0.000 62.525 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/data_in_dly_1 + ILOGIC_X1Y88 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/DDLY + ------------------------------------------------------------------- ------------------- + + (clock u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk rise edge) + 15.000 15.000 r + E3 0.000 15.000 r CLK100MHZ (IN) + net (fo=0) 0.000 15.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 15.438 r input_clock/O + net (fo=1, routed) 0.480 15.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 12.755 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 13.298 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 13.327 r sys_buffer/O + net (fo=1, routed) 0.835 14.162 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.053 14.215 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.211 14.426 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.381 15.806 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + net (fo=16, routed) 0.183 15.989 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq_0 + ILOGIC_X1Y88 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLK + clock pessimism 0.237 16.226 + clock uncertainty 0.220 16.446 + ILOGIC_X1Y88 ISERDESE2 (Hold_iserdese2_CLK_DDLY) + 0.056 16.502 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq + ------------------------------------------------------------------- + required time -16.502 + arrival time 62.525 + ------------------------------------------------------------------- + slack 46.023 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: sync_pulse + To Clock: mem_refclk + +Setup : 0 Failing Endpoints, Worst Slack 1.276ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.909ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.276ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 + (clock source 'sync_pulse' {rise@1.312ns fall@4.312ns period=48.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/SYNCIN + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: mem_refclk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 1.687ns (mem_refclk rise@6.000ns - sync_pulse fall@4.312ns) + Data Path Delay: 0.621ns (logic 0.000ns (0.000%) route 0.621ns (100.000%)) + Logic Levels: 0 + Clock Path Skew: 0.589ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.804ns = ( 5.196 - 6.000 ) + Source Clock Delay (SCD): -0.786ns = ( 3.527 - 4.312 ) + Clock Pessimism Removal (CPR): 0.607ns + Clock Uncertainty: 0.198ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.139ns + Phase Error (PE): 0.120ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sync_pulse fall edge) + 4.312 4.312 f + E3 0.000 4.312 f CLK100MHZ (IN) + net (fo=0) 0.000 4.312 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 5.794 f input_clock/O + net (fo=1, routed) 1.233 7.027 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -0.043 f clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 1.676 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 1.772 f sys_buffer/O + net (fo=1, routed) 1.666 3.439 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + 0.088 3.527 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 + net (fo=7, routed) 0.621 4.148 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/sync_pulse + PHY_CONTROL_X1Y1 PHY_CONTROL f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/SYNCIN + ------------------------------------------------------------------- ------------------- + + (clock mem_refclk rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, routed) 1.162 8.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 1.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 2.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 2.979 r sys_buffer/O + net (fo=1, routed) 1.544 4.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 4.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.589 5.196 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + clock pessimism 0.607 5.803 + clock uncertainty -0.198 5.605 + PHY_CONTROL_X1Y1 PHY_CONTROL (Setup_phy_control_MEMREFCLK_SYNCIN) + -0.182 5.423 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i + ------------------------------------------------------------------- + required time 5.423 + arrival time -4.148 + ------------------------------------------------------------------- + slack 1.276 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.909ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 + (clock source 'sync_pulse' {rise@1.312ns fall@4.312ns period=48.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/SYNCIN + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: mem_refclk + Path Type: Hold (Min at Slow Process Corner) + Requirement: -1.312ns (mem_refclk rise@0.000ns - sync_pulse rise@1.312ns) + Data Path Delay: 0.589ns (logic 0.000ns (0.000%) route 0.589ns (100.000%)) + Logic Levels: 0 + Clock Path Skew: 0.621ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.165ns + Source Clock Delay (SCD): -1.393ns = ( -0.081 - 1.312 ) + Clock Pessimism Removal (CPR): 0.607ns + Clock Uncertainty: 0.198ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.139ns + Phase Error (PE): 0.120ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sync_pulse rise edge) + 1.312 1.312 r + E3 0.000 1.312 r CLK100MHZ (IN) + net (fo=0) 0.000 1.312 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 2.724 r input_clock/O + net (fo=1, routed) 1.162 3.886 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -3.438 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -1.799 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -1.708 r sys_buffer/O + net (fo=1, routed) 1.544 -0.164 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + 0.083 -0.081 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 + net (fo=7, routed) 0.589 0.508 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/sync_pulse + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/SYNCIN + ------------------------------------------------------------------- ------------------- + + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.621 -0.165 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + clock pessimism -0.607 -0.772 + clock uncertainty 0.198 -0.574 + PHY_CONTROL_X1Y1 PHY_CONTROL (Hold_phy_control_MEMREFCLK_SYNCIN) + 0.174 -0.400 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i + ------------------------------------------------------------------- + required time 0.400 + arrival time 0.508 + ------------------------------------------------------------------- + slack 0.909 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk + To Clock: oserdes_clkdiv + +Setup : 0 Failing Endpoints, Worst Slack 2.105ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.095ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 2.105ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clkdiv rise@12.000ns - oserdes_clk rise@9.000ns) + Data Path Delay: 0.338ns (logic 0.338ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.148ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.707ns = ( 13.707 - 12.000 ) + Source Clock Delay (SCD): 2.262ns = ( 11.262 - 9.000 ) + Clock Pessimism Removal (CPR): 0.703ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.081ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk rise edge) + 9.000 9.000 r + E3 0.000 9.000 r CLK100MHZ (IN) + net (fo=0) 0.000 9.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 10.482 r input_clock/O + net (fo=1, routed) 1.233 11.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 4.645 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 6.364 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 6.460 r sys_buffer/O + net (fo=1, routed) 1.666 8.126 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 8.214 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.614 8.828 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 11.262 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.338 11.600 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/RDENABLE + net (fo=1, routed) 0.000 11.600 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/po_rd_enable + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.582 11.189 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 13.559 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 13.707 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, routed) 0.000 13.707 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/oserdes_clkdiv + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + clock pessimism 0.703 14.410 + clock uncertainty -0.054 14.356 + OUT_FIFO_X1Y4 OUT_FIFO (Setup_out_fifo_RDCLK_RDEN) + -0.651 13.705 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo + ------------------------------------------------------------------- + required time 13.705 + arrival time -11.600 + ------------------------------------------------------------------- + slack 2.105 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.095ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv rise@0.000ns - oserdes_clk rise@0.000ns) + Data Path Delay: 0.172ns (logic 0.172ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.088ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.661ns + Source Clock Delay (SCD): 1.741ns + Clock Pessimism Removal (CPR): -0.168ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.197 -0.351 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.741 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.172 1.913 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/RDENABLE + net (fo=1, routed) 0.000 1.913 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/po_rd_enable + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.218 -0.567 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.573 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.661 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, routed) 0.000 1.661 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/oserdes_clkdiv + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + clock pessimism 0.168 1.829 + OUT_FIFO_X1Y4 OUT_FIFO (Hold_out_fifo_RDCLK_RDEN) + -0.011 1.818 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo + ------------------------------------------------------------------- + required time -1.818 + arrival time 1.913 + ------------------------------------------------------------------- + slack 0.095 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_1 + To Clock: oserdes_clkdiv_1 + +Setup : 0 Failing Endpoints, Worst Slack 2.105ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.095ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 2.105ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_1 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv_1 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clkdiv_1 rise@12.000ns - oserdes_clk_1 rise@9.000ns) + Data Path Delay: 0.338ns (logic 0.338ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.148ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.697ns = ( 13.697 - 12.000 ) + Source Clock Delay (SCD): 2.251ns = ( 11.251 - 9.000 ) + Clock Pessimism Removal (CPR): 0.702ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.081ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_1 rise edge) + 9.000 9.000 r + E3 0.000 9.000 r CLK100MHZ (IN) + net (fo=0) 0.000 9.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 10.482 r input_clock/O + net (fo=1, routed) 1.233 11.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 4.645 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 6.364 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 6.460 r sys_buffer/O + net (fo=1, routed) 1.666 8.126 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 8.214 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.603 8.817 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 11.251 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.338 11.589 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/RDENABLE + net (fo=1, routed) 0.000 11.589 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/po_rd_enable + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_1 rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.572 11.179 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 13.549 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 13.697 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, routed) 0.000 13.697 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/oserdes_clkdiv + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + clock pessimism 0.702 14.399 + clock uncertainty -0.054 14.345 + OUT_FIFO_X1Y5 OUT_FIFO (Setup_out_fifo_RDCLK_RDEN) + -0.651 13.694 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo + ------------------------------------------------------------------- + required time 13.694 + arrival time -11.589 + ------------------------------------------------------------------- + slack 2.105 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.095ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_1 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv_1 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_1 rise@0.000ns - oserdes_clk_1 rise@0.000ns) + Data Path Delay: 0.172ns (logic 0.172ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.088ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.652ns + Source Clock Delay (SCD): 1.734ns + Clock Pessimism Removal (CPR): -0.170ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.190 -0.358 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.734 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.172 1.906 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/RDENABLE + net (fo=1, routed) 0.000 1.906 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/po_rd_enable + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.209 -0.576 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.564 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.652 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, routed) 0.000 1.652 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/oserdes_clkdiv + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + clock pessimism 0.170 1.822 + OUT_FIFO_X1Y5 OUT_FIFO (Hold_out_fifo_RDCLK_RDEN) + -0.011 1.811 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo + ------------------------------------------------------------------- + required time -1.811 + arrival time 1.906 + ------------------------------------------------------------------- + slack 0.095 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_2 + To Clock: oserdes_clkdiv_2 + +Setup : 0 Failing Endpoints, Worst Slack 2.105ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.095ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 2.105ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_2 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clkdiv_2 rise@6.000ns - oserdes_clk_2 rise@3.000ns) + Data Path Delay: 0.338ns (logic 0.338ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.148ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.707ns = ( 7.707 - 6.000 ) + Source Clock Delay (SCD): 2.262ns = ( 5.262 - 3.000 ) + Clock Pessimism Removal (CPR): 0.703ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.081ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_2 rise edge) + 3.000 3.000 r + E3 0.000 3.000 r CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 4.482 r input_clock/O + net (fo=1, routed) 1.233 5.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -1.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 0.364 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 0.460 r sys_buffer/O + net (fo=1, routed) 1.666 2.126 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 2.214 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.614 2.828 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 5.262 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.338 5.600 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/RDENABLE + net (fo=1, routed) 0.000 5.600 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/po_rd_enable + OUT_FIFO_X1Y6 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_2 rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, routed) 1.162 8.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 1.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 2.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 2.979 r sys_buffer/O + net (fo=1, routed) 1.544 4.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 4.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.582 5.189 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 7.559 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 7.707 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, routed) 0.000 7.707 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/oserdes_clkdiv + OUT_FIFO_X1Y6 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + clock pessimism 0.703 8.410 + clock uncertainty -0.054 8.356 + OUT_FIFO_X1Y6 OUT_FIFO (Setup_out_fifo_RDCLK_RDEN) + -0.651 7.705 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo + ------------------------------------------------------------------- + required time 7.705 + arrival time -5.600 + ------------------------------------------------------------------- + slack 2.105 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.095ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_2 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_2 rise@0.000ns - oserdes_clk_2 rise@0.000ns) + Data Path Delay: 0.172ns (logic 0.172ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.088ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.661ns + Source Clock Delay (SCD): 1.741ns + Clock Pessimism Removal (CPR): -0.168ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.197 -0.351 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.741 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.172 1.913 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/RDENABLE + net (fo=1, routed) 0.000 1.913 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/po_rd_enable + OUT_FIFO_X1Y6 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.218 -0.567 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.573 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.661 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, routed) 0.000 1.661 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/oserdes_clkdiv + OUT_FIFO_X1Y6 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + clock pessimism 0.168 1.829 + OUT_FIFO_X1Y6 OUT_FIFO (Hold_out_fifo_RDCLK_RDEN) + -0.011 1.818 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo + ------------------------------------------------------------------- + required time -1.818 + arrival time 1.913 + ------------------------------------------------------------------- + slack 0.095 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_3 + To Clock: oserdes_clkdiv_3 + +Setup : 0 Failing Endpoints, Worst Slack 2.105ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.095ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 2.105ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_3 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clkdiv_3 rise@6.000ns - oserdes_clk_3 rise@3.000ns) + Data Path Delay: 0.338ns (logic 0.338ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.148ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.697ns = ( 7.697 - 6.000 ) + Source Clock Delay (SCD): 2.251ns = ( 5.251 - 3.000 ) + Clock Pessimism Removal (CPR): 0.702ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.081ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_3 rise edge) + 3.000 3.000 r + E3 0.000 3.000 r CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 4.482 r input_clock/O + net (fo=1, routed) 1.233 5.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -1.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 0.364 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 0.460 r sys_buffer/O + net (fo=1, routed) 1.666 2.126 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 2.214 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.603 2.817 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 5.251 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.338 5.589 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/RDENABLE + net (fo=1, routed) 0.000 5.589 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/po_rd_enable + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_3 rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, routed) 1.162 8.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 1.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 2.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 2.979 r sys_buffer/O + net (fo=1, routed) 1.544 4.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 4.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.572 5.179 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 7.549 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 7.697 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, routed) 0.000 7.697 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/oserdes_clkdiv + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + clock pessimism 0.702 8.399 + clock uncertainty -0.054 8.345 + OUT_FIFO_X1Y7 OUT_FIFO (Setup_out_fifo_RDCLK_RDEN) + -0.651 7.694 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo + ------------------------------------------------------------------- + required time 7.694 + arrival time -5.589 + ------------------------------------------------------------------- + slack 2.105 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.095ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_3 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_3 rise@0.000ns - oserdes_clk_3 rise@0.000ns) + Data Path Delay: 0.172ns (logic 0.172ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.088ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.652ns + Source Clock Delay (SCD): 1.734ns + Clock Pessimism Removal (CPR): -0.170ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.190 -0.358 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.734 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.172 1.906 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/RDENABLE + net (fo=1, routed) 0.000 1.906 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/po_rd_enable + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.209 -0.576 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.564 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.652 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, routed) 0.000 1.652 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/oserdes_clkdiv + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + clock pessimism 0.170 1.822 + OUT_FIFO_X1Y7 OUT_FIFO (Hold_out_fifo_RDCLK_RDEN) + -0.011 1.811 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo + ------------------------------------------------------------------- + required time -1.811 + arrival time 1.906 + ------------------------------------------------------------------- + slack 0.095 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: core_raw + To Clock: clk_pll_i + +Setup : 0 Failing Endpoints, Worst Slack 38.557ns, Total Violation 0.000ns +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 38.557ns (required time - arrival time) + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: clk_pll_i + Path Type: Setup (Max at Slow Process Corner) + Requirement: 40.000ns (MaxDelay Path 40.000ns) + Data Path Delay: 1.165ns (logic 0.419ns (35.978%) route 0.746ns (64.022%)) + Logic Levels: 0 + Timing Exception: MaxDelay Path 40.000ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + SLICE_X53Y80 0.000 0.000 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + SLICE_X53Y80 FDRE (Prop_fdre_C_Q) 0.419 0.419 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.746 1.165 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[1] + SLICE_X48Y80 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + max delay 40.000 40.000 + SLICE_X48Y80 FDRE (Setup_fdre_C_D) -0.278 39.722 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + ------------------------------------------------------------------- + required time 39.722 + arrival time -1.165 + ------------------------------------------------------------------- + slack 38.557 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: ref_raw + To Clock: clk_pll_i + +Setup : 0 Failing Endpoints, Worst Slack 16.737ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.112ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 16.737ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[10]/C + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[10]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: clk_pll_i + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (MaxDelay Path 20.000ns) + Data Path Delay: 4.958ns (logic 0.518ns (10.448%) route 4.440ns (89.552%)) + Logic Levels: 0 + Clock Path Skew: 1.987ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.668ns + Source Clock Delay (SCD): -0.924ns + Clock Pessimism Removal (CPR): 0.395ns + Clock Uncertainty: 0.245ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.178ns + Timing Exception: MaxDelay Path 20.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.070 -4.355 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.719 -2.636 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r ref_buffer/O + net (fo=67, routed) 1.616 -0.924 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/clk_ref_i + SLICE_X30Y132 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[10]/C + ------------------------------------------------------------------- ------------------- + SLICE_X30Y132 FDRE (Prop_fdre_C_Q) 0.518 -0.406 r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[10]/Q + net (fo=1, routed) 4.440 4.034 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_lcl[10] + SLICE_X37Y131 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[10]/D + ------------------------------------------------------------------- ------------------- + + max delay 20.000 20.000 + E3 0.000 20.000 r CLK100MHZ (IN) + net (fo=0) 0.000 20.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 21.411 r input_clock/O + net (fo=1, routed) 1.162 22.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 15.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 16.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 16.979 r sys_buffer/O + net (fo=1, routed) 1.544 18.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 18.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 19.812 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 19.893 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 20.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 17.442 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 19.081 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 19.172 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.496 20.668 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r5_reg[11]_0 + SLICE_X37Y131 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[10]/C + clock pessimism 0.395 21.063 + clock uncertainty -0.245 20.818 + SLICE_X37Y131 FDRE (Setup_fdre_C_D) -0.047 20.771 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[10] + ------------------------------------------------------------------- + required time 20.771 + arrival time -4.034 + ------------------------------------------------------------------- + slack 16.737 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.112ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[4]/C + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[4]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: clk_pll_i + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_pll_i rise@0.000ns - ref_raw rise@0.000ns) + Data Path Delay: 1.784ns (logic 0.141ns (7.901%) route 1.643ns (92.099%)) + Logic Levels: 0 + Clock Path Skew: 1.352ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.185ns + Source Clock Delay (SCD): -0.611ns + Clock Pessimism Removal (CPR): -0.557ns + Clock Uncertainty: 0.245ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.178ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -2.379 -1.689 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.499 -1.190 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r ref_buffer/O + net (fo=67, routed) 0.553 -0.611 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/clk_ref_i + SLICE_X33Y126 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X33Y126 FDRE (Prop_fdre_C_Q) 0.141 -0.470 r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[4]/Q + net (fo=1, routed) 1.643 1.173 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_lcl[4] + SLICE_X35Y127 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[4]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.437 -0.348 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.043 -0.305 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.494 0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.400 -1.211 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.544 -0.668 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -0.639 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.823 0.185 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r5_reg[11]_0 + SLICE_X35Y127 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[4]/C + clock pessimism 0.557 0.741 + clock uncertainty 0.245 0.986 + SLICE_X35Y127 FDRE (Hold_fdre_C_D) 0.075 1.061 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[4] + ------------------------------------------------------------------- + required time -1.061 + arrival time 1.173 + ------------------------------------------------------------------- + slack 0.112 + + + + + +--------------------------------------------------------------------------------------------------- +Path Group: **async_default** +From Clock: clk_pll_i + To Clock: clk_pll_i + +Setup : 0 Failing Endpoints, Worst Slack 8.929ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.176ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 8.929ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__8/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n_reg/CLR + (recovery check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 12.000ns (clk_pll_i rise@12.000ns - clk_pll_i rise@0.000ns) + Data Path Delay: 2.735ns (logic 0.518ns (18.939%) route 2.217ns (81.061%)) + Logic Levels: 0 + Clock Path Skew: 0.050ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.763ns = ( 12.763 - 12.000 ) + Source Clock Delay (SCD): 1.442ns + Clock Pessimism Removal (CPR): 0.729ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.620 1.442 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + SLICE_X58Y66 FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__8/C + ------------------------------------------------------------------- ------------------- + SLICE_X58Y66 FDPE (Prop_fdpe_C_Q) 0.518 1.960 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__8/Q + net (fo=47, routed) 2.217 4.177 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/calib_ctl_wren_reg_7 + SLICE_X78Y66 FDCE f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 11.812 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 11.893 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 12.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 9.442 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 11.081 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 11.172 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.590 12.763 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg[14]_0 + SLICE_X78Y66 FDCE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n_reg/C + clock pessimism 0.729 13.492 + clock uncertainty -0.067 13.425 + SLICE_X78Y66 FDCE (Recov_fdce_C_CLR) -0.319 13.106 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n_reg + ------------------------------------------------------------------- + required time 13.106 + arrival time -4.177 + ------------------------------------------------------------------- + slack 8.929 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.176ns (arrival time - required time) + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]/CLR + (removal check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (clk_pll_i rise@0.000ns - clk_pll_i rise@0.000ns) + Data Path Delay: 0.291ns (logic 0.128ns (43.969%) route 0.163ns (56.031%)) + Logic Levels: 0 + Clock Path Skew: 0.261ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.180ns + Source Clock Delay (SCD): 0.129ns + Clock Pessimism Removal (CPR): -0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 -0.154 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 -0.134 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 -0.949 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 -0.450 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.424 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.553 0.129 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/dest_clk + SLICE_X51Y77 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X51Y77 FDPE (Prop_fdpe_C_Q) 0.128 0.257 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/Q + net (fo=3, routed) 0.163 0.420 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.rst_rd_reg2 + SLICE_X53Y77 FDCE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.437 -0.348 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.043 -0.305 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.494 0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.400 -1.211 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.544 -0.668 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -0.639 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.819 0.180 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/m_aclk + SLICE_X53Y77 FDCE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]/C + clock pessimism 0.210 0.390 + SLICE_X53Y77 FDCE (Remov_fdce_C_CLR) -0.146 0.244 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0] + ------------------------------------------------------------------- + required time -0.244 + arrival time 0.420 + ------------------------------------------------------------------- + slack 0.176 + + + + + +--------------------------------------------------------------------------------------------------- +Path Group: **async_default** +From Clock: core_raw + To Clock: core_raw + +Setup : 0 Failing Endpoints, Worst Slack 24.453ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.154ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 24.453ns (required time - arrival time) + Source: reset_count_reg[12]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: platform/chip/system/clint_domain/intsource/reg_0/reg_0_reg[0]/CLR + (recovery check against rising-edge clock core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 40.000ns (core_raw rise@40.000ns - core_raw rise@0.000ns) + Data Path Delay: 14.936ns (logic 1.308ns (8.757%) route 13.628ns (91.243%)) + Logic Levels: 5 (LUT2=1 LUT4=2 LUT5=1 LUT6=1) + Clock Path Skew: -0.115ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.519ns = ( 38.481 - 40.000 ) + Source Clock Delay (SCD): -0.924ns + Clock Pessimism Removal (CPR): 0.480ns + Clock Uncertainty: 0.091ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.616 -0.924 clk + SLICE_X68Y77 FDRE r reset_count_reg[12]/C + ------------------------------------------------------------------- ------------------- + SLICE_X68Y77 FDRE (Prop_fdre_C_Q) 0.456 -0.468 r reset_count_reg[12]/Q + net (fo=2, routed) 1.107 0.639 platform/normalizer/reset_count_reg[12] + SLICE_X69Y76 LUT6 (Prop_lut6_I1_O) 0.124 0.763 r platform/normalizer/axi_fullwidth_LUT6_1/O + net (fo=1, routed) 0.292 1.056 platform/normalizer/axi_fullwidth_net_1 + SLICE_X69Y77 LUT5 (Prop_lut5_I4_O) 0.124 1.180 r platform/normalizer/axi_fullwidth_LUT5_1/O + net (fo=1, routed) 0.433 1.613 platform/normalizer/axi_fullwidth_net_3 + SLICE_X69Y77 LUT4 (Prop_lut4_I3_O) 0.124 1.737 f platform/normalizer/axi_fullwidth_LUT4_9/O + net (fo=21, routed) 0.825 2.561 platform/normalizer/sel + SLICE_X69Y78 LUT4 (Prop_lut4_I3_O) 0.153 2.714 f platform/normalizer/axi_fullwidth_LUT4_10/O + net (fo=899, routed) 2.824 5.539 platform/loader/cpu_run_reg_inv_20 + SLICE_X85Y102 LUT2 (Prop_lut2_I0_O) 0.327 5.866 f platform/loader/in_pipe_v_i_1__0/O + net (fo=3764, routed) 8.147 14.013 platform/chip/system/clint_domain/intsource/reg_0/cpu_reset + SLICE_X32Y139 FDCE f platform/chip/system/clint_domain/intsource/reg_0/reg_0_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 40.000 40.000 r + E3 0.000 40.000 r CLK100MHZ (IN) + net (fo=0) 0.000 40.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r input_clock/O + net (fo=1, routed) 1.162 42.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 35.249 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 36.888 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 36.979 r core_buffer/O + net (fo=35517, routed) 1.502 38.481 platform/chip/system/clint_domain/intsource/reg_0/clk + SLICE_X32Y139 FDCE r platform/chip/system/clint_domain/intsource/reg_0/reg_0_reg[0]/C + clock pessimism 0.480 38.962 + clock uncertainty -0.091 38.871 + SLICE_X32Y139 FDCE (Recov_fdce_C_CLR) -0.405 38.466 platform/chip/system/clint_domain/intsource/reg_0/reg_0_reg[0] + ------------------------------------------------------------------- + required time 38.466 + arrival time -14.013 + ------------------------------------------------------------------- + slack 24.453 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.154ns (arrival time - required time) + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + (rising edge-triggered cell FDPE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1]/CLR + (removal check against rising-edge clock core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (core_raw rise@0.000ns - core_raw rise@0.000ns) + Data Path Delay: 0.349ns (logic 0.141ns (40.345%) route 0.208ns (59.655%)) + Logic Levels: 0 + Clock Path Skew: 0.262ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.849ns + Source Clock Delay (SCD): -0.607ns + Clock Pessimism Removal (CPR): -0.504ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.379 -1.689 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.499 -1.190 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.164 r core_buffer/O + net (fo=35517, routed) 0.557 -0.607 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/s_aclk + SLICE_X51Y80 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X51Y80 FDPE (Prop_fdpe_C_Q) 0.141 -0.466 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q + net (fo=15, routed) 0.208 -0.258 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] + SLICE_X54Y80 FDCE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.163 -2.245 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.544 -1.702 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.673 r core_buffer/O + net (fo=35517, routed) 0.824 -0.849 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/s_aclk + SLICE_X54Y80 FDCE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1]/C + clock pessimism 0.504 -0.345 + SLICE_X54Y80 FDCE (Remov_fdce_C_CLR) -0.067 -0.412 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1] + ------------------------------------------------------------------- + required time 0.412 + arrival time -0.258 + ------------------------------------------------------------------- + slack 0.154 + + + + + +--------------------------------------------------------------------------------------------------- +Path Group: **default** +From Clock: clk_pll_i + To Clock: + +Setup : 0 Failing Endpoints, Worst Slack 1.969ns, Total Violation 0.000ns +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.969ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/RESET + Path Group: **default** + Path Type: Max at Slow Process Corner + Requirement: 5.000ns (MaxDelay Path 5.000ns) + Data Path Delay: 3.031ns (logic 0.456ns (15.043%) route 2.575ns (84.957%)) + Logic Levels: 0 + Output Delay: 0.000ns + Timing Exception: MaxDelay Path 5.000ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + SLICE_X69Y117 0.000 0.000 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + SLICE_X69Y117 FDPE (Prop_fdpe_C_Q) 0.456 0.456 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/Q + net (fo=50, routed) 2.575 3.031 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i_0 + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/RESET + ------------------------------------------------------------------- ------------------- + + max delay 5.000 5.000 + PHY_CONTROL_X1Y1 PHY_CONTROL 0.000 5.000 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i + output delay -0.000 5.000 + ------------------------------------------------------------------- + required time 5.000 + arrival time -3.031 + ------------------------------------------------------------------- + slack 1.969 + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: clk_pll_i + To Clock: + +Max Delay 1 Endpoint +Min Delay 2 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n_reg/C + (rising edge-triggered cell FDCE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr3_reset_n + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 5.748ns (logic 2.163ns (37.622%) route 3.586ns (62.378%)) + Logic Levels: 2 (LUT2=1 OBUF=1) + Clock Uncertainty: 0.193ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.132ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.711 1.533 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg[14]_0 + SLICE_X78Y66 FDCE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X78Y66 FDCE (Prop_fdce_C_Q) 0.518 2.051 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n_reg/Q + net (fo=1, routed) 0.961 3.012 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n + SLICE_X87Y66 LUT2 (Prop_lut2_I1_O) 0.124 3.136 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/gen_reset_obuf.u_reset_obuf_i_1/O + net (fo=1, routed) 2.625 5.761 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/mux_reset_n + K6 OBUF (Prop_obuf_I_O) 1.521 7.282 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_reset_obuf.u_reset_obuf/O + net (fo=0) 0.000 7.282 ddr3_reset_n + K6 r ddr3_reset_n (OUT) + ------------------------------------------------------------------- ------------------- + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/RESET + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 1.384ns (logic 0.141ns (10.185%) route 1.243ns (89.815%)) + Logic Levels: 0 + Clock Uncertainty: 0.193ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.132ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 -0.154 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 -0.134 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 -0.949 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 -0.450 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.424 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.558 0.134 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + SLICE_X69Y117 FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X69Y117 FDPE (Prop_fdpe_C_Q) 0.141 0.275 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/Q + net (fo=50, routed) 1.243 1.518 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i_0 + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/RESET + ------------------------------------------------------------------- ------------------- + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: core_raw + To Clock: + +Max Delay 5 Endpoints +Min Delay 5 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: reset_count_reg[12]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: led[2] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 11.989ns (logic 4.963ns (41.400%) route 7.025ns (58.600%)) + Logic Levels: 5 (LUT4=1 LUT5=2 LUT6=1 OBUF=1) + Clock Uncertainty: 0.186ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.099ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.616 -0.924 clk + SLICE_X68Y77 FDRE r reset_count_reg[12]/C + ------------------------------------------------------------------- ------------------- + SLICE_X68Y77 FDRE (Prop_fdre_C_Q) 0.456 -0.468 r reset_count_reg[12]/Q + net (fo=2, routed) 1.107 0.639 platform/normalizer/reset_count_reg[12] + SLICE_X69Y76 LUT6 (Prop_lut6_I1_O) 0.124 0.763 r platform/normalizer/axi_fullwidth_LUT6_1/O + net (fo=1, routed) 0.292 1.056 platform/normalizer/axi_fullwidth_net_1 + SLICE_X69Y77 LUT5 (Prop_lut5_I4_O) 0.124 1.180 r platform/normalizer/axi_fullwidth_LUT5_1/O + net (fo=1, routed) 0.433 1.613 platform/normalizer/axi_fullwidth_net_3 + SLICE_X69Y77 LUT4 (Prop_lut4_I3_O) 0.124 1.737 f platform/normalizer/axi_fullwidth_LUT4_9/O + net (fo=21, routed) 0.825 2.561 platform/loader/sel + SLICE_X69Y78 LUT5 (Prop_lut5_I3_O) 0.124 2.685 r platform/loader/led_OBUF[2]_inst_i_1/O + net (fo=1, routed) 4.368 7.054 led_OBUF[2] + T9 OBUF (Prop_obuf_I_O) 4.011 11.065 r led_OBUF[2]_inst/O + net (fo=0) 0.000 11.065 led[2] + T9 r led[2] (OUT) + ------------------------------------------------------------------- ------------------- + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: platform/peripherals/exit_code_reg[19]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: led[1] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.331ns (logic 2.205ns (66.189%) route 1.126ns (33.811%)) + Logic Levels: 3 (LUT5=1 LUT6=1 OBUF=1) + Clock Uncertainty: 0.186ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.099ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.379 -1.689 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.499 -1.190 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.164 r core_buffer/O + net (fo=35517, routed) 0.559 -0.605 platform/peripherals/clk + SLICE_X54Y101 FDRE r platform/peripherals/exit_code_reg[19]/C + ------------------------------------------------------------------- ------------------- + SLICE_X54Y101 FDRE (Prop_fdre_C_Q) 0.164 -0.441 r platform/peripherals/exit_code_reg[19]/Q + net (fo=2, routed) 0.094 -0.347 platform/peripherals/exit_code[19] + SLICE_X55Y101 LUT6 (Prop_lut6_I3_O) 0.045 -0.302 r platform/peripherals/led_OBUF[1]_inst_i_4/O + net (fo=1, routed) 0.082 -0.220 platform/peripherals/led_OBUF[1]_inst_i_4_n_0 + SLICE_X55Y101 LUT5 (Prop_lut5_I2_O) 0.045 -0.175 r platform/peripherals/led_OBUF[1]_inst_i_1/O + net (fo=1, routed) 0.950 0.775 led_OBUF[1] + J5 OBUF (Prop_obuf_I_O) 1.951 2.726 r led_OBUF[1]_inst/O + net (fo=0) 0.000 2.726 led[1] + J5 r led[1] (OUT) + ------------------------------------------------------------------- ------------------- + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: clk_pll_i + To Clock: clk_pll_i + +Max Delay 13 Endpoints +Min Delay 13 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ui_reset_pipe_reg[2]/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + (recovery check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 4.076ns (logic 0.711ns (17.445%) route 3.365ns (82.555%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: -0.670ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.766ns + Source Clock Delay (SCD): 1.436ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.614 1.436 ui_clk + SLICE_X65Y77 FDPE r ui_reset_pipe_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y77 FDPE (Prop_fdpe_C_Q) 0.419 1.855 f ui_reset_pipe_reg[2]/Q + net (fo=2, routed) 0.267 2.122 memory_cdc/inst/m_axi_aresetn + SLICE_X65Y77 LUT2 (Prop_lut2_I1_O) 0.292 2.414 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi_i_1/O + net (fo=20, routed) 3.098 5.512 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/src_arst + SLICE_X89Y113 FDPE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.594 0.766 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/dest_clk + SLICE_X89Y113 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ui_reset_pipe_reg[2]/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + (removal check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Removal (Min at Fast Process Corner) + Data Path Delay: 0.744ns (logic 0.232ns (31.172%) route 0.512ns (68.828%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: 0.049ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.181ns + Source Clock Delay (SCD): 0.132ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 -0.154 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 -0.134 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 -0.949 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 -0.450 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.424 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.556 0.132 ui_clk + SLICE_X65Y77 FDPE r ui_reset_pipe_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y77 FDPE (Prop_fdpe_C_Q) 0.128 0.260 f ui_reset_pipe_reg[2]/Q + net (fo=2, routed) 0.086 0.345 memory_cdc/inst/m_axi_aresetn + SLICE_X65Y77 LUT2 (Prop_lut2_I1_O) 0.104 0.449 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi_i_1/O + net (fo=20, routed) 0.427 0.876 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/src_arst + SLICE_X51Y77 FDPE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.437 -0.348 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.043 -0.305 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.494 0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.400 -1.211 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.544 -0.668 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -0.639 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.820 0.181 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/dest_clk + SLICE_X51Y77 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: core_raw + To Clock: clk_pll_i + +Max Delay 235 Endpoints +Min Delay 255 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: reset_count_reg[12]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + (recovery check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 7.475ns (logic 1.308ns (17.497%) route 6.167ns (82.503%)) + Logic Levels: 5 (LUT2=1 LUT4=2 LUT5=1 LUT6=1) + Clock Path Skew: 1.690ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.766ns + Source Clock Delay (SCD): -0.924ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.247ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.117ns + Phase Error (PE): 0.178ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.616 -0.924 clk + SLICE_X68Y77 FDRE r reset_count_reg[12]/C + ------------------------------------------------------------------- ------------------- + SLICE_X68Y77 FDRE (Prop_fdre_C_Q) 0.456 -0.468 r reset_count_reg[12]/Q + net (fo=2, routed) 1.107 0.639 platform/normalizer/reset_count_reg[12] + SLICE_X69Y76 LUT6 (Prop_lut6_I1_O) 0.124 0.763 r platform/normalizer/axi_fullwidth_LUT6_1/O + net (fo=1, routed) 0.292 1.056 platform/normalizer/axi_fullwidth_net_1 + SLICE_X69Y77 LUT5 (Prop_lut5_I4_O) 0.124 1.180 r platform/normalizer/axi_fullwidth_LUT5_1/O + net (fo=1, routed) 0.433 1.613 platform/normalizer/axi_fullwidth_net_3 + SLICE_X69Y77 LUT4 (Prop_lut4_I3_O) 0.124 1.737 f platform/normalizer/axi_fullwidth_LUT4_9/O + net (fo=21, routed) 0.440 2.177 sel + SLICE_X69Y78 LUT4 (Prop_lut4_I3_O) 0.119 2.296 r memory_cdc_i_1/O + net (fo=1, routed) 0.797 3.093 memory_cdc/inst/s_axi_aresetn + SLICE_X65Y77 LUT2 (Prop_lut2_I0_O) 0.361 3.454 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi_i_1/O + net (fo=20, routed) 3.098 6.552 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/src_arst + SLICE_X89Y113 FDPE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.594 0.766 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/dest_clk + SLICE_X89Y113 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.586ns (logic 0.337ns (57.552%) route 0.249ns (42.448%)) + Logic Levels: 0 + Clock Path Skew: 2.961ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.453ns + Source Clock Delay (SCD): -1.508ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.247ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.117ns + Phase Error (PE): 0.178ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=35517, routed) 1.512 -1.508 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X68Y94 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X68Y94 FDRE (Prop_fdre_C_Q) 0.337 -1.171 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.249 -0.923 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[1] + SLICE_X69Y94 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.631 1.453 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X69Y94 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: mem_refclk + To Clock: clk_pll_i + +Max Delay 2 Endpoints +Min Delay 2 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/MEMREFCLK + (rising edge-triggered cell PHASER_IN_PHY clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[3]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 1.754ns (logic 0.402ns (22.913%) route 1.352ns (77.087%)) + Logic Levels: 0 + Clock Path Skew: 0.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.758ns + Source Clock Delay (SCD): -0.189ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.245ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.178ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.597 -0.189 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/MEMREFCLK + ------------------------------------------------------------------- ------------------- + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_MEMREFCLK_DQSFOUND) + 0.402 0.213 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/DQSFOUND + net (fo=1, routed) 1.352 1.566 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes[1] + SLICE_X81Y73 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.585 0.758 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/init_dqsfound_done_r5_reg_0 + SLICE_X81Y73 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[3]/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/MEMREFCLK + (rising edge-triggered cell PHASER_IN_PHY clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[2]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 0.546ns (logic 0.204ns (37.365%) route 0.342ns (62.635%)) + Logic Levels: 0 + Clock Path Skew: 0.574ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.223ns + Source Clock Delay (SCD): -0.351ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.245ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.178ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.197 -0.351 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/MEMREFCLK + ------------------------------------------------------------------- ------------------- + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_MEMREFCLK_DQSFOUND) + 0.204 -0.147 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/DQSFOUND + net (fo=1, routed) 0.342 0.195 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes[0] + SLICE_X89Y73 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.437 -0.348 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.043 -0.305 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.494 0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.400 -1.211 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.544 -0.668 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -0.639 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.862 0.223 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/init_dqsfound_done_r5_reg_0 + SLICE_X89Y73 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[2]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: ref_raw + To Clock: clk_pll_i + +Max Delay 32 Endpoints +Min Delay 32 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: mig_resetn_pipe_reg[2]/C + (rising edge-triggered cell FDCE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__11/PRE + (recovery check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 6.619ns (logic 0.779ns (11.769%) route 5.840ns (88.231%)) + Logic Levels: 1 (LUT4=1) + Clock Path Skew: 1.586ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.659ns + Source Clock Delay (SCD): -0.927ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.245ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.178ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.070 -4.355 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.719 -2.636 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r ref_buffer/O + net (fo=67, routed) 1.613 -0.927 ref_clk + SLICE_X70Y75 FDCE r mig_resetn_pipe_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X70Y75 FDCE (Prop_fdce_C_Q) 0.478 -0.449 r mig_resetn_pipe_reg[2]/Q + net (fo=2, routed) 1.326 0.877 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/sys_rst_i + SLICE_X89Y75 LUT4 (Prop_lut4_I2_O) 0.301 1.178 f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rstdiv2_sync_r[11]_i_1/O + net (fo=32, routed) 4.514 5.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_tmp + SLICE_X51Y119 FDPE f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__11/PRE + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.487 0.659 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + SLICE_X51Y119 FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__11/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: mig_resetn_pipe_reg[2]/C + (rising edge-triggered cell FDCE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[9]/PRE + (removal check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Removal (Min at Fast Process Corner) + Data Path Delay: 1.567ns (logic 0.247ns (15.765%) route 1.320ns (84.235%)) + Logic Levels: 1 (LUT4=1) + Clock Path Skew: 0.847ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.238ns + Source Clock Delay (SCD): -0.609ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.245ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.178ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -2.379 -1.689 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.499 -1.190 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r ref_buffer/O + net (fo=67, routed) 0.555 -0.609 ref_clk + SLICE_X70Y75 FDCE r mig_resetn_pipe_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X70Y75 FDCE (Prop_fdce_C_Q) 0.148 -0.461 r mig_resetn_pipe_reg[2]/Q + net (fo=2, routed) 0.601 0.140 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/sys_rst_i + SLICE_X89Y75 LUT4 (Prop_lut4_I2_O) 0.099 0.239 f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rstdiv2_sync_r[11]_i_1/O + net (fo=32, routed) 0.719 0.957 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_tmp + SLICE_X83Y97 FDPE f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[9]/PRE + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.437 -0.348 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.043 -0.305 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.494 0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.400 -1.211 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.544 -0.668 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -0.639 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.877 0.238 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + SLICE_X83Y97 FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[9]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: + To Clock: core_raw + +Max Delay 2 Endpoints +Min Delay 2 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: btn0 + (input port) + Destination: btn_meta_reg/D + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 7.988ns (logic 1.487ns (18.620%) route 6.501ns (81.380%)) + Logic Levels: 1 (IBUF=1) + Clock Path Skew: -1.522ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.522ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.186ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.099ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + D9 0.000 0.000 r btn0 (IN) + net (fo=0) 0.000 0.000 btn0 + D9 IBUF (Prop_ibuf_I_O) 1.487 1.487 r btn0_IBUF_inst/O + net (fo=2, routed) 6.501 7.988 btn0_IBUF + SLICE_X67Y77 FDRE r btn_meta_reg/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=35517, routed) 1.498 -1.522 clk + SLICE_X67Y77 FDRE r btn_meta_reg/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: uart_txd_in + (input port) + Destination: platform/receiver/rx_meta_reg/D + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 2.012ns (logic 0.294ns (14.604%) route 1.718ns (85.396%)) + Logic Levels: 1 (IBUF=1) + Clock Path Skew: -0.838ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.838ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + A9 0.000 0.000 r uart_txd_in (IN) + net (fo=0) 0.000 0.000 uart_txd_in + A9 IBUF (Prop_ibuf_I_O) 0.294 0.294 r uart_txd_in_IBUF_inst/O + net (fo=1, routed) 1.718 2.012 platform/receiver/rx + SLICE_X39Y102 FDRE r platform/receiver/rx_meta_reg/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.163 -2.245 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.544 -1.702 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.673 r core_buffer/O + net (fo=35517, routed) 0.835 -0.838 platform/receiver/clk + SLICE_X39Y102 FDRE r platform/receiver/rx_meta_reg/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: clk_pll_i + To Clock: core_raw + +Max Delay 157 Endpoints +Min Delay 177 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ui_reset_pipe_reg[2]/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + (recovery check against rising-edge clock core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 3.789ns (logic 0.711ns (18.764%) route 3.078ns (81.236%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: -2.866ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.430ns + Source Clock Delay (SCD): 1.436ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.255ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.164ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.614 1.436 ui_clk + SLICE_X65Y77 FDPE r ui_reset_pipe_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y77 FDPE (Prop_fdpe_C_Q) 0.419 1.855 f ui_reset_pipe_reg[2]/Q + net (fo=2, routed) 0.267 2.122 memory_cdc/inst/m_axi_aresetn + SLICE_X65Y77 LUT2 (Prop_lut2_I1_O) 0.292 2.414 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi_i_1/O + net (fo=20, routed) 2.812 5.225 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst + SLICE_X87Y113 FDPE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=35517, routed) 1.591 -1.430 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk + SLICE_X87Y113 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 0.238ns (logic 0.128ns (53.830%) route 0.110ns (46.170%)) + Logic Levels: 0 + Clock Path Skew: -0.978ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.847ns + Source Clock Delay (SCD): 0.131ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.255ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.164ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 -0.154 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 -0.134 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 -0.949 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 -0.450 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.424 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.555 0.131 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X57Y80 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X57Y80 FDRE (Prop_fdre_C_Q) 0.128 0.259 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.110 0.369 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[1] + SLICE_X57Y81 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.163 -2.245 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.544 -1.702 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.673 r core_buffer/O + net (fo=35517, routed) 0.826 -0.847 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X57Y81 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: core_raw + To Clock: core_raw + +Max Delay 10 Endpoints +Min Delay 10 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: reset_count_reg[12]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + (recovery check against rising-edge clock core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 7.189ns (logic 1.308ns (18.195%) route 5.881ns (81.805%)) + Logic Levels: 5 (LUT2=1 LUT4=2 LUT5=1 LUT6=1) + Clock Path Skew: -0.506ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.430ns + Source Clock Delay (SCD): -0.924ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.091ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.616 -0.924 clk + SLICE_X68Y77 FDRE r reset_count_reg[12]/C + ------------------------------------------------------------------- ------------------- + SLICE_X68Y77 FDRE (Prop_fdre_C_Q) 0.456 -0.468 r reset_count_reg[12]/Q + net (fo=2, routed) 1.107 0.639 platform/normalizer/reset_count_reg[12] + SLICE_X69Y76 LUT6 (Prop_lut6_I1_O) 0.124 0.763 r platform/normalizer/axi_fullwidth_LUT6_1/O + net (fo=1, routed) 0.292 1.056 platform/normalizer/axi_fullwidth_net_1 + SLICE_X69Y77 LUT5 (Prop_lut5_I4_O) 0.124 1.180 r platform/normalizer/axi_fullwidth_LUT5_1/O + net (fo=1, routed) 0.433 1.613 platform/normalizer/axi_fullwidth_net_3 + SLICE_X69Y77 LUT4 (Prop_lut4_I3_O) 0.124 1.737 f platform/normalizer/axi_fullwidth_LUT4_9/O + net (fo=21, routed) 0.440 2.177 sel + SLICE_X69Y78 LUT4 (Prop_lut4_I3_O) 0.119 2.296 r memory_cdc_i_1/O + net (fo=1, routed) 0.797 3.093 memory_cdc/inst/s_axi_aresetn + SLICE_X65Y77 LUT2 (Prop_lut2_I0_O) 0.361 3.454 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi_i_1/O + net (fo=20, routed) 2.812 6.265 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst + SLICE_X87Y113 FDPE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=35517, routed) 1.591 -1.430 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk + SLICE_X87Y113 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: lock_sync_reg[2]/C + (rising edge-triggered cell FDPE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + (removal check against rising-edge clock core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: (none) + Path Type: Removal (Min at Fast Process Corner) + Data Path Delay: 1.285ns (logic 0.293ns (22.796%) route 0.992ns (77.204%)) + Logic Levels: 2 (LUT2=1 LUT4=1) + Clock Path Skew: -0.245ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.851ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.091ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.379 -1.689 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.499 -1.190 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.164 r core_buffer/O + net (fo=35517, routed) 0.558 -0.606 clk + SLICE_X63Y78 FDPE r lock_sync_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X63Y78 FDPE (Prop_fdpe_C_Q) 0.141 -0.465 f lock_sync_reg[2]/Q + net (fo=4, routed) 0.287 -0.179 lock_sync[2] + SLICE_X69Y78 LUT4 (Prop_lut4_I1_O) 0.043 -0.136 r memory_cdc_i_1/O + net (fo=1, routed) 0.279 0.143 memory_cdc/inst/s_axi_aresetn + SLICE_X65Y77 LUT2 (Prop_lut2_I0_O) 0.109 0.252 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi_i_1/O + net (fo=20, routed) 0.427 0.679 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst + SLICE_X50Y77 FDPE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.163 -2.245 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.544 -1.702 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.673 r core_buffer/O + net (fo=35517, routed) 0.822 -0.851 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk + SLICE_X50Y77 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: + To Clock: ref_raw + +Max Delay 1 Endpoint +Min Delay 1 Endpoint +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: btn0 + (input port) + Destination: btn_ref_meta_reg/D + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 8.119ns (logic 1.487ns (18.320%) route 6.632ns (81.680%)) + Logic Levels: 1 (IBUF=1) + Clock Path Skew: -1.525ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.525ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.099ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + D9 0.000 0.000 r btn0 (IN) + net (fo=0) 0.000 0.000 btn0 + D9 IBUF (Prop_ibuf_I_O) 1.487 1.487 r btn0_IBUF_inst/O + net (fo=2, routed) 6.632 8.119 btn0_IBUF + SLICE_X67Y74 FDRE r btn_ref_meta_reg/D + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.324 -4.751 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.639 -3.112 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.021 r ref_buffer/O + net (fo=67, routed) 1.495 -1.525 ref_clk + SLICE_X67Y74 FDRE r btn_ref_meta_reg/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: btn0 + (input port) + Destination: btn_ref_meta_reg/D + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.179ns (logic 0.255ns (8.026%) route 2.924ns (91.974%)) + Logic Levels: 1 (IBUF=1) + Clock Path Skew: -0.849ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.849ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + D9 0.000 0.000 r btn0 (IN) + net (fo=0) 0.000 0.000 btn0 + D9 IBUF (Prop_ibuf_I_O) 0.255 0.255 r btn0_IBUF_inst/O + net (fo=2, routed) 2.924 3.179 btn0_IBUF + SLICE_X67Y74 FDRE r btn_ref_meta_reg/D + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -3.163 -2.245 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.544 -1.702 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r ref_buffer/O + net (fo=67, routed) 0.824 -0.849 ref_clk + SLICE_X67Y74 FDRE r btn_ref_meta_reg/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: clk_pll_i + To Clock: ref_raw + +Max Delay 0 Endpoints +Min Delay 1 Endpoint +-------------------------------------------------------------------------------------- + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg/D + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.028ns (logic 0.141ns (13.719%) route 0.887ns (86.282%)) + Logic Levels: 0 + Clock Path Skew: -0.987ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.853ns + Source Clock Delay (SCD): 0.134ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.231ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.164ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 -0.154 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 -0.134 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 -0.949 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 -0.450 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.424 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.558 0.134 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + SLICE_X69Y117 FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X69Y117 FDPE (Prop_fdpe_C_Q) 0.141 0.275 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/Q + net (fo=50, routed) 0.887 1.162 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg_0 + SLICE_X32Y125 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg/D + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -3.163 -2.245 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.544 -1.702 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r ref_buffer/O + net (fo=67, routed) 0.820 -0.853 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/clk_ref_i + SLICE_X32Y125 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: ref_raw + To Clock: ref_raw + +Max Delay 15 Endpoints +Min Delay 15 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: mig_resetn_pipe_reg[2]/C + (rising edge-triggered cell FDCE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rst_ref_sync_r_reg[0][11]/PRE + (recovery check against rising-edge clock ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 4.125ns (logic 0.808ns (19.586%) route 3.317ns (80.414%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.481ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.408ns + Source Clock Delay (SCD): -0.927ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.070 -4.355 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.719 -2.636 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r ref_buffer/O + net (fo=67, routed) 1.613 -0.927 ref_clk + SLICE_X70Y75 FDCE r mig_resetn_pipe_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X70Y75 FDCE (Prop_fdce_C_Q) 0.478 -0.449 r mig_resetn_pipe_reg[2]/Q + net (fo=2, routed) 1.326 0.877 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/sys_rst_i + SLICE_X89Y75 LUT1 (Prop_lut1_I0_O) 0.330 1.207 f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/plle2_i_i_1/O + net (fo=16, routed) 1.992 3.199 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/AS[0] + SLICE_X89Y53 FDPE f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rst_ref_sync_r_reg[0][11]/PRE + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.324 -4.751 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.639 -3.112 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.021 r ref_buffer/O + net (fo=67, routed) 1.612 -1.408 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/clk_ref_i + SLICE_X89Y53 FDPE r ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rst_ref_sync_r_reg[0][11]/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: mig_resetn_pipe_reg[2]/C + (rising edge-triggered cell FDCE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rst_ref_sync_r_reg[0][0]/PRE + (removal check against rising-edge clock ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: (none) + Path Type: Removal (Min at Fast Process Corner) + Data Path Delay: 1.482ns (logic 0.244ns (16.461%) route 1.238ns (83.539%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.184ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.793ns + Source Clock Delay (SCD): -0.609ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -2.379 -1.689 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.499 -1.190 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r ref_buffer/O + net (fo=67, routed) 0.555 -0.609 ref_clk + SLICE_X70Y75 FDCE r mig_resetn_pipe_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X70Y75 FDCE (Prop_fdce_C_Q) 0.148 -0.461 r mig_resetn_pipe_reg[2]/Q + net (fo=2, routed) 0.601 0.140 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/sys_rst_i + SLICE_X89Y75 LUT1 (Prop_lut1_I0_O) 0.096 0.236 f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/plle2_i_i_1/O + net (fo=16, routed) 0.637 0.873 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/AS[0] + SLICE_X89Y50 FDPE f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rst_ref_sync_r_reg[0][0]/PRE + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -3.163 -2.245 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.544 -1.702 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r ref_buffer/O + net (fo=67, routed) 0.880 -0.793 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/clk_ref_i + SLICE_X89Y50 FDPE r ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rst_ref_sync_r_reg[0][0]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: clk_pll_i + To Clock: + +Max Delay 1 Endpoint +Min Delay 1 Endpoint +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + (clock source 'clk_pll_i' {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBIN + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 3.457ns (logic 0.096ns (2.777%) route 3.361ns (97.223%)) + Logic Levels: 1 (BUFG=1) + Clock Uncertainty: 0.193ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.132ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i fall edge) + 6.000 6.000 f + E3 0.000 6.000 f CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 7.482 f input_clock/O + net (fo=1, routed) 1.233 8.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 1.645 f clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 3.364 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 3.460 f sys_buffer/O + net (fo=1, routed) 1.666 5.126 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 5.214 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 6.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 6.622 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 7.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + ------------------------------------------------------------------- ------------------- + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 4.007 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 5.726 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 5.822 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.641 7.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + MMCME2_ADV_X1Y1 MMCME2_ADV f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBIN + ------------------------------------------------------------------- ------------------- + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + (clock source 'clk_pll_i' {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBIN + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 1.084ns (logic 0.026ns (2.400%) route 1.058ns (97.600%)) + Logic Levels: 1 (BUFG=1) + Clock Uncertainty: 0.193ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.132ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 -0.154 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 -0.134 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + ------------------------------------------------------------------- ------------------- + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 -0.949 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 -0.450 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.424 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.559 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + MMCME2_ADV_X1Y1 MMCME2_ADV r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBIN + ------------------------------------------------------------------- ------------------- + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: fb + To Clock: + +Max Delay 1 Endpoint +Min Delay 1 Endpoint +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: clock_mmcm/CLKFBOUT + (clock source 'fb' {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: clock_mmcm/CLKFBIN + Path Group: (none) + Path Type: Max at Fast Process Corner + Data Path Delay: 1.396ns (logic 0.029ns (2.077%) route 1.367ns (97.923%)) + Logic Levels: 1 (BUFG=1) + Clock Uncertainty: 0.147ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.099ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock fb fall edge) 5.000 5.000 f + E3 0.000 5.000 f CLK100MHZ (IN) + net (fo=0) 0.000 5.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 5.438 f input_clock/O + net (fo=1, routed) 0.480 5.918 clk_in + ------------------------------------------------------------------- ------------------- + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.163 2.755 f clock_mmcm/CLKFBOUT + net (fo=1, routed) 0.544 3.298 fb + BUFGCTRL_X0Y19 BUFG (Prop_bufg_I_O) 0.029 3.327 f fb_buffer/O + net (fo=1, routed) 0.824 4.151 fb_buf + MMCME2_ADV_X1Y2 MMCME2_ADV f clock_mmcm/CLKFBIN + ------------------------------------------------------------------- ------------------- + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: clock_mmcm/CLKFBOUT + (clock source 'fb' {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: clock_mmcm/CLKFBIN + Path Group: (none) + Path Type: Min at Slow Process Corner + Data Path Delay: 3.236ns (logic 0.091ns (2.812%) route 3.145ns (97.188%)) + Logic Levels: 1 (BUFG=1) + Clock Uncertainty: 0.147ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.099ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock fb rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + ------------------------------------------------------------------- ------------------- + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -7.324 -4.751 r clock_mmcm/CLKFBOUT + net (fo=1, routed) 1.639 -3.112 fb + BUFGCTRL_X0Y19 BUFG (Prop_bufg_I_O) 0.091 -3.021 r fb_buffer/O + net (fo=1, routed) 1.506 -1.515 fb_buf + MMCME2_ADV_X1Y2 MMCME2_ADV r clock_mmcm/CLKFBIN + ------------------------------------------------------------------- ------------------- + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: freq_refclk + To Clock: + +Max Delay 5 Endpoints +Min Delay 5 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + (clock source 'freq_refclk' {rise@0.000ns fall@0.750ns period=1.500ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i/CLKIN + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 0.647ns (logic 0.000ns (0.000%) route 0.647ns (100.000%)) + Logic Levels: 0 + Clock Uncertainty: 0.123ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.071ns + Phase Error (PE): 0.080ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock freq_refclk fall edge) + 0.750 0.750 f + E3 0.000 0.750 f CLK100MHZ (IN) + net (fo=0) 0.000 0.750 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 2.232 f input_clock/O + net (fo=1, routed) 1.233 3.465 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -3.605 f clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -1.886 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -1.790 f sys_buffer/O + net (fo=1, routed) 1.666 -0.124 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.088 -0.036 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.647 0.611 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/freq_refclk + PHASER_REF_X1Y1 PHASER_REF f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i/CLKIN + ------------------------------------------------------------------- ------------------- + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + (clock source 'freq_refclk' {rise@0.000ns fall@0.750ns period=1.500ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/FREQREFCLK + Path Group: (none) + Path Type: Min at Slow Process Corner + Data Path Delay: 0.572ns (logic 0.000ns (0.000%) route 0.572ns (100.000%)) + Logic Levels: 0 + Clock Uncertainty: 0.123ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.071ns + Phase Error (PE): 0.080ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock freq_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.572 -0.821 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/FREQREFCLK + ------------------------------------------------------------------- ------------------- + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: pll_clkfbout + To Clock: + +Max Delay 1 Endpoint +Min Delay 1 Endpoint +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT + (clock source 'pll_clkfbout' {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBIN + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 0.014ns (logic 0.000ns (0.000%) route 0.014ns (100.001%)) + Logic Levels: 0 + Clock Uncertainty: 0.120ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.062ns + Phase Error (PE): 0.080ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock pll_clkfbout fall edge) + 3.000 3.000 f + E3 0.000 3.000 f CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 4.482 f input_clock/O + net (fo=1, routed) 1.233 5.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -1.355 f clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 0.364 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 0.460 f sys_buffer/O + net (fo=1, routed) 1.666 2.126 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) + 0.088 2.214 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT + net (fo=1, routed) 0.014 2.228 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clkfbout + PLLE2_ADV_X1Y1 PLLE2_ADV f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBIN + ------------------------------------------------------------------- ------------------- + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT + (clock source 'pll_clkfbout' {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBIN + Path Group: (none) + Path Type: Min at Slow Process Corner + Data Path Delay: 0.013ns (logic 0.000ns (0.000%) route 0.013ns (100.000%)) + Logic Levels: 0 + Clock Uncertainty: 0.120ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.062ns + Phase Error (PE): 0.080ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock pll_clkfbout rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT + net (fo=1, routed) 0.013 -1.380 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clkfbout + PLLE2_ADV_X1Y1 PLLE2_ADV r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBIN + ------------------------------------------------------------------- ------------------- + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: ref_raw + To Clock: + +Max Delay 1 Endpoint +Min Delay 1 Endpoint +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: clock_mmcm/CLKOUT2 + (clock source 'ref_raw' {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/u_idelayctrl_200/REFCLK + Path Group: (none) + Path Type: Max at Fast Process Corner + Data Path Delay: 1.340ns (logic 0.029ns (2.164%) route 1.311ns (97.836%)) + Logic Levels: 1 (BUFG=1) + Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.099ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw fall edge) 2.500 2.500 f + E3 0.000 2.500 f CLK100MHZ (IN) + net (fo=0) 0.000 2.500 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 2.938 f input_clock/O + net (fo=1, routed) 0.480 3.418 clk_in + ------------------------------------------------------------------- ------------------- + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -3.163 0.255 f clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.544 0.798 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.827 f ref_buffer/O + net (fo=67, routed) 0.768 1.595 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/clk_ref_i + IDELAYCTRL_X1Y1 IDELAYCTRL f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/u_idelayctrl_200/REFCLK + ------------------------------------------------------------------- ------------------- + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: clock_mmcm/CLKOUT2 + (clock source 'ref_raw' {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/u_idelayctrl_200/REFCLK + Path Group: (none) + Path Type: Min at Slow Process Corner + Data Path Delay: 3.031ns (logic 0.091ns (3.003%) route 2.940ns (96.997%)) + Logic Levels: 1 (BUFG=1) + Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.099ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + ------------------------------------------------------------------- ------------------- + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.324 -4.751 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.639 -3.112 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.021 r ref_buffer/O + net (fo=67, routed) 1.300 -1.720 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/clk_ref_i + IDELAYCTRL_X1Y1 IDELAYCTRL r ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/u_idelayctrl_200/REFCLK + ------------------------------------------------------------------- ------------------- + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: + To Clock: clk_pll_i + +Max Delay 33 Endpoints +Min Delay 33 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/LOCKED + (internal pin) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__11/PRE + (recovery check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 6.581ns (logic 0.124ns (1.884%) route 6.457ns (98.116%)) + Logic Levels: 1 (LUT4=1) + Clock Uncertainty: 0.193ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.132ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + MMCME2_ADV_X1Y1 MMCME2_ADV 0.000 0.000 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/LOCKED + net (fo=3, routed) 1.943 1.943 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rstdiv2_sync_r_reg[11] + SLICE_X89Y75 LUT4 (Prop_lut4_I0_O) 0.124 2.067 f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rstdiv2_sync_r[11]_i_1/O + net (fo=32, routed) 4.514 6.581 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_tmp + SLICE_X51Y119 FDPE f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__11/PRE + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.487 0.659 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + SLICE_X51Y119 FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__11/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/PHASELOCKED + (internal pin) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/pi_phase_locked_all_r1_reg/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 0.723ns (logic 0.045ns (6.224%) route 0.678ns (93.776%)) + Logic Levels: 1 (LUT2=1) + Clock Uncertainty: 0.193ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.132ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY 0.000 0.000 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/PHASELOCKED + net (fo=1, routed) 0.317 0.317 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in_n_6 + SLICE_X89Y75 LUT2 (Prop_lut2_I0_O) 0.045 0.362 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/pi_phase_locked_all_inferred_i_1/O + net (fo=1, routed) 0.361 0.723 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/in0 + SLICE_X81Y69 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/pi_phase_locked_all_r1_reg/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.437 -0.348 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.043 -0.305 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.494 0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.400 -1.211 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.544 -0.668 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -0.639 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.862 0.223 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg[14]_0 + SLICE_X81Y69 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/pi_phase_locked_all_r1_reg/C + + + + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/routed-utilization.rpt b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/routed-utilization.rpt new file mode 100644 index 0000000..fff2cb0 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/routed-utilization.rpt @@ -0,0 +1,264 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Tue Oct 13 01:31:53 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_utilization -file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/routed-utilization.rpt +| Design : toy_a7_top +| Device : xc7a100tcsg324-1 +| Speed File : -1 +| Design State : Routed +----------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++----------------------------+-------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++----------------------------+-------+-------+------------+-----------+-------+ +| Slice LUTs | 53929 | 0 | 0 | 63400 | 85.06 | +| LUT as Logic | 50007 | 0 | 0 | 63400 | 78.88 | +| LUT as Memory | 3922 | 0 | 0 | 19000 | 20.64 | +| LUT as Distributed RAM | 3644 | 0 | | | | +| LUT as Shift Register | 278 | 0 | | | | +| Slice Registers | 33943 | 0 | 0 | 126800 | 26.77 | +| Register as Flip Flop | 33943 | 0 | 0 | 126800 | 26.77 | +| Register as Latch | 0 | 0 | 0 | 126800 | 0.00 | +| F7 Muxes | 689 | 0 | 0 | 31700 | 2.17 | +| F8 Muxes | 112 | 0 | 0 | 15850 | 0.71 | ++----------------------------+-------+-------+------------+-----------+-------+ +* Warning! LUT value is adjusted to account for LUT combining. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 163 | Yes | - | Set | +| 140 | Yes | - | Reset | +| 562 | Yes | Set | - | +| 33078 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++--------------------------------------------+-------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++--------------------------------------------+-------+-------+------------+-----------+-------+ +| Slice | 15579 | 0 | 0 | 15850 | 98.29 | +| SLICEL | 10888 | 0 | | | | +| SLICEM | 4691 | 0 | | | | +| LUT as Logic | 50007 | 0 | 0 | 63400 | 78.88 | +| using O5 output only | 31 | | | | | +| using O6 output only | 37318 | | | | | +| using O5 and O6 | 12658 | | | | | +| LUT as Memory | 3922 | 0 | 0 | 19000 | 20.64 | +| LUT as Distributed RAM | 3644 | 0 | | | | +| using O5 output only | 0 | | | | | +| using O6 output only | 260 | | | | | +| using O5 and O6 | 3384 | | | | | +| LUT as Shift Register | 278 | 0 | | | | +| using O5 output only | 17 | | | | | +| using O6 output only | 160 | | | | | +| using O5 and O6 | 101 | | | | | +| Slice Registers | 33943 | 0 | 0 | 126800 | 26.77 | +| Register driven from within the Slice | 15009 | | | | | +| Register driven from outside the Slice | 18934 | | | | | +| LUT in front of the register is unused | 4958 | | | | | +| LUT in front of the register is used | 13976 | | | | | +| Unique Control Sets | 1256 | | 0 | 15850 | 7.92 | ++--------------------------------------------+-------+-------+------------+-----------+-------+ +* * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++-------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------------+------+-------+------------+-----------+-------+ +| Block RAM Tile | 31 | 0 | 0 | 135 | 22.96 | +| RAMB36/FIFO* | 27 | 0 | 0 | 135 | 20.00 | +| RAMB36E1 only | 27 | | | | | +| RAMB18 | 8 | 0 | 0 | 270 | 2.96 | +| RAMB18E1 only | 8 | | | | | ++-------------------+------+-------+------------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++----------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++----------------+------+-------+------------+-----------+-------+ +| DSPs | 117 | 0 | 0 | 240 | 48.75 | +| DSP48E1 only | 117 | | | | | ++----------------+------+-------+------------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-----------------------------+------+-------+------------+-----------+-------+ +| Bonded IOB | 60 | 60 | 0 | 210 | 28.57 | +| IOB Master Pads | 29 | | | | | +| IOB Slave Pads | 28 | | | | | +| Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 | +| PHY_CONTROL | 1 | 1 | 0 | 6 | 16.67 | +| PHASER_REF | 1 | 1 | 0 | 6 | 16.67 | +| OUT_FIFO | 4 | 4 | 0 | 24 | 16.67 | +| IN_FIFO | 2 | 2 | 0 | 24 | 8.33 | +| IDELAYCTRL | 1 | 0 | 0 | 6 | 16.67 | +| IBUFDS | 0 | 0 | 0 | 202 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 4 | 4 | 0 | 24 | 16.67 | +| PHASER_OUT_PHY only | 4 | 4 | | | | +| PHASER_IN/PHASER_IN_PHY | 2 | 2 | 0 | 24 | 8.33 | +| PHASER_IN_PHY only | 2 | 2 | | | | +| IDELAYE2/IDELAYE2_FINEDELAY | 16 | 16 | 0 | 300 | 5.33 | +| IDELAYE2 only | 16 | 16 | | | | +| ILOGIC | 16 | 16 | 0 | 210 | 7.62 | +| ISERDES | 16 | 16 | 0 | 210 | | +| OLOGIC | 46 | 46 | 0 | 210 | 21.90 | +| OUTFF_ODDR_Register | 3 | 3 | | | | +| TFF_ODDR_Register | 2 | 2 | | | | +| OSERDES | 43 | 43 | 0 | 210 | | ++-----------------------------+------+-------+------------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++------------+------+-------+------------+-----------+-------+ +| BUFGCTRL | 5 | 0 | 0 | 32 | 15.63 | +| BUFIO | 0 | 0 | 0 | 24 | 0.00 | +| MMCME2_ADV | 2 | 1 | 0 | 6 | 33.33 | +| PLLE2_ADV | 1 | 1 | 0 | 6 | 16.67 | +| BUFMRCE | 0 | 0 | 0 | 12 | 0.00 | +| BUFHCE | 1 | 0 | 0 | 96 | 1.04 | +| BUFR | 0 | 0 | 0 | 24 | 0.00 | ++------------+------+-------+------------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+------------+-----------+--------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------+------+-------+------------+-----------+--------+ +| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 | +| XADC | 1 | 0 | 0 | 1 | 100.00 | ++-------------+------+-------+------------+-----------+--------+ + + +8. Primitives +------------- + ++--------------------------+-------+---------------------+ +| Ref Name | Used | Functional Category | ++--------------------------+-------+---------------------+ +| FDRE | 33078 | Flop & Latch | +| LUT6 | 20391 | LUT | +| LUT3 | 13504 | LUT | +| LUT5 | 12689 | LUT | +| LUT4 | 10385 | LUT | +| RAMD32 | 5100 | Distributed Memory | +| LUT2 | 4885 | LUT | +| CARRY4 | 2073 | CarryLogic | +| RAMS32 | 1774 | Distributed Memory | +| LUT1 | 811 | LUT | +| MUXF7 | 689 | MuxFx | +| FDSE | 562 | Flop & Latch | +| SRL16E | 246 | Distributed Memory | +| FDPE | 163 | Flop & Latch | +| FDCE | 140 | Flop & Latch | +| SRLC32E | 133 | Distributed Memory | +| DSP48E1 | 117 | Block Arithmetic | +| RAMD64E | 112 | Distributed Memory | +| MUXF8 | 112 | MuxFx | +| OSERDESE2 | 43 | IO | +| RAMS64E | 42 | Distributed Memory | +| OBUF | 33 | IO | +| RAMB36E1 | 27 | Block Memory | +| OBUFT | 18 | IO | +| ISERDESE2 | 16 | IO | +| IDELAYE2 | 16 | IO | +| IBUF_INTERMDISABLE | 16 | IO | +| RAMB18E1 | 8 | Block Memory | +| ODDR | 5 | IO | +| BUFG | 5 | Clock | +| PHASER_OUT_PHY | 4 | IO | +| OUT_FIFO | 4 | IO | +| OBUFTDS | 4 | IO | +| IBUFDS_INTERMDISABLE_INT | 4 | IO | +| INV | 3 | LUT | +| IBUF | 3 | IO | +| PHASER_IN_PHY | 2 | IO | +| OBUFDS | 2 | IO | +| MMCME2_ADV | 2 | Clock | +| IN_FIFO | 2 | IO | +| XADC | 1 | Others | +| PLLE2_ADV | 1 | Clock | +| PHY_CONTROL | 1 | IO | +| PHASER_REF | 1 | IO | +| IDELAYCTRL | 1 | IO | +| BUFH | 1 | Clock | ++--------------------------+-------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++-------------+------+ +| Ref Name | Used | ++-------------+------+ +| toy_axi_cdc | 1 | +| arty_ddr3 | 1 | ++-------------+------+ + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/synth-hierarchy.rpt b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/synth-hierarchy.rpt new file mode 100644 index 0000000..b9cd65b --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/synth-hierarchy.rpt @@ -0,0 +1,1157 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Tue Oct 13 01:26:36 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_utilization -hierarchical -file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/synth-hierarchy.rpt +| Design : toy_a7_top +| Device : xc7a100tcsg324-1 +| Speed File : -1 +| Design State : Synthesized +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Utilization by Hierarchy + +1. Utilization by Hierarchy +--------------------------- + ++----------------------------------------------------------------------------------------+-----------------------------------------------------------------+------------+------------+---------+------+-------+--------+--------+------------+ +| Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP Blocks | ++----------------------------------------------------------------------------------------+-----------------------------------------------------------------+------------+------------+---------+------+-------+--------+--------+------------+ +| toy_a7_top | (top) | 57555 | 53496 | 3680 | 379 | 34174 | 27 | 8 | 117 | +| (toy_a7_top) | (top) | 7 | 7 | 0 | 0 | 65 | 0 | 0 | 0 | +| ddr_controller | arty_ddr3 | 5052 | 4446 | 452 | 154 | 4193 | 0 | 0 | 0 | +| (ddr_controller) | arty_ddr3 | 216 | 0 | 216 | 0 | 0 | 0 | 0 | 0 | +| u_arty_ddr3_mig | arty_ddr3_mig | 4836 | 4446 | 236 | 154 | 4193 | 0 | 0 | 0 | +| temp_mon_enabled.u_tempmon | arty_ddr3mig_7series_v4_2_tempmon | 39 | 39 | 0 | 0 | 122 | 0 | 0 | 0 | +| u_ddr3_clk_ibuf | arty_ddr3mig_7series_v4_2_clk_ibuf | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| u_ddr3_infrastructure | arty_ddr3mig_7series_v4_2_infrastructure | 27 | 27 | 0 | 0 | 58 | 0 | 0 | 0 | +| u_iodelay_ctrl | arty_ddr3mig_7series_v4_2_iodelay_ctrl | 2 | 2 | 0 | 0 | 15 | 0 | 0 | 0 | +| u_memc_ui_top_axi | arty_ddr3mig_7series_v4_2_memc_ui_top_axi | 4768 | 4378 | 236 | 154 | 3998 | 0 | 0 | 0 | +| (u_memc_ui_top_axi) | arty_ddr3mig_7series_v4_2_memc_ui_top_axi | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem_intfc0 | arty_ddr3mig_7series_v4_2_mem_intfc | 3681 | 3624 | 40 | 17 | 2902 | 0 | 0 | 0 | +| ddr_phy_top0 | arty_ddr3mig_7series_v4_2_ddr_phy_top | 3047 | 2999 | 32 | 16 | 2370 | 0 | 0 | 0 | +| (ddr_phy_top0) | arty_ddr3mig_7series_v4_2_ddr_phy_top | 3 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | +| u_ddr_calib_top | arty_ddr3mig_7series_v4_2_ddr_calib_top | 2376 | 2362 | 0 | 14 | 1986 | 0 | 0 | 0 | +| (u_ddr_calib_top) | arty_ddr3mig_7series_v4_2_ddr_calib_top | 107 | 106 | 0 | 1 | 29 | 0 | 0 | 0 | +| ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl | arty_ddr3mig_7series_v4_2_ddr_phy_rdlvl | 543 | 543 | 0 | 0 | 872 | 0 | 0 | 0 | +| ddr_phy_tempmon_0 | arty_ddr3mig_7series_v4_2_ddr_phy_tempmon | 258 | 258 | 0 | 0 | 229 | 0 | 0 | 0 | +| dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr | arty_ddr3mig_7series_v4_2_ddr_phy_dqs_found_cal_hr | 150 | 149 | 0 | 1 | 97 | 0 | 0 | 0 | +| mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay | arty_ddr3mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay | 17 | 16 | 0 | 1 | 16 | 0 | 0 | 0 | +| mb_wrlvl_inst.u_ddr_phy_wrlvl | arty_ddr3mig_7series_v4_2_ddr_phy_wrlvl | 266 | 265 | 0 | 1 | 160 | 0 | 0 | 0 | +| u_ddr_phy_init | arty_ddr3mig_7series_v4_2_ddr_phy_init | 872 | 868 | 0 | 4 | 279 | 0 | 0 | 0 | +| u_ddr_phy_wrcal | arty_ddr3mig_7series_v4_2_ddr_phy_wrcal | 163 | 157 | 0 | 6 | 304 | 0 | 0 | 0 | +| u_ddr_mc_phy_wrapper | arty_ddr3mig_7series_v4_2_ddr_mc_phy_wrapper | 668 | 634 | 32 | 2 | 384 | 0 | 0 | 0 | +| (u_ddr_mc_phy_wrapper) | arty_ddr3mig_7series_v4_2_ddr_mc_phy_wrapper | 0 | 0 | 0 | 0 | 24 | 0 | 0 | 0 | +| genblk24.phy_ctl_pre_fifo_0 | arty_ddr3mig_7series_v4_2_ddr_of_pre_fifo | 33 | 33 | 0 | 0 | 21 | 0 | 0 | 0 | +| genblk24.phy_ctl_pre_fifo_1 | arty_ddr3mig_7series_v4_2_ddr_of_pre_fifo__parameterized0 | 33 | 33 | 0 | 0 | 21 | 0 | 0 | 0 | +| genblk24.phy_ctl_pre_fifo_2 | arty_ddr3mig_7series_v4_2_ddr_of_pre_fifo__parameterized0_9 | 33 | 33 | 0 | 0 | 21 | 0 | 0 | 0 | +| u_ddr_mc_phy | arty_ddr3mig_7series_v4_2_ddr_mc_phy | 569 | 535 | 32 | 2 | 297 | 0 | 0 | 0 | +| (u_ddr_mc_phy) | arty_ddr3mig_7series_v4_2_ddr_mc_phy | 0 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | +| ddr_phy_4lanes_0.u_ddr_phy_4lanes | arty_ddr3mig_7series_v4_2_ddr_phy_4lanes | 569 | 535 | 32 | 2 | 281 | 0 | 0 | 0 | +| (ddr_phy_4lanes_0.u_ddr_phy_4lanes) | arty_ddr3mig_7series_v4_2_ddr_phy_4lanes | 10 | 9 | 0 | 1 | 20 | 0 | 0 | 0 | +| ddr_byte_lane_A.ddr_byte_lane_A | arty_ddr3mig_7series_v4_2_ddr_byte_lane | 55 | 23 | 32 | 0 | 20 | 0 | 0 | 0 | +| (ddr_byte_lane_A.ddr_byte_lane_A) | arty_ddr3mig_7series_v4_2_ddr_byte_lane | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | +| ddr_byte_group_io | arty_ddr3mig_7series_v4_2_ddr_byte_group_io | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| of_pre_fifo_gen.u_ddr_of_pre_fifo | arty_ddr3mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_14 | 54 | 22 | 32 | 0 | 19 | 0 | 0 | 0 | +| ddr_byte_lane_B.ddr_byte_lane_B | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized0 | 25 | 25 | 0 | 0 | 19 | 0 | 0 | 0 | +| (ddr_byte_lane_B.ddr_byte_lane_B) | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized0 | 9 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | +| ddr_byte_group_io | arty_ddr3mig_7series_v4_2_ddr_byte_group_io__parameterized0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| of_pre_fifo_gen.u_ddr_of_pre_fifo | arty_ddr3mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_13 | 16 | 16 | 0 | 0 | 19 | 0 | 0 | 0 | +| ddr_byte_lane_C.ddr_byte_lane_C | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized1 | 241 | 241 | 0 | 0 | 111 | 0 | 0 | 0 | +| (ddr_byte_lane_C.ddr_byte_lane_C) | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized1 | 7 | 7 | 0 | 0 | 69 | 0 | 0 | 0 | +| ddr_byte_group_io | arty_ddr3mig_7series_v4_2_ddr_byte_group_io__parameterized1_10 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo | arty_ddr3mig_7series_v4_2_ddr_if_post_fifo_11 | 212 | 212 | 0 | 0 | 17 | 0 | 0 | 0 | +| of_pre_fifo_gen.u_ddr_of_pre_fifo | arty_ddr3mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_12 | 22 | 22 | 0 | 0 | 24 | 0 | 0 | 0 | +| ddr_byte_lane_D.ddr_byte_lane_D | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized2 | 238 | 237 | 0 | 1 | 111 | 0 | 0 | 0 | +| (ddr_byte_lane_D.ddr_byte_lane_D) | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized2 | 0 | 0 | 0 | 0 | 69 | 0 | 0 | 0 | +| ddr_byte_group_io | arty_ddr3mig_7series_v4_2_ddr_byte_group_io__parameterized1 | 2 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | +| dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo | arty_ddr3mig_7series_v4_2_ddr_if_post_fifo | 215 | 215 | 0 | 0 | 17 | 0 | 0 | 0 | +| of_pre_fifo_gen.u_ddr_of_pre_fifo | arty_ddr3mig_7series_v4_2_ddr_of_pre_fifo__parameterized1 | 21 | 21 | 0 | 0 | 24 | 0 | 0 | 0 | +| mc0 | arty_ddr3mig_7series_v4_2_mc | 634 | 625 | 8 | 1 | 532 | 0 | 0 | 0 | +| (mc0) | arty_ddr3mig_7series_v4_2_mc | 8 | 8 | 0 | 0 | 73 | 0 | 0 | 0 | +| bank_mach0 | arty_ddr3mig_7series_v4_2_bank_mach | 508 | 508 | 0 | 0 | 362 | 0 | 0 | 0 | +| arb_mux0 | arty_ddr3mig_7series_v4_2_arb_mux | 197 | 197 | 0 | 0 | 45 | 0 | 0 | 0 | +| arb_row_col0 | arty_ddr3mig_7series_v4_2_arb_row_col | 197 | 197 | 0 | 0 | 40 | 0 | 0 | 0 | +| (arb_row_col0) | arty_ddr3mig_7series_v4_2_arb_row_col | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | +| col_arb0 | arty_ddr3mig_7series_v4_2_round_robin_arb__parameterized1 | 66 | 66 | 0 | 0 | 8 | 0 | 0 | 0 | +| config_arb0 | arty_ddr3mig_7series_v4_2_round_robin_arb__parameterized1_6 | 17 | 17 | 0 | 0 | 8 | 0 | 0 | 0 | +| pre_4_1_1T_arb.pre_arb0 | arty_ddr3mig_7series_v4_2_round_robin_arb__parameterized1_7 | 47 | 47 | 0 | 0 | 8 | 0 | 0 | 0 | +| row_arb0 | arty_ddr3mig_7series_v4_2_round_robin_arb__parameterized1_8 | 65 | 65 | 0 | 0 | 8 | 0 | 0 | 0 | +| arb_select0 | arty_ddr3mig_7series_v4_2_arb_select | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| bank_cntrl[0].bank0 | arty_ddr3mig_7series_v4_2_bank_cntrl | 72 | 72 | 0 | 0 | 75 | 0 | 0 | 0 | +| bank_compare0 | arty_ddr3mig_7series_v4_2_bank_compare_5 | 8 | 8 | 0 | 0 | 35 | 0 | 0 | 0 | +| bank_queue0 | arty_ddr3mig_7series_v4_2_bank_queue | 41 | 41 | 0 | 0 | 18 | 0 | 0 | 0 | +| bank_state0 | arty_ddr3mig_7series_v4_2_bank_state | 23 | 23 | 0 | 0 | 22 | 0 | 0 | 0 | +| bank_cntrl[1].bank0 | arty_ddr3mig_7series_v4_2_bank_cntrl__parameterized0 | 70 | 70 | 0 | 0 | 73 | 0 | 0 | 0 | +| bank_compare0 | arty_ddr3mig_7series_v4_2_bank_compare_4 | 13 | 13 | 0 | 0 | 35 | 0 | 0 | 0 | +| bank_queue0 | arty_ddr3mig_7series_v4_2_bank_queue__parameterized0 | 36 | 36 | 0 | 0 | 18 | 0 | 0 | 0 | +| bank_state0 | arty_ddr3mig_7series_v4_2_bank_state__parameterized0 | 21 | 21 | 0 | 0 | 20 | 0 | 0 | 0 | +| bank_cntrl[2].bank0 | arty_ddr3mig_7series_v4_2_bank_cntrl__parameterized1 | 71 | 71 | 0 | 0 | 74 | 0 | 0 | 0 | +| bank_compare0 | arty_ddr3mig_7series_v4_2_bank_compare_3 | 10 | 10 | 0 | 0 | 35 | 0 | 0 | 0 | +| bank_queue0 | arty_ddr3mig_7series_v4_2_bank_queue__parameterized1 | 33 | 33 | 0 | 0 | 18 | 0 | 0 | 0 | +| bank_state0 | arty_ddr3mig_7series_v4_2_bank_state__parameterized1 | 28 | 28 | 0 | 0 | 21 | 0 | 0 | 0 | +| bank_cntrl[3].bank0 | arty_ddr3mig_7series_v4_2_bank_cntrl__parameterized2 | 72 | 72 | 0 | 0 | 73 | 0 | 0 | 0 | +| bank_compare0 | arty_ddr3mig_7series_v4_2_bank_compare | 14 | 14 | 0 | 0 | 35 | 0 | 0 | 0 | +| bank_queue0 | arty_ddr3mig_7series_v4_2_bank_queue__parameterized2 | 33 | 33 | 0 | 0 | 18 | 0 | 0 | 0 | +| bank_state0 | arty_ddr3mig_7series_v4_2_bank_state__parameterized2 | 25 | 25 | 0 | 0 | 20 | 0 | 0 | 0 | +| bank_common0 | arty_ddr3mig_7series_v4_2_bank_common | 26 | 26 | 0 | 0 | 22 | 0 | 0 | 0 | +| col_mach0 | arty_ddr3mig_7series_v4_2_col_mach | 27 | 19 | 8 | 0 | 26 | 0 | 0 | 0 | +| rank_mach0 | arty_ddr3mig_7series_v4_2_rank_mach | 91 | 90 | 0 | 1 | 71 | 0 | 0 | 0 | +| rank_cntrl[0].rank_cntrl0 | arty_ddr3mig_7series_v4_2_rank_cntrl | 11 | 10 | 0 | 1 | 13 | 0 | 0 | 0 | +| rank_common0 | arty_ddr3mig_7series_v4_2_rank_common | 80 | 80 | 0 | 0 | 58 | 0 | 0 | 0 | +| (rank_common0) | arty_ddr3mig_7series_v4_2_rank_common | 67 | 67 | 0 | 0 | 52 | 0 | 0 | 0 | +| maintenance_request.maint_arb0 | arty_ddr3mig_7series_v4_2_round_robin_arb | 13 | 13 | 0 | 0 | 6 | 0 | 0 | 0 | +| u_axi_mc | arty_ddr3mig_7series_v4_2_axi_mc | 615 | 478 | 0 | 137 | 544 | 0 | 0 | 0 | +| (u_axi_mc) | arty_ddr3mig_7series_v4_2_axi_mc | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| axi_mc_ar_channel_0 | arty_ddr3mig_7series_v4_2_axi_mc_ar_channel | 129 | 129 | 0 | 0 | 93 | 0 | 0 | 0 | +| (axi_mc_ar_channel_0) | arty_ddr3mig_7series_v4_2_axi_mc_ar_channel | 1 | 1 | 0 | 0 | 48 | 0 | 0 | 0 | +| ar_cmd_fsm_0 | arty_ddr3mig_7series_v4_2_axi_mc_cmd_fsm | 83 | 83 | 0 | 0 | 1 | 0 | 0 | 0 | +| axi_mc_cmd_translator_0 | arty_ddr3mig_7series_v4_2_axi_mc_cmd_translator_0 | 46 | 46 | 0 | 0 | 44 | 0 | 0 | 0 | +| axi_mc_incr_cmd_0 | arty_ddr3mig_7series_v4_2_axi_mc_incr_cmd_1 | 38 | 38 | 0 | 0 | 36 | 0 | 0 | 0 | +| axi_mc_wrap_cmd_0 | arty_ddr3mig_7series_v4_2_axi_mc_wrap_cmd_2 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| axi_mc_aw_channel_0 | arty_ddr3mig_7series_v4_2_axi_mc_aw_channel | 132 | 132 | 0 | 0 | 91 | 0 | 0 | 0 | +| (axi_mc_aw_channel_0) | arty_ddr3mig_7series_v4_2_axi_mc_aw_channel | 0 | 0 | 0 | 0 | 46 | 0 | 0 | 0 | +| aw_cmd_fsm_0 | arty_ddr3mig_7series_v4_2_axi_mc_wr_cmd_fsm | 82 | 82 | 0 | 0 | 1 | 0 | 0 | 0 | +| axi_mc_cmd_translator_0 | arty_ddr3mig_7series_v4_2_axi_mc_cmd_translator | 51 | 51 | 0 | 0 | 44 | 0 | 0 | 0 | +| axi_mc_incr_cmd_0 | arty_ddr3mig_7series_v4_2_axi_mc_incr_cmd | 43 | 43 | 0 | 0 | 36 | 0 | 0 | 0 | +| axi_mc_wrap_cmd_0 | arty_ddr3mig_7series_v4_2_axi_mc_wrap_cmd | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| axi_mc_b_channel_0 | arty_ddr3mig_7series_v4_2_axi_mc_b_channel | 12 | 8 | 0 | 4 | 9 | 0 | 0 | 0 | +| (axi_mc_b_channel_0) | arty_ddr3mig_7series_v4_2_axi_mc_b_channel | 1 | 1 | 0 | 0 | 5 | 0 | 0 | 0 | +| bid_fifo_0 | arty_ddr3mig_7series_v4_2_axi_mc_fifo | 11 | 7 | 0 | 4 | 4 | 0 | 0 | 0 | +| axi_mc_cmd_arbiter_0 | arty_ddr3mig_7series_v4_2_axi_mc_cmd_arbiter | 34 | 34 | 0 | 0 | 31 | 0 | 0 | 0 | +| axi_mc_r_channel_0 | arty_ddr3mig_7series_v4_2_axi_mc_r_channel | 160 | 27 | 0 | 133 | 24 | 0 | 0 | 0 | +| (axi_mc_r_channel_0) | arty_ddr3mig_7series_v4_2_axi_mc_r_channel | 0 | 0 | 0 | 0 | 12 | 0 | 0 | 0 | +| rd_data_fifo_0 | arty_ddr3mig_7series_v4_2_axi_mc_fifo__parameterized0 | 141 | 13 | 0 | 128 | 6 | 0 | 0 | 0 | +| transaction_fifo_0 | arty_ddr3mig_7series_v4_2_axi_mc_fifo__parameterized1 | 19 | 14 | 0 | 5 | 6 | 0 | 0 | 0 | +| axi_mc_w_channel_0 | arty_ddr3mig_7series_v4_2_axi_mc_w_channel | 147 | 147 | 0 | 0 | 294 | 0 | 0 | 0 | +| u_ui_top | arty_ddr3mig_7series_v4_2_ui_top | 472 | 276 | 196 | 0 | 550 | 0 | 0 | 0 | +| ui_cmd0 | arty_ddr3mig_7series_v4_2_ui_cmd | 38 | 38 | 0 | 0 | 54 | 0 | 0 | 0 | +| ui_rd_data0 | arty_ddr3mig_7series_v4_2_ui_rd_data | 124 | 32 | 92 | 0 | 163 | 0 | 0 | 0 | +| ui_wr_data0 | arty_ddr3mig_7series_v4_2_ui_wr_data | 310 | 206 | 104 | 0 | 333 | 0 | 0 | 0 | +| memory_cdc | toy_axi_cdc | 530 | 252 | 278 | 0 | 1326 | 0 | 0 | 0 | +| (memory_cdc) | toy_axi_cdc | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| inst | toy_axi_cdcaxi_clock_converter_v2_1_30_axi_clock_converter | 530 | 252 | 278 | 0 | 1326 | 0 | 0 | 0 | +| (inst) | toy_axi_cdcaxi_clock_converter_v2_1_30_axi_clock_converter | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | +| gen_clock_conv.gen_async_conv.asyncfifo_axi | toy_axi_cdcfifo_generator_v13_2_10 | 529 | 251 | 278 | 0 | 1326 | 0 | 0 | 0 | +| (gen_clock_conv.gen_async_conv.asyncfifo_axi) | toy_axi_cdcfifo_generator_v13_2_10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| inst_fifo_gen | toy_axi_cdcfifo_generator_v13_2_10_synth | 529 | 251 | 278 | 0 | 1326 | 0 | 0 | 0 | +| gaxi_full_lite.gread_ch.grach2.axi_rach | toy_axi_cdcfifo_generator_top | 92 | 50 | 42 | 0 | 221 | 0 | 0 | 0 | +| grf.rf | toy_axi_cdcfifo_generator_ramfifo | 92 | 50 | 42 | 0 | 221 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gcx.clkx | toy_axi_cdcclk_x_pntrs__xdcDup__4 | 12 | 12 | 0 | 0 | 40 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.gcx.clkx) | toy_axi_cdcclk_x_pntrs__xdcDup__4 | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | +| rd_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__17 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| wr_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__16 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.rd | toy_axi_cdcrd_logic_21 | 15 | 15 | 0 | 0 | 18 | 0 | 0 | 0 | +| gr1.gr1_int.rfwft | toy_axi_cdcrd_fwft_27 | 9 | 9 | 0 | 0 | 8 | 0 | 0 | 0 | +| gras.rsts | toy_axi_cdcrd_status_flags_as_28 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpntr | toy_axi_cdcrd_bin_cntr_29 | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.wr | toy_axi_cdcwr_logic_22 | 8 | 8 | 0 | 0 | 14 | 0 | 0 | 0 | +| gwas.wsts | toy_axi_cdcwr_status_flags_as_25 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | +| wpntr | toy_axi_cdcwr_bin_cntr_26 | 5 | 5 | 0 | 0 | 12 | 0 | 0 | 0 | +| gntv_or_sync_fifo.mem | toy_axi_cdcmemory_23 | 42 | 0 | 42 | 0 | 122 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.mem) | toy_axi_cdcmemory_23 | 0 | 0 | 0 | 0 | 61 | 0 | 0 | 0 | +| gdm.dm_gen.dm | toy_axi_cdcdmem_24 | 42 | 0 | 42 | 0 | 61 | 0 | 0 | 0 | +| rstblk | toy_axi_cdcreset_blk_ramfifo__xdcDup__4 | 15 | 15 | 0 | 0 | 27 | 0 | 0 | 0 | +| (rstblk) | toy_axi_cdcreset_blk_ramfifo__xdcDup__4 | 15 | 15 | 0 | 0 | 13 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__12 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | toy_axi_cdcxpm_cdc_single__parameterized1__17 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | toy_axi_cdcxpm_cdc_single__parameterized1__16 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__11 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gaxi_full_lite.gread_ch.grach2.cdc_wr_rst_busy_ic_3.xpm_cdc_single_inst3 | toy_axi_cdcxpm_cdc_single | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| gaxi_full_lite.gread_ch.grdch2.axi_rdch | toy_axi_cdcfifo_generator_top__parameterized2 | 143 | 51 | 92 | 0 | 369 | 0 | 0 | 0 | +| grf.rf | toy_axi_cdcfifo_generator_ramfifo__parameterized2 | 143 | 51 | 92 | 0 | 369 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gcx.clkx | toy_axi_cdcclk_x_pntrs | 12 | 12 | 0 | 0 | 40 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.gcx.clkx) | toy_axi_cdcclk_x_pntrs | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | +| rd_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| wr_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__18 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.rd | toy_axi_cdcrd_logic_14 | 15 | 15 | 0 | 0 | 18 | 0 | 0 | 0 | +| gr1.gr1_int.rfwft | toy_axi_cdcrd_fwft_18 | 9 | 9 | 0 | 0 | 8 | 0 | 0 | 0 | +| gras.rsts | toy_axi_cdcrd_status_flags_as_19 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpntr | toy_axi_cdcrd_bin_cntr_20 | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.wr | toy_axi_cdcwr_logic_15 | 8 | 8 | 0 | 0 | 14 | 0 | 0 | 0 | +| gwas.wsts | toy_axi_cdcwr_status_flags_as_16 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | +| wpntr | toy_axi_cdcwr_bin_cntr_17 | 5 | 5 | 0 | 0 | 12 | 0 | 0 | 0 | +| gntv_or_sync_fifo.mem | toy_axi_cdcmemory__parameterized2 | 92 | 0 | 92 | 0 | 270 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.mem) | toy_axi_cdcmemory__parameterized2 | 0 | 0 | 0 | 0 | 135 | 0 | 0 | 0 | +| gdm.dm_gen.dm | toy_axi_cdcdmem__parameterized2 | 92 | 0 | 92 | 0 | 135 | 0 | 0 | 0 | +| rstblk | toy_axi_cdcreset_blk_ramfifo | 16 | 16 | 0 | 0 | 27 | 0 | 0 | 0 | +| (rstblk) | toy_axi_cdcreset_blk_ramfifo | 16 | 16 | 0 | 0 | 13 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | toy_axi_cdcxpm_cdc_async_rst | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | toy_axi_cdcxpm_cdc_single__parameterized1 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | toy_axi_cdcxpm_cdc_single__parameterized1__18 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__13 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gaxi_full_lite.gwrite_ch.gwach2.axi_wach | toy_axi_cdcfifo_generator_top__xdcDup__1 | 92 | 50 | 42 | 0 | 221 | 0 | 0 | 0 | +| grf.rf | toy_axi_cdcfifo_generator_ramfifo__xdcDup__1 | 92 | 50 | 42 | 0 | 221 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gcx.clkx | toy_axi_cdcclk_x_pntrs__xdcDup__1 | 12 | 12 | 0 | 0 | 40 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.gcx.clkx) | toy_axi_cdcclk_x_pntrs__xdcDup__1 | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | +| rd_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__11 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| wr_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__10 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.rd | toy_axi_cdcrd_logic_7 | 15 | 15 | 0 | 0 | 18 | 0 | 0 | 0 | +| gr1.gr1_int.rfwft | toy_axi_cdcrd_fwft_11 | 9 | 9 | 0 | 0 | 8 | 0 | 0 | 0 | +| gras.rsts | toy_axi_cdcrd_status_flags_as_12 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpntr | toy_axi_cdcrd_bin_cntr_13 | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.wr | toy_axi_cdcwr_logic_8 | 8 | 8 | 0 | 0 | 14 | 0 | 0 | 0 | +| gwas.wsts | toy_axi_cdcwr_status_flags_as_9 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | +| wpntr | toy_axi_cdcwr_bin_cntr_10 | 5 | 5 | 0 | 0 | 12 | 0 | 0 | 0 | +| gntv_or_sync_fifo.mem | toy_axi_cdcmemory | 42 | 0 | 42 | 0 | 122 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.mem) | toy_axi_cdcmemory | 0 | 0 | 0 | 0 | 61 | 0 | 0 | 0 | +| gdm.dm_gen.dm | toy_axi_cdcdmem | 42 | 0 | 42 | 0 | 61 | 0 | 0 | 0 | +| rstblk | toy_axi_cdcreset_blk_ramfifo__xdcDup__1 | 15 | 15 | 0 | 0 | 27 | 0 | 0 | 0 | +| (rstblk) | toy_axi_cdcreset_blk_ramfifo__xdcDup__1 | 15 | 15 | 0 | 0 | 13 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__6 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | toy_axi_cdcxpm_cdc_single__parameterized1__11 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | toy_axi_cdcxpm_cdc_single__parameterized1__10 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__5 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gaxi_full_lite.gwrite_ch.gwach2.cdc_wr_rst_busy_ic_1.xpm_cdc_single_inst1 | toy_axi_cdcxpm_cdc_single__3 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch | toy_axi_cdcfifo_generator_top__parameterized0 | 148 | 50 | 98 | 0 | 389 | 0 | 0 | 0 | +| grf.rf | toy_axi_cdcfifo_generator_ramfifo__parameterized0 | 148 | 50 | 98 | 0 | 389 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gcx.clkx | toy_axi_cdcclk_x_pntrs__xdcDup__2 | 12 | 12 | 0 | 0 | 40 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.gcx.clkx) | toy_axi_cdcclk_x_pntrs__xdcDup__2 | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | +| rd_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__13 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| wr_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__12 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.rd | toy_axi_cdcrd_logic_0 | 15 | 15 | 0 | 0 | 18 | 0 | 0 | 0 | +| gr1.gr1_int.rfwft | toy_axi_cdcrd_fwft_4 | 9 | 9 | 0 | 0 | 8 | 0 | 0 | 0 | +| gras.rsts | toy_axi_cdcrd_status_flags_as_5 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpntr | toy_axi_cdcrd_bin_cntr_6 | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.wr | toy_axi_cdcwr_logic_1 | 8 | 8 | 0 | 0 | 14 | 0 | 0 | 0 | +| gwas.wsts | toy_axi_cdcwr_status_flags_as_2 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | +| wpntr | toy_axi_cdcwr_bin_cntr_3 | 5 | 5 | 0 | 0 | 12 | 0 | 0 | 0 | +| gntv_or_sync_fifo.mem | toy_axi_cdcmemory__parameterized0 | 98 | 0 | 98 | 0 | 290 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.mem) | toy_axi_cdcmemory__parameterized0 | 0 | 0 | 0 | 0 | 145 | 0 | 0 | 0 | +| gdm.dm_gen.dm | toy_axi_cdcdmem__parameterized0 | 98 | 0 | 98 | 0 | 145 | 0 | 0 | 0 | +| rstblk | toy_axi_cdcreset_blk_ramfifo__xdcDup__2 | 15 | 15 | 0 | 0 | 27 | 0 | 0 | 0 | +| (rstblk) | toy_axi_cdcreset_blk_ramfifo__xdcDup__2 | 15 | 15 | 0 | 0 | 13 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__8 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | toy_axi_cdcxpm_cdc_single__parameterized1__13 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | toy_axi_cdcxpm_cdc_single__parameterized1__12 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__7 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gaxi_full_lite.gwrite_ch.gwdch2.cdc_wr_rst_busy_ic_2.xpm_cdc_single_inst2 | toy_axi_cdcxpm_cdc_single__4 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch | toy_axi_cdcfifo_generator_top__parameterized1 | 54 | 50 | 4 | 0 | 111 | 0 | 0 | 0 | +| grf.rf | toy_axi_cdcfifo_generator_ramfifo__parameterized1 | 54 | 50 | 4 | 0 | 111 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gcx.clkx | toy_axi_cdcclk_x_pntrs__xdcDup__3 | 12 | 12 | 0 | 0 | 40 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.gcx.clkx) | toy_axi_cdcclk_x_pntrs__xdcDup__3 | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | +| rd_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__15 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| wr_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__14 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.rd | toy_axi_cdcrd_logic | 15 | 15 | 0 | 0 | 18 | 0 | 0 | 0 | +| gr1.gr1_int.rfwft | toy_axi_cdcrd_fwft | 9 | 9 | 0 | 0 | 8 | 0 | 0 | 0 | +| gras.rsts | toy_axi_cdcrd_status_flags_as | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpntr | toy_axi_cdcrd_bin_cntr | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.wr | toy_axi_cdcwr_logic | 8 | 8 | 0 | 0 | 14 | 0 | 0 | 0 | +| gwas.wsts | toy_axi_cdcwr_status_flags_as | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | +| wpntr | toy_axi_cdcwr_bin_cntr | 5 | 5 | 0 | 0 | 12 | 0 | 0 | 0 | +| gntv_or_sync_fifo.mem | toy_axi_cdcmemory__parameterized1 | 4 | 0 | 4 | 0 | 12 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.mem) | toy_axi_cdcmemory__parameterized1 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | +| gdm.dm_gen.dm | toy_axi_cdcdmem__parameterized1 | 4 | 0 | 4 | 0 | 6 | 0 | 0 | 0 | +| rstblk | toy_axi_cdcreset_blk_ramfifo__xdcDup__3 | 15 | 15 | 0 | 0 | 27 | 0 | 0 | 0 | +| (rstblk) | toy_axi_cdcreset_blk_ramfifo__xdcDup__3 | 15 | 15 | 0 | 0 | 13 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__10 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | toy_axi_cdcxpm_cdc_single__parameterized1__15 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | toy_axi_cdcxpm_cdc_single__parameterized1__14 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__9 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| platform | toy_a7_platform | 51966 | 48791 | 2950 | 225 | 28590 | 27 | 8 | 117 | +| chip | ToyLinuxChip | 50944 | 47881 | 2838 | 225 | 27538 | 27 | 8 | 117 | +| system | ToyLinuxSystem | 50944 | 47881 | 2838 | 225 | 27538 | 27 | 8 | 117 | +| (system) | ToyLinuxSystem | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | +| bootrom_domain | bootromClockSinkDomain | 462 | 462 | 0 | 0 | 0 | 0 | 0 | 0 | +| bootrom | TLROM | 462 | 462 | 0 | 0 | 0 | 0 | 0 | 0 | +| cbus | PeripheryBus_cbus | 1023 | 869 | 154 | 0 | 364 | 0 | 0 | 0 | +| atomics | TLAtomicAutomata_cbus | 407 | 407 | 0 | 0 | 203 | 0 | 0 | 0 | +| buffer | TLBuffer_a28d64s3k1z4u | 263 | 133 | 130 | 0 | 6 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a28d64s3k1z4u | 111 | 57 | 54 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q) | Queue2_TLBundleD_a28d64s3k1z4u | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x79_445 | 107 | 53 | 54 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a28d64s3k1z4u | 152 | 76 | 76 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a28d64s3k1z4u | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x114 | 151 | 75 | 76 | 0 | 0 | 0 | 0 | 0 | +| coupler_to_bootrom | TLInterconnectCoupler_cbus_to_bootrom | 85 | 85 | 0 | 0 | 29 | 0 | 0 | 0 | +| fragmenter | TLFragmenter_bootrom | 85 | 85 | 0 | 0 | 29 | 0 | 0 | 0 | +| (fragmenter) | TLFragmenter_bootrom | 1 | 1 | 0 | 0 | 9 | 0 | 0 | 0 | +| repeater | Repeater_TLBundleA_a17d64s3k1z3u | 84 | 84 | 0 | 0 | 20 | 0 | 0 | 0 | +| coupler_to_clint | TLInterconnectCoupler_cbus_to_clint | 79 | 79 | 0 | 0 | 32 | 0 | 0 | 0 | +| fragmenter | TLFragmenter_CLINT | 79 | 79 | 0 | 0 | 32 | 0 | 0 | 0 | +| (fragmenter) | TLFragmenter_CLINT | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | +| repeater | Repeater_TLBundleA_a26d64s3k1z3u | 79 | 79 | 0 | 0 | 23 | 0 | 0 | 0 | +| coupler_to_plic | TLInterconnectCoupler_cbus_to_plic | 24 | 24 | 0 | 0 | 42 | 0 | 0 | 0 | +| fragmenter | TLFragmenter_PLIC | 24 | 24 | 0 | 0 | 42 | 0 | 0 | 0 | +| (fragmenter) | TLFragmenter_PLIC | 3 | 3 | 0 | 0 | 9 | 0 | 0 | 0 | +| repeater | Repeater_TLBundleA_a28d64s3k1z3u | 21 | 21 | 0 | 0 | 33 | 0 | 0 | 0 | +| out_xbar | TLXbar_cbus_out_i1_o4_a28d64s3k1z4u | 83 | 83 | 0 | 0 | 17 | 0 | 0 | 0 | +| wrapped_error_device | ErrorDeviceWrapper | 82 | 58 | 24 | 0 | 35 | 0 | 0 | 0 | +| buffer | TLBuffer_a14d64s3k1z4u | 44 | 20 | 24 | 0 | 6 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a14d64s3k1z4u | 29 | 17 | 12 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q) | Queue2_TLBundleD_a14d64s3k1z4u | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x79 | 25 | 13 | 12 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a14d64s3k1z4u | 15 | 3 | 12 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a14d64s3k1z4u | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x100 | 13 | 1 | 12 | 0 | 0 | 0 | 0 | 0 | +| error | TLError | 38 | 38 | 0 | 0 | 29 | 0 | 0 | 0 | +| (error) | TLError | 7 | 7 | 0 | 0 | 18 | 0 | 0 | 0 | +| a_q | Queue1_TLBundleA_a14d64s3k1z4u | 31 | 31 | 0 | 0 | 11 | 0 | 0 | 0 | +| clint_domain | CLINTClockSinkDomain | 70 | 70 | 0 | 0 | 131 | 0 | 0 | 0 | +| clint | CLINT | 70 | 70 | 0 | 0 | 129 | 0 | 0 | 0 | +| intsource | IntSyncCrossingSource_n1x2 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| reg_0 | AsyncResetRegVec_w2_i0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| coh_wrapper | CoherenceManagerWrapper | 549 | 357 | 192 | 0 | 142 | 0 | 0 | 0 | +| broadcast_1 | TLBroadcast | 549 | 357 | 192 | 0 | 142 | 0 | 0 | 0 | +| (broadcast_1) | TLBroadcast | 17 | 17 | 0 | 0 | 44 | 0 | 0 | 0 | +| TLBroadcastTracker | TLBroadcastTracker | 384 | 288 | 96 | 0 | 49 | 0 | 0 | 0 | +| (TLBroadcastTracker) | TLBroadcastTracker | 20 | 20 | 0 | 0 | 44 | 0 | 0 | 0 | +| o_data_q | Queue4_TLBroadcastData_443 | 364 | 268 | 96 | 0 | 5 | 0 | 0 | 0 | +| (o_data_q) | Queue4_TLBroadcastData_443 | 102 | 102 | 0 | 0 | 5 | 0 | 0 | 0 | +| ram_ext | ram_4x144_444 | 262 | 166 | 96 | 0 | 0 | 0 | 0 | 0 | +| TLBroadcastTracker_1 | TLBroadcastTracker_1 | 148 | 52 | 96 | 0 | 49 | 0 | 0 | 0 | +| (TLBroadcastTracker_1) | TLBroadcastTracker_1 | 32 | 32 | 0 | 0 | 44 | 0 | 0 | 0 | +| o_data_q | Queue4_TLBroadcastData | 116 | 20 | 96 | 0 | 5 | 0 | 0 | 0 | +| (o_data_q) | Queue4_TLBroadcastData | 15 | 15 | 0 | 0 | 5 | 0 | 0 | 0 | +| ram_ext | ram_4x144 | 101 | 5 | 96 | 0 | 0 | 0 | 0 | 0 | +| ibus_intsink | IntSyncAsyncCrossingSink_n1x1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | +| chain | SynchronizerShiftReg_w1_d3 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | +| output_chain | NonSyncResetSynchronizerPrimitiveShiftReg_d3 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | +| ibus_intsource | IntSyncCrossingSource_n1x1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| reg_0__0 | AsyncResetRegVec_w1_i0_442 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| mbus | MemoryBus | 745 | 489 | 256 | 0 | 330 | 0 | 0 | 0 | +| coupler_to_memory_controller_port_named_axi4 | TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4 | 745 | 489 | 256 | 0 | 330 | 0 | 0 | 0 | +| axi4yank | AXI4UserYanker_1 | 439 | 183 | 256 | 0 | 96 | 0 | 0 | 0 | +| Queue2_BundleMap | Queue2_BundleMap_6 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap) | Queue2_BundleMap_6 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_441 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_1 | Queue2_BundleMap_6_380 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_1) | Queue2_BundleMap_6_380 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_440 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_10 | Queue2_BundleMap_6_381 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_10) | Queue2_BundleMap_6_381 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_439 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_11 | Queue2_BundleMap_6_382 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_11) | Queue2_BundleMap_6_382 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_438 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_12 | Queue2_BundleMap_6_383 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_12) | Queue2_BundleMap_6_383 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_437 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_13 | Queue2_BundleMap_6_384 | 9 | 1 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_13) | Queue2_BundleMap_6_384 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_436 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_14 | Queue2_BundleMap_6_385 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_14) | Queue2_BundleMap_6_385 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_435 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_15 | Queue2_BundleMap_6_386 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_15) | Queue2_BundleMap_6_386 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_434 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_16 | Queue2_BundleMap_6_387 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_16) | Queue2_BundleMap_6_387 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_433 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_17 | Queue2_BundleMap_6_388 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_17) | Queue2_BundleMap_6_388 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_432 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_18 | Queue2_BundleMap_6_389 | 14 | 6 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_18) | Queue2_BundleMap_6_389 | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_431 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_19 | Queue2_BundleMap_6_390 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_19) | Queue2_BundleMap_6_390 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_430 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_2 | Queue2_BundleMap_6_391 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_2) | Queue2_BundleMap_6_391 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_429 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_20 | Queue2_BundleMap_6_392 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_20) | Queue2_BundleMap_6_392 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_428 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_21 | Queue2_BundleMap_6_393 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_21) | Queue2_BundleMap_6_393 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_427 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_22 | Queue2_BundleMap_6_394 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_22) | Queue2_BundleMap_6_394 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_426 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_23 | Queue2_BundleMap_6_395 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_23) | Queue2_BundleMap_6_395 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_425 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_24 | Queue2_BundleMap_6_396 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_24) | Queue2_BundleMap_6_396 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_424 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_25 | Queue2_BundleMap_6_397 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_25) | Queue2_BundleMap_6_397 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_423 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_26 | Queue2_BundleMap_6_398 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_26) | Queue2_BundleMap_6_398 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_422 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_27 | Queue2_BundleMap_6_399 | 43 | 35 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_27) | Queue2_BundleMap_6_399 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_421 | 42 | 34 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_28 | Queue2_BundleMap_6_400 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_28) | Queue2_BundleMap_6_400 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_420 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_29 | Queue2_BundleMap_6_401 | 9 | 1 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_29) | Queue2_BundleMap_6_401 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_419 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_3 | Queue2_BundleMap_6_402 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_3) | Queue2_BundleMap_6_402 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_418 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_30 | Queue2_BundleMap_6_403 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_30) | Queue2_BundleMap_6_403 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_417 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_31 | Queue2_BundleMap_6_404 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_31) | Queue2_BundleMap_6_404 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_416 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_4 | Queue2_BundleMap_6_405 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_4) | Queue2_BundleMap_6_405 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_415 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_5 | Queue2_BundleMap_6_406 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_5) | Queue2_BundleMap_6_406 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_414 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_6 | Queue2_BundleMap_6_407 | 13 | 5 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_6) | Queue2_BundleMap_6_407 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_413 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_7 | Queue2_BundleMap_6_408 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_7) | Queue2_BundleMap_6_408 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_412 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_8 | Queue2_BundleMap_6_409 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_8) | Queue2_BundleMap_6_409 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_411 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_9 | Queue2_BundleMap_6_410 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_9) | Queue2_BundleMap_6_410 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| tl2axi4 | TLToAXI4_1 | 306 | 306 | 0 | 0 | 234 | 0 | 0 | 0 | +| (tl2axi4) | TLToAXI4_1 | 3 | 3 | 0 | 0 | 41 | 0 | 0 | 0 | +| nodeOut_w_deq_q | Queue1_AXI4BundleW_1 | 83 | 83 | 0 | 0 | 146 | 0 | 0 | 0 | +| queue_arw_deq_q | Queue1_AXI4BundleARW_1 | 220 | 220 | 0 | 0 | 47 | 0 | 0 | 0 | +| plic_domain | PLICClockSinkDomain | 36 | 36 | 0 | 0 | 52 | 0 | 0 | 0 | +| intsource | IntSyncCrossingSource_n1x1_377 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| reg_0 | AsyncResetRegVec_w1_i0_379 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| intsource_1 | IntSyncCrossingSource_n1x1_378 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| reg_0 | AsyncResetRegVec_w1_i0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| plic | TLPLIC | 36 | 36 | 0 | 0 | 50 | 0 | 0 | 0 | +| (plic) | TLPLIC | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | +| gateways_gateway | LevelGateway | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| out_back_front_q | Queue1_RegMapperInput_i23_m8 | 31 | 31 | 0 | 0 | 41 | 0 | 0 | 0 | +| sbus | SystemBus | 1457 | 1111 | 346 | 0 | 608 | 0 | 0 | 0 | +| coupler_to_bus_named_cbus | TLInterconnectCoupler_sbus_to_bus_named_cbus | 143 | 143 | 0 | 0 | 191 | 0 | 0 | 0 | +| widget | TLWidthWidget16 | 143 | 143 | 0 | 0 | 191 | 0 | 0 | 0 | +| (widget) | TLWidthWidget16 | 64 | 64 | 0 | 0 | 68 | 0 | 0 | 0 | +| repeated_repeater | Repeater_TLBundleA_a28d128s3k1z4u | 79 | 79 | 0 | 0 | 123 | 0 | 0 | 0 | +| coupler_to_port_named_mmio_port_axi4 | TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4 | 804 | 458 | 346 | 0 | 353 | 0 | 0 | 0 | +| axi4buf | AXI4Buffer | 207 | 69 | 138 | 0 | 15 | 0 | 0 | 0 | +| nodeIn_b_deq_q | Queue2_AXI4BundleB | 18 | 14 | 4 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_b_deq_q) | Queue2_AXI4BundleB | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x4 | 13 | 9 | 4 | 0 | 0 | 0 | 0 | 0 | +| nodeIn_r_deq_q | Queue2_AXI4BundleR | 42 | 6 | 36 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_r_deq_q) | Queue2_AXI4BundleR | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x69 | 39 | 3 | 36 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_ar_deq_q | Queue2_AXI4BundleAR | 61 | 29 | 32 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_ar_deq_q) | Queue2_AXI4BundleAR | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x58_376 | 57 | 25 | 32 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_aw_deq_q | Queue2_AXI4BundleAW | 48 | 16 | 32 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_aw_deq_q) | Queue2_AXI4BundleAW | 6 | 6 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x58 | 42 | 10 | 32 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_w_deq_q | Queue2_AXI4BundleW | 38 | 4 | 34 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_w_deq_q) | Queue2_AXI4BundleW | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x73 | 36 | 2 | 34 | 0 | 0 | 0 | 0 | 0 | +| axi4deint | AXI4Deinterleaver | 277 | 117 | 160 | 0 | 47 | 0 | 0 | 0 | +| (axi4deint) | AXI4Deinterleaver | 0 | 0 | 0 | 0 | 19 | 0 | 0 | 0 | +| qs_queue_0 | Queue8_AXI4BundleR | 51 | 11 | 40 | 0 | 7 | 0 | 0 | 0 | +| (qs_queue_0) | Queue8_AXI4BundleR | 8 | 8 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x77_375 | 43 | 3 | 40 | 0 | 0 | 0 | 0 | 0 | +| qs_queue_1 | Queue8_AXI4BundleR_370 | 73 | 33 | 40 | 0 | 7 | 0 | 0 | 0 | +| (qs_queue_1) | Queue8_AXI4BundleR_370 | 6 | 6 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x77_374 | 67 | 27 | 40 | 0 | 0 | 0 | 0 | 0 | +| qs_queue_2 | Queue8_AXI4BundleR_371 | 49 | 9 | 40 | 0 | 7 | 0 | 0 | 0 | +| (qs_queue_2) | Queue8_AXI4BundleR_371 | 6 | 6 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x77_373 | 43 | 3 | 40 | 0 | 0 | 0 | 0 | 0 | +| qs_queue_3 | Queue8_AXI4BundleR_372 | 104 | 64 | 40 | 0 | 7 | 0 | 0 | 0 | +| (qs_queue_3) | Queue8_AXI4BundleR_372 | 6 | 6 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x77 | 98 | 58 | 40 | 0 | 0 | 0 | 0 | 0 | +| axi4yank | AXI4UserYanker | 92 | 44 | 48 | 0 | 34 | 0 | 0 | 0 | +| Queue1_BundleMap | Queue1_BundleMap | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| Queue1_BundleMap_1 | Queue1_BundleMap_359 | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| Queue2_BundleMap | Queue2_BundleMap | 15 | 7 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap) | Queue2_BundleMap | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8_369 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_1 | Queue2_BundleMap_360 | 13 | 5 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_1) | Queue2_BundleMap_360 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8_368 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_2 | Queue2_BundleMap_361 | 14 | 6 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_2) | Queue2_BundleMap_361 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8_367 | 11 | 3 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_3 | Queue2_BundleMap_362 | 14 | 6 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_3) | Queue2_BundleMap_362 | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8_366 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_4 | Queue2_BundleMap_363 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_4) | Queue2_BundleMap_363 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8_365 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_5 | Queue2_BundleMap_364 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_5) | Queue2_BundleMap_364 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| tl2axi4 | TLToAXI4 | 127 | 127 | 0 | 0 | 114 | 0 | 0 | 0 | +| (tl2axi4) | TLToAXI4 | 22 | 22 | 0 | 0 | 17 | 0 | 0 | 0 | +| nodeOut_w_deq_q | Queue1_AXI4BundleW | 57 | 57 | 0 | 0 | 50 | 0 | 0 | 0 | +| queue_arw_deq_q | Queue1_AXI4BundleARW | 48 | 48 | 0 | 0 | 47 | 0 | 0 | 0 | +| widget | TLWidthWidget16_2 | 101 | 101 | 0 | 0 | 143 | 0 | 0 | 0 | +| (widget) | TLWidthWidget16_2 | 45 | 45 | 0 | 0 | 48 | 0 | 0 | 0 | +| repeated_repeater | Repeater_TLBundleA_a31d128s3k1z3u | 56 | 56 | 0 | 0 | 95 | 0 | 0 | 0 | +| system_bus_xbar | TLXbar_sbus_i2_o3_a32d128s3k1z4c | 510 | 510 | 0 | 0 | 64 | 0 | 0 | 0 | +| tile_prci_domain | TilePRCIDomain | 46597 | 44483 | 1890 | 224 | 25903 | 27 | 8 | 117 | +| buffer | TLBuffer_a32d128s2k1z4u_1 | 1214 | 628 | 586 | 0 | 21 | 0 | 0 | 0 | +| nodeIn_b_q | Queue2_TLBundleB_a32d128s2k1z4c | 28 | 4 | 24 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_b_q) | Queue2_TLBundleB_a32d128s2k1z4c | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x60 | 25 | 1 | 24 | 0 | 0 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a32d128s2k1z4u | 101 | 5 | 96 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q) | Queue2_TLBundleD_a32d128s2k1z4u | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x142_358 | 97 | 1 | 96 | 0 | 0 | 0 | 0 | 0 | +| nodeIn_d_q_1 | Queue2_TLBundleD_a32d128s2k1z4c | 161 | 65 | 96 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q_1) | Queue2_TLBundleD_a32d128s2k1z4c | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x142 | 158 | 62 | 96 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a32d128s2k1z4u | 144 | 16 | 128 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a32d128s2k1z4u | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x189_357 | 142 | 14 | 128 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q_1 | Queue2_TLBundleA_a32d128s2k1z4c | 646 | 518 | 128 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q_1) | Queue2_TLBundleA_a32d128s2k1z4c | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x189 | 643 | 515 | 128 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_c_q | Queue2_TLBundleC_a32d128s2k1z4c | 128 | 16 | 112 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_c_q) | Queue2_TLBundleC_a32d128s2k1z4c | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x173 | 125 | 13 | 112 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_e_q | Queue2_TLBundleE_a32d128s2k1z4c | 6 | 4 | 2 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_e_q) | Queue2_TLBundleE_a32d128s2k1z4c | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_sink_ext | ram_sink_2x1 | 3 | 1 | 2 | 0 | 0 | 0 | 0 | 0 | +| element_reset_domain_bbtile | BBTile | 45383 | 43855 | 1304 | 224 | 25882 | 27 | 8 | 117 | +| (element_reset_domain_bbtile) | BBTile | 24 | 0 | 24 | 0 | 0 | 0 | 0 | 0 | +| accelerators_0 | BuckyballAccelerator | 24384 | 23650 | 510 | 224 | 15033 | 18 | 0 | 95 | +| ballDomain | BallDomain | 14446 | 14032 | 190 | 224 | 10879 | 0 | 0 | 93 | +| ballRs | BallReservationStation | 148 | 52 | 96 | 0 | 5 | 0 | 0 | 0 | +| fifo | Queue4_BallReservationStation_Anon | 148 | 52 | 96 | 0 | 5 | 0 | 0 | 0 | +| (fifo) | Queue4_BallReservationStation_Anon | 3 | 3 | 0 | 0 | 5 | 0 | 0 | 0 | +| ram_ext | ram_4x281 | 145 | 49 | 96 | 0 | 0 | 0 | 0 | 0 | +| bbus | BBus | 14298 | 13980 | 94 | 224 | 10874 | 0 | 0 | 93 | +| (bbus) | BBus | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | +| balls_0 | GemminiBall | 14298 | 13980 | 94 | 224 | 10864 | 0 | 0 | 93 | +| (balls_0) | GemminiBall | 1 | 1 | 0 | 0 | 470 | 0 | 0 | 0 | +| convUnroller | LoopConvUnroller | 521 | 521 | 0 | 0 | 375 | 0 | 0 | 20 | +| (convUnroller) | LoopConvUnroller | 40 | 40 | 0 | 0 | 375 | 0 | 0 | 0 | +| addrGen | LoopConvAddrGen | 487 | 487 | 0 | 0 | 0 | 0 | 0 | 20 | +| exCtrl | GemminiExCtrl | 13112 | 12794 | 94 | 224 | 9717 | 0 | 0 | 64 | +| (exCtrl) | GemminiExCtrl | 1428 | 1428 | 0 | 0 | 2444 | 0 | 0 | 0 | +| mesh | MeshWithDelays | 11288 | 11058 | 6 | 224 | 7259 | 0 | 0 | 64 | +| (mesh) | MeshWithDelays | 632 | 408 | 0 | 224 | 557 | 0 | 0 | 0 | +| mesh | Mesh | 9993 | 9993 | 0 | 0 | 6098 | 0 | 0 | 64 | +| (mesh) | Mesh | 225 | 225 | 0 | 0 | 3530 | 0 | 0 | 0 | +| mesh_0_0 | Tile | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_354 | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_354 | 96 | 96 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_355 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_356 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_1 | Tile_104 | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_351 | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_351 | 96 | 96 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_352 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_353 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_2 | Tile_105 | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_348 | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_348 | 96 | 96 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_349 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_350 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_3 | Tile_106 | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_345 | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_345 | 96 | 96 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_346 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_347 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_4 | Tile_107 | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_342 | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_342 | 96 | 96 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_343 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_344 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_5 | Tile_108 | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_339 | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_339 | 96 | 96 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_340 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_341 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_6 | Tile_109 | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_336 | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_336 | 96 | 96 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_337 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_338 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_7 | Tile_110 | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_333 | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_333 | 96 | 96 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_334 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_335 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_0 | Tile_111 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_330 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_330 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_331 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_332 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_1 | Tile_112 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_327 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_327 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_328 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_329 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_2 | Tile_113 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_324 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_324 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_325 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_326 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_3 | Tile_114 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_321 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_321 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_322 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_323 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_4 | Tile_115 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_318 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_318 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_319 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_320 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_5 | Tile_116 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_315 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_315 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_316 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_317 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_6 | Tile_117 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_312 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_312 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_313 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_314 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_7 | Tile_118 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_309 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_309 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_310 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_311 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_0 | Tile_119 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_306 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_306 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_307 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_308 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_1 | Tile_120 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_303 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_303 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_304 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_305 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_2 | Tile_121 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_300 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_300 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_301 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_302 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_3 | Tile_122 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_297 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_297 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_298 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_299 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_4 | Tile_123 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_294 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_294 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_295 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_296 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_5 | Tile_124 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_291 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_291 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_292 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_293 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_6 | Tile_125 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_288 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_288 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_289 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_290 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_7 | Tile_126 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_285 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_285 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_286 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_287 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_0 | Tile_127 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_282 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_282 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_283 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_284 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_1 | Tile_128 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_279 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_279 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_280 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_281 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_2 | Tile_129 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_276 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_276 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_277 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_278 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_3 | Tile_130 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_273 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_273 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_274 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_275 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_4 | Tile_131 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_270 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_270 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_271 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_272 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_5 | Tile_132 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_267 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_267 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_268 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_269 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_6 | Tile_133 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_264 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_264 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_265 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_266 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_7 | Tile_134 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_261 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_261 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_262 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_263 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_0 | Tile_135 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_258 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_258 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_259 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_260 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_1 | Tile_136 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_255 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_255 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_256 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_257 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_2 | Tile_137 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_252 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_252 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_253 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_254 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_3 | Tile_138 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_249 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_249 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_250 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_251 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_4 | Tile_139 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_246 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_246 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_247 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_248 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_5 | Tile_140 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_243 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_243 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_244 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_245 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_6 | Tile_141 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_240 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_240 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_241 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_242 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_7 | Tile_142 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_237 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_237 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_238 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_239 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_0 | Tile_143 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_234 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_234 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_235 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_236 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_1 | Tile_144 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_231 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_231 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_232 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_233 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_2 | Tile_145 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_228 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_228 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_229 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_230 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_3 | Tile_146 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_225 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_225 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_226 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_227 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_4 | Tile_147 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_222 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_222 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_223 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_224 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_5 | Tile_148 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_219 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_219 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_220 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_221 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_6 | Tile_149 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_216 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_216 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_217 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_218 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_7 | Tile_150 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_213 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_213 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_214 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_215 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_0 | Tile_151 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_210 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_210 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_211 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_212 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_1 | Tile_152 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_207 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_207 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_208 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_209 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_2 | Tile_153 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_204 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_204 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_205 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_206 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_3 | Tile_154 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_201 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_201 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_202 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_203 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_4 | Tile_155 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_198 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_198 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_199 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_200 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_5 | Tile_156 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_195 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_195 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_196 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_197 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_6 | Tile_157 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_192 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_192 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_193 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_194 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_7 | Tile_158 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_189 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_189 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_190 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_191 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_0 | Tile_159 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_186 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_186 | 97 | 97 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_187 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_188 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_1 | Tile_160 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_183 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_183 | 97 | 97 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_184 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_185 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_2 | Tile_161 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_180 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_180 | 97 | 97 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_181 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_182 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_3 | Tile_162 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_177 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_177 | 97 | 97 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_178 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_179 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_4 | Tile_163 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_174 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_174 | 97 | 97 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_175 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_176 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_5 | Tile_164 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_171 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_171 | 97 | 97 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_172 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_173 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_6 | Tile_165 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_168 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_168 | 97 | 97 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_169 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_170 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_7 | Tile_166 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_167 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_167 | 97 | 97 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| tagq | TagQueue | 117 | 117 | 0 | 0 | 75 | 0 | 0 | 0 | +| total_rows_q | Queue6_TagWithIdAndTotalRows | 32 | 26 | 6 | 0 | 7 | 0 | 0 | 0 | +| (total_rows_q) | Queue6_TagWithIdAndTotalRows | 5 | 5 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_6x7 | 27 | 21 | 6 | 0 | 0 | 0 | 0 | 0 | +| transposer | AlwaysOutTransposer | 514 | 514 | 0 | 0 | 522 | 0 | 0 | 0 | +| (transposer) | AlwaysOutTransposer | 8 | 8 | 0 | 0 | 10 | 0 | 0 | 0 | +| pes_0_0 | PE | 17 | 17 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_1 | PE_41 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_2 | PE_42 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_3 | PE_43 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_4 | PE_44 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_5 | PE_45 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_6 | PE_46 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_7 | PE_47 | 32 | 32 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_0 | PE_48 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_1 | PE_49 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_2 | PE_50 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_3 | PE_51 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_4 | PE_52 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_5 | PE_53 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_6 | PE_54 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_7 | PE_55 | 13 | 13 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_0 | PE_56 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_1 | PE_57 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_2 | PE_58 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_3 | PE_59 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_4 | PE_60 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_5 | PE_61 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_6 | PE_62 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_7 | PE_63 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_0 | PE_64 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_1 | PE_65 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_2 | PE_66 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_3 | PE_67 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_4 | PE_68 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_5 | PE_69 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_6 | PE_70 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_7 | PE_71 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_0 | PE_72 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_1 | PE_73 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_2 | PE_74 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_3 | PE_75 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_4 | PE_76 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_5 | PE_77 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_6 | PE_78 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_7 | PE_79 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_0 | PE_80 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_1 | PE_81 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_2 | PE_82 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_3 | PE_83 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_4 | PE_84 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_5 | PE_85 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_6 | PE_86 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_7 | PE_87 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_0 | PE_88 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_1 | PE_89 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_2 | PE_90 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_3 | PE_91 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_4 | PE_92 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_5 | PE_93 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_6 | PE_94 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_7 | PE_95 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_0 | PE_96 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_1 | PE_97 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_2 | PE_98 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_3 | PE_99 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_4 | PE_100 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_5 | PE_101 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_6 | PE_102 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_7 | PE_103 | 16 | 16 | 0 | 0 | 8 | 0 | 0 | 0 | +| rdQueue0 | Queue8_SramReadResp | 306 | 262 | 44 | 0 | 7 | 0 | 0 | 0 | +| (rdQueue0) | Queue8_SramReadResp | 100 | 100 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_data_ext | ram_data_8x64_40 | 206 | 162 | 44 | 0 | 0 | 0 | 0 | 0 | +| rdQueue1 | Queue8_SramReadResp_39 | 90 | 46 | 44 | 0 | 7 | 0 | 0 | 0 | +| (rdQueue1) | Queue8_SramReadResp_39 | 44 | 44 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_data_ext | ram_data_8x64 | 46 | 2 | 44 | 0 | 0 | 0 | 0 | 0 | +| matmulUnroller | LoopMatmulUnroller | 664 | 664 | 0 | 0 | 302 | 0 | 0 | 9 | +| cmdRouter | CmdRouter | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| bankReadReqQ_q | Queue8_BuckyballAccelerator_Anon | 33 | 17 | 16 | 0 | 7 | 0 | 0 | 0 | +| (bankReadReqQ_q) | Queue8_BuckyballAccelerator_Anon | 6 | 6 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x21_38 | 27 | 11 | 16 | 0 | 0 | 0 | 0 | 0 | +| bankReadReqQ_q_1 | Queue8_BuckyballAccelerator_Anon_10 | 37 | 21 | 16 | 0 | 7 | 0 | 0 | 0 | +| (bankReadReqQ_q_1) | Queue8_BuckyballAccelerator_Anon_10 | 6 | 6 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x21 | 31 | 15 | 16 | 0 | 0 | 0 | 0 | 0 | +| frontend | Frontend_1 | 5269 | 5073 | 196 | 0 | 2205 | 2 | 0 | 0 | +| boot | BootRom | 10 | 10 | 0 | 0 | 6 | 0 | 0 | 0 | +| scheduler | GlobalScheduler | 5259 | 5063 | 196 | 0 | 2199 | 2 | 0 | 0 | +| (scheduler) | GlobalScheduler | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | +| completeQueue | Queue16_UInt4 | 34 | 30 | 4 | 0 | 9 | 0 | 0 | 0 | +| (completeQueue) | Queue16_UInt4 | 10 | 10 | 0 | 0 | 9 | 0 | 0 | 0 | +| ram_ext | ram_16x4 | 24 | 20 | 4 | 0 | 0 | 0 | 0 | 0 | +| rob | GlobalROB | 4660 | 4660 | 0 | 0 | 1668 | 2 | 0 | 0 | +| (rob) | GlobalROB | 1446 | 1446 | 0 | 0 | 1476 | 0 | 0 | 0 | +| bat | BankAliasTable | 1017 | 1017 | 0 | 0 | 176 | 0 | 0 | 0 | +| robOperands | robOperands | 1725 | 1725 | 0 | 0 | 0 | 2 | 0 | 0 | +| robOperands_ext | robOperands_ext | 1725 | 1725 | 0 | 0 | 0 | 2 | 0 | 0 | +| scoreboard | BankScoreboard | 472 | 472 | 0 | 0 | 16 | 0 | 0 | 0 | +| subRob | SubROB | 565 | 373 | 192 | 0 | 519 | 0 | 0 | 0 | +| (subRob) | SubROB | 370 | 370 | 0 | 0 | 273 | 0 | 0 | 0 | +| sram | sram | 195 | 3 | 192 | 0 | 246 | 0 | 0 | 0 | +| sram_ext | sram_ext | 195 | 3 | 192 | 0 | 246 | 0 | 0 | 0 | +| gpDomain | GpDomain | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | +| completeQ | Queue1_GlobalSchedComplete | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | +| memDomain | MemDomain | 4599 | 4507 | 92 | 0 | 1928 | 16 | 0 | 2 | +| backend | MemBackend | 2387 | 2387 | 0 | 0 | 472 | 16 | 0 | 0 | +| privateBackend | PrivateMemBackend | 2387 | 2387 | 0 | 0 | 472 | 16 | 0 | 0 | +| (privateBackend) | PrivateMemBackend | 203 | 203 | 0 | 0 | 243 | 0 | 0 | 0 | +| accPipes_0 | AccPipe | 350 | 350 | 0 | 0 | 67 | 0 | 0 | 0 | +| accPipes_1 | AccPipe_11 | 334 | 334 | 0 | 0 | 67 | 0 | 0 | 0 | +| accPipes_2 | AccPipe_12 | 59 | 59 | 0 | 0 | 3 | 0 | 0 | 0 | +| accPipes_3 | AccPipe_13 | 292 | 292 | 0 | 0 | 3 | 0 | 0 | 0 | +| accPipes_4 | AccPipe_14 | 333 | 333 | 0 | 0 | 3 | 0 | 0 | 0 | +| accPipes_5 | AccPipe_15 | 520 | 520 | 0 | 0 | 3 | 0 | 0 | 0 | +| accPipes_6 | AccPipe_16 | 296 | 296 | 0 | 0 | 67 | 0 | 0 | 0 | +| banks_0 | SramBank | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_0) | SramBank | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_36 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_37 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_1 | SramBank_17 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_1) | SramBank_17 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_34 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_35 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_2 | SramBank_18 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_2) | SramBank_18 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_32 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_33 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_3 | SramBank_19 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_3) | SramBank_19 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_30 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_31 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_4 | SramBank_20 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_4) | SramBank_20 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_28 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_29 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_5 | SramBank_21 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_5) | SramBank_21 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_26 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_27 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_6 | SramBank_22 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_6) | SramBank_22 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_24 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_25 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_7 | SramBank_23 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_7) | SramBank_23 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| frontend | MemFrontend | 2172 | 2080 | 92 | 0 | 1446 | 0 | 0 | 2 | +| (frontend) | MemFrontend | 594 | 594 | 0 | 0 | 2 | 0 | 0 | 0 | +| configer | MemConfiger | 135 | 135 | 0 | 0 | 63 | 0 | 0 | 0 | +| (configer) | MemConfiger | 96 | 96 | 0 | 0 | 29 | 0 | 0 | 0 | +| zeroLines | ZeroLineGenerator | 39 | 39 | 0 | 0 | 34 | 0 | 0 | 0 | +| groupQuery | MemGroupQueryArbiter | 10 | 10 | 0 | 0 | 12 | 0 | 0 | 0 | +| (groupQuery) | MemGroupQueryArbiter | 10 | 10 | 0 | 0 | 11 | 0 | 0 | 0 | +| arbiter | RRArbiter_2 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| memLoader | MemLoader | 240 | 240 | 0 | 0 | 242 | 0 | 0 | 0 | +| memRs | MemReservationStation | 164 | 72 | 92 | 0 | 5 | 0 | 0 | 0 | +| fifo | Queue4_MemReservationStation_Anon | 164 | 72 | 92 | 0 | 5 | 0 | 0 | 0 | +| (fifo) | Queue4_MemReservationStation_Anon | 3 | 3 | 0 | 0 | 5 | 0 | 0 | 0 | +| ram_ext | ram_4x158 | 161 | 69 | 92 | 0 | 0 | 0 | 0 | 0 | +| memStorer | MemStorer | 384 | 384 | 0 | 0 | 447 | 0 | 0 | 0 | +| reader | StreamReader | 548 | 548 | 0 | 0 | 304 | 0 | 0 | 2 | +| tlbCluster | BBTLBCluster | 151 | 151 | 0 | 0 | 261 | 0 | 0 | 0 | +| (tlbCluster) | BBTLBCluster | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| tlb | TLB | 151 | 151 | 0 | 0 | 259 | 0 | 0 | 0 | +| tlbArb | RRArbiter_1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| writer | StreamWriter | 5 | 5 | 0 | 0 | 110 | 0 | 0 | 0 | +| midend | MemMidend | 40 | 40 | 0 | 0 | 10 | 0 | 0 | 0 | +| barrierUnit | BarrierUnit | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | +| buffer | TLBuffer_a32d64s1k1z4u | 130 | 50 | 80 | 0 | 6 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a32d64s1k1z4u_7 | 94 | 42 | 52 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q) | Queue2_TLBundleD_a32d64s1k1z4u_7 | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x77 | 90 | 38 | 52 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a32d64s1k1z4u_8 | 36 | 8 | 28 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a32d64s1k1z4u_8 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x116_9 | 33 | 5 | 28 | 0 | 0 | 0 | 0 | 0 | +| buffer_1 | TLBuffer_a32d64s1k1z4u_1 | 147 | 75 | 72 | 0 | 6 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a32d64s1k1z4u | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a32d64s1k1z4u | 143 | 71 | 72 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a32d64s1k1z4u | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x116 | 140 | 68 | 72 | 0 | 0 | 0 | 0 | 0 | +| buffer_2 | TLBuffer_a32d64s2k1z4u | 241 | 109 | 132 | 0 | 6 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a32d64s2k1z4u | 57 | 5 | 52 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q) | Queue2_TLBundleD_a32d64s2k1z4u | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x78 | 54 | 2 | 52 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a32d64s2k1z4u | 184 | 104 | 80 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a32d64s2k1z4u | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x117 | 183 | 103 | 80 | 0 | 0 | 0 | 0 | 0 | +| cores_0 | RocketBB | 6198 | 6110 | 88 | 0 | 1898 | 0 | 0 | 13 | +| (cores_0) | RocketBB | 2423 | 2423 | 0 | 0 | 755 | 0 | 0 | 0 | +| csr | CSRFile | 1983 | 1983 | 0 | 0 | 870 | 0 | 0 | 0 | +| div | MulDiv | 1571 | 1571 | 0 | 0 | 214 | 0 | 0 | 13 | +| ibuf | IBuf | 102 | 102 | 0 | 0 | 59 | 0 | 0 | 0 | +| rf_ext | rf_31x64 | 119 | 31 | 88 | 0 | 0 | 0 | 0 | 0 | +| dcache | NonBlockingDCache | 3253 | 3161 | 92 | 0 | 3330 | 9 | 0 | 0 | +| (dcache) | NonBlockingDCache | 519 | 519 | 0 | 0 | 1150 | 0 | 0 | 0 | +| data | DataArray | 256 | 256 | 0 | 0 | 2 | 8 | 0 | 0 | +| (data) | DataArray | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| array_0_0 | array_0_0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_0_0_ext | array_0_0_ext_6 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_0_1 | array_0_1 | 64 | 64 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_0_0_ext | array_0_0_ext_5 | 64 | 64 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_2_0 | array_2_0 | 64 | 64 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_0_0_ext | array_0_0_ext_4 | 64 | 64 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_2_1 | array_2_1 | 128 | 128 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_0_0_ext | array_0_0_ext | 128 | 128 | 0 | 0 | 0 | 2 | 0 | 0 | +| dtlb | DTLB | 1277 | 1277 | 0 | 0 | 1692 | 0 | 0 | 0 | +| lfsr_prng | MaxPeriodFibonacciLFSR_3 | 13 | 13 | 0 | 0 | 16 | 0 | 0 | 0 | +| meta | L1MetadataArray | 129 | 37 | 92 | 0 | 98 | 0 | 0 | 0 | +| (meta) | L1MetadataArray | 3 | 3 | 0 | 0 | 6 | 0 | 0 | 0 | +| tag_array | tag_array | 126 | 34 | 92 | 0 | 92 | 0 | 0 | 0 | +| tag_array_ext | tag_array_ext | 126 | 34 | 92 | 0 | 92 | 0 | 0 | 0 | +| mshrs | MSHRFile | 693 | 693 | 0 | 0 | 292 | 1 | 0 | 0 | +| (mshrs) | MSHRFile | 2 | 2 | 0 | 0 | 26 | 0 | 0 | 0 | +| mmios_0 | IOMSHR | 297 | 297 | 0 | 0 | 180 | 0 | 0 | 0 | +| mshrs_0 | MSHR | 314 | 314 | 0 | 0 | 86 | 0 | 0 | 0 | +| (mshrs_0) | MSHR | 119 | 119 | 0 | 0 | 75 | 0 | 0 | 0 | +| grantackq | Queue1_TLBundleE_a32d128s1k1z4c | 78 | 78 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpq | Queue16_ReplayInternal | 117 | 117 | 0 | 0 | 9 | 0 | 0 | 0 | +| sdq_ext | sdq_17x64 | 80 | 80 | 0 | 0 | 0 | 1 | 0 | 0 | +| prober | ProbeUnit | 81 | 81 | 0 | 0 | 40 | 0 | 0 | 0 | +| wb | WritebackUnit | 285 | 285 | 0 | 0 | 40 | 0 | 0 | 0 | +| dcacheArb | HellaCacheArbiter | 15 | 15 | 0 | 0 | 4 | 0 | 0 | 0 | +| fpuOpts_0 | FPU | 8025 | 7761 | 264 | 0 | 2618 | 0 | 0 | 9 | +| (fpuOpts_0) | FPU | 28 | 28 | 0 | 0 | 193 | 0 | 0 | 0 | +| divSqrt | DivSqrtRecFM_small_e5_s11 | 152 | 152 | 0 | 0 | 60 | 0 | 0 | 0 | +| divSqrtRecFNToRaw | DivSqrtRecFMToRaw_small_e5_s11 | 152 | 152 | 0 | 0 | 60 | 0 | 0 | 0 | +| divSqrtRawFN | DivSqrtRawFN_small_e5_s11 | 152 | 152 | 0 | 0 | 60 | 0 | 0 | 0 | +| roundRawFNToRecFN | RoundRawFNToRecFN_e5_s11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie5_is13_oe5_os11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| divSqrt_1 | DivSqrtRecFM_small_e8_s24 | 345 | 345 | 0 | 0 | 103 | 0 | 0 | 0 | +| divSqrtRecFNToRaw | DivSqrtRecFMToRaw_small_e8_s24 | 340 | 340 | 0 | 0 | 103 | 0 | 0 | 0 | +| divSqrtRawFN | DivSqrtRawFN_small_e8_s24 | 340 | 340 | 0 | 0 | 103 | 0 | 0 | 0 | +| roundRawFNToRecFN | RoundRawFNToRecFN_e8_s24 | 5 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie8_is26_oe8_os24 | 5 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | +| divSqrt_2 | DivSqrtRecFM_small_e11_s53 | 858 | 858 | 0 | 0 | 195 | 0 | 0 | 0 | +| divSqrtRecFNToRaw | DivSqrtRecFMToRaw_small_e11_s53 | 849 | 849 | 0 | 0 | 195 | 0 | 0 | 0 | +| divSqrtRawFN | DivSqrtRawFN_small_e11_s53 | 849 | 849 | 0 | 0 | 195 | 0 | 0 | 0 | +| roundRawFNToRecFN | RoundRawFNToRecFN_e11_s53 | 9 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie11_is55_oe11_os53 | 9 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | +| fpiu | FPToInt | 1044 | 1044 | 0 | 0 | 140 | 0 | 0 | 0 | +| (fpiu) | FPToInt | 993 | 993 | 0 | 0 | 140 | 0 | 0 | 0 | +| dcmp | CompareRecFN | 51 | 51 | 0 | 0 | 0 | 0 | 0 | 0 | +| fpmu | FPToFP | 436 | 436 | 0 | 0 | 208 | 0 | 0 | 0 | +| (fpmu) | FPToFP | 93 | 93 | 0 | 0 | 208 | 0 | 0 | 0 | +| narrower | RecFNToRecFN | 126 | 126 | 0 | 0 | 0 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie11_is53_oe5_os11 | 126 | 126 | 0 | 0 | 0 | 0 | 0 | 0 | +| narrower_1 | RecFNToRecFN_1 | 217 | 217 | 0 | 0 | 0 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie11_is53_oe8_os24 | 217 | 217 | 0 | 0 | 0 | 0 | 0 | 0 | +| ifpu | IntToFP | 1581 | 1581 | 0 | 0 | 695 | 0 | 0 | 0 | +| (ifpu) | IntToFP | 61 | 61 | 0 | 0 | 140 | 0 | 0 | 0 | +| i2f_0 | PipelinedINToRecFN | 799 | 799 | 0 | 0 | 281 | 0 | 0 | 0 | +| (i2f_0) | PipelinedINToRecFN | 772 | 772 | 0 | 0 | 281 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie7_is64_oe5_os11 | 27 | 27 | 0 | 0 | 0 | 0 | 0 | 0 | +| i2f_1 | PipelinedINToRecFN_1 | 361 | 361 | 0 | 0 | 137 | 0 | 0 | 0 | +| (i2f_1) | PipelinedINToRecFN_1 | 333 | 333 | 0 | 0 | 137 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie7_is64_oe8_os24 | 28 | 28 | 0 | 0 | 0 | 0 | 0 | 0 | +| i2f_2 | PipelinedINToRecFN_2 | 360 | 360 | 0 | 0 | 137 | 0 | 0 | 0 | +| (i2f_2) | PipelinedINToRecFN_2 | 319 | 319 | 0 | 0 | 137 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie7_is64_oe11_os53 | 41 | 41 | 0 | 0 | 0 | 0 | 0 | 0 | +| regfile_ext | regfile_32x65 | 1108 | 844 | 264 | 0 | 32 | 0 | 0 | 0 | +| sharedFma | FPUSharedFMAPipe | 2473 | 2473 | 0 | 0 | 992 | 0 | 0 | 9 | +| (sharedFma) | FPUSharedFMAPipe | 15 | 15 | 0 | 0 | 238 | 0 | 0 | 0 | +| fma | SharedMulAddRecFNPipe | 2458 | 2458 | 0 | 0 | 754 | 0 | 0 | 9 | +| frontend | Frontend | 2154 | 2112 | 42 | 0 | 2221 | 0 | 8 | 0 | +| (frontend) | Frontend | 3 | 3 | 0 | 0 | 90 | 0 | 0 | 0 | +| fq | ShiftQueue | 775 | 775 | 0 | 0 | 375 | 0 | 0 | 0 | +| icache | ICache | 550 | 508 | 42 | 0 | 294 | 0 | 8 | 0 | +| (icache) | ICache | 266 | 266 | 0 | 0 | 236 | 0 | 0 | 0 | +| bbtile_icache_data_arrays_0 | bbtile_icache_data_arrays_0 | 2 | 2 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_0_ext | bbtile_icache_data_arrays_0_ext_2 | 2 | 2 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_1 | bbtile_icache_data_arrays_1 | 43 | 43 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_0_ext | bbtile_icache_data_arrays_0_ext_1 | 43 | 43 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_2 | bbtile_icache_data_arrays_2 | 2 | 2 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_0_ext | bbtile_icache_data_arrays_0_ext_0 | 2 | 2 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_3 | bbtile_icache_data_arrays_3 | 45 | 45 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_0_ext | bbtile_icache_data_arrays_0_ext | 45 | 45 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_tag_array | bbtile_icache_tag_array | 63 | 21 | 42 | 0 | 42 | 0 | 0 | 0 | +| bbtile_icache_tag_array_ext | bbtile_icache_tag_array_ext | 63 | 21 | 42 | 0 | 42 | 0 | 0 | 0 | +| repl_way_v0_prng | MaxPeriodFibonacciLFSR | 129 | 129 | 0 | 0 | 16 | 0 | 0 | 0 | +| tlb | ITLB | 826 | 826 | 0 | 0 | 1462 | 0 | 0 | 0 | +| ptw | PTW | 786 | 786 | 0 | 0 | 567 | 0 | 0 | 0 | +| roccMemIF | SimpleHellaCacheIF | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| (roccMemIF) | SimpleHellaCacheIF | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| replayq | SimpleHellaCacheIFReplayQueue | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 | +| (replayq) | SimpleHellaCacheIFReplayQueue | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| nackq | Queue3_UInt2 | 8 | 8 | 0 | 0 | 5 | 0 | 0 | 0 | +| tlMasterXbar | TLXbar_MasterXbar_BBTile_i2_o1_a32d128s2k1z4c | 44 | 44 | 0 | 0 | 11 | 0 | 0 | 0 | +| widget_3 | TLWidthWidget8_4 | 85 | 85 | 0 | 0 | 160 | 0 | 0 | 0 | +| (widget_3) | TLWidthWidget8_4 | 1 | 1 | 0 | 0 | 81 | 0 | 0 | 0 | +| repeated_repeater | Repeater_TLBundleD_a32d128s2k1z4u | 84 | 84 | 0 | 0 | 79 | 0 | 0 | 0 | +| xbar | TLXbar_i2_o1_a32d64s2k1z4u | 65 | 65 | 0 | 0 | 13 | 0 | 0 | 0 | +| load_bridge | loader_axi | 41 | 41 | 0 | 0 | 306 | 0 | 0 | 0 | +| loader | ddr_uart_loader | 441 | 377 | 64 | 0 | 159 | 0 | 0 | 0 | +| normalizer | axi_fullwidth | 334 | 334 | 0 | 0 | 376 | 0 | 0 | 0 | +| peripherals | axi_scu | 152 | 104 | 48 | 0 | 162 | 0 | 0 | 0 | +| receiver | uart_rx | 39 | 39 | 0 | 0 | 31 | 0 | 0 | 0 | +| transmitter | uart_tx | 15 | 15 | 0 | 0 | 18 | 0 | 0 | 0 | ++----------------------------------------------------------------------------------------+-----------------------------------------------------------------+------------+------------+---------+------+-------+--------+--------+------------+ + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/synth-timing.rpt b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/synth-timing.rpt new file mode 100644 index 0000000..879417a --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/synth-timing.rpt @@ -0,0 +1,4930 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Tue Oct 13 01:26:43 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_timing_summary -delay_type min_max -file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/synth-timing.rpt +| Design : toy_a7_top +| Device : 7a100t-csg324 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +| Design State : Synthesized +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : No + Borrow Time for Max Delay Exceptions : Yes + Merge Timing Exceptions : Yes + Inter-SLR Compensation : Conservative + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + +------------------------------------------------------------------------------------------------ +| Report Methodology +| ------------------ +------------------------------------------------------------------------------------------------ + +No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations. + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock (0) +2. checking constant_clock (0) +3. checking pulse_width_clock (0) +4. checking unconstrained_internal_endpoints (0) +5. checking no_input_delay (3) +6. checking no_output_delay (6) +7. checking multiple_clock (0) +8. checking generated_clocks (0) +9. checking loops (0) +10. checking partial_input_delay (0) +11. checking partial_output_delay (0) +12. checking latch_loops (0) + +1. checking no_clock (0) +------------------------ + There are 0 register/latch pins with no clock. + + +2. checking constant_clock (0) +------------------------------ + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock (0) +--------------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints (0) +------------------------------------------------ + There are 0 pins that are not constrained for maximum delay. + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay (3) +------------------------------ + There is 1 input port with no input delay specified. (HIGH) + + There are 2 input ports with no input delay but user has a false path constraint. (MEDIUM) + + +6. checking no_output_delay (6) +------------------------------- + There are 0 ports with no output delay specified. + + There are 6 ports with no output delay but user has a false path constraint (MEDIUM) + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock (0) +------------------------------ + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks (0) +-------------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops (0) +--------------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay (0) +------------------------------------ + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay (0) +------------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops (0) +---------------------------- + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + 1.277 0.000 0 108329 -1.631 -26.741 55 108287 0.187 0.000 0 42005 + + +Timing constraints are not met. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + +Clock Waveform(ns) Period(ns) Frequency(MHz) +----- ------------ ---------- -------------- +board_clk {0.000 5.000} 10.000 100.000 + core_raw {0.000 20.000} 40.000 25.000 + fb {0.000 5.000} 10.000 100.000 + ref_raw {0.000 2.500} 5.000 200.000 + sys_raw {0.000 3.000} 6.000 166.667 + freq_refclk {0.000 0.750} 1.500 666.667 + u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk {0.000 1.500} 3.000 333.333 + iserdes_clkdiv {0.000 6.000} 12.000 83.333 + u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk {0.000 1.500} 3.000 333.333 + iserdes_clkdiv_1 {0.000 6.000} 12.000 83.333 + mem_refclk {0.000 1.500} 3.000 333.333 + oserdes_clk {0.000 1.500} 3.000 333.333 + oserdes_clkdiv {0.000 6.000} 12.000 83.333 + oserdes_clk_1 {0.000 1.500} 3.000 333.333 + oserdes_clkdiv_1 {0.000 6.000} 12.000 83.333 + oserdes_clk_2 {0.000 1.500} 3.000 333.333 + oserdes_clkdiv_2 {0.000 3.000} 6.000 166.667 + oserdes_clk_3 {0.000 1.500} 3.000 333.333 + oserdes_clkdiv_3 {0.000 3.000} 6.000 166.667 + pll_clk3_out {0.000 6.000} 12.000 83.333 + clk_div2_bufg_in {0.000 3.000} 6.000 166.667 + clk_pll_i {0.000 6.000} 12.000 83.333 + mmcm_ps_clk_bufg_in {0.000 12.000} 24.000 41.667 + pll_clkfbout {0.000 3.000} 6.000 166.667 + sync_pulse {1.312 4.313} 48.000 20.833 + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- +board_clk 3.000 0.000 0 1 + core_raw 14.939 0.000 0 92516 0.045 0.000 0 92516 18.750 0.000 0 35544 + fb 7.845 0.000 0 3 + ref_raw 2.263 0.000 0 130 0.045 0.000 0 130 0.264 0.000 0 69 + sys_raw 1.500 0.000 0 3 + freq_refclk 0.187 0.000 0 8 + u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk 1.333 0.000 0 16 + iserdes_clkdiv 9.972 0.000 0 33 0.071 0.000 0 33 3.850 0.000 0 9 + u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk 1.333 0.000 0 16 + iserdes_clkdiv_1 9.955 0.000 0 33 0.071 0.000 0 33 3.850 0.000 0 9 + mem_refclk 1.810 0.000 0 1 0.375 0.000 0 1 0.875 0.000 0 8 + oserdes_clk 1.333 0.000 0 12 + oserdes_clkdiv 10.094 0.000 0 44 0.113 0.000 0 44 3.850 0.000 0 12 + oserdes_clk_1 1.333 0.000 0 12 + oserdes_clkdiv_1 10.595 0.000 0 48 0.119 0.000 0 48 3.850 0.000 0 13 + oserdes_clk_2 1.442 0.000 0 4 0.440 0.000 0 4 1.333 0.000 0 12 + oserdes_clkdiv_2 4.602 0.000 0 36 0.116 0.000 0 36 0.850 0.000 0 11 + oserdes_clk_3 1.458 0.000 0 4 0.432 0.000 0 4 1.333 0.000 0 12 + oserdes_clkdiv_3 4.618 0.000 0 36 0.109 0.000 0 36 0.850 0.000 0 11 + pll_clk3_out 3.000 0.000 0 3 + clk_div2_bufg_in 4.741 0.000 0 12 0.152 0.000 0 12 2.500 0.000 0 15 + clk_pll_i 5.851 0.000 0 15062 0.034 0.000 0 15062 3.850 0.000 0 6181 + mmcm_ps_clk_bufg_in 22.715 0.000 0 12 0.152 0.000 0 12 11.500 0.000 0 15 + pll_clkfbout 4.751 0.000 0 2 + sync_pulse 1.750 0.000 0 8 + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- +clk_pll_i core_raw 10.968 0.000 0 20 +clk_pll_i ref_raw 18.960 0.000 0 1 +clk_pll_i u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk 12.367 0.000 0 8 44.683 0.000 0 8 +clk_pll_i u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk 12.374 0.000 0 8 44.679 0.000 0 8 +sync_pulse mem_refclk 1.277 0.000 0 1 0.910 0.000 0 1 +oserdes_clk oserdes_clkdiv 2.105 0.000 0 12 -0.247 -1.473 11 12 +oserdes_clk_1 oserdes_clkdiv_1 2.105 0.000 0 13 -0.268 -2.486 12 13 +oserdes_clk_2 oserdes_clkdiv_2 2.105 0.000 0 15 -0.274 -2.156 10 15 +oserdes_clk_3 oserdes_clkdiv_3 2.105 0.000 0 15 -0.197 -1.058 10 15 +core_raw clk_pll_i 38.968 0.000 0 20 +ref_raw clk_pll_i 19.759 0.000 0 12 -1.631 -19.568 12 12 + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- +**async_default** clk_pll_i clk_pll_i 9.663 0.000 0 113 0.295 0.000 0 113 +**async_default** core_raw core_raw 34.624 0.000 0 119 0.295 0.000 0 119 +**default** clk_pll_i 3.113 0.000 0 1 + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + +--------------------------------------------------------------------------------------------------- +From Clock: board_clk + To Clock: board_clk + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 3.000ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: board_clk +Waveform(ns): { 0.000 5.000 } +Period(ns): 10.000 +Sources: { CLK100MHZ } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a MMCME2_ADV/CLKIN1 n/a 1.249 10.000 8.751 clock_mmcm/CLKIN1 +Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 10.000 90.000 clock_mmcm/CLKIN1 +Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 clock_mmcm/CLKIN1 +High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 clock_mmcm/CLKIN1 + + + +--------------------------------------------------------------------------------------------------- +From Clock: core_raw + To Clock: core_raw + +Setup : 0 Failing Endpoints, Worst Slack 14.939ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.045ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 18.750ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 14.939ns (required time - arrival time) + Source: platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5/CLK + (rising edge-triggered cell DSP48E1 clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/frontend/scheduler/subRob/sram/sram_ext/lanes[0].ram_reg_0_7_234_239/RAMA_D1/I + (rising edge-triggered cell RAMD32 clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: core_raw + Path Type: Setup (Max at Slow Process Corner) + Requirement: 40.000ns (core_raw rise@40.000ns - core_raw rise@0.000ns) + Data Path Delay: 24.566ns (logic 19.514ns (79.434%) route 5.052ns (20.566%)) + Logic Levels: 12 (CARRY4=4 DSP48E1=5 LUT2=1 LUT4=1 LUT6=1) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.238ns = ( 37.762 - 40.000 ) + Source Clock Delay (SCD): -1.562ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.091ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.111 -3.045 r clock_mmcm/CLKOUT0 + net (fo=1, unplaced) 0.803 -2.242 core_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r core_buffer/O + net (fo=35560, unplaced) 0.584 -1.562 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/clk + DSP48E1 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5/CLK + ------------------------------------------------------------------- ------------------- + DSP48E1 (Prop_dsp48e1_CLK_P[16]) + 4.009 2.447 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5/P[16] + net (fo=1, unplaced) 0.803 3.250 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5_n_89 + DSP48E1 (Prop_dsp48e1_A[16]_PCOUT[47]) + 4.036 7.286 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0/PCOUT[47] + net (fo=1, unplaced) 0.000 7.286 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0_n_106 + DSP48E1 (Prop_dsp48e1_PCIN[47]_P[19]) + 1.518 8.804 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1/P[19] + net (fo=1, unplaced) 0.803 9.607 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1_n_86 + DSP48E1 (Prop_dsp48e1_C[36]_P[16]) + 1.820 11.427 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2/P[16] + net (fo=1, unplaced) 0.803 12.229 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2_n_89 + DSP48E1 (Prop_dsp48e1_A[16]_PCOUT[47]) + 4.036 16.265 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1/PCOUT[47] + net (fo=1, unplaced) 0.000 16.265 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1_n_106 + DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) + 1.518 17.783 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0/P[0] + net (fo=1, unplaced) 0.803 18.586 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0_n_105 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.659 19.245 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr_carry__3_i_5/CO[3] + net (fo=1, unplaced) 0.000 19.245 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr_carry__3_i_5_n_0 + CARRY4 (Prop_carry4_CI_O[3]) + 0.331 19.576 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr_carry__4_i_5/O[3] + net (fo=1, unplaced) 0.448 20.024 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr0[23] + LUT2 (Prop_lut2_I1_O) 0.307 20.331 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr_carry__5_i_4/O + net (fo=1, unplaced) 0.000 20.331 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr_carry__5_i_4_n_0 + CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 20.844 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr_carry__5/CO[3] + net (fo=1, unplaced) 0.000 20.844 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr_carry__5_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.337 21.181 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr_carry__6/O[1] + net (fo=1, unplaced) 0.611 21.792 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_addrGen_io_outputAddr[30] + LUT4 (Prop_lut4_I1_O) 0.306 22.098 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/lanes[0].ram_reg_0_7_234_239_i_8/O + net (fo=1, unplaced) 0.449 22.547 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_convUnroller_io_cmd_bits_slots_0_bits_dram_addr[26] + LUT6 (Prop_lut6_I5_O) 0.124 22.671 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/lanes[0].ram_reg_0_7_234_239_i_1/O + net (fo=1, unplaced) 0.333 23.004 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/frontend/scheduler/subRob/sram/sram_ext/lanes[0].ram_reg_0_7_234_239/DIA1 + RAMD32 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/frontend/scheduler/subRob/sram/sram_ext/lanes[0].ram_reg_0_7_234_239/RAMA_D1/I + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 40.000 40.000 r + E3 0.000 40.000 r CLK100MHZ (IN) + net (fo=0) 0.000 40.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r input_clock/O + net (fo=1, unplaced) 0.439 41.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.381 36.470 r clock_mmcm/CLKOUT0 + net (fo=1, unplaced) 0.763 37.232 core_raw + BUFG (Prop_bufg_I_O) 0.091 37.323 r core_buffer/O + net (fo=35560, unplaced) 0.439 37.762 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/frontend/scheduler/subRob/sram/sram_ext/lanes[0].ram_reg_0_7_234_239/WCLK + RAMD32 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/frontend/scheduler/subRob/sram/sram_ext/lanes[0].ram_reg_0_7_234_239/RAMA_D1/CLK + clock pessimism 0.531 38.293 + clock uncertainty -0.091 38.202 + RAMD32 (Setup_ramd32_CLK_I) + -0.258 37.944 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/frontend/scheduler/subRob/sram/sram_ext/lanes[0].ram_reg_0_7_234_239/RAMA_D1 + ------------------------------------------------------------------- + required time 37.944 + arrival time -23.004 + ------------------------------------------------------------------- + slack 14.939 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.045ns (arrival time - required time) + Source: btn_meta_reg/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: btn_sync_reg/D + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: core_raw + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (core_raw rise@0.000ns - core_raw rise@0.000ns) + Data Path Delay: 0.228ns (logic 0.147ns (64.493%) route 0.081ns (35.507%)) + Logic Levels: 0 + Clock Path Skew: 0.145ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -1.070ns + Source Clock Delay (SCD): -0.935ns + Clock Pessimism Removal (CPR): -0.280ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.777 -1.414 r clock_mmcm/CLKOUT0 + net (fo=1, unplaced) 0.338 -1.075 core_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r core_buffer/O + net (fo=35560, unplaced) 0.114 -0.935 clk + FDRE r btn_meta_reg/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.147 -0.788 r btn_meta_reg/Q + net (fo=1, unplaced) 0.081 -0.707 btn_meta + FDRE r btn_sync_reg/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.411 -1.715 r clock_mmcm/CLKOUT0 + net (fo=1, unplaced) 0.356 -1.358 core_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r core_buffer/O + net (fo=35560, unplaced) 0.259 -1.070 clk + FDRE r btn_sync_reg/C + clock pessimism 0.280 -0.790 + FDRE (Hold_fdre_C_D) 0.038 -0.752 btn_sync_reg + ------------------------------------------------------------------- + required time 0.752 + arrival time -0.707 + ------------------------------------------------------------------- + slack 0.045 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: core_raw +Waveform(ns): { 0.000 20.000 } +Period(ns): 40.000 +Sources: { clock_mmcm/CLKOUT0 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a DSP48E1/CLK n/a 3.884 40.000 36.116 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg/CLK +Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 40.000 173.360 clock_mmcm/CLKOUT0 +Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMA/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMA/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: fb + To Clock: fb + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 7.845ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: fb +Waveform(ns): { 0.000 5.000 } +Period(ns): 10.000 +Sources: { clock_mmcm/CLKFBOUT } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFG/I n/a 2.155 10.000 7.845 fb_buffer/I +Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 10.000 90.000 clock_mmcm/CLKFBIN + + + +--------------------------------------------------------------------------------------------------- +From Clock: ref_raw + To Clock: ref_raw + +Setup : 0 Failing Endpoints, Worst Slack 2.263ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.045ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 0.264ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 2.263ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r2_reg/C + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.sample_timer_reg[0]/R + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: ref_raw + Path Type: Setup (Max at Slow Process Corner) + Requirement: 5.000ns (ref_raw rise@5.000ns - ref_raw rise@0.000ns) + Data Path Delay: 1.968ns (logic 0.773ns (39.278%) route 1.195ns (60.722%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.238ns = ( 2.762 - 5.000 ) + Source Clock Delay (SCD): -1.562ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -5.111 -3.045 r clock_mmcm/CLKOUT2 + net (fo=1, unplaced) 0.803 -2.242 ref_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r ref_buffer/O + net (fo=67, unplaced) 0.584 -1.562 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/clk_ref_i + FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r2_reg/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.478 -1.084 r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r2_reg/Q + net (fo=32, unplaced) 0.541 -0.543 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r2 + LUT2 (Prop_lut2_I0_O) 0.295 -0.248 r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.sample_timer[10]_i_1/O + net (fo=11, unplaced) 0.654 0.406 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.sample_timer0__20 + FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.sample_timer_reg[0]/R + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 5.000 5.000 r + E3 0.000 5.000 r CLK100MHZ (IN) + net (fo=0) 0.000 5.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 6.411 r input_clock/O + net (fo=1, unplaced) 0.439 6.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -5.381 1.470 r clock_mmcm/CLKOUT2 + net (fo=1, unplaced) 0.763 2.232 ref_raw + BUFG (Prop_bufg_I_O) 0.091 2.323 r ref_buffer/O + net (fo=67, unplaced) 0.439 2.762 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/clk_ref_i + FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.sample_timer_reg[0]/C + clock pessimism 0.531 3.293 + clock uncertainty -0.067 3.226 + FDRE (Setup_fdre_C_R) -0.557 2.669 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.sample_timer_reg[0] + ------------------------------------------------------------------- + required time 2.669 + arrival time -0.406 + ------------------------------------------------------------------- + slack 2.263 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.045ns (arrival time - required time) + Source: btn_ref_meta_reg/C + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: btn_ref_sync_reg/D + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: ref_raw + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (ref_raw rise@0.000ns - ref_raw rise@0.000ns) + Data Path Delay: 0.228ns (logic 0.147ns (64.493%) route 0.081ns (35.507%)) + Logic Levels: 0 + Clock Path Skew: 0.145ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -1.070ns + Source Clock Delay (SCD): -0.935ns + Clock Pessimism Removal (CPR): -0.280ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -1.777 -1.414 r clock_mmcm/CLKOUT2 + net (fo=1, unplaced) 0.338 -1.075 ref_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r ref_buffer/O + net (fo=67, unplaced) 0.114 -0.935 ref_clk + FDRE r btn_ref_meta_reg/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.147 -0.788 r btn_ref_meta_reg/Q + net (fo=1, unplaced) 0.081 -0.707 btn_ref_meta + FDRE r btn_ref_sync_reg/D + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -2.411 -1.715 r clock_mmcm/CLKOUT2 + net (fo=1, unplaced) 0.356 -1.358 ref_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r ref_buffer/O + net (fo=67, unplaced) 0.259 -1.070 ref_clk + FDRE r btn_ref_sync_reg/C + clock pessimism 0.280 -0.790 + FDRE (Hold_fdre_C_D) 0.038 -0.752 btn_ref_sync_reg + ------------------------------------------------------------------- + required time 0.752 + arrival time -0.707 + ------------------------------------------------------------------- + slack 0.045 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: ref_raw +Waveform(ns): { 0.000 2.500 } +Period(ns): 5.000 +Sources: { clock_mmcm/CLKOUT2 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a XADC/DCLK n/a 4.000 5.000 1.000 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.XADC_inst/DCLK +Max Period n/a IDELAYCTRL/REFCLK n/a 5.264 5.000 0.264 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/u_idelayctrl_200/REFCLK +Low Pulse Width Slow FDRE/C n/a 0.500 2.500 2.000 btn_ref_meta_reg/C +High Pulse Width Slow FDRE/C n/a 0.500 2.500 2.000 btn_ref_meta_reg/C + + + +--------------------------------------------------------------------------------------------------- +From Clock: sys_raw + To Clock: sys_raw + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.500ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: sys_raw +Waveform(ns): { 0.000 3.000 } +Period(ns): 6.000 +Sources: { clock_mmcm/CLKOUT1 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFG/I n/a 2.155 6.000 3.845 sys_buffer/I +Max Period n/a PLLE2_ADV/CLKIN1 n/a 52.633 6.000 46.633 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 +Low Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 1.500 3.000 1.500 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 +High Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 1.500 3.000 1.500 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 + + + +--------------------------------------------------------------------------------------------------- +From Clock: freq_refclk + To Clock: freq_refclk + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 0.187ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: freq_refclk +Waveform(ns): { 0.000 0.750 } +Period(ns): 1.500 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a PHASER_OUT_PHY/FREQREFCLK n/a 1.250 1.500 0.250 PHASER_OUT_PHY_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/FREQREFCLK +Max Period n/a PHASER_OUT_PHY/FREQREFCLK n/a 2.500 1.500 1.000 PHASER_OUT_PHY_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/FREQREFCLK +Low Pulse Width Slow PHASER_REF/CLKIN n/a 0.562 0.750 0.188 PHASER_REF_X1Y1 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i/CLKIN +High Pulse Width Slow PHASER_OUT_PHY/FREQREFCLK n/a 0.563 0.750 0.187 PHASER_OUT_PHY_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/FREQREFCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk + To Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a ISERDESE2/CLK n/a 1.667 3.000 1.333 ILOGIC_X1Y76 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: iserdes_clkdiv + To Clock: iserdes_clkdiv + +Setup : 0 Failing Endpoints, Worst Slack 9.972ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.071ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 3.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 9.972ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLKDIVP + (rising edge-triggered cell ISERDESE2 clocked by iserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/D1[3] + (rising edge-triggered cell IN_FIFO clocked by iserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: iserdes_clkdiv + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (iserdes_clkdiv rise@12.000ns - iserdes_clkdiv rise@0.000ns) + Data Path Delay: 0.956ns (logic 0.425ns (44.456%) route 0.531ns (55.544%)) + Logic Levels: 0 + Clock Path Skew: -0.450ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.533ns = ( 12.533 - 12.000 ) + Source Clock Delay (SCD): 1.637ns + Clock Pessimism Removal (CPR): 0.654ns + Clock Uncertainty: 0.051ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.073ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock iserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, estimated) 0.607 -0.648 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.662 1.014 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.173 1.187 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, estimated) 0.450 1.637 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/iserdes_clkdiv + ILOGIC_X1Y76 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLKDIVP + ------------------------------------------------------------------- ------------------- + ILOGIC_X1Y76 ISERDESE2 (Prop_iserdese2_CLKDIVP_Q1) + 0.425 2.062 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/Q1 + net (fo=1, estimated) 0.531 2.593 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/if_d1[3] + IN_FIFO_X1Y6 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/D1[3] + ------------------------------------------------------------------- ------------------- + + (clock iserdes_clkdiv rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, unplaced) 0.439 13.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 8.470 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 9.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 9.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 10.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.083 10.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, estimated) 0.577 10.746 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.624 12.370 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.163 12.533 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, estimated) 0.000 12.533 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clkdiv + IN_FIFO_X1Y6 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK + clock pessimism 0.654 13.187 + clock uncertainty -0.051 13.136 + IN_FIFO_X1Y6 IN_FIFO (Setup_in_fifo_WRCLK_D1[3]) + -0.571 12.565 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo + ------------------------------------------------------------------- + required time 12.565 + arrival time -2.593 + ------------------------------------------------------------------- + slack 9.972 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.071ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV + (rising edge-triggered cell PHASER_IN_PHY clocked by iserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WREN + (rising edge-triggered cell IN_FIFO clocked by iserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: iserdes_clkdiv + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (iserdes_clkdiv rise@0.000ns - iserdes_clkdiv rise@0.000ns) + Data Path Delay: 0.058ns (logic 0.058ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.826ns + Source Clock Delay (SCD): 1.042ns + Clock Pessimism Removal (CPR): -0.216ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock iserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, estimated) 0.256 -0.405 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.357 0.952 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.090 1.042 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV + ------------------------------------------------------------------- ------------------- + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_ICLKDIV_WRENABLE) + 0.058 1.100 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/WRENABLE + net (fo=1, estimated) 0.000 1.100 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ififo_wr_enable + IN_FIFO_X1Y6 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WREN + ------------------------------------------------------------------- ------------------- + + (clock iserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, estimated) 0.269 -0.651 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.381 0.730 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.096 0.826 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, estimated) 0.000 0.826 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clkdiv + IN_FIFO_X1Y6 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK + clock pessimism 0.216 1.042 + IN_FIFO_X1Y6 IN_FIFO (Hold_in_fifo_WRCLK_WREN) + -0.013 1.029 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo + ------------------------------------------------------------------- + required time -1.029 + arrival time 1.100 + ------------------------------------------------------------------- + slack 0.071 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: iserdes_clkdiv +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a IN_FIFO/WRCLK n/a 5.000 12.000 7.000 IN_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK +Low Pulse Width Slow IN_FIFO/WRCLK n/a 2.150 6.000 3.850 IN_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK +High Pulse Width Slow IN_FIFO/WRCLK n/a 2.150 6.000 3.850 IN_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk + To Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a ISERDESE2/CLK n/a 1.667 3.000 1.333 ILOGIC_X1Y88 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: iserdes_clkdiv_1 + To Clock: iserdes_clkdiv_1 + +Setup : 0 Failing Endpoints, Worst Slack 9.955ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.071ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 3.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 9.955ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLKDIVP + (rising edge-triggered cell ISERDESE2 clocked by iserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/D1[3] + (rising edge-triggered cell IN_FIFO clocked by iserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: iserdes_clkdiv_1 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (iserdes_clkdiv_1 rise@12.000ns - iserdes_clkdiv_1 rise@0.000ns) + Data Path Delay: 0.956ns (logic 0.425ns (44.456%) route 0.531ns (55.544%)) + Logic Levels: 0 + Clock Path Skew: -0.467ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.523ns = ( 12.523 - 12.000 ) + Source Clock Delay (SCD): 1.644ns + Clock Pessimism Removal (CPR): 0.654ns + Clock Uncertainty: 0.051ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.073ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock iserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, estimated) 0.597 -0.658 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.662 1.004 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.173 1.177 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, estimated) 0.467 1.644 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/iserdes_clkdiv + ILOGIC_X1Y88 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLKDIVP + ------------------------------------------------------------------- ------------------- + ILOGIC_X1Y88 ISERDESE2 (Prop_iserdese2_CLKDIVP_Q1) + 0.425 2.069 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/Q1 + net (fo=1, estimated) 0.531 2.600 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/if_d1[3] + IN_FIFO_X1Y7 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/D1[3] + ------------------------------------------------------------------- ------------------- + + (clock iserdes_clkdiv_1 rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, unplaced) 0.439 13.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 8.470 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 9.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 9.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 10.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.083 10.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, estimated) 0.567 10.736 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.624 12.360 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.163 12.523 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, estimated) 0.000 12.523 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clkdiv + IN_FIFO_X1Y7 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK + clock pessimism 0.654 13.177 + clock uncertainty -0.051 13.126 + IN_FIFO_X1Y7 IN_FIFO (Setup_in_fifo_WRCLK_D1[3]) + -0.571 12.555 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo + ------------------------------------------------------------------- + required time 12.555 + arrival time -2.600 + ------------------------------------------------------------------- + slack 9.955 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.071ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV + (rising edge-triggered cell PHASER_IN_PHY clocked by iserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WREN + (rising edge-triggered cell IN_FIFO clocked by iserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: iserdes_clkdiv_1 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (iserdes_clkdiv_1 rise@0.000ns - iserdes_clkdiv_1 rise@0.000ns) + Data Path Delay: 0.058ns (logic 0.058ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.821ns + Source Clock Delay (SCD): 1.037ns + Clock Pessimism Removal (CPR): -0.216ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock iserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, estimated) 0.252 -0.409 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.357 0.947 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.090 1.037 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV + ------------------------------------------------------------------- ------------------- + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_ICLKDIV_WRENABLE) + 0.058 1.095 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/WRENABLE + net (fo=1, estimated) 0.000 1.095 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ififo_wr_enable + IN_FIFO_X1Y7 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WREN + ------------------------------------------------------------------- ------------------- + + (clock iserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, estimated) 0.265 -0.655 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.381 0.725 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.096 0.821 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, estimated) 0.000 0.821 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clkdiv + IN_FIFO_X1Y7 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK + clock pessimism 0.216 1.037 + IN_FIFO_X1Y7 IN_FIFO (Hold_in_fifo_WRCLK_WREN) + -0.013 1.024 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo + ------------------------------------------------------------------- + required time -1.024 + arrival time 1.095 + ------------------------------------------------------------------- + slack 0.071 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: iserdes_clkdiv_1 +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a IN_FIFO/WRCLK n/a 5.000 12.000 7.000 IN_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK +Low Pulse Width Slow IN_FIFO/WRCLK n/a 2.150 6.000 3.850 IN_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK +High Pulse Width Slow IN_FIFO/WRCLK n/a 2.150 6.000 3.850 IN_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: mem_refclk + To Clock: mem_refclk + +Setup : 0 Failing Endpoints, Worst Slack 1.810ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.375ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 0.875ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.810ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLMSTREMPTY + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: mem_refclk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (mem_refclk rise@3.000ns - mem_refclk rise@0.000ns) + Data Path Delay: 1.093ns (logic 0.622ns (56.908%) route 0.471ns (43.092%)) + Logic Levels: 0 + Clock Path Skew: -0.031ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.241ns = ( 1.759 - 3.000 ) + Source Clock Delay (SCD): -0.634ns + Clock Pessimism Removal (CPR): 0.576ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.621 -0.634 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + ------------------------------------------------------------------- ------------------- + PHY_CONTROL_X1Y1 PHY_CONTROL (Prop_phy_control_MEMREFCLK_PHYCTLEMPTY) + 0.622 -0.012 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLEMPTY + net (fo=1, estimated) 0.471 0.459 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i_n_1 + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLMSTREMPTY + ------------------------------------------------------------------- ------------------- + + (clock mem_refclk rise edge) + 3.000 3.000 r + E3 0.000 3.000 r CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 4.411 r input_clock/O + net (fo=1, unplaced) 0.439 4.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 -0.530 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 0.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 0.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 1.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 1.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.590 1.759 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + clock pessimism 0.576 2.335 + clock uncertainty -0.054 2.280 + PHY_CONTROL_X1Y1 PHY_CONTROL (Setup_phy_control_MEMREFCLK_PHYCTLMSTREMPTY) + -0.011 2.269 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i + ------------------------------------------------------------------- + required time 2.269 + arrival time -0.459 + ------------------------------------------------------------------- + slack 1.810 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.375ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLMSTREMPTY + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: mem_refclk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mem_refclk rise@0.000ns - mem_refclk rise@0.000ns) + Data Path Delay: 0.512ns (logic 0.313ns (61.188%) route 0.199ns (38.812%)) + Logic Levels: 0 + Clock Path Skew: 0.014ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.645ns + Source Clock Delay (SCD): -0.399ns + Clock Pessimism Removal (CPR): -0.259ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.262 -0.399 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + ------------------------------------------------------------------- ------------------- + PHY_CONTROL_X1Y1 PHY_CONTROL (Prop_phy_control_MEMREFCLK_PHYCTLEMPTY) + 0.313 -0.086 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLEMPTY + net (fo=1, estimated) 0.199 0.112 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i_n_1 + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLMSTREMPTY + ------------------------------------------------------------------- ------------------- + + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.276 -0.645 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + clock pessimism 0.259 -0.385 + PHY_CONTROL_X1Y1 PHY_CONTROL (Hold_phy_control_MEMREFCLK_PHYCTLMSTREMPTY) + 0.123 -0.262 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i + ------------------------------------------------------------------- + required time 0.262 + arrival time 0.112 + ------------------------------------------------------------------- + slack 0.375 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: mem_refclk +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a PHY_CONTROL/MEMREFCLK n/a 1.475 3.000 1.525 PHY_CONTROL_X1Y1 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK +Max Period n/a PLLE2_ADV/CLKOUT1 n/a 160.000 3.000 157.000 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 +Low Pulse Width Slow PHY_CONTROL/MEMREFCLK n/a 0.625 1.500 0.875 PHY_CONTROL_X1Y1 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK +High Pulse Width Slow PHY_CONTROL/MEMREFCLK n/a 0.625 1.500 0.875 PHY_CONTROL_X1Y1 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk + To Clock: oserdes_clk + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clk +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OSERDESE2/CLK n/a 1.667 3.000 1.333 OLOGIC_X1Y51 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[0].oserdes_dq_.sdr.oserdes_dq_i/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clkdiv + To Clock: oserdes_clkdiv + +Setup : 0 Failing Endpoints, Worst Slack 10.094ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.113ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 3.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 10.094ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[11].oserdes_dq_.sdr.oserdes_dq_i/D4 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (oserdes_clkdiv rise@12.000ns - oserdes_clkdiv rise@0.000ns) + Data Path Delay: 1.662ns (logic 0.674ns (40.554%) route 0.988ns (59.446%)) + Logic Levels: 0 + Clock Path Skew: 0.435ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.706ns = ( 13.706 - 12.000 ) + Source Clock Delay (SCD): 1.950ns + Clock Pessimism Removal (CPR): 0.679ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.614 -0.641 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 1.793 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.157 1.950 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, estimated) 0.000 1.950 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/oserdes_clkdiv + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y4 OUT_FIFO (Prop_out_fifo_RDCLK_Q6[7]) + 0.674 2.624 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/Q6[7] + net (fo=1, estimated) 0.988 3.612 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/oserdes_dq[43] + OLOGIC_X1Y50 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[11].oserdes_dq_.sdr.oserdes_dq_i/D4 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, unplaced) 0.439 13.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 8.470 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 9.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 9.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 10.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 10.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.583 10.752 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 13.123 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 13.271 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, estimated) 0.435 13.706 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y50 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[11].oserdes_dq_.sdr.oserdes_dq_i/CLKDIV + clock pessimism 0.679 14.385 + clock uncertainty -0.054 14.330 + OLOGIC_X1Y50 OSERDESE2 (Setup_oserdese2_CLKDIV_D4) + -0.625 13.705 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[11].oserdes_dq_.sdr.oserdes_dq_i + ------------------------------------------------------------------- + required time 13.705 + arrival time -3.612 + ------------------------------------------------------------------- + slack 10.094 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.113ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/D3 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv rise@0.000ns - oserdes_clkdiv rise@0.000ns) + Data Path Delay: 0.336ns (logic 0.138ns (41.109%) route 0.198ns (58.891%)) + Logic Levels: 0 + Clock Path Skew: 0.203ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.784ns + Source Clock Delay (SCD): 1.773ns + Clock Pessimism Removal (CPR): -0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.259 -0.402 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.690 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.083 1.773 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, estimated) 0.000 1.773 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/oserdes_clkdiv + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y4 OUT_FIFO (Prop_out_fifo_RDCLK_Q2[2]) + 0.138 1.911 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/Q2[2] + net (fo=1, estimated) 0.198 2.109 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/oserdes_dq[10] + OLOGIC_X1Y53 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/D3 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.272 -0.648 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.493 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.581 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, estimated) 0.203 1.784 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y53 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/CLKDIV + clock pessimism 0.192 1.976 + OLOGIC_X1Y53 OSERDESE2 (Hold_oserdese2_CLKDIV_D3) + 0.019 1.995 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i + ------------------------------------------------------------------- + required time -1.995 + arrival time 2.109 + ------------------------------------------------------------------- + slack 0.113 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clkdiv +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OUT_FIFO/RDCLK n/a 5.000 12.000 7.000 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK +Low Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK +High Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_1 + To Clock: oserdes_clk_1 + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clk_1 +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OSERDESE2/CLK n/a 1.667 3.000 1.333 OLOGIC_X1Y63 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[0].oserdes_dq_.sdr.oserdes_dq_i/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clkdiv_1 + To Clock: oserdes_clkdiv_1 + +Setup : 0 Failing Endpoints, Worst Slack 10.595ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.119ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 3.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 10.595ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[10].oserdes_dq_.sdr.oserdes_dq_i/D1 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv_1 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (oserdes_clkdiv_1 rise@12.000ns - oserdes_clkdiv_1 rise@0.000ns) + Data Path Delay: 1.144ns (logic 0.674ns (58.916%) route 0.470ns (41.084%)) + Logic Levels: 0 + Clock Path Skew: 0.419ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.679ns = ( 13.679 - 12.000 ) + Source Clock Delay (SCD): 1.939ns + Clock Pessimism Removal (CPR): 0.678ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.603 -0.652 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 1.782 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.157 1.939 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, estimated) 0.000 1.939 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/oserdes_clkdiv + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y5 OUT_FIFO (Prop_out_fifo_RDCLK_Q5[4]) + 0.674 2.613 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/Q5[4] + net (fo=1, estimated) 0.470 3.083 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/oserdes_dq[40] + OLOGIC_X1Y69 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[10].oserdes_dq_.sdr.oserdes_dq_i/D1 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_1 rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, unplaced) 0.439 13.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 8.470 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 9.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 9.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 10.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 10.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.573 10.742 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 13.112 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 13.260 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, estimated) 0.419 13.679 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y69 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[10].oserdes_dq_.sdr.oserdes_dq_i/CLKDIV + clock pessimism 0.678 14.358 + clock uncertainty -0.054 14.303 + OLOGIC_X1Y69 OSERDESE2 (Setup_oserdese2_CLKDIV_D1) + -0.625 13.678 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[10].oserdes_dq_.sdr.oserdes_dq_i + ------------------------------------------------------------------- + required time 13.678 + arrival time -3.083 + ------------------------------------------------------------------- + slack 10.595 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.119ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/D3 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv_1 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_1 rise@0.000ns - oserdes_clkdiv_1 rise@0.000ns) + Data Path Delay: 0.336ns (logic 0.138ns (41.109%) route 0.198ns (58.891%)) + Logic Levels: 0 + Clock Path Skew: 0.197ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.773ns + Source Clock Delay (SCD): 1.768ns + Clock Pessimism Removal (CPR): -0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.254 -0.407 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.685 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.083 1.768 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, estimated) 0.000 1.768 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/oserdes_clkdiv + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y5 OUT_FIFO (Prop_out_fifo_RDCLK_Q2[2]) + 0.138 1.906 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/Q2[2] + net (fo=1, estimated) 0.198 2.104 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/oserdes_dq[10] + OLOGIC_X1Y65 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/D3 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.268 -0.653 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.488 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.576 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, estimated) 0.197 1.773 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y65 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/CLKDIV + clock pessimism 0.192 1.966 + OLOGIC_X1Y65 OSERDESE2 (Hold_oserdese2_CLKDIV_D3) + 0.019 1.985 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i + ------------------------------------------------------------------- + required time -1.985 + arrival time 2.104 + ------------------------------------------------------------------- + slack 0.119 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clkdiv_1 +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OUT_FIFO/RDCLK n/a 5.000 12.000 7.000 OUT_FIFO_X1Y5 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK +Low Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y5 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK +High Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y5 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_2 + To Clock: oserdes_clk_2 + +Setup : 0 Failing Endpoints, Worst Slack 1.442ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.440ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.442ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqsts/D1 + (rising edge-triggered cell ODDR clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: oserdes_clk_2 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clk_2 rise@3.000ns - oserdes_clk_2 rise@0.000ns) + Data Path Delay: 1.041ns (logic 0.562ns (53.987%) route 0.479ns (46.013%)) + Logic Levels: 0 + Clock Path Skew: 0.423ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.285ns = ( 5.285 - 3.000 ) + Source Clock Delay (SCD): 2.577ns + Clock Pessimism Removal (CPR): 0.715ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.614 -0.641 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 1.793 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.784 2.577 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLKDELAYED_CTSBUS[0]) + 0.562 3.139 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/CTSBUS[0] + net (fo=2, estimated) 0.479 3.618 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/CTSBUS[0] + OLOGIC_X1Y82 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqsts/D1 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clk_2 rise edge) + 3.000 3.000 r + E3 0.000 3.000 r CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 4.411 r input_clock/O + net (fo=1, unplaced) 0.439 4.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 -0.530 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 0.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 0.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 1.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 1.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.583 1.752 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 4.123 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.739 4.862 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + net (fo=2, estimated) 0.423 5.285 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/oserdes_clk_delayed + OLOGIC_X1Y82 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqsts/C + clock pessimism 0.715 6.000 + clock uncertainty -0.054 5.945 + OLOGIC_X1Y82 ODDR (Setup_oddr_C_D1) -0.885 5.060 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqsts + ------------------------------------------------------------------- + required time 5.060 + arrival time -3.618 + ------------------------------------------------------------------- + slack 1.442 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.440ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqs/D1 + (rising edge-triggered cell ODDR clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: oserdes_clk_2 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clk_2 rise@0.000ns - oserdes_clk_2 rise@0.000ns) + Data Path Delay: 0.544ns (logic 0.346ns (63.590%) route 0.198ns (36.410%)) + Logic Levels: 0 + Clock Path Skew: 0.197ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 2.360ns + Source Clock Delay (SCD): 2.320ns + Clock Pessimism Removal (CPR): -0.158ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.259 -0.402 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.690 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.630 2.320 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLKDELAYED_DQSBUS[0]) + 0.346 2.666 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/DQSBUS[0] + net (fo=1, estimated) 0.198 2.865 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/DQSBUS[0] + OLOGIC_X1Y82 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqs/D1 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clk_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.272 -0.648 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.493 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.670 2.163 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + net (fo=2, estimated) 0.197 2.360 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/oserdes_clk_delayed + OLOGIC_X1Y82 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqs/C + clock pessimism 0.158 2.518 + OLOGIC_X1Y82 ODDR (Hold_oddr_C_D1) -0.093 2.425 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqs + ------------------------------------------------------------------- + required time -2.425 + arrival time 2.865 + ------------------------------------------------------------------- + slack 0.440 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clk_2 +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OSERDESE2/CLK n/a 1.667 3.000 1.333 OLOGIC_X1Y76 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[1].oserdes_dq_.ddr.oserdes_dq_i/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clkdiv_2 + To Clock: oserdes_clkdiv_2 + +Setup : 0 Failing Endpoints, Worst Slack 4.602ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.116ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 0.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 4.602ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/D1 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_2 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 6.000ns (oserdes_clkdiv_2 rise@6.000ns - oserdes_clkdiv_2 rise@0.000ns) + Data Path Delay: 1.144ns (logic 0.674ns (58.916%) route 0.470ns (41.084%)) + Logic Levels: 0 + Clock Path Skew: 0.426ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.696ns = ( 7.696 - 6.000 ) + Source Clock Delay (SCD): 1.950ns + Clock Pessimism Removal (CPR): 0.679ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.614 -0.641 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 1.793 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.157 1.950 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, estimated) 0.000 1.950 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/oserdes_clkdiv + OUT_FIFO_X1Y6 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y6 OUT_FIFO (Prop_out_fifo_RDCLK_Q6[0]) + 0.674 2.624 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/Q6[0] + net (fo=1, estimated) 0.470 3.094 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/of_dqbus[20] + OLOGIC_X1Y83 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/D1 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_2 rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, unplaced) 0.439 7.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 2.470 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 3.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 3.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 4.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 4.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.583 4.752 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 7.123 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 7.271 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, estimated) 0.426 7.696 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y83 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV + clock pessimism 0.679 8.375 + clock uncertainty -0.054 8.321 + OLOGIC_X1Y83 OSERDESE2 (Setup_oserdese2_CLKDIV_D1) + -0.625 7.696 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i + ------------------------------------------------------------------- + required time 7.696 + arrival time -3.094 + ------------------------------------------------------------------- + slack 4.602 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.116ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D3 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_2 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_2 rise@0.000ns - oserdes_clkdiv_2 rise@0.000ns) + Data Path Delay: 0.336ns (logic 0.138ns (41.109%) route 0.198ns (58.891%)) + Logic Levels: 0 + Clock Path Skew: 0.201ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.781ns + Source Clock Delay (SCD): 1.773ns + Clock Pessimism Removal (CPR): -0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.259 -0.402 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.690 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.083 1.773 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, estimated) 0.000 1.773 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/oserdes_clkdiv + OUT_FIFO_X1Y6 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y6 OUT_FIFO (Prop_out_fifo_RDCLK_Q2[2]) + 0.138 1.911 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/Q2[2] + net (fo=1, estimated) 0.198 2.109 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/of_dqbus[6] + OLOGIC_X1Y77 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D3 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.272 -0.648 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.493 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.581 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, estimated) 0.201 1.781 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y77 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV + clock pessimism 0.192 1.974 + OLOGIC_X1Y77 OSERDESE2 (Hold_oserdese2_CLKDIV_D3) + 0.019 1.993 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i + ------------------------------------------------------------------- + required time -1.993 + arrival time 2.109 + ------------------------------------------------------------------- + slack 0.116 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clkdiv_2 +Waveform(ns): { 0.000 3.000 } +Period(ns): 6.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OUT_FIFO/RDCLK n/a 5.000 6.000 1.000 OUT_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK +Low Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 3.000 0.850 OUT_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK +High Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 3.000 0.850 OUT_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_3 + To Clock: oserdes_clk_3 + +Setup : 0 Failing Endpoints, Worst Slack 1.458ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.432ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.458ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqsts/D1 + (rising edge-triggered cell ODDR clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: oserdes_clk_3 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clk_3 rise@3.000ns - oserdes_clk_3 rise@0.000ns) + Data Path Delay: 1.041ns (logic 0.562ns (53.987%) route 0.479ns (46.013%)) + Logic Levels: 0 + Clock Path Skew: 0.439ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.290ns = ( 5.290 - 3.000 ) + Source Clock Delay (SCD): 2.566ns + Clock Pessimism Removal (CPR): 0.714ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.603 -0.652 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 1.782 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.784 2.566 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLKDELAYED_CTSBUS[0]) + 0.562 3.128 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/CTSBUS[0] + net (fo=2, estimated) 0.479 3.607 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/CTSBUS[0] + OLOGIC_X1Y94 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqsts/D1 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clk_3 rise edge) + 3.000 3.000 r + E3 0.000 3.000 r CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 4.411 r input_clock/O + net (fo=1, unplaced) 0.439 4.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 -0.530 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 0.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 0.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 1.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 1.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.573 1.742 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 4.112 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.739 4.851 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + net (fo=2, estimated) 0.439 5.290 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/oserdes_clk_delayed + OLOGIC_X1Y94 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqsts/C + clock pessimism 0.714 6.005 + clock uncertainty -0.054 5.950 + OLOGIC_X1Y94 ODDR (Setup_oddr_C_D1) -0.885 5.065 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqsts + ------------------------------------------------------------------- + required time 5.065 + arrival time -3.607 + ------------------------------------------------------------------- + slack 1.458 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.432ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqs/D1 + (rising edge-triggered cell ODDR clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: oserdes_clk_3 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clk_3 rise@0.000ns - oserdes_clk_3 rise@0.000ns) + Data Path Delay: 0.544ns (logic 0.346ns (63.590%) route 0.198ns (36.410%)) + Logic Levels: 0 + Clock Path Skew: 0.205ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 2.363ns + Source Clock Delay (SCD): 2.316ns + Clock Pessimism Removal (CPR): -0.158ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.254 -0.407 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.685 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.630 2.316 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLKDELAYED_DQSBUS[0]) + 0.346 2.662 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/DQSBUS[0] + net (fo=1, estimated) 0.198 2.860 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/DQSBUS[0] + OLOGIC_X1Y94 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqs/D1 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clk_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.268 -0.653 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.488 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.670 2.158 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + net (fo=2, estimated) 0.205 2.363 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/oserdes_clk_delayed + OLOGIC_X1Y94 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqs/C + clock pessimism 0.158 2.521 + OLOGIC_X1Y94 ODDR (Hold_oddr_C_D1) -0.093 2.428 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqs + ------------------------------------------------------------------- + required time -2.428 + arrival time 2.860 + ------------------------------------------------------------------- + slack 0.432 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clk_3 +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OSERDESE2/CLK n/a 1.667 3.000 1.333 OLOGIC_X1Y88 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[1].oserdes_dq_.ddr.oserdes_dq_i/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clkdiv_3 + To Clock: oserdes_clkdiv_3 + +Setup : 0 Failing Endpoints, Worst Slack 4.618ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.109ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 0.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 4.618ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/D1 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_3 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 6.000ns (oserdes_clkdiv_3 rise@6.000ns - oserdes_clkdiv_3 rise@0.000ns) + Data Path Delay: 1.144ns (logic 0.674ns (58.916%) route 0.470ns (41.084%)) + Logic Levels: 0 + Clock Path Skew: 0.442ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.702ns = ( 7.702 - 6.000 ) + Source Clock Delay (SCD): 1.939ns + Clock Pessimism Removal (CPR): 0.678ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.603 -0.652 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 1.782 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.157 1.939 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, estimated) 0.000 1.939 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/oserdes_clkdiv + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y7 OUT_FIFO (Prop_out_fifo_RDCLK_Q6[0]) + 0.674 2.613 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/Q6[0] + net (fo=1, estimated) 0.470 3.083 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/of_dqbus[20] + OLOGIC_X1Y95 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/D1 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_3 rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, unplaced) 0.439 7.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 2.470 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 3.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 3.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 4.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 4.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.573 4.742 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 7.112 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 7.260 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, estimated) 0.442 7.702 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y95 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV + clock pessimism 0.678 8.381 + clock uncertainty -0.054 8.326 + OLOGIC_X1Y95 OSERDESE2 (Setup_oserdese2_CLKDIV_D1) + -0.625 7.701 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i + ------------------------------------------------------------------- + required time 7.701 + arrival time -3.083 + ------------------------------------------------------------------- + slack 4.618 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.109ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D3 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_3 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_3 rise@0.000ns - oserdes_clkdiv_3 rise@0.000ns) + Data Path Delay: 0.336ns (logic 0.138ns (41.109%) route 0.198ns (58.891%)) + Logic Levels: 0 + Clock Path Skew: 0.208ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.784ns + Source Clock Delay (SCD): 1.768ns + Clock Pessimism Removal (CPR): -0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.254 -0.407 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.685 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.083 1.768 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, estimated) 0.000 1.768 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/oserdes_clkdiv + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y7 OUT_FIFO (Prop_out_fifo_RDCLK_Q2[2]) + 0.138 1.906 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/Q2[2] + net (fo=1, estimated) 0.198 2.104 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/of_dqbus[6] + OLOGIC_X1Y89 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D3 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.268 -0.653 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.488 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.576 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, estimated) 0.208 1.784 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y89 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV + clock pessimism 0.192 1.976 + OLOGIC_X1Y89 OSERDESE2 (Hold_oserdese2_CLKDIV_D3) + 0.019 1.995 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i + ------------------------------------------------------------------- + required time -1.995 + arrival time 2.104 + ------------------------------------------------------------------- + slack 0.109 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clkdiv_3 +Waveform(ns): { 0.000 3.000 } +Period(ns): 6.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OUT_FIFO/RDCLK n/a 5.000 6.000 1.000 OUT_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK +Low Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 3.000 0.850 OUT_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK +High Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 3.000 0.850 OUT_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: pll_clk3_out + To Clock: pll_clk3_out + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 3.000ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: pll_clk3_out +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFH/I n/a 2.155 12.000 9.845 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/I +Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 12.000 88.000 MMCME2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKIN1 +Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 3.000 6.000 3.000 MMCME2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKIN1 +High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 3.000 6.000 3.000 MMCME2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKIN1 + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_div2_bufg_in + To Clock: clk_div2_bufg_in + +Setup : 0 Failing Endpoints, Worst Slack 4.741ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.152ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 2.500ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 4.741ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r_reg[11]/C + (rising edge-triggered cell FDPE clocked by clk_div2_bufg_in {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r1_reg/D + (rising edge-triggered cell FDPE clocked by clk_div2_bufg_in {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: clk_div2_bufg_in + Path Type: Setup (Max at Slow Process Corner) + Requirement: 6.000ns (clk_div2_bufg_in rise@6.000ns - clk_div2_bufg_in rise@0.000ns) + Data Path Delay: 0.812ns (logic 0.478ns (58.867%) route 0.334ns (41.133%)) + Logic Levels: 0 + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.872ns = ( 5.128 - 6.000 ) + Source Clock Delay (SCD): 0.040ns + Clock Pessimism Removal (CPR): 0.767ns + Clock Uncertainty: 0.082ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.149ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_div2_bufg_in rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.584 -0.671 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.127 -0.544 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.803 0.259 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.702 -1.443 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKOUT1 + net (fo=1, unplaced) 0.803 -0.640 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_div2_bufg_in + BUFG (Prop_bufg_I_O) 0.096 -0.544 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_clk_div2/O + net (fo=13, unplaced) 0.584 0.040 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_clk_div2_n_0 + FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r_reg[11]/C + ------------------------------------------------------------------- ------------------- + FDPE (Prop_fdpe_C_Q) 0.478 0.518 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r_reg[11]/Q + net (fo=1, unplaced) 0.334 0.852 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r[11] + FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r1_reg/D + ------------------------------------------------------------------- ------------------- + + (clock clk_div2_bufg_in rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, unplaced) 0.439 7.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 2.470 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 3.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 3.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 4.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 4.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.439 4.608 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.081 4.689 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.763 5.452 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.616 3.835 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKOUT1 + net (fo=1, unplaced) 0.763 4.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_div2_bufg_in + BUFG (Prop_bufg_I_O) 0.091 4.689 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_clk_div2/O + net (fo=13, unplaced) 0.439 5.128 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_clk_div2_n_0 + FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r1_reg/C + clock pessimism 0.767 5.895 + clock uncertainty -0.082 5.812 + FDPE (Setup_fdpe_C_D) -0.220 5.592 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r1_reg + ------------------------------------------------------------------- + required time 5.592 + arrival time -0.852 + ------------------------------------------------------------------- + slack 4.741 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.152ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r_reg[11]/C + (rising edge-triggered cell FDPE clocked by clk_div2_bufg_in {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r1_reg/D + (rising edge-triggered cell FDPE clocked by clk_div2_bufg_in {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: clk_div2_bufg_in + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_div2_bufg_in rise@0.000ns - clk_div2_bufg_in rise@0.000ns) + Data Path Delay: 0.288ns (logic 0.147ns (51.079%) route 0.141ns (48.921%)) + Logic Levels: 0 + Clock Path Skew: 0.145ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.359ns + Source Clock Delay (SCD): -0.413ns + Clock Pessimism Removal (CPR): -0.091ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_div2_bufg_in rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.114 -0.547 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.020 -0.527 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.338 -0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -0.703 -0.891 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKOUT1 + net (fo=1, unplaced) 0.338 -0.553 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_div2_bufg_in + BUFG (Prop_bufg_I_O) 0.026 -0.527 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_clk_div2/O + net (fo=13, unplaced) 0.114 -0.413 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_clk_div2_n_0 + FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r_reg[11]/C + ------------------------------------------------------------------- ------------------- + FDPE (Prop_fdpe_C_Q) 0.147 -0.266 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r_reg[11]/Q + net (fo=1, unplaced) 0.141 -0.125 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r[11] + FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r1_reg/D + ------------------------------------------------------------------- ------------------- + + (clock clk_div2_bufg_in rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.259 -0.661 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.043 -0.618 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.356 -0.262 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -0.741 -1.003 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKOUT1 + net (fo=1, unplaced) 0.356 -0.647 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_div2_bufg_in + BUFG (Prop_bufg_I_O) 0.029 -0.618 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_clk_div2/O + net (fo=13, unplaced) 0.259 -0.359 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_clk_div2_n_0 + FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r1_reg/C + clock pessimism 0.091 -0.268 + FDPE (Hold_fdpe_C_D) -0.009 -0.277 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r1_reg + ------------------------------------------------------------------- + required time 0.277 + arrival time -0.125 + ------------------------------------------------------------------- + slack 0.152 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: clk_div2_bufg_in +Waveform(ns): { 0.000 3.000 } +Period(ns): 6.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKOUT1 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFG/I n/a 2.155 6.000 3.845 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_clk_div2/I +Max Period n/a MMCME2_ADV/CLKOUT1 n/a 213.360 6.000 207.360 MMCME2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKOUT1 +Low Pulse Width Slow FDPE/C n/a 0.500 3.000 2.500 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r1_reg/C +High Pulse Width Slow FDPE/C n/a 0.500 3.000 2.500 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r1_reg/C + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_pll_i + To Clock: clk_pll_i + +Setup : 0 Failing Endpoints, Worst Slack 5.851ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.034ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 3.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 5.851ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrlvl_done_r1_reg/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_final_chk_reg/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: clk_pll_i + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (clk_pll_i rise@12.000ns - clk_pll_i rise@0.000ns) + Data Path Delay: 5.981ns (logic 1.393ns (23.290%) route 4.588ns (76.710%)) + Logic Levels: 6 (LUT5=1 LUT6=5) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.653ns = ( 11.347 - 12.000 ) + Source Clock Delay (SCD): 0.259ns + Clock Pessimism Removal (CPR): 0.767ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.584 -0.671 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.127 -0.544 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.803 0.259 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.702 -1.443 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, unplaced) 0.803 -0.640 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFG (Prop_bufg_I_O) 0.096 -0.544 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=6179, unplaced) 0.803 0.259 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg[14]_0 + FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrlvl_done_r1_reg/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.478 0.737 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrlvl_done_r1_reg/Q + net (fo=12, unplaced) 1.013 1.750 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrlvl_done_r1 + LUT6 (Prop_lut6_I0_O) 0.295 2.045 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/init_state_r[3]_i_24/O + net (fo=3, unplaced) 0.982 3.027 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/init_state_r[3]_i_24_n_0 + LUT6 (Prop_lut6_I0_O) 0.124 3.151 f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/init_state_r[4]_i_27/O + net (fo=2, unplaced) 0.460 3.611 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/init_state_r[4]_i_27_n_0 + LUT5 (Prop_lut5_I0_O) 0.124 3.735 f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/init_state_r[0]_i_16/O + net (fo=1, unplaced) 0.449 4.184 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/init_state_r[0]_i_16_n_0 + LUT6 (Prop_lut6_I5_O) 0.124 4.308 f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/init_state_r[0]_i_5/O + net (fo=1, unplaced) 0.732 5.040 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/init_state_r[0]_i_5_n_0 + LUT6 (Prop_lut6_I3_O) 0.124 5.164 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/init_state_r[0]_i_1/O + net (fo=2, unplaced) 0.952 6.116 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/init_state_r[0]_i_1_n_0 + LUT6 (Prop_lut6_I0_O) 0.124 6.240 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_final_chk_i_1/O + net (fo=1, unplaced) 0.000 6.240 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_final_chk_i_1_n_0 + FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_final_chk_reg/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, unplaced) 0.439 13.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 8.470 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 9.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 9.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 10.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 10.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.439 10.608 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.081 10.689 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.763 11.452 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.616 9.835 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, unplaced) 0.763 10.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFG (Prop_bufg_I_O) 0.091 10.689 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=6179, unplaced) 0.658 11.347 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg[14]_0 + FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_final_chk_reg/C + clock pessimism 0.767 12.114 + clock uncertainty -0.067 12.046 + FDRE (Setup_fdre_C_D) 0.044 12.090 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_final_chk_reg + ------------------------------------------------------------------- + required time 12.090 + arrival time -6.240 + ------------------------------------------------------------------- + slack 5.851 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.034ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_b_channel_0/bid_t_reg[0]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMB/I + (rising edge-triggered cell RAMD32 clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: clk_pll_i + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_pll_i rise@0.000ns - clk_pll_i rise@0.000ns) + Data Path Delay: 0.272ns (logic 0.131ns (48.199%) route 0.141ns (51.801%)) + Logic Levels: 0 + Clock Path Skew: 0.145ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.316ns + Clock Pessimism Removal (CPR): -0.091ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.114 -0.547 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.020 -0.527 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.338 -0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -0.703 -0.891 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, unplaced) 0.338 -0.553 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFG (Prop_bufg_I_O) 0.026 -0.527 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=6179, unplaced) 0.211 -0.316 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_b_channel_0/cnt_read_reg[0] + FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_b_channel_0/bid_t_reg[0]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.131 -0.185 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_b_channel_0/bid_t_reg[0]/Q + net (fo=1, unplaced) 0.141 -0.044 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/DIB0 + RAMD32 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMB/I + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.259 -0.661 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.043 -0.618 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.356 -0.262 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -0.741 -1.003 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, unplaced) 0.356 -0.647 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFG (Prop_bufg_I_O) 0.029 -0.618 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=6179, unplaced) 0.356 -0.262 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/WCLK + RAMD32 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMB/CLK + clock pessimism 0.091 -0.171 + RAMD32 (Hold_ramd32_CLK_I) + 0.093 -0.078 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMB + ------------------------------------------------------------------- + required time 0.078 + arrival time -0.044 + ------------------------------------------------------------------- + slack 0.034 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: clk_pll_i +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OUT_FIFO/WRCLK n/a 5.000 12.000 7.000 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/WRCLK +Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 12.000 88.000 MMCME2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBIN +Low Pulse Width Slow OUT_FIFO/WRCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/WRCLK +High Pulse Width Slow OUT_FIFO/WRCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/WRCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: mmcm_ps_clk_bufg_in + To Clock: mmcm_ps_clk_bufg_in + +Setup : 0 Failing Endpoints, Worst Slack 22.715ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.152ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 11.500ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 22.715ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r_reg[11]/C + (rising edge-triggered cell FDPE clocked by mmcm_ps_clk_bufg_in {rise@0.000ns fall@12.000ns period=24.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r1_reg/D + (rising edge-triggered cell FDPE clocked by mmcm_ps_clk_bufg_in {rise@0.000ns fall@12.000ns period=24.000ns}) + Path Group: mmcm_ps_clk_bufg_in + Path Type: Setup (Max at Slow Process Corner) + Requirement: 24.000ns (mmcm_ps_clk_bufg_in rise@24.000ns - mmcm_ps_clk_bufg_in rise@0.000ns) + Data Path Delay: 0.812ns (logic 0.478ns (58.867%) route 0.334ns (41.133%)) + Logic Levels: 0 + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.872ns = ( 23.128 - 24.000 ) + Source Clock Delay (SCD): 0.040ns + Clock Pessimism Removal (CPR): 0.767ns + Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.204ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mmcm_ps_clk_bufg_in rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.584 -0.671 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.127 -0.544 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.803 0.259 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.702 -1.443 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKOUT0 + net (fo=1, unplaced) 0.803 -0.640 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_ps_clk_bufg_in + BUFG (Prop_bufg_I_O) 0.096 -0.544 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_mmcm_ps_clk/O + net (fo=13, unplaced) 0.584 0.040 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_mmcm_ps_clk_n_0 + FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r_reg[11]/C + ------------------------------------------------------------------- ------------------- + FDPE (Prop_fdpe_C_Q) 0.478 0.518 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r_reg[11]/Q + net (fo=1, unplaced) 0.334 0.852 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r[11] + FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r1_reg/D + ------------------------------------------------------------------- ------------------- + + (clock mmcm_ps_clk_bufg_in rise edge) + 24.000 24.000 r + E3 0.000 24.000 r CLK100MHZ (IN) + net (fo=0) 0.000 24.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 25.411 r input_clock/O + net (fo=1, unplaced) 0.439 25.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 20.470 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 21.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 21.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 22.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 22.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.439 22.608 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.081 22.689 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.763 23.452 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.616 21.835 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKOUT0 + net (fo=1, unplaced) 0.763 22.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_ps_clk_bufg_in + BUFG (Prop_bufg_I_O) 0.091 22.689 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_mmcm_ps_clk/O + net (fo=13, unplaced) 0.439 23.128 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_mmcm_ps_clk_n_0 + FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r1_reg/C + clock pessimism 0.767 23.895 + clock uncertainty -0.108 23.787 + FDPE (Setup_fdpe_C_D) -0.220 23.567 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r1_reg + ------------------------------------------------------------------- + required time 23.567 + arrival time -0.852 + ------------------------------------------------------------------- + slack 22.715 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.152ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r_reg[11]/C + (rising edge-triggered cell FDPE clocked by mmcm_ps_clk_bufg_in {rise@0.000ns fall@12.000ns period=24.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r1_reg/D + (rising edge-triggered cell FDPE clocked by mmcm_ps_clk_bufg_in {rise@0.000ns fall@12.000ns period=24.000ns}) + Path Group: mmcm_ps_clk_bufg_in + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mmcm_ps_clk_bufg_in rise@0.000ns - mmcm_ps_clk_bufg_in rise@0.000ns) + Data Path Delay: 0.288ns (logic 0.147ns (51.079%) route 0.141ns (48.921%)) + Logic Levels: 0 + Clock Path Skew: 0.145ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.359ns + Source Clock Delay (SCD): -0.413ns + Clock Pessimism Removal (CPR): -0.091ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mmcm_ps_clk_bufg_in rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.114 -0.547 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.020 -0.527 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.338 -0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -0.703 -0.891 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKOUT0 + net (fo=1, unplaced) 0.338 -0.553 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_ps_clk_bufg_in + BUFG (Prop_bufg_I_O) 0.026 -0.527 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_mmcm_ps_clk/O + net (fo=13, unplaced) 0.114 -0.413 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_mmcm_ps_clk_n_0 + FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r_reg[11]/C + ------------------------------------------------------------------- ------------------- + FDPE (Prop_fdpe_C_Q) 0.147 -0.266 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r_reg[11]/Q + net (fo=1, unplaced) 0.141 -0.125 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r[11] + FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r1_reg/D + ------------------------------------------------------------------- ------------------- + + (clock mmcm_ps_clk_bufg_in rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.259 -0.661 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.043 -0.618 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.356 -0.262 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -0.741 -1.003 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKOUT0 + net (fo=1, unplaced) 0.356 -0.647 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_ps_clk_bufg_in + BUFG (Prop_bufg_I_O) 0.029 -0.618 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_mmcm_ps_clk/O + net (fo=13, unplaced) 0.259 -0.359 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_mmcm_ps_clk_n_0 + FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r1_reg/C + clock pessimism 0.091 -0.268 + FDPE (Hold_fdpe_C_D) -0.009 -0.277 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r1_reg + ------------------------------------------------------------------- + required time 0.277 + arrival time -0.125 + ------------------------------------------------------------------- + slack 0.152 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: mmcm_ps_clk_bufg_in +Waveform(ns): { 0.000 12.000 } +Period(ns): 24.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKOUT0 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFG/I n/a 2.155 24.000 21.845 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_mmcm_ps_clk/I +Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 24.000 189.360 MMCME2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKOUT0 +Low Pulse Width Slow FDPE/C n/a 0.500 12.000 11.500 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r1_reg/C +High Pulse Width Slow FDPE/C n/a 0.500 12.000 11.500 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r1_reg/C + + + +--------------------------------------------------------------------------------------------------- +From Clock: pll_clkfbout + To Clock: pll_clkfbout + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 4.751ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: pll_clkfbout +Waveform(ns): { 0.000 3.000 } +Period(ns): 6.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a PLLE2_ADV/CLKFBOUT n/a 1.249 6.000 4.751 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT +Max Period n/a PLLE2_ADV/CLKFBIN n/a 52.633 6.000 46.633 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBIN + + + +--------------------------------------------------------------------------------------------------- +From Clock: sync_pulse + To Clock: sync_pulse + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.750ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: sync_pulse +Waveform(ns): { 1.312 4.312 } +Period(ns): 48.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a PLLE2_ADV/CLKOUT2 n/a 1.249 48.000 46.751 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 +Max Period n/a PLLE2_ADV/CLKOUT2 n/a 160.000 48.000 112.000 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 +High Pulse Width Slow PHASER_OUT_PHY/SYNCIN n/a 1.250 3.000 1.750 PHASER_OUT_PHY_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/SYNCIN + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_pll_i + To Clock: core_raw + +Setup : 0 Failing Endpoints, Worst Slack 10.968ns, Total Violation 0.000ns +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 10.968ns (required time - arrival time) + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: core_raw + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (MaxDelay Path 12.000ns) + Data Path Delay: 0.812ns (logic 0.478ns (58.867%) route 0.334ns (41.133%)) + Logic Levels: 0 + Timing Exception: MaxDelay Path 12.000ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + 0.000 0.000 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C + FDRE (Prop_fdre_C_Q) 0.478 0.478 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, unplaced) 0.334 0.812 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[0] + FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + ------------------------------------------------------------------- ------------------- + + max delay 12.000 12.000 + FDRE (Setup_fdre_C_D) -0.220 11.780 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + ------------------------------------------------------------------- + required time 11.780 + arrival time -0.812 + ------------------------------------------------------------------- + slack 10.968 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_pll_i + To Clock: ref_raw + +Setup : 0 Failing Endpoints, Worst Slack 18.960ns, Total Violation 0.000ns +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 18.960ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg/D + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: ref_raw + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (MaxDelay Path 20.000ns) + Data Path Delay: 1.084ns (logic 0.773ns (71.310%) route 0.311ns (28.690%)) + Logic Levels: 1 (LUT1=1) + Timing Exception: MaxDelay Path 20.000ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + 0.000 0.000 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + FDPE (Prop_fdpe_C_Q) 0.478 0.478 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/Q + net (fo=1, unplaced) 0.311 0.789 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep_n_0 + LUT1 (Prop_lut1_I0_O) 0.295 1.084 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_inst/O + net (fo=50, unplaced) 0.000 1.084 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg_0 + FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg/D + ------------------------------------------------------------------- ------------------- + + max delay 20.000 20.000 + FDRE (Setup_fdre_C_D) 0.044 20.044 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg + ------------------------------------------------------------------- + required time 20.044 + arrival time -1.084 + ------------------------------------------------------------------- + slack 18.960 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_pll_i + To Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk + +Setup : 0 Failing Endpoints, Worst Slack 12.367ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 44.683ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 12.367ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq/DDLY + (falling edge-triggered cell ISERDESE2 clocked by u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 16.500ns (u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk fall@16.500ns - clk_pll_i rise@0.000ns) + Data Path Delay: 4.867ns (logic 4.064ns (83.504%) route 0.803ns (16.496%)) + Logic Levels: 2 (IBUF_INTERMDISABLE=1 IDELAYE2=1) + Clock Path Skew: 1.118ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.801ns = ( 2.301 - 1.500 ) + Source Clock Delay (SCD): 0.259ns + Clock Pessimism Removal (CPR): 0.576ns + Clock Uncertainty: 0.220ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.154ns + Timing Exception: MultiCycle Path Setup -end 6 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.584 -0.671 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.127 -0.544 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.803 0.259 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.702 -1.443 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, unplaced) 0.803 -0.640 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFG (Prop_bufg_I_O) 0.096 -0.544 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=6179, unplaced) 0.803 0.259 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/last_master_r_reg[2] + FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.478 0.737 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/Q + net (fo=40, unplaced) 0.803 1.539 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[13].u_iobuf_dq/IBUFDISABLE + T3 IBUF_INTERMDISABLE (Prop_ibuf_intermdisable_IBUFDISABLE_O) + 2.771 4.310 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[13].u_iobuf_dq/IBUF/O + net (fo=2, estimated) 0.000 4.310 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/mem_dq_in[1] + IDELAY_X1Y77 IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT) + 0.815 5.125 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[2].iserdes_dq_.idelay_dq.idelaye2/DATAOUT + net (fo=1, estimated) 0.000 5.125 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/data_in_dly_2 + ILOGIC_X1Y77 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq/DDLY + ------------------------------------------------------------------- ------------------- + + (clock u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk fall edge) + 16.500 16.500 f + E3 0.000 16.500 f CLK100MHZ (IN) + net (fo=0) 0.000 16.500 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 17.911 f input_clock/O + net (fo=1, unplaced) 0.439 18.350 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 12.970 f clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 13.732 sys_raw + BUFG (Prop_bufg_I_O) 0.091 13.823 f sys_buffer/O + net (fo=1, unplaced) 0.763 14.586 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.083 14.669 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, estimated) 0.577 15.246 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.624 16.870 f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + net (fo=16, estimated) 0.431 17.301 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/CLKB0 + ILOGIC_X1Y77 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq/CLKB (IS_INVERTED) + clock pessimism 0.576 17.877 + clock uncertainty -0.220 17.657 + ILOGIC_X1Y77 ISERDESE2 (Setup_iserdese2_CLKB_DDLY) + -0.165 17.492 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq + ------------------------------------------------------------------- + required time 17.492 + arrival time -5.125 + ------------------------------------------------------------------- + slack 12.367 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 44.683ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[7].iserdes_dq_.iserdesdq/DDLY + (rising edge-triggered cell ISERDESE2 clocked by u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: -45.000ns (u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk rise@15.000ns - clk_pll_i rise@60.000ns) + Data Path Delay: 1.466ns (logic 1.128ns (76.922%) route 0.338ns (23.078%)) + Logic Levels: 2 (IBUF_INTERMDISABLE=1 IDELAYE2=1) + Clock Path Skew: 1.508ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.933ns + Source Clock Delay (SCD): -0.316ns + Clock Pessimism Removal (CPR): -0.259ns + Clock Uncertainty: 0.220ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.154ns + Timing Exception: MultiCycle Path Setup -end 6 Hold -start 5 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 60.000 60.000 r + E3 0.000 60.000 r CLK100MHZ (IN) + net (fo=0) 0.000 60.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 60.250 r input_clock/O + net (fo=1, unplaced) 0.114 60.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 58.586 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 58.925 sys_raw + BUFG (Prop_bufg_I_O) 0.026 58.951 r sys_buffer/O + net (fo=1, unplaced) 0.338 59.289 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 59.339 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.114 59.453 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.020 59.473 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.338 59.811 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -0.703 59.109 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, unplaced) 0.338 59.447 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFG (Prop_bufg_I_O) 0.026 59.473 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=6179, unplaced) 0.211 59.684 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/last_master_r_reg[2] + FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.147 59.831 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/Q + net (fo=40, unplaced) 0.338 60.170 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[10].u_iobuf_dq/IBUFDISABLE + U4 IBUF_INTERMDISABLE (Prop_ibuf_intermdisable_IBUFDISABLE_O) + 0.738 60.908 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[10].u_iobuf_dq/IBUF/O + net (fo=2, estimated) 0.000 60.908 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/mem_dq_in[6] + IDELAY_X1Y84 IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT) + 0.243 61.151 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[7].iserdes_dq_.idelay_dq.idelaye2/DATAOUT + net (fo=1, estimated) 0.000 61.151 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/data_in_dly_7 + ILOGIC_X1Y84 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[7].iserdes_dq_.iserdesdq/DDLY + ------------------------------------------------------------------- ------------------- + + (clock u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk rise edge) + 15.000 15.000 r + E3 0.000 15.000 r CLK100MHZ (IN) + net (fo=0) 0.000 15.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 15.438 r input_clock/O + net (fo=1, unplaced) 0.259 15.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 13.285 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 13.642 sys_raw + BUFG (Prop_bufg_I_O) 0.029 13.671 r sys_buffer/O + net (fo=1, unplaced) 0.356 14.027 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.053 14.080 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, estimated) 0.269 14.349 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.381 15.730 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + net (fo=16, estimated) 0.203 15.933 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq_0 + ILOGIC_X1Y84 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[7].iserdes_dq_.iserdesdq/CLK + clock pessimism 0.259 16.192 + clock uncertainty 0.220 16.412 + ILOGIC_X1Y84 ISERDESE2 (Hold_iserdese2_CLK_DDLY) + 0.056 16.468 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[7].iserdes_dq_.iserdesdq + ------------------------------------------------------------------- + required time -16.468 + arrival time 61.151 + ------------------------------------------------------------------- + slack 44.683 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_pll_i + To Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk + +Setup : 0 Failing Endpoints, Worst Slack 12.374ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 44.679ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 12.374ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq/DDLY + (falling edge-triggered cell ISERDESE2 clocked by u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 16.500ns (u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk fall@16.500ns - clk_pll_i rise@0.000ns) + Data Path Delay: 4.867ns (logic 4.064ns (83.504%) route 0.803ns (16.496%)) + Logic Levels: 2 (IBUF_INTERMDISABLE=1 IDELAYE2=1) + Clock Path Skew: 1.126ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.809ns = ( 2.309 - 1.500 ) + Source Clock Delay (SCD): 0.259ns + Clock Pessimism Removal (CPR): 0.576ns + Clock Uncertainty: 0.220ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.154ns + Timing Exception: MultiCycle Path Setup -end 6 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.584 -0.671 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.127 -0.544 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.803 0.259 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.702 -1.443 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, unplaced) 0.803 -0.640 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFG (Prop_bufg_I_O) 0.096 -0.544 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=6179, unplaced) 0.803 0.259 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/last_master_r_reg[2] + FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.478 0.737 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/Q + net (fo=40, unplaced) 0.803 1.539 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[6].u_iobuf_dq/IBUFDISABLE + L4 IBUF_INTERMDISABLE (Prop_ibuf_intermdisable_IBUFDISABLE_O) + 2.771 4.310 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[6].u_iobuf_dq/IBUF/O + net (fo=2, estimated) 0.000 4.310 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/mem_dq_in[1] + IDELAY_X1Y89 IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT) + 0.815 5.125 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[2].iserdes_dq_.idelay_dq.idelaye2/DATAOUT + net (fo=1, estimated) 0.000 5.125 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/data_in_dly_2 + ILOGIC_X1Y89 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq/DDLY + ------------------------------------------------------------------- ------------------- + + (clock u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk fall edge) + 16.500 16.500 f + E3 0.000 16.500 f CLK100MHZ (IN) + net (fo=0) 0.000 16.500 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 17.911 f input_clock/O + net (fo=1, unplaced) 0.439 18.350 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 12.970 f clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 13.732 sys_raw + BUFG (Prop_bufg_I_O) 0.091 13.823 f sys_buffer/O + net (fo=1, unplaced) 0.763 14.586 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.083 14.669 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, estimated) 0.567 15.236 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.624 16.860 f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + net (fo=16, estimated) 0.448 17.309 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/CLKB0_4 + ILOGIC_X1Y89 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq/CLKB (IS_INVERTED) + clock pessimism 0.576 17.884 + clock uncertainty -0.220 17.665 + ILOGIC_X1Y89 ISERDESE2 (Setup_iserdese2_CLKB_DDLY) + -0.165 17.500 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq + ------------------------------------------------------------------- + required time 17.500 + arrival time -5.125 + ------------------------------------------------------------------- + slack 12.374 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 44.679ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[7].iserdes_dq_.iserdesdq/DDLY + (rising edge-triggered cell ISERDESE2 clocked by u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: -45.000ns (u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk rise@15.000ns - clk_pll_i rise@60.000ns) + Data Path Delay: 1.466ns (logic 1.128ns (76.922%) route 0.338ns (23.078%)) + Logic Levels: 2 (IBUF_INTERMDISABLE=1 IDELAYE2=1) + Clock Path Skew: 1.512ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.937ns + Source Clock Delay (SCD): -0.316ns + Clock Pessimism Removal (CPR): -0.259ns + Clock Uncertainty: 0.220ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.154ns + Timing Exception: MultiCycle Path Setup -end 6 Hold -start 5 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 60.000 60.000 r + E3 0.000 60.000 r CLK100MHZ (IN) + net (fo=0) 0.000 60.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 60.250 r input_clock/O + net (fo=1, unplaced) 0.114 60.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 58.586 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 58.925 sys_raw + BUFG (Prop_bufg_I_O) 0.026 58.951 r sys_buffer/O + net (fo=1, unplaced) 0.338 59.289 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 59.339 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.114 59.453 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.020 59.473 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.338 59.811 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -0.703 59.109 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, unplaced) 0.338 59.447 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFG (Prop_bufg_I_O) 0.026 59.473 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=6179, unplaced) 0.211 59.684 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/last_master_r_reg[2] + FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.147 59.831 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/Q + net (fo=40, unplaced) 0.338 60.170 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[2].u_iobuf_dq/IBUFDISABLE + K3 IBUF_INTERMDISABLE (Prop_ibuf_intermdisable_IBUFDISABLE_O) + 0.738 60.908 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[2].u_iobuf_dq/IBUF/O + net (fo=2, estimated) 0.000 60.908 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/mem_dq_in[6] + IDELAY_X1Y96 IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT) + 0.243 61.151 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[7].iserdes_dq_.idelay_dq.idelaye2/DATAOUT + net (fo=1, estimated) 0.000 61.151 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/data_in_dly_7 + ILOGIC_X1Y96 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[7].iserdes_dq_.iserdesdq/DDLY + ------------------------------------------------------------------- ------------------- + + (clock u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk rise edge) + 15.000 15.000 r + E3 0.000 15.000 r CLK100MHZ (IN) + net (fo=0) 0.000 15.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 15.438 r input_clock/O + net (fo=1, unplaced) 0.259 15.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 13.285 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 13.642 sys_raw + BUFG (Prop_bufg_I_O) 0.029 13.671 r sys_buffer/O + net (fo=1, unplaced) 0.356 14.027 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.053 14.080 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, estimated) 0.265 14.345 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.381 15.725 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + net (fo=16, estimated) 0.211 15.937 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq_0 + ILOGIC_X1Y96 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[7].iserdes_dq_.iserdesdq/CLK + clock pessimism 0.259 16.196 + clock uncertainty 0.220 16.416 + ILOGIC_X1Y96 ISERDESE2 (Hold_iserdese2_CLK_DDLY) + 0.056 16.472 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[7].iserdes_dq_.iserdesdq + ------------------------------------------------------------------- + required time -16.472 + arrival time 61.151 + ------------------------------------------------------------------- + slack 44.679 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: sync_pulse + To Clock: mem_refclk + +Setup : 0 Failing Endpoints, Worst Slack 1.277ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.910ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.277ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 + (clock source 'sync_pulse' {rise@1.312ns fall@4.312ns period=48.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/SYNCIN + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: mem_refclk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 1.687ns (mem_refclk rise@6.000ns - sync_pulse fall@4.312ns) + Data Path Delay: 0.621ns (logic 0.000ns (0.000%) route 0.621ns (100.000%)) + Logic Levels: 0 + Clock Path Skew: 0.590ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.241ns = ( 4.759 - 6.000 ) + Source Clock Delay (SCD): -1.255ns = ( 3.057 - 4.312 ) + Clock Pessimism Removal (CPR): 0.576ns + Clock Uncertainty: 0.198ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.139ns + Phase Error (PE): 0.120ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sync_pulse fall edge) + 4.312 4.312 f + E3 0.000 4.312 f CLK100MHZ (IN) + net (fo=0) 0.000 4.312 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 5.794 f input_clock/O + net (fo=1, unplaced) 0.584 6.378 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 1.267 f clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 2.070 sys_raw + BUFG (Prop_bufg_I_O) 0.096 2.166 f sys_buffer/O + net (fo=1, unplaced) 0.803 2.969 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + 0.088 3.057 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 + net (fo=7, estimated) 0.621 3.678 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/sync_pulse + PHY_CONTROL_X1Y1 PHY_CONTROL f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/SYNCIN + ------------------------------------------------------------------- ------------------- + + (clock mem_refclk rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, unplaced) 0.439 7.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 2.470 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 3.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 3.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 4.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 4.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.590 4.759 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + clock pessimism 0.576 5.335 + clock uncertainty -0.198 5.137 + PHY_CONTROL_X1Y1 PHY_CONTROL (Setup_phy_control_MEMREFCLK_SYNCIN) + -0.182 4.955 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i + ------------------------------------------------------------------- + required time 4.955 + arrival time -3.678 + ------------------------------------------------------------------- + slack 1.277 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.910ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 + (clock source 'sync_pulse' {rise@1.312ns fall@4.312ns period=48.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/SYNCIN + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: mem_refclk + Path Type: Hold (Min at Slow Process Corner) + Requirement: -1.312ns (mem_refclk rise@0.000ns - sync_pulse rise@1.312ns) + Data Path Delay: 0.590ns (logic 0.000ns (0.000%) route 0.590ns (100.000%)) + Logic Levels: 0 + Clock Path Skew: 0.621ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.634ns + Source Clock Delay (SCD): -1.831ns = ( -0.519 - 1.312 ) + Clock Pessimism Removal (CPR): 0.576ns + Clock Uncertainty: 0.198ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.139ns + Phase Error (PE): 0.120ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sync_pulse rise edge) + 1.312 1.312 r + E3 0.000 1.312 r CLK100MHZ (IN) + net (fo=0) 0.000 1.312 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 2.724 r input_clock/O + net (fo=1, unplaced) 0.439 3.163 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 -2.218 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 -1.455 sys_raw + BUFG (Prop_bufg_I_O) 0.091 -1.364 r sys_buffer/O + net (fo=1, unplaced) 0.763 -0.602 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + 0.083 -0.519 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 + net (fo=7, estimated) 0.590 0.071 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/sync_pulse + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/SYNCIN + ------------------------------------------------------------------- ------------------- + + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.621 -0.634 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + clock pessimism -0.576 -1.210 + clock uncertainty 0.198 -1.012 + PHY_CONTROL_X1Y1 PHY_CONTROL (Hold_phy_control_MEMREFCLK_SYNCIN) + 0.174 -0.838 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i + ------------------------------------------------------------------- + required time 0.838 + arrival time 0.071 + ------------------------------------------------------------------- + slack 0.910 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk + To Clock: oserdes_clkdiv + +Setup : 0 Failing Endpoints, Worst Slack 2.105ns, Total Violation 0.000ns +Hold : 11 Failing Endpoints, Worst Slack -0.247ns, Total Violation -1.473ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 2.105ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clkdiv rise@12.000ns - oserdes_clk rise@9.000ns) + Data Path Delay: 0.338ns (logic 0.338ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.148ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.271ns = ( 13.271 - 12.000 ) + Source Clock Delay (SCD): 1.793ns = ( 10.793 - 9.000 ) + Clock Pessimism Removal (CPR): 0.670ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.081ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk rise edge) + 9.000 9.000 r + E3 0.000 9.000 r CLK100MHZ (IN) + net (fo=0) 0.000 9.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 10.482 r input_clock/O + net (fo=1, unplaced) 0.584 11.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 5.955 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 6.758 sys_raw + BUFG (Prop_bufg_I_O) 0.096 6.854 r sys_buffer/O + net (fo=1, unplaced) 0.803 7.657 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 7.745 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.614 8.359 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 10.793 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.338 11.131 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/RDENABLE + net (fo=1, estimated) 0.000 11.131 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/po_rd_enable + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, unplaced) 0.439 13.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 8.470 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 9.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 9.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 10.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 10.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.583 10.752 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 13.123 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 13.271 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, estimated) 0.000 13.271 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/oserdes_clkdiv + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + clock pessimism 0.670 13.941 + clock uncertainty -0.054 13.887 + OUT_FIFO_X1Y4 OUT_FIFO (Setup_out_fifo_RDCLK_RDEN) + -0.651 13.236 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo + ------------------------------------------------------------------- + required time 13.236 + arrival time -11.131 + ------------------------------------------------------------------- + slack 2.105 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (VIOLATED) : -0.247ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[6].oserdes_dq_.sdr.oserdes_dq_i/RST + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv rise@0.000ns - oserdes_clk rise@0.000ns) + Data Path Delay: 0.602ns (logic 0.272ns (45.211%) route 0.330ns (54.789%)) + Logic Levels: 0 + Clock Path Skew: 0.289ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.782ns + Source Clock Delay (SCD): 1.690ns + Clock Pessimism Removal (CPR): -0.197ns + Timing Exception: MultiCycle Path Setup -start 2 Hold -start 1 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.259 -0.402 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.690 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OSERDESRST) + 0.272 1.962 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OSERDESRST + net (fo=11, estimated) 0.330 2.292 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/po_oserdes_rst + OLOGIC_X1Y59 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[6].oserdes_dq_.sdr.oserdes_dq_i/RST + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.272 -0.648 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.493 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.581 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, estimated) 0.201 1.782 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y59 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[6].oserdes_dq_.sdr.oserdes_dq_i/CLKDIV + clock pessimism 0.197 1.979 + OLOGIC_X1Y59 OSERDESE2 (Hold_oserdese2_CLKDIV_RST) + 0.559 2.538 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[6].oserdes_dq_.sdr.oserdes_dq_i + ------------------------------------------------------------------- + required time -2.538 + arrival time 2.292 + ------------------------------------------------------------------- + slack -0.247 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_1 + To Clock: oserdes_clkdiv_1 + +Setup : 0 Failing Endpoints, Worst Slack 2.105ns, Total Violation 0.000ns +Hold : 12 Failing Endpoints, Worst Slack -0.268ns, Total Violation -2.486ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 2.105ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_1 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv_1 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clkdiv_1 rise@12.000ns - oserdes_clk_1 rise@9.000ns) + Data Path Delay: 0.338ns (logic 0.338ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.148ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.260ns = ( 13.260 - 12.000 ) + Source Clock Delay (SCD): 1.782ns = ( 10.782 - 9.000 ) + Clock Pessimism Removal (CPR): 0.669ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.081ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_1 rise edge) + 9.000 9.000 r + E3 0.000 9.000 r CLK100MHZ (IN) + net (fo=0) 0.000 9.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 10.482 r input_clock/O + net (fo=1, unplaced) 0.584 11.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 5.955 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 6.758 sys_raw + BUFG (Prop_bufg_I_O) 0.096 6.854 r sys_buffer/O + net (fo=1, unplaced) 0.803 7.657 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 7.745 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.603 8.348 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 10.782 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.338 11.120 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/RDENABLE + net (fo=1, estimated) 0.000 11.120 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/po_rd_enable + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_1 rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, unplaced) 0.439 13.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 8.470 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 9.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 9.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 10.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 10.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.573 10.742 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 13.112 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 13.260 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, estimated) 0.000 13.260 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/oserdes_clkdiv + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + clock pessimism 0.669 13.930 + clock uncertainty -0.054 13.876 + OUT_FIFO_X1Y5 OUT_FIFO (Setup_out_fifo_RDCLK_RDEN) + -0.651 13.225 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo + ------------------------------------------------------------------- + required time 13.225 + arrival time -11.120 + ------------------------------------------------------------------- + slack 2.105 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (VIOLATED) : -0.268ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_1 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[8].oserdes_dq_.sdr.oserdes_dq_i/RST + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv_1 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_1 rise@0.000ns - oserdes_clk_1 rise@0.000ns) + Data Path Delay: 0.576ns (logic 0.272ns (47.195%) route 0.304ns (52.805%)) + Logic Levels: 0 + Clock Path Skew: 0.285ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.773ns + Source Clock Delay (SCD): 1.685ns + Clock Pessimism Removal (CPR): -0.197ns + Timing Exception: MultiCycle Path Setup -start 2 Hold -start 1 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.254 -0.407 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.685 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OSERDESRST) + 0.272 1.957 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OSERDESRST + net (fo=12, estimated) 0.304 2.262 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/po_oserdes_rst + OLOGIC_X1Y73 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[8].oserdes_dq_.sdr.oserdes_dq_i/RST + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.268 -0.653 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.488 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.576 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, estimated) 0.197 1.773 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y73 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[8].oserdes_dq_.sdr.oserdes_dq_i/CLKDIV + clock pessimism 0.197 1.970 + OLOGIC_X1Y73 OSERDESE2 (Hold_oserdese2_CLKDIV_RST) + 0.559 2.529 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[8].oserdes_dq_.sdr.oserdes_dq_i + ------------------------------------------------------------------- + required time -2.529 + arrival time 2.262 + ------------------------------------------------------------------- + slack -0.268 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_2 + To Clock: oserdes_clkdiv_2 + +Setup : 0 Failing Endpoints, Worst Slack 2.105ns, Total Violation 0.000ns +Hold : 10 Failing Endpoints, Worst Slack -0.274ns, Total Violation -2.156ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 2.105ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_2 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clkdiv_2 rise@6.000ns - oserdes_clk_2 rise@3.000ns) + Data Path Delay: 0.338ns (logic 0.338ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.148ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.271ns = ( 7.271 - 6.000 ) + Source Clock Delay (SCD): 1.793ns = ( 4.793 - 3.000 ) + Clock Pessimism Removal (CPR): 0.670ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.081ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_2 rise edge) + 3.000 3.000 r + E3 0.000 3.000 r CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 4.482 r input_clock/O + net (fo=1, unplaced) 0.584 5.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -0.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 0.758 sys_raw + BUFG (Prop_bufg_I_O) 0.096 0.854 r sys_buffer/O + net (fo=1, unplaced) 0.803 1.657 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 1.745 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.614 2.359 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 4.793 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.338 5.131 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/RDENABLE + net (fo=1, estimated) 0.000 5.131 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/po_rd_enable + OUT_FIFO_X1Y6 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_2 rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, unplaced) 0.439 7.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 2.470 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 3.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 3.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 4.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 4.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.583 4.752 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 7.123 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 7.271 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, estimated) 0.000 7.271 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/oserdes_clkdiv + OUT_FIFO_X1Y6 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + clock pessimism 0.670 7.941 + clock uncertainty -0.054 7.887 + OUT_FIFO_X1Y6 OUT_FIFO (Setup_out_fifo_RDCLK_RDEN) + -0.651 7.236 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo + ------------------------------------------------------------------- + required time 7.236 + arrival time -5.131 + ------------------------------------------------------------------- + slack 2.105 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (VIOLATED) : -0.274ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/RST + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_2 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_2 rise@0.000ns - oserdes_clk_2 rise@0.000ns) + Data Path Delay: 0.574ns (logic 0.272ns (47.403%) route 0.302ns (52.597%)) + Logic Levels: 0 + Clock Path Skew: 0.289ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.781ns + Source Clock Delay (SCD): 1.690ns + Clock Pessimism Removal (CPR): -0.197ns + Timing Exception: MultiCycle Path Setup -start 2 Hold -start 1 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.259 -0.402 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.690 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OSERDESRST) + 0.272 1.962 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OSERDESRST + net (fo=10, estimated) 0.302 2.264 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/po_oserdes_rst + OLOGIC_X1Y77 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/RST + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.272 -0.648 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.493 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.581 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, estimated) 0.201 1.781 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y77 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV + clock pessimism 0.197 1.979 + OLOGIC_X1Y77 OSERDESE2 (Hold_oserdese2_CLKDIV_RST) + 0.559 2.538 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i + ------------------------------------------------------------------- + required time -2.538 + arrival time 2.264 + ------------------------------------------------------------------- + slack -0.274 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_3 + To Clock: oserdes_clkdiv_3 + +Setup : 0 Failing Endpoints, Worst Slack 2.105ns, Total Violation 0.000ns +Hold : 10 Failing Endpoints, Worst Slack -0.197ns, Total Violation -1.058ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 2.105ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_3 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clkdiv_3 rise@6.000ns - oserdes_clk_3 rise@3.000ns) + Data Path Delay: 0.338ns (logic 0.338ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.148ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.260ns = ( 7.260 - 6.000 ) + Source Clock Delay (SCD): 1.782ns = ( 4.782 - 3.000 ) + Clock Pessimism Removal (CPR): 0.669ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.081ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_3 rise edge) + 3.000 3.000 r + E3 0.000 3.000 r CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 4.482 r input_clock/O + net (fo=1, unplaced) 0.584 5.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -0.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 0.758 sys_raw + BUFG (Prop_bufg_I_O) 0.096 0.854 r sys_buffer/O + net (fo=1, unplaced) 0.803 1.657 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 1.745 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.603 2.348 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 4.782 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.338 5.120 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/RDENABLE + net (fo=1, estimated) 0.000 5.120 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/po_rd_enable + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_3 rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, unplaced) 0.439 7.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 2.470 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 3.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 3.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 4.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 4.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.573 4.742 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 7.112 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 7.260 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, estimated) 0.000 7.260 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/oserdes_clkdiv + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + clock pessimism 0.669 7.930 + clock uncertainty -0.054 7.876 + OUT_FIFO_X1Y7 OUT_FIFO (Setup_out_fifo_RDCLK_RDEN) + -0.651 7.225 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo + ------------------------------------------------------------------- + required time 7.225 + arrival time -5.120 + ------------------------------------------------------------------- + slack 2.105 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (VIOLATED) : -0.197ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[1].oserdes_dq_.ddr.oserdes_dq_i/RST + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_3 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_3 rise@0.000ns - oserdes_clk_3 rise@0.000ns) + Data Path Delay: 0.658ns (logic 0.272ns (41.330%) route 0.386ns (58.670%)) + Logic Levels: 0 + Clock Path Skew: 0.296ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.784ns + Source Clock Delay (SCD): 1.685ns + Clock Pessimism Removal (CPR): -0.197ns + Timing Exception: MultiCycle Path Setup -start 2 Hold -start 1 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.254 -0.407 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.685 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OSERDESRST) + 0.272 1.957 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OSERDESRST + net (fo=10, estimated) 0.386 2.343 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/po_oserdes_rst + OLOGIC_X1Y88 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[1].oserdes_dq_.ddr.oserdes_dq_i/RST + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.268 -0.653 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.488 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.576 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, estimated) 0.208 1.784 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y88 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[1].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV + clock pessimism 0.197 1.981 + OLOGIC_X1Y88 OSERDESE2 (Hold_oserdese2_CLKDIV_RST) + 0.559 2.540 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[1].oserdes_dq_.ddr.oserdes_dq_i + ------------------------------------------------------------------- + required time -2.540 + arrival time 2.343 + ------------------------------------------------------------------- + slack -0.197 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: core_raw + To Clock: clk_pll_i + +Setup : 0 Failing Endpoints, Worst Slack 38.968ns, Total Violation 0.000ns +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 38.968ns (required time - arrival time) + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: clk_pll_i + Path Type: Setup (Max at Slow Process Corner) + Requirement: 40.000ns (MaxDelay Path 40.000ns) + Data Path Delay: 0.812ns (logic 0.478ns (58.867%) route 0.334ns (41.133%)) + Logic Levels: 0 + Timing Exception: MaxDelay Path 40.000ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + 0.000 0.000 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + FDRE (Prop_fdre_C_Q) 0.478 0.478 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, unplaced) 0.334 0.812 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[0] + FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + ------------------------------------------------------------------- ------------------- + + max delay 40.000 40.000 + FDRE (Setup_fdre_C_D) -0.220 39.780 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + ------------------------------------------------------------------- + required time 39.780 + arrival time -0.812 + ------------------------------------------------------------------- + slack 38.968 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: ref_raw + To Clock: clk_pll_i + +Setup : 0 Failing Endpoints, Worst Slack 19.759ns, Total Violation 0.000ns +Hold : 12 Failing Endpoints, Worst Slack -1.631ns, Total Violation -19.568ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 19.759ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[0]/C + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[0]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: clk_pll_i + Path Type: Setup (Max at Fast Process Corner) + Requirement: 20.000ns (MaxDelay Path 20.000ns) + Data Path Delay: 0.331ns (logic 0.183ns (55.254%) route 0.148ns (44.746%)) + Logic Levels: 0 + Clock Path Skew: 0.454ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.316ns + Source Clock Delay (SCD): -1.070ns + Clock Pessimism Removal (CPR): -0.301ns + Clock Uncertainty: 0.245ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.178ns + Timing Exception: MaxDelay Path 20.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -2.411 -1.715 r clock_mmcm/CLKOUT2 + net (fo=1, unplaced) 0.356 -1.358 ref_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r ref_buffer/O + net (fo=67, unplaced) 0.259 -1.070 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/clk_ref_i + FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[0]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.183 -0.887 r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[0]/Q + net (fo=1, unplaced) 0.148 -0.739 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_lcl[0] + FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[0]/D + ------------------------------------------------------------------- ------------------- + + max delay 20.000 20.000 + E3 0.000 20.000 r CLK100MHZ (IN) + net (fo=0) 0.000 20.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 20.250 r input_clock/O + net (fo=1, unplaced) 0.114 20.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 18.586 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 18.925 sys_raw + BUFG (Prop_bufg_I_O) 0.026 18.951 r sys_buffer/O + net (fo=1, unplaced) 0.338 19.289 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 19.339 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.114 19.453 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.020 19.473 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.338 19.811 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -0.703 19.109 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, unplaced) 0.338 19.447 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFG (Prop_bufg_I_O) 0.026 19.473 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=6179, unplaced) 0.211 19.684 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r5_reg[11]_0 + FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[0]/C + clock pessimism -0.301 19.383 + clock uncertainty -0.245 19.138 + FDRE (Setup_fdre_C_D) -0.119 19.019 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[0] + ------------------------------------------------------------------- + required time 19.019 + arrival time 0.739 + ------------------------------------------------------------------- + slack 19.759 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (VIOLATED) : -1.631ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[0]/C + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[0]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: clk_pll_i + Path Type: Hold (Min at Slow Process Corner) + Requirement: 0.000ns (clk_pll_i rise@0.000ns - ref_raw rise@0.000ns) + Data Path Delay: 0.702ns (logic 0.385ns (54.820%) route 0.317ns (45.180%)) + Logic Levels: 0 + Clock Path Skew: 2.011ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.259ns + Source Clock Delay (SCD): -2.238ns + Clock Pessimism Removal (CPR): 0.485ns + Clock Uncertainty: 0.245ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.178ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, unplaced) 0.439 1.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -5.381 -3.530 r clock_mmcm/CLKOUT2 + net (fo=1, unplaced) 0.763 -2.768 ref_raw + BUFG (Prop_bufg_I_O) 0.091 -2.677 r ref_buffer/O + net (fo=67, unplaced) 0.439 -2.238 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/clk_ref_i + FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[0]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.385 -1.853 r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[0]/Q + net (fo=1, unplaced) 0.317 -1.535 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_lcl[0] + FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.584 -0.671 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.127 -0.544 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.803 0.259 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.702 -1.443 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, unplaced) 0.803 -0.640 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFG (Prop_bufg_I_O) 0.096 -0.544 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=6179, unplaced) 0.803 0.259 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r5_reg[11]_0 + FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[0]/C + clock pessimism -0.485 -0.227 + clock uncertainty 0.245 0.018 + FDRE (Hold_fdre_C_D) 0.077 0.095 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[0] + ------------------------------------------------------------------- + required time -0.095 + arrival time -1.535 + ------------------------------------------------------------------- + slack -1.631 + + + + + +--------------------------------------------------------------------------------------------------- +Path Group: **async_default** +From Clock: clk_pll_i + To Clock: clk_pll_i + +Setup : 0 Failing Endpoints, Worst Slack 9.663ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.295ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 9.663ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__8/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n_reg/CLR + (recovery check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 12.000ns (clk_pll_i rise@12.000ns - clk_pll_i rise@0.000ns) + Data Path Delay: 1.773ns (logic 0.773ns (43.598%) route 1.000ns (56.402%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.653ns = ( 11.347 - 12.000 ) + Source Clock Delay (SCD): 0.259ns + Clock Pessimism Removal (CPR): 0.767ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.584 -0.671 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.127 -0.544 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.803 0.259 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.702 -1.443 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, unplaced) 0.803 -0.640 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFG (Prop_bufg_I_O) 0.096 -0.544 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=6179, unplaced) 0.803 0.259 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__8/C + ------------------------------------------------------------------- ------------------- + FDPE (Prop_fdpe_C_Q) 0.478 0.737 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__8/Q + net (fo=1, unplaced) 0.311 1.048 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__8_n_0 + LUT1 (Prop_lut1_I0_O) 0.295 1.343 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_inst_rep__7/O + net (fo=47, unplaced) 0.689 2.032 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/calib_ctl_wren_reg_7 + FDCE f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, unplaced) 0.439 13.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 8.470 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 9.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 9.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 10.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 10.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.439 10.608 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.081 10.689 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.763 11.452 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.616 9.835 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, unplaced) 0.763 10.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFG (Prop_bufg_I_O) 0.091 10.689 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=6179, unplaced) 0.658 11.347 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg[14]_0 + FDCE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n_reg/C + clock pessimism 0.767 12.114 + clock uncertainty -0.067 12.046 + FDCE (Recov_fdce_C_CLR) -0.352 11.694 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n_reg + ------------------------------------------------------------------- + required time 11.694 + arrival time -2.032 + ------------------------------------------------------------------- + slack 9.663 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.295ns (arrival time - required time) + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]/CLR + (removal check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (clk_pll_i rise@0.000ns - clk_pll_i rise@0.000ns) + Data Path Delay: 0.299ns (logic 0.147ns (49.136%) route 0.152ns (50.864%)) + Logic Levels: 0 + Clock Path Skew: 0.145ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.316ns + Clock Pessimism Removal (CPR): -0.091ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.114 -0.547 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.020 -0.527 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.338 -0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -0.703 -0.891 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, unplaced) 0.338 -0.553 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFG (Prop_bufg_I_O) 0.026 -0.527 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=6179, unplaced) 0.211 -0.316 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/dest_clk + FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + FDPE (Prop_fdpe_C_Q) 0.147 -0.169 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/Q + net (fo=3, unplaced) 0.152 -0.017 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.rst_rd_reg2 + FDCE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.259 -0.661 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.043 -0.618 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.356 -0.262 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -0.741 -1.003 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, unplaced) 0.356 -0.647 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFG (Prop_bufg_I_O) 0.029 -0.618 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=6179, unplaced) 0.356 -0.262 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/m_aclk + FDCE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]/C + clock pessimism 0.091 -0.171 + FDCE (Remov_fdce_C_CLR) -0.141 -0.312 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0] + ------------------------------------------------------------------- + required time 0.312 + arrival time -0.017 + ------------------------------------------------------------------- + slack 0.295 + + + + + +--------------------------------------------------------------------------------------------------- +Path Group: **async_default** +From Clock: core_raw + To Clock: core_raw + +Setup : 0 Failing Endpoints, Worst Slack 34.624ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.295ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 34.624ns (required time - arrival time) + Source: reset_count_reg[10]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: platform/chip/system/clint_domain/intsource/reg_0/reg_0_reg[0]/CLR + (recovery check against rising-edge clock core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 40.000ns (core_raw rise@40.000ns - core_raw rise@0.000ns) + Data Path Delay: 4.788ns (logic 1.269ns (26.504%) route 3.519ns (73.496%)) + Logic Levels: 5 (LUT2=1 LUT4=2 LUT5=1 LUT6=1) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.238ns = ( 37.762 - 40.000 ) + Source Clock Delay (SCD): -1.562ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.091ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.111 -3.045 r clock_mmcm/CLKOUT0 + net (fo=1, unplaced) 0.803 -2.242 core_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r core_buffer/O + net (fo=35560, unplaced) 0.584 -1.562 clk + FDRE r reset_count_reg[10]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.478 -1.084 r reset_count_reg[10]/Q + net (fo=2, unplaced) 0.774 -0.310 platform/normalizer/reset_count_reg[10] + LUT4 (Prop_lut4_I1_O) 0.295 -0.015 f platform/normalizer/reset_count[0]_i_7/O + net (fo=1, unplaced) 0.449 0.434 platform/normalizer/reset_count[0]_i_7_n_0 + LUT5 (Prop_lut5_I4_O) 0.124 0.558 f platform/normalizer/reset_count[0]_i_5/O + net (fo=1, unplaced) 0.449 1.007 platform/normalizer/reset_count[0]_i_5_n_0 + LUT6 (Prop_lut6_I5_O) 0.124 1.131 f platform/normalizer/reset_count[0]_i_2/O + net (fo=21, unplaced) 0.510 1.641 platform/normalizer/sel + LUT4 (Prop_lut4_I3_O) 0.124 1.765 f platform/normalizer/FSM_sequential_state[2]_i_1/O + net (fo=900, unplaced) 0.589 2.354 platform/loader/cpu_run_reg_inv_20 + LUT2 (Prop_lut2_I0_O) 0.124 2.478 f platform/loader/in_pipe_v_i_1__0/O + net (fo=3765, unplaced) 0.748 3.226 platform/chip/system/clint_domain/intsource/reg_0/cpu_reset + FDCE f platform/chip/system/clint_domain/intsource/reg_0/reg_0_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 40.000 40.000 r + E3 0.000 40.000 r CLK100MHZ (IN) + net (fo=0) 0.000 40.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r input_clock/O + net (fo=1, unplaced) 0.439 41.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.381 36.470 r clock_mmcm/CLKOUT0 + net (fo=1, unplaced) 0.763 37.232 core_raw + BUFG (Prop_bufg_I_O) 0.091 37.323 r core_buffer/O + net (fo=35560, unplaced) 0.439 37.762 platform/chip/system/clint_domain/intsource/reg_0/clk + FDCE r platform/chip/system/clint_domain/intsource/reg_0/reg_0_reg[0]/C + clock pessimism 0.531 38.293 + clock uncertainty -0.091 38.202 + FDCE (Recov_fdce_C_CLR) -0.352 37.850 platform/chip/system/clint_domain/intsource/reg_0/reg_0_reg[0] + ------------------------------------------------------------------- + required time 37.850 + arrival time -3.226 + ------------------------------------------------------------------- + slack 34.624 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.295ns (arrival time - required time) + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/C + (rising edge-triggered cell FDPE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]/CLR + (removal check against rising-edge clock core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (core_raw rise@0.000ns - core_raw rise@0.000ns) + Data Path Delay: 0.299ns (logic 0.147ns (49.136%) route 0.152ns (50.864%)) + Logic Levels: 0 + Clock Path Skew: 0.145ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -1.070ns + Source Clock Delay (SCD): -0.935ns + Clock Pessimism Removal (CPR): -0.280ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.777 -1.414 r clock_mmcm/CLKOUT0 + net (fo=1, unplaced) 0.338 -1.075 core_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r core_buffer/O + net (fo=35560, unplaced) 0.114 -0.935 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/dest_clk + FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + FDPE (Prop_fdpe_C_Q) 0.147 -0.788 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/Q + net (fo=3, unplaced) 0.152 -0.636 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.rst_rd_reg2 + FDCE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.411 -1.715 r clock_mmcm/CLKOUT0 + net (fo=1, unplaced) 0.356 -1.358 core_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r core_buffer/O + net (fo=35560, unplaced) 0.259 -1.070 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/s_aclk + FDCE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]/C + clock pessimism 0.280 -0.790 + FDCE (Remov_fdce_C_CLR) -0.141 -0.931 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0] + ------------------------------------------------------------------- + required time 0.931 + arrival time -0.636 + ------------------------------------------------------------------- + slack 0.295 + + + + + +--------------------------------------------------------------------------------------------------- +Path Group: **default** +From Clock: clk_pll_i + To Clock: + +Setup : 0 Failing Endpoints, Worst Slack 3.113ns, Total Violation 0.000ns +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 3.113ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/RESET + Path Group: **default** + Path Type: Max at Slow Process Corner + Requirement: 5.000ns (MaxDelay Path 5.000ns) + Data Path Delay: 1.887ns (logic 0.773ns (40.968%) route 1.114ns (59.032%)) + Logic Levels: 1 (LUT1=1) + Output Delay: 0.000ns + Timing Exception: MaxDelay Path 5.000ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + 0.000 0.000 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + FDPE (Prop_fdpe_C_Q) 0.478 0.478 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/Q + net (fo=1, unplaced) 0.311 0.789 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep_n_0 + LUT1 (Prop_lut1_I0_O) 0.295 1.084 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_inst/O + net (fo=50, unplaced) 0.803 1.887 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i_0 + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/RESET + ------------------------------------------------------------------- ------------------- + + max delay 5.000 5.000 + PHY_CONTROL_X1Y1 PHY_CONTROL 0.000 5.000 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i + output delay -0.000 5.000 + ------------------------------------------------------------------- + required time 5.000 + arrival time -1.887 + ------------------------------------------------------------------- + slack 3.113 + + + + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/synth-utilization.rpt b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/synth-utilization.rpt new file mode 100644 index 0000000..36d7378 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/synth-utilization.rpt @@ -0,0 +1,233 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Tue Oct 13 01:26:35 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_utilization -file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/synth-utilization.rpt +| Design : toy_a7_top +| Device : xc7a100tcsg324-1 +| Speed File : -1 +| Design State : Synthesized +---------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++----------------------------+-------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++----------------------------+-------+-------+------------+-----------+-------+ +| Slice LUTs* | 57555 | 0 | 0 | 63400 | 90.78 | +| LUT as Logic | 53496 | 0 | 0 | 63400 | 84.38 | +| LUT as Memory | 4059 | 0 | 0 | 19000 | 21.36 | +| LUT as Distributed RAM | 3680 | 0 | | | | +| LUT as Shift Register | 379 | 0 | | | | +| Slice Registers | 34174 | 0 | 0 | 126800 | 26.95 | +| Register as Flip Flop | 34174 | 0 | 0 | 126800 | 26.95 | +| Register as Latch | 0 | 0 | 0 | 126800 | 0.00 | +| F7 Muxes | 689 | 0 | 0 | 31700 | 2.17 | +| F8 Muxes | 112 | 0 | 0 | 15850 | 0.71 | ++----------------------------+-------+-------+------------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. +Warning! LUT value is adjusted to account for LUT combining. +Warning! For any ECO changes, please run place_design if there are unplaced instances + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 194 | Yes | - | Set | +| 140 | Yes | - | Reset | +| 580 | Yes | Set | - | +| 33260 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++-------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------------+------+-------+------------+-----------+-------+ +| Block RAM Tile | 31 | 0 | 0 | 135 | 22.96 | +| RAMB36/FIFO* | 27 | 0 | 0 | 135 | 20.00 | +| RAMB36E1 only | 27 | | | | | +| RAMB18 | 8 | 0 | 0 | 270 | 2.96 | +| RAMB18E1 only | 8 | | | | | ++-------------------+------+-------+------------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++----------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++----------------+------+-------+------------+-----------+-------+ +| DSPs | 117 | 0 | 0 | 240 | 48.75 | +| DSP48E1 only | 117 | | | | | ++----------------+------+-------+------------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-----------------------------+------+-------+------------+-----------+-------+ +| Bonded IOB | 61 | 61 | 0 | 210 | 29.05 | +| IOB Master Pads | 29 | | | | | +| IOB Slave Pads | 29 | | | | | +| Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 | +| PHY_CONTROL | 1 | 1 | 0 | 6 | 16.67 | +| PHASER_REF | 1 | 1 | 0 | 6 | 16.67 | +| OUT_FIFO | 4 | 4 | 0 | 24 | 16.67 | +| IN_FIFO | 2 | 2 | 0 | 24 | 8.33 | +| IDELAYCTRL | 1 | 0 | 0 | 6 | 16.67 | +| IBUFDS | 0 | 0 | 0 | 202 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 4 | 4 | 0 | 24 | 16.67 | +| PHASER_OUT_PHY only | 4 | 4 | | | | +| PHASER_IN/PHASER_IN_PHY | 2 | 2 | 0 | 24 | 8.33 | +| PHASER_IN_PHY only | 2 | 2 | | | | +| IDELAYE2/IDELAYE2_FINEDELAY | 16 | 16 | 0 | 300 | 5.33 | +| IDELAYE2 only | 16 | 16 | | | | +| ILOGIC | 16 | 16 | 0 | 210 | 7.62 | +| ISERDES | 16 | 16 | 0 | 210 | | +| OLOGIC | 46 | 46 | 0 | 210 | 21.90 | +| OUTFF_ODDR_Register | 3 | 3 | | | | +| TFF_ODDR_Register | 2 | 2 | | | | +| OSERDES | 43 | 43 | 0 | 210 | | ++-----------------------------+------+-------+------------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++------------+------+-------+------------+-----------+-------+ +| BUFGCTRL | 7 | 0 | 0 | 32 | 21.88 | +| BUFIO | 0 | 0 | 0 | 24 | 0.00 | +| MMCME2_ADV | 2 | 1 | 0 | 6 | 33.33 | +| PLLE2_ADV | 1 | 1 | 0 | 6 | 16.67 | +| BUFMRCE | 0 | 0 | 0 | 12 | 0.00 | +| BUFHCE | 1 | 0 | 0 | 96 | 1.04 | +| BUFR | 0 | 0 | 0 | 24 | 0.00 | ++------------+------+-------+------------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+------------+-----------+--------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------+------+-------+------------+-----------+--------+ +| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 | +| XADC | 1 | 0 | 0 | 1 | 100.00 | ++-------------+------+-------+------------+-----------+--------+ + + +7. Primitives +------------- + ++--------------------------+-------+---------------------+ +| Ref Name | Used | Functional Category | ++--------------------------+-------+---------------------+ +| FDRE | 33260 | Flop & Latch | +| LUT6 | 19737 | LUT | +| LUT5 | 13793 | LUT | +| LUT3 | 13255 | LUT | +| LUT4 | 11100 | LUT | +| RAMD32 | 5124 | Distributed Memory | +| LUT2 | 4864 | LUT | +| CARRY4 | 2074 | CarryLogic | +| RAMS32 | 1782 | Distributed Memory | +| LUT1 | 1266 | LUT | +| MUXF7 | 689 | MuxFx | +| FDSE | 580 | Flop & Latch | +| SRL16E | 245 | Distributed Memory | +| FDPE | 194 | Flop & Latch | +| FDCE | 140 | Flop & Latch | +| SRLC32E | 134 | Distributed Memory | +| DSP48E1 | 117 | Block Arithmetic | +| RAMD64E | 112 | Distributed Memory | +| MUXF8 | 112 | MuxFx | +| OSERDESE2 | 43 | IO | +| RAMS64E | 42 | Distributed Memory | +| OBUF | 33 | IO | +| RAMB36E1 | 27 | Block Memory | +| OBUFT | 18 | IO | +| ISERDESE2 | 16 | IO | +| IDELAYE2 | 16 | IO | +| IBUF_INTERMDISABLE | 16 | IO | +| RAMB18E1 | 8 | Block Memory | +| BUFG | 7 | Clock | +| ODDR | 5 | IO | +| PHASER_OUT_PHY | 4 | IO | +| OUT_FIFO | 4 | IO | +| OBUFTDS | 4 | IO | +| IBUFDS_INTERMDISABLE_INT | 4 | IO | +| IBUF | 4 | IO | +| INV | 3 | LUT | +| PHASER_IN_PHY | 2 | IO | +| OBUFDS | 2 | IO | +| MMCME2_ADV | 2 | Clock | +| IN_FIFO | 2 | IO | +| XADC | 1 | Others | +| PLLE2_ADV | 1 | Clock | +| PHY_CONTROL | 1 | IO | +| PHASER_REF | 1 | IO | +| IDELAYCTRL | 1 | IO | +| BUFH | 1 | Clock | ++--------------------------+-------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++-------------+------+ +| Ref Name | Used | ++-------------+------+ +| toy_axi_cdc | 1 | +| arty_ddr3 | 1 | ++-------------+------+ + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/vivado.jou b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/vivado.jou new file mode 100644 index 0000000..40f6dfc --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/vivado.jou @@ -0,0 +1,24 @@ +#----------------------------------------------------------- +# Vivado v2024.1 (64-bit) +# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024 +# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024 +# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024 +# Start of session at: Tue Oct 13 01:09:22 2026 +# Process ID: 533642 +# Current directory: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform +# Command line: vivado -mode batch -source /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/build_board.tcl -log /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/vivado.log -journal /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/vivado.jou -tclargs /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921 +# Log file: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/vivado.log +# Journal file: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/vivado.jou +# Running On :amax +# Platform :Ubuntu +# Operating System :Ubuntu 24.04 LTS +# Processor Detail :INTEL(R) XEON(R) GOLD 6542Y +# CPU Frequency :2495.797 MHz +# CPU Physical cores:48 +# CPU Logical cores :96 +# Host memory :540650 MB +# Swap memory :130443 MB +# Total Virtual :671094 MB +# Available Virtual :562344 MB +#----------------------------------------------------------- +source /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/build_board.tcl diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/vivado.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/vivado.log new file mode 100644 index 0000000..0626ac0 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/implementation/vivado.log @@ -0,0 +1,5914 @@ +#----------------------------------------------------------- +# Vivado v2024.1 (64-bit) +# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024 +# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024 +# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024 +# Start of session at: Tue Oct 13 01:09:22 2026 +# Process ID: 533642 +# Current directory: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform +# Command line: vivado -mode batch -source /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/build_board.tcl -log /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/vivado.log -journal /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/vivado.jou -tclargs /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921 +# Log file: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/vivado.log +# Journal file: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/vivado.jou +# Running On :amax +# Platform :Ubuntu +# Operating System :Ubuntu 24.04 LTS +# Processor Detail :INTEL(R) XEON(R) GOLD 6542Y +# CPU Frequency :2495.797 MHz +# CPU Physical cores:48 +# CPU Logical cores :96 +# Host memory :540650 MB +# Swap memory :130443 MB +# Total Virtual :671094 MB +# Available Virtual :562344 MB +#----------------------------------------------------------- +source /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/build_board.tcl +# set root [file dirname [file dirname [file normalize [info script]]]] +# cd $root +# if {[llength $argv]<1 || [llength $argv]>2} {error "Usage: build_board.tcl OUTPUT_DIRECTORY ?flash?"} +# set flash 0 +# if {[llength $argv]==2} { +# if {[lindex $argv 1] ne "flash"} {error "Second argument must be flash"} +# set flash 1 +# } +# set out [file normalize [lindex $argv 0]] +# file mkdir $out +# file mkdir $out/ip +# proc phase {name} { +# global out +# set f [open $out/phase.txt w];puts $f $name;close $f +# puts "BOARD_PHASE $name" +# } +# set_param general.maxThreads 8 +# phase CREATE_IP +BOARD_PHASE CREATE_IP +# create_project -in_memory -part xc7a100tcsg324-1 +# set_property target_language Verilog [current_project] +# create_ip -name mig_7series -vendor xilinx.com -library ip -version 4.2 -module_name arty_ddr3 -dir $out/ip +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data0/tools/Xilinx/Vivado/2024.1/data/ip'. +# set_property CONFIG.XML_INPUT_FILE $root/board/vendor/mig.prj [get_ips arty_ddr3] +INFO: [IP_Flow 19-3484] Absolute path of file '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/vendor/mig.prj' provided. It will be converted relative to IP Instance files '../../../../board/vendor/mig.prj' +INFO: [Device 21-403] Loading part xc7a100tcsg324-1 +INFO: [Device 21-9227] Part: xc7a100tcsg324-1 does not have CEAM library. +# create_ip -name axi_clock_converter -vendor xilinx.com -library ip -version 2.1 -module_name toy_axi_cdc -dir $out/ip +# set_property -dict {CONFIG.PROTOCOL AXI4 CONFIG.ADDR_WIDTH 28 CONFIG.DATA_WIDTH 128 CONFIG.ID_WIDTH 4 CONFIG.ACLK_ASYNC 1 CONFIG.SYNCHRONIZATION_STAGES 3} [get_ips toy_axi_cdc] +# generate_target all [get_ips] +INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'arty_ddr3'... +INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'arty_ddr3'... +INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'arty_ddr3'... +INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'arty_ddr3'... +INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'arty_ddr3'... +INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'toy_axi_cdc'... +INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'toy_axi_cdc'... +WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_ooc.xdc' +INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'toy_axi_cdc'... +INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'toy_axi_cdc'... +INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'toy_axi_cdc'... +generate_target: Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 2220.156 ; gain = 272.484 ; free physical = 194785 ; free virtual = 543731 +# report_ip_status -file $out/ip-status.rpt +# phase SYNTH_IP +BOARD_PHASE SYNTH_IP +# synth_ip [get_ips] +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data0/tools/Xilinx/Vivado/2024.1/data/ip'. +WARNING: [Vivado 12-13650] The IP file '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3.xci' has been moved from its original location, as a result the outputs for this IP will now be generated in '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3'. Alternatively a copy of the IP can be imported into the project using one of the 'import_ip' or 'import_files' commands. +Command: synth_design -top arty_ddr3 -part xc7a100tcsg324-1 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. +INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes +INFO: [Synth 8-7075] Helper process launched with PID 535585 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2658.754 ; gain = 416.715 ; free physical = 194057 ; free virtual = 543005 +--------------------------------------------------------------------------------- +WARNING: [Synth 8-10515] begin/end is required for generate-for in this mode of Verilog [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v:253] +INFO: [Synth 8-11241] undeclared symbol 'dbg_sel_po_incdec', assumed default net type 'wire' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:1223] +INFO: [Synth 8-11241] undeclared symbol 'dbg_po_f_inc', assumed default net type 'wire' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:1227] +INFO: [Synth 8-11241] undeclared symbol 'dbg_po_f_stg23_sel', assumed default net type 'wire' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:1228] +INFO: [Synth 8-11241] undeclared symbol 'dbg_po_f_dec', assumed default net type 'wire' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:1229] +INFO: [Synth 8-6157] synthesizing module 'arty_ddr3' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3.v:70] +INFO: [Synth 8-6157] synthesizing module 'arty_ddr3_mig' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:75] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_tempmon' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v:69] + Parameter TCQ bound to: 100 - type: integer + Parameter TEMP_MON_CONTROL bound to: INTERNAL - type: string + Parameter XADC_CLK_PERIOD bound to: 5000 - type: integer + Parameter tTEMPSAMPLE bound to: 10000000 - type: integer +INFO: [Synth 8-6157] synthesizing module 'XADC' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:143027] + Parameter INIT_40 bound to: 16'b0001000000000000 + Parameter INIT_41 bound to: 16'b0010111111111111 + Parameter INIT_42 bound to: 16'b0000100000000000 + Parameter INIT_48 bound to: 16'b0000000100000001 + Parameter INIT_49 bound to: 16'b0000000000000000 + Parameter INIT_4A bound to: 16'b0000000100000000 + Parameter INIT_4B bound to: 16'b0000000000000000 + Parameter INIT_4C bound to: 16'b0000000000000000 + Parameter INIT_4D bound to: 16'b0000000000000000 + Parameter INIT_4E bound to: 16'b0000000000000000 + Parameter INIT_4F bound to: 16'b0000000000000000 + Parameter INIT_50 bound to: 16'b1011010111101101 + Parameter INIT_51 bound to: 16'b0101011111100100 + Parameter INIT_52 bound to: 16'b1010000101000111 + Parameter INIT_53 bound to: 16'b1100101000110011 + Parameter INIT_54 bound to: 16'b1010100100111010 + Parameter INIT_55 bound to: 16'b0101001011000110 + Parameter INIT_56 bound to: 16'b1001010101010101 + Parameter INIT_57 bound to: 16'b1010111001001110 + Parameter INIT_58 bound to: 16'b0101100110011001 + Parameter INIT_5C bound to: 16'b0101000100010001 + Parameter SIM_DEVICE bound to: 7SERIES - type: string +INFO: [Synth 8-6155] done synthesizing module 'XADC' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:143027] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_tempmon' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v:69] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_iodelay_ctrl' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_iodelay_ctrl.v:80] + Parameter TCQ bound to: 100 - type: integer + Parameter IODELAY_GRP0 bound to: ARTY_DDR3_IODELAY_MIG0 - type: string + Parameter IODELAY_GRP1 bound to: ARTY_DDR3_IODELAY_MIG1 - type: string + Parameter REFCLK_TYPE bound to: NO_BUFFER - type: string + Parameter SYSCLK_TYPE bound to: NO_BUFFER - type: string + Parameter SYS_RST_PORT bound to: FALSE - type: string + Parameter RST_ACT_LOW bound to: 1 - type: integer + Parameter DIFF_TERM_REFCLK bound to: TRUE - type: string + Parameter FPGA_SPEED_GRADE bound to: 1 - type: integer + Parameter REF_CLK_MMCM_IODELAY_CTRL bound to: FALSE - type: string +INFO: [Synth 8-6157] synthesizing module 'IDELAYCTRL' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:75739] +INFO: [Synth 8-6155] done synthesizing module 'IDELAYCTRL' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:75739] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_iodelay_ctrl' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_iodelay_ctrl.v:80] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_clk_ibuf' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_clk_ibuf.v:68] + Parameter SYSCLK_TYPE bound to: NO_BUFFER - type: string + Parameter DIFF_TERM_SYSCLK bound to: TRUE - type: string +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_clk_ibuf' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_clk_ibuf.v:68] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_infrastructure' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:78] + Parameter TCQ bound to: 100 - type: integer + Parameter CLKIN_PERIOD bound to: 6000 - type: integer + Parameter nCK_PER_CLK bound to: 4 - type: integer + Parameter SYSCLK_TYPE bound to: NO_BUFFER - type: string + Parameter CLKFBOUT_MULT bound to: 8 - type: integer + Parameter DIVCLK_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT0_DIVIDE bound to: 2 - type: integer + Parameter CLKOUT1_DIVIDE bound to: 4 - type: integer + Parameter CLKOUT2_DIVIDE bound to: 64 - type: integer + Parameter CLKOUT3_DIVIDE bound to: 16 - type: integer + Parameter MMCM_VCO bound to: 666 - type: integer + Parameter MMCM_MULT_F bound to: 8 - type: integer + Parameter MMCM_DIVCLK_DIVIDE bound to: 1 - type: integer + Parameter RST_ACT_LOW bound to: 1 - type: integer + Parameter tCK bound to: 3000 - type: integer + Parameter MEM_TYPE bound to: DDR3 - type: string +INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82388] + Parameter BANDWIDTH bound to: HIGH - type: string + Parameter CLKFBOUT_MULT_F bound to: 8.000000 - type: double + Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double + Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKIN1_PERIOD bound to: 12.000000 - type: double + Parameter CLKOUT0_DIVIDE_F bound to: 16.000000 - type: double + Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT0_USE_FINE_PS bound to: TRUE - type: string + Parameter CLKOUT1_DIVIDE bound to: 4 - type: integer + Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT4_CASCADE bound to: FALSE - type: string + Parameter COMPENSATION bound to: BUF_IN - type: string + Parameter DIVCLK_DIVIDE bound to: 1 - type: integer + Parameter REF_JITTER1 bound to: 0.000000 - type: double + Parameter STARTUP_WAIT bound to: FALSE - type: string +INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82388] +INFO: [Synth 8-6157] synthesizing module 'BUFG' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951] +INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951] +INFO: [Synth 8-6157] synthesizing module 'PLLE2_ADV' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114750] + Parameter BANDWIDTH bound to: OPTIMIZED - type: string + Parameter CLKFBOUT_MULT bound to: 8 - type: integer + Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double + Parameter CLKIN1_PERIOD bound to: 6.000000 - type: double + Parameter CLKOUT0_DIVIDE bound to: 2 - type: integer + Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT1_DIVIDE bound to: 4 - type: integer + Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT2_DIVIDE bound to: 64 - type: integer + Parameter CLKOUT2_DUTY_CYCLE bound to: 0.062500 - type: double + Parameter CLKOUT2_PHASE bound to: 9.843750 - type: double + Parameter CLKOUT3_DIVIDE bound to: 16 - type: integer + Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT3_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT4_DIVIDE bound to: 8 - type: integer + Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT4_PHASE bound to: 168.750000 - type: double + Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT5_PHASE bound to: 0.000000 - type: double + Parameter COMPENSATION bound to: INTERNAL - type: string + Parameter DIVCLK_DIVIDE bound to: 1 - type: integer + Parameter REF_JITTER1 bound to: 0.010000 - type: double + Parameter REF_JITTER2 bound to: 0.010000 - type: double + Parameter STARTUP_WAIT bound to: FALSE - type: string +INFO: [Synth 8-6155] done synthesizing module 'PLLE2_ADV' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114750] +INFO: [Synth 8-6157] synthesizing module 'BUFH' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:2199] +INFO: [Synth 8-6155] done synthesizing module 'BUFH' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:2199] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_infrastructure' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:78] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_memc_ui_top_axi' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_memc_ui_top_axi.v:71] + Parameter TCQ bound to: 100 - type: integer + Parameter DDR3_VDD_OP_VOLT bound to: 135 - type: string + Parameter PAYLOAD_WIDTH bound to: 16 - type: integer + Parameter ADDR_CMD_MODE bound to: 1T - type: string + Parameter AL bound to: 0 - type: string + Parameter BANK_WIDTH bound to: 3 - type: integer + Parameter BM_CNT_WIDTH bound to: 2 - type: integer + Parameter BURST_MODE bound to: 8 - type: string + Parameter BURST_TYPE bound to: SEQ - type: string + Parameter CA_MIRROR bound to: OFF - type: string + Parameter CK_WIDTH bound to: 1 - type: integer + Parameter CL bound to: 5 - type: integer + Parameter COL_WIDTH bound to: 10 - type: integer + Parameter CMD_PIPE_PLUS1 bound to: ON - type: string + Parameter CS_WIDTH bound to: 1 - type: integer + Parameter CKE_WIDTH bound to: 1 - type: integer + Parameter CWL bound to: 5 - type: integer + Parameter DATA_WIDTH bound to: 16 - type: integer + Parameter DATA_BUF_ADDR_WIDTH bound to: 5 - type: integer + Parameter DM_WIDTH bound to: 2 - type: integer + Parameter DQ_CNT_WIDTH bound to: 4 - type: integer + Parameter DQ_WIDTH bound to: 16 - type: integer + Parameter DQS_CNT_WIDTH bound to: 1 - type: integer + Parameter DQS_WIDTH bound to: 2 - type: integer + Parameter DRAM_TYPE bound to: DDR3 - type: string + Parameter DRAM_WIDTH bound to: 8 - type: integer + Parameter ECC bound to: OFF - type: string + Parameter ECC_WIDTH bound to: 0 - type: integer + Parameter ECC_TEST bound to: OFF - type: string + Parameter MC_ERR_ADDR_WIDTH bound to: 28 - type: integer + Parameter MASTER_PHY_CTL bound to: 0 - type: integer + Parameter nAL bound to: 0 - type: integer + Parameter nBANK_MACHS bound to: 4 - type: integer + Parameter nCK_PER_CLK bound to: 4 - type: integer + Parameter nCS_PER_RANK bound to: 1 - type: integer + Parameter ORDERING bound to: NORM - type: string + Parameter IBUF_LPWR_MODE bound to: OFF - type: string + Parameter BANK_TYPE bound to: HR_IO - type: string + Parameter DATA_IO_PRIM_TYPE bound to: HR_LP - type: string + Parameter DATA_IO_IDLE_PWRDWN bound to: ON - type: string + Parameter IODELAY_GRP0 bound to: ARTY_DDR3_IODELAY_MIG0 - type: string + Parameter IODELAY_GRP1 bound to: ARTY_DDR3_IODELAY_MIG1 - type: string + Parameter FPGA_SPEED_GRADE bound to: 1 - type: integer + Parameter OUTPUT_DRV bound to: LOW - type: string + Parameter REG_CTRL bound to: OFF - type: string + Parameter RTT_NOM bound to: 40 - type: string + Parameter RTT_WR bound to: OFF - type: string + Parameter STARVE_LIMIT bound to: 2 - type: integer + Parameter tCK bound to: 3000 - type: integer + Parameter tCKE bound to: 5625 - type: integer + Parameter tFAW bound to: 45000 - type: integer + Parameter tPRDI bound to: 1000000 - type: integer + Parameter tRAS bound to: 36000 - type: integer + Parameter tRCD bound to: 13500 - type: integer + Parameter tREFI bound to: 7800000 - type: integer + Parameter tRFC bound to: 160000 - type: integer + Parameter tRP bound to: 13500 - type: integer + Parameter tRRD bound to: 7500 - type: integer + Parameter tRTP bound to: 7500 - type: integer + Parameter tWTR bound to: 7500 - type: integer + Parameter tZQI bound to: 128000000 - type: integer + Parameter tZQCS bound to: 64 - type: integer + Parameter USER_REFRESH bound to: OFF - type: string + Parameter TEMP_MON_EN bound to: ON - type: string + Parameter WRLVL bound to: ON - type: string + Parameter DEBUG_PORT bound to: OFF - type: string + Parameter CAL_WIDTH bound to: HALF - type: string + Parameter RANK_WIDTH bound to: 1 - type: integer + Parameter RANKS bound to: 1 - type: integer + Parameter ODT_WIDTH bound to: 1 - type: integer + Parameter ROW_WIDTH bound to: 14 - type: integer + Parameter ADDR_WIDTH bound to: 28 - type: integer + Parameter APP_MASK_WIDTH bound to: 16 - type: integer + Parameter APP_DATA_WIDTH bound to: 128 - type: integer + Parameter BYTE_LANES_B0 bound to: 4'b1111 + Parameter BYTE_LANES_B1 bound to: 4'b0000 + Parameter BYTE_LANES_B2 bound to: 4'b0000 + Parameter BYTE_LANES_B3 bound to: 4'b0000 + Parameter BYTE_LANES_B4 bound to: 4'b0000 + Parameter DATA_CTL_B0 bound to: 4'b1100 + Parameter DATA_CTL_B1 bound to: 4'b0000 + Parameter DATA_CTL_B2 bound to: 4'b0000 + Parameter DATA_CTL_B3 bound to: 4'b0000 + Parameter DATA_CTL_B4 bound to: 4'b0000 + Parameter PHY_0_BITLANES bound to: 48'b001111111110001111111110111111111111101111111111 + Parameter PHY_1_BITLANES bound to: 48'b000000000000000000000000000000000000000000000000 + Parameter PHY_2_BITLANES bound to: 48'b000000000000000000000000000000000000000000000000 + Parameter CK_BYTE_MAP bound to: 144'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter ADDR_MAP bound to: 192'b000000000000000000000000000000000000000000000010000000000100000000001001000000000111000000000001000000000101000000000110000000000011000000010000000000010010000000010100000000010001000000011010 + Parameter BANK_MAP bound to: 36'b000000011011000000010111000000010011 + Parameter CAS_MAP bound to: 12'b000000010101 + Parameter CKE_ODT_BYTE_MAP bound to: 8'b00000000 + Parameter CKE_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011001 + Parameter ODT_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000 + Parameter CKE_ODT_AUX bound to: FALSE - type: string + Parameter CS_MAP bound to: 120'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001011 + Parameter PARITY_MAP bound to: 12'b000000000000 + Parameter RAS_MAP bound to: 12'b000000010110 + Parameter WE_MAP bound to: 12'b000000011000 + Parameter DQS_BYTE_MAP bound to: 144'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000011 + Parameter DATA0_MAP bound to: 96'b000000110100000000110010000000111000000000110101000000110001000000110111000000110110000000110011 + Parameter DATA1_MAP bound to: 96'b000000100011000000100110000000100010000000101000000000100101000000100111000000100001000000100100 + Parameter DATA2_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA3_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA4_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA5_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA6_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA7_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA8_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA9_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA10_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA11_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA12_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA13_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA14_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA15_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA16_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA17_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter MASK0_MAP bound to: 108'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101001000000111001 + Parameter MASK1_MAP bound to: 108'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter SLOT_0_CONFIG bound to: 8'b00000001 + Parameter SLOT_1_CONFIG bound to: 8'b00000000 + Parameter MEM_ADDR_ORDER bound to: BANK_ROW_COLUMN - type: string + Parameter CALIB_ROW_ADD bound to: 16'b0000000000000000 + Parameter CALIB_COL_ADD bound to: 12'b000000000000 + Parameter CALIB_BA_ADD bound to: 3'b000 + Parameter SIM_BYPASS_INIT_CAL bound to: OFF - type: string + Parameter REFCLK_FREQ bound to: 200.000000 - type: double + Parameter USE_CS_PORT bound to: 1 - type: integer + Parameter USE_DM_PORT bound to: 1 - type: integer + Parameter USE_ODT_PORT bound to: 1 - type: integer + Parameter IDELAY_ADJ bound to: OFF - type: string + Parameter FINE_PER_BIT bound to: OFF - type: string + Parameter CENTER_COMP_MODE bound to: OFF - type: string + Parameter PI_VAL_ADJ bound to: OFF - type: string + Parameter SKIP_CALIB bound to: FALSE - type: string + Parameter TAPSPERKCLK bound to: 112 - type: integer + Parameter C_S_AXI_ID_WIDTH bound to: 4 - type: integer + Parameter C_S_AXI_ADDR_WIDTH bound to: 28 - type: integer + Parameter C_S_AXI_DATA_WIDTH bound to: 128 - type: integer + Parameter C_S_AXI_SUPPORTS_NARROW_BURST bound to: 0 - type: integer + Parameter C_RD_WR_ARB_ALGORITHM bound to: RD_PRI_REG - type: string + Parameter C_S_AXI_REG_EN0 bound to: 20'b00000000000000000000 + Parameter C_S_AXI_REG_EN1 bound to: 20'b00000000000000000000 + Parameter C_S_AXI_CTRL_ADDR_WIDTH bound to: 32 - type: integer + Parameter C_S_AXI_CTRL_DATA_WIDTH bound to: 32 - type: integer + Parameter C_S_AXI_BASEADDR bound to: 0 - type: integer + Parameter C_ECC_ONOFF_RESET_VALUE bound to: 1 - type: integer + Parameter C_ECC_CE_COUNTER_WIDTH bound to: 8 - type: integer + Parameter FPGA_VOLT_TYPE bound to: N - type: string +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_mem_intfc' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_mem_intfc.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_mc' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v:73] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_rank_mach' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_mach.v:71] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_rank_cntrl' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v:79] +INFO: [Synth 8-6157] synthesizing module 'SRLC32E' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:137412] +INFO: [Synth 8-6155] done synthesizing module 'SRLC32E' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:137412] +WARNING: [Synth 8-567] referenced signal 'periodic_rd_generation.periodic_rd_timer_one' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v:509] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_rank_cntrl' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v:79] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_rank_common' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_common.v:72] +WARNING: [Synth 8-567] referenced signal 'zq_cntrl.zq_tick' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_common.v:172] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_round_robin_arb' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_round_robin_arb' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_round_robin_arb__parameterized0' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_round_robin_arb__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_rank_common' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_common.v:72] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_rank_mach' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_mach.v:71] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_mach' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_mach.v:72] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_compare' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v:74] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_compare' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v:74] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_state' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_queue' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_cntrl' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized0' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state__parameterized0' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_state__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue__parameterized0' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_queue__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized1' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state__parameterized1' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_state__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue__parameterized1' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_queue__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized2' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state__parameterized2' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_state__parameterized2' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue__parameterized2' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_queue__parameterized2' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized2' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_common' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_common.v:73] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_common' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_common.v:73] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_arb_mux' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_mux.v:69] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_arb_row_col' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v:83] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_round_robin_arb__parameterized1' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_round_robin_arb__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_arb_row_col' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v:83] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_arb_select' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:75] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_arb_select' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:75] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_arb_mux' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_mux.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_mach' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_mach.v:72] +WARNING: [Synth 8-7071] port 'idle' of module 'mig_7series_v4_2_bank_mach' is unconnected for instance 'bank_mach0' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v:670] +WARNING: [Synth 8-7023] instance 'bank_mach0' of module 'mig_7series_v4_2_bank_mach' has 74 connections declared, but only 73 given [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v:670] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_col_mach' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_col_mach.v:88] +INFO: [Synth 8-6157] synthesizing module 'RAM32M' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:129077] +INFO: [Synth 8-6155] done synthesizing module 'RAM32M' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:129077] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_col_mach' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_col_mach.v:88] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_mc' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v:73] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_top' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_top.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_mc_phy_wrapper' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:71] +INFO: [Synth 8-6157] synthesizing module 'OBUF' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96458] +INFO: [Synth 8-6155] done synthesizing module 'OBUF' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96458] +INFO: [Synth 8-6157] synthesizing module 'OBUFT' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96846] +INFO: [Synth 8-6155] done synthesizing module 'OBUFT' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96846] +INFO: [Synth 8-6157] synthesizing module 'IOBUF_INTERMDISABLE' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:79002] +INFO: [Synth 8-6155] done synthesizing module 'IOBUF_INTERMDISABLE' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:79002] +INFO: [Synth 8-6157] synthesizing module 'IOBUFDS_INTERMDISABLE' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:78516] +INFO: [Synth 8-6155] done synthesizing module 'IOBUFDS_INTERMDISABLE' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:78516] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +WARNING: [Synth 8-7071] port 'afull' of module 'mig_7series_v4_2_ddr_of_pre_fifo' is unconnected for instance 'phy_ctl_pre_fifo_0' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1428] +WARNING: [Synth 8-7023] instance 'phy_ctl_pre_fifo_0' of module 'mig_7series_v4_2_ddr_of_pre_fifo' has 8 connections declared, but only 7 given [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1428] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo__parameterized0' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +WARNING: [Synth 8-7071] port 'afull' of module 'mig_7series_v4_2_ddr_of_pre_fifo' is unconnected for instance 'phy_ctl_pre_fifo_1' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1445] +WARNING: [Synth 8-7023] instance 'phy_ctl_pre_fifo_1' of module 'mig_7series_v4_2_ddr_of_pre_fifo' has 8 connections declared, but only 7 given [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1445] +WARNING: [Synth 8-7071] port 'afull' of module 'mig_7series_v4_2_ddr_of_pre_fifo' is unconnected for instance 'phy_ctl_pre_fifo_2' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1462] +WARNING: [Synth 8-7023] instance 'phy_ctl_pre_fifo_2' of module 'mig_7series_v4_2_ddr_of_pre_fifo' has 8 connections declared, but only 7 given [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1462] +WARNING: [Synth 8-5974] attribute "use_dsp48" has been deprecated, please use "use_dsp" instead +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_mc_phy' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_4lanes' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:72] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo__parameterized1' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +INFO: [Synth 8-6157] synthesizing module 'ODDR' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100102] +INFO: [Synth 8-6155] done synthesizing module 'ODDR' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100102] +INFO: [Synth 8-6157] synthesizing module 'OBUFDS' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96472] +INFO: [Synth 8-6155] done synthesizing module 'OBUFDS' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96472] +INFO: [Synth 8-6157] synthesizing module 'PHASER_OUT_PHY' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114573] +INFO: [Synth 8-6155] done synthesizing module 'PHASER_OUT_PHY' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114573] +INFO: [Synth 8-6157] synthesizing module 'OUT_FIFO' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100824] +INFO: [Synth 8-6155] done synthesizing module 'OUT_FIFO' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100824] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_group_io' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6157] synthesizing module 'OSERDESE2' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6155] done synthesizing module 'OSERDESE2' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_group_io' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized0' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized0' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized1' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_if_post_fifo' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v:68] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v:110] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_if_post_fifo' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v:68] +INFO: [Synth 8-6157] synthesizing module 'PHASER_IN_PHY' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114436] +INFO: [Synth 8-6155] done synthesizing module 'PHASER_IN_PHY' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114436] +INFO: [Synth 8-6157] synthesizing module 'IN_FIFO' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:78141] +INFO: [Synth 8-6155] done synthesizing module 'IN_FIFO' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:78141] +INFO: [Synth 8-6157] synthesizing module 'PHASER_OUT_PHY__parameterized0' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114573] +INFO: [Synth 8-6155] done synthesizing module 'PHASER_OUT_PHY__parameterized0' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114573] +INFO: [Synth 8-6157] synthesizing module 'OUT_FIFO__parameterized0' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100824] +INFO: [Synth 8-6155] done synthesizing module 'OUT_FIFO__parameterized0' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100824] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized1' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6157] synthesizing module 'IDELAYE2' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:75752] +INFO: [Synth 8-6155] done synthesizing module 'IDELAYE2' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:75752] +INFO: [Synth 8-6157] synthesizing module 'ISERDESE2' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:80773] +INFO: [Synth 8-6155] done synthesizing module 'ISERDESE2' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:80773] +INFO: [Synth 8-6157] synthesizing module 'OSERDESE2__parameterized0' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6155] done synthesizing module 'OSERDESE2__parameterized0' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6157] synthesizing module 'OSERDESE2__parameterized1' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6155] done synthesizing module 'OSERDESE2__parameterized1' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized2' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized2' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'BUFIO' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:2224] +INFO: [Synth 8-6155] done synthesizing module 'BUFIO' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:2224] +INFO: [Synth 8-6157] synthesizing module 'PHY_CONTROL' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114664] +INFO: [Synth 8-6155] done synthesizing module 'PHY_CONTROL' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114664] +INFO: [Synth 8-226] default block is never used [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:1557] +INFO: [Synth 8-6157] synthesizing module 'PHASER_REF' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114648] +INFO: [Synth 8-6155] done synthesizing module 'PHASER_REF' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114648] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_4lanes' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:72] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_mc_phy' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy.v:70] +WARNING: [Synth 8-689] width (12) of port connection 'pi_dqs_found_lanes' does not match port width (4) of module 'mig_7series_v4_2_ddr_mc_phy' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1671] +WARNING: [Synth 8-689] width (12) of port connection 'pi_phase_locked_lanes' does not match port width (4) of module 'mig_7series_v4_2_ddr_mc_phy' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1679] +WARNING: [Synth 8-7071] port 'of_data_a_full' of module 'mig_7series_v4_2_ddr_mc_phy' is unconnected for instance 'u_ddr_mc_phy' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1579] +WARNING: [Synth 8-7023] instance 'u_ddr_mc_phy' of module 'mig_7series_v4_2_ddr_mc_phy' has 89 connections declared, but only 88 given [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1579] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_mc_phy_wrapper' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:71] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_calib_top' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:82] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_wrlvl' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:90] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:797] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_wrlvl' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:90] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v:68] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v:68] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_dqs_found_cal_hr' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:79] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_dqs_found_cal_hr' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:79] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_rdlvl' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:79] +WARNING: [Synth 8-5974] attribute "use_dsp48" has been deprecated, please use "use_dsp" instead +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2746] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_rdlvl' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:79] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_prbs_gen' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:92] +WARNING: [Synth 8-7186] Applying attribute ram_style = "distributed" is ignored, object 'rd_addr' is not inferred as ram due to incorrect usage [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:203] +WARNING: [Synth 8-7186] Applying attribute ram_style = "distributed" is ignored, object 'mem_out' is not inferred as ram due to incorrect usage [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:205] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_prbs_gen' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:92] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_init' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:89] +INFO: [Synth 8-226] default block is never used [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:5273] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_init' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:89] +WARNING: [Synth 8-7071] port 'complex_oclk_prech_req' of module 'mig_7series_v4_2_ddr_phy_init' is unconnected for instance 'u_ddr_phy_init' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:1367] +WARNING: [Synth 8-7023] instance 'u_ddr_phy_init' of module 'mig_7series_v4_2_ddr_phy_init' has 131 connections declared, but only 130 given [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:1367] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_wrcal' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:77] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:1130] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_wrcal' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:77] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_tempmon' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_tempmon' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_calib_top' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:82] +WARNING: [Synth 8-689] width (12) of port connection 'pi_dqs_found_lanes' does not match port width (4) of module 'mig_7series_v4_2_ddr_calib_top' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_top.v:1340] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_top' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_top.v:70] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_mem_intfc' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_mem_intfc.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ui_top' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_top.v:71] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ui_cmd' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_cmd.v:70] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ui_cmd' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_cmd.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ui_wr_data' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v:131] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v:342] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v:380] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ui_wr_data' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v:131] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ui_rd_data' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:140] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:406] +WARNING: [Synth 8-567] referenced signal 'not_strict_mode.occ_cnt_r' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403] +WARNING: [Synth 8-567] referenced signal 'not_strict_mode.free_rd_buf' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403] +WARNING: [Synth 8-567] referenced signal 'not_strict_mode.occ_minus_one' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403] +WARNING: [Synth 8-567] referenced signal 'not_strict_mode.occ_plus_one' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403] +WARNING: [Synth 8-567] referenced signal 'not_strict_mode.rd_data_buf_addr_r_lcl' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:432] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ui_rd_data' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:140] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ui_top' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_top.v:71] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_axi_mc' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc.v:90] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_axi_register_slice' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axi_register_slice.v:63] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized0' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized1' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized2' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized2' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_axi_register_slice' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axi_register_slice.v:63] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_axi_mc_aw_channel' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_aw_channel.v:57] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_axi_mc_cmd_translator' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_cmd_translator.v:62] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_axi_mc_incr_cmd' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_incr_cmd.v:64] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_incr_cmd' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_incr_cmd.v:64] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_axi_mc_wrap_cmd' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wrap_cmd.v:97] +INFO: [Common 17-14] Message 'Synth 8-6157' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_wrap_cmd' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wrap_cmd.v:97] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_cmd_translator' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_cmd_translator.v:62] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_wr_cmd_fsm' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wr_cmd_fsm.v:76] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_aw_channel' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_aw_channel.v:57] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_w_channel' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_w_channel.v:64] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_fifo' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_fifo.v:70] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_b_channel' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_b_channel.v:83] +INFO: [Common 17-14] Message 'Synth 8-6155' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [Synth 8-589] replacing case/wildcard equality operator === with logical equality operator == [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_r_channel.v:189] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_r_channel.v:315] +WARNING: [Synth 8-3848] Net ui_addn_clk_0 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:140] +WARNING: [Synth 8-3848] Net ui_addn_clk_1 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:141] +WARNING: [Synth 8-3848] Net ui_addn_clk_2 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:142] +WARNING: [Synth 8-3848] Net ui_addn_clk_3 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:143] +WARNING: [Synth 8-3848] Net ui_addn_clk_4 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:144] +WARNING: [Synth 8-6014] Unused sequential element periodic_rd_generation.read_this_rank_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v:487] +WARNING: [Synth 8-3936] Found unconnected internal register 'dbl_req_reg' and it is trimmed from '6' to '5' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:145] +WARNING: [Synth 8-3936] Found unconnected internal register 'dbl_last_master_ns_reg' and it is trimmed from '6' to '4' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:143] +WARNING: [Synth 8-6014] Unused sequential element last_master_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:181] +WARNING: [Synth 8-3848] Net channel[0].inh_group in module/entity mig_7series_v4_2_round_robin_arb__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:153] +WARNING: [Synth 8-3936] Found unconnected internal register 'col_addr_template_reg' and it is trimmed from '16' to '14' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v:251] +WARNING: [Synth 8-3936] Found unconnected internal register 'dbl_req_reg' and it is trimmed from '8' to '7' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:145] +WARNING: [Synth 8-3936] Found unconnected internal register 'dbl_last_master_ns_reg' and it is trimmed from '8' to '6' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:143] +WARNING: [Synth 8-6014] Unused sequential element sent_row_or_maint_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v:357] +WARNING: [Synth 8-6014] Unused sequential element mc_aux_out_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:680] +WARNING: [Synth 8-6014] Unused sequential element mc_aux_out_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:681] +WARNING: [Synth 8-3848] Net col_mux.col_row_r in module/entity mig_7series_v4_2_arb_select does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:390] +WARNING: [Synth 8-3936] Found unconnected internal register 'read_fifo.fifo_out_data_r_reg' and it is trimmed from '12' to '8' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_col_mach.v:396] +WARNING: [Synth 8-3848] Net oserdes_dqts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:143] +WARNING: [Synth 8-3848] Net oserdes_dqs_buf in module/entity mig_7series_v4_2_ddr_byte_group_io does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:144] +WARNING: [Synth 8-3848] Net oserdes_dqsts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:145] +WARNING: [Synth 8-3848] Net iserdes_dout in module/entity mig_7series_v4_2_ddr_byte_group_io does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:92] +WARNING: [Synth 8-6014] Unused sequential element ififo_rst_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:307] +WARNING: [Synth 8-3848] Net rclk in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:147] +WARNING: [Synth 8-3848] Net pi_iserdes_rst in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:193] +WARNING: [Synth 8-3848] Net pi_fine_overflow in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:195] +WARNING: [Synth 8-3848] Net pi_counter_read_val_w in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:431] +WARNING: [Synth 8-3848] Net dqs_out_of_range in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:198] +WARNING: [Synth 8-3848] Net iserdes_clk in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:275] +WARNING: [Synth 8-3848] Net iserdes_clkdiv in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:276] +WARNING: [Synth 8-3848] Net oserdes_dqts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:143] +WARNING: [Synth 8-3848] Net oserdes_dqs_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:144] +WARNING: [Synth 8-3848] Net oserdes_dqsts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:145] +WARNING: [Synth 8-3848] Net iserdes_dout in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:92] +WARNING: [Synth 8-6014] Unused sequential element ififo_rst_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:307] +WARNING: [Synth 8-3848] Net rclk in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:147] +WARNING: [Synth 8-3848] Net pi_iserdes_rst in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:193] +WARNING: [Synth 8-3848] Net pi_fine_overflow in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:195] +WARNING: [Synth 8-3848] Net pi_counter_read_val_w in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:431] +WARNING: [Synth 8-3848] Net dqs_out_of_range in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:198] +WARNING: [Synth 8-3848] Net iserdes_clk in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:275] +WARNING: [Synth 8-3848] Net iserdes_clkdiv in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:276] +WARNING: [Synth 8-6014] Unused sequential element fine_delay_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:185] +WARNING: [Synth 8-3848] Net dummy_i5 in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized1 does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:269] +WARNING: [Synth 8-3848] Net dummy_i6 in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized1 does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:270] +WARNING: [Synth 8-3848] Net dummy_i5 in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized2 does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:269] +WARNING: [Synth 8-3848] Net dummy_i6 in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized2 does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:270] +WARNING: [Synth 8-6014] Unused sequential element B_rst_primitives_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:737] +WARNING: [Synth 8-6014] Unused sequential element C_rst_primitives_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:738] +WARNING: [Synth 8-6014] Unused sequential element D_rst_primitives_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:739] +WARNING: [Synth 8-3936] Found unconnected internal register 'byte_sel_data_map_reg' and it is trimmed from '96' to '88' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:731] +WARNING: [Synth 8-3848] Net phy_data_full in module/entity mig_7series_v4_2_ddr_mc_phy_wrapper does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:227] +WARNING: [Synth 8-6014] Unused sequential element fast_cal_fine_cnt_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:790] +WARNING: [Synth 8-6014] Unused sequential element fast_cal_coarse_cnt_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:791] +WARNING: [Synth 8-6014] Unused sequential element final_corse_dec_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:792] +WARNING: [Synth 8-6014] Unused sequential element add_smallest_reg[1] was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:516] +WARNING: [Synth 8-6014] Unused sequential element add_largest_reg[0] was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:517] +WARNING: [Synth 8-6014] Unused sequential element add_largest_reg[1] was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:517] +WARNING: [Synth 8-6014] Unused sequential element dqs_wl_po_en_stg2_c_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:628] +WARNING: [Synth 8-6014] Unused sequential element po_en_stg2_c_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v:162] +WARNING: [Synth 8-6014] Unused sequential element rank_final_loop[0].final_do_max_reg[0] was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:1116] +WARNING: [Synth 8-6014] Unused sequential element rank_final_loop[0].final_do_index_reg[0] was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:1146] +WARNING: [Synth 8-6014] Unused sequential element dqsfound_retry_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:690] +WARNING: [Synth 8-3848] Net dqsfound_retry_done in module/entity mig_7series_v4_2_ddr_phy_dqs_found_cal_hr does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:131] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[0].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[1].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[2].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[3].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[4].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[5].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[6].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[7].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_stg1_done_int_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:686] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_stg1_done_int_r2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:687] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_stg1_done_int_r3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:688] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_last_byte_done_int_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:689] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_last_byte_done_int_r2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:690] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_last_byte_done_int_r3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:691] +WARNING: [Synth 8-6014] Unused sequential element fine_dly_dec_done_r3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:940] +WARNING: [Synth 8-6014] Unused sequential element fine_dly_dec_done_r4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:941] +WARNING: [Synth 8-6014] Unused sequential element regl_rank_done_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:1044] +WARNING: [Synth 8-6014] Unused sequential element cal1_state_r2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2696] +WARNING: [Synth 8-6014] Unused sequential element cal1_state_r3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2697] +WARNING: [Synth 8-6014] Unused sequential element cal1_cnt_cpt_timing_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:610] +WARNING: [Synth 8-6014] Unused sequential element sample_cnt_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:156] +WARNING: [Synth 8-6014] Unused sequential element reseed_prbs_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:157] +WARNING: [Synth 8-6014] Unused sequential element lfsr_q_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:174] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.phy_tmp_cs1_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4271] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.phy_tmp_odt_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4273] +WARNING: [Synth 8-6014] Unused sequential element wrlvl_final_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1421] +WARNING: [Synth 8-6014] Unused sequential element wrlvl_rank_cntr_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1539] +WARNING: [Synth 8-6014] Unused sequential element cnt_pwron_cke_done_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1781] +WARNING: [Synth 8-6014] Unused sequential element cnt_init_pre_wait_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1814] +WARNING: [Synth 8-6014] Unused sequential element cnt_init_pre_wait_done_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1815] +WARNING: [Synth 8-6014] Unused sequential element rnk_ref_cnt_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1941] +WARNING: [Synth 8-6014] Unused sequential element read_calib_int_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:2720] +WARNING: [Synth 8-6014] Unused sequential element read_calib_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:2727] +WARNING: [Synth 8-6014] Unused sequential element pi_dqs_found_rank_done_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:2778] +WARNING: [Synth 8-6014] Unused sequential element pi_dqs_found_all_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:2783] +WARNING: [Synth 8-6014] Unused sequential element complex_row0_rd_done_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:3339] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_wr_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:3632] +WARNING: [Synth 8-6014] Unused sequential element extend_cal_pat_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:3638] +WARNING: [Synth 8-6014] Unused sequential element cnt_init_data_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:3714] +WARNING: [Synth 8-6014] Unused sequential element victim_byte_cnt_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:818] +WARNING: [Synth 8-3936] Found unconnected internal register 'rdlvl_start_dly0_r_reg' and it is trimmed from '16' to '15' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1228] +WARNING: [Synth 8-3936] Found unconnected internal register 'wrcal_start_dly_r_reg' and it is trimmed from '16' to '15' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1230] +WARNING: [Synth 8-3936] Found unconnected internal register 'oclkdelay_start_dly_r_reg' and it is trimmed from '16' to '15' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1232] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr2_r_reg[1] was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4265] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr2_r_reg[2] was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4265] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr2_r_reg[3] was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4265] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr1_r_reg[1] was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4268] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr1_r_reg[2] was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4268] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr1_r_reg[3] was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4268] +WARNING: [Synth 8-6014] Unused sequential element prech_done_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1303] +WARNING: [Synth 8-6014] Unused sequential element calib_cmd_wren_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4229] +WARNING: [Synth 8-3848] Net calib_aux_out in module/entity mig_7series_v4_2_ddr_phy_init does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:276] +WARNING: [Synth 8-6014] Unused sequential element rd_active_r4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:534] +WARNING: [Synth 8-6014] Unused sequential element rd_active_r5_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:535] +WARNING: [Synth 8-6014] Unused sequential element pat1_detect_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:1124] +WARNING: [Synth 8-6014] Unused sequential element early1_detect_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:1125] +WARNING: [Synth 8-6014] Unused sequential element rd_mux_sel_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:438] +WARNING: [Synth 8-3848] Net i in module/entity mig_7series_v4_2_ddr_phy_wrcal does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:155] +WARNING: [Synth 8-6014] Unused sequential element calib_complete_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v:182] +WARNING: [Synth 8-6014] Unused sequential element sample_en_cnt_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v:188] +WARNING: [Synth 8-6014] Unused sequential element device_temp_capture_102_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v:290] +WARNING: [Synth 8-6014] Unused sequential element tempmon_sel_pi_incdec_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:883] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:898] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:899] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:900] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:901] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r5_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:902] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r6_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:903] +WARNING: [Synth 8-6014] Unused sequential element skip_calib_tap_off.skip_cal_tempmon_samp_en_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:2262] +WARNING: [Synth 8-6014] Unused sequential element wrlvl_final_mux_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:834] +WARNING: [Synth 8-3848] Net dbg_skip_cal in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:673] +WARNING: [Synth 8-3848] Net coarse_dec_err in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:662] +WARNING: [Synth 8-3848] Net dbg_poc in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:335] +WARNING: [Synth 8-3848] Net fine_delay_incdec_pb in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:341] +WARNING: [Synth 8-3848] Net fine_delay_sel in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:342] +WARNING: [Synth 8-3848] Net lim_done in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:620] +WARNING: [Synth 8-3848] Net lim2init_write_request in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:619] +WARNING: [Synth 8-3848] Net complex_ocal_num_samples_done_r in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:533] +WARNING: [Synth 8-3848] Net complex_ocal_rd_victim_sel in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:534] +WARNING: [Synth 8-3848] Net complex_victim_inc in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:592] +WARNING: [Synth 8-3848] Net rd_victim_sel in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:588] +WARNING: [Synth 8-3848] Net oclkdelay_center_calib_start in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:597] +WARNING: [Synth 8-3848] Net oclk_center_write_resume in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:615] +WARNING: [Synth 8-3848] Net oclkdelay_center_calib_done in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:616] +WARNING: [Synth 8-6014] Unused sequential element app_wdf_rdy_r_copy4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v:268] +WARNING: [Synth 8-6014] Unused sequential element int_next_pending_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_incr_cmd.v:191] +WARNING: [Synth 8-6014] Unused sequential element sel_first_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_incr_cmd.v:220] +WARNING: [Synth 8-6014] Unused sequential element int_next_pending_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wrap_cmd.v:221] +WARNING: [Synth 8-6014] Unused sequential element sel_first_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wrap_cmd.v:239] +WARNING: [Synth 8-3848] Net cmd_wr_bytes in module/entity mig_7series_v4_2_axi_mc_w_channel does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_w_channel.v:96] +WARNING: [Synth 8-6014] Unused sequential element rd_last_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_r_channel.v:216] +WARNING: [Synth 8-3848] Net error in module/entity mig_7series_v4_2_memc_ui_top_axi does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_memc_ui_top_axi.v:555] +WARNING: [Synth 8-3848] Net app_correct_en_i in module/entity mig_7series_v4_2_memc_ui_top_axi does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_memc_ui_top_axi.v:500] +WARNING: [Synth 8-3848] Net s_axi_ctrl_awvalid in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:754] +WARNING: [Synth 8-3848] Net s_axi_ctrl_awaddr in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:756] +WARNING: [Synth 8-3848] Net s_axi_ctrl_wvalid in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:758] +WARNING: [Synth 8-3848] Net s_axi_ctrl_wdata in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:760] +WARNING: [Synth 8-3848] Net s_axi_ctrl_bready in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:763] +WARNING: [Synth 8-3848] Net s_axi_ctrl_arvalid in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:766] +WARNING: [Synth 8-3848] Net s_axi_ctrl_araddr in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:768] +WARNING: [Synth 8-3848] Net s_axi_ctrl_rready in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:771] +WARNING: [Synth 8-3848] Net device_temp_i in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:784] +WARNING: [Synth 8-7129] Port mc_app_rd_last in module mig_7series_v4_2_axi_mc_r_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port axlen[7] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axlen[6] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axlen[5] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axlen[4] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[2] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[1] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[0] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[2] in module mig_7series_v4_2_axi_mc_incr_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[1] in module mig_7series_v4_2_axi_mc_incr_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[0] in module mig_7series_v4_2_axi_mc_incr_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axburst[0] in module mig_7series_v4_2_axi_mc_cmd_translator is either unconnected or has no load +WARNING: [Synth 8-7129] Port arlock[1] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arlock[0] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arcache[3] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arcache[2] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arcache[1] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arcache[0] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arprot[2] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arprot[1] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arprot[0] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port b_resp_rdy in module mig_7series_v4_2_axi_mc_b_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port cmd_wr_bytes in module mig_7series_v4_2_axi_mc_w_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awvalid in module mig_7series_v4_2_axi_mc_w_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port w_ignore_begin in module mig_7series_v4_2_axi_mc_w_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port w_ignore_end in module mig_7series_v4_2_axi_mc_w_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awlock[1] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awlock[0] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awcache[3] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awcache[2] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awcache[1] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awcache[0] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awprot[2] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awprot[1] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awprot[0] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port cmd_wr_bytes in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice__parameterized1 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice__parameterized1 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice__parameterized0 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice__parameterized0 is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_AWUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_WUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_ARUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port M_AXI_BUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port M_AXI_RUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[7] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[6] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[5] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[4] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[3] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[2] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[1] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[0] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[7] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[6] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[5] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[4] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[3] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[2] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[1] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[0] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[7] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[6] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[5] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[4] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[3] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[2] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[1] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[0] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port wr_data_addr[4] in module mig_7series_v4_2_ui_top is either unconnected or has no load +WARNING: [Synth 8-7129] Port accept in module mig_7series_v4_2_ui_top is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[11] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[10] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[9] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[8] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[7] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[6] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[5] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[4] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[3] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[2] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[1] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[0] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[99] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[98] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[97] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[96] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[95] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[94] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[93] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[16] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[15] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[14] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[12] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[11] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[10] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2910.293 ; gain = 668.254 ; free physical = 193728 ; free virtual = 542682 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2910.293 ; gain = 668.254 ; free physical = 193715 ; free virtual = 542669 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2910.293 ; gain = 668.254 ; free physical = 193715 ; free virtual = 542669 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.2 . Memory (MB): peak = 2910.293 ; gain = 0.000 ; free physical = 193740 ; free virtual = 542692 +INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3_ooc.xdc] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3_ooc.xdc] +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] +WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc:346] +WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc:353] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/arty_ddr3_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/arty_ddr3_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +INFO: [Timing 38-2] Deriving generated clocks +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.137 ; gain = 0.000 ; free physical = 193624 ; free virtual = 542576 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 70 instances were transformed. + IOBUFDS_INTERMDISABLE => IOBUFDS_INTERMDISABLE (IBUFDS_INTERMDISABLE_INT(x2), INV, OBUFTDS(x2)): 2 instances + IOBUF_INTERMDISABLE => IOBUF_INTERMDISABLE (IBUF_INTERMDISABLE, OBUFT): 16 instances + OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 1 instance + RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 51 instances + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.19 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3019.137 ; gain = 0.000 ; free physical = 193629 ; free virtual = 542581 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 3019.137 ; gain = 777.098 ; free physical = 193667 ; free virtual = 542623 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a100tcsg324-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 3027.141 ; gain = 785.102 ; free physical = 193667 ; free virtual = 542623 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_ck_n[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc, line 27). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_ck_p[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc, line 28). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:14 . Memory (MB): peak = 3027.141 ; gain = 785.102 ; free physical = 193677 ; free virtual = 542633 +--------------------------------------------------------------------------------- +INFO: [Synth 8-802] inferred FSM for state register 'xadc_supplied_temperature.tempmon_state_reg' in module 'mig_7series_v4_2_tempmon' +INFO: [Synth 8-802] inferred FSM for state register 'wl_state_r_reg' in module 'mig_7series_v4_2_ddr_phy_wrlvl' +INFO: [Synth 8-802] inferred FSM for state register 'fine_adj_state_r_reg' in module 'mig_7series_v4_2_ddr_phy_dqs_found_cal_hr' +INFO: [Synth 8-802] inferred FSM for state register 'cal1_state_r_reg' in module 'mig_7series_v4_2_ddr_phy_rdlvl' +INFO: [Synth 8-802] inferred FSM for state register 'tempmon_state_reg' in module 'mig_7series_v4_2_ddr_phy_tempmon' +INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'mig_7series_v4_2_axi_mc_r_channel' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + INIT_IDLE | 0001 | 000 + REQUEST_READ_TEMP | 1000 | 001 + WAIT_FOR_READ | 0100 | 010 + READ | 0010 | 011 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'xadc_supplied_temperature.tempmon_state_reg' using encoding 'one-hot' in module 'mig_7series_v4_2_tempmon' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + WL_IDLE | 01110 | 00000 + WL_INIT | 10010 | 00001 + WL_INIT_FINE_INC | 01100 | 00010 + WL_INIT_FINE_INC_WAIT1 | 01000 | 00011 + WL_INIT_FINE_INC_WAIT | 01001 | 00100 + WL_INIT_FINE_DEC | 11001 | 00101 + WL_INIT_FINE_DEC_WAIT1 | 10111 | 11001 + WL_INIT_FINE_DEC_WAIT | 11000 | 00110 + WL_WAIT | 00110 | 01000 + WL_EDGE_CHECK | 11011 | 01001 + WL_DQS_CNT | 10100 | 01011 + WL_FINE_DEC | 00000 | 01110 + WL_FINE_DEC_WAIT1 | 00001 | 11010 + WL_FINE_DEC_WAIT | 10001 | 01111 + WL_CORSE_DEC | 10110 | 10100 + WL_CORSE_DEC_WAIT | 11010 | 10101 + WL_CORSE_DEC_WAIT1 | 10101 | 10110 + WL_2RANK_DQS_CNT | 00010 | 01101 + WL_DQS_CHECK | 00011 | 01010 + WL_FINE_INC | 01101 | 00111 + WL_FINE_INC_WAIT | 10011 | 10111 + WL_2RANK_FINAL_TAP | 01111 | 11000 + WL_CORSE_INC | 01011 | 10000 + WL_CORSE_INC_WAIT_TMP | 10000 | 11011 + WL_CORSE_INC_WAIT | 01010 | 10001 + WL_CORSE_INC_WAIT1 | 00111 | 10010 + WL_CORSE_INC_WAIT2 | 00101 | 10011 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'wl_state_r_reg' using encoding 'sequential' in module 'mig_7series_v4_2_ddr_phy_wrlvl' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + FINE_ADJ_IDLE | 0000 | 0000 + RST_WAIT | 0001 | 0011 + FINE_ADJ_DONE | 0010 | 1111 + RST_POSTWAIT | 0011 | 0001 + RST_POSTWAIT1 | 0100 | 0010 + FINE_ADJ_INIT | 0101 | 0100 + FINE_INC | 0110 | 0101 + FINE_INC_WAIT | 0111 | 0110 + FINE_INC_PREWAIT | 1000 | 0111 + DETECT_PREWAIT | 1001 | 1000 + DETECT_DQSFOUND | 1010 | 1001 + FINE_DEC | 1011 | 1011 + FINE_DEC_WAIT | 1100 | 1100 + FINE_DEC_PREWAIT | 1101 | 1101 + FINAL_WAIT | 1110 | 1110 + PRECH_WAIT | 1111 | 1010 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'fine_adj_state_r_reg' using encoding 'sequential' in module 'mig_7series_v4_2_ddr_phy_dqs_found_cal_hr' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + CAL1_IDLE | 00000000000000000000000000010000000 | 000000 + CAL1_NEW_DQS_WAIT | 00000000000000000000010000000000000 | 000001 + CAL1_STORE_FIRST_WAIT | 00000000000000000010000000000000000 | 000010 + CAL1_PAT_DETECT | 00000000000000100000000000000000000 | 000011 + CAL1_DQ_IDEL_TAP_INC | 00000000000000000000000000000000100 | 000100 +CAL1_DQ_IDEL_TAP_INC_WAIT | 00000000000000000000000000000001000 | 000101 + CAL1_MPR_PAT_DETECT | 00000000000000000000000010000000000 | 011111 + CAL1_VALID_WAIT | 10000000000000000000000000000000000 | 011110 + CAL1_DETECT_EDGE | 00000000000001000000000000000000000 | 001000 + CAL1_CALC_IDEL | 00000100000000000000000000000000000 | 001011 + CAL1_CENTER_WAIT | 00000000000000000000000000000000001 | 100010 + CAL1_IDEL_DEC_CPT | 00000000000000000000000000000000010 | 001100 + CAL1_DQ_IDEL_TAP_DEC | 00000000000000000001000000000000000 | 000110 +CAL1_DQ_IDEL_TAP_DEC_WAIT | 00100000000000000000000000000000000 | 000111 + CAL1_NEXT_DQS | 00000000000000000000000000000010000 | 001110 + CAL1_REGL_LOAD | 00000000000000000000000000001000000 | 011011 + CAL1_DONE | 00000000000000000000000000000100000 | 001111 + CAL1_NEW_DQS_PREWAIT | 00000000000000000000000000100000000 | 100000 + CAL1_MPR_NEW_DQS_WAIT | 00000000000000000000000001000000000 | 011101 + CAL1_IDEL_DEC_CPT_WAIT | 00000000000000000000100000000000000 | 001101 + CAL1_RD_STOP_FOR_PI_INC | 00000000000000000000000100000000000 | 100001 + CAL1_IDEL_INC_CPT | 00000000000000000000001000000000000 | 001001 + CAL1_IDEL_INC_CPT_WAIT | 00010000000000000000000000000000000 | 001010 + CAL1_RDLVL_ERR | 00000000000010000000000000000000000 | 011100 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'cal1_state_r_reg' using encoding 'one-hot' in module 'mig_7series_v4_2_ddr_phy_rdlvl' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 00000000001 | 00000000001 + INIT | 00000000010 | 00000000010 + NEUTRAL | 00001000000 | 00001000000 + ONE_DEC | 00010000000 | 00010000000 + TWO_DEC | 00100000000 | 00100000000 + THREE_DEC | 01000000000 | 01000000000 + FOUR_DEC | 10000000000 | 10000000000 + ONE_INC | 00000100000 | 00000100000 + TWO_INC | 00000010000 | 00000010000 + THREE_INC | 00000001000 | 00000001000 + FOUR_INC | 00000000100 | 00000000100 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'tempmon_state_reg' in module 'mig_7series_v4_2_ddr_phy_tempmon' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + ZERO | 11 | 10 + ONE | 01 | 11 + TWO | 00 | 01 + iSTATE | 10 | 00 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'mig_7series_v4_2_axi_mc_r_channel' +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:20 ; elapsed = 00:00:19 . Memory (MB): peak = 3027.141 ; gain = 785.102 ; free physical = 193714 ; free virtual = 542673 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 4 Input 32 Bit Adders := 2 + 3 Input 32 Bit Adders := 1 + 2 Input 28 Bit Adders := 2 + 2 Input 13 Bit Adders := 1 + 2 Input 12 Bit Adders := 15 + 2 Input 11 Bit Adders := 1 + 2 Input 10 Bit Adders := 6 + 2 Input 9 Bit Adders := 4 + 2 Input 8 Bit Adders := 8 + 3 Input 7 Bit Adders := 2 + 2 Input 7 Bit Adders := 1 + 2 Input 6 Bit Adders := 30 + 3 Input 6 Bit Adders := 3 + 2 Input 5 Bit Adders := 37 + 2 Input 4 Bit Adders := 34 + 2 Input 3 Bit Adders := 20 + 3 Input 3 Bit Adders := 1 + 2 Input 2 Bit Adders := 51 + 3 Input 2 Bit Adders := 3 + 4 Input 2 Bit Adders := 5 + 5 Input 2 Bit Adders := 1 + 8 Input 2 Bit Adders := 1 + 2 Input 1 Bit Adders := 5 + 3 Input 1 Bit Adders := 1 + 4 Input 1 Bit Adders := 1 + 5 Input 1 Bit Adders := 1 + 6 Input 1 Bit Adders := 1 + 7 Input 1 Bit Adders := 1 + 8 Input 1 Bit Adders := 1 + 9 Input 1 Bit Adders := 1 ++---XORs : + 2 Input 1 Bit XORs := 1 ++---Registers : + 144 Bit Registers := 1 + 128 Bit Registers := 5 + 88 Bit Registers := 1 + 80 Bit Registers := 3 + 56 Bit Registers := 1 + 32 Bit Registers := 3 + 30 Bit Registers := 1 + 28 Bit Registers := 6 + 16 Bit Registers := 13 + 15 Bit Registers := 4 + 14 Bit Registers := 6 + 13 Bit Registers := 1 + 12 Bit Registers := 33 + 11 Bit Registers := 1 + 10 Bit Registers := 4 + 9 Bit Registers := 12 + 8 Bit Registers := 15 + 7 Bit Registers := 5 + 6 Bit Registers := 59 + 5 Bit Registers := 46 + 4 Bit Registers := 82 + 3 Bit Registers := 47 + 2 Bit Registers := 66 + 1 Bit Registers := 1542 ++---Muxes : + 2 Input 128 Bit Muxes := 10 + 4 Input 128 Bit Muxes := 1 + 2 Input 127 Bit Muxes := 1 + 2 Input 80 Bit Muxes := 6 + 2 Input 56 Bit Muxes := 1 + 24 Input 35 Bit Muxes := 1 + 2 Input 35 Bit Muxes := 22 + 2 Input 32 Bit Muxes := 1 + 2 Input 30 Bit Muxes := 12 + 4 Input 30 Bit Muxes := 4 + 2 Input 28 Bit Muxes := 11 + 2 Input 21 Bit Muxes := 8 + 2 Input 16 Bit Muxes := 8 + 3 Input 16 Bit Muxes := 1 + 3 Input 14 Bit Muxes := 1 + 2 Input 14 Bit Muxes := 8 + 4 Input 14 Bit Muxes := 1 + 2 Input 12 Bit Muxes := 5 + 12 Input 11 Bit Muxes := 1 + 2 Input 11 Bit Muxes := 1 + 2 Input 10 Bit Muxes := 7 + 4 Input 9 Bit Muxes := 6 + 2 Input 9 Bit Muxes := 18 + 2 Input 8 Bit Muxes := 61 + 5 Input 8 Bit Muxes := 1 + 2 Input 7 Bit Muxes := 64 + 3 Input 7 Bit Muxes := 1 + 4 Input 7 Bit Muxes := 1 + 5 Input 7 Bit Muxes := 2 + 2 Input 6 Bit Muxes := 81 + 4 Input 6 Bit Muxes := 8 + 27 Input 6 Bit Muxes := 4 + 5 Input 6 Bit Muxes := 2 + 16 Input 6 Bit Muxes := 1 + 24 Input 6 Bit Muxes := 5 + 3 Input 6 Bit Muxes := 2 + 2 Input 5 Bit Muxes := 35 + 8 Input 5 Bit Muxes := 2 + 27 Input 5 Bit Muxes := 1 + 58 Input 5 Bit Muxes := 1 + 24 Input 5 Bit Muxes := 1 + 4 Input 5 Bit Muxes := 2 + 3 Input 5 Bit Muxes := 4 + 2 Input 4 Bit Muxes := 67 + 32 Input 4 Bit Muxes := 1 + 8 Input 4 Bit Muxes := 1 + 7 Input 4 Bit Muxes := 1 + 2 Input 3 Bit Muxes := 69 + 27 Input 3 Bit Muxes := 6 + 3 Input 3 Bit Muxes := 1 + 4 Input 3 Bit Muxes := 3 + 8 Input 3 Bit Muxes := 1 + 2 Input 2 Bit Muxes := 101 + 4 Input 2 Bit Muxes := 7 + 3 Input 2 Bit Muxes := 9 + 8 Input 2 Bit Muxes := 4 + 27 Input 2 Bit Muxes := 1 + 24 Input 2 Bit Muxes := 2 + 5 Input 2 Bit Muxes := 1 + 10 Input 2 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 491 + 3 Input 1 Bit Muxes := 12 + 8 Input 1 Bit Muxes := 4 + 4 Input 1 Bit Muxes := 204 + 27 Input 1 Bit Muxes := 27 + 5 Input 1 Bit Muxes := 1 + 16 Input 1 Bit Muxes := 21 + 24 Input 1 Bit Muxes := 30 + 10 Input 1 Bit Muxes := 17 + 12 Input 1 Bit Muxes := 4 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 240 (col length:80) +BRAMs: 270 (col length: RAMB18 80 RAMB36 40) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +WARNING: [Synth 8-7080] Parallel synthesis criteria is not met +WARNING: [Synth 8-3936] Found unconnected internal register 'byte_sel_data_map_reg' and it is trimmed from '88' to '4' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:731] +WARNING: [Synth 8-3936] Found unconnected internal register 'oclkdelay_start_dly_r_reg' and it is trimmed from '15' to '14' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1232] +WARNING: [Synth 8-3936] Found unconnected internal register 'wrcal_start_dly_r_reg' and it is trimmed from '15' to '14' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1230] +WARNING: [Synth 8-3332] Sequential element (FSM_onehot_cal1_state_r_reg[33]) is unused and will be removed from module mig_7series_v4_2_ddr_phy_rdlvl. +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:18 ; elapsed = 00:01:18 . Memory (MB): peak = 3299.703 ; gain = 1057.664 ; free physical = 191400 ; free virtual = 540545 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +ROM: Preliminary Mapping Report ++------------------------------+------------+---------------+----------------+ +|Module Name | RTL Object | Depth x Width | Implemented As | ++------------------------------+------------+---------------+----------------+ +|mig_7series_v4_2_ddr_prbs_gen | mem_out | 256x18 | LUT | +|mig_7series_v4_2_ddr_prbs_gen | mem_out | 256x18 | LUT | ++------------------------------+------------+---------------+----------------+ + + +Distributed RAM: Preliminary Mapping Report (see note below) ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ +|arty_ddr3 | of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ + +Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +WARNING: [Synth 8-3321] set_false_path : Empty through list for constraint at line 359 of /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc:359] +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:22 ; elapsed = 00:01:22 . Memory (MB): peak = 3299.703 ; gain = 1057.664 ; free physical = 196036 ; free virtual = 545183 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:01:22 ; elapsed = 00:01:23 . Memory (MB): peak = 3299.703 ; gain = 1057.664 ; free physical = 196091 ; free virtual = 545237 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Distributed RAM: Final Mapping Report ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ +|arty_ddr3 | of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:01:25 ; elapsed = 00:01:25 . Memory (MB): peak = 3299.703 ; gain = 1057.664 ; free physical = 195925 ; free virtual = 545073 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:01:28 ; elapsed = 00:01:28 . Memory (MB): peak = 3299.703 ; gain = 1057.664 ; free physical = 195750 ; free virtual = 544898 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:01:28 ; elapsed = 00:01:28 . Memory (MB): peak = 3299.703 ; gain = 1057.664 ; free physical = 195750 ; free virtual = 544898 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:29 ; elapsed = 00:01:29 . Memory (MB): peak = 3299.703 ; gain = 1057.664 ; free physical = 195852 ; free virtual = 544999 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:01:29 ; elapsed = 00:01:29 . Memory (MB): peak = 3299.703 ; gain = 1057.664 ; free physical = 195852 ; free virtual = 544999 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:01:29 ; elapsed = 00:01:29 . Memory (MB): peak = 3299.703 ; gain = 1057.664 ; free physical = 195852 ; free virtual = 544999 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:01:29 ; elapsed = 00:01:29 . Memory (MB): peak = 3299.703 ; gain = 1057.664 ; free physical = 195852 ; free virtual = 544999 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Static Shift Register Report: ++------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ +|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | ++------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/rclk_delay_reg[11] | 12 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/rst_r4_reg | 4 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/phy_ctl_ready_r5_reg | 5 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay/delay_done_r4_reg | 4 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/init_dqsfound_done_r5_reg | 3 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrlvl_rank_done_r7_reg | 6 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prech_done_reg | 17 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_start_dly_r_reg[5] | 6 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg[14] | 15 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_pat_match_div4.pat_data_match_valid_r_reg | 3 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] | 3 | 4 | NO | NO | YES | 4 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/wrcal_pat_resume_reg | 3 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/reset_if_r9_reg | 9 | 1 | NO | NO | YES | 1 | 0 | ++------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ + + +Dynamic Shift Register Report: ++------------+----------------+--------+------------+--------+---------+--------+--------+--------+ +|Module Name | RTL Name | Length | Data Width | SRL16E | SRLC32E | Mux F7 | Mux F8 | Mux F9 | ++------------+----------------+--------+------------+--------+---------+--------+--------+--------+ +|dsrl | memory_reg[7] | 4 | 4 | 4 | 0 | 0 | 0 | 0 | +|dsrl__1 | memory_reg[31] | 129 | 129 | 0 | 129 | 0 | 0 | 0 | +|dsrl__2 | memory_reg[29] | 7 | 7 | 0 | 7 | 0 | 0 | 0 | ++------------+----------------+--------+------------+--------+---------+--------+--------+--------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+----------------------+------+ +| |Cell |Count | ++------+----------------------+------+ +|1 |BUFG | 3| +|2 |BUFH | 1| +|3 |BUFIO | 1| +|4 |CARRY4 | 124| +|5 |IDELAYCTRL | 1| +|6 |IDELAYE2 | 16| +|7 |IN_FIFO | 2| +|8 |ISERDESE2 | 16| +|9 |LUT1 | 375| +|10 |LUT2 | 438| +|11 |LUT3 | 1023| +|12 |LUT4 | 905| +|13 |LUT5 | 1361| +|14 |LUT6 | 1262| +|15 |MMCME2_ADV | 1| +|16 |MUXF7 | 28| +|17 |ODDR | 5| +|18 |OSERDESE2 | 43| +|21 |OUT_FIFO | 4| +|23 |PHASER_IN_PHY | 2| +|24 |PHASER_OUT_PHY | 4| +|26 |PHASER_REF | 1| +|27 |PHY_CONTROL | 1| +|28 |PLLE2_ADV | 1| +|29 |RAM32M | 112| +|30 |RAM32X1D | 2| +|31 |SRL16E | 20| +|32 |SRLC32E | 134| +|33 |XADC | 1| +|34 |FDCE | 2| +|35 |FDPE | 73| +|36 |FDRE | 3995| +|37 |FDSE | 123| +|38 |IOBUFDS_INTERMDISABLE | 2| +|39 |IOBUF_INTERMDISABLE | 16| +|40 |OBUF | 24| +|41 |OBUFDS | 1| +|42 |OBUFT | 2| ++------+----------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:01:29 ; elapsed = 00:01:29 . Memory (MB): peak = 3299.703 ; gain = 1057.664 ; free physical = 195852 ; free virtual = 544999 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 6 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:01:25 ; elapsed = 00:01:26 . Memory (MB): peak = 3299.703 ; gain = 948.820 ; free physical = 195852 ; free virtual = 544999 +Synthesis Optimization Complete : Time (s): cpu = 00:01:29 ; elapsed = 00:01:29 . Memory (MB): peak = 3299.711 ; gain = 1057.664 ; free physical = 195852 ; free virtual = 544999 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.13 . Memory (MB): peak = 3299.711 ; gain = 0.000 ; free physical = 196176 ; free virtual = 545323 +INFO: [Netlist 29-17] Analyzing 325 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3_ooc.xdc] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3_ooc.xdc] +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] +INFO: [Opt 31-138] Pushed 2 inverter(s) to 16 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3355.730 ; gain = 0.000 ; free physical = 196204 ; free virtual = 545351 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 133 instances were transformed. + IOBUFDS_INTERMDISABLE => IOBUFDS_INTERMDISABLE (IBUFDS_INTERMDISABLE_INT(x2), INV, OBUFTDS(x2)): 2 instances + IOBUF_INTERMDISABLE => IOBUF_INTERMDISABLE (IBUF_INTERMDISABLE, OBUFT): 16 instances + OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 1 instance + RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 112 instances + RAM32X1D => RAM32X1D (RAMD32(x2)): 2 instances + +Synth Design complete | Checksum: cc6d6f52 +INFO: [Common 17-83] Releasing license: Synthesis +249 Infos, 303 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:01:34 ; elapsed = 00:01:31 . Memory (MB): peak = 3355.730 ; gain = 1119.629 ; free physical = 196197 ; free virtual = 545343 +INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 3064.380; main = 2772.867; forked = 443.080 +INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 4342.293; main = 3355.734; forked = 1042.586 +INFO: [Coretcl 2-1174] Renamed 88 cell refs. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-2] Deriving generated clocks +INFO: [Timing 38-480] Writing timing data to binary archive. +Write ShapeDB Complete: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3419.746 ; gain = 0.000 ; free physical = 195973 ; free virtual = 545119 +Wrote PlaceDB: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3419.746 ; gain = 0.000 ; free physical = 195965 ; free virtual = 545111 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3419.746 ; gain = 0.000 ; free physical = 195965 ; free virtual = 545111 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3419.746 ; gain = 0.000 ; free physical = 195965 ; free virtual = 545111 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3419.746 ; gain = 0.000 ; free physical = 195965 ; free virtual = 545111 +Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3419.746 ; gain = 0.000 ; free physical = 195957 ; free virtual = 545104 +Write Physdb Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3419.746 ; gain = 0.000 ; free physical = 195957 ; free virtual = 545104 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3.dcp' has been generated. +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data0/tools/Xilinx/Vivado/2024.1/data/ip'. +WARNING: [Vivado 12-13650] The IP file '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc.xci' has been moved from its original location, as a result the outputs for this IP will now be generated in '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc'. Alternatively a copy of the IP can be imported into the project using one of the 'import_ip' or 'import_files' commands. +Command: synth_design -top toy_axi_cdc -part xc7a100tcsg324-1 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 3419.746 ; gain = 0.000 ; free physical = 194787 ; free virtual = 543940 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'toy_axi_cdc' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/synth/toy_axi_cdc.v:53] +INFO: [Synth 8-6157] synthesizing module 'axi_clock_converter_v2_1_30_axi_clock_converter' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/hdl/axi_clock_converter_v2_1_vl_rfs.v:650] +INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_single' [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:152] +INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_single' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:152] +INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_async_rst' [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1175] +INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_async_rst' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1175] +INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_single__parameterized1' [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:152] +INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_single__parameterized1' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:152] +INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray' [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:283] +INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:283] +INFO: [Synth 8-6155] done synthesizing module 'axi_clock_converter_v2_1_30_axi_clock_converter' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/hdl/axi_clock_converter_v2_1_vl_rfs.v:650] +INFO: [Synth 8-6155] done synthesizing module 'toy_axi_cdc' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/synth/toy_axi_cdc.v:53] +WARNING: [Synth 8-7129] Port ALMOST_FULL_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ALMOST_EMPTY_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_ACK_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port VALID_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port OVERFLOW_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port UNDERFLOW_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DATA_COUNT_I[4] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DATA_COUNT_I[3] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DATA_COUNT_I[2] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DATA_COUNT_I[1] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DATA_COUNT_I[0] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[4] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[3] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[2] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[1] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[0] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[4] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[3] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[2] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[1] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[0] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port SBITERR_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DBITERR_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_RST in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port SAFETY_CKT_WR_RST in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[3] in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[2] in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[1] in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[0] in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module wr_bin_cntr is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_EN_INTO_LOGIC in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_RST_INTO_LOGIC in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_EN in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST_FULL_FF in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_RST_BUSY in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port EMPTY in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RAM_RD_EN in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port ALMOST_EMPTY in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[3] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[2] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[1] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[0] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[3] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[2] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[1] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[0] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_NEGATE[3] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_NEGATE[2] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_NEGATE[1] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_NEGATE[0] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module rd_fwft is either unconnected or has no load +WARNING: [Synth 8-7129] Port SAFETY_CKT_RD_RST in module rd_fwft is either unconnected or has no load +WARNING: [Synth 8-7129] Port RAM_ALMOST_EMPTY in module rd_fwft is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port SAFETY_CKT_RD_RST in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_PNTR_PLUS2[3] in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_PNTR_PLUS2[2] in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_PNTR_PLUS2[1] in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_PNTR_PLUS2[0] in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module rd_bin_cntr is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_EN_INTO_LOGIC in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_RST_INTO_LOGIC in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_RST_BUSY in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RAM_WR_EN in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RST_FULL_FF in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port ALMOST_FULL_FB in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port FULL in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS1_RD[3] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS1_RD[2] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS1_RD[1] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS1_RD[0] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[3] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[2] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[1] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[0] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_ASSERT[3] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_ASSERT[2] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_ASSERT[1] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_ASSERT[0] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_NEGATE[3] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_NEGATE[2] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_NEGATE[1] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_NEGATE[0] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_RST in module clk_x_pntrs is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_RST in module clk_x_pntrs is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module dmem__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FAB_REGOUT_EN in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port SFT_RST in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port SAFETY_CKT_RD_RST in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port SLEEP in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port INJECTDBITERR in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port INJECTSBITERR in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port CLK in module input_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port INT_CLK in module input_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[3] in module input_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[2] in module input_blk__parameterized2 is either unconnected or has no load +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 3419.746 ; gain = 0.000 ; free physical = 194544 ; free virtual = 543693 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 3419.746 ; gain = 0.000 ; free physical = 194544 ; free virtual = 543693 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 3419.746 ; gain = 0.000 ; free physical = 194544 ; free virtual = 543693 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3419.746 ; gain = 0.000 ; free physical = 194545 ; free virtual = 543695 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_ooc.xdc] for cell 'inst' +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_ooc.xdc] for cell 'inst' +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/toy_axi_cdc_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/toy_axi_cdc_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/toy_axi_cdc_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/toy_axi_cdc_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +INFO: [Project 1-1714] 33 XPM XDC files have been applied to the design. +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3465.559 ; gain = 0.000 ; free physical = 194063 ; free virtual = 543212 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3465.559 ; gain = 0.000 ; free physical = 194063 ; free virtual = 543212 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 3465.559 ; gain = 45.812 ; free physical = 194088 ; free virtual = 543238 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a100tcsg324-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 3465.559 ; gain = 45.812 ; free physical = 194088 ; free virtual = 543238 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property KEEP_HIERARCHY = SOFT for inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.cdc_wr_rst_busy_ic_3.xpm_cdc_single_inst3 . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.cdc_wr_rst_busy_ic_1.xpm_cdc_single_inst1 . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.cdc_wr_rst_busy_ic_2.xpm_cdc_single_inst2 . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 3465.559 ; gain = 45.812 ; free physical = 194098 ; free virtual = 543248 +--------------------------------------------------------------------------------- +INFO: [Synth 8-802] inferred FSM for state register 'gpregsm1.curr_fwft_state_reg' in module 'rd_fwft' +INFO: [Synth 8-6159] Found Keep on FSM register 'gpregsm1.curr_fwft_state_reg' in module 'rd_fwft', re-encoding will not be performed +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + invalid | 00 | 00 + stage1_valid | 10 | 10 + both_stages_valid | 11 | 11 + stage2_valid | 01 | 01 +--------------------------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 3465.559 ; gain = 45.812 ; free physical = 194087 ; free virtual = 543238 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 10 ++---XORs : + 2 Input 4 Bit XORs := 10 + 2 Input 1 Bit XORs := 110 ++---Registers : + 145 Bit Registers := 2 + 135 Bit Registers := 2 + 61 Bit Registers := 4 + 6 Bit Registers := 2 + 5 Bit Registers := 10 + 4 Bit Registers := 83 + 2 Bit Registers := 15 + 1 Bit Registers := 88 ++---Muxes : + 4 Input 2 Bit Muxes := 5 + 2 Input 2 Bit Muxes := 50 + 5 Input 2 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 5 + 2 Input 1 Bit Muxes := 15 + 4 Input 1 Bit Muxes := 10 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 240 (col length:80) +BRAMs: 270 (col length: RAMB18 80 RAMB36 40) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +WARNING: [Synth 8-7080] Parallel synthesis criteria is not met +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 3465.559 ; gain = 45.812 ; free physical = 194083 ; free virtual = 543235 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Distributed RAM: Preliminary Mapping Report (see note below) ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 61 | RAM32M x 11 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 145 | RAM32M x 25 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 6 | RAM32M x 1 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 61 | RAM32M x 11 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 135 | RAM32M x 23 | ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ + +Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 3465.559 ; gain = 45.812 ; free physical = 193992 ; free virtual = 543142 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 3465.559 ; gain = 45.812 ; free physical = 193967 ; free virtual = 543117 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Distributed RAM: Final Mapping Report ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 61 | RAM32M x 11 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 145 | RAM32M x 25 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 6 | RAM32M x 1 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 61 | RAM32M x 11 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 135 | RAM32M x 23 | ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 3465.559 ; gain = 45.812 ; free physical = 193950 ; free virtual = 543100 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 3465.559 ; gain = 45.812 ; free physical = 193959 ; free virtual = 543110 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 3465.559 ; gain = 45.812 ; free physical = 193959 ; free virtual = 543110 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 3465.559 ; gain = 45.812 ; free physical = 193959 ; free virtual = 543110 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 3465.559 ; gain = 45.812 ; free physical = 193959 ; free virtual = 543110 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 3465.559 ; gain = 45.812 ; free physical = 193962 ; free virtual = 543112 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 3465.559 ; gain = 45.812 ; free physical = 193962 ; free virtual = 543112 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+---------+------+ +| |Cell |Count | ++------+---------+------+ +|1 |LUT1 | 76| +|2 |LUT2 | 66| +|3 |LUT3 | 35| +|4 |LUT4 | 65| +|5 |LUT5 | 10| +|6 |LUT6 | 25| +|7 |RAM32M | 68| +|8 |RAM32X1D | 3| +|9 |FDCE | 130| +|10 |FDPE | 115| +|11 |FDRE | 1081| ++------+---------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 3465.559 ; gain = 45.812 ; free physical = 193962 ; free virtual = 543112 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 206 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3465.559 ; gain = 0.000 ; free physical = 193962 ; free virtual = 543113 +Synthesis Optimization Complete : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 3465.566 ; gain = 45.812 ; free physical = 193962 ; free virtual = 543113 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3465.566 ; gain = 0.000 ; free physical = 194257 ; free virtual = 543408 +INFO: [Netlist 29-17] Analyzing 71 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_ooc.xdc] for cell 'inst' +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_ooc.xdc] for cell 'inst' +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc] for cell 'inst' +INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:16] +WARNING: [Vivado_Tcl 4-2057] Waiver ID 'LUTAR-1' object list specifies likely unusable hierarchical instance 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi'. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:30] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:35] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:35] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:35] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:39] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:39] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:42] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:42] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:45] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:45] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:45] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:49] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:49] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:52] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:52] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:52] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:56] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:56] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:56] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:60] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:60] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:63] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:63] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:66] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:66] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:66] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:70] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:70] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc] for cell 'inst' +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3465.566 ; gain = 0.000 ; free physical = 194271 ; free virtual = 543421 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 71 instances were transformed. + RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 68 instances + RAM32X1D => RAM32X1D (RAMD32(x2)): 3 instances + +Synth Design complete | Checksum: ed94db3a +INFO: [Common 17-83] Releasing license: Synthesis +33 Infos, 130 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:25 . Memory (MB): peak = 3465.566 ; gain = 45.820 ; free physical = 194271 ; free virtual = 543421 +INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 3109.458; main = 2816.219; forked = 442.133 +INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 4507.152; main = 3465.562; forked = 1041.590 +INFO: [Coretcl 2-1174] Renamed 101 cell refs. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-480] Writing timing data to binary archive. +Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3473.562 ; gain = 0.000 ; free physical = 194272 ; free virtual = 543423 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc.dcp' has been generated. +INFO: [Vivado 12-3441] generate_netlist_ip - operation complete +synth_ip: Time (s): cpu = 00:02:09 ; elapsed = 00:02:04 . Memory (MB): peak = 3473.562 ; gain = 1253.406 ; free physical = 194261 ; free virtual = 543413 +INFO: [Common 17-2834] synth_ip peak Physical Memory [PSS] (MB): overall = 3109.458; main = 2816.242; forked = 442.133 +INFO: [Common 17-2834] synth_ip peak Virtual Memory [VSS] (MB): overall = 4507.152; main = 3473.566; forked = 1041.590 +# phase SYNTH_BOARD +BOARD_PHASE SYNTH_BOARD +# if {$flash} {read_verilog -sv $root/build/flash-boot/ToyLinuxChip.sv} else { +# read_verilog -sv $root/build/serial-bound/ToyLinuxChip.sv +# } +# read_verilog -sv $root/build/serial-bound/FpgaMemories.sv +# foreach f [glob $root/board/*.sv] {read_verilog -sv $f} +# set_property verilog_define {SYNTHESIS BUCKYBALL_DISABLE_DPI} [current_fileset] +# read_xdc $root/board/arty_a7.xdc +# read_xdc $root/board/flash_boot.xdc +# synth_design -top toy_a7_top -part xc7a100tcsg324-1 -flatten_hierarchy rebuilt -directive AreaOptimized_high -resource_sharing on -generic FLASH_BOOT=$flash +Command: synth_design -top toy_a7_top -part xc7a100tcsg324-1 -flatten_hierarchy rebuilt -directive AreaOptimized_high -resource_sharing on -generic FLASH_BOOT=0 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 3473.684 ; gain = 0.000 ; free physical = 193905 ; free virtual = 543055 +--------------------------------------------------------------------------------- +WARNING: [Synth 8-6901] identifier 'reset' is used before its declaration [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/toy_a7_top.sv:30] +INFO: [Synth 8-6157] synthesizing module 'toy_a7_top' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/toy_a7_top.sv:1] + Parameter FLASH_BOOT bound to: 0 - type: integer +INFO: [Synth 8-6157] synthesizing module 'IBUF' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:73643] +INFO: [Synth 8-6155] done synthesizing module 'IBUF' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:73643] +INFO: [Synth 8-6157] synthesizing module 'MMCME2_BASE' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82508] + Parameter CLKFBOUT_MULT_F bound to: 10.000000 - type: double + Parameter CLKIN1_PERIOD bound to: 10.000000 - type: double + Parameter CLKOUT0_DIVIDE_F bound to: 40.000000 - type: double + Parameter CLKOUT1_DIVIDE bound to: 6 - type: integer + Parameter CLKOUT2_DIVIDE bound to: 5 - type: integer + Parameter DIVCLK_DIVIDE bound to: 1 - type: integer +INFO: [Synth 8-6155] done synthesizing module 'MMCME2_BASE' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82508] +WARNING: [Synth 8-7071] port 'CLKFBOUTB' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT0B' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT1B' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT2B' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT3' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT3B' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT4' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT5' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT6' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7023] instance 'clock_mmcm' of module 'MMCME2_BASE' has 18 connections declared, but only 9 given [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/toy_a7_top.sv:13] +INFO: [Synth 8-6157] synthesizing module 'BUFG' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951] +INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951] +INFO: [Synth 8-6157] synthesizing module 'toy_a7_platform' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/toy_a7_platform.sv:2] + Parameter FLASH_BOOT bound to: 0 - type: integer +INFO: [Synth 8-6157] synthesizing module 'uart_rx' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_rx.sv:3] + Parameter DIVISOR bound to: 25 - type: integer +INFO: [Synth 8-6155] done synthesizing module 'uart_rx' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_rx.sv:3] +INFO: [Synth 8-6157] synthesizing module 'uart_tx' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_tx.sv:1] + Parameter DIVISOR bound to: 25 - type: integer +INFO: [Synth 8-6155] done synthesizing module 'uart_tx' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_tx.sv:1] +INFO: [Synth 8-6157] synthesizing module 'ddr_uart_loader' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:5] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:99] +INFO: [Synth 8-6155] done synthesizing module 'ddr_uart_loader' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:5] +INFO: [Synth 8-6157] synthesizing module 'ToyLinuxChip' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103817] +INFO: [Synth 8-6157] synthesizing module 'ToyLinuxSystem' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:102569] +INFO: [Synth 8-6157] synthesizing module 'IntSyncAsyncCrossingSink_n1x1' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:61] +INFO: [Synth 8-6157] synthesizing module 'SynchronizerShiftReg_w1_d3' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:48] +INFO: [Synth 8-6157] synthesizing module 'NonSyncResetSynchronizerPrimitiveShiftReg_d3' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31] +INFO: [Synth 8-6155] done synthesizing module 'NonSyncResetSynchronizerPrimitiveShiftReg_d3' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31] +INFO: [Synth 8-6155] done synthesizing module 'SynchronizerShiftReg_w1_d3' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:48] +INFO: [Synth 8-6155] done synthesizing module 'IntSyncAsyncCrossingSink_n1x1' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:61] +INFO: [Synth 8-6157] synthesizing module 'IntSyncCrossingSource_n1x1' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103] +INFO: [Synth 8-6157] synthesizing module 'AsyncResetRegVec_w1_i0' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:74] +INFO: [Synth 8-6155] done synthesizing module 'AsyncResetRegVec_w1_i0' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:74] +INFO: [Synth 8-6155] done synthesizing module 'IntSyncCrossingSource_n1x1' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103] +INFO: [Synth 8-6157] synthesizing module 'SystemBus' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:9400] +INFO: [Synth 8-6157] synthesizing module 'FixedClockBroadcast_3' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:118] +INFO: [Synth 8-6155] done synthesizing module 'FixedClockBroadcast_3' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:118] +INFO: [Synth 8-6157] synthesizing module 'TLXbar_sbus_i2_o3_a32d128s3k1z4c' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:2434] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:3011] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:139] +INFO: [Synth 8-6157] synthesizing module 'plusarg_reader' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104301] + Parameter FORMAT bound to: tilelink_timeout=%d - type: string + Parameter WIDTH bound to: 32 - type: integer + Parameter DEFAULT bound to: 32'b00000000000000000000000000000000 +INFO: [Synth 8-6155] done synthesizing module 'plusarg_reader' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104301] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:139] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:3033] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_1' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:987] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_1' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:987] +INFO: [Synth 8-6155] done synthesizing module 'TLXbar_sbus_i2_o3_a32d128s3k1z4c' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:2434] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_sbus_to_bus_named_cbus' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4386] +INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget16' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4218] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4310] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_2' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:3195] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_2' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:3195] +INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a28d128s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4151] +INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a28d128s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4151] +INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget16' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4218] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_sbus_to_bus_named_cbus' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4386] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8623] +INFO: [Synth 8-6157] synthesizing module 'AXI4Buffer' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4891] +INFO: [Synth 8-6157] synthesizing module 'Queue2_AXI4BundleAW' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4497] +INFO: [Synth 8-6157] synthesizing module 'ram_2x58' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4478] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x58' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4478] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_AXI4BundleAW' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4497] +INFO: [Synth 8-6157] synthesizing module 'Queue2_AXI4BundleW' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4600] +INFO: [Synth 8-6157] synthesizing module 'ram_2x73' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4581] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x73' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4581] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_AXI4BundleW' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4600] +INFO: [Synth 8-6157] synthesizing module 'Queue2_AXI4BundleB' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4676] +INFO: [Synth 8-6157] synthesizing module 'ram_2x4' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4657] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x4' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4657] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_AXI4BundleB' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4676] +INFO: [Synth 8-6157] synthesizing module 'Queue2_AXI4BundleAR' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4729] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_AXI4BundleAR' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4729] +INFO: [Synth 8-6157] synthesizing module 'Queue2_AXI4BundleR' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4832] +INFO: [Synth 8-6157] synthesizing module 'ram_2x69' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4813] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x69' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4813] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_AXI4BundleR' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4832] +INFO: [Synth 8-6155] done synthesizing module 'AXI4Buffer' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4891] +INFO: [Synth 8-6157] synthesizing module 'AXI4UserYanker' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5178] +INFO: [Synth 8-6157] synthesizing module 'Queue2_BundleMap' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5086] +INFO: [Synth 8-6157] synthesizing module 'ram_2x8' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5067] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x8' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5067] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_BundleMap' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5086] +INFO: [Synth 8-6157] synthesizing module 'Queue1_BundleMap' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5143] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_BundleMap' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5143] +INFO: [Synth 8-6155] done synthesizing module 'AXI4UserYanker' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5178] +INFO: [Synth 8-6157] synthesizing module 'AXI4Deinterleaver' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5631] +INFO: [Synth 8-6157] synthesizing module 'Queue8_AXI4BundleR' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5559] +INFO: [Synth 8-6157] synthesizing module 'ram_8x77' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5540] +INFO: [Synth 8-6155] done synthesizing module 'ram_8x77' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5540] +INFO: [Synth 8-6155] done synthesizing module 'Queue8_AXI4BundleR' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5559] +INFO: [Synth 8-6155] done synthesizing module 'AXI4Deinterleaver' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5631] +INFO: [Synth 8-6157] synthesizing module 'AXI4IdIndexer' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:6073] +INFO: [Synth 8-6155] done synthesizing module 'AXI4IdIndexer' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:6073] +INFO: [Synth 8-6157] synthesizing module 'TLToAXI4' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7148] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7423] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_3' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:6219] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_3' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:6219] +INFO: [Synth 8-6157] synthesizing module 'Queue1_AXI4BundleW' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7048] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_AXI4BundleW' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7048] +INFO: [Synth 8-6157] synthesizing module 'Queue1_AXI4BundleARW' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7082] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_AXI4BundleARW' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7082] +INFO: [Synth 8-6155] done synthesizing module 'TLToAXI4' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7148] +INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget16_2' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8463] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8551] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_4' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7529] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_4' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7529] +INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a31d128s3k1z3u' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8396] +INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a31d128s3k1z3u' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8396] +INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget16_2' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8463] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8623] +INFO: [Synth 8-6155] done synthesizing module 'SystemBus' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:9400] +INFO: [Synth 8-6157] synthesizing module 'PeripheryBus_cbus' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19330] +INFO: [Synth 8-6157] synthesizing module 'FixedClockBroadcast_4' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10050] +INFO: [Synth 8-6155] done synthesizing module 'FixedClockBroadcast_4' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10050] +INFO: [Synth 8-6157] synthesizing module 'TLXbar_cbus_out_i1_o4_a28d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10975] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:11207] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_5' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10073] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_5' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10073] +INFO: [Synth 8-6155] done synthesizing module 'TLXbar_cbus_out_i1_o4_a28d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10975] +INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a28d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12399] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12453] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_6' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:11288] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_6' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:11288] +INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleA_a28d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12221] +INFO: [Synth 8-6157] synthesizing module 'ram_2x114' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12202] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x114' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12202] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleA_a28d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12221] +INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleD_a28d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12320] +INFO: [Synth 8-6157] synthesizing module 'ram_2x79' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12301] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x79' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12301] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleD_a28d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12320] +INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a28d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12399] +INFO: [Synth 8-6157] synthesizing module 'TLAtomicAutomata_cbus' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:13449] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:13829] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_7' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12534] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_7' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12534] +INFO: [Synth 8-6155] done synthesizing module 'TLAtomicAutomata_cbus' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:13449] +INFO: [Synth 8-6157] synthesizing module 'ErrorDeviceWrapper' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16155] +INFO: [Synth 8-6157] synthesizing module 'TLError' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14846] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14907] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_8' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:13973] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_8' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:13973] +INFO: [Synth 8-6157] synthesizing module 'Queue1_TLBundleA_a14d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14799] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_TLBundleA_a14d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14799] +INFO: [Synth 8-6155] done synthesizing module 'TLError' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14846] +INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a14d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16028] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16078] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_9' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14953] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_9' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14953] +INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleA_a14d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15876] +INFO: [Synth 8-6157] synthesizing module 'ram_2x100' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15857] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x100' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15857] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleA_a14d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15876] +INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleD_a14d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15955] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleD_a14d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15955] +INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a14d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16028] +INFO: [Synth 8-6155] done synthesizing module 'ErrorDeviceWrapper' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16155] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_clint' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17261] +INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_CLINT' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17081] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17199] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_10' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16258] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_10' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16258] +INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a26d64s3k1z3u' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17017] +INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a26d64s3k1z3u' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17017] +INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_CLINT' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17081] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_clint' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17261] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_plic' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18350] +INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_PLIC' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18170] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18288] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_11' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17336] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_11' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17336] +INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a28d64s3k1z3u' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18106] +INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a28d64s3k1z3u' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18106] +INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_PLIC' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18170] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_plic' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18350] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_bootrom' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19263] +INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_bootrom' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19104] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19205] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_12' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18425] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19035] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_12' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18425] +INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a17d64s3k1z3u' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19040] +INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a17d64s3k1z3u' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19040] +INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_bootrom' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19104] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_bootrom' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19263] +INFO: [Synth 8-6155] done synthesizing module 'PeripheryBus_cbus' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19330] +INFO: [Synth 8-6157] synthesizing module 'MemoryBus' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:24031] +INFO: [Synth 8-6157] synthesizing module 'ProbePicker' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20610] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20649] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_13' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19882] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_13' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19882] +INFO: [Synth 8-6155] done synthesizing module 'ProbePicker' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20610] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:23555] +INFO: [Synth 8-6157] synthesizing module 'AXI4UserYanker_1' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20764] +INFO: [Synth 8-6157] synthesizing module 'Queue2_BundleMap_6' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20707] +INFO: [Synth 8-6157] synthesizing module 'ram_2x10' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20688] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x10' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20688] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_BundleMap_6' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20707] +INFO: [Synth 8-6155] done synthesizing module 'AXI4UserYanker_1' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20764] +INFO: [Synth 8-6157] synthesizing module 'AXI4IdIndexer_1' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:21713] +INFO: [Synth 8-6155] done synthesizing module 'AXI4IdIndexer_1' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:21713] +INFO: [Synth 8-6157] synthesizing module 'TLToAXI4_1' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22687] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:23450] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_14' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:21859] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_14' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:21859] +INFO: [Synth 8-6157] synthesizing module 'Queue1_AXI4BundleW_1' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22587] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_AXI4BundleW_1' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22587] +INFO: [Synth 8-6157] synthesizing module 'Queue1_AXI4BundleARW_1' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22621] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_AXI4BundleARW_1' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22621] +INFO: [Synth 8-6155] done synthesizing module 'TLToAXI4_1' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22687] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:23555] +INFO: [Synth 8-6155] done synthesizing module 'MemoryBus' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:24031] +INFO: [Synth 8-6157] synthesizing module 'CoherenceManagerWrapper' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27491] +INFO: [Synth 8-6157] synthesizing module 'TLBroadcast' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:26100] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:26482] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_15' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:24349] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_15' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:24349] +INFO: [Synth 8-6157] synthesizing module 'BroadcastFilter' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25732] +INFO: [Common 17-14] Message 'Synth 8-6157' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-6155] done synthesizing module 'BroadcastFilter' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25732] +INFO: [Synth 8-6155] done synthesizing module 'ram_4x144' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25756] +INFO: [Synth 8-6155] done synthesizing module 'Queue4_TLBroadcastData' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25775] +INFO: [Synth 8-6155] done synthesizing module 'TLBroadcastTracker' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25828] +INFO: [Synth 8-6155] done synthesizing module 'TLBroadcastTracker_1' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25964] +INFO: [Synth 8-6155] done synthesizing module 'TLBroadcast' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:26100] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27453] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_16' (0#1) [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:26686] +INFO: [Common 17-14] Message 'Synth 8-6155' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29794] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29834] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43249] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43271] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44089] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44825] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:45961] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47133] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68592] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68606] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68620] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:82885] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:82084] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86970] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85223] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85231] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:90541] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:90573] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:90605] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:90637] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:90669] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:90701] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:90733] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98928] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98950] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99569] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99575] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99581] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100308] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101303] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:102505] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101968] + Parameter FLASH_BOOT bound to: 0 - type: integer +WARNING: [Synth 8-6014] Unused sequential element rmPost_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52403] +WARNING: [Synth 8-6014] Unused sequential element rmPost_pipe_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52405] +WARNING: [Synth 8-6014] Unused sequential element rm_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52416] +WARNING: [Synth 8-6014] Unused sequential element rm_pipe_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52418] +WARNING: [Synth 8-6014] Unused sequential element rm_pipe_pipe_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52420] +WARNING: [Synth 8-6014] Unused sequential element tag_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52422] +WARNING: [Synth 8-6014] Unused sequential element tag_pipe_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52424] +WARNING: [Synth 8-6014] Unused sequential element tag_pipe_pipe_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52426] +WARNING: [Synth 8-6014] Unused sequential element ex_ctrl_rxs1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:61288] +WARNING: [Synth 8-6014] Unused sequential element ex_ctrl_rfs1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62163] +WARNING: [Synth 8-6014] Unused sequential element ex_ctrl_rfs2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62183] +WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rxs2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62375] +WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rxs1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62376] +WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rfs1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62378] +WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rfs2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62379] +WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rxs2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62390] +WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rxs1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62391] +WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rfs1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62393] +WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rfs2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62394] +WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd0val_REG_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62497] +WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd0val_REG_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62498] +WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd1val_REG_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62499] +WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd1val_REG_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62500] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:63220] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:63221] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:63222] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:63223] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:63224] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_5_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:63225] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_6_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:63226] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_7_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:63227] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_8_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:63228] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_9_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:63229] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_10_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:63230] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_11_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:63231] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_12_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:63232] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_13_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:63233] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_14_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:63234] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_15_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:63235] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_2_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76912] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_2_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76914] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76916] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76919] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76922] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76926] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76930] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76935] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76940] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76946] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76952] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76959] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_2_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76968] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76970] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76973] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76977] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76982] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76988] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_84_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77024] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_85_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77026] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_87_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77029] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_90_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77033] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_94_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77038] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_99_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77044] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_105_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77052] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_106_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77054] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_108_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77057] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_111_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77061] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_115_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77066] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_120_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77072] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_dataflow_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76917] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_propagate_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76920] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_dataflow_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76923] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_dataflow_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76924] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_propagate_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76927] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_propagate_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76928] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_dataflow_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76931] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_dataflow_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76932] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_dataflow_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76933] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_propagate_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76936] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_propagate_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76937] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_propagate_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76938] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_dataflow_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76941] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_dataflow_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76942] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_dataflow_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76943] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_dataflow_r_4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76944] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_propagate_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76947] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_propagate_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76948] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_propagate_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76949] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_propagate_r_4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76950] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76953] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76954] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76955] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76956] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_5_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76957] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76960] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76961] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76962] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76963] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_5_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76964] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_shift_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76971] +INFO: [Common 17-14] Message 'Synth 8-6014' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [Synth 8-3936] Found unconnected internal register 's2_req_tag_reg' and it is trimmed from '8' to '6' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93740] +WARNING: [Synth 8-3917] design toy_a7_top has port flash_wp_n driven by constant 1 +WARNING: [Synth 8-3917] design toy_a7_top has port flash_hold_n driven by constant 1 +WARNING: [Synth 8-7129] Port wdata[63] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[62] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[61] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[60] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[59] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[58] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[57] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[56] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[55] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[54] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[53] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[52] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[51] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[50] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[49] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[48] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[47] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[46] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[45] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[44] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[43] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[42] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[41] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[40] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[39] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[38] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[37] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[36] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[35] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[34] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[33] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[32] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wstrb[7] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wstrb[6] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wstrb[5] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wstrb[4] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port flash_miso in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port flash_recovery in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port load_addr[3] in module loader_axi is either unconnected or has no load +WARNING: [Synth 8-7129] Port load_addr[2] in module loader_axi is either unconnected or has no load +WARNING: [Synth 8-7129] Port load_addr[1] in module loader_axi is either unconnected or has no load +WARNING: [Synth 8-7129] Port load_addr[0] in module loader_axi is either unconnected or has no load +WARNING: [Synth 8-7129] Port clock in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port reset in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_ready in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_valid in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_opcode[2] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_opcode[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_opcode[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_param[2] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_param[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_param[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_size[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_size[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[6] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[5] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[4] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[3] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[2] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[16] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[15] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[14] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[13] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[12] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[11] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[10] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[9] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[8] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[7] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[6] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[5] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[4] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[3] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[2] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[7] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[6] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[5] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[4] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[3] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[2] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_corrupt in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_ready in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_valid in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_size[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_size[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_source[6] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_source[5] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_source[4] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_source[3] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_source[2] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_source[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_source[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port clock in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port reset in module TLMonitor_28 is either unconnected or has no load +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 3814.555 ; gain = 340.871 ; free physical = 193375 ; free virtual = 542534 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 3829.398 ; gain = 355.715 ; free physical = 193432 ; free virtual = 542590 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 3829.398 ; gain = 355.715 ; free physical = 193432 ; free virtual = 542590 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 3829.398 ; gain = 0.000 ; free physical = 193267 ; free virtual = 542422 +INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc] for cell 'ddr_controller' +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc] for cell 'ddr_controller' +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc/toy_axi_cdc_in_context.xdc] for cell 'memory_cdc' +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc/toy_axi_cdc_in_context.xdc] for cell 'memory_cdc' +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/arty_a7.xdc] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/arty_a7.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/arty_a7.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/toy_a7_top_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/toy_a7_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/flash_boot.xdc] +CRITICAL WARNING: [Designutils 20-1307] Command 'if' is not supported in the xdc constraint file. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/flash_boot.xdc:11] +CRITICAL WARNING: [Designutils 20-1307] Command 'if' is not supported in the xdc constraint file. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/flash_boot.xdc:15] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/flash_boot.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/flash_boot.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/toy_a7_top_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/toy_a7_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +INFO: [Timing 38-2] Deriving generated clocks +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4001.055 ; gain = 0.000 ; free physical = 193330 ; free virtual = 542485 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 1 instances were transformed. + MMCME2_BASE => MMCME2_ADV: 1 instance + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.12 . Memory (MB): peak = 4004.973 ; gain = 0.000 ; free physical = 193329 ; free virtual = 542484 +WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'memory_cdc' at clock pin 'm_axi_aclk' is different from the actual clock period '12.000', this can lead to different synthesis results. +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:34 ; elapsed = 00:00:30 . Memory (MB): peak = 4004.973 ; gain = 531.289 ; free physical = 192007 ; free virtual = 541164 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a100tcsg324-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:34 ; elapsed = 00:00:30 . Memory (MB): peak = 4004.973 ; gain = 531.289 ; free physical = 192007 ; free virtual = 541164 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 2). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 3). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[10]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 4). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[10]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 5). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[11]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 6). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[11]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 7). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[12]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 8). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[12]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 9). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[13]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 10). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[13]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 11). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[1]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 12). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[1]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 13). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[2]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 14). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[2]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 15). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[3]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 16). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[3]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 17). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[4]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 18). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[4]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 19). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[5]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 20). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[5]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 21). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[6]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 22). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[6]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 23). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[7]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 24). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[7]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 25). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[8]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 26). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[8]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 27). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[9]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 28). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[9]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 29). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_ba[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 30). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_ba[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 31). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_ba[1]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 32). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_ba[1]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 33). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_ba[2]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 34). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_ba[2]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 35). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_cas_n. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 36). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_cas_n. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 37). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_ck_n[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 38). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_ck_n[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 39). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_ck_p[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 40). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_ck_p[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 41). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_cke[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 42). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_cke[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 43). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_cs_n[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 44). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_cs_n[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 45). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dm[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 46). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dm[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 47). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dm[1]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 48). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dm[1]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 49). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 50). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 51). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[10]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 52). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[10]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 53). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[11]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 54). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[11]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 55). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[12]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 56). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[12]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 57). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[13]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 58). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[13]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 59). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[14]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 60). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[14]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 61). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[15]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 62). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[15]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 63). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[1]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 64). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[1]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 65). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[2]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 66). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[2]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 67). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[3]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 68). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[3]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 69). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[4]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 70). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[4]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 71). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[5]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 72). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[5]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 73). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[6]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 74). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[6]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 75). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[7]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 76). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[7]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 77). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[8]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 78). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[8]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 79). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[9]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 80). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[9]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 81). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dqs_n[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 82). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dqs_n[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 83). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dqs_n[1]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 84). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dqs_n[1]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 85). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dqs_p[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 86). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dqs_p[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 87). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dqs_p[1]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 88). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dqs_p[1]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 89). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_odt[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 90). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_odt[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 91). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_ras_n. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 92). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_ras_n. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 93). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_reset_n. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 94). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_reset_n. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 95). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_we_n. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 96). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_we_n. (constraint file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 97). +Applied set_property KEEP_HIERARCHY = SOFT for ddr_controller. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for memory_cdc. (constraint file auto generated constraint). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:35 ; elapsed = 00:00:30 . Memory (MB): peak = 4004.973 ; gain = 531.289 ; free physical = 191903 ; free virtual = 541060 +--------------------------------------------------------------------------------- +INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'uart_rx' +WARNING: [Synth 8-3936] Found unconnected internal register 'cam_a_0_bits_opcode_reg' and it is trimmed from '3' to '1' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:13813] +WARNING: [Synth 8-3936] Found unconnected internal register 'ram_reg' and it is trimmed from '100' to '13' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14825] +WARNING: [Synth 8-3936] Found unconnected internal register 'req_addr_reg' and it is trimmed from '40' to '32' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30468] +WARNING: [Synth 8-3936] Found unconnected internal register 'r_raddr_reg' and it is trimmed from '11' to '4' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36089] +WARNING: [Synth 8-3936] Found unconnected internal register 'in_fmt_reg' and it is trimmed from '2' to '1' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50199] +WARNING: [Synth 8-3936] Found unconnected internal register 'mem_reg_inst_reg' and it is trimmed from '32' to '12' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:54509] +WARNING: [Synth 8-3936] Found unconnected internal register 'ex_reg_inst_reg' and it is trimmed from '32' to '28' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:54256] +WARNING: [Synth 8-3936] Found unconnected internal register 'reg_mcounteren_reg' and it is trimmed from '32' to '3' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:55509] +WARNING: [Synth 8-3936] Found unconnected internal register 'reg_scounteren_reg' and it is trimmed from '32' to '3' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:55511] +WARNING: [Synth 8-3936] Found unconnected internal register 'reg_mideleg_reg' and it is trimmed from '64' to '14' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:55493] +WARNING: [Synth 8-3936] Found unconnected internal register 'reg_medeleg_reg' and it is trimmed from '64' to '16' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:55497] +WARNING: [Synth 8-3936] Found unconnected internal register 'wb_reg_raw_inst_reg' and it is trimmed from '32' to '16' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62407] +WARNING: [Synth 8-3936] Found unconnected internal register 'mem_reg_raw_inst_reg' and it is trimmed from '32' to '16' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62407] +WARNING: [Synth 8-3936] Found unconnected internal register 'ex_reg_raw_inst_reg' and it is trimmed from '32' to '16' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62438] +WARNING: [Synth 8-3936] Found unconnected internal register 'iter_reg_reg' and it is trimmed from '34' to '29' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84823] +WARNING: [Synth 8-3936] Found unconnected internal register 'iter_cmd_reg' and it is trimmed from '34' to '29' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84821] +WARNING: [Synth 8-3936] Found unconnected internal register 'reqReg_vaddr_reg' and it is trimmed from '64' to '39' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86206] +INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'MemConfiger' +INFO: [Synth 8-802] inferred FSM for state register 'ws_reg' in module 'axi_fullwidth' +INFO: [Synth 8-802] inferred FSM for state register 'rs_reg' in module 'axi_fullwidth' +INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'loader_axi' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + IDLE | 000 | 000 + START | 001 | 001 + DATA | 010 | 010 + STOP | 011 | 011 + WAIT_HIGH | 100 | 100 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'uart_rx' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + iSTATE3 | 00000001 | 000 + iSTATE2 | 00000010 | 001 + iSTATE6 | 00000100 | 010 + iSTATE4 | 00010000 | 011 + iSTATE1 | 00100000 | 100 + iSTATE5 | 00001000 | 101 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'MemConfiger' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + P_DA814840 | 00 | 00 + P_DA814540 | 01 | 01 + P_DA814930 | 10 | 10 + P_DA7E9800 | 11 | 11 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'ws_reg' using encoding 'sequential' in module 'axi_fullwidth' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + R_IDLE | 00 | 00 + R_SEND | 01 | 01 + R_RESP | 10 | 10 + R_RETURN | 11 | 11 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'rs_reg' using encoding 'sequential' in module 'axi_fullwidth' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + IDLE | 000001 | 000 + SEND_W | 100000 | 001 + WAIT_B | 010000 | 010 + SEND_R | 001000 | 011 + WAIT_R | 000100 | 100 + RELEASE | 000010 | 101 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'loader_axi' +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:47 ; elapsed = 00:00:44 . Memory (MB): peak = 4004.973 ; gain = 531.289 ; free physical = 188316 ; free virtual = 537474 +--------------------------------------------------------------------------------- +INFO: [Synth 8-223] decloning instance 'platform/chip/system/sbus/system_bus_xbar/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/sbus/system_bus_xbar/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/sbus/system_bus_xbar/monitor_1/plusarg_reader' (plusarg_reader) to 'platform/chip/system/sbus/system_bus_xbar/monitor_1/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/sbus/coupler_to_bus_named_cbus/widget/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/sbus/coupler_to_bus_named_cbus/widget/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/sbus/coupler_to_port_named_mmio_port_axi4/tl2axi4/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/sbus/coupler_to_port_named_mmio_port_axi4/tl2axi4/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/sbus/coupler_to_port_named_mmio_port_axi4/widget/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/sbus/coupler_to_port_named_mmio_port_axi4/widget/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/out_xbar/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/out_xbar/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/buffer/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/buffer/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/atomics/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/atomics/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/wrapped_error_device/error/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/wrapped_error_device/error/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/wrapped_error_device/buffer/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/wrapped_error_device/buffer/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/coupler_to_clint/fragmenter/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/coupler_to_clint/fragmenter/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/coupler_to_plic/fragmenter/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/coupler_to_plic/fragmenter/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/coupler_to_bootrom/fragmenter/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/coupler_to_bootrom/fragmenter/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/mbus/picker/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/mbus/picker/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/mbus/coupler_to_memory_controller_port_named_axi4/tl2axi4/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/mbus/coupler_to_memory_controller_port_named_axi4/tl2axi4/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/coh_wrapper/broadcast_1/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/coh_wrapper/broadcast_1/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/coh_wrapper/binder/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/coh_wrapper/binder/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/tlMasterXbar/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/tlMasterXbar/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/tlMasterXbar/monitor_1/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/tlMasterXbar/monitor_1/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/dtlb/mpu_ppn_barrier' (OptimizationBarrier_TLBEntryData) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/dtlb/entries_barrier_12' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/tlb/mpu_ppn_barrier' (OptimizationBarrier_TLBEntryData) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/tlb/entries_barrier_12' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/xbar/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/xbar/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/xbar/monitor_1/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/xbar/monitor_1/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer_1/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer_1/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/widget_3/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/widget_3/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer_2/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer_2/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/buffer/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/buffer/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/buffer/monitor_1/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/buffer/monitor_1/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/intsource' (IntSyncCrossingSource_n1x1) to 'platform/chip/system/tile_prci_domain/intsource_2' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/clint_domain/clint/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/clint_domain/clint/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/plic_domain/plic/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/plic_domain/plic/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/bootrom_domain/bootrom/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/bootrom_domain/bootrom/monitor/plusarg_reader_1' +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 109 Bit Adders := 1 + 2 Input 107 Bit Adders := 1 + 2 Input 73 Bit Adders := 1 + 3 Input 65 Bit Adders := 1 + 2 Input 64 Bit Adders := 21 + 3 Input 64 Bit Adders := 2 + 3 Input 58 Bit Adders := 1 + 2 Input 58 Bit Adders := 2 + 2 Input 55 Bit Adders := 4 + 2 Input 48 Bit Adders := 1 + 2 Input 40 Bit Adders := 3 + 3 Input 39 Bit Adders := 5 + 2 Input 39 Bit Adders := 3 + 2 Input 37 Bit Adders := 1 + 2 Input 34 Bit Adders := 1 + 2 Input 33 Bit Adders := 3 + 2 Input 32 Bit Adders := 18 + 3 Input 32 Bit Adders := 1 + 2 Input 30 Bit Adders := 8 + 3 Input 29 Bit Adders := 1 + 2 Input 28 Bit Adders := 1 + 2 Input 26 Bit Adders := 4 + 2 Input 20 Bit Adders := 64 + 2 Input 19 Bit Adders := 2 + 2 Input 17 Bit Adders := 2 + 3 Input 16 Bit Adders := 1 + 2 Input 16 Bit Adders := 12 + 2 Input 15 Bit Adders := 4 + 2 Input 14 Bit Adders := 7 + 4 Input 14 Bit Adders := 1 + 2 Input 13 Bit Adders := 6 + 3 Input 13 Bit Adders := 2 + 2 Input 12 Bit Adders := 12 + 3 Input 12 Bit Adders := 1 + 2 Input 11 Bit Adders := 4 + 2 Input 10 Bit Adders := 7 + 4 Input 10 Bit Adders := 1 + 3 Input 10 Bit Adders := 1 + 2 Input 9 Bit Adders := 14 + 3 Input 9 Bit Adders := 4 + 2 Input 8 Bit Adders := 16 + 3 Input 8 Bit Adders := 8 + 2 Input 7 Bit Adders := 6 + 3 Input 7 Bit Adders := 1 + 2 Input 6 Bit Adders := 13 + 3 Input 6 Bit Adders := 2 + 2 Input 5 Bit Adders := 9 + 2 Input 4 Bit Adders := 60 + 5 Input 4 Bit Adders := 1 + 4 Input 4 Bit Adders := 4 + 2 Input 3 Bit Adders := 65 + 3 Input 3 Bit Adders := 7 + 2 Input 2 Bit Adders := 70 + 3 Input 2 Bit Adders := 5 + 4 Input 2 Bit Adders := 1 + 3 Input 1 Bit Adders := 3 + 2 Input 1 Bit Adders := 126 + 4 Input 1 Bit Adders := 39 ++---XORs : + 2 Input 65 Bit XORs := 1 + 2 Input 64 Bit XORs := 5 + 2 Input 32 Bit XORs := 8 + 2 Input 29 Bit XORs := 8 + 2 Input 27 Bit XORs := 6 + 2 Input 25 Bit XORs := 16 + 2 Input 20 Bit XORs := 8 + 2 Input 18 Bit XORs := 8 + 2 Input 16 Bit XORs := 18 + 2 Input 11 Bit XORs := 8 + 2 Input 10 Bit XORs := 3 + 2 Input 4 Bit XORs := 3 + 2 Input 3 Bit XORs := 11 + 2 Input 2 Bit XORs := 8 + 2 Input 1 Bit XORs := 14 + 3 Input 1 Bit XORs := 2 + 4 Input 1 Bit XORs := 2 ++---Registers : + 1269 Bit Registers := 1 + 145 Bit Registers := 1 + 130 Bit Registers := 1 + 128 Bit Registers := 9 + 107 Bit Registers := 1 + 106 Bit Registers := 3 + 105 Bit Registers := 1 + 73 Bit Registers := 1 + 72 Bit Registers := 1 + 67 Bit Registers := 1 + 65 Bit Registers := 14 + 64 Bit Registers := 184 + 62 Bit Registers := 2 + 58 Bit Registers := 2 + 56 Bit Registers := 1 + 55 Bit Registers := 5 + 53 Bit Registers := 3 + 44 Bit Registers := 5 + 42 Bit Registers := 74 + 40 Bit Registers := 21 + 39 Bit Registers := 19 + 34 Bit Registers := 2 + 32 Bit Registers := 115 + 31 Bit Registers := 2 + 30 Bit Registers := 8 + 29 Bit Registers := 2 + 28 Bit Registers := 5 + 27 Bit Registers := 34 + 26 Bit Registers := 4 + 24 Bit Registers := 1 + 23 Bit Registers := 4 + 21 Bit Registers := 8 + 20 Bit Registers := 293 + 19 Bit Registers := 2 + 17 Bit Registers := 2 + 16 Bit Registers := 54 + 14 Bit Registers := 1 + 13 Bit Registers := 8 + 12 Bit Registers := 1 + 11 Bit Registers := 1 + 10 Bit Registers := 140 + 9 Bit Registers := 12 + 8 Bit Registers := 434 + 7 Bit Registers := 27 + 6 Bit Registers := 11 + 5 Bit Registers := 113 + 4 Bit Registers := 193 + 3 Bit Registers := 234 + 2 Bit Registers := 127 + 1 Bit Registers := 1664 ++---Multipliers : + 53x53 Multipliers := 1 + 73x73 Multipliers := 1 + 16x32 Multipliers := 6 + 16x39 Multipliers := 2 + 16x37 Multipliers := 1 ++---RAMs : + 64K Bit (1024 X 64 bit) RAMs := 8 + 8K Bit (256 X 32 bit) RAMs := 8 + 8K Bit (128 X 64 bit) RAMs := 8 + 2K Bit (16 X 128 bit) RAMs := 1 ++---Muxes : + 2 Input 130 Bit Muxes := 4 + 2 Input 128 Bit Muxes := 34 + 4 Input 128 Bit Muxes := 1 + 2 Input 109 Bit Muxes := 1 + 2 Input 108 Bit Muxes := 1 + 2 Input 65 Bit Muxes := 33 + 4 Input 65 Bit Muxes := 4 + 2 Input 64 Bit Muxes := 303 + 3 Input 64 Bit Muxes := 2 + 4 Input 64 Bit Muxes := 26 + 8 Input 64 Bit Muxes := 3 + 2 Input 62 Bit Muxes := 1 + 2 Input 61 Bit Muxes := 2 + 2 Input 58 Bit Muxes := 2 + 2 Input 56 Bit Muxes := 9 + 2 Input 55 Bit Muxes := 11 + 2 Input 54 Bit Muxes := 3 + 2 Input 53 Bit Muxes := 2 + 2 Input 52 Bit Muxes := 10 + 2 Input 51 Bit Muxes := 2 + 2 Input 48 Bit Muxes := 2 + 4 Input 44 Bit Muxes := 1 + 2 Input 44 Bit Muxes := 6 + 4 Input 42 Bit Muxes := 16 + 2 Input 40 Bit Muxes := 25 + 2 Input 39 Bit Muxes := 19 + 5 Input 39 Bit Muxes := 1 + 3 Input 39 Bit Muxes := 1 + 2 Input 38 Bit Muxes := 1 + 2 Input 34 Bit Muxes := 57 + 2 Input 33 Bit Muxes := 1 + 2 Input 32 Bit Muxes := 129 + 3 Input 32 Bit Muxes := 2 + 4 Input 32 Bit Muxes := 4 + 13 Input 32 Bit Muxes := 2 + 10 Input 32 Bit Muxes := 1 + 8 Input 32 Bit Muxes := 1 + 2 Input 31 Bit Muxes := 4 + 2 Input 30 Bit Muxes := 8 + 2 Input 29 Bit Muxes := 5 + 2 Input 28 Bit Muxes := 13 + 2 Input 27 Bit Muxes := 5 + 2 Input 26 Bit Muxes := 15 + 2 Input 25 Bit Muxes := 6 + 2 Input 24 Bit Muxes := 2 + 2 Input 23 Bit Muxes := 11 + 2 Input 22 Bit Muxes := 388 + 2 Input 21 Bit Muxes := 6 + 2 Input 20 Bit Muxes := 621 + 2 Input 19 Bit Muxes := 11 + 4 Input 18 Bit Muxes := 1 + 2 Input 17 Bit Muxes := 1 + 4 Input 16 Bit Muxes := 1 + 2 Input 16 Bit Muxes := 134 + 13 Input 16 Bit Muxes := 3 + 10 Input 16 Bit Muxes := 1 + 8 Input 16 Bit Muxes := 1 + 2 Input 14 Bit Muxes := 12 + 2 Input 13 Bit Muxes := 23 + 2 Input 12 Bit Muxes := 21 + 5 Input 12 Bit Muxes := 1 + 2 Input 11 Bit Muxes := 8 + 2 Input 10 Bit Muxes := 53 + 2 Input 9 Bit Muxes := 41 + 4 Input 9 Bit Muxes := 1 + 13 Input 9 Bit Muxes := 2 + 2 Input 8 Bit Muxes := 370 + 6 Input 8 Bit Muxes := 1 + 3 Input 8 Bit Muxes := 1 + 5 Input 8 Bit Muxes := 1 + 13 Input 8 Bit Muxes := 3 + 4 Input 8 Bit Muxes := 2 + 2 Input 7 Bit Muxes := 28 + 4 Input 7 Bit Muxes := 1 + 7 Input 7 Bit Muxes := 2 + 6 Input 7 Bit Muxes := 1 + 2 Input 6 Bit Muxes := 32 + 4 Input 6 Bit Muxes := 1 + 5 Input 6 Bit Muxes := 1 + 6 Input 6 Bit Muxes := 1 + 2 Input 5 Bit Muxes := 103 + 4 Input 5 Bit Muxes := 1 + 5 Input 5 Bit Muxes := 1 + 3 Input 5 Bit Muxes := 1 + 4 Input 4 Bit Muxes := 10 + 2 Input 4 Bit Muxes := 198 + 3 Input 4 Bit Muxes := 5 + 5 Input 4 Bit Muxes := 1 + 8 Input 4 Bit Muxes := 4 + 6 Input 4 Bit Muxes := 1 + 13 Input 4 Bit Muxes := 1 + 2 Input 3 Bit Muxes := 225 + 8 Input 3 Bit Muxes := 6 + 3 Input 3 Bit Muxes := 7 + 4 Input 3 Bit Muxes := 11 + 5 Input 3 Bit Muxes := 5 + 6 Input 3 Bit Muxes := 2 + 2 Input 2 Bit Muxes := 257 + 4 Input 2 Bit Muxes := 16 + 3 Input 2 Bit Muxes := 9 + 5 Input 2 Bit Muxes := 2 + 16 Input 2 Bit Muxes := 5 + 2 Input 1 Bit Muxes := 1279 + 8 Input 1 Bit Muxes := 6 + 6 Input 1 Bit Muxes := 12 + 4 Input 1 Bit Muxes := 33 + 3 Input 1 Bit Muxes := 2 + 5 Input 1 Bit Muxes := 6 + 13 Input 1 Bit Muxes := 10 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 240 (col length:80) +BRAMs: 270 (col length: RAMB18 80 RAMB36 40) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +WARNING: [Synth 8-3936] Found unconnected internal register 'subRob/sram/sram_ext/lanes[0].R0_data_reg' and it is trimmed from '1269' to '1262' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:103] +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +WARNING: [Synth 8-3917] design toy_a7_top has port flash_wp_n driven by constant 1 +WARNING: [Synth 8-3917] design toy_a7_top has port flash_hold_n driven by constant 1 +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 10 [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52365] +DSP Report: Generating DSP product_pipe_b0, operation Mode is: A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b0, operation Mode is: PCIN+A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b_reg, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +DSP Report: Generating DSP product_pipe_b0, operation Mode is: A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b0, operation Mode is: PCIN+A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b_reg, operation Mode is: (PCIN+A2*B2)'. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +DSP Report: Generating DSP product_pipe_b0, operation Mode is: A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b0, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b_reg, operation Mode is: (PCIN+A2*B2)'. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +INFO: [Synth 8-4471] merging register 'cfg_max_j_reg[15:0]' into 'cfg_max_j_reg[15:0]' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79428] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79511] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79576] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79605] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79627] +DSP Report: Generating DSP _GEN_363, operation Mode is: A2*B2. +DSP Report: register cfg_max_j_reg is absorbed into DSP _GEN_363. +DSP Report: register cfg_max_i_reg is absorbed into DSP _GEN_363. +DSP Report: operator _GEN_363 is absorbed into DSP _GEN_363. +DSP Report: Generating DSP _GEN_362, operation Mode is: A*B2. +DSP Report: register _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: operator _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: operator _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: Generating DSP _GEN_362, operation Mode is: (PCIN>>17)+A2*B. +DSP Report: register _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: operator _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: operator _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: Generating DSP io_cmd_bits_slots_0_bits_dram_addr5, operation Mode is: A2*B2. +DSP Report: register io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: register io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: operator io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: operator io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: Generating DSP io_cmd_bits_slots_0_bits_dram_addr5, operation Mode is: (PCIN>>17)+A2*B. +DSP Report: register io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: operator io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: operator io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: Generating DSP io_cmd_bits_slots_1_bits_dram_addr4, operation Mode is: A2*B. +DSP Report: register io_cmd_bits_slots_1_bits_dram_addr4 is absorbed into DSP io_cmd_bits_slots_1_bits_dram_addr4. +DSP Report: operator io_cmd_bits_slots_1_bits_dram_addr4 is absorbed into DSP io_cmd_bits_slots_1_bits_dram_addr4. +DSP Report: operator io_cmd_bits_slots_1_bits_dram_addr4 is absorbed into DSP io_cmd_bits_slots_1_bits_dram_addr4. +DSP Report: Generating DSP io_cmd_bits_slots_1_bits_dram_addr4, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_cmd_bits_slots_1_bits_dram_addr4 is absorbed into DSP io_cmd_bits_slots_1_bits_dram_addr4. +DSP Report: operator io_cmd_bits_slots_1_bits_dram_addr4 is absorbed into DSP io_cmd_bits_slots_1_bits_dram_addr4. +DSP Report: Generating DSP io_cmd_bits_slots_2_bits_dram_addr2, operation Mode is: A2*B. +DSP Report: register io_cmd_bits_slots_2_bits_dram_addr2 is absorbed into DSP io_cmd_bits_slots_2_bits_dram_addr2. +DSP Report: operator io_cmd_bits_slots_2_bits_dram_addr2 is absorbed into DSP io_cmd_bits_slots_2_bits_dram_addr2. +DSP Report: operator io_cmd_bits_slots_2_bits_dram_addr2 is absorbed into DSP io_cmd_bits_slots_2_bits_dram_addr2. +DSP Report: Generating DSP io_cmd_bits_slots_2_bits_dram_addr2, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_cmd_bits_slots_2_bits_dram_addr2 is absorbed into DSP io_cmd_bits_slots_2_bits_dram_addr2. +DSP Report: operator io_cmd_bits_slots_2_bits_dram_addr2 is absorbed into DSP io_cmd_bits_slots_2_bits_dram_addr2. +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79673] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79673] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79677] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79681] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79681] +DSP Report: Generating DSP _irow_T_7, operation Mode is: C+A*B. +DSP Report: operator _irow_T_7 is absorbed into DSP _irow_T_7. +DSP Report: operator _irow_T_71 is absorbed into DSP _irow_T_7. +DSP Report: Generating DSP io_inputAddr4, operation Mode is: A*B. +DSP Report: operator io_inputAddr4 is absorbed into DSP io_inputAddr4. +DSP Report: Generating DSP io_inputAddr5, operation Mode is: A*B. +DSP Report: operator io_inputAddr5 is absorbed into DSP io_inputAddr5. +DSP Report: Generating DSP io_inputAddr4, operation Mode is: A*B. +DSP Report: operator io_inputAddr4 is absorbed into DSP io_inputAddr4. +DSP Report: operator io_inputAddr4 is absorbed into DSP io_inputAddr4. +DSP Report: Generating DSP io_inputAddr4, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_inputAddr4 is absorbed into DSP io_inputAddr4. +DSP Report: operator io_inputAddr4 is absorbed into DSP io_inputAddr4. +DSP Report: Generating DSP _icol_T_7, operation Mode is: C+A*B. +DSP Report: operator _icol_T_7 is absorbed into DSP _icol_T_7. +DSP Report: operator _icol_T_71 is absorbed into DSP _icol_T_7. +DSP Report: Generating DSP io_inputAddr2, operation Mode is: PCIN+A:B+C. +DSP Report: operator io_inputAddr2 is absorbed into DSP io_inputAddr2. +DSP Report: Generating DSP io_inputAddr1, operation Mode is: A*B. +DSP Report: operator io_inputAddr1 is absorbed into DSP io_inputAddr1. +DSP Report: operator io_inputAddr1 is absorbed into DSP io_inputAddr1. +DSP Report: Generating DSP io_inputAddr1, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_inputAddr1 is absorbed into DSP io_inputAddr1. +DSP Report: operator io_inputAddr1 is absorbed into DSP io_inputAddr1. +DSP Report: Generating DSP io_weightAddr4, operation Mode is: C+A*B. +DSP Report: operator io_weightAddr4 is absorbed into DSP io_weightAddr4. +DSP Report: operator io_weightAddr5 is absorbed into DSP io_weightAddr4. +DSP Report: Generating DSP io_weightAddr2, operation Mode is: C+A*B. +DSP Report: operator io_weightAddr2 is absorbed into DSP io_weightAddr2. +DSP Report: operator io_weightAddr3 is absorbed into DSP io_weightAddr2. +DSP Report: Generating DSP io_weightAddr1, operation Mode is: A*B. +DSP Report: operator io_weightAddr1 is absorbed into DSP io_weightAddr1. +DSP Report: operator io_weightAddr1 is absorbed into DSP io_weightAddr1. +DSP Report: Generating DSP io_weightAddr1, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_weightAddr1 is absorbed into DSP io_weightAddr1. +DSP Report: operator io_weightAddr1 is absorbed into DSP io_weightAddr1. +DSP Report: Generating DSP io_outputAddr4, operation Mode is: A*B. +DSP Report: operator io_outputAddr4 is absorbed into DSP io_outputAddr4. +DSP Report: Generating DSP io_outputAddr5, operation Mode is: A*B. +DSP Report: operator io_outputAddr5 is absorbed into DSP io_outputAddr5. +DSP Report: Generating DSP io_outputAddr4, operation Mode is: A*B. +DSP Report: operator io_outputAddr4 is absorbed into DSP io_outputAddr4. +DSP Report: operator io_outputAddr4 is absorbed into DSP io_outputAddr4. +DSP Report: Generating DSP io_outputAddr4, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_outputAddr4 is absorbed into DSP io_outputAddr4. +DSP Report: operator io_outputAddr4 is absorbed into DSP io_outputAddr4. +DSP Report: Generating DSP io_outputAddr2, operation Mode is: PCIN+(A:0x0):B+C. +DSP Report: operator io_outputAddr2 is absorbed into DSP io_outputAddr2. +DSP Report: Generating DSP io_outputAddr1, operation Mode is: A*B. +DSP Report: operator io_outputAddr1 is absorbed into DSP io_outputAddr1. +DSP Report: operator io_outputAddr1 is absorbed into DSP io_outputAddr1. +DSP Report: Generating DSP io_outputAddr1, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_outputAddr1 is absorbed into DSP io_outputAddr1. +DSP Report: operator io_outputAddr1 is absorbed into DSP io_outputAddr1. +WARNING: [Synth 8-3936] Found unconnected internal register 'cfg_input_stride_reg' and it is trimmed from '32' to '22' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79776] +WARNING: [Synth 8-3936] Found unconnected internal register 'cfg_output_stride_reg' and it is trimmed from '32' to '24' bits. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79780] +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_domain_id[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_domain_id[2] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_funct[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[63] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[62] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[61] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[60] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[59] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[58] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_domain_id[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_domain_id[2] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_funct[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[63] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[62] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[61] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[60] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[59] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[58] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_domain_id[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_domain_id[2] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_funct[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[63] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[62] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[61] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[60] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[59] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[58] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[4] driven by constant 0 +INFO: [Synth 8-4471] merging register 'reqReg_pixel_bytes_reg[9:0]' into 'reqReg_pixel_bytes_reg[9:0]' [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86013] +DSP Report: Generating DSP rowSkip_reg, operation Mode is: (A*B)'. +DSP Report: register rowSkip_reg is absorbed into DSP rowSkip_reg. +DSP Report: operator rowSkip0 is absorbed into DSP rowSkip_reg. +DSP Report: Generating DSP readVaddr1, operation Mode is: A*B2. +DSP Report: register reqReg_pixel_bytes_reg is absorbed into DSP readVaddr1. +DSP Report: operator readVaddr1 is absorbed into DSP readVaddr1. +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 17 [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:58083] +DSP Report: Generating DSP remainder1, operation Mode is: A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [Synth 8-6430] The Block RAM "dcache/mshrs/sdq_ext/Memory_reg" may get memory collision error if read and write address collide. Use attribute (* rw_addr_collision= "yes" *) to avoid collision +WARNING: [Synth 8-3917] design BBTile__GCB2 has port io_requestor_1_resp_bits_tag[7] driven by constant 0 +WARNING: [Synth 8-3917] design BBTile__GCB2 has port io_requestor_1_resp_bits_tag[6] driven by constant 0 +WARNING: [Synth 8-3917] design BBTile__GCB2 has port io_requestor_2_resp_bits_tag[7] driven by constant 0 +WARNING: [Synth 8-3917] design BBTile__GCB2 has port io_requestor_2_resp_bits_tag[6] driven by constant 0 +WARNING: [Synth 8-3917] design BBTile__GCB2 has port auto_buffer_out_1_c_bits_source[1] driven by constant 0 +RAM Pipeline Warning: Read Address Register Found For RAM sdq_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance. +RAM Pipeline Warning: Read Address Register Found For RAM sdq_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance. +RAM Pipeline Warning: Read Address Register Found For RAM sdq_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance. +WARNING: [Synth 8-6430] The Block RAM "dcache/mshrs/sdq_ext/Memory_reg" may get memory collision error if read and write address collide. Use attribute (* rw_addr_collision= "yes" *) to avoid collision +RAM Pipeline Warning: Read Address Register Found For RAM sdq_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance. +--------------------------------------------------------------------------------- +Start Pre Area Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Iterative Area Optimization +--------------------------------------------------------------------------------- +INFO: [Synth 8-3333] propagating constant 0 across sequential element (fpmu/\io_out_pipe_b_exc_reg[3] ) +INFO: [Synth 8-3886] merging instance 'wb_toint_exc_reg[1]' (FDE) to 'wb_toint_exc_reg[3]' +INFO: [Synth 8-3886] merging instance 'wb_toint_exc_reg[2]' (FDE) to 'wb_toint_exc_reg[3]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\wb_toint_exc_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (sharedFma/\io_out_pipe_b_exc_reg[3] ) +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[47]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[46]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[45]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[44]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[43]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[42]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[41]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[40]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[39]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[38]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[37]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[36]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[35]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[34]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[33]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[32]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[31]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[30]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[29]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[28]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[27]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[26]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[25]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[24]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[23]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[22]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[21]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[47]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[46]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[45]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[44]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[43]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[42]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[41]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[40]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[39]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[38]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[37]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[36]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[35]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[34]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[33]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[32]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[31]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[30]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[29]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[28]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[27]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[26]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[25]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[24]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[23]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[22]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[21]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[20]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[19]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[18]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[17]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[47]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[46]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[45]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[44]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[43]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[42]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[41]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[40]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[39]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[38]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[37]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[36]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[35]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[34]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[33]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[32]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[31]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[30]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[29]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[28]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[27]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[26]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[25]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[24]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[23]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[22]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[21]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[20]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[19]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[18]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[17]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_15_reg[9]' (FDRE) to 'bat/entNewAlias_15_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_15_reg[6]' (FDRE) to 'bat/entNewAlias_15_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_15_reg[7]' (FDRE) to 'bat/entNewAlias_15_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_15_reg[8]' (FDRE) to 'bat/entNewAlias_15_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_15_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_14_reg[9]' (FDRE) to 'bat/entNewAlias_14_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_14_reg[6]' (FDRE) to 'bat/entNewAlias_14_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_14_reg[7]' (FDRE) to 'bat/entNewAlias_14_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_14_reg[8]' (FDRE) to 'bat/entNewAlias_14_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_14_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_13_reg[9]' (FDRE) to 'bat/entNewAlias_13_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_13_reg[6]' (FDRE) to 'bat/entNewAlias_13_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_13_reg[7]' (FDRE) to 'bat/entNewAlias_13_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_13_reg[8]' (FDRE) to 'bat/entNewAlias_13_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_13_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_12_reg[9]' (FDRE) to 'bat/entNewAlias_12_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_12_reg[6]' (FDRE) to 'bat/entNewAlias_12_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_12_reg[7]' (FDRE) to 'bat/entNewAlias_12_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_12_reg[8]' (FDRE) to 'bat/entNewAlias_12_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_12_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_11_reg[9]' (FDRE) to 'bat/entNewAlias_11_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_11_reg[6]' (FDRE) to 'bat/entNewAlias_11_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_11_reg[7]' (FDRE) to 'bat/entNewAlias_11_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_11_reg[8]' (FDRE) to 'bat/entNewAlias_11_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_11_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_10_reg[9]' (FDRE) to 'bat/entNewAlias_10_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_10_reg[6]' (FDRE) to 'bat/entNewAlias_10_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_10_reg[7]' (FDRE) to 'bat/entNewAlias_10_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_10_reg[8]' (FDRE) to 'bat/entNewAlias_10_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_10_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_9_reg[9]' (FDRE) to 'bat/entNewAlias_9_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_9_reg[6]' (FDRE) to 'bat/entNewAlias_9_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_9_reg[7]' (FDRE) to 'bat/entNewAlias_9_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_9_reg[8]' (FDRE) to 'bat/entNewAlias_9_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_9_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_8_reg[9]' (FDRE) to 'bat/entNewAlias_8_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_8_reg[6]' (FDRE) to 'bat/entNewAlias_8_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_8_reg[7]' (FDRE) to 'bat/entNewAlias_8_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_8_reg[8]' (FDRE) to 'bat/entNewAlias_8_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_8_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_7_reg[9]' (FDRE) to 'bat/entNewAlias_7_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_7_reg[6]' (FDRE) to 'bat/entNewAlias_7_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_7_reg[7]' (FDRE) to 'bat/entNewAlias_7_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_7_reg[8]' (FDRE) to 'bat/entNewAlias_7_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_7_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_6_reg[9]' (FDRE) to 'bat/entNewAlias_6_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_6_reg[6]' (FDRE) to 'bat/entNewAlias_6_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_6_reg[7]' (FDRE) to 'bat/entNewAlias_6_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_6_reg[8]' (FDRE) to 'bat/entNewAlias_6_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_6_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_5_reg[9]' (FDRE) to 'bat/entNewAlias_5_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_5_reg[6]' (FDRE) to 'bat/entNewAlias_5_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_5_reg[7]' (FDRE) to 'bat/entNewAlias_5_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_5_reg[8]' (FDRE) to 'bat/entNewAlias_5_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_5_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_4_reg[9]' (FDRE) to 'bat/entNewAlias_4_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_4_reg[6]' (FDRE) to 'bat/entNewAlias_4_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_4_reg[7]' (FDRE) to 'bat/entNewAlias_4_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_4_reg[8]' (FDRE) to 'bat/entNewAlias_4_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_4_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_3_reg[9]' (FDRE) to 'bat/entNewAlias_3_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_3_reg[6]' (FDRE) to 'bat/entNewAlias_3_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_3_reg[7]' (FDRE) to 'bat/entNewAlias_3_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_3_reg[8]' (FDRE) to 'bat/entNewAlias_3_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_3_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_2_reg[9]' (FDRE) to 'bat/entNewAlias_2_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_2_reg[6]' (FDRE) to 'bat/entNewAlias_2_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_2_reg[7]' (FDRE) to 'bat/entNewAlias_2_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_2_reg[8]' (FDRE) to 'bat/entNewAlias_2_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_2_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_1_reg[9]' (FDRE) to 'bat/entNewAlias_1_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_1_reg[6]' (FDRE) to 'bat/entNewAlias_1_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_1_reg[7]' (FDRE) to 'bat/entNewAlias_1_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_1_reg[8]' (FDRE) to 'bat/entNewAlias_1_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_1_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_0_reg[9]' (FDRE) to 'bat/entNewAlias_0_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_0_reg[6]' (FDRE) to 'bat/entNewAlias_0_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_0_reg[7]' (FDRE) to 'bat/entNewAlias_0_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_0_reg[8]' (FDRE) to 'bat/entNewAlias_0_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_0_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/v2a_15_reg[9]' (FDRE) to 'bat/v2a_15_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_14_reg[9]' (FDRE) to 'bat/v2a_14_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_13_reg[9]' (FDRE) to 'bat/v2a_13_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_12_reg[9]' (FDRE) to 'bat/v2a_12_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_11_reg[9]' (FDRE) to 'bat/v2a_11_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_10_reg[9]' (FDRE) to 'bat/v2a_10_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_9_reg[9]' (FDRE) to 'bat/v2a_9_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_8_reg[9]' (FDRE) to 'bat/v2a_8_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_7_reg[9]' (FDRE) to 'bat/v2a_7_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_6_reg[9]' (FDRE) to 'bat/v2a_6_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_5_reg[9]' (FDRE) to 'bat/v2a_5_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_4_reg[9]' (FDRE) to 'bat/v2a_4_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_3_reg[9]' (FDRE) to 'bat/v2a_3_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_2_reg[9]' (FDRE) to 'bat/v2a_2_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_1_reg[9]' (FDRE) to 'bat/v2a_1_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_0_reg[9]' (FDRE) to 'bat/v2a_0_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_15_reg[6]' (FDRE) to 'bat/v2a_15_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_14_reg[6]' (FDRE) to 'bat/v2a_14_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_13_reg[6]' (FDRE) to 'bat/v2a_13_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_12_reg[6]' (FDRE) to 'bat/v2a_12_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_11_reg[6]' (FDRE) to 'bat/v2a_11_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_10_reg[6]' (FDRE) to 'bat/v2a_10_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_9_reg[6]' (FDRE) to 'bat/v2a_9_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_8_reg[6]' (FDRE) to 'bat/v2a_8_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_7_reg[6]' (FDRE) to 'bat/v2a_7_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_6_reg[6]' (FDRE) to 'bat/v2a_6_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_5_reg[6]' (FDRE) to 'bat/v2a_5_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_4_reg[6]' (FDRE) to 'bat/v2a_4_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_3_reg[6]' (FDRE) to 'bat/v2a_3_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_2_reg[6]' (FDRE) to 'bat/v2a_2_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_1_reg[6]' (FDRE) to 'bat/v2a_1_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_0_reg[6]' (FDRE) to 'bat/v2a_0_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_15_reg[7]' (FDRE) to 'bat/v2a_15_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_14_reg[7]' (FDRE) to 'bat/v2a_14_reg[8]' +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_15_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_14_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_13_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_12_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_11_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_10_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_9_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_8_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_7_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_6_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_5_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_4_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_3_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_2_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_1_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_0_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_15_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_14_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_13_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_12_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_11_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_10_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_9_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_8_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_7_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_6_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_5_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_4_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_3_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_2_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_1_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_0_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_15_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_0_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_1_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_2_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_3_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_4_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_5_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_6_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_7_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_8_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_9_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_10_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_11_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_12_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_13_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_14_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [Synth 8-3332] Sequential element (FSM_onehot_state_reg[7]) is unused and will be removed from module MemConfiger. +WARNING: [Synth 8-3332] Sequential element (FSM_onehot_state_reg[6]) is unused and will be removed from module MemConfiger. +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\roccMemIF/s1_req_tag_reg[0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/\ex_reg_cause_reg[7] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_mie_reg[38] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_mcountinhibit_reg[1] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\roccMemIF/io_cache_s1_data_r_data_reg[63] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/reg_singleStepped_reg) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_satp_mode_reg[2] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[40] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[41] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[42] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[43] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[44] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[45] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[46] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[47] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[48] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[49] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[50] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[51] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[52] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[53] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[54] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[55] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[56] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[57] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[58] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[59] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[60] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[61] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[62] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (cores_0/csr/\reg_misa_reg[63] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[7] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[10] ) +INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_114_115 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_108_113 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_102_107 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_96_101 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_90_95 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_84_89 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_78_83 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_72_77 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_66_71 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_60_65 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_54_59 from module BBTile__GCB1 due to constant propagation +INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_114_115 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_72_77 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_66_71 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_60_65 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_54_59 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_48_53 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_42_47 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_36_41 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_30_35 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_24_29 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_18_23 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_72_77 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_10/buffer_1/nodeOut_a_q/ram_ext/Memory_reg_0_1_6_11 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_4/coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_r_deq_q/ram_ext/Memory_reg_0_1_60_65 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_4/coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_r_deq_q/ram_ext/Memory_reg_0_1_54_59 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_4/coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_r_deq_q/ram_ext/Memory_reg_0_1_48_53 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_11/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_0/ram_ext/Memory_reg_0_7_60_65 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_12/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_1/ram_ext/Memory_reg_0_7_60_65 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_13/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_2/ram_ext/Memory_reg_0_7_60_65 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_14/i_0/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_3/ram_ext/Memory_reg_0_7_60_65 from module extram__53 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_11/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_0/ram_ext/Memory_reg_0_7_54_59 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_12/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_1/ram_ext/Memory_reg_0_7_60_65 from module SystemBus due to constant propagation +--------------------------------------------------------------------------------- +Start Post Area Optimization : Time (s): cpu = 00:12:10 ; elapsed = 00:12:45 . Memory (MB): peak = 6506.914 ; gain = 3033.230 ; free physical = 170883 ; free virtual = 522372 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:12:16 ; elapsed = 00:12:51 . Memory (MB): peak = 6506.914 ; gain = 3033.230 ; free physical = 170933 ; free virtual = 522423 +--------------------------------------------------------------------------------- + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_0 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_0 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_10 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_10 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_11 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_12 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_13 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_14 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_15 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_16 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_17 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_18 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_19 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1a : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1b : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1c : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1d : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1e : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1f : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_2 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_20 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_21 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_22 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_23 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_24 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_25 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_26 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_27 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_28 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_29 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2a : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2b : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2c : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2d : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2e : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2f : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_3 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_3 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_30 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_4 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_4 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_5 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_5 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_6 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_6 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_7 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_7 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_8 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_8 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_9 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_9 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_a : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_a : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_b : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_b : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_c : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_c : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_d : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_d : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_e : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_e : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_f : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_f : 0 0 : 519 519 : Used 1 time 100 + Sort Area is BBTile__GCB0 remainder1_8 : 0 0 : 3475 13938 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_8 : 0 1 : 3494 13938 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_8 : 0 2 : 3475 13938 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_8 : 0 3 : 3494 13938 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_6 : 0 0 : 3137 13243 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_6 : 0 1 : 3475 13243 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_6 : 0 2 : 3494 13243 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_6 : 0 3 : 3137 13243 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_4 : 0 0 : 3137 12905 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_4 : 0 1 : 3137 12905 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_4 : 0 2 : 3494 12905 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_4 : 0 3 : 3137 12905 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_0 : 0 0 : 3137 12586 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_0 : 0 1 : 3156 12586 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_0 : 0 2 : 3137 12586 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_0 : 0 3 : 3156 12586 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_8 : 0 0 : 3274 9889 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_8 : 0 1 : 3274 9889 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_8 : 0 2 : 3341 9889 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_4 : 0 0 : 3274 9733 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_4 : 0 1 : 3137 9733 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_4 : 0 2 : 3322 9733 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_0 : 0 0 : 3137 9478 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_0 : 0 1 : 3156 9478 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_0 : 0 2 : 3185 9478 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr1_15 : 0 0 : 2588 5929 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr1_15 : 0 1 : 3341 5929 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_weightAddr1_1b : 0 0 : 2588 5929 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_weightAddr1_1b : 0 1 : 3341 5929 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr1_20 : 0 0 : 2588 5807 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr1_20 : 0 1 : 3219 5807 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_0_bits_dram_addr5_5 : 0 0 : 3052 5790 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_0_bits_dram_addr5_5 : 0 1 : 2738 5790 : Used 1 time 0 + Sort Area is GemminiBall__GC0 _GEN_362_2 : 0 0 : 3034 5772 : Used 1 time 0 + Sort Area is GemminiBall__GC0 _GEN_362_2 : 0 1 : 2738 5772 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_1_bits_dram_addr4_7 : 0 0 : 3035 5756 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_1_bits_dram_addr4_7 : 0 1 : 2721 5756 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_2_bits_dram_addr2_a : 0 0 : 3035 5756 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_2_bits_dram_addr2_a : 0 1 : 2721 5756 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr4_f : 0 0 : 2588 5309 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr4_f : 0 1 : 2721 5309 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr4_1d : 0 0 : 2588 5309 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr4_1d : 0 1 : 2721 5309 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr4_12 : 0 0 : 2722 2987 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr4_12 : 0 1 : 265 2987 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_weightAddr2_19 : 0 0 : 2838 2838 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr4_1e : 0 0 : 1946 2168 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr4_1e : 0 1 : 222 2168 : Used 1 time 0 + Sort Area is GemminiBall__GC0 _GEN_363_0 : 0 0 : 1978 1978 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr5_d : 0 0 : 1946 1946 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr5_1c : 0 0 : 1946 1946 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_a : 0 0 : 1207 1207 : Used 1 time 0 + Sort Area is GemminiBall__GC0 _icol_T_7_b : 0 0 : 949 949 : Used 1 time 0 + Sort Area is GemminiBall__GC0 _irow_T_7_11 : 0 0 : 949 949 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_weightAddr4_17 : 0 0 : 949 949 : Used 1 time 0 + Sort Area is MemFrontend rowSkip_reg_0 : 0 0 : 768 768 : Used 1 time 0 + Sort Area is MemFrontend readVaddr1_2 : 0 0 : 733 733 : Used 1 time 0 +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Block RAM: Preliminary Mapping Report (see note below) ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|GlobalROB__GB1 | robOperands/robOperands_ext/lanes[0].ram_reg | 16 x 128(READ_FIRST) | W | | 16 x 128(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_0 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_1 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_2 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_3 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_4 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_5 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_6 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_7 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|dcache/mshrs | sdq_ext/Memory_reg | 17 x 64(READ_FIRST) | W | | 17 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_0/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_0/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_1/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_1/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_0/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_0/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_1/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_1/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ + +Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once. + +Distributed RAM: Preliminary Mapping Report (see note below) ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ +|regfile_ext | bank0_reg | User Attribute | 32 x 65 | RAM32M x 33 | +|regfile_ext | bank1_reg | User Attribute | 32 x 65 | RAM32M x 33 | +|toy_a7_top | completeQueue/ram_ext/Memory_reg | Implied | 16 x 4 | RAM32M x 1 | +|toy_a7_top | subRob/sram/sram_ext/lanes[0].ram_reg | User Attribute | 8 x 1262 | RAM32M x 211 | +|toy_a7_top | total_rows_q/ram_ext/Memory_reg | Implied | 8 x 7 | RAM32M x 2 | +|GemminiExCtrl__GC0 | rdQueue0/ram_data_ext/Memory_reg | Implied | 8 x 64 | RAM32M x 11 | +|GemminiExCtrl__GC0 | rdQueue1/ram_data_ext/Memory_reg | Implied | 8 x 64 | RAM32M x 11 | +|toy_a7_top | ballRs/fifo/ram_ext/Memory_reg | Implied | 4 x 281 | RAM32M x 47 | +|memRs | fifo/ram_ext/Memory_reg | Implied | 4 x 158 | RAM32M x 27 | +|toy_a7_top | bankReadReqQ_q/ram_ext/Memory_reg | Implied | 8 x 21 | RAM32M x 4 | +|toy_a7_top | bankReadReqQ_q_1/ram_ext/Memory_reg | Implied | 8 x 21 | RAM32M x 4 | +|cores_0 | rf_ext/Memory_reg | Implied | 32 x 64 | RAM32M x 22 | +|BBTile__GCB0 | buffer_2/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 117 | RAM32M x 20 | +|BBTile__GCB0 | buffer_2/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 78 | RAM32M x 13 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_tag_array/bbtile_icache_tag_array_ext/lanes[0].ram_reg | User Attribute | 64 x 21 | RAM64X1S x 21 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_tag_array/bbtile_icache_tag_array_ext/lanes[1].ram_reg | User Attribute | 64 x 21 | RAM64X1S x 21 | +|BBTile__GCB1 | buffer_1/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 116 | RAM32M x 20 | +|BBTile__GCB1 | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 116 | RAM32M x 20 | +|BBTile__GCB1 | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 76 | RAM32M x 13 | +|dcache/mshrs | mshrs_0/rpq/ram_ext/Memory_reg | Implied | 16 x 64 | RAM32M x 11 | +|dcache/meta | tag_array/tag_array_ext/lanes[0].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[1].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[2].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[3].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|toy_a7_top | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 189 | RAM32M x 32 | +|toy_a7_top | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 142 | RAM32M x 24 | +|toy_a7_top | buffer/nodeOut_a_q_1/ram_ext/Memory_reg | Implied | 2 x 188 | RAM32M x 32 | +|toy_a7_top | buffer/nodeIn_d_q_1/ram_ext/Memory_reg | Implied | 2 x 142 | RAM32M x 24 | +|toy_a7_top | buffer/nodeIn_b_q/ram_ext/Memory_reg | Implied | 2 x 60 | RAM32M x 10 | +|toy_a7_top | buffer/nodeOut_c_q/ram_ext/Memory_reg | Implied | 2 x 172 | RAM32M x 29 | +|toy_a7_top | buffer/nodeOut_e_q/ram_sink_ext/Memory_reg | Implied | 2 x 1 | RAM16X1D x 1 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_aw_deq_q/ram_ext/Memory_reg | Implied | 2 x 58 | RAM32M x 10 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_w_deq_q/ram_ext/Memory_reg | Implied | 2 x 73 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_b_deq_q/ram_ext/Memory_reg | Implied | 2 x 4 | RAM32M x 1 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_ar_deq_q/ram_ext/Memory_reg | Implied | 2 x 58 | RAM32M x 10 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_r_deq_q/ram_ext/Memory_reg | Implied | 2 x 69 | RAM32M x 12 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_1/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_2/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_3/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_4/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_5/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_0/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_1/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_2/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_3/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|cbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 114 | RAM32M x 19 | +|cbus | wrapped_error_device/buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 100 | RAM32M x 17 | +|cbus | wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 79 | RAM32M x 14 | +|cbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 79 | RAM32M x 14 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_1/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_2/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_3/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_4/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_5/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_6/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_7/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_8/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_9/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_10/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_11/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_12/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_13/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_14/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_15/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_16/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_17/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_18/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_19/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_20/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_21/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_22/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_23/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_24/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_25/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_26/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_27/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_28/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_29/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_30/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_31/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|coh_wrapper | broadcast_1/TLBroadcastTracker/o_data_q/ram_ext/Memory_reg | Implied | 4 x 144 | RAM32M x 24 | +|coh_wrapper | broadcast_1/TLBroadcastTracker_1/o_data_q/ram_ext/Memory_reg | Implied | 4 x 144 | RAM32M x 24 | +|platformi_21/loader | payload_reg | User Attribute | 256 x 8 | RAM128X1D x 16 | +|platformi_21/peripherals | fifo_reg | User Attribute | 256 x 8 | RAM64M x 12 | ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ + +Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. + +DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set) ++----------------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ +|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | ++----------------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | A2*B2 | 20 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | PCIN+A2*B2 | 20 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN>>17)+A2*B2 | 20 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 1 | +|SharedMulAddRecFNPipe | A2*B2 | 20 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN+A2*B2)' | 20 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 1 | +|SharedMulAddRecFNPipe | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN>>17)+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN+A2*B2)' | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 1 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopMatmulUnroller | A2*B2 | 16 | 16 | - | - | 32 | 1 | 1 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A*B2 | 18 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | (PCIN>>17)+A2*B | 17 | 16 | - | - | 48 | 1 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A2*B2 | 18 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | (PCIN>>17)+A2*B | 17 | 16 | - | - | 48 | 1 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A2*B | 18 | 17 | - | - | 48 | 1 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | (PCIN>>17)+A*B | 17 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A2*B | 18 | 17 | - | - | 48 | 1 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | (PCIN>>17)+A*B | 17 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | C+A*B | 16 | 8 | 24 | - | 24 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 24 | 16 | - | - | 40 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 16 | 16 | - | - | 32 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 18 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | (PCIN>>17)+A*B | 17 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | C+A*B | 16 | 8 | 24 | - | 24 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN+A:B+C | 6 | 18 | 39 | - | -1 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 18 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | (PCIN>>17)+A*B | 23 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | C+A*B | 16 | 8 | 16 | - | 24 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | C+A*B | 24 | 16 | 16 | - | 39 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 18 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | (PCIN>>17)+A*B | 23 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 16 | 16 | - | - | 32 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 16 | 16 | - | - | 32 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 18 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | (PCIN>>17)+A*B | 17 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN+(A:0x0):B+C | 30 | 16 | 37 | - | -1 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 18 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | (PCIN>>17)+A*B | 21 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|StreamReader | (A*B)' | 19 | 6 | - | - | 25 | 0 | 0 | - | - | - | 1 | 0 | +|StreamReader | A*B2 | 10 | 10 | - | - | 20 | 0 | 1 | - | - | - | 0 | 0 | +|MulDiv | A2*B2 | 23 | 6 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | ++----------------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ + +Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once. +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:12:23 ; elapsed = 00:12:58 . Memory (MB): peak = 6506.914 ; gain = 3033.230 ; free physical = 170809 ; free virtual = 522399 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:12:37 ; elapsed = 00:13:12 . Memory (MB): peak = 6506.914 ; gain = 3033.230 ; free physical = 170923 ; free virtual = 522495 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Block RAM: Final Mapping Report ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|GlobalROB__GB1 | robOperands/robOperands_ext/lanes[0].ram_reg | 16 x 128(READ_FIRST) | W | | 16 x 128(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_0 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_1 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_2 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_3 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_4 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_5 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_6 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_7 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|dcache/mshrs | sdq_ext/Memory_reg | 17 x 64(READ_FIRST) | W | | 17 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_0/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_0/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_1/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_1/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_0/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_0/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_1/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_1/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ + + +Distributed RAM: Final Mapping Report ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ +|regfile_ext | bank0_reg | User Attribute | 32 x 65 | RAM32M x 33 | +|regfile_ext | bank1_reg | User Attribute | 32 x 65 | RAM32M x 33 | +|toy_a7_top | total_rows_q/ram_ext/Memory_reg | Implied | 8 x 7 | RAM32M x 2 | +|GemminiExCtrl__GC0 | rdQueue0/ram_data_ext/Memory_reg | Implied | 8 x 64 | RAM32M x 11 | +|GemminiExCtrl__GC0 | rdQueue1/ram_data_ext/Memory_reg | Implied | 8 x 64 | RAM32M x 11 | +|toy_a7_top | ballRs/fifo/ram_ext/Memory_reg | Implied | 4 x 281 | RAM32M x 47 | +|memRs | fifo/ram_ext/Memory_reg | Implied | 4 x 158 | RAM32M x 27 | +|toy_a7_top | bankReadReqQ_q/ram_ext/Memory_reg | Implied | 8 x 21 | RAM32M x 4 | +|toy_a7_top | bankReadReqQ_q_1/ram_ext/Memory_reg | Implied | 8 x 21 | RAM32M x 4 | +|toy_a7_top | completeQueue/ram_ext/Memory_reg | Implied | 16 x 4 | RAM32M x 1 | +|toy_a7_top | subRob/sram/sram_ext/lanes[0].ram_reg | User Attribute | 8 x 1262 | RAM32M x 211 | +|cores_0 | rf_ext/Memory_reg | Implied | 32 x 64 | RAM32M x 22 | +|BBTile__GCB0 | buffer_2/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 117 | RAM32M x 20 | +|BBTile__GCB0 | buffer_2/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 78 | RAM32M x 13 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_tag_array/bbtile_icache_tag_array_ext/lanes[0].ram_reg | User Attribute | 64 x 21 | RAM64X1S x 21 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_tag_array/bbtile_icache_tag_array_ext/lanes[1].ram_reg | User Attribute | 64 x 21 | RAM64X1S x 21 | +|BBTile__GCB1 | buffer_1/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 116 | RAM32M x 20 | +|BBTile__GCB1 | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 116 | RAM32M x 20 | +|BBTile__GCB1 | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 76 | RAM32M x 13 | +|dcache/mshrs | mshrs_0/rpq/ram_ext/Memory_reg | Implied | 16 x 64 | RAM32M x 11 | +|dcache/meta | tag_array/tag_array_ext/lanes[0].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[1].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[2].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[3].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|toy_a7_top | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 189 | RAM32M x 32 | +|toy_a7_top | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 142 | RAM32M x 24 | +|toy_a7_top | buffer/nodeOut_a_q_1/ram_ext/Memory_reg | Implied | 2 x 188 | RAM32M x 32 | +|toy_a7_top | buffer/nodeIn_d_q_1/ram_ext/Memory_reg | Implied | 2 x 142 | RAM32M x 24 | +|toy_a7_top | buffer/nodeIn_b_q/ram_ext/Memory_reg | Implied | 2 x 60 | RAM32M x 10 | +|toy_a7_top | buffer/nodeOut_c_q/ram_ext/Memory_reg | Implied | 2 x 172 | RAM32M x 29 | +|toy_a7_top | buffer/nodeOut_e_q/ram_sink_ext/Memory_reg | Implied | 2 x 1 | RAM16X1D x 1 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_aw_deq_q/ram_ext/Memory_reg | Implied | 2 x 58 | RAM32M x 10 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_w_deq_q/ram_ext/Memory_reg | Implied | 2 x 73 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_b_deq_q/ram_ext/Memory_reg | Implied | 2 x 4 | RAM32M x 1 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_ar_deq_q/ram_ext/Memory_reg | Implied | 2 x 58 | RAM32M x 10 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_r_deq_q/ram_ext/Memory_reg | Implied | 2 x 69 | RAM32M x 12 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_1/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_2/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_3/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_4/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_5/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_0/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_1/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_2/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_3/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|cbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 114 | RAM32M x 19 | +|cbus | wrapped_error_device/buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 100 | RAM32M x 17 | +|cbus | wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 79 | RAM32M x 14 | +|cbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 79 | RAM32M x 14 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_1/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_2/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_3/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_4/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_5/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_6/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_7/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_8/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_9/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_10/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_11/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_12/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_13/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_14/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_15/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_16/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_17/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_18/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_19/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_20/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_21/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_22/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_23/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_24/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_25/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_26/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_27/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_28/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_29/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_30/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_31/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|coh_wrapper | broadcast_1/TLBroadcastTracker/o_data_q/ram_ext/Memory_reg | Implied | 4 x 144 | RAM32M x 24 | +|coh_wrapper | broadcast_1/TLBroadcastTracker_1/o_data_q/ram_ext/Memory_reg | Implied | 4 x 144 | RAM32M x 24 | +|platformi_21/loader | payload_reg | User Attribute | 256 x 8 | RAM128X1D x 16 | +|platformi_21/peripherals | fifo_reg | User Attribute | 256 x 8 | RAM64M x 12 | ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_0/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_0/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_1/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_1/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_2/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_2/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_3/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_3/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_4/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_4/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_5/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_5/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_6/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_6/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_7/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_7/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/mshrs/sdq_ext/Memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_0/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_0/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_1/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_1/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_0/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_0/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_1/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_1/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:12:55 ; elapsed = 00:13:31 . Memory (MB): peak = 6518.840 ; gain = 3045.156 ; free physical = 170749 ; free virtual = 522355 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_0/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_0/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_1/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_1/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_2/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_2/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_3/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_3/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_4/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_4/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_5/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_5/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_6/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_6/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_7/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_7/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/mshrs/sdq_ext/Memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_0/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_0/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_1/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_1/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_0/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_0/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_1/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_1/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/frontend/scheduler/rob/itraceComp of module ITraceDPI__1 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/frontend/scheduler/rob/itraceIssue of module ITraceDPI__2 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/frontend/scheduler/rob/itraceAlloc of module ITraceDPI having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/pmc/pmcTraces_0 of module PMCTraceDPI having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/pmc/ldPmcTrace of module MemPMCTraceDPI__1 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/pmc/stPmcTrace of module MemPMCTraceDPI having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_0 of module MTraceDPI__1 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_1 of module MTraceDPI__2 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_2 of module MTraceDPI__3 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_3 of module MTraceDPI__4 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_4 of module MTraceDPI__5 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_5 of module MTraceDPI__6 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_6 of module MTraceDPI having unconnected or no output ports +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:13:05 ; elapsed = 00:13:41 . Memory (MB): peak = 6518.840 ; gain = 3045.156 ; free physical = 170337 ; free virtual = 522368 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:13:05 ; elapsed = 00:13:41 . Memory (MB): peak = 6518.840 ; gain = 3045.156 ; free physical = 170329 ; free virtual = 522361 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:13:19 ; elapsed = 00:13:55 . Memory (MB): peak = 6518.840 ; gain = 3045.156 ; free physical = 170611 ; free virtual = 522358 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:13:20 ; elapsed = 00:13:55 . Memory (MB): peak = 6518.840 ; gain = 3045.156 ; free physical = 170598 ; free virtual = 522342 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:13:21 ; elapsed = 00:13:57 . Memory (MB): peak = 6518.840 ; gain = 3045.156 ; free physical = 170527 ; free virtual = 522271 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:13:21 ; elapsed = 00:13:57 . Memory (MB): peak = 6518.840 ; gain = 3045.156 ; free physical = 170524 ; free virtual = 522269 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Static Shift Register Report: ++------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ +|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | ++------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/out_matmul_id_RegShifted_0_0_reg[2] | 16 | 3 | NO | NO | YES | 3 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_0_0_reg[19] | 7 | 20 | NO | NO | YES | 20 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_1_6_0_reg[19] | 6 | 20 | NO | NO | YES | 20 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_2_6_0_reg[19] | 5 | 20 | NO | NO | YES | 20 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_3_6_0_reg[19] | 4 | 20 | NO | NO | YES | 20 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_4_6_0_reg[19] | 3 | 20 | NO | NO | YES | 20 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/out_last_RegShifted_0_0_reg | 16 | 1 | NO | NO | YES | 1 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_3_0_reg[7] | 3 | 8 | NO | NO | YES | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_4_0_reg[7] | 4 | 8 | NO | NO | YES | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_5_0_reg[7] | 5 | 8 | NO | NO | YES | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_6_0_reg[7] | 6 | 8 | NO | NO | YES | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_7_0_reg[7] | 7 | 8 | NO | NO | YES | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_3_1_0_reg[7] | 3 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_4_1_0_reg[7] | 4 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_5_1_0_reg[7] | 5 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_6_1_0_reg[7] | 6 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_7_1_0_reg[7] | 7 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_3_2_0_reg[7] | 3 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_4_2_0_reg[7] | 4 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_5_2_0_reg[7] | 5 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_6_2_0_reg[7] | 6 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_7_2_0_reg[7] | 7 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/ibus_intsink/chain/output_chain/sync_0_reg | 3 | 1 | NO | NO | YES | 1 | 0 | ++------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +DSP Final Report (the ' indicates corresponding REG is set) ++----------------------+--------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ +|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | ++----------------------+--------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ +|LoopConvAddrGen | C'+A'*B'' | 16 | 8 | 24 | - | 24 | 1 | 2 | 2 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 24 | 16 | - | - | 40 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A'*B'' | 16 | 16 | - | - | 32 | 1 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN>>17+A''*B | 16 | 15 | - | - | 48 | 2 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | C'+A'*B'' | 16 | 8 | 24 | - | 24 | 1 | 2 | 2 | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN+A:B+C | 6 | 18 | - | - | 39 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN>>17+A*B'' | 22 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | C'+A'*B'' | 16 | 8 | 16 | - | 24 | 1 | 2 | 2 | - | - | 0 | 0 | +|LoopConvAddrGen | C'+A*B'' | 24 | 16 | 16 | - | 39 | 0 | 2 | 2 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN>>17+A*B'' | 22 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A'*B'' | 16 | 16 | - | - | 32 | 1 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A'*B'' | 16 | 16 | - | - | 32 | 1 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN>>17+A''*B | 16 | 15 | - | - | 48 | 2 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN+A:B'+C | 0 | 16 | - | - | 37 | 0 | 1 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN>>17+A*B'' | 20 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|FpgaDspMac | C+A'*B | 30 | 18 | 48 | - | 20 | 1 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|LoopMatmulUnroller | A''*B'' | 16 | 16 | - | - | 32 | 2 | 2 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | PCIN>>17+A''*B | 16 | 15 | - | - | 48 | 2 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A''*B' | 17 | 16 | - | - | 48 | 2 | 1 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | PCIN>>17+A'*B'' | 16 | 15 | - | - | 48 | 1 | 2 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A''*B | 17 | 16 | - | - | 48 | 2 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | PCIN>>17+A*B'' | 16 | 15 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A''*B | 17 | 16 | - | - | 48 | 2 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | PCIN>>17+A*B'' | 16 | 15 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|StreamReader | (A*B')' | 19 | 4 | - | - | 25 | 0 | 1 | - | - | - | 0 | 1 | +|StreamReader | A*B' | 10 | 10 | - | - | 20 | 0 | 1 | - | - | - | 0 | 0 | +|MulDiv | A'*B' | 22 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A'*B' | 17 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A'*B' | 22 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN>>17+A'*B' | 22 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A'*B' | 17 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN>>17+A'*B' | 22 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN>>17+A'*B' | 17 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN>>17+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | A'*B' | 19 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | PCIN+A'*B'' | 19 | 17 | - | - | 48 | 1 | 2 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN>>17+A'*B'')' | 19 | 17 | - | - | 48 | 1 | 2 | - | - | - | 0 | 1 | +|SharedMulAddRecFNPipe | A'*B' | 19 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | PCIN+A'*B'' | 17 | 17 | - | - | 0 | 1 | 2 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN+A'*B'')' | 19 | 17 | - | - | 48 | 1 | 2 | - | - | - | 0 | 1 | +|SharedMulAddRecFNPipe | A'*B'' | 17 | 17 | - | - | 48 | 1 | 2 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | PCIN>>17+A'*B'' | 17 | 17 | - | - | 0 | 1 | 2 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN+A'*B'')' | 17 | 17 | - | - | 48 | 1 | 2 | - | - | - | 0 | 1 | ++----------------------+--------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ + + +Report BlackBoxes: ++------+--------------+----------+ +| |BlackBox name |Instances | ++------+--------------+----------+ +|1 |toy_axi_cdc | 1| +|2 |arty_ddr3 | 1| ++------+--------------+----------+ + +Report Cell Usage: ++------+------------+------+ +| |Cell |Count | ++------+------------+------+ +|1 |arty_ddr3 | 1| +|2 |toy_axi_cdc | 1| +|3 |BUFG | 4| +|4 |CARRY4 | 1950| +|5 |DSP48E1 | 117| +|18 |LUT1 | 817| +|19 |LUT2 | 4360| +|20 |LUT3 | 12197| +|21 |LUT4 | 10130| +|22 |LUT5 | 12422| +|23 |LUT6 | 18450| +|24 |MMCME2_BASE | 1| +|25 |MUXF7 | 629| +|26 |MUXF8 | 112| +|27 |RAM128X1D | 16| +|28 |RAM16X1D | 1| +|29 |RAM32M | 665| +|30 |RAM32X1D | 21| +|31 |RAM32X1S | 92| +|32 |RAM64M | 12| +|33 |RAM64X1S | 42| +|34 |RAMB18E1 | 8| +|35 |RAMB36E1 | 27| +|38 |SRL16E | 225| +|39 |FDCE | 8| +|40 |FDPE | 6| +|41 |FDRE | 28184| +|42 |FDSE | 457| +|43 |IBUF | 4| +|44 |OBUF | 9| ++------+------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:13:22 ; elapsed = 00:13:57 . Memory (MB): peak = 6518.840 ; gain = 3045.156 ; free physical = 170526 ; free virtual = 522271 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 553 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:13:08 ; elapsed = 00:13:50 . Memory (MB): peak = 6518.840 ; gain = 2869.582 ; free physical = 178430 ; free virtual = 530175 +Synthesis Optimization Complete : Time (s): cpu = 00:13:24 ; elapsed = 00:14:01 . Memory (MB): peak = 6518.840 ; gain = 3045.156 ; free physical = 178452 ; free virtual = 530179 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Project 1-454] Reading design checkpoint '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc.dcp' for cell 'memory_cdc' +INFO: [Project 1-454] Reading design checkpoint '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3.dcp' for cell 'ddr_controller' +Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 6518.840 ; gain = 0.000 ; free physical = 178422 ; free virtual = 530148 +INFO: [Netlist 29-17] Analyzing 4089 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2024.1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] for cell 'ddr_controller' +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] for cell 'ddr_controller' +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/arty_a7.xdc] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/arty_a7.xdc] +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/flash_boot.xdc] +CRITICAL WARNING: [Designutils 20-1307] Command 'if' is not supported in the xdc constraint file. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/flash_boot.xdc:11] +CRITICAL WARNING: [Designutils 20-1307] Command 'if' is not supported in the xdc constraint file. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/flash_boot.xdc:15] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/flash_boot.xdc] +INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/arty_ddr3/arty_ddr3.dcp' +INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc.dcp' +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc] for cell 'memory_cdc/inst' +INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:16] +INFO: [Timing 38-2] Deriving generated clocks [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:16] +all_fanout: Time (s): cpu = 00:00:14 ; elapsed = 00:00:06 . Memory (MB): peak = 6518.840 ; gain = 0.000 ; free physical = 178304 ; free virtual = 530036 +WARNING: [Vivado_Tcl 4-2057] Waiver ID 'LUTAR-1' object list specifies likely unusable hierarchical instance 'memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi'. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:30] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:35] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:39] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:42] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:45] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:49] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:52] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:56] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:60] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:63] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:66] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:70] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc] for cell 'memory_cdc/inst' +INFO: [Project 1-1714] 33 XPM XDC files have been applied to the design. +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-1687] 16 scoped IP constraints or related sub-commands were skipped due to synthesis logic optimizations usually triggered by constant connectivity or unconnected output pins. To review the skipped constraints and messages, run the command 'set_param netlist.IPMsgFiltering false' before opening the design. +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6518.840 ; gain = 0.000 ; free physical = 178332 ; free virtual = 530063 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 1054 instances were transformed. + IOBUFDS_INTERMDISABLE => IOBUFDS_INTERMDISABLE (IBUFDS_INTERMDISABLE_INT(x2), INV, OBUFTDS(x2)): 2 instances + IOBUF_INTERMDISABLE => IOBUF_INTERMDISABLE (IBUF_INTERMDISABLE, OBUFT): 16 instances + MMCME2_BASE => MMCME2_ADV: 1 instance + OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 1 instance + RAM128X1D => RAM128X1D (MUXF7(x2), RAMD64E(x4)): 16 instances + RAM16X1D => RAM32X1D (RAMD32(x2)): 1 instance + RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 845 instances + RAM32X1D => RAM32X1D (RAMD32(x2)): 26 instances + RAM32X1S => RAM32X1S (RAMS32): 92 instances + RAM64M => RAM64M (RAMD64E(x4)): 12 instances + RAM64X1S => RAM64X1S (RAMS64E): 42 instances + +Synth Design complete | Checksum: a9a9e22e +INFO: [Common 17-83] Releasing license: Synthesis +608 Infos, 466 Warnings, 4 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:13:57 ; elapsed = 00:14:23 . Memory (MB): peak = 6518.840 ; gain = 3045.277 ; free physical = 178297 ; free virtual = 530027 +INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 13719.642; main = 5860.059; forked = 8257.207 +INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 19170.168; main = 6514.926; forked = 12655.242 +# write_checkpoint -force $out/synthesized.dcp +INFO: [Timing 38-480] Writing timing data to binary archive. +Wrote PlaceDB: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6538.930 ; gain = 0.000 ; free physical = 178297 ; free virtual = 530027 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6538.930 ; gain = 0.000 ; free physical = 178297 ; free virtual = 530027 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.02 . Memory (MB): peak = 6538.930 ; gain = 0.000 ; free physical = 178297 ; free virtual = 530028 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6538.930 ; gain = 0.000 ; free physical = 178297 ; free virtual = 530028 +Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 6538.930 ; gain = 0.000 ; free physical = 178297 ; free virtual = 530029 +Write Physdb Complete: Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.03 . Memory (MB): peak = 6538.930 ; gain = 0.000 ; free physical = 178297 ; free virtual = 530029 +Write ShapeDB Complete: Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.11 . Memory (MB): peak = 6538.930 ; gain = 0.000 ; free physical = 178289 ; free virtual = 530027 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/synthesized.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 6538.930 ; gain = 20.090 ; free physical = 178342 ; free virtual = 530142 +# report_utilization -file $out/synth-utilization.rpt +# report_utilization -hierarchical -file $out/synth-hierarchy.rpt +# report_timing_summary -delay_type min_max -file $out/synth-timing.rpt +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. +report_timing_summary: Time (s): cpu = 00:00:21 ; elapsed = 00:00:07 . Memory (MB): peak = 6538.930 ; gain = 0.000 ; free physical = 178359 ; free virtual = 530163 +# set unresolved [get_cells -hier -quiet -filter {IS_BLACKBOX == 1}] +# if {[llength $unresolved]} {error "Unresolved black boxes: $unresolved"} +# phase OPTIMIZE +BOARD_PHASE OPTIMIZE +# opt_design -directive ExploreArea +Command: opt_design -directive ExploreArea +INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: ExploreArea +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 8 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.78 . Memory (MB): peak = 6570.945 ; gain = 32.016 ; free physical = 178367 ; free virtual = 530173 + +Starting Logic Optimization Task + +Phase 1 Initialization + +Phase 1.1 Core Generation And Design Setup +Phase 1.1 Core Generation And Design Setup | Checksum: 2c6ce0b9c + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 178365 ; free virtual = 530172 + +Phase 1.2 Setup Constraints And Sort Netlist +Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 2c6ce0b9c + +Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.04 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 178365 ; free virtual = 530172 +Phase 1 Initialization | Checksum: 2c6ce0b9c + +Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 178365 ; free virtual = 530172 + +Phase 2 Timer Update And Timing Data Collection + +Phase 2.1 Timer Update +Phase 2.1 Timer Update | Checksum: 2c6ce0b9c + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 178371 ; free virtual = 530178 + +Phase 2.2 Timing Data Collection +Phase 2.2 Timing Data Collection | Checksum: 2c6ce0b9c + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 178375 ; free virtual = 530182 +Phase 2 Timer Update And Timing Data Collection | Checksum: 2c6ce0b9c + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 178375 ; free virtual = 530182 + +Phase 3 Retarget +INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0 +INFO: [Opt 31-1566] Pulled 311 inverters resulting in an inversion of 2868 pins +INFO: [Opt 31-138] Pushed 8 inverter(s) to 9 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 3 Retarget | Checksum: 295d70cd1 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 178347 ; free virtual = 530154 +Retarget | Checksum: 295d70cd1 +INFO: [Opt 31-389] Phase Retarget created 97 cells and removed 603 cells +INFO: [Opt 31-1021] In phase Retarget, 52 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 4 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 4 Constant propagation | Checksum: 256694385 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 178293 ; free virtual = 530101 +Constant propagation | Checksum: 256694385 +INFO: [Opt 31-389] Phase Constant propagation created 12 cells and removed 19 cells +INFO: [Opt 31-1021] In phase Constant propagation, 30 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 5 Sweep +Phase 5 Sweep | Checksum: 25a775b40 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 178233 ; free virtual = 530041 +Sweep | Checksum: 25a775b40 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 333 cells +INFO: [Opt 31-1021] In phase Sweep, 150 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 6 BUFG optimization +Phase 6 BUFG optimization | Checksum: 2e91af07d + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 178234 ; free virtual = 530042 +BUFG optimization | Checksum: 2e91af07d +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. + +Phase 7 Shift Register Optimization +INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs +Phase 7 Shift Register Optimization | Checksum: 2e91af07d + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:05 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 178234 ; free virtual = 530042 +Shift Register Optimization | Checksum: 2e91af07d +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells +INFO: [Opt 31-1555] control_set_opt supports Versal devices only, and device 7a100t is unsupported + +Phase 8 Resynthesis +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Opt 31-74] Optimized 105 modules. +INFO: [Opt 31-75] Optimized module 'AccPipe'. +INFO: [Opt 31-75] Optimized module 'AccPipe_11'. +INFO: [Opt 31-75] Optimized module 'AccPipe_12'. +INFO: [Opt 31-75] Optimized module 'AccPipe_13'. +INFO: [Opt 31-75] Optimized module 'AccPipe_14'. +INFO: [Opt 31-75] Optimized module 'AccPipe_15'. +INFO: [Opt 31-75] Optimized module 'AccPipe_16'. +INFO: [Opt 31-75] Optimized module 'BankScoreboard'. +INFO: [Opt 31-75] Optimized module 'DTLB'. +INFO: [Opt 31-75] Optimized module 'DivSqrtRawFN_small_e8_s24'. +INFO: [Opt 31-75] Optimized module 'FPToInt'. +INFO: [Opt 31-75] Optimized module 'GemminiExCtrl'. +INFO: [Opt 31-75] Optimized module 'IBuf'. +INFO: [Opt 31-75] Optimized module 'ICache'. +INFO: [Opt 31-75] Optimized module 'ITLB'. +INFO: [Opt 31-75] Optimized module 'LoopConvUnroller'. +INFO: [Opt 31-75] Optimized module 'MaxPeriodFibonacciLFSR_3'. +INFO: [Opt 31-75] Optimized module 'MemConfiger'. +INFO: [Opt 31-75] Optimized module 'MemMidend'. +INFO: [Opt 31-75] Optimized module 'MeshWithDelays'. +INFO: [Opt 31-75] Optimized module 'NonBlockingDCache'. +INFO: [Opt 31-75] Optimized module 'PE_64_186'. +INFO: [Opt 31-75] Optimized module 'PE_64_189'. +INFO: [Opt 31-75] Optimized module 'PE_64_192'. +INFO: [Opt 31-75] Optimized module 'PE_64_195'. +INFO: [Opt 31-75] Optimized module 'PE_64_198'. +INFO: [Opt 31-75] Optimized module 'PE_64_201'. +INFO: [Opt 31-75] Optimized module 'PE_64_204'. +INFO: [Opt 31-75] Optimized module 'PE_64_207'. +INFO: [Opt 31-75] Optimized module 'PE_64_210'. +INFO: [Opt 31-75] Optimized module 'PE_64_213'. +INFO: [Opt 31-75] Optimized module 'PE_64_216'. +INFO: [Opt 31-75] Optimized module 'PE_64_219'. +INFO: [Opt 31-75] Optimized module 'PE_64_222'. +INFO: [Opt 31-75] Optimized module 'PE_64_225'. +INFO: [Opt 31-75] Optimized module 'PE_64_228'. +INFO: [Opt 31-75] Optimized module 'PE_64_231'. +INFO: [Opt 31-75] Optimized module 'PE_64_234'. +INFO: [Opt 31-75] Optimized module 'PE_64_237'. +INFO: [Opt 31-75] Optimized module 'PE_64_240'. +INFO: [Opt 31-75] Optimized module 'PE_64_243'. +INFO: [Opt 31-75] Optimized module 'PE_64_246'. +INFO: [Opt 31-75] Optimized module 'PE_64_249'. +INFO: [Opt 31-75] Optimized module 'PE_64_252'. +INFO: [Opt 31-75] Optimized module 'PE_64_255'. +INFO: [Opt 31-75] Optimized module 'PE_64_258'. +INFO: [Opt 31-75] Optimized module 'PE_64_261'. +INFO: [Opt 31-75] Optimized module 'PE_64_264'. +INFO: [Opt 31-75] Optimized module 'PE_64_267'. +INFO: [Opt 31-75] Optimized module 'PE_64_270'. +INFO: [Opt 31-75] Optimized module 'PE_64_273'. +INFO: [Opt 31-75] Optimized module 'PE_64_276'. +INFO: [Opt 31-75] Optimized module 'PE_64_279'. +INFO: [Opt 31-75] Optimized module 'PE_64_282'. +INFO: [Opt 31-75] Optimized module 'PE_64_285'. +INFO: [Opt 31-75] Optimized module 'PE_64_288'. +INFO: [Opt 31-75] Optimized module 'PE_64_291'. +INFO: [Opt 31-75] Optimized module 'PE_64_294'. +INFO: [Opt 31-75] Optimized module 'PE_64_297'. +INFO: [Opt 31-75] Optimized module 'PE_64_300'. +INFO: [Opt 31-75] Optimized module 'PE_64_303'. +INFO: [Opt 31-75] Optimized module 'PE_64_306'. +INFO: [Opt 31-75] Optimized module 'PE_64_309'. +INFO: [Opt 31-75] Optimized module 'PE_64_312'. +INFO: [Opt 31-75] Optimized module 'PE_64_315'. +INFO: [Opt 31-75] Optimized module 'PE_64_318'. +INFO: [Opt 31-75] Optimized module 'PE_64_321'. +INFO: [Opt 31-75] Optimized module 'PE_64_324'. +INFO: [Opt 31-75] Optimized module 'PE_64_327'. +INFO: [Opt 31-75] Optimized module 'PE_64_330'. +INFO: [Opt 31-75] Optimized module 'PE_64_333'. +INFO: [Opt 31-75] Optimized module 'PE_64_336'. +INFO: [Opt 31-75] Optimized module 'PE_64_339'. +INFO: [Opt 31-75] Optimized module 'PE_64_342'. +INFO: [Opt 31-75] Optimized module 'PE_64_345'. +INFO: [Opt 31-75] Optimized module 'PE_64_348'. +INFO: [Opt 31-75] Optimized module 'PE_64_351'. +INFO: [Opt 31-75] Optimized module 'PE_64_354'. +INFO: [Opt 31-75] Optimized module 'Queue16_ReplayInternal'. +INFO: [Opt 31-75] Optimized module 'Queue1_RegMapperInput_i23_m8'. +INFO: [Opt 31-75] Optimized module 'Queue4_TLBroadcastData'. +INFO: [Opt 31-75] Optimized module 'Queue8_SramReadResp_39'. +INFO: [Opt 31-75] Optimized module 'Repeater_TLBundleA_a17d64s3k1z3u'. +INFO: [Opt 31-75] Optimized module 'ShiftQueue'. +INFO: [Opt 31-75] Optimized module 'SubROB'. +INFO: [Opt 31-75] Optimized module 'TLB'. +INFO: [Opt 31-75] Optimized module 'TLXbar_sbus_i2_o3_a32d128s3k1z4c'. +INFO: [Opt 31-75] Optimized module 'TagQueue'. +INFO: [Opt 31-75] Optimized module 'WritebackUnit'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_axi_mc_wr_cmd_fsm'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_bank_state__parameterized2'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_ddr_if_post_fifo'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_ddr_phy_rdlvl'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_ddr_phy_wrcal'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_rank_common'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_round_robin_arb'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_tempmon'. +INFO: [Opt 31-75] Optimized module 'axi_fullwidth'. +INFO: [Opt 31-75] Optimized module 'ram_2x58'. +INFO: [Opt 31-75] Optimized module 'ram_2x58_376'. +INFO: [Common 17-14] Message 'Opt 31-75' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Opt 31-1566] Pulled 2280 inverters resulting in an inversion of 7908 pins +INFO: [Opt 31-138] Pushed 4 inverter(s) to 19 load pin(s). +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 8 Resynthesis | Checksum: 1c3bf1ef2 + +Time (s): cpu = 00:02:49 ; elapsed = 00:00:55 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 177969 ; free virtual = 529776 +Resynthesis | Checksum: 1c3bf1ef2 +INFO: [Opt 31-389] Phase Resynthesis created 19062 cells and removed 19811 cells +INFO: [Opt 31-1021] In phase Resynthesis, 151 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 9 Post Processing Netlist +Phase 9 Post Processing Netlist | Checksum: 1c3bf1ef2 + +Time (s): cpu = 00:02:49 ; elapsed = 00:00:55 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 177974 ; free virtual = 529782 +Post Processing Netlist | Checksum: 1c3bf1ef2 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells +INFO: [Opt 31-1021] In phase Post Processing Netlist, 45 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 10 Finalization + +Phase 10.1 Finalizing Design Cores and Updating Shapes +Phase 10.1 Finalizing Design Cores and Updating Shapes | Checksum: 2249eaaa7 + +Time (s): cpu = 00:02:50 ; elapsed = 00:00:56 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 177981 ; free virtual = 529788 + +Phase 10.2 Verifying Netlist Connectivity + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.14 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 177982 ; free virtual = 529789 +Phase 10.2 Verifying Netlist Connectivity | Checksum: 2249eaaa7 + +Time (s): cpu = 00:02:50 ; elapsed = 00:00:57 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 177982 ; free virtual = 529789 +Phase 10 Finalization | Checksum: 2249eaaa7 + +Time (s): cpu = 00:02:50 ; elapsed = 00:00:57 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 177982 ; free virtual = 529789 +Opt_design Change Summary +========================= + + +------------------------------------------------------------------------------------------------------------------------- +| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | +------------------------------------------------------------------------------------------------------------------------- +| Retarget | 97 | 603 | 52 | +| Constant propagation | 12 | 19 | 30 | +| Sweep | 0 | 333 | 150 | +| BUFG optimization | 0 | 0 | 0 | +| Shift Register Optimization | 0 | 0 | 0 | +| Resynthesis | 19062 | 19811 | 151 | +| Post Processing Netlist | 0 | 0 | 45 | +------------------------------------------------------------------------------------------------------------------------- + + +Ending Logic Optimization Task | Checksum: 2249eaaa7 + +Time (s): cpu = 00:02:50 ; elapsed = 00:00:57 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 177982 ; free virtual = 529789 + +Starting Netlist Obfuscation Task +Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 177982 ; free virtual = 529789 +Ending Netlist Obfuscation Task | Checksum: 2249eaaa7 + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 177982 ; free virtual = 529789 +INFO: [Common 17-83] Releasing license: Implementation +131 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:02:54 ; elapsed = 00:01:00 . Memory (MB): peak = 6570.945 ; gain = 32.016 ; free physical = 177982 ; free virtual = 529789 +# write_checkpoint -force $out/optimized.dcp +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-480] Writing timing data to binary archive. +Wrote PlaceDB: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.02 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 177974 ; free virtual = 529780 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 177974 ; free virtual = 529780 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 177973 ; free virtual = 529780 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 177973 ; free virtual = 529780 +Wrote Device Cache: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 177973 ; free virtual = 529781 +Write Physdb Complete: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.04 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 177973 ; free virtual = 529781 +Write ShapeDB Complete: Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.12 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 177961 ; free virtual = 529778 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/optimized.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:18 ; elapsed = 00:00:12 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 177791 ; free virtual = 529665 +# report_utilization -file $out/opt-utilization.rpt +# phase PLACE +BOARD_PHASE PLACE +# place_design -directive Explore +Command: place_design -directive Explore +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-83] Releasing license: Implementation +INFO: [DRC 23-27] Running DRC with 8 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +INFO: [Vivado_Tcl 4-2302] The placer was invoked with the 'Explore' directive. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 8 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs + +Starting Placer Task + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 177799 ; free virtual = 529674 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 14f5d1a2b + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 177799 ; free virtual = 529674 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 177799 ; free virtual = 529674 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 17dfc4ae4 + +Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 6570.945 ; gain = 0.000 ; free physical = 177823 ; free virtual = 529697 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 189c2ca53 + +Time (s): cpu = 00:00:26 ; elapsed = 00:00:13 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 177656 ; free virtual = 529528 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 189c2ca53 + +Time (s): cpu = 00:00:27 ; elapsed = 00:00:13 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 177661 ; free virtual = 529532 +Phase 1 Placer Initialization | Checksum: 189c2ca53 + +Time (s): cpu = 00:00:27 ; elapsed = 00:00:13 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 177677 ; free virtual = 529549 + +Phase 2 Global Placement + +Phase 2.1 Floorplanning +Phase 2.1 Floorplanning | Checksum: 20bb1dab5 + +Time (s): cpu = 00:00:36 ; elapsed = 00:00:16 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 177664 ; free virtual = 529535 + +Phase 2.2 Update Timing before SLR Path Opt +Phase 2.2 Update Timing before SLR Path Opt | Checksum: 2286fe973 + +Time (s): cpu = 00:00:43 ; elapsed = 00:00:18 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 177631 ; free virtual = 529502 + +Phase 2.3 Post-Processing in Floorplanning +Phase 2.3 Post-Processing in Floorplanning | Checksum: 2286fe973 + +Time (s): cpu = 00:00:43 ; elapsed = 00:00:19 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 177627 ; free virtual = 529498 + +Phase 2.4 Global Placement Core + +Phase 2.4.1 UpdateTiming Before Physical Synthesis +Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 1a630b68c + +Time (s): cpu = 00:02:09 ; elapsed = 00:00:50 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 177186 ; free virtual = 529050 + +Phase 2.4.2 Physical Synthesis In Placer +INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 5152 LUT instances to create LUTNM shape +INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0 +INFO: [Physopt 32-1138] End 1 Pass. Optimized 2204 nets or LUTs. Breaked 0 LUT, combined 2204 existing LUTs and moved 0 existing LUT +INFO: [Physopt 32-65] No nets found for high-fanout optimization. +INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. +INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed. +INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. +INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. +INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed. +INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 177179 ; free virtual = 529043 + +Summary of Physical Synthesis Optimizations +============================================ + + +----------------------------------------------------------------------------------------------------------------------------------------------------------- +| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | +----------------------------------------------------------------------------------------------------------------------------------------------------------- +| LUT Combining | 0 | 2204 | 2204 | 0 | 1 | 00:00:02 | +| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Total | 0 | 2204 | 2204 | 0 | 4 | 00:00:03 | +----------------------------------------------------------------------------------------------------------------------------------------------------------- + + +Phase 2.4.2 Physical Synthesis In Placer | Checksum: 2a3298b58 + +Time (s): cpu = 00:02:20 ; elapsed = 00:00:56 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 177189 ; free virtual = 529055 +Phase 2.4 Global Placement Core | Checksum: 28e960a12 + +Time (s): cpu = 00:02:31 ; elapsed = 00:01:01 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 177310 ; free virtual = 529173 +Phase 2 Global Placement | Checksum: 28e960a12 + +Time (s): cpu = 00:02:31 ; elapsed = 00:01:01 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 177310 ; free virtual = 529173 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 2ba6ea6d8 + +Time (s): cpu = 00:02:38 ; elapsed = 00:01:03 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 177217 ; free virtual = 529080 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 2733bb972 + +Time (s): cpu = 00:02:51 ; elapsed = 00:01:08 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 177178 ; free virtual = 529039 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 27d09f09c + +Time (s): cpu = 00:02:52 ; elapsed = 00:01:09 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 177154 ; free virtual = 529016 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 280076c81 + +Time (s): cpu = 00:02:52 ; elapsed = 00:01:09 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 177163 ; free virtual = 529026 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 274e2b06e + +Time (s): cpu = 00:03:13 ; elapsed = 00:01:28 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 171132 ; free virtual = 528577 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 2462932d4 + +Time (s): cpu = 00:03:16 ; elapsed = 00:01:31 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 168560 ; free virtual = 528495 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 3265b2010 + +Time (s): cpu = 00:03:16 ; elapsed = 00:01:31 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 168074 ; free virtual = 528507 +Phase 3 Detail Placement | Checksum: 3265b2010 + +Time (s): cpu = 00:03:17 ; elapsed = 00:01:32 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 167522 ; free virtual = 528552 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Phase 4.1.1 Post Placement Optimization +Post Placement Optimization Initialization | Checksum: 260892d3c + +Phase 4.1.1.1 BUFG Insertion + +Starting Physical Synthesis Task + +Phase 1 Physical Synthesis Initialization +INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=1.277 | TNS=0.000 | +Phase 1 Physical Synthesis Initialization | Checksum: 19563dd38 + +Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 158247 ; free virtual = 528472 +INFO: [Place 46-33] Processed net platform/loader/SR[0], BUFG insertion was skipped due to placement/routing conflicts. +INFO: [Place 46-56] BUFG insertion identified 1 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 1, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. +Ending Physical Synthesis Task | Checksum: 27bd8317e + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 158117 ; free virtual = 528343 +Phase 4.1.1.1 BUFG Insertion | Checksum: 260892d3c + +Time (s): cpu = 00:03:49 ; elapsed = 00:01:44 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 158114 ; free virtual = 528340 + +Phase 4.1.1.2 Post Placement Timing Optimization +INFO: [Place 30-746] Post Placement Timing Summary WNS=1.277. For the most accurate timing information please run report_timing. +Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 29d6b1f6b + +Time (s): cpu = 00:03:51 ; elapsed = 00:01:44 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 158244 ; free virtual = 528470 + +Time (s): cpu = 00:03:51 ; elapsed = 00:01:44 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 158244 ; free virtual = 528470 +Phase 4.1 Post Commit Optimization | Checksum: 29d6b1f6b + +Time (s): cpu = 00:03:51 ; elapsed = 00:01:45 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 158244 ; free virtual = 528470 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 29d6b1f6b + +Time (s): cpu = 00:03:52 ; elapsed = 00:01:45 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 158264 ; free virtual = 528490 + +Phase 4.3 Placer Reporting + +Phase 4.3.1 Print Estimated Congestion +INFO: [Place 30-612] Post-Placement Estimated Congestion + ____________________________________________________ +| | Global Congestion | Short Congestion | +| Direction | Region Size | Region Size | +|___________|___________________|___________________| +| North| 1x1| 8x8| +|___________|___________________|___________________| +| South| 2x2| 8x8| +|___________|___________________|___________________| +| East| 2x2| 8x8| +|___________|___________________|___________________| +| West| 1x1| 2x2| +|___________|___________________|___________________| + +Phase 4.3.1 Print Estimated Congestion | Checksum: 29d6b1f6b + +Time (s): cpu = 00:03:53 ; elapsed = 00:01:46 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 158277 ; free virtual = 528503 +Phase 4.3 Placer Reporting | Checksum: 29d6b1f6b + +Time (s): cpu = 00:03:53 ; elapsed = 00:01:46 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 158276 ; free virtual = 528503 + +Phase 4.4 Final Placement Cleanup +Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 158276 ; free virtual = 528502 + +Time (s): cpu = 00:03:53 ; elapsed = 00:01:46 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 158276 ; free virtual = 528502 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 2e4b25a14 + +Time (s): cpu = 00:03:54 ; elapsed = 00:01:47 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 158228 ; free virtual = 528455 +Ending Placer Task | Checksum: 1eddddbab + +Time (s): cpu = 00:03:54 ; elapsed = 00:01:47 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 158251 ; free virtual = 528478 +30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +place_design: Time (s): cpu = 00:03:59 ; elapsed = 00:01:49 . Memory (MB): peak = 6577.973 ; gain = 7.027 ; free physical = 158247 ; free virtual = 528474 +# write_checkpoint -force $out/placed.dcp +INFO: [Timing 38-480] Writing timing data to binary archive. +Write ShapeDB Complete: Time (s): cpu = 00:00:00.78 ; elapsed = 00:00:00.17 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 158237 ; free virtual = 528481 +Wrote PlaceDB: Time (s): cpu = 00:00:08 ; elapsed = 00:00:03 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 158231 ; free virtual = 528563 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 158231 ; free virtual = 528563 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 158223 ; free virtual = 528556 +Wrote Netlist Cache: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.1 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 158232 ; free virtual = 528573 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 158232 ; free virtual = 528574 +Write Physdb Complete: Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 158232 ; free virtual = 528574 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/placed.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:16 ; elapsed = 00:00:11 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 158468 ; free virtual = 528777 +# phase PHYS_OPT +BOARD_PHASE PHYS_OPT +# phys_opt_design -directive Explore +Command: phys_opt_design -directive Explore +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: Explore + +Starting Initial Update Timing Task + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:05 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 158586 ; free virtual = 528895 +INFO: [Vivado_Tcl 4-2279] Estimated Timing Summary | WNS= 1.277 | TNS= 0.000 | +INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. All physical synthesis setup optimizations will be skipped. +INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified. +INFO: [Common 17-83] Releasing license: Implementation +6 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +phys_opt_design completed successfully +phys_opt_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:05 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 158586 ; free virtual = 528895 +# phase ROUTE +BOARD_PHASE ROUTE +# route_design -directive Explore +Command: route_design -directive Explore +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 8 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-270] Using Router directive 'Explore'. +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs + +Phase 1 Build RT Design +Checksum: PlaceDB: ee9480ea ConstDB: 0 ShapeSum: 4d76fb2b RouteDB: b1d25f96 +Post Restoration Checksum: NetGraph: 241726a8 | NumContArr: 5afb29d9 | Constraints: c2a8fa9d | Timing: c2a8fa9d +Phase 1 Build RT Design | Checksum: 2046445bb + +Time (s): cpu = 00:00:31 ; elapsed = 00:00:14 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 158879 ; free virtual = 529183 + +Phase 2 Router Initialization + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 2046445bb + +Time (s): cpu = 00:00:32 ; elapsed = 00:00:15 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 158875 ; free virtual = 529179 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 2046445bb + +Time (s): cpu = 00:00:32 ; elapsed = 00:00:15 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 158883 ; free virtual = 529188 + Number of Nodes with overlaps = 0 + +Phase 2.3 Update Timing +Phase 2.3 Update Timing | Checksum: 35e0f5c98 + +Time (s): cpu = 00:01:01 ; elapsed = 00:00:24 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 158963 ; free virtual = 529266 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.274 | TNS=0.000 | WHS=-1.411 | THS=-707.878| + + +Phase 2.4 Update Timing for Bus Skew + +Phase 2.4.1 Update Timing +Phase 2.4.1 Update Timing | Checksum: 2c11b980e + +Time (s): cpu = 00:01:22 ; elapsed = 00:00:29 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 159024 ; free virtual = 529325 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.274 | TNS=0.000 | WHS=-2.372 | THS=-68.356| + +Phase 2.4 Update Timing for Bus Skew | Checksum: 2d1538f6d + +Time (s): cpu = 00:01:22 ; elapsed = 00:00:29 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 159024 ; free virtual = 529325 + +Router Utilization Summary + Global Vertical Routing Utilization = 0 % + Global Horizontal Routing Utilization = 0 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 93600 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 93600 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Phase 2 Router Initialization | Checksum: 3833990d1 + +Time (s): cpu = 00:01:24 ; elapsed = 00:00:30 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 159025 ; free virtual = 529326 + +Phase 3 Global Routing +Phase 3 Global Routing | Checksum: 3833990d1 + +Time (s): cpu = 00:01:24 ; elapsed = 00:00:30 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 159025 ; free virtual = 529326 + +Phase 4 Initial Routing + +Phase 4.1 Initial Net Routing Pass +Phase 4.1 Initial Net Routing Pass | Checksum: 29558e5a8 + +Time (s): cpu = 00:01:38 ; elapsed = 00:00:33 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 159062 ; free virtual = 529363 +Phase 4 Initial Routing | Checksum: 29558e5a8 + +Time (s): cpu = 00:01:38 ; elapsed = 00:00:33 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 159062 ; free virtual = 529364 + +Phase 5 Rip-up And Reroute + +Phase 5.1 Global Iteration 0 + Number of Nodes with overlaps = 14471 + Number of Nodes with overlaps = 1519 + Number of Nodes with overlaps = 378 + Number of Nodes with overlaps = 101 + Number of Nodes with overlaps = 31 + Number of Nodes with overlaps = 9 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 0 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.274 | TNS=0.000 | WHS=N/A | THS=N/A | + +Phase 5.1 Global Iteration 0 | Checksum: 1bcb17191 + +Time (s): cpu = 00:02:48 ; elapsed = 00:01:12 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 158636 ; free virtual = 529127 + +Phase 5.2 Global Iteration 1 + Number of Nodes with overlaps = 10 + Number of Nodes with overlaps = 13 + Number of Nodes with overlaps = 12 + Number of Nodes with overlaps = 7 + Number of Nodes with overlaps = 4 + Number of Nodes with overlaps = 0 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.274 | TNS=0.000 | WHS=N/A | THS=N/A | + +Phase 5.2 Global Iteration 1 | Checksum: 28fd5ecfa + +Time (s): cpu = 00:03:00 ; elapsed = 00:01:18 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 157226 ; free virtual = 527719 +Phase 5 Rip-up And Reroute | Checksum: 28fd5ecfa + +Time (s): cpu = 00:03:00 ; elapsed = 00:01:18 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 157211 ; free virtual = 527698 + +Phase 6 Delay and Skew Optimization + +Phase 6.1 Delay CleanUp + +Phase 6.1.1 Update Timing +Phase 6.1.1 Update Timing | Checksum: 2fec1ab35 + +Time (s): cpu = 00:03:09 ; elapsed = 00:01:21 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 157210 ; free virtual = 527697 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.274 | TNS=0.000 | WHS=N/A | THS=N/A | + +Phase 6.1 Delay CleanUp | Checksum: 216e3ec42 + +Time (s): cpu = 00:03:10 ; elapsed = 00:01:21 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 157202 ; free virtual = 527689 + +Phase 6.2 Clock Skew Optimization +Phase 6.2 Clock Skew Optimization | Checksum: 216e3ec42 + +Time (s): cpu = 00:03:10 ; elapsed = 00:01:21 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 157186 ; free virtual = 527674 +Phase 6 Delay and Skew Optimization | Checksum: 216e3ec42 + +Time (s): cpu = 00:03:10 ; elapsed = 00:01:21 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 157195 ; free virtual = 527683 + +Phase 7 Post Hold Fix + +Phase 7.1 Hold Fix Iter +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.274 | TNS=0.000 | WHS=0.010 | THS=0.000 | + +Phase 7.1 Hold Fix Iter | Checksum: 22ae53d4c + +Time (s): cpu = 00:03:20 ; elapsed = 00:01:23 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 157080 ; free virtual = 527568 +Phase 7 Post Hold Fix | Checksum: 22ae53d4c + +Time (s): cpu = 00:03:20 ; elapsed = 00:01:23 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 157072 ; free virtual = 527560 + +Phase 8 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 21.9441 % + Global Horizontal Routing Utilization = 26.5389 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Phase 8 Route finalize | Checksum: 22ae53d4c + +Time (s): cpu = 00:03:21 ; elapsed = 00:01:23 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 157048 ; free virtual = 527536 + +Phase 9 Verifying routed nets + + Verification completed successfully +Phase 9 Verifying routed nets | Checksum: 22ae53d4c + +Time (s): cpu = 00:03:22 ; elapsed = 00:01:24 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 157055 ; free virtual = 527542 + +Phase 10 Depositing Routes +Phase 10 Depositing Routes | Checksum: 1f66f8eea + +Time (s): cpu = 00:03:28 ; elapsed = 00:01:27 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 156293 ; free virtual = 526781 + +Phase 11 Post Process Routing +Phase 11 Post Process Routing | Checksum: 1f66f8eea + +Time (s): cpu = 00:03:28 ; elapsed = 00:01:27 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 156291 ; free virtual = 526779 + +Phase 12 Post Router Timing +INFO: [Route 35-20] Post Routing Timing Summary | WNS=1.276 | TNS=0.000 | WHS=0.012 | THS=0.000 | + +Phase 12 Post Router Timing | Checksum: 1e1452a1b + +Time (s): cpu = 00:03:54 ; elapsed = 00:01:33 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 156752 ; free virtual = 527434 +INFO: [Route 35-61] The design met the timing requirement. +Total Elapsed time in route_design: 93.29 secs + +Phase 13 Post-Route Event Processing +Phase 13 Post-Route Event Processing | Checksum: 171b86a1b + +Time (s): cpu = 00:03:55 ; elapsed = 00:01:34 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 156327 ; free virtual = 526927 +INFO: [Route 35-16] Router Completed Successfully +Ending Routing Task | Checksum: 171b86a1b + +Time (s): cpu = 00:03:56 ; elapsed = 00:01:35 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 156233 ; free virtual = 526777 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +16 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:04:02 ; elapsed = 00:01:38 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 156296 ; free virtual = 526902 +# write_checkpoint -force $out/routed.dcp +INFO: [Timing 38-480] Writing timing data to binary archive. +Write ShapeDB Complete: Time (s): cpu = 00:00:00.78 ; elapsed = 00:00:00.17 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 155980 ; free virtual = 526683 +Wrote PlaceDB: Time (s): cpu = 00:00:08 ; elapsed = 00:00:03 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 155746 ; free virtual = 526530 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 155746 ; free virtual = 526530 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00.98 ; elapsed = 00:00:00.61 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 155799 ; free virtual = 526599 +Wrote Netlist Cache: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.09 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 155785 ; free virtual = 526593 +Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 155785 ; free virtual = 526594 +Write Physdb Complete: Time (s): cpu = 00:00:09 ; elapsed = 00:00:04 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 155785 ; free virtual = 526594 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/routed.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:25 ; elapsed = 00:00:14 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 156308 ; free virtual = 527072 +# phase REPORT +BOARD_PHASE REPORT +# report_utilization -file $out/routed-utilization.rpt +# report_utilization -hierarchical -file $out/routed-hierarchy.rpt +# report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -file $out/routed-timing.rpt +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. +report_timing_summary: Time (s): cpu = 00:00:24 ; elapsed = 00:00:06 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 157307 ; free virtual = 528071 +# report_route_status -file $out/route-status.rpt +# report_drc -file $out/drc.rpt +Command: report_drc -file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/drc.rpt +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 8 threads +INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/drc.rpt. +report_drc completed successfully +INFO: [Timing 38-91] UpdateTimingParams: No interconnect No Cell Dly, Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +INFO: [Timing 38-314] The report_cdc command only analyzes and reports clock domain crossing paths where clocks have been defined on both source and destination sides. Ports with no input delay constraint are skipped. Please run check_timing to verify there are no missing clock definitions in your design, nor any unconstrained input port. +# set cdc [report_cdc -details -return_string] +# set f [open $out/cdc.rpt w] +# puts $f $cdc +# close $f +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +# set skew [report_bus_skew -return_string] +# set f [open $out/bus-skew.rpt w] +# puts $f $skew +# close $f +# report_methodology -file $out/methodology.rpt +Command: report_methodology -file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/methodology.rpt +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 8 threads +INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/methodology.rpt. +report_methodology completed successfully +report_methodology: Time (s): cpu = 00:00:32 ; elapsed = 00:00:10 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 158293 ; free virtual = 529054 +# report_io -file $out/io.rpt +report_io: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.26 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 158297 ; free virtual = 529059 +# report_clocks -file $out/clocks.rpt +INFO: [Timing 38-35] Done setting XDC timing constraints. +# check_timing -verbose -file $out/check-timing.rpt +# if {[regexp {CDC-[0-9]+\s+Critical} $cdc]} {error "Critical CDC findings; see cdc.rpt"} +# if {[string match *VIOLATED* $skew]} {error "Bus skew failed; see bus-skew.rpt"} +# foreach kind {max min} { +# set paths [get_timing_paths -delay_type $kind -max_paths 1] +# if {[llength $paths]==0} {error "Missing $kind timing paths"} +# if {[get_property SLACK [lindex $paths 0]]<0} {error "$kind timing failed"} +# } +# if {![report_route_status -boolean_check ROUTED_FULLY]} {error "Routing incomplete"} +# if {[report_route_status -boolean_check ERRORS_IN_ROUTES]} {error "Routing errors"} +# set errors [get_drc_violations -quiet -filter {SEVERITY == Error || SEVERITY == {Critical Warning}}] +# if {[llength $errors]} {error "DRC errors/critical warnings: $errors"} +# phase BITSTREAM +BOARD_PHASE BITSTREAM +# set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +# write_bitstream -force $out/toy_a7.bit +Command: write_bitstream -force /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/toy_a7.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +Running DRC as a precondition to command write_bitstream +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 8 threads +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +INFO: [Common 17-14] Message 'DRC DPIP-1' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +INFO: [Common 17-14] Message 'DRC DPOP-1' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/rowSkip_reg multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/rowSkip_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +INFO: [Common 17-14] Message 'DRC DPOP-2' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [DRC REQP-1709] Clock output buffering: PLLE2_ADV connectivity violation. The signal ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out on the ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 pin of ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i does not drive the same kind of BUFFER load as the other CLKOUT pins. Routing from the different buffer types will not be phase aligned. +WARNING: [DRC RTSTAT-10] No routable loads: 45 net(s) have no routable loads. The problem bus(es) and/or net(s) are memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0]... and (the first 15 of 25 listed). +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 360 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Bitstream compression saved 7411584 bits. +Writing bitstream /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921/toy_a7.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-83] Releasing license: Implementation +12 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:45 ; elapsed = 00:00:25 . Memory (MB): peak = 6577.973 ; gain = 0.000 ; free physical = 158516 ; free virtual = 529274 +# phase COMPLETE +BOARD_PHASE COMPLETE +# puts "PASS BOARD_PLACE_ROUTE_TIMING_BITSTREAM: engineering Rev E target; flash=$flash; this build does not validate physical boot" +PASS BOARD_PLACE_ROUTE_TIMING_BITSTREAM: engineering Rev E target; flash=0; this build does not validate physical boot +INFO: [Common 17-206] Exiting Vivado at Tue Oct 13 01:32:55 2026... diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/memory-test.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/memory-test.log new file mode 100644 index 0000000..73ebfc1 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/memory-test.log @@ -0,0 +1,9 @@ +PASS sram_ext depth=8 width=1269 1R1W +PASS robOperands_ext depth=16 width=128 1R1W +PASS tag_array_ext: original RTL + scoreboard, full depth/mask/enable +PASS array_0_0_ext depth=128 width=128 1R1W +PASS bbtile_icache_tag_array_ext: original RTL + scoreboard, full depth/mask/enable +PASS bbtile_icache_data_arrays_0_ext: original RTL + scoreboard, full depth/mask/enable +PASS mem_ext: original RTL + scoreboard, full depth/mask/enable +PASS all memory bindings +build/serial-bound/tb_memories.sv:585: $finish called at 51147000 (1ps) diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/run-fullcheck.sh b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/run-fullcheck.sh new file mode 100644 index 0000000..1cd8fca --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/run-fullcheck.sh @@ -0,0 +1,58 @@ +#!/usr/bin/env bash +set -euo pipefail +source scripts/toolchain.sh +mkdir -p build/fullcheck +phase() { printf '%s +' "$1" >build/fullcheck/phase.txt; printf 'FULLCHECK_PHASE %s +' "$1"; } +phase INPUTS +python3 build/bootstrap.py +python3 scripts/verify_target.py +python3 scripts/verify_rob_evidence.py +python3 scripts/verify_pr10_evidence.py +phase ELABORATE +timeout --signal=TERM --kill-after=15s 3600s bash scripts/elaborate_rob_candidate.sh --repository build/baseline.git +python3 scripts/verify_rob_evidence.py --core +phase OFFLINE_INTERFACES +python3 scripts/check_board.py +python3 scripts/check_programming_scripts.py +python3 scripts/check_flash_guards.py +python3 scripts/check_runner_status.py +python3 scripts/check_platform_mutations.py +phase MEMORY_AND_UNITS +timeout --signal=TERM --kill-after=15s 3600s python3 tests/check_fpga_memories.py --original build/serial-reference/ToyLinuxChip.sv --bound build/serial-bound +timeout --signal=TERM --kill-after=15s 3600s python3 scripts/check_core_units.py +python3 tests/check_routing.py +phase WHOLE_CHIP +timeout --signal=TERM --kill-after=15s 3600s bash scripts/build_test_programs.sh +timeout --signal=TERM --kill-after=15s 3600s python3 tests/check_ws_round.py +timeout --signal=TERM --kill-after=15s 3600s python3 tests/check_ws_shift_edges.py +timeout --signal=TERM --kill-after=15s 3600s python3 tests/check_fpu_shared.py --baseline-core ../reference-fpu +phase BOARD_REGRESSION +timeout --signal=TERM --kill-after=15s 3600s python3 scripts/run_board_regression.py +timeout --signal=TERM --kill-after=15s 3600s python3 scripts/check_board_uart_boot.py +phase BOARD_IMPLEMENTATION +python3 scripts/start_rob_board_build.py >build/fullcheck/BOARD_LAUNCH.json +phase LINUX_RTL +timeout --signal=TERM --kill-after=15s 3600s python3 scripts/check_board_linux.py +phase WAIT_BOARD +python3 - <<'PYCHECK' +import json,time +from pathlib import Path +launch=json.loads(Path('build/fullcheck/BOARD_LAUNCH.json').read_text());record=Path(launch['output_directory'])/'RUN.json' +started=time.monotonic() +while True: + data=json.loads(record.read_text()) + if data['status'] not in ['CREATED','RUNNING']:break + if time.monotonic()-started>3615:raise TimeoutError('Bounded board completion wait') + time.sleep(10) +assert data['status']=='COMPLETED' and data['exit_code']==0 and data['bitstream_generated'],data +assert data['candidate_core_unchanged'] and data['candidate_memory_unchanged'],data +print('PASS full board implementation',launch['output_directory']) +PYCHECK +phase REAL_XILINX_CDC +board_run=$(python3 -c 'import json,pathlib;print(pathlib.Path(json.load(open("build/fullcheck/BOARD_LAUNCH.json"))["output_directory"]).name)') +timeout --signal=TERM --kill-after=15s 3600s python3 scripts/check_board_cdc.py "$board_run" +phase COMPLETE +printf 'PASS ROB_PR10_FULL_VALIDATION +' diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/session.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/session.log new file mode 100644 index 0000000..f9bf8aa --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/session.log @@ -0,0 +1,749 @@ +FULLCHECK_PHASE INPUTS +hint: Using 'master' as the name for the initial branch. This default branch name +hint: is subject to change. To configure the initial branch name to use in all +hint: of your new repositories, which will suppress this warning, call: +hint: +hint: git config --global init.defaultBranch +hint: +hint: Names commonly chosen instead of 'master' are 'main', 'trunk' and +hint: 'development'. The just-created branch can be renamed via this command: +hint: +hint: git branch -m +Initialized empty Git repository in /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/baseline.git/ +PASS physical hardware archive: 14 original artifacts; complete DDR image readback, five Linux checks and live shell +PASS Flash evidence: implementation, program/verify and physical cold-start Linux checks +PASS Toy target: 668 source hashes; published implementation and RTL evidence +PASS ROB RAM archive: 91 files; unchanged regression cycles; routed candidate +This initial archive predates physical tests; later hardware evidence is in PR #9 +PASS PR10 archive: 77 artifacts; 4/20/10 offline checks and expected negatives +PASS PR10 selfcheck archive: 90 artifacts; fresh failure status and BVALID oracles +FULLCHECK_PHASE ELABORATE +From https://github.com/DangoSys/buckyball + * branch 1f3d54535bd5fb76d5fd2f6b05ed36e591cf3097 -> FETCH_HEAD + % Total % Received % Xferd Average Speed Time Time Time Current + Dload Upload Total Spent Left Speed + 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 422k 0 422k 0 0 410k 0 --:--:-- 0:00:01 --:--:-- 411k 100 938k 0 938k 0 0 841k 0 --:--:-- 0:00:01 --:--:-- 842k + % Total % Received % Xferd Average Speed Time Time Time Current + Dload Upload Total Spent Left Speed + 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 8818 0 8818 0 0 8599 0 --:--:-- 0:00:01 --:--:-- 8602 100 39278 0 39278 0 0 28601 0 --:--:-- 0:00:01 --:--:-- 28607 + % Total % Received % Xferd Average Speed Time Time Time Current + Dload Upload Total Spent Left Speed + 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 12943 0 12943 0 0 23637 0 --:--:-- --:--:-- --:--:-- 23618 100 17164 0 17164 0 0 26872 0 --:--:-- --:--:-- --:--:-- 26860 + % Total % Received % Xferd Average Speed Time Time Time Current + Dload Upload Total Spent Left Speed + 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 41595 0 41595 0 0 54541 0 --:--:-- --:--:-- --:--:-- 54515 100 44650 0 44650 0 0 58531 0 --:--:-- --:--:-- --:--:-- 58519 + % Total % Received % Xferd Average Speed Time Time Time Current + Dload Upload Total Spent Left Speed + 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 412k 0 412k 0 0 402k 0 --:--:-- 0:00:01 --:--:-- 402k 100 1001k 0 1001k 0 0 897k 0 --:--:-- 0:00:01 --:--:-- 897k + % Total % Received % Xferd Average Speed Time Time Time Current + Dload Upload Total Spent Left Speed + 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 96974 0 96974 0 0 115k 0 --:--:-- --:--:-- --:--:-- 115k 100 535k 0 535k 0 0 540k 0 --:--:-- --:--:-- --:--:-- 540k + % Total % Received % Xferd Average Speed Time Time Time Current + Dload Upload Total Spent Left Speed + 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 42343 0 42343 0 0 48863 0 --:--:-- --:--:-- --:--:-- 48838 100 3393k 0 3393k 0 0 2380k 0 --:--:-- 0:00:01 --:--:-- 2381k +Verified 336 original Buckyball files at 1f3d54535bd5fb76d5fd2f6b05ed36e591cf3097 +Verified/exported rocket-chip: 411 files at 35488f108c1ee9e42175b5240ae957d8970e9c5b +Verified/exported inclusive-cache: 27 files at 88317ea415459d274026bd59850517a9fcc87ede +Verified/exported cde: 15 files at 2bcaeae2b9914bd25497ce3c6fa62dc5ca80e09f +Verified/exported diplomacy: 53 files at fe5e131d4fc8adec14a3ce4a4935bb5c0a269871 +Verified/exported hardfloat: 127 files at 536cf3727f655713f424438190100bb08cbf2e5a +Verified/exported gemmini: 102 files at 8c3f9923a44a2fe2c7930587be297d6d4f8c09ca +Verified/exported firesim: 9 files at da2a1cbcebbb96e21c551ebef513fd95a9d73403 +Original Toy: VM=True, FPU={'enable': True, 'minFLen': 16, 'fLen': 64}, Balls=4, banks={'num': 16, 'width': 128, 'entries': 1024, 'maskLen': 16, 'channel': 7} +PASS GLOBALROB RAM/register cycle comparison, payloads, wrap, stalls, resets cycles=8029 +- /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/tb_globalrob.sv:25: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 80us; walltime 0.032 s; speed 2.475 ms/s +- Verilator: cpu 0.032 s on 1 threads; allocated 7 MB + +[info] welcome to sbt 1.12.11 (N/A Java 17.0.20) +[info] loading project definition from /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/project +[info] loading settings for project root from build.sbt... +[info] set current project to toy-arty-a7-linux (in build file:/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/) +[info] running fpga.arty.linux.EmitToyLinux build/serial-raw --fpga-memories --serial-fpga +[warn] patches/buckyball/GemminiExCtrlPreloadStates.scala 67:15: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] op2Buf(xpose_row_cnt) := rdQueue0.io.deq.bits.data +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlPreloadStates.scala 83:51: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] VecInit((0 until DIM).map(i => op2Buf(i)(transpose_col))) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlStoreOps.scala 16:13: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] outBuf(outBufRows) := widenMeshToAcc(mesh.io.resp.bits.data) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlComputeFeedState.scala 46:17: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] op1Buf(xpose_row_cnt) := rdQueue0.io.deq.bits.data +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlComputeFeedState.scala 51:17: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] op2Buf(xpose_row_cnt) := rdQueue1.io.deq.bits.data +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlComputeFeedState.scala 68:65: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] val a_col_row = VecInit((0 until DIM).map(i => op1Buf(i)(feed_row_cnt))) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlComputeFeedState.scala 69:65: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] val x_col_row = VecInit((0 until DIM).map(i => op2Buf(i)(feed_row_cnt))) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlStoreOps.scala 27:15: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] outBuf(total_rows - 1.U - outBufCollected) := widenMeshToAcc( +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlStoreOps.scala 69:17: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] outBuf(outBufRows) := widenMeshToAcc(mesh.io.resp.bits.data) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlStoreOps.scala 100:31: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] val row = outBuf(rowIdx) +[warn] ^ +[warn] There were 10 warning(s) during hardware elaboration. +espresso is not found in your PATH: +/nix/store/2y0qz1r84ckgmmrnfvx9bbysnyn1zb61-openjdk-17.0.20+8/lib/openjdk/bin +/nix/store/2y0qz1r84ckgmmrnfvx9bbysnyn1zb61-openjdk-17.0.20+8/bin +/nix/store/ahvmb4byixykslwcxiay7c4ivhgpf8vg-sbt-1.8.2/bin +/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/bin +/nix/store/y8vkcyc8frd7ipcq0a6jix4xilgm93j7-riscv64-unknown-elf-gcc/bin +/nix/store/ywdz7hiyhb7hkp0vyzqfdx3fmrf1v8pa-yosys-0.67/bin +/home/yys/bin +/usr/local/sbin +/usr/local/bin +/usr/sbin +/usr/bin +/sbin +/bin +/usr/games +/usr/local/games +/snap/bin +Interrupt map (2 harts 1 interrupts): + [1, 1] => system + +:52.18-57.5: Warning (simple_bus_reg): /soc/cbus_clock: missing or empty reg/ranges property +:68.28-71.5: Warning (simple_bus_reg): /soc/external-interrupts: missing or empty reg/ranges property +:72.18-77.5: Warning (simple_bus_reg): /soc/fbus_clock: missing or empty reg/ranges property +:88.18-93.5: Warning (simple_bus_reg): /soc/mbus_clock: missing or empty reg/ranges property +:100.18-105.5: Warning (simple_bus_reg): /soc/pbus_clock: missing or empty reg/ranges property +:111.18-116.5: Warning (simple_bus_reg): /soc/sbus_clock: missing or empty reg/ranges property +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ucb-bar,buckyball-dev"; + model = "ucb-bar,buckyball"; + L10: cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <1000000>; + L12: cpu@0 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <32>; + d-cache-size = <8192>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + hardware-exec-breakpoint-count = <0>; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <8192>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + next-level-cache = <&L16>; + reg = <0x0>; + riscv,isa = "rv64imafdcbzicsr_zifencei_zihpm_zfh_zba_zbb_zbs_xrocket"; + riscv,pmpgranularity = <4>; + riscv,pmpregions = <8>; + status = "okay"; + timebase-frequency = <1000000>; + tlb-split; + L6: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + L16: memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; + }; + L9: soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ucb-bar,buckyball-soc", "simple-bus"; + ranges; + L3: cbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "cbus_clock"; + compatible = "fixed-clock"; + }; + L13: clint@2000000 { + compatible = "riscv,clint0"; + interrupts-extended = <&L6 3 &L6 7>; + reg = <0x2000000 0x10000>; + reg-names = "control"; + }; + L4: error-device@3000 { + compatible = "sifive,error0"; + reg = <0x3000 0x1000>; + }; + L15: external-interrupts { + interrupt-parent = <&L14>; + interrupts = <1>; + }; + L2: fbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "fbus_clock"; + compatible = "fixed-clock"; + }; + L14: interrupt-controller@c000000 { + #interrupt-cells = <1>; + compatible = "riscv,plic0"; + interrupt-controller; + interrupts-extended = <&L6 11 &L6 9>; + reg = <0xc000000 0x4000000>; + reg-names = "control"; + riscv,max-priority = <1>; + riscv,ndev = <1>; + }; + L5: mbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "mbus_clock"; + compatible = "fixed-clock"; + }; + L17: mmio-port-axi4@60000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x60000000 0x60000000 0x10000000>; + }; + L1: pbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "pbus_clock"; + compatible = "fixed-clock"; + }; + L18: rom@10000 { + compatible = "sifive,rom0"; + reg = <0x10000 0x10000>; + reg-names = "mem"; + }; + L0: sbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "sbus_clock"; + compatible = "fixed-clock"; + }; + }; +}; + +Generated Address Map + 3000 - 4000 ARWX error-device@3000 + 10000 - 20000 R X rom@10000 + 2000000 - 2010000 ARW clint@2000000 + c000000 - 10000000 ARW interrupt-controller@c000000 + 60000000 - 70000000 RWX mmio-port-axi4@60000000 + 80000000 - 90000000 RWXC memory@80000000 + +[warn] thirdparty/rocket-chip/src/main/scala/rocket/NBDcache.scala 456:25: [W004] Dynamic index with width 1 is too wide for Vec of size 1 (expected index width 0). +[warn] io.refill := refillMux(io.mem_grant.bits.source) +[warn] ^ +[warn] There were 1 warning(s) during hardware elaboration. +[success] Total time: 13 s, completed Oct 13, 2026, 12:57:12 AM +[info] running fpga.arty.linux.EmitToyLinux build/serial-reference --serial-fpga +[warn] patches/buckyball/GemminiExCtrlPreloadStates.scala 67:15: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] op2Buf(xpose_row_cnt) := rdQueue0.io.deq.bits.data +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlPreloadStates.scala 83:51: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] VecInit((0 until DIM).map(i => op2Buf(i)(transpose_col))) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlStoreOps.scala 16:13: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] outBuf(outBufRows) := widenMeshToAcc(mesh.io.resp.bits.data) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlComputeFeedState.scala 46:17: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] op1Buf(xpose_row_cnt) := rdQueue0.io.deq.bits.data +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlComputeFeedState.scala 51:17: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] op2Buf(xpose_row_cnt) := rdQueue1.io.deq.bits.data +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlComputeFeedState.scala 68:65: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] val a_col_row = VecInit((0 until DIM).map(i => op1Buf(i)(feed_row_cnt))) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlComputeFeedState.scala 69:65: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] val x_col_row = VecInit((0 until DIM).map(i => op2Buf(i)(feed_row_cnt))) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlStoreOps.scala 27:15: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] outBuf(total_rows - 1.U - outBufCollected) := widenMeshToAcc( +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlStoreOps.scala 69:17: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] outBuf(outBufRows) := widenMeshToAcc(mesh.io.resp.bits.data) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlStoreOps.scala 100:31: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] val row = outBuf(rowIdx) +[warn] ^ +[warn] There were 10 warning(s) during hardware elaboration. +espresso is not found in your PATH: +/nix/store/2y0qz1r84ckgmmrnfvx9bbysnyn1zb61-openjdk-17.0.20+8/lib/openjdk/bin +/nix/store/2y0qz1r84ckgmmrnfvx9bbysnyn1zb61-openjdk-17.0.20+8/bin +/nix/store/ahvmb4byixykslwcxiay7c4ivhgpf8vg-sbt-1.8.2/bin +/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/bin +/nix/store/y8vkcyc8frd7ipcq0a6jix4xilgm93j7-riscv64-unknown-elf-gcc/bin +/nix/store/ywdz7hiyhb7hkp0vyzqfdx3fmrf1v8pa-yosys-0.67/bin +/home/yys/bin +/usr/local/sbin +/usr/local/bin +/usr/sbin +/usr/bin +/sbin +/bin +/usr/games +/usr/local/games +/snap/bin +Interrupt map (2 harts 1 interrupts): + [1, 1] => system + +:52.18-57.5: Warning (simple_bus_reg): /soc/cbus_clock: missing or empty reg/ranges property +:68.28-71.5: Warning (simple_bus_reg): /soc/external-interrupts: missing or empty reg/ranges property +:72.18-77.5: Warning (simple_bus_reg): /soc/fbus_clock: missing or empty reg/ranges property +:88.18-93.5: Warning (simple_bus_reg): /soc/mbus_clock: missing or empty reg/ranges property +:100.18-105.5: Warning (simple_bus_reg): /soc/pbus_clock: missing or empty reg/ranges property +:111.18-116.5: Warning (simple_bus_reg): /soc/sbus_clock: missing or empty reg/ranges property +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ucb-bar,buckyball-dev"; + model = "ucb-bar,buckyball"; + L10: cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <1000000>; + L12: cpu@0 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <32>; + d-cache-size = <8192>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + hardware-exec-breakpoint-count = <0>; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <8192>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + next-level-cache = <&L16>; + reg = <0x0>; + riscv,isa = "rv64imafdcbzicsr_zifencei_zihpm_zfh_zba_zbb_zbs_xrocket"; + riscv,pmpgranularity = <4>; + riscv,pmpregions = <8>; + status = "okay"; + timebase-frequency = <1000000>; + tlb-split; + L6: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + L16: memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; + }; + L9: soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ucb-bar,buckyball-soc", "simple-bus"; + ranges; + L3: cbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "cbus_clock"; + compatible = "fixed-clock"; + }; + L13: clint@2000000 { + compatible = "riscv,clint0"; + interrupts-extended = <&L6 3 &L6 7>; + reg = <0x2000000 0x10000>; + reg-names = "control"; + }; + L4: error-device@3000 { + compatible = "sifive,error0"; + reg = <0x3000 0x1000>; + }; + L15: external-interrupts { + interrupt-parent = <&L14>; + interrupts = <1>; + }; + L2: fbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "fbus_clock"; + compatible = "fixed-clock"; + }; + L14: interrupt-controller@c000000 { + #interrupt-cells = <1>; + compatible = "riscv,plic0"; + interrupt-controller; + interrupts-extended = <&L6 11 &L6 9>; + reg = <0xc000000 0x4000000>; + reg-names = "control"; + riscv,max-priority = <1>; + riscv,ndev = <1>; + }; + L5: mbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "mbus_clock"; + compatible = "fixed-clock"; + }; + L17: mmio-port-axi4@60000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x60000000 0x60000000 0x10000000>; + }; + L1: pbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "pbus_clock"; + compatible = "fixed-clock"; + }; + L18: rom@10000 { + compatible = "sifive,rom0"; + reg = <0x10000 0x10000>; + reg-names = "mem"; + }; + L0: sbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "sbus_clock"; + compatible = "fixed-clock"; + }; + }; +}; + +Generated Address Map + 3000 - 4000 ARWX error-device@3000 + 10000 - 20000 R X rom@10000 + 2000000 - 2010000 ARW clint@2000000 + c000000 - 10000000 ARW interrupt-controller@c000000 + 60000000 - 70000000 RWX mmio-port-axi4@60000000 + 80000000 - 90000000 RWXC memory@80000000 + +[warn] thirdparty/rocket-chip/src/main/scala/rocket/NBDcache.scala 456:25: [W004] Dynamic index with width 1 is too wide for Vec of size 1 (expected index width 0). +[warn] io.refill := refillMux(io.mem_grant.bits.source) +[warn] ^ +[warn] There were 1 warning(s) during hardware elaboration. +[success] Total time: 10 s, completed Oct 13, 2026, 12:57:22 AM +[info] running fpga.arty.linux.EmitRoutingCheck build/routing-check +[success] Total time: 1 s, completed Oct 13, 2026, 12:57:23 AM +Bound 7 memory types, 20 instances +PASS RF adapter matches original port contract; only RF module body replaced +Final core SHA256: 31e7e07f94d08208dbb564edf9546240df26ff834935bfb646b71b541d875fb9 +{ + "result": "PREPARED_NOT_VALIDATED", + "architectural_profile_unchanged": true, + "existing_memory_geometry_unchanged": true, + "rob_operand_memory": { + "module_name": "robOperands_ext", + "depth": 16, + "width": 128, + "masked": false, + "read": 1, + "write": 1, + "readwrite": 0, + "extra_ports": [], + "hierarchy": [ + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.accelerators_0.frontend.scheduler.rob.robOperands.robOperands_ext" + ] + }, + "rob_operand_ram_style": "block", + "core_rtl_sha256": "31e7e07f94d08208dbb564edf9546240df26ff834935bfb646b71b541d875fb9", + "memory_rtl_sha256": "d5a37896aee19c8d4931c87dc9683861abf32f096a1c1441f4362370d3d7b054" +} +Exported 23 Ball opcodes from the elaborated profile +PASS ROB RAM archive: 91 files; unchanged regression cycles; routed candidate +This initial archive predates physical tests; later hardware evidence is in PR #9 +FULLCHECK_PHASE OFFLINE_INTERFACES +PASS fullwidth AXI: sizes 8..128 bits, INCR/FIXED, strobes, concurrent R/W, stalls, IDs, range/4KiB rejection; read beats=90 +/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/tb_axi_fullwidth.sv:107: $finish called at 9270000 (1ps) +PASS SCU OpenSBI byte addresses, AXI lanes, RX pop/IRQ, TX backpressure, EXIT +/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/tb_axi_scu.sv:64: $finish called at 20580000 (1ps) +PASS platform AXI B response: valid, invalid address, unaligned, burst, ID and backpressure +/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/tb_platform_bresp.sv:55: $finish called at 420000 (1ps) +PASS: DDR UART loader CRC, 256-byte unaligned RAM roundtrip, rejected writes/RUN, timeout and boot +/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-unit/tb_ddr_loader.sv:116: $finish called at 78290000 (1ps) +PASS programming scripts: 20 documented-return/status/error cases; no hardware +PASS Flash image guards: 10 normal/-O tamper/control cases; no hardware +PASS runner failure status: 3 actual entrypoints; baseline=current +PASS mutation oracles: old test misses premature BVALID drop; new test rejects it and old response bug +FULLCHECK_PHASE MEMORY_AND_UNITS +PASS sram_ext depth=8 width=1269 1R1W +PASS robOperands_ext depth=16 width=128 1R1W +PASS tag_array_ext: original RTL + scoreboard, full depth/mask/enable +PASS array_0_0_ext depth=128 width=128 1R1W +PASS bbtile_icache_tag_array_ext: original RTL + scoreboard, full depth/mask/enable +PASS bbtile_icache_data_arrays_0_ext: original RTL + scoreboard, full depth/mask/enable +PASS mem_ext: original RTL + scoreboard, full depth/mask/enable +PASS all memory bindings +build/serial-bound/tb_memories.sv:585: $finish called at 51147000 (1ps) + +PASS core units: PE/formal quantizer, FMA, round shift, FPU RF, group query and SubROB +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/routing-check/RoutingCheck.sv:22:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 22 | module MemMidend( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/routing-check/tb.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ + ... For warning description see https://verilator.org/warn/TIMESCALEMOD?v=5.050 + ... Use "/* verilator lint_off TIMESCALEMOD */" and lint_on around source to disable this message. +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/routing-check/RoutingCheck.sv:272:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 272 | module AccPipe( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/routing-check/tb.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/routing-check/RoutingCheck.sv:379:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 379 | module RoutingCheck( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/routing-check/tb.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +PASS fixed routing: 512 transactions, DMA arbitration, stalls +- /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/routing-check/tb.sv:12: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 15us; walltime 0.001 s; speed 12.635 ms/s +- Verilator: cpu 0.001 s on 1 threads; allocated 6 MB + +FULLCHECK_PHASE WHOLE_CHIP +CPU status = 000000000000b007 +CPU status = 00000000600d600d +PASS whole Toy CPU smoke +- /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:88: Verilog $finish +MEASURE cycles=639544 memory_reads=5970 memory_writes=2049 +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 6ms; walltime 4.710 s; speed 1.358 ms/s +- Verilator: cpu 4.709 s on 1 threads; allocated 8 MB + +/nix/store/ifip54psm478vypifgx8pjl0zv4gw2ci-riscv64-none-elf-binutils-2.46/bin/riscv64-none-elf-ld.bfd: warning: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/gemmini.elf has a LOAD segment with RWX permissions +CPU status = 0000000071000001 +CPU status = 0000000072000001 +CPU status = 0000000071000002 +CPU status = 0000000072000002 +CPU status = 0000000071000003 +CPU status = 0000000072000003 +CPU status = 0000000071000004 +CPU status = 0000000072000004 +CPU status = 0000000071000005 +CPU status = 0000000072000005 +CPU status = 0000000071000006 +CPU status = 0000000072000006 +CPU status = 0000000071000007 +CPU status = 0000000072000007 +CPU status = 0000000071000008 +CPU status = 0000000072000008 +CPU status = 0000000071000009 +CPU status = 0000000072000009 +CPU status = 000000007100000a +CPU status = 000000007200000a +CPU status = 000000007100000b +CPU status = 000000007200000b +CPU status = 000000007100000c +CPU status = 000000007200000c +CPU status = 000000007100000d +CPU status = 000000007200000d +CPU status = 00000000600d600d +PASS whole Toy Gemmini regression +- /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:88: Verilog $finish +MEASURE cycles=245517 memory_reads=674 memory_writes=444 +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 2ms; walltime 2.089 s; speed 1.175 ms/s +- Verilator: cpu 2.089 s on 1 threads; allocated 8 MB + +13/13 upstream Gemmini workloads passed +/nix/store/ifip54psm478vypifgx8pjl0zv4gw2ci-riscv64-none-elf-binutils-2.46/bin/riscv64-none-elf-ld.bfd: warning: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/stress.elf has a LOAD segment with RWX permissions +CPU status = 00000000600d600d +PASS whole Toy 40 alternating multi tile OS WS loops +- /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:88: Verilog $finish +MEASURE cycles=652682 memory_reads=3498 memory_writes=5766 +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 7ms; walltime 4.818 s; speed 1.355 ms/s +- Verilator: cpu 4.817 s on 1 threads; allocated 8 MB + +CPU status = 00000000600d600d +PASS whole Toy unaligned DMA 64 bit beats +- /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:88: Verilog $finish +MEASURE cycles=1879410 memory_reads=2249 memory_writes=1790 +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 19ms; walltime 15.300 s; speed 1.228 ms/s +- Verilator: cpu 15.297 s on 1 threads; allocated 8 MB + +/nix/store/ifip54psm478vypifgx8pjl0zv4gw2ci-riscv64-none-elf-binutils-2.46/bin/riscv64-none-elf-ld.bfd: warning: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/edges.elf has a LOAD segment with RWX permissions +CPU status = 00000000600d600d +PASS whole Toy 64 OS WS RNE edge cases 4096 results +- /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:88: Verilog $finish +MEASURE cycles=979581 memory_reads=3347 memory_writes=2496 +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 10ms; walltime 7.903 s; speed 1.239 ms/s +- Verilator: cpu 7.902 s on 1 threads; allocated 8 MB + +/nix/store/ifip54psm478vypifgx8pjl0zv4gw2ci-riscv64-none-elf-binutils-2.46/bin/riscv64-none-elf-ld.bfd: warning: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/edges.elf has a LOAD segment with RWX permissions +CPU status = 00000000600d600d +PASS whole Toy 64 OS WS RNE edge cases 4096 results +- /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:88: Verilog $finish +MEASURE cycles=978208 memory_reads=3219 memory_writes=2496 +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 10ms; walltime 7.258 s; speed 1.348 ms/s +- Verilator: cpu 7.257 s on 1 threads; allocated 8 MB + +CPU status = 7300000000002048 +CPU status = 7300000100002063 +CPU status = 7300000200002015 +CPU status = 00000000600d600d +PASS whole Toy shared FPU 1536 oracle vectors +- /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:88: Verilog $finish +MEASURE cycles=168403 memory_reads=1387 memory_writes=11 +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 2ms; walltime 1.552 s; speed 1.085 ms/s +- Verilator: cpu 1.552 s on 1 threads; allocated 8 MB + +CPU status = 7300000000001c4a +CPU status = 7300000100001c67 +CPU status = 7300000200002013 +CPU status = 00000000600d600d +PASS whole Toy baseline FPU 1536 oracle vectors +- /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:88: Verilog $finish +MEASURE cycles=165339 memory_reads=1387 memory_writes=11 +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 2ms; walltime 1.258 s; speed 1.314 ms/s +- Verilator: cpu 1.258 s on 1 threads; allocated 8 MB + +FULLCHECK_PHASE BOARD_REGRESSION +PASS fullwidth AXI: sizes 8..128 bits, INCR/FIXED, strobes, concurrent R/W, stalls, IDs, range/4KiB rejection; read beats=90 +/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/tb_axi_fullwidth.sv:107: $finish called at 9270000 (1ps) +PASS SCU OpenSBI byte addresses, AXI lanes, RX pop/IRQ, TX backpressure, EXIT +/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/tb_axi_scu.sv:64: $finish called at 20580000 (1ps) +PASS platform AXI B response: valid, invalid address, unaligned, burst, ID and backpressure +/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/tb_platform_bresp.sv:55: $finish called at 420000 (1ps) +PASS: DDR UART loader CRC, 256-byte unaligned RAM roundtrip, rejected writes/RUN, timeout and boot +/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-unit/tb_ddr_loader.sv:116: $finish called at 78290000 (1ps) +PASS CPU Sv39/FPU/AMO/cache/interrupt through board AXI/SCU cycles=709434 +- /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:56: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 7ms; walltime 6.002 s; speed 1.182 ms/s +- Verilator: cpu 6.001 s on 1 threads; allocated 8 MB + +PASS CPU Sv39/FPU/AMO/cache/interrupt through board AXI/SCU cycles=251063 +- /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:56: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 3ms; walltime 1.874 s; speed 1.340 ms/s +- Verilator: cpu 1.874 s on 1 threads; allocated 8 MB + +PASS CPU Sv39/FPU/AMO/cache/interrupt through board AXI/SCU cycles=684219 +- /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:56: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 7ms; walltime 5.045 s; speed 1.356 ms/s +- Verilator: cpu 5.045 s on 1 threads; allocated 8 MB + +PASS CPU Sv39/FPU/AMO/cache/interrupt through board AXI/SCU cycles=1914839 +- /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:56: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 19ms; walltime 14.179 s; speed 1.351 ms/s +- Verilator: cpu 14.175 s on 1 threads; allocated 8 MB + +PASS BOARD_REGRESSION CPU/Gemmini/loop/DMA +PASS UART_PAYLOAD_READBACK bytes=110592 cycles=61134003 +PASS UART_VERIFIED_RUN cycles=61144580 +PASS CPU Sv39/FPU/AMO/cache/interrupt through board AXI/SCU cycles=61853990 +- /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:56: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 2s; walltime 415.489 s; speed 5.955 ms/s +- Verilator: cpu 415.438 s on 1 threads; allocated 8 MB + +FULLCHECK_PHASE BOARD_IMPLEMENTATION +FULLCHECK_PHASE LINUX_RTL + ____ + + / / / /___ __ _____ ____ _ / /_ ____ _/ / / + + / /_/ / __ `/ | / / _ \ / __ `/ / __ \/ __ `/ / / + + / __ / /_/ /| |/ / __/ / /_/ / / /_/ / /_/ / / / + + /_/ /_/\__,_/ |___/\___/ \__,_/ /_.___/\__,_/_/_/ + + + +/bin/sh: can't access tty; job control turned off + +~ # +SIM_SHELL_PROMPT cycles=309244118 +/root/linux_system_check-linux +SIM_COMMAND_SENT cycles=317001898 overflow=0 framing=0 pending_rx=1 + + +BEGIN LINUX_SYSTEM_CHECK + +PASS VM_COPY_ON_WRITE + +linux_system_ch[25]: unhandled signal 11 code 0x2 at 0x0000003fac65e000 in linux_system_check-linux[10000+7a000] + +CPU: 0 PID: 25 Comm: linux_system_ch Not tainted 6.6.0 #1 + +Hardware name: ucb-bar,buckyball (DT) + +epc : 00000000000105c6 ra : 000000000001041e sp : 0000003fecfb5b50 + + gp : 0000000000090078 tp : 0000000000096760 t0 : 0000000000000000 + + t1 : 0000000000000000 t2 : 0000000000000000 s0 : 0000003fecfb5bd0 + + s1 : 0000003fac65d000 a0 : 0000000000000000 a1 : 0000000000000000 + + a2 : 0000000000000000 a3 : 0000000000000000 a4 : 0000000000000000 + + a5 : 0000000000000000 a6 : 0000000000000000 a7 : 0000000000000000 + + s2 : 0000000000000042 s3 : 0000000000001000 s4 : 0000003fac65e000 + + s5 : 0000003fecfb5d88 s6 : 0000000000000002 s7 : 00000000000106ba + + s8 : 00000000000101e0 s9 : 000000000000003a s10: 0000000000094e28 + + s11: 0000000000000000 t3 : 0000000000000000 t4 : 0000000000000000 + + t5 : 0000000000000000 t6 : 0000000000000000 + +status: 800000020001e020 badaddr: 0000003fac65e000 cause: 000000000000000d + +PASS VM_PAGE_PROTECTION + +PASS FP64_PROCESS_CONTEXT + +PASS LINUX_TIMER elapsed_ns=104208000 + +PASS LINUX_SYSTEM_CHECK +PASS BOARD_LINUX_USERSPACE cycles=340774843 characters=7994 +- /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:99: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 14s; walltime 2622.251 s; speed 5.198 ms/s +- Verilator: cpu 2621.942 s on 1 threads; allocated 264 MB + +FULLCHECK_PHASE WAIT_BOARD +PASS full board implementation /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-rob-ram-20261013-010921 +FULLCHECK_PHASE REAL_XILINX_CDC +RNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information. +WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information. +WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information. +WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information. +WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information. +PASS BOARD_CDC: sizes 8..128 bits, INCR/FIXED, strobes, concurrent R/W, stalls, IDs, range/4KiB rejection; read beats=90 +$finish called at time : 100800 ns : File "/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cdc/tb_board_cdc.sv" Line 221 + +FULLCHECK_PHASE COMPLETE +PASS ROB_PR10_FULL_VALIDATION diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/UPSTREAM_MANIFEST.json b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/UPSTREAM_MANIFEST.json new file mode 100644 index 0000000..7b394cc --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/UPSTREAM_MANIFEST.json @@ -0,0 +1,1014 @@ +{ + "upstream_repository": "https://github.com/DangoSys/buckyball.git", + "commit": "1f3d54535bd5fb76d5fd2f6b05ed36e591cf3097", + "files": { + "LICENSE": { + "sha256": "8aaa2affbbd7b350dea52e1ff1b78198f83f9e1117ce83def35f71de9753217a" + }, + "arch/build.sc": { + "sha256": "81f6e27f6bcdb2c40257c39eda333032a9bf9874478e3c8c65b679e1ab270838" + }, + "arch/src/main/resources/bootrom/linux/Makefile": { + "sha256": "25770880805ba5e2f2202b88b4d12c4ee36983d51fca0363bb3207527764ac12" + }, + "arch/src/main/resources/bootrom/linux/bootrom.S": { + "sha256": "736e0fb94e5f032fb155673ac5d5b5dd8f42c9ab514a7c1c72763eab3bf7c8fb" + }, + "arch/src/main/resources/bootrom/linux/bootrom.rv64.img": { + "sha256": "2144ea7da36f8cbe5f45515658c13e5f344a757495436b249267e06be5b6d230" + }, + "arch/src/main/resources/bootrom/linux/linker.ld": { + "sha256": "8f785c45f62579dba95ddf60e40f10787050d9d106a4659e8e5776d0898102be" + }, + "arch/src/main/scala/framework/balldomain/BallDomain.scala": { + "sha256": "1d1810bb88fabe2cd14e99ed767b879412037ba8e57a29ac95e92ce45ebe1285" + }, + "arch/src/main/scala/framework/balldomain/bbus/bbus.scala": { + "sha256": "85f380b7320ec593d1648f9d1cfa06ec3253117e05ad881a7dafb112cf5ef5ba" + }, + "arch/src/main/scala/framework/balldomain/bbus/cmdrouter/CmdRouter.scala": { + "sha256": "23c770cbd5b768577ffca4bdc46e352d5f6d08acfe7c61f655f782b59edc755e" + }, + "arch/src/main/scala/framework/balldomain/bbus/pmc/BallCyclePMC.scala": { + "sha256": "77a0e9153ad6d48a25472808e1c5f4a03e1bb101c8f0b6ddcee048e4beaa129f" + }, + "arch/src/main/scala/framework/balldomain/bbus/pmc/PMCTraceDPI.scala": { + "sha256": "bc2fba649a6fb4e0287876b102edd883e22bd7a836e7ab3970c5ca5a17dd0d45" + }, + "arch/src/main/scala/framework/balldomain/blink/SubRobRow.scala": { + "sha256": "d5150476786c6c0d818f6e6500773c399a7804b9e373354a3626e84ba92a3f53" + }, + "arch/src/main/scala/framework/balldomain/blink/axis/axis.scala": { + "sha256": "b5e7d4154341339ab8fae7b6b98c0da7fa438918309ebdc95ab206a3dd025669" + }, + "arch/src/main/scala/framework/balldomain/blink/bank.scala": { + "sha256": "4e7f3fe37980f971dee199ed759780c531b00bca84e155d9d92e68612ec82f2d" + }, + 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{ + "sha256": "9801a541398faf022e2183a8db9cde2cdd9d23d181f9c37af2ee0ce810fc5dac" + }, + "examples/chips/toy/workloads/mlir_tests/linalg/CMakeLists.txt": { + "sha256": "585b85e171a4da84bb247055354668e9af7ac041f44e77d075e92385de6bf756" + }, + "examples/chips/toy/workloads/mlir_tests/linalg/conv2d_nchw_fchw.mlir": { + "sha256": "6a3e820e5686d2b44d75fcf3584269eac58f33c7b4dca701b0c30bb6f18e626b" + }, + "examples/chips/toy/workloads/mlir_tests/linalg/conv2d_nchw_fchw_main.cpp": { + "sha256": "e602c43717408d5fd3267cd9c2380c681bb30dd2d2adc5361b1e69af98b26aad" + }, + "examples/chips/toy/workloads/mlir_tests/linalg/conv2d_nhwc_fhwc.mlir": { + "sha256": "cdca3d39bf82cacecb1dc804b4e1037f43123799057d80a46eccac9712b33c07" + }, + "examples/chips/toy/workloads/mlir_tests/linalg/conv2d_nhwc_fhwc_main.cpp": { + "sha256": "88a63156165e26d0b0be689ead7358c1a42e92630bbc98c493702d6fdacf1633" + }, + "examples/chips/toy/workloads/mlir_tests/linalg/conv2d_nhwc_hwcf.mlir": { + "sha256": "e38eeca62e60e12901fbd04d15794322c8348dd21d4a9f43104654b2dd594daf" + }, + "examples/chips/toy/workloads/mlir_tests/linalg/conv2d_nhwc_hwcf_main.cpp": { + "sha256": "c296ba777f8072019dfeee1aa3005021a2b3eace65b8db0d06273a35ce3154aa" + }, + "examples/cores/rocket/configs/balldomains/default.toml": { + "sha256": "86f7ffc9706a3d7644b828dc7786f6f29dfa4194bf3091e6a81e0f699c925990" + }, + "examples/cores/rocket/configs/cpu/default.toml": { + "sha256": "85ea60dc1a2e10633d76e9932fb8701498a7a810a92965f0e967e85e0120a911" + }, + "examples/cores/rocket/configs/cpu/rocket/default.toml": { + "sha256": "820941bace2cc35c93c411ed8a551ea68a92012d715cf81f8507d0eaa1688bd4" + }, + "examples/cores/rocket/configs/default.toml": { + "sha256": "b06582e35013bd0f785a4156cad6921fe2a7d31b499dc2775821080454416981" + }, + "examples/cores/rocket/configs/memdomains/default.toml": { + "sha256": "04f62e6603ba869945c065074c07994293369a3d276210115596ee3f113e24b9" + }, + "examples/cores/toy/configs/balldomains/balls/smatmul/lane16.toml": { + "sha256": "5b04af36b6f3e2a4fd55364576086dbca7765766889035a8e00a63b12d8ec614" + }, + "examples/cores/toy/configs/balldomains/default.toml": { + "sha256": "41b367ae6fc951febb9e5224c4c1ff86ea761623fd87866453adbaf40eac4574" + }, + "examples/cores/toy/configs/cpu/default.toml": { + "sha256": "31c22bce06c93701437878ef17af16b7227eac50b4c9d9620e9aacb4c04d4ac8" + }, + "examples/cores/toy/configs/default.toml": { + "sha256": "6566f24802a2269b7e0486f88065f9a1fff4457c3c58b8b4637d843fad12b922" + }, + "examples/cores/toy/configs/demo.toml": { + "sha256": "c6a269646a773e82ed0e1072ec851a02df672d68a86f0595ca1e3224a0135476" + }, + "examples/cores/toy/configs/frontends/default.toml": { + "sha256": "6d5bf22337811fceff37f048eb0788450cc4c5e1983917b1644595fa9785c072" + }, + "examples/cores/toy/configs/frontends/demo.toml": { + "sha256": "b8d6a933677b88b4c366d6c9f49e59a35e67c2022385e30b40d243760d7955ea" + }, + "examples/cores/toy/configs/gpdomains/default.toml": { + "sha256": "73ef3dffde7b241f51f987a0af3909ca15682627d9efb22d631166e38ef7e80c" + }, + "examples/cores/toy/configs/memdomains/default.toml": { + "sha256": "64c7c3f806058bac75d5b0c090db8bac89ee27a5ca60b8b767a0262b1e2040d3" + } + } +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/README.md b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/README.md new file mode 100644 index 0000000..af10a48 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/README.md @@ -0,0 +1,27 @@ +# Board integration + +Build and programming commands are in [the platform guide](../README.md). +This directory targets Arty A7-100T `xc7a100tcsg324-1` with official Digilent +Rev E.0 DDR parameters. The recorded hardware run passes full payload DDR +readback and Linux checks; physical PCB revision remains unconfirmed. + +- `toy_a7_top.sv`: 100 MHz input, MMCM/BUFG clocks, per-domain reset sequencing, + physical UART/LED/DDR pins, actual MIG and AXI Clock Converter instances. +- `toy_a7_platform.sv`: validated Chisel core, loader/CPU DDR arbitration, + fullwidth memory adapter and SCU console. CPU remains reset until verified RUN. +- `axi_fullwidth.sv`: preserves lanes, strobes, IDs and backpressure while + translating narrow INCR/FIXED beats into aligned 128-bit DDR accesses. +- `ddr_uart_loader.sv` / `loader_axi.sv`: CRC-framed load, readback and release; + acknowledgements wait for DDR responses. INFO bytes preserve LUTRAM inference. +- `axi_scu.sv`: UART/exit MMIO and 256-byte RX FIFO, with accepted-response pops. +- `arty_a7.xdc`: actual pins and targeted asynchronous I/O/reset exceptions; + DDR data/address/control and internal CPU timing remain checked. +- `build_board.tcl`: complete IP generation, synthesis, placement, routing and + bitstream. Setup/hold, CDC Critical, bus skew, routing errors and DRC errors + stop the build. No warning severity downgrade or CDC waiver is applied. +- `program_arty.tcl`: explicit volatile JTAG programming; exactly one target + and one XC7A100T required. The platform's `../program.tcl` entry delegates here. + The exact script used for first bring-up is also archived with the hardware logs. + +`vendor/` contains unmodified pinned Digilent MIG/board inputs and their license. +Vivado generates proprietary vendor IP into ignored build directories locally. diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/SOURCE_MANIFEST.json b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/SOURCE_MANIFEST.json new file mode 100644 index 0000000..3ced1fd --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/SOURCE_MANIFEST.json @@ -0,0 +1,18 @@ +{ + "core_sha256": "4c6aacf64660bbbf14b1114e8d5e4439d6a4e1427aaf1f681c6a4f618f2d2779", + "copied_files": { + "uart_rx.sv": "0b35263884577324f146ff7fd516e5b561dcc8787e0d8ad599669bac1958406d", + "uart_tx.sv": "c20d420fc20be4f6313bdde5abc45ef0b9f8e93bf75350dd9951bc8868b3b65c", + "vendor/board.xml": "5bd9a7ca97ccb2fef617515a14401166464b45a06684d663c0be1a06b02a86df", + "vendor/MANIFEST.json": "3fbfac2499bc99a23356873a5d81e0f87d32f02ec1b7929ead51a15f33d9af85", + "vendor/mig.prj": "914a9e4bb1b3002837592944cdf49f8dfbaf4d112552dd8b5be48602ff1ac329", + "vendor/part0_pins.xml": "50aa844aa9c78af6342de68ae3c980f7618716447b28282878d5a106f86fed31", + "vendor/preset.xml": "ff95b9b976323fefa588873588dfa2bdce1673759c0a9e91c12ee9f2a2955bce" + }, + "clock_hz": 25000000, + "uart_baud": 1000000, + "memory_bytes": 268435456, + "clint_actual_hz": 500000, + "vendor_revision": "E.0", + "physical_board_revision": "unknown" +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/arty_a7.xdc b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/arty_a7.xdc new file mode 100644 index 0000000..51efe3b --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/arty_a7.xdc @@ -0,0 +1,27 @@ +# User pins from Digilent Arty A7-100 Master XDC Rev D/E. DDR pins/timing +# are supplied by the unmodified official MIG output products. +set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports CLK100MHZ] +create_clock -name board_clk -period 10.000 [get_ports CLK100MHZ] +set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS33} [get_ports btn0] +set_property -dict {PACKAGE_PIN A9 IOSTANDARD LVCMOS33} [get_ports uart_txd_in] +set_property -dict {PACKAGE_PIN D10 IOSTANDARD LVCMOS33} [get_ports uart_rxd_out] +set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports {led[0]}] +set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports {led[1]}] +set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {led[2]}] +set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {led[3]}] +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property DRIVE 8 [get_ports {led[*] uart_rxd_out}] +set_property SLEW SLOW [get_ports {led[*] uart_rxd_out}] +# Asynchronous button and UART input: cut only the first synchronizer stage. +set_false_path -from [get_ports btn0] -to [get_pins -hier -filter {NAME =~ *btn_meta_reg/D || NAME =~ *btn_ref_meta_reg/D}] +set_false_path -from [get_ports uart_txd_in] -to [get_pins -hier -filter {NAME =~ *rx_meta_reg/D}] +# Reset assertion is asynchronous; deassertion is synchronized in each domain. +set_false_path -to [get_pins -hier -filter {NAME =~ *lock_sync_reg*/PRE || NAME =~ *ui_reset_pipe_reg*/PRE}] +# Calibration status crosses ui_clk to core_clk through a two-stage synchronizer. +set_false_path -to [get_pins -hier -regexp {.*calib_sync_reg\[0\]/D}] +# Human-visible indicators and asynchronous serial TX have no external clock. +set_false_path -to [get_ports {led[*] uart_rxd_out}] +# DDR RESET_N is an asynchronous memory reset, sequenced by the unmodified MIG +# initialization FSM. It is not a command/data signal sampled on DDR CK edges. +set_false_path -to [get_ports ddr3_reset_n] diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/axi_fullwidth.sv b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/axi_fullwidth.sv new file mode 100644 index 0000000..a17053c --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/axi_fullwidth.sv @@ -0,0 +1,115 @@ +// Serialize each INCR/FIXED AXI beat into an aligned 128-bit MIG transaction. +// Lane positions/strobes and IDs are preserved. Narrow reads may overfetch DDR +// bytes but never MMIO. One read and one write burst can progress independently. +module axi_fullwidth ( + input wire clk, reset, + input wire [3:0] s_awid, s_arid, + input wire [31:0] s_awaddr, s_araddr, + input wire [7:0] s_awlen, s_arlen, + input wire [2:0] s_awsize, s_arsize, + input wire [1:0] s_awburst, s_arburst, + input wire s_awvalid, s_arvalid, s_wvalid, s_wlast, s_bready, s_rready, + output wire s_awready, s_arready, s_wready, + input wire [127:0] s_wdata, input wire [15:0] s_wstrb, + output reg [3:0] s_bid, s_rid, + output reg [1:0] s_bresp, s_rresp, + output reg s_bvalid, s_rvalid, s_rlast, output reg [127:0] s_rdata, + output wire [3:0] m_awid, m_arid, + output wire [27:0] m_awaddr, m_araddr, + output wire [7:0] m_awlen, m_arlen, + output wire [2:0] m_awsize, m_arsize, + output wire [1:0] m_awburst, m_arburst, + output wire m_awvalid, m_arvalid, m_wvalid, m_wlast, m_bready, m_rready, + input wire m_awready, m_arready, m_wready, + output wire [127:0] m_wdata, output wire [15:0] m_wstrb, + input wire [3:0] m_bid, m_rid, + input wire [1:0] m_bresp, m_rresp, + input wire m_bvalid, m_rvalid, m_rlast, input wire [127:0] m_rdata +); + localparam W_IDLE=0, W_DATA=1, W_SEND=2, W_RESP=3; + localparam R_IDLE=0, R_SEND=1, R_RESP=2, R_RETURN=3; + reg [1:0] ws, rs; + reg [31:0] wa, ra; + reg [7:0] wl, rl; + reg [2:0] wz, rz; + reg wi, ri, wbad, rbad, aw_sent, w_sent; + reg [127:0] wd; + reg [15:0] wm; + wire [32:0] wend = {1'b0,s_awaddr} + ({25'd0,s_awlen} << s_awsize); + wire [32:0] rend = {1'b0,s_araddr} + ({25'd0,s_arlen} << s_arsize); + wire wlegal = s_awaddr[31:28]==4'h8 && s_awsize<=4 && s_awburst<=1 && + (s_awaddr & ((32'd1<3 || awburst>1 || + (awaddr & ((31'd1<3 || arburst>1 || (araddr & ((31'd1<=3) rdata[47:40]<={5'd0,framing,overflow,count!=0}; + end else rresp<=2; + end + if(push) begin fifo[wp]<=rx_data;wp<=wp+1'b1;end + if(pop) rp<=rp+1'b1; + case({push,pop}) + 2'b10:count<=count+1'b1; + 2'b01:count<=count-1'b1; + default:count<=count; + endcase + if(rx_valid && !push) overflow<=1; + if(rx_error) framing<=1; + end + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/backup_flash.tcl b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/backup_flash.tcl new file mode 100644 index 0000000..ad12561 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/backup_flash.tcl @@ -0,0 +1,42 @@ +# Read all existing Flash before any erase. This temporarily replaces FPGA SRAM +# with Vivado's SPI bridge, but never requests a Flash write/erase. +if {$argc!=2} {error "Usage: backup_flash.tcl FLASH_PART output.bin"} +lassign $argv part backup +set backup [file normalize $backup] +if {[file exists $backup]} {error "Refusing to overwrite an existing backup"} +if {$part ni {s25fl128sxxxxxx0-spi-x1_x2_x4 s25fl128sxxxxxx1-spi-x1_x2_x4 mt25ql128-spi-x1_x2_x4}} { + error "Select the exact supported 128-Mbit Arty Flash model" +} +open_hw_manager +connect_hw_server -allow_non_jtag +set targets [get_hw_targets -quiet] +if {[llength $targets]!=1} {error "Expected one attached JTAG target"} +open_hw_target [lindex $targets 0] +set devices [get_hw_devices -quiet -filter {PART == xc7a100t}] +if {[llength $devices]!=1} {error "Expected one XC7A100T"} +set device [lindex $devices 0] +current_hw_device $device +set choices [get_cfgmem_parts -of_objects $device -filter "NAME == $part"] +if {[llength $choices]!=1} {error "Flash part is not uniquely compatible with this FPGA"} +create_hw_cfgmem -hw_device $device [lindex $choices 0] +set memory [get_property PROGRAM.HW_CFGMEM $device] +create_hw_bitstream -hw_device $device [get_property PROGRAM.HW_CFGMEM_BITFILE $device] +if {[catch {program_hw_devices $device} message options]} { + return -options $options "SPI bridge programming failed: $message" +} +refresh_hw_device $device +if {[get_property REGISTER.CONFIG_STATUS.BIT14_DONE_PIN $device]!=1 || + [get_property REGISTER.CONFIG_STATUS.BIT04_END_OF_STARTUP_(EOS)_STATUS $device]!=1 || + [get_property REGISTER.CONFIG_STATUS.BIT00_CRC_ERROR $device]!=0} { + error "SPI bridge configuration status rejected" +} +file mkdir [file dirname $backup] +if {[catch {readback_hw_cfgmem -all -file $backup -format bin $memory} message options]} { + return -options $options "Flash readback failed: $message" +} +if {[file size $backup]!=16777216} {error "Incomplete Flash backup"} +puts "PASS FLASH_BACKUP: $part $backup bytes=16777216" +close_hw_target +disconnect_hw_server +close_hw_manager +exit diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/build_board.tcl b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/build_board.tcl new file mode 100644 index 0000000..93159c2 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/build_board.tcl @@ -0,0 +1,86 @@ +set root [file dirname [file dirname [file normalize [info script]]]] +cd $root +if {[llength $argv]<1 || [llength $argv]>2} {error "Usage: build_board.tcl OUTPUT_DIRECTORY ?flash?"} +set flash 0 +if {[llength $argv]==2} { + if {[lindex $argv 1] ne "flash"} {error "Second argument must be flash"} + set flash 1 +} +set out [file normalize [lindex $argv 0]] +file mkdir $out +file mkdir $out/ip +proc phase {name} { + global out + set f [open $out/phase.txt w];puts $f $name;close $f + puts "BOARD_PHASE $name" +} +set_param general.maxThreads 8 +phase CREATE_IP +create_project -in_memory -part xc7a100tcsg324-1 +set_property target_language Verilog [current_project] +create_ip -name mig_7series -vendor xilinx.com -library ip -version 4.2 -module_name arty_ddr3 -dir $out/ip +set_property CONFIG.XML_INPUT_FILE $root/board/vendor/mig.prj [get_ips arty_ddr3] +create_ip -name axi_clock_converter -vendor xilinx.com -library ip -version 2.1 -module_name toy_axi_cdc -dir $out/ip +set_property -dict {CONFIG.PROTOCOL AXI4 CONFIG.ADDR_WIDTH 28 CONFIG.DATA_WIDTH 128 CONFIG.ID_WIDTH 4 CONFIG.ACLK_ASYNC 1 CONFIG.SYNCHRONIZATION_STAGES 3} [get_ips toy_axi_cdc] +generate_target all [get_ips] +report_ip_status -file $out/ip-status.rpt +phase SYNTH_IP +synth_ip [get_ips] +phase SYNTH_BOARD +if {$flash} {read_verilog -sv $root/build/flash-boot/ToyLinuxChip.sv} else { + read_verilog -sv $root/build/serial-bound/ToyLinuxChip.sv +} +read_verilog -sv $root/build/serial-bound/FpgaMemories.sv +foreach f [glob $root/board/*.sv] {read_verilog -sv $f} +set_property verilog_define {SYNTHESIS BUCKYBALL_DISABLE_DPI} [current_fileset] +read_xdc $root/board/arty_a7.xdc +read_xdc $root/board/flash_boot.xdc +synth_design -top toy_a7_top -part xc7a100tcsg324-1 -flatten_hierarchy rebuilt -directive AreaOptimized_high -resource_sharing on -generic FLASH_BOOT=$flash +write_checkpoint -force $out/synthesized.dcp +report_utilization -file $out/synth-utilization.rpt +report_utilization -hierarchical -file $out/synth-hierarchy.rpt +report_timing_summary -delay_type min_max -file $out/synth-timing.rpt +set unresolved [get_cells -hier -quiet -filter {IS_BLACKBOX == 1}] +if {[llength $unresolved]} {error "Unresolved black boxes: $unresolved"} +phase OPTIMIZE +opt_design -directive ExploreArea +write_checkpoint -force $out/optimized.dcp +report_utilization -file $out/opt-utilization.rpt +phase PLACE +place_design -directive Explore +write_checkpoint -force $out/placed.dcp +phase PHYS_OPT +phys_opt_design -directive Explore +phase ROUTE +route_design -directive Explore +write_checkpoint -force $out/routed.dcp +phase REPORT +report_utilization -file $out/routed-utilization.rpt +report_utilization -hierarchical -file $out/routed-hierarchy.rpt +report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -file $out/routed-timing.rpt +report_route_status -file $out/route-status.rpt +report_drc -file $out/drc.rpt +set cdc [report_cdc -details -return_string] +set f [open $out/cdc.rpt w];puts $f $cdc;close $f +set skew [report_bus_skew -return_string] +set f [open $out/bus-skew.rpt w];puts $f $skew;close $f +report_methodology -file $out/methodology.rpt +report_io -file $out/io.rpt +report_clocks -file $out/clocks.rpt +check_timing -verbose -file $out/check-timing.rpt +if {[regexp {CDC-[0-9]+\s+Critical} $cdc]} {error "Critical CDC findings; see cdc.rpt"} +if {[string match *VIOLATED* $skew]} {error "Bus skew failed; see bus-skew.rpt"} +foreach kind {max min} { + set paths [get_timing_paths -delay_type $kind -max_paths 1] + if {[llength $paths]==0} {error "Missing $kind timing paths"} + if {[get_property SLACK [lindex $paths 0]]<0} {error "$kind timing failed"} +} +if {![report_route_status -boolean_check ROUTED_FULLY]} {error "Routing incomplete"} +if {[report_route_status -boolean_check ERRORS_IN_ROUTES]} {error "Routing errors"} +set errors [get_drc_violations -quiet -filter {SEVERITY == Error || SEVERITY == {Critical Warning}}] +if {[llength $errors]} {error "DRC errors/critical warnings: $errors"} +phase BITSTREAM +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +write_bitstream -force $out/toy_a7.bit +phase COMPLETE +puts "PASS BOARD_PLACE_ROUTE_TIMING_BITSTREAM: engineering Rev E target; flash=$flash; this build does not validate physical boot" diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/ddr_uart_loader.sv b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/ddr_uart_loader.sv new file mode 100644 index 0000000..9aa2dc9 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/ddr_uart_loader.sv @@ -0,0 +1,169 @@ +// Stop-and-wait serial boot protocol. Requests: A5 5A op seq addrLE32 lenLE16 +// [WRITE payload] crcLE16. CRC-16/CCITT-FALSE covers op through payload. +// Responses: 5A A5 (op|80) seq status lenLE16 [data] crcLE16. +// CRC is checked before any DDR write; CPU starts after the RUN reply drains. +module ddr_uart_loader #( + parameter integer RAM_BYTES = 268435456, + parameter integer CLOCK_HZ = 25000000, + parameter integer RX_TIMEOUT = CLOCK_HZ/10 +) ( + input wire clk, reset, + input wire rx_valid, input wire [7:0] rx_data, input wire rx_error, + output wire tx_valid, output reg [7:0] tx_data, input wire tx_ready, + output reg cpu_run, output reg error_seen, + output wire load_en, + output wire [$clog2(RAM_BYTES)-1:0] load_addr, + output reg [127:0] load_data, + output reg [15:0] load_mask, + input wire load_valid, load_error, input wire [127:0] load_result +); + localparam [3:0] SYNC0=0,SYNC1=1,HEADER=2,PAYLOAD=3,CRC0=4,CRC1=5, + EXECUTE=6,WRITE=7,READ_REQ=8,READ_WAIT=9,REPLY=10,DRAIN=11; + reg [3:0] state; + reg [7:0] operation, sequence_id, status; + reg [31:0] address; + reg [15:0] length, reply_length, crc, received_crc; + reg [8:0] cursor, reply_index; + reg [3:0] header_index; + (* ram_style="distributed" *) reg [7:0] payload [0:255]; + reg pending_run, image_loaded; + reg [$clog2(RX_TIMEOUT+1)-1:0] timeout_count; + wire receiving = state==SYNC1 || state==HEADER || state==PAYLOAD || state==CRC0 || state==CRC1; + wire [32:0] end_address = {1'b0,address}+length; + wire valid_range = length!=0 && length<=256 && address>=32'h80000000 && + end_address<=33'h080000000+RAM_BYTES; + wire [31:0] byte_address = address + cursor; + assign load_addr = byte_address[$clog2(RAM_BYTES)-1:0]; + assign load_en = !cpu_run && (state==WRITE || state==READ_REQ); + always @* begin + load_data=0;load_mask=0; + if(state==WRITE) begin + load_data[byte_address[3:0]*8 +: 8]=payload[cursor[7:0]]; + load_mask=16'b1<> ((reply_index-11)*8); + 15,16,17,18:tx_data=CLOCK_HZ >> ((reply_index-15)*8); + default:tx_data=0; + endcase + else tx_data=payload[(reply_index-7) & 255]; + end + else if(reply_index==7+reply_length) tx_data=crc[7:0]; + else tx_data=crc[15:8]; + end + endcase + end + always @(posedge clk) begin + if(reset) begin + state<=SYNC0;cpu_run<=0;error_seen<=0;image_loaded<=0;pending_run<=0; + operation<=0;sequence_id<=0;status<=0;address<=0;length<=0; + reply_length<=0;crc<=16'hffff;received_crc<=0;cursor<=0; + reply_index<=0;header_index<=0;timeout_count<=0; + end else if(!cpu_run) begin + if(!receiving || rx_valid) timeout_count<=0; + else timeout_count<=timeout_count+1'b1; + if((receiving && timeout_count==RX_TIMEOUT-1) || (receiving && rx_error)) begin + state<=SYNC0;error_seen<=1;timeout_count<=0; + end else case(state) + SYNC0: if(rx_valid && rx_data==8'ha5) state<=SYNC1; + SYNC1: if(rx_valid) begin + if(rx_data==8'h5a) begin + state<=HEADER;header_index<=0;crc<=16'hffff;length<=0;address<=0; + pending_run<=0;reply_index<=0;reply_length<=0;status<=0; + end else if(rx_data!=8'ha5) state<=SYNC0; + end + HEADER: if(rx_valid) begin + crc<=crc_next(crc,rx_data); + case(header_index) + 0:operation<=rx_data; + 1:sequence_id<=rx_data; + 2:address[7:0]<=rx_data; + 3:address[15:8]<=rx_data; + 4:address[23:16]<=rx_data; + 5:address[31:24]<=rx_data; + 6:length[7:0]<=rx_data; + 7:begin + length[15:8]<=rx_data;cursor<=0; + if({rx_data,length[7:0]}>256) begin state<=SYNC0;error_seen<=1;end + else if(operation==1 && {rx_data,length[7:0]}!=0) state<=PAYLOAD; + else state<=CRC0; + end + endcase + header_index<=header_index+1'b1; + end + PAYLOAD: if(rx_valid) begin + payload[cursor[7:0]]<=rx_data;crc<=crc_next(crc,rx_data); + cursor<=cursor+1'b1; + if(cursor+1==length) state<=CRC0; + end + CRC0: if(rx_valid) begin received_crc[7:0]<=rx_data;state<=CRC1;end + CRC1: if(rx_valid) begin + cursor<=0; + if({rx_data,received_crc[7:0]}!=crc) begin + status<=1;error_seen<=1;crc<=16'hffff;state<=REPLY; + end else state<=EXECUTE; + end + EXECUTE: begin + crc<=16'hffff; + if(operation==1 || operation==2) begin + if(!valid_range) begin status<=2;error_seen<=1;state<=REPLY;end + else if(operation==1) state<=WRITE; + else begin reply_length<=length;state<=READ_REQ;end + end else if(operation==3 && length==0 && address==32'h80000000) begin + if(!image_loaded) begin status<=5;error_seen<=1;end + else pending_run<=1; + state<=REPLY; + end else if(operation==4 && length==0 && address==0) begin + reply_length<=12;state<=REPLY; + end else begin status<=3;error_seen<=1;state<=REPLY;end + end + WRITE: if(load_valid) begin + if(load_error) begin status<=6;error_seen<=1;state<=REPLY;end + else if(cursor+1==length) begin image_loaded<=1;state<=REPLY;end + else cursor<=cursor+1'b1; + end + READ_REQ: state<=READ_WAIT; + READ_WAIT: if(load_valid) begin + if(load_error) begin status<=6;error_seen<=1;reply_length<=0;state<=REPLY;end + else begin + payload[cursor[7:0]]<=load_result[byte_address[3:0]*8 +: 8]; + if(cursor+1==length) state<=REPLY; + else begin cursor<=cursor+1'b1;state<=READ_REQ;end + end + end + REPLY: if(tx_ready) begin + if(reply_index>=2 && reply_index<7+reply_length) crc<=crc_next(crc,tx_data); + if(reply_index==8+reply_length) state<=DRAIN; + else reply_index<=reply_index+1'b1; + end + DRAIN: if(tx_ready) begin + if(pending_run) cpu_run<=1; + state<=SYNC0; + end + default:state<=SYNC0; + endcase + end + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/flash_boot.xdc b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/flash_boot.xdc new file mode 100644 index 0000000..902d6a7 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/flash_boot.xdc @@ -0,0 +1,19 @@ +# Digilent Arty-A7-100-Master.xdc Rev D/E; CCLK is owned by STARTUPE2. +set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS33} [get_ports sw0] +set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS33} [get_ports flash_cs_n] +set_property -dict {PACKAGE_PIN K17 IOSTANDARD LVCMOS33} [get_ports flash_mosi] +set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33} [get_ports flash_miso] +set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS33} [get_ports flash_wp_n] +set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS33} [get_ports flash_hold_n] +set_property DRIVE 8 [get_ports {flash_cs_n flash_mosi flash_wp_n flash_hold_n}] +set_property SLEW SLOW [get_ports {flash_cs_n flash_mosi flash_wp_n flash_hold_n}] +set switch_sync [get_pins -quiet -hier -filter {NAME =~ *sw_meta_reg/D}] +if {[llength $switch_sync]} {set_false_path -from [get_ports sw0] -to $switch_sync} +# Serial input sampled after two synchronizer stages. Mode-0 half bit is 160 ns; +# the external data settles before these stages, then is sampled on the next rise. +set flash_sync [get_pins -quiet -hier -filter {NAME =~ *miso_meta_reg/D}] +if {[llength $flash_sync]} {set_false_path -from [get_ports flash_miso] -to $flash_sync} +set_false_path -to [get_ports {flash_cs_n flash_mosi flash_wp_n flash_hold_n}] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 1 [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 16 [current_design] +set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/flash_spi_byte.sv b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/flash_spi_byte.sv new file mode 100644 index 0000000..1610a12 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/flash_spi_byte.sv @@ -0,0 +1,33 @@ +// Read-only boot software uses this mode-0 byte engine; no Flash writes in RTL. +// 25 MHz / (2 * 4) = 3.125 MHz. Two MISO synchronizers settle within a half bit. +module flash_spi_byte ( + input wire clk, reset, start, + input wire [7:0] tx_data, + input wire miso, + output reg busy, sck, + output wire mosi, + output reg [7:0] rx_data +); + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg miso_meta, miso_sync; + reg [7:0] shift_tx, shift_rx; + reg [2:0] bit_count; + reg [1:0] divider; + assign mosi=shift_tx[7]; + always @(posedge clk) begin + miso_meta<=miso;miso_sync<=miso_meta; + if(reset) begin + busy<=0;sck<=0;shift_tx<=0;shift_rx<=0;rx_data<=0;bit_count<=0;divider<=0; + end else if(!busy) begin + sck<=0; + if(start) begin busy<=1;shift_tx<=tx_data;shift_rx<=0;bit_count<=0;divider<=0;end + end else if(divider==3) begin + divider<=0;sck<=!sck; + if(!sck) shift_rx<={shift_rx[6:0],miso_sync}; + else begin + shift_tx<={shift_tx[6:0],1'b1}; + if(bit_count==7) begin busy<=0;rx_data<=shift_rx;end + else bit_count<=bit_count+1'b1; + end + end else divider<=divider+1'b1; + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/loader_axi.sv b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/loader_axi.sv new file mode 100644 index 0000000..096ddb0 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/loader_axi.sv @@ -0,0 +1,53 @@ +// Convert a held loader byte request into a completed AXI transaction. +// The loader advances only after B/R. A RELEASE cycle prevents resubmission +// while its synchronous state machine consumes the acknowledgement. +module loader_axi ( + input wire clk, reset, load_en, + input wire [27:0] load_addr, + input wire [127:0] load_data, input wire [15:0] load_mask, + output reg load_valid, load_error, output reg [127:0] load_result, + output wire [27:0] awaddr, araddr, + output wire awvalid, wvalid, arvalid, bready, rready, + input wire awready, wready, arready, bvalid, rvalid, + output wire [127:0] wdata, output wire [15:0] wstrb, + input wire [1:0] bresp, rresp, input wire [127:0] rdata +); + localparam IDLE=0, SEND_W=1, WAIT_B=2, SEND_R=3, WAIT_R=4, RELEASE=5; + reg [2:0] state; + reg [27:0] addr; + reg [127:0] data; + reg [15:0] mask; + reg sent_aw, sent_w; + assign awaddr=addr;assign araddr=addr; + assign wdata=data;assign wstrb=mask; + assign awvalid=!reset && state==SEND_W && !sent_aw; + assign wvalid=!reset && state==SEND_W && !sent_w; + assign arvalid=!reset && state==SEND_R; + assign bready=!reset && state==WAIT_B; + assign rready=!reset && state==WAIT_R; + always @(posedge clk) begin + load_valid<=0; + if(reset) begin + state<=IDLE;addr<=0;data<=0;mask<=0;sent_aw<=0;sent_w<=0; + load_valid<=0;load_error<=0;load_result<=0; + end else case(state) + IDLE:if(load_en) begin + addr<={load_addr[27:4],4'd0};data<=load_data;mask<=load_mask; + sent_aw<=0;sent_w<=0;load_error<=0; + state<=|load_mask ? SEND_W : SEND_R; + end + SEND_W:begin + if(awvalid && awready) sent_aw<=1; + if(wvalid && wready) sent_w<=1; + if((sent_aw || awready) && (sent_w || wready)) state<=WAIT_B; + end + WAIT_B:if(bvalid) begin load_valid<=1;load_error<=bresp!=0;state<=RELEASE;end + SEND_R:if(arready) state<=WAIT_R; + WAIT_R:if(rvalid) begin + load_valid<=1;load_error<=rresp!=0;load_result<=rdata;state<=RELEASE; + end + RELEASE:state<=IDLE; + default:state<=IDLE; + endcase + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/make_flash_image.tcl b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/make_flash_image.tcl new file mode 100644 index 0000000..ad0a6d6 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/make_flash_image.tcl @@ -0,0 +1,18 @@ +# Combine configuration and packed software without crossing partitions. +if {$argc!=3} {error "Usage: make_flash_image.tcl toy_a7.bit flash_payload.bin output.mcs"} +lassign $argv bitfile payload output +set bitfile [file normalize $bitfile] +set payload [file normalize $payload] +set output [file normalize $output] +if {![file isfile $bitfile] || ![file isfile $payload]} {error "Missing input file"} +if {[file size $bitfile]>=0x400000} {error "Configuration exceeds the 4 MiB partition"} +if {[file size $payload]<=32 || [file size $payload]>0xc00000} {error "Invalid software partition size"} +set f [open $payload rb] +set magic [read $f 8] +close $f +if {$magic ne "TOYFLZ4\x00"} {error "Expected a packed TOYFLZ4 image"} +file mkdir [file dirname $output] +write_cfgmem -force -format mcs -interface SPIx1 -size 16 \ + -loadbit [list up 0x00000000 $bitfile] -loaddata [list up 0x00400000 $payload] -file $output +puts "PASS FLASH_IMAGE_LAYOUT: config=0x0 software=0x400000 capacity=16MiB" +exit diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/program_arty.tcl b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/program_arty.tcl new file mode 100644 index 0000000..a328bd8 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/program_arty.tcl @@ -0,0 +1,32 @@ +# Volatile JTAG programming only. Usage: +# Confirm physical Rev E DDR compatibility before using this engineering image. +# vivado -mode batch -source board/program_arty.tcl -tclargs /path/to/toy_a7.bit +if {$argc != 1} { error "Supply the Arty A7-100T .bit file" } +set bitfile [file normalize [lindex $argv 0]] +if {![file isfile $bitfile]} { error "Bitstream not found: $bitfile" } +open_hw_manager +connect_hw_server -allow_non_jtag +set targets [get_hw_targets -quiet] +if {[llength $targets] != 1} { + error "Expected one connected JTAG target. Select the Arty manually in Hardware Manager if multiple boards are attached." +} +open_hw_target [lindex $targets 0] +set devices [get_hw_devices -quiet -filter {PART == xc7a100t}] +if {[llength $devices] != 1} { error "Expected one XC7A100T; inspect the connected board" } +set device [lindex $devices 0] +current_hw_device $device +set_property PROGRAM.FILE $bitfile $device +if {[catch {program_hw_devices $device} message options]} { + return -options $options "JTAG programming failed: $message" +} +refresh_hw_device $device +if {[get_property REGISTER.CONFIG_STATUS.BIT14_DONE_PIN $device]!=1 || + [get_property REGISTER.CONFIG_STATUS.BIT04_END_OF_STARTUP_(EOS)_STATUS $device]!=1 || + [get_property REGISTER.CONFIG_STATUS.BIT00_CRC_ERROR $device]!=0} { + error "JTAG configuration status rejected: expected DONE/EOS high and CRC error clear" +} +puts "ARTY_JTAG_PROGRAMMED: $bitfile" +close_hw_target +disconnect_hw_server +close_hw_manager +exit diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/program_flash.tcl b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/program_flash.tcl new file mode 100644 index 0000000..3b47630 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/program_flash.tcl @@ -0,0 +1,63 @@ +# Explicit nonvolatile programming: backs up Flash, then erases/programs/verifies. +if {$argc!=3} {error "Usage: program_flash.tcl image.mcs FLASH_PART fresh-backup.bin"} +lassign $argv image part backup +set image [file normalize $image] +set backup [file normalize $backup] +if {![file isfile $image]} {error "Missing Flash image"} +if {[file exists $backup]} {error "Refusing to overwrite an existing backup"} +if {$part ni {s25fl128sxxxxxx0-spi-x1_x2_x4 s25fl128sxxxxxx1-spi-x1_x2_x4 mt25ql128-spi-x1_x2_x4}} { + error "Select the exact supported 128-Mbit Arty Flash model" +} +open_hw_manager +connect_hw_server -allow_non_jtag +set targets [get_hw_targets -quiet] +if {[llength $targets]!=1} {error "Expected one attached JTAG target"} +open_hw_target [lindex $targets 0] +set devices [get_hw_devices -quiet -filter {PART == xc7a100t}] +if {[llength $devices]!=1} {error "Expected one XC7A100T"} +set device [lindex $devices 0] +current_hw_device $device +set choices [get_cfgmem_parts -of_objects $device -filter "NAME == $part"] +if {[llength $choices]!=1} {error "Flash part is not uniquely compatible with this FPGA"} +create_hw_cfgmem -hw_device $device [lindex $choices 0] +set memory [get_property PROGRAM.HW_CFGMEM $device] +create_hw_bitstream -hw_device $device [get_property PROGRAM.HW_CFGMEM_BITFILE $device] +if {[catch {program_hw_devices $device} message options]} { + return -options $options "SPI bridge programming failed: $message" +} +refresh_hw_device $device +if {[get_property REGISTER.CONFIG_STATUS.BIT14_DONE_PIN $device]!=1 || + [get_property REGISTER.CONFIG_STATUS.BIT04_END_OF_STARTUP_(EOS)_STATUS $device]!=1 || + [get_property REGISTER.CONFIG_STATUS.BIT00_CRC_ERROR $device]!=0} { + error "SPI bridge configuration status rejected; Flash programming cancelled" +} +file mkdir [file dirname $backup] +if {[catch {readback_hw_cfgmem -all -file $backup -format bin $memory} message options]} { + return -options $options "Flash backup failed; programming cancelled: $message" +} +if {[file size $backup]!=16777216} {error "Incomplete backup; programming cancelled"} +puts "PASS FLASH_BACKUP: $backup bytes=16777216" +set_property PROGRAM.ADDRESS_RANGE use_file $memory +set_property PROGRAM.FILES [list $image] $memory +set_property PROGRAM.BLANK_CHECK 0 $memory +set_property PROGRAM.ERASE 1 $memory +set_property PROGRAM.CFG_PROGRAM 1 $memory +set_property PROGRAM.VERIFY 1 $memory +set_property PROGRAM.CHECKSUM 0 $memory +if {[catch {program_hw_cfgmem $memory} message options]} { + return -options $options "Flash program/verify failed: $message" +} +puts "PASS FLASH_PROGRAM_VERIFY: $part $image" +# JP1 must be shorted; this reloads the FPGA from Flash without downloading .bit. +boot_hw_device -timeout 60 $device +refresh_hw_device $device +if {[get_property REGISTER.CONFIG_STATUS.BIT14_DONE_PIN $device]!=1 || + [get_property REGISTER.CONFIG_STATUS.BIT04_END_OF_STARTUP_(EOS)_STATUS $device]!=1 || + [get_property REGISTER.CONFIG_STATUS.BIT00_CRC_ERROR $device]!=0} { + error "FPGA did not successfully reconfigure from Flash" +} +puts "FLASH_BOOT_CONFIG_STATUS [get_property REGISTER.CONFIG_STATUS $device]" +close_hw_target +disconnect_hw_server +close_hw_manager +exit diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/toy_a7_platform.sv b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/toy_a7_platform.sv new file mode 100644 index 0000000..ade0c4d --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/toy_a7_platform.sv @@ -0,0 +1,450 @@ +// Generated wiring; source CPU/accelerator RTL is byte-identical. +module toy_a7_platform #(parameter UART_DIVISOR=25, parameter FLASH_BOOT=0) ( + input wire clk, reset, uart_rx_in, + output wire uart_tx_out, cpu_run, exited, loader_error, + output wire [31:0] exit_code, + output wire [3:0] ddr_awid, + output wire [27:0] ddr_awaddr, + output wire [7:0] ddr_awlen, + output wire [2:0] ddr_awsize, + output wire [1:0] ddr_awburst, + output wire ddr_awvalid, + input wire ddr_awready, + output wire [127:0] ddr_wdata, + output wire [15:0] ddr_wstrb, + output wire ddr_wlast, + output wire ddr_wvalid, + input wire ddr_wready, + input wire [3:0] ddr_bid, + input wire [1:0] ddr_bresp, + input wire ddr_bvalid, + output wire ddr_bready, + output wire [3:0] ddr_arid, + output wire [27:0] ddr_araddr, + output wire [7:0] ddr_arlen, + output wire [2:0] ddr_arsize, + output wire [1:0] ddr_arburst, + output wire ddr_arvalid, + input wire ddr_arready, + input wire [3:0] ddr_rid, + input wire [127:0] ddr_rdata, + input wire [1:0] ddr_rresp, + input wire ddr_rlast, + input wire ddr_rvalid, + output wire ddr_rready, + input wire flash_miso, flash_recovery, + output wire flash_mosi, flash_sck, flash_cs_n +); + wire cpu_reset=reset || !cpu_run; + wire loader_cpu_run; + assign cpu_run=loader_cpu_run || (FLASH_BOOT && !flash_recovery); + wire irq; + wire rx_valid, rx_error, tx_ready, loader_tx_valid, mmio_tx_valid; + wire [7:0] rx_data, loader_tx_data, mmio_tx_data; + wire load_en, load_valid, load_error; wire [27:0] load_addr; + wire [127:0] load_data, load_result; wire [15:0] load_mask; + uart_rx #(.DIVISOR(UART_DIVISOR)) receiver (.clk(clk),.reset(reset),.rx(uart_rx_in), + .valid(rx_valid),.data(rx_data),.frame_error(rx_error)); + uart_tx #(.DIVISOR(UART_DIVISOR)) transmitter (.clk(clk),.reset(reset), + .valid(cpu_run ? mmio_tx_valid : loader_tx_valid),.data(cpu_run ? mmio_tx_data : loader_tx_data), + .ready(tx_ready),.tx(uart_tx_out)); + ddr_uart_loader loader (.clk(clk),.reset(reset),.rx_valid(rx_valid && !cpu_run),.rx_data(rx_data), + .rx_error(rx_error),.tx_valid(loader_tx_valid),.tx_data(loader_tx_data),.tx_ready(tx_ready), + .cpu_run(loader_cpu_run),.error_seen(loader_error),.load_en(load_en),.load_addr(load_addr), + .load_data(load_data),.load_mask(load_mask),.load_valid(load_valid),.load_error(load_error),.load_result(load_result)); + wire memory_aw_ready; + wire memory_aw_valid; + wire [3:0] memory_aw_bits_id; + wire [31:0] memory_aw_bits_addr; + wire [7:0] memory_aw_bits_len; + wire [2:0] memory_aw_bits_size; + wire [1:0] memory_aw_bits_burst; + wire memory_aw_bits_lock; + wire [3:0] memory_aw_bits_cache; + wire [2:0] memory_aw_bits_prot; + wire [3:0] memory_aw_bits_qos; + wire memory_w_ready; + wire memory_w_valid; + wire [127:0] memory_w_bits_data; + wire [15:0] memory_w_bits_strb; + wire memory_w_bits_last; + wire memory_b_ready; + wire memory_b_valid; + wire [3:0] memory_b_bits_id; + wire [1:0] memory_b_bits_resp; + wire memory_ar_ready; + wire memory_ar_valid; + wire [3:0] memory_ar_bits_id; + wire [31:0] memory_ar_bits_addr; + wire [7:0] memory_ar_bits_len; + wire [2:0] memory_ar_bits_size; + wire [1:0] memory_ar_bits_burst; + wire memory_ar_bits_lock; + wire [3:0] memory_ar_bits_cache; + wire [2:0] memory_ar_bits_prot; + wire [3:0] memory_ar_bits_qos; + wire memory_r_ready; + wire memory_r_valid; + wire [3:0] memory_r_bits_id; + wire [127:0] memory_r_bits_data; + wire [1:0] memory_r_bits_resp; + wire memory_r_bits_last; + wire peripherals_aw_ready; + wire peripherals_aw_valid; + wire [1:0] peripherals_aw_bits_id; + wire [30:0] peripherals_aw_bits_addr; + wire [7:0] peripherals_aw_bits_len; + wire [2:0] peripherals_aw_bits_size; + wire [1:0] peripherals_aw_bits_burst; + wire peripherals_aw_bits_lock; + wire [3:0] peripherals_aw_bits_cache; + wire [2:0] peripherals_aw_bits_prot; + wire [3:0] peripherals_aw_bits_qos; + wire peripherals_w_ready; + wire peripherals_w_valid; + wire [63:0] peripherals_w_bits_data; + wire [7:0] peripherals_w_bits_strb; + wire peripherals_w_bits_last; + wire peripherals_b_ready; + wire peripherals_b_valid; + wire [1:0] peripherals_b_bits_id; + wire [1:0] peripherals_b_bits_resp; + wire peripherals_ar_ready; + wire peripherals_ar_valid; + wire [1:0] peripherals_ar_bits_id; + wire [30:0] peripherals_ar_bits_addr; + wire [7:0] peripherals_ar_bits_len; + wire [2:0] peripherals_ar_bits_size; + wire [1:0] peripherals_ar_bits_burst; + wire peripherals_ar_bits_lock; + wire [3:0] peripherals_ar_bits_cache; + wire [2:0] peripherals_ar_bits_prot; + wire [3:0] peripherals_ar_bits_qos; + wire peripherals_r_ready; + wire peripherals_r_valid; + wire [1:0] peripherals_r_bits_id; + wire [63:0] peripherals_r_bits_data; + wire [1:0] peripherals_r_bits_resp; + wire peripherals_r_bits_last; + ToyLinuxChip chip ( + .clock(clk), + .reset(cpu_reset), + .interrupt(irq), + .memory_aw_ready(memory_aw_ready), + .memory_aw_valid(memory_aw_valid), + .memory_aw_bits_id(memory_aw_bits_id), + .memory_aw_bits_addr(memory_aw_bits_addr), + .memory_aw_bits_len(memory_aw_bits_len), + .memory_aw_bits_size(memory_aw_bits_size), + .memory_aw_bits_burst(memory_aw_bits_burst), + .memory_aw_bits_lock(memory_aw_bits_lock), + .memory_aw_bits_cache(memory_aw_bits_cache), + .memory_aw_bits_prot(memory_aw_bits_prot), + .memory_aw_bits_qos(memory_aw_bits_qos), + .memory_w_ready(memory_w_ready), + .memory_w_valid(memory_w_valid), + .memory_w_bits_data(memory_w_bits_data), + .memory_w_bits_strb(memory_w_bits_strb), + .memory_w_bits_last(memory_w_bits_last), + .memory_b_ready(memory_b_ready), + .memory_b_valid(memory_b_valid), + .memory_b_bits_id(memory_b_bits_id), + .memory_b_bits_resp(memory_b_bits_resp), + .memory_ar_ready(memory_ar_ready), + .memory_ar_valid(memory_ar_valid), + .memory_ar_bits_id(memory_ar_bits_id), + .memory_ar_bits_addr(memory_ar_bits_addr), + .memory_ar_bits_len(memory_ar_bits_len), + .memory_ar_bits_size(memory_ar_bits_size), + .memory_ar_bits_burst(memory_ar_bits_burst), + .memory_ar_bits_lock(memory_ar_bits_lock), + .memory_ar_bits_cache(memory_ar_bits_cache), + .memory_ar_bits_prot(memory_ar_bits_prot), + .memory_ar_bits_qos(memory_ar_bits_qos), + .memory_r_ready(memory_r_ready), + .memory_r_valid(memory_r_valid), + .memory_r_bits_id(memory_r_bits_id), + .memory_r_bits_data(memory_r_bits_data), + .memory_r_bits_resp(memory_r_bits_resp), + .memory_r_bits_last(memory_r_bits_last), + .peripherals_aw_ready(peripherals_aw_ready), + .peripherals_aw_valid(peripherals_aw_valid), + .peripherals_aw_bits_id(peripherals_aw_bits_id), + .peripherals_aw_bits_addr(peripherals_aw_bits_addr), + .peripherals_aw_bits_len(peripherals_aw_bits_len), + .peripherals_aw_bits_size(peripherals_aw_bits_size), + .peripherals_aw_bits_burst(peripherals_aw_bits_burst), + .peripherals_aw_bits_lock(peripherals_aw_bits_lock), + .peripherals_aw_bits_cache(peripherals_aw_bits_cache), + .peripherals_aw_bits_prot(peripherals_aw_bits_prot), + .peripherals_aw_bits_qos(peripherals_aw_bits_qos), + .peripherals_w_ready(peripherals_w_ready), + .peripherals_w_valid(peripherals_w_valid), + .peripherals_w_bits_data(peripherals_w_bits_data), + .peripherals_w_bits_strb(peripherals_w_bits_strb), + .peripherals_w_bits_last(peripherals_w_bits_last), + .peripherals_b_ready(peripherals_b_ready), + .peripherals_b_valid(peripherals_b_valid), + .peripherals_b_bits_id(peripherals_b_bits_id), + .peripherals_b_bits_resp(peripherals_b_bits_resp), + .peripherals_ar_ready(peripherals_ar_ready), + .peripherals_ar_valid(peripherals_ar_valid), + .peripherals_ar_bits_id(peripherals_ar_bits_id), + .peripherals_ar_bits_addr(peripherals_ar_bits_addr), + .peripherals_ar_bits_len(peripherals_ar_bits_len), + .peripherals_ar_bits_size(peripherals_ar_bits_size), + .peripherals_ar_bits_burst(peripherals_ar_bits_burst), + .peripherals_ar_bits_lock(peripherals_ar_bits_lock), + .peripherals_ar_bits_cache(peripherals_ar_bits_cache), + .peripherals_ar_bits_prot(peripherals_ar_bits_prot), + .peripherals_ar_bits_qos(peripherals_ar_bits_qos), + .peripherals_r_ready(peripherals_r_ready), + .peripherals_r_valid(peripherals_r_valid), + .peripherals_r_bits_id(peripherals_r_bits_id), + .peripherals_r_bits_data(peripherals_r_bits_data), + .peripherals_r_bits_resp(peripherals_r_bits_resp), + .peripherals_r_bits_last(peripherals_r_bits_last) + ); + wire [3:0] c_awid; + wire [27:0] c_awaddr; + wire [7:0] c_awlen; + wire [2:0] c_awsize; + wire [1:0] c_awburst; + wire c_awvalid; + wire c_awready; + wire [127:0] c_wdata; + wire [15:0] c_wstrb; + wire c_wlast; + wire c_wvalid; + wire c_wready; + wire [3:0] c_bid; + wire [1:0] c_bresp; + wire c_bvalid; + wire c_bready; + wire [3:0] c_arid; + wire [27:0] c_araddr; + wire [7:0] c_arlen; + wire [2:0] c_arsize; + wire [1:0] c_arburst; + wire c_arvalid; + wire c_arready; + wire [3:0] c_rid; + wire [127:0] c_rdata; + wire [1:0] c_rresp; + wire c_rlast; + wire c_rvalid; + wire c_rready; + wire [3:0] l_awid; + wire [27:0] l_awaddr; + wire [7:0] l_awlen; + wire [2:0] l_awsize; + wire [1:0] l_awburst; + wire l_awvalid; + wire l_awready; + wire [127:0] l_wdata; + wire [15:0] l_wstrb; + wire l_wlast; + wire l_wvalid; + wire l_wready; + wire [3:0] l_bid; + wire [1:0] l_bresp; + wire l_bvalid; + wire l_bready; + wire [3:0] l_arid; + wire [27:0] l_araddr; + wire [7:0] l_arlen; + wire [2:0] l_arsize; + wire [1:0] l_arburst; + wire l_arvalid; + wire l_arready; + wire [3:0] l_rid; + wire [127:0] l_rdata; + wire [1:0] l_rresp; + wire l_rlast; + wire l_rvalid; + wire l_rready; + axi_fullwidth normalizer ( + .clk(clk), + .reset(reset), + .s_awid(memory_aw_bits_id), + .m_awid(c_awid), + .s_awaddr(memory_aw_bits_addr), + .m_awaddr(c_awaddr), + .s_awlen(memory_aw_bits_len), + .m_awlen(c_awlen), + .s_awsize(memory_aw_bits_size), + .m_awsize(c_awsize), + .s_awburst(memory_aw_bits_burst), + .m_awburst(c_awburst), + .s_awvalid(memory_aw_valid), + .m_awvalid(c_awvalid), + .s_awready(memory_aw_ready), + .m_awready(c_awready), + .s_wdata(memory_w_bits_data), + .m_wdata(c_wdata), + .s_wstrb(memory_w_bits_strb), + .m_wstrb(c_wstrb), + .s_wlast(memory_w_bits_last), + .m_wlast(c_wlast), + .s_wvalid(memory_w_valid), + .m_wvalid(c_wvalid), + .s_wready(memory_w_ready), + .m_wready(c_wready), + .s_bid(memory_b_bits_id), + .m_bid(c_bid), + .s_bresp(memory_b_bits_resp), + .m_bresp(c_bresp), + .s_bvalid(memory_b_valid), + .m_bvalid(c_bvalid), + .s_bready(memory_b_ready), + .m_bready(c_bready), + .s_arid(memory_ar_bits_id), + .m_arid(c_arid), + .s_araddr(memory_ar_bits_addr), + .m_araddr(c_araddr), + .s_arlen(memory_ar_bits_len), + .m_arlen(c_arlen), + .s_arsize(memory_ar_bits_size), + .m_arsize(c_arsize), + .s_arburst(memory_ar_bits_burst), + .m_arburst(c_arburst), + .s_arvalid(memory_ar_valid), + .m_arvalid(c_arvalid), + .s_arready(memory_ar_ready), + .m_arready(c_arready), + .s_rid(memory_r_bits_id), + .m_rid(c_rid), + .s_rdata(memory_r_bits_data), + .m_rdata(c_rdata), + .s_rresp(memory_r_bits_resp), + .m_rresp(c_rresp), + .s_rlast(memory_r_bits_last), + .m_rlast(c_rlast), + .s_rvalid(memory_r_valid), + .m_rvalid(c_rvalid), + .s_rready(memory_r_ready), + .m_rready(c_rready) + ); + loader_axi load_bridge ( + .clk(clk), + .reset(reset), + .load_en(load_en), + .load_addr(load_addr), + .load_data(load_data), + .load_mask(load_mask), + .load_valid(load_valid), + .load_error(load_error), + .load_result(load_result), + .awaddr(l_awaddr), + .araddr(l_araddr), + .awvalid(l_awvalid), + .wvalid(l_wvalid), + .arvalid(l_arvalid), + .bready(l_bready), + .rready(l_rready), + .awready(l_awready), + .wready(l_wready), + .arready(l_arready), + .bvalid(l_bvalid), + .rvalid(l_rvalid), + .wdata(l_wdata), + .wstrb(l_wstrb), + .bresp(l_bresp), + .rresp(l_rresp), + .rdata(l_rdata) + ); + assign l_awid=0; + assign l_arid=0; + assign l_awlen=0; + assign l_arlen=0; + assign l_awsize=4; + assign l_arsize=4; + assign l_awburst=1; + assign l_arburst=1; + assign l_wlast=1; + assign ddr_awid=cpu_run ? c_awid : l_awid; + assign ddr_awaddr=cpu_run ? c_awaddr : l_awaddr; + assign ddr_awlen=cpu_run ? c_awlen : l_awlen; + assign ddr_awsize=cpu_run ? c_awsize : l_awsize; + assign ddr_awburst=cpu_run ? c_awburst : l_awburst; + assign ddr_awvalid=cpu_run ? c_awvalid : l_awvalid; + assign c_awready=ddr_awready && cpu_run; + assign l_awready=ddr_awready && !cpu_run; + assign ddr_wdata=cpu_run ? c_wdata : l_wdata; + assign ddr_wstrb=cpu_run ? c_wstrb : l_wstrb; + assign ddr_wlast=cpu_run ? c_wlast : l_wlast; + assign ddr_wvalid=cpu_run ? c_wvalid : l_wvalid; + assign c_wready=ddr_wready && cpu_run; + assign l_wready=ddr_wready && !cpu_run; + assign c_bid=ddr_bid; + assign l_bid=ddr_bid; + assign c_bresp=ddr_bresp; + assign l_bresp=ddr_bresp; + assign c_bvalid=ddr_bvalid && cpu_run; + assign l_bvalid=ddr_bvalid && !cpu_run; + assign ddr_bready=cpu_run ? c_bready : l_bready; + assign ddr_arid=cpu_run ? c_arid : l_arid; + assign ddr_araddr=cpu_run ? c_araddr : l_araddr; + assign ddr_arlen=cpu_run ? c_arlen : l_arlen; + assign ddr_arsize=cpu_run ? c_arsize : l_arsize; + assign ddr_arburst=cpu_run ? c_arburst : l_arburst; + assign ddr_arvalid=cpu_run ? c_arvalid : l_arvalid; + assign c_arready=ddr_arready && cpu_run; + assign l_arready=ddr_arready && !cpu_run; + assign c_rid=ddr_rid; + assign l_rid=ddr_rid; + assign c_rdata=ddr_rdata; + assign l_rdata=ddr_rdata; + assign c_rresp=ddr_rresp; + assign l_rresp=ddr_rresp; + assign c_rlast=ddr_rlast; + assign l_rlast=ddr_rlast; + assign c_rvalid=ddr_rvalid && cpu_run; + assign l_rvalid=ddr_rvalid && !cpu_run; + assign ddr_rready=cpu_run ? c_rready : l_rready; + wire [1:0] scu_bresp; + assign peripherals_b_bits_resp=scu_bresp; + axi_scu #(.FLASH_BOOT(FLASH_BOOT)) peripherals ( + .clk(clk), + .reset(cpu_reset), + .awid(peripherals_aw_bits_id), + .awaddr(peripherals_aw_bits_addr), + .awlen(peripherals_aw_bits_len), + .awsize(peripherals_aw_bits_size), + .awburst(peripherals_aw_bits_burst), + .awvalid(peripherals_aw_valid), + .awready(peripherals_aw_ready), + .wdata(peripherals_w_bits_data), + .wstrb(peripherals_w_bits_strb), + .wlast(peripherals_w_bits_last), + .wvalid(peripherals_w_valid), + .wready(peripherals_w_ready), + .bid(peripherals_b_bits_id), + .bresp(scu_bresp), + .bvalid(peripherals_b_valid), + .bready(peripherals_b_ready), + .arid(peripherals_ar_bits_id), + .araddr(peripherals_ar_bits_addr), + .arlen(peripherals_ar_bits_len), + .arsize(peripherals_ar_bits_size), + .arburst(peripherals_ar_bits_burst), + .arvalid(peripherals_ar_valid), + .arready(peripherals_ar_ready), + .rid(peripherals_r_bits_id), + .rdata(peripherals_r_bits_data), + .rresp(peripherals_r_bits_resp), + .rlast(peripherals_r_bits_last), + .rvalid(peripherals_r_valid), + .rready(peripherals_r_ready), + .rx_valid(rx_valid && cpu_run), + .rx_data(rx_data), + .rx_error(rx_error), + .tx_valid(mmio_tx_valid), + .tx_data(mmio_tx_data), + .tx_ready(tx_ready), + .exited(exited), + .exit_code(exit_code), + .interrupt(irq),.flash_miso(flash_miso),.flash_recovery(flash_recovery), + .flash_mosi(flash_mosi),.flash_sck(flash_sck),.flash_cs_n(flash_cs_n) + ); +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/toy_a7_top.sv b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/toy_a7_top.sv new file mode 100644 index 0000000..397a262 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/toy_a7_top.sv @@ -0,0 +1,305 @@ +module toy_a7_top #(parameter FLASH_BOOT=0) ( + input wire CLK100MHZ, btn0, uart_txd_in, output wire uart_rxd_out, output wire [3:0] led, + inout wire [15:0] ddr3_dq, inout wire [1:0] ddr3_dqs_n, ddr3_dqs_p, + output wire [13:0] ddr3_addr, output wire [2:0] ddr3_ba, + output wire ddr3_ras_n, ddr3_cas_n, ddr3_we_n, ddr3_reset_n, + output wire [0:0] ddr3_ck_p, ddr3_ck_n, ddr3_cke, ddr3_cs_n, ddr3_odt, output wire [1:0] ddr3_dm, + input wire sw0, flash_miso, + output wire flash_mosi, flash_cs_n, flash_wp_n, flash_hold_n +); + wire clk_in,fb,fb_buf,core_raw,sys_raw,ref_raw,clk,sys_clk,ref_clk,locked; + IBUF input_clock (.I(CLK100MHZ),.O(clk_in)); + MMCME2_BASE #(.CLKIN1_PERIOD(10.0),.DIVCLK_DIVIDE(1),.CLKFBOUT_MULT_F(10.0), + .CLKOUT0_DIVIDE_F(40.0),.CLKOUT1_DIVIDE(6),.CLKOUT2_DIVIDE(5)) clock_mmcm ( + .CLKIN1(clk_in),.CLKFBIN(fb_buf),.CLKFBOUT(fb),.CLKOUT0(core_raw), + .CLKOUT1(sys_raw),.CLKOUT2(ref_raw),.LOCKED(locked),.RST(1'b0),.PWRDWN(1'b0)); + BUFG fb_buffer (.I(fb),.O(fb_buf)); BUFG core_buffer (.I(core_raw),.O(clk)); + BUFG sys_buffer (.I(sys_raw),.O(sys_clk)); BUFG ref_buffer (.I(ref_raw),.O(ref_clk)); + wire ui_clk,ui_rst,mig_locked,calibrated; + wire flash_sck; + assign flash_wp_n=1;assign flash_hold_n=1; + generate if(FLASH_BOOT) begin : flash_clock + STARTUPE2 startup (.CLK(1'b0),.GSR(1'b0),.GTS(1'b0),.KEYCLEARB(1'b1),.PACK(1'b0), + .USRCCLKO(flash_sck),.USRCCLKTS(1'b0),.USRDONEO(1'b1),.USRDONETS(1'b1), + .CFGCLK(),.CFGMCLK(),.EOS(),.PREQ()); + end endgenerate + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg sw_meta=0,sw_sync=0; + reg flash_recovery=0; + always @(posedge clk) begin + sw_meta<=sw0;sw_sync<=sw_meta; + if(reset) flash_recovery<=sw_sync; + end + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg [2:0] lock_sync=7; + always @(posedge clk or negedge locked) if(!locked) lock_sync<=7;else lock_sync<={lock_sync[1:0],1'b0}; + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg btn_meta=0,btn_sync=0; + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg btn_ref_meta=0,btn_ref_sync=0; + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg [2:0] mig_resetn_pipe=0; + always @(posedge ref_clk) begin btn_ref_meta<=btn0;btn_ref_sync<=btn_ref_meta;end + always @(posedge ref_clk or negedge locked) if(!locked) mig_resetn_pipe<=0; + else mig_resetn_pipe<={mig_resetn_pipe[1:0],!btn_ref_sync}; + wire mig_resetn=mig_resetn_pipe[2]; + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg [1:0] calib_sync=0; + always @(posedge clk) begin btn_meta<=btn0;btn_sync<=btn_meta;calib_sync<={calib_sync[0],calibrated};end + reg [17:0] reset_count=0;wire reset=lock_sync[2] || btn_sync || !calib_sync[1] || !(&reset_count); + always @(posedge clk) if(lock_sync[2] || btn_sync || !calib_sync[1]) reset_count<=0; + else if(!(&reset_count)) reset_count<=reset_count+1'b1; + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg [2:0] ui_reset_pipe=7; + always @(posedge ui_clk or posedge ui_rst) if(ui_rst) ui_reset_pipe<=7; + else ui_reset_pipe<={ui_reset_pipe[1:0],1'b0}; + wire ui_aresetn=~ui_reset_pipe[2]; + wire cpu_run,exited,loader_error;wire [31:0] exit_code;reg [24:0] heartbeat=0; + always @(posedge clk) if(reset) heartbeat<=0;else heartbeat<=heartbeat+1'b1; + assign led={heartbeat[24],cpu_run && !reset,loader_error || (exited && exit_code!=0),calib_sync[1]}; + wire [3:0] ddr_awid; + wire [27:0] ddr_awaddr; + wire [7:0] ddr_awlen; + wire [2:0] ddr_awsize; + wire [1:0] ddr_awburst; + wire ddr_awvalid; + wire ddr_awready; + wire [127:0] ddr_wdata; + wire [15:0] ddr_wstrb; + wire ddr_wlast; + wire ddr_wvalid; + wire ddr_wready; + wire [3:0] ddr_bid; + wire [1:0] ddr_bresp; + wire ddr_bvalid; + wire ddr_bready; + wire [3:0] ddr_arid; + wire [27:0] ddr_araddr; + wire [7:0] ddr_arlen; + wire [2:0] ddr_arsize; + wire [1:0] ddr_arburst; + wire ddr_arvalid; + wire ddr_arready; + wire [3:0] ddr_rid; + wire [127:0] ddr_rdata; + wire [1:0] ddr_rresp; + wire ddr_rlast; + wire ddr_rvalid; + wire ddr_rready; + wire [3:0] ui_awid; + wire [27:0] ui_awaddr; + wire [7:0] ui_awlen; + wire [2:0] ui_awsize; + wire [1:0] ui_awburst; + wire ui_awvalid; + wire ui_awready; + wire [127:0] ui_wdata; + wire [15:0] ui_wstrb; + wire ui_wlast; + wire ui_wvalid; + wire ui_wready; + wire [3:0] ui_bid; + wire [1:0] ui_bresp; + wire ui_bvalid; + wire ui_bready; + wire [3:0] ui_arid; + wire [27:0] ui_araddr; + wire [7:0] ui_arlen; + wire [2:0] ui_arsize; + wire [1:0] ui_arburst; + wire ui_arvalid; + wire ui_arready; + wire [3:0] ui_rid; + wire [127:0] ui_rdata; + wire [1:0] ui_rresp; + wire ui_rlast; + wire ui_rvalid; + wire ui_rready; + toy_a7_platform #(.FLASH_BOOT(FLASH_BOOT)) platform ( + .clk(clk), + .reset(reset), + .uart_rx_in(uart_txd_in), + .uart_tx_out(uart_rxd_out), + .cpu_run(cpu_run), + .exited(exited), + .loader_error(loader_error), + .exit_code(exit_code), + .flash_miso(flash_miso),.flash_mosi(flash_mosi),.flash_sck(flash_sck), + .flash_cs_n(flash_cs_n),.flash_recovery(flash_recovery), + .ddr_awid(ddr_awid), + .ddr_awaddr(ddr_awaddr), + .ddr_awlen(ddr_awlen), + .ddr_awsize(ddr_awsize), + .ddr_awburst(ddr_awburst), + .ddr_awvalid(ddr_awvalid), + .ddr_awready(ddr_awready), + .ddr_wdata(ddr_wdata), + .ddr_wstrb(ddr_wstrb), + .ddr_wlast(ddr_wlast), + .ddr_wvalid(ddr_wvalid), + .ddr_wready(ddr_wready), + .ddr_bid(ddr_bid), + .ddr_bresp(ddr_bresp), + .ddr_bvalid(ddr_bvalid), + .ddr_bready(ddr_bready), + .ddr_arid(ddr_arid), + .ddr_araddr(ddr_araddr), + .ddr_arlen(ddr_arlen), + .ddr_arsize(ddr_arsize), + .ddr_arburst(ddr_arburst), + .ddr_arvalid(ddr_arvalid), + .ddr_arready(ddr_arready), + .ddr_rid(ddr_rid), + .ddr_rdata(ddr_rdata), + .ddr_rresp(ddr_rresp), + .ddr_rlast(ddr_rlast), + .ddr_rvalid(ddr_rvalid), + .ddr_rready(ddr_rready) + ); + toy_axi_cdc memory_cdc ( + .s_axi_aclk(clk), + .s_axi_aresetn(!reset), + .m_axi_aclk(ui_clk), + .m_axi_aresetn(ui_aresetn), + .s_axi_awid(ddr_awid), + .s_axi_awaddr(ddr_awaddr), + .s_axi_awlen(ddr_awlen), + .s_axi_awsize(ddr_awsize), + .s_axi_awburst(ddr_awburst), + .s_axi_awvalid(ddr_awvalid), + .s_axi_awready(ddr_awready), + .s_axi_wdata(ddr_wdata), + .s_axi_wstrb(ddr_wstrb), + .s_axi_wlast(ddr_wlast), + .s_axi_wvalid(ddr_wvalid), + .s_axi_wready(ddr_wready), + .s_axi_bid(ddr_bid), + .s_axi_bresp(ddr_bresp), + .s_axi_bvalid(ddr_bvalid), + .s_axi_bready(ddr_bready), + .s_axi_arid(ddr_arid), + .s_axi_araddr(ddr_araddr), + .s_axi_arlen(ddr_arlen), + .s_axi_arsize(ddr_arsize), + .s_axi_arburst(ddr_arburst), + .s_axi_arvalid(ddr_arvalid), + .s_axi_arready(ddr_arready), + .s_axi_rid(ddr_rid), + .s_axi_rdata(ddr_rdata), + .s_axi_rresp(ddr_rresp), + .s_axi_rlast(ddr_rlast), + .s_axi_rvalid(ddr_rvalid), + .s_axi_rready(ddr_rready), + .s_axi_awlock(1'b0), + .s_axi_arlock(1'b0), + .s_axi_awcache(4'b0011), + .s_axi_arcache(4'b0011), + .s_axi_awprot(3'd0), + .s_axi_arprot(3'd0), + .s_axi_awqos(4'd0), + .s_axi_arqos(4'd0), + .s_axi_awregion(4'd0), + .s_axi_arregion(4'd0), + .m_axi_awid(ui_awid), + .m_axi_awaddr(ui_awaddr), + .m_axi_awlen(ui_awlen), + .m_axi_awsize(ui_awsize), + .m_axi_awburst(ui_awburst), + .m_axi_awvalid(ui_awvalid), + .m_axi_awready(ui_awready), + .m_axi_wdata(ui_wdata), + .m_axi_wstrb(ui_wstrb), + .m_axi_wlast(ui_wlast), + .m_axi_wvalid(ui_wvalid), + .m_axi_wready(ui_wready), + .m_axi_bid(ui_bid), + .m_axi_bresp(ui_bresp), + .m_axi_bvalid(ui_bvalid), + .m_axi_bready(ui_bready), + .m_axi_arid(ui_arid), + .m_axi_araddr(ui_araddr), + .m_axi_arlen(ui_arlen), + .m_axi_arsize(ui_arsize), + .m_axi_arburst(ui_arburst), + .m_axi_arvalid(ui_arvalid), + .m_axi_arready(ui_arready), + .m_axi_rid(ui_rid), + .m_axi_rdata(ui_rdata), + .m_axi_rresp(ui_rresp), + .m_axi_rlast(ui_rlast), + .m_axi_rvalid(ui_rvalid), + .m_axi_rready(ui_rready), + .m_axi_awlock(), + .m_axi_arlock(), + .m_axi_awcache(), + .m_axi_arcache(), + .m_axi_awprot(), + .m_axi_arprot(), + .m_axi_awqos(), + .m_axi_arqos(), + .m_axi_awregion(), + .m_axi_arregion() + ); + arty_ddr3 ddr_controller ( + .ddr3_dq(ddr3_dq), + .ddr3_dqs_n(ddr3_dqs_n), + .ddr3_dqs_p(ddr3_dqs_p), + .ddr3_addr(ddr3_addr), + .ddr3_ba(ddr3_ba), + .ddr3_ras_n(ddr3_ras_n), + .ddr3_cas_n(ddr3_cas_n), + .ddr3_we_n(ddr3_we_n), + .ddr3_reset_n(ddr3_reset_n), + .ddr3_ck_p(ddr3_ck_p), + .ddr3_ck_n(ddr3_ck_n), + .ddr3_cke(ddr3_cke), + .ddr3_cs_n(ddr3_cs_n), + .ddr3_dm(ddr3_dm), + .ddr3_odt(ddr3_odt), + .sys_clk_i(sys_clk), + .clk_ref_i(ref_clk), + .sys_rst(mig_resetn), + .ui_clk(ui_clk), + .ui_clk_sync_rst(ui_rst), + .mmcm_locked(mig_locked), + .aresetn(ui_aresetn), + .init_calib_complete(calibrated), + .device_temp(), + .app_sr_req(1'b0), + .app_ref_req(1'b0), + .app_zq_req(1'b0), + .app_sr_active(), + .app_ref_ack(), + .app_zq_ack(), + .s_axi_awid(ui_awid), + .s_axi_awaddr(ui_awaddr), + .s_axi_awlen(ui_awlen), + .s_axi_awsize(ui_awsize), + .s_axi_awburst(ui_awburst), + .s_axi_awvalid(ui_awvalid), + .s_axi_awready(ui_awready), + .s_axi_wdata(ui_wdata), + .s_axi_wstrb(ui_wstrb), + .s_axi_wlast(ui_wlast), + .s_axi_wvalid(ui_wvalid), + .s_axi_wready(ui_wready), + .s_axi_bid(ui_bid), + .s_axi_bresp(ui_bresp), + .s_axi_bvalid(ui_bvalid), + .s_axi_bready(ui_bready), + .s_axi_arid(ui_arid), + .s_axi_araddr(ui_araddr), + .s_axi_arlen(ui_arlen), + .s_axi_arsize(ui_arsize), + .s_axi_arburst(ui_arburst), + .s_axi_arvalid(ui_arvalid), + .s_axi_arready(ui_arready), + .s_axi_rid(ui_rid), + .s_axi_rdata(ui_rdata), + .s_axi_rresp(ui_rresp), + .s_axi_rlast(ui_rlast), + .s_axi_rvalid(ui_rvalid), + .s_axi_rready(ui_rready), + .s_axi_awlock(1'b0), + .s_axi_arlock(1'b0), + .s_axi_awcache(4'b0011), + .s_axi_arcache(4'b0011), + .s_axi_awprot(3'd0), + .s_axi_arprot(3'd0), + .s_axi_awqos(4'd0), + .s_axi_arqos(4'd0) + ); +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/uart_rx.sv b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/uart_rx.sv new file mode 100644 index 0000000..567b8b4 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/uart_rx.sv @@ -0,0 +1,40 @@ +// 8-N-1 receiver. Data is sampled in the middle of each bit after a verified +// start bit. A held-low/broken line reports one framing error, then waits high. +module uart_rx #( + parameter integer DIVISOR = 434 +) ( + input wire clk, reset, rx, + output reg valid, + output reg [7:0] data, + output reg frame_error +); + (* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) reg rx_meta = 1, rx_sync = 1; + always @(posedge clk) begin rx_meta <= rx; rx_sync <= rx_meta; end + localparam integer WIDTH = $clog2(DIVISOR) < 1 ? 1 : $clog2(DIVISOR); + localparam [2:0] IDLE=0, START=1, DATA=2, STOP=3, WAIT_HIGH=4; + reg [2:0] state, bit_index; + reg [WIDTH-1:0] count; + reg [7:0] shift; + always @(posedge clk) begin + valid <= 0; frame_error <= 0; + if (reset) begin + state <= IDLE; bit_index <= 0; count <= 0; shift <= 0; data <= 0; + end else case (state) + IDLE: if (!rx_sync) begin state <= START; count <= DIVISOR/2 - 1; end + START: if (count != 0) count <= count - 1'b1; + else if (rx_sync) state <= IDLE; + else begin state <= DATA; bit_index <= 0; count <= DIVISOR - 1; end + DATA: if (count != 0) count <= count - 1'b1; + else begin + shift[bit_index] <= rx_sync; count <= DIVISOR - 1; + if (bit_index == 7) state <= STOP; + else bit_index <= bit_index + 1'b1; + end + STOP: if (count != 0) count <= count - 1'b1; + else if (rx_sync) begin data <= shift; valid <= 1; state <= IDLE; end + else begin frame_error <= 1; state <= WAIT_HIGH; end + WAIT_HIGH: if (rx_sync) state <= IDLE; + default: state <= IDLE; + endcase + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/uart_tx.sv b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/uart_tx.sv new file mode 100644 index 0000000..11f6e4a --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/uart_tx.sv @@ -0,0 +1,37 @@ +module uart_tx #( + parameter integer DIVISOR = 434 // 50 MHz / 115200, error < 0.01%. +) ( + input wire clk, + input wire reset, + input wire valid, + input wire [7:0] data, + output wire ready, + output wire tx +); + localparam integer COUNT_BITS = $clog2(DIVISOR) < 1 ? 1 : $clog2(DIVISOR); + reg [COUNT_BITS-1:0] count; + reg [9:0] shift; + reg [3:0] bits_left; + assign ready = bits_left == 0; + assign tx = shift[0]; + + always @(posedge clk) begin + if (reset) begin + count <= 0; + shift <= 10'h3ff; + bits_left <= 0; + end else if (ready) begin + if (valid) begin + shift <= {1'b1, data, 1'b0}; + bits_left <= 10; + count <= DIVISOR - 1; + end + end else if (count == 0) begin + shift <= {1'b1, shift[9:1]}; + bits_left <= bits_left - 1'b1; + count <= DIVISOR - 1; + end else begin + count <= count - 1'b1; + end + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/vendor/License.txt b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/vendor/License.txt new file mode 100644 index 0000000..b76cf0c --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/vendor/License.txt @@ -0,0 +1,21 @@ +MIT License + +Copyright (c) 2021 Digilent, Inc. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. \ No newline at end of file diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/vendor/MANIFEST.json b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/vendor/MANIFEST.json new file mode 100644 index 0000000..ae5699f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/vendor/MANIFEST.json @@ -0,0 +1,24 @@ +{ + "repository": "Digilent/vivado-boards", + "commit": "36f34ab687b7fa9c778b779d027f3bce63b3ace9", + "vendor_revision": "E.0", + "physical_board_revision": "unknown", + "files": { + "board.xml": { + "url": "https://raw.githubusercontent.com/Digilent/vivado-boards/36f34ab687b7fa9c778b779d027f3bce63b3ace9/new/board_files/arty-a7-100/E.0/1.0/board.xml", + "sha256": "5bd9a7ca97ccb2fef617515a14401166464b45a06684d663c0be1a06b02a86df" + }, + "part0_pins.xml": { + "url": "https://raw.githubusercontent.com/Digilent/vivado-boards/36f34ab687b7fa9c778b779d027f3bce63b3ace9/new/board_files/arty-a7-100/E.0/1.0/part0_pins.xml", + "sha256": "50aa844aa9c78af6342de68ae3c980f7618716447b28282878d5a106f86fed31" + }, + "mig.prj": { + "url": "https://raw.githubusercontent.com/Digilent/vivado-boards/36f34ab687b7fa9c778b779d027f3bce63b3ace9/new/board_files/arty-a7-100/E.0/1.0/mig.prj", + "sha256": "914a9e4bb1b3002837592944cdf49f8dfbaf4d112552dd8b5be48602ff1ac329" + }, + "preset.xml": { + "url": "https://raw.githubusercontent.com/Digilent/vivado-boards/36f34ab687b7fa9c778b779d027f3bce63b3ace9/new/board_files/arty-a7-100/E.0/1.0/preset.xml", + "sha256": "ff95b9b976323fefa588873588dfa2bdce1673759c0a9e91c12ee9f2a2955bce" + } + } +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/vendor/board.xml b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/vendor/board.xml new file mode 100644 index 0000000..50f4535 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/vendor/board.xml @@ -0,0 +1,1247 @@ + + + + + E.0 + +1.0 +Arty A7-100 + + + + + DDR3 board interface, it can use MIG IP for connection. + + + + + + 4-position user DIP Switches + + + + + + + + + + + + + + + + Secondary interface to communicate with ethernet phy. + + + + + + + + + + + + + + + + + + + + + + + + + Primary interface to communicate with ethernet phy in MII mode. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Shield I2C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + I2C Pullups to enable shield I2C + + + + + + + + + + + + + + 4 LEDs + + + + + + + + + + + + + + + + 4 Push Buttons + + + + + + + + + + + + + + + + Quad SPI Flash + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Onboard Reset Button + + + + + + + + + + + + + + + + 4 RGB LEDs + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 256 MB DDR3L memory SODIMM + + + + + + + DIP Switches 3 to 0 + + + PHY Ethernet on the board + + + + + + + + + + + Shield i2c + + + Shield i2c pullups, must pull high if using the shield I2C on J3 + + + LEDs 3 to 0 + + + Push buttons 3 to 0 + + + 16 MB of nonvolatile storage that can be used for configuration or data storage + + + CPU Reset Push Button, active low + + + RGB leds 12 to 0 (3 per LED) + + + Shield pins 0 through 19 + + + Shield pins 26 through 41 + + + Shield SPI + + + 3.3V Single-Ended 100MHz oscillator used as system clock on the board + + + USB-to-UART Bridge, which allows a connection to a host computer with a USB port + + + Pmod Connector JA + + + Pmod Connector JB + + + Pmod Connector JC + + + Pmod Connector JD + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/vendor/mig.prj b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/vendor/mig.prj new file mode 100644 index 0000000..1bff709 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/vendor/mig.prj @@ -0,0 +1,134 @@ + + + + design_1_mig_7series_0_0 + 1 + 1 + OFF + 1024 + ON + Enabled + xc7a100t-csg324/-1 + 2.3 + No Buffer + No Buffer + ACTIVE LOW + FALSE + 1 + 50 Ohms + 0 + + DDR3_SDRAM/Components/MT41K128M16XX-15E + 3000 + 1.8V + 4:1 + 166.666 + 0 + 666 + 1.000 + 1 + 1 + 1 + 1 + 16 + 1 + 1 + Disabled + Normal + FALSE + + 14 + 10 + 3 + 1.35V + 268435456 + BANK_ROW_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 5 + Normal + No + Slow Exit + Enable + RZQ/6 + Disable + Enable + RZQ/6 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 5 + Enabled + Normal + Dynamic ODT off + AXI + + RD_PRI_REG + 28 + 128 + 4 + 0 + + + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/vendor/part0_pins.xml b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/vendor/part0_pins.xml new file mode 100644 index 0000000..dc32e54 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/vendor/part0_pins.xml @@ -0,0 +1,156 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/vendor/preset.xml b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/vendor/preset.xml new file mode 100644 index 0000000..ec20fb4 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/board/vendor/preset.xml @@ -0,0 +1,418 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/build.sbt b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/build.sbt new file mode 100644 index 0000000..79eb11f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/build.sbt @@ -0,0 +1,70 @@ +ThisBuild / scalaVersion := "2.13.16" +ThisBuild / organization := "srtp.fpga" +ThisBuild / version := "0.1.0" +ThisBuild / scalacOptions ++= Seq("-language:reflectiveCalls", "-Ymacro-annotations", "-deprecation", "-feature") + +lazy val chiselSettings = Seq( + scalaVersion := "2.13.16", + libraryDependencies += "org.chipsalliance" %% "chisel" % "6.7.0", + addCompilerPlugin("org.chipsalliance" % "chisel-plugin" % "6.7.0" cross CrossVersion.full) +) +lazy val cde = project.in(file("thirdparty/cde")).settings(chiselSettings).settings( + Compile / unmanagedSourceDirectories += baseDirectory.value / "cde/src/chipsalliance" +) +lazy val diplomacy = project.in(file("thirdparty/diplomacy/diplomacy")).dependsOn(cde).settings(chiselSettings).settings( + Compile / unmanagedSourceDirectories += baseDirectory.value / "src/diplomacy", + libraryDependencies += "com.lihaoyi" %% "sourcecode" % "0.3.0" +) +lazy val hardfloat = project.in(file("thirdparty/hardfloat/hardfloat")).dependsOn(cde).settings(chiselSettings) +lazy val macros = project.in(file("thirdparty/rocket-chip/macros")).settings( + libraryDependencies += "org.scala-lang" % "scala-reflect" % "2.13.16" +) +lazy val rocket = project.in(file("thirdparty/rocket-chip")).dependsOn(cde, diplomacy, hardfloat, macros).settings(chiselSettings).settings( + Compile / unmanagedSources := { + val original = ((baseDirectory.value / "src/main/scala") ** "*.scala").get + original.filterNot(f => f.getName == "FPU.scala") ++ + ((baseDirectory.value / "../../patches/rocket") ** "*.scala").get + }, + libraryDependencies ++= Seq( + "com.lihaoyi" %% "mainargs" % "0.5.0", + "org.json4s" %% "json4s-jackson" % "4.0.5", + "org.scala-graph" %% "graph-core" % "1.13.5" + ) +) +lazy val inclusive = project.in(file("thirdparty/inclusive-cache")).dependsOn(rocket).settings(chiselSettings).settings( + Compile / unmanagedSourceDirectories += baseDirectory.value / "design/craft" +) +lazy val midas = project.in(file("thirdparty/firesim-compile")).settings(chiselSettings).settings( + Compile / unmanagedSourceDirectories += baseDirectory.value / "../firesim/sim/midas/targetutils/src/main/scala" +) +lazy val gemmini = project.in(file("thirdparty/gemmini-compile")).dependsOn(rocket, midas).settings(chiselSettings).settings( + Compile / unmanagedSources := { + val original = ((baseDirectory.value / "../gemmini/src/main/scala") ** "*.scala").get + original.filterNot(f => Set("PE.scala", "Tile.scala", "Mesh.scala")(f.getName)) ++ + ((baseDirectory.value / "../../patches/gemmini") ** "*.scala").get + }, + Compile / unmanagedResourceDirectories += baseDirectory.value / "../gemmini/src/main/resources" +) +lazy val root = project.in(file(".")).dependsOn(inclusive, gemmini).settings(chiselSettings).settings( + name := "toy-arty-a7-linux", + libraryDependencies ++= Seq( + "com.lihaoyi" %% "upickle" % "3.3.1", + "tech.sparse" %% "toml-scala" % "0.2.2" + ), + Compile / unmanagedSources ++= { + val upstream = baseDirectory.value / "upstream" + val framework = upstream / "arch/src/main/scala/framework" + val directories = Seq("balldomain", "builtin", "dpi", "frontend", "gpdomain", "memdomain", "top", + "system/core/rocket", "system/core/accelerator", "system/tile") + val shared = directories.flatMap(d => ((framework / d) ** "*.scala").get) + .filterNot(f => Set("WithBuckyballTiles.scala", "WithBoomTile.scala", "MemMidend.scala", "MemStorer.scala", "PrivateMemBackend.scala", "SubROB.scala", "GlobalROB.scala", "MemFrontend.scala", "MemLoader.scala")(f.getName)) + shared ++ ((baseDirectory.value / "patches/framework") ** "*.scala").get ++ + ((baseDirectory.value / "patches/buckyball") ** "*.scala").get ++ ((upstream / "arch/src/main/scala/sims/hash") ** "*.scala").get ++ Seq("gemmini", "trace", "mxfp2int", "relu").flatMap { name => + val ball = upstream / "examples/balls" / name + ((ball / "arch/src/main/scala") ** "*.scala").get.filterNot(f => + Set("GemminiExCtrl.scala", "GemminiExCtrlDefs.scala", + "GemminiExCtrlComputeFeedState.scala", "GemminiExCtrlStoreOps.scala", + "GemminiExCtrlPreloadStates.scala", "GemminiExCtrlCmdStates.scala", "GemminiBall.scala", "LoopMatmulUnroller.scala")(f.getName)) ++ ((ball / "configs") ** "*.scala").get + } + } +) diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/dependencies.json b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/dependencies.json new file mode 100644 index 0000000..285ef6d --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/dependencies.json @@ -0,0 +1,31 @@ +{ + "rocket-chip": { + "repository": "SEU-ACAL/rocket-chip", + "commit": "35488f108c1ee9e42175b5240ae957d8970e9c5b" + }, + "inclusive-cache": { + "repository": "SEU-ACAL/rocket-chip-inclusive-cache", + "commit": "88317ea415459d274026bd59850517a9fcc87ede" + }, + "cde": { + "repository": "chipsalliance/cde", + "commit": "2bcaeae2b9914bd25497ce3c6fa62dc5ca80e09f" + }, + "diplomacy": { + "repository": "chipsalliance/diplomacy", + "commit": "fe5e131d4fc8adec14a3ce4a4935bb5c0a269871" + }, + "hardfloat": { + "repository": "SEU-ACAL/berkeley-hardfloat", + "commit": "536cf3727f655713f424438190100bb08cbf2e5a" + }, + "gemmini": { + "repository": "ucb-bar/gemmini", + "commit": "8c3f9923a44a2fe2c7930587be297d6d4f8c09ca" + }, + "firesim": { + "repository": "firesim/firesim", + "commit": "da2a1cbcebbb96e21c551ebef513fd95a9d73403", + "subtree": "sim/midas/targetutils" + } +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/buckyball/GemminiBall.scala b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/buckyball/GemminiBall.scala new file mode 100644 index 0000000..4ef8542 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/buckyball/GemminiBall.scala @@ -0,0 +1,298 @@ +package examples.balls.gemmini + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import framework.balldomain.blink.{BallStatus, BlinkIO, HasBallStatus, HasBlink, SubRobRow} +import framework.balldomain.blink.mmio.MmioRead +import framework.balldomain.rs.BallRsComplete +import framework.top.GlobalConfig + +@instantiable +class GemminiBall(val b: GlobalConfig) extends Module with HasBlink with HasBallStatus { + require(b.memDomain.bankEntries <= 1024, "GemminiBall rs2 row-base fields support at most 1024 bank entries") + require( + b.frontend.sub_rob_enable, + "GemminiBall requires frontend.sub_rob_enable=true because loop instructions emit SubROB rows" + ) + + val ballCommonConfig = b.ballDomain.ballIdMappings + .find(_.ballName == "GemminiBall") + .getOrElse( + throw new IllegalArgumentException("GemminiBall not found in config") + ) + + val inBW = ballCommonConfig.inBW + val outBW = ballCommonConfig.outBW + + @public + val io = IO(new BlinkIO(b, inBW, outBW)) + + def blink: BlinkIO = io + def status: BallStatus = io.status + dontTouch(io) + + // ========================================================================= + // Sub-modules + // ========================================================================= + val exCtrl: Instance[GemminiExCtrl] = Instantiate(new GemminiExCtrl(b)) + + val matmulUnroller: Instance[LoopMatmulUnroller] = Instantiate( + new LoopMatmulUnroller(b) + ) + + val convUnroller: Instance[LoopConvUnroller] = Instantiate( + new LoopConvUnroller(b) + ) + + val encoder: Instance[LoopCmdEncoder] = Instantiate(new LoopCmdEncoder(b)) + + // ========================================================================= + // Config registers for Loop modes + // ========================================================================= + val loopWsConfig = Reg(new LoopWsConfig(b)) + val loopConvConfig = Reg(new LoopConvWsConfig(b)) + + // rob_id tracking for bank metadata + val rob_id_reg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) + when(io.cmdReq.fire) { + rob_id_reg := io.cmdReq.bits.rob_id + } + + // ========================================================================= + // Instruction routing by funct7 + // ========================================================================= + val funct7 = io.cmdReq.bits.cmd.funct7 + + def ballFunct(mnemonic: String): UInt = + b.ballDomain.ballISA + .find(_.mnemonic == mnemonic) + .map(_.funct7.U(7.W)) + .getOrElse(throw new IllegalArgumentException(s"$mnemonic not found in ballISA")) + + val configFunct = ballFunct("GEMMINI_CONFIG") + val preloadFunct = ballFunct("GEMMINI_PRELOAD") + val computePreFunct = ballFunct("GEMMINI_COMPUTE_PRELOADED") + val computeAccFunct = ballFunct("GEMMINI_COMPUTE_ACCUMULATED") + val flushFunct = ballFunct("GEMMINI_FLUSH") + + val loopWsConfigFuncts = Seq( + ballFunct("GEMMINI_LOOP_WS_CONFIG_BOUNDS"), + ballFunct("GEMMINI_LOOP_WS_CONFIG_ADDR_A"), + ballFunct("GEMMINI_LOOP_WS_CONFIG_ADDR_B"), + ballFunct("GEMMINI_LOOP_WS_CONFIG_ADDR_D"), + ballFunct("GEMMINI_LOOP_WS_CONFIG_ADDR_C"), + ballFunct("GEMMINI_LOOP_WS_CONFIG_STRIDES_AB"), + ballFunct("GEMMINI_LOOP_WS_CONFIG_STRIDES_DC") + ) + + val loopWsTriggerFunct = ballFunct("GEMMINI_LOOP_WS") + + val loopConvConfigFuncts = Seq( + ballFunct("GEMMINI_LOOP_CONV_WS_CONFIG_1"), + ballFunct("GEMMINI_LOOP_CONV_WS_CONFIG_2"), + ballFunct("GEMMINI_LOOP_CONV_WS_CONFIG_3"), + ballFunct("GEMMINI_LOOP_CONV_WS_CONFIG_4"), + ballFunct("GEMMINI_LOOP_CONV_WS_CONFIG_5"), + ballFunct("GEMMINI_LOOP_CONV_WS_CONFIG_6"), + ballFunct("GEMMINI_LOOP_CONV_WS_CONFIG_7"), + ballFunct("GEMMINI_LOOP_CONV_WS_CONFIG_8"), + ballFunct("GEMMINI_LOOP_CONV_WS_CONFIG_9") + ) + + val loopConvTriggerFunct = ballFunct("GEMMINI_LOOP_CONV_WS") + + val rs2Data = io.cmdReq.bits.cmd.special + + val isConfig = funct7 === configFunct + val isPreload = funct7 === preloadFunct + val isComputePre = funct7 === computePreFunct + val isComputeAcc = funct7 === computeAccFunct + val isFlush = funct7 === flushFunct + // Keep loop expansion consistent with the CONFIG accepted by the execute unit. + val loopDataflow = RegInit(false.B) + when(io.cmdReq.fire && isConfig) { loopDataflow := rs2Data(4) } + matmulUnroller.io.dataflow := loopDataflow + val isExUnit = + isConfig || isPreload || isComputePre || isComputeAcc || isFlush + + val isLoopWsConfig = loopWsConfigFuncts.map(funct7 === _).reduce(_ || _) + val isLoopWsTrigger = funct7 === loopWsTriggerFunct + val isLoopConvConfig = loopConvConfigFuncts.map(funct7 === _).reduce(_ || _) + val isLoopConvTrigger = funct7 === loopConvTriggerFunct + + // ========================================================================= + // ExUnit path (non-Loop: CONFIG/PRELOAD/COMPUTE/FLUSH) + // ========================================================================= + exCtrl.exio.cmdReq.valid := io.cmdReq.valid && isExUnit + exCtrl.exio.cmdReq.bits := io.cmdReq.bits + + // ========================================================================= + // Config latch path (immediate cmdResp) + // ========================================================================= + val configRespValid = RegInit(false.B) + val configRespBits = Reg(new BallRsComplete(b)) + configRespValid := false.B // default: pulse + + when(io.cmdReq.fire && isLoopWsConfig) { + configRespValid := true.B + configRespBits.rob_id := io.cmdReq.bits.rob_id + configRespBits.is_sub := io.cmdReq.bits.is_sub + configRespBits.sub_rob_id := io.cmdReq.bits.sub_rob_id + switch(funct7) { + is(loopWsConfigFuncts(0)) { + loopWsConfig.max_k := rs2Data(15, 0) + loopWsConfig.max_j := rs2Data(31, 16) + loopWsConfig.max_i := rs2Data(47, 32) + } + is(loopWsConfigFuncts(1))(loopWsConfig.dram_addr_a := rs2Data(38, 0)) + is(loopWsConfigFuncts(2))(loopWsConfig.dram_addr_b := rs2Data(38, 0)) + is(loopWsConfigFuncts(3))(loopWsConfig.dram_addr_d := rs2Data(38, 0)) + is(loopWsConfigFuncts(4))(loopWsConfig.dram_addr_c := rs2Data(38, 0)) + is(loopWsConfigFuncts(5)) { + loopWsConfig.stride_a := rs2Data(31, 0) + loopWsConfig.stride_b := rs2Data(63, 32) + } + is(loopWsConfigFuncts(6)) { + loopWsConfig.stride_d := rs2Data(31, 0) + loopWsConfig.stride_c := rs2Data(63, 32) + } + } + } + + when(io.cmdReq.fire && isLoopConvConfig) { + configRespValid := true.B + configRespBits.rob_id := io.cmdReq.bits.rob_id + configRespBits.is_sub := io.cmdReq.bits.is_sub + configRespBits.sub_rob_id := io.cmdReq.bits.sub_rob_id + switch(funct7) { + is(loopConvConfigFuncts(0)) { + loopConvConfig.batch_size := rs2Data(15, 0) + loopConvConfig.in_dim := rs2Data(31, 16) + loopConvConfig.in_channels := rs2Data(47, 32) + } + is(loopConvConfigFuncts(1)) { + loopConvConfig.out_channels := rs2Data(15, 0) + loopConvConfig.out_dim := rs2Data(31, 16) + loopConvConfig.stride := rs2Data(39, 32) + loopConvConfig.padding := rs2Data(47, 40) + } + is(loopConvConfigFuncts(2)) { + loopConvConfig.kernel_dim := rs2Data(7, 0) + loopConvConfig.pool_size := rs2Data(15, 8) + loopConvConfig.pool_stride := rs2Data(23, 16) + loopConvConfig.pool_padding := rs2Data(31, 24) + } + is(loopConvConfigFuncts(3))(loopConvConfig.dram_addr_bias := rs2Data(38, 0)) + is(loopConvConfigFuncts(4))(loopConvConfig.dram_addr_input := rs2Data(38, 0)) + is(loopConvConfigFuncts(5))(loopConvConfig.dram_addr_weight := rs2Data(38, 0)) + is(loopConvConfigFuncts(6))(loopConvConfig.dram_addr_output := rs2Data(38, 0)) + is(loopConvConfigFuncts(7)) { + loopConvConfig.input_stride := rs2Data(31, 0) + loopConvConfig.weight_stride := rs2Data(63, 32) + } + is(loopConvConfigFuncts(8))(loopConvConfig.output_stride := rs2Data(31, 0)) + } + } + + // ========================================================================= + // Loop trigger: latch bank IDs and start unroller (no cmdResp) + // Bank values come from rs2Data in the trigger instruction, but loopWsConfig + // Reg won't update until next edge. Override start.bits combinationally. + // ========================================================================= + matmulUnroller.io.start.valid := false.B + matmulUnroller.io.start.bits := loopWsConfig + + when(io.cmdReq.fire && isLoopWsTrigger) { + loopWsConfig.bank_a := rs2Data(9, 0) + loopWsConfig.bank_b := rs2Data(19, 10) + loopWsConfig.bank_c := rs2Data(29, 20) + loopWsConfig.low_d := rs2Data(30) + matmulUnroller.io.start.valid := true.B + matmulUnroller.io.start.bits.bank_a := rs2Data(9, 0) + matmulUnroller.io.start.bits.bank_b := rs2Data(19, 10) + matmulUnroller.io.start.bits.bank_c := rs2Data(29, 20) + matmulUnroller.io.start.bits.low_d := rs2Data(30) + } + + convUnroller.io.start.valid := false.B + convUnroller.io.start.bits := loopConvConfig + + when(io.cmdReq.fire && isLoopConvTrigger) { + loopConvConfig.bank_input := rs2Data(9, 0) + loopConvConfig.bank_weight := rs2Data(19, 10) + loopConvConfig.bank_output := rs2Data(29, 20) + loopConvConfig.no_bias := rs2Data(30) + convUnroller.io.start.valid := true.B + convUnroller.io.start.bits.bank_input := rs2Data(9, 0) + convUnroller.io.start.bits.bank_weight := rs2Data(19, 10) + convUnroller.io.start.bits.bank_output := rs2Data(29, 20) + convUnroller.io.start.bits.no_bias := rs2Data(30) + } + + // ========================================================================= + // LoopUnrollers → Arbiter → LoopCmdEncoder → io.subRobReq + // ========================================================================= + val cmdArb = Module(new Arbiter(new LoopCmd(b), 2)) + cmdArb.io.in(0) <> matmulUnroller.io.cmd + cmdArb.io.in(1) <> convUnroller.io.cmd + encoder.io.cmd <> cmdArb.io.out + encoder.io.subRobRow <> io.subRobReq + encoder.io.ballId := ballCommonConfig.ballId.U + encoder.io.masterRobId := rob_id_reg + + // ========================================================================= + // cmdReq.ready: route to correct consumer + // ========================================================================= + val idleReady = + exCtrl.exio.cmdReq.ready && !matmulUnroller.io.busy && !convUnroller.io.busy + io.cmdReq.ready := Mux( + isExUnit, + exCtrl.exio.cmdReq.ready, + Mux( + isLoopWsConfig || isLoopConvConfig, + idleReady, + Mux( + isLoopWsTrigger, + !matmulUnroller.io.busy, + Mux(isLoopConvTrigger, !convUnroller.io.busy, idleReady) + ) + ) + ) + + // ========================================================================= + // cmdResp: mux between exUnit and config immediate response + // ========================================================================= + io.cmdResp <> exCtrl.exio.cmdResp + when(configRespValid) { + io.cmdResp.valid := true.B + io.cmdResp.bits := configRespBits + } + + // ========================================================================= + // Bank connections (unchanged from original) + // ========================================================================= + for (i <- 0 until inBW) { + io.bankRead(i).io.req <> exCtrl.exio.bankReadReq(i) + exCtrl.exio.bankReadResp(i) <> io.bankRead(i).io.resp + io.bankRead(i).rob_id := rob_id_reg + io.bankRead(i).ball_id := 0.U + io.bankRead(i).group_id := 0.U + } + io.bankRead(0).bank_id := exCtrl.exio.op1_bank_o + if (inBW > 1) { + io.bankRead(1).bank_id := exCtrl.exio.op2_bank_o + } + + for (i <- 0 until outBW) { + io.bankWrite(i).io <> exCtrl.exio.bankWrite(i) + io.bankWrite(i).bank_id := exCtrl.exio.wr_bank_o + io.bankWrite(i).rob_id := rob_id_reg + io.bankWrite(i).ball_id := 0.U + io.bankWrite(i).group_id := i.U + } + + io.status <> exCtrl.exio.status + + MmioRead.tieOff(io.mmioRead) +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/buckyball/GemminiExCtrl.scala b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/buckyball/GemminiExCtrl.scala new file mode 100644 index 0000000..e6d2fed --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/buckyball/GemminiExCtrl.scala @@ -0,0 +1,34 @@ +package examples.balls.gemmini + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public} +import framework.top.GlobalConfig + +@instantiable +class GemminiExCtrl(val b: GlobalConfig) + extends Module + with GemminiExCtrlDefs + with GemminiExCtrlDefaults + with GemminiExCtrlCmdStates + with GemminiExCtrlPreloadStates + with GemminiExCtrlComputeReadState + with GemminiExCtrlComputeFeedState + with GemminiExCtrlStoreOps + with GemminiExCtrlFsm { + @public val exio = io + + applyDefaults() + runFsm() + + // WS output is associated with the preceding non-flush mesh request. + // Unlike a ROB ID, the internal token changes for each loop iteration. + when(mesh.io.req.fire && mesh.io.req.bits.flush === 0.U) { + wsResultTag := lastMeshTag + lastMeshTag := mesh.io.req.bits.tag.rob + nextMeshTag := Mux(nextMeshTag === 254.U, 0.U, nextMeshTag + 1.U) + } + + io.status.idle := state === sIdle + io.status.running := state =/= sIdle +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/buckyball/GemminiExCtrlCmdStates.scala b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/buckyball/GemminiExCtrlCmdStates.scala new file mode 100644 index 0000000..9c7c62d --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/buckyball/GemminiExCtrlCmdStates.scala @@ -0,0 +1,92 @@ +package examples.balls.gemmini + +import chisel3._ +import chisel3.util._ +import gemmini._ + +trait GemminiExCtrlCmdStates { this: GemminiExCtrl => + + protected def handleIdleState(): Unit = { + io.cmdReq.ready := true.B + when(io.cmdReq.fire) { + rob_id_reg := io.cmdReq.bits.rob_id + is_sub_reg := io.cmdReq.bits.is_sub + sub_rob_id_reg := io.cmdReq.bits.sub_rob_id + op1_bank := io.cmdReq.bits.cmd.op1_bank + op2_bank := io.cmdReq.bits.cmd.op2_bank + wr_bank := io.cmdReq.bits.cmd.wr_bank + op1_base := io.cmdReq.bits.cmd.special(15, 6) + op2_base := io.cmdReq.bits.cmd.special(25, 16) + wr_base := io.cmdReq.bits.cmd.special(35, 26) + total_rows := Mux( + io.cmdReq.bits.cmd.iter === 0.U, + DIM.U, + io.cmdReq.bits.cmd.iter + ) + zero_op2 := io.cmdReq.bits.cmd.special(4) + zero_op1_tail := io.cmdReq.bits.cmd.special(5) + + when(sub_cmd === GemminiSubCmd.CONFIG) { + cfg_dataflow := io.cmdReq.bits.cmd.special(4) + cfg_a_transpose := io.cmdReq.bits.cmd.special(7) + cfg_bd_transpose := io.cmdReq.bits.cmd.special(8) + cfg_in_shift := io.cmdReq.bits.cmd.special( + log2Up(config.accWidth) + 8, + 9 + ) + io.cmdResp.valid := true.B + state := sCommit + }.elsewhen(sub_cmd === GemminiSubCmd.PRELOAD) { + read_row_cnt := 0.U + feed_row_cnt := 0.U + req_sent := false.B + xpose_ready := false.B + xpose_row_cnt := 0.U + state := sPreloadRead + }.elsewhen( + sub_cmd === GemminiSubCmd.COMPUTE_PRELOADED || sub_cmd === GemminiSubCmd.COMPUTE_ACCUMULATED + ) { + read_row_cnt := 0.U + feed_row_cnt := 0.U + outBufRows := 0.U + outBufCollected := 0.U + req_sent := false.B + xpose_ready := false.B + xpose_row_cnt := 0.U + read_done.foreach(_ := false.B) + state := sComputeRead + }.elsewhen(sub_cmd === GemminiSubCmd.FLUSH) { + state := sFlush + } + } + } + + protected def handleCommitState(): Unit = { + io.cmdResp.valid := true.B + when(io.cmdResp.fire) { + state := sIdle + } + } + + protected def handleFlushState(): Unit = { + mesh.io.req.valid := true.B + mesh.io.req.bits.flush := 2.U + mesh.io.req.bits.total_rows := DIM.U + mesh.io.req.bits.tag.rob := nextMeshTag + + mesh.io.a.valid := true.B + mesh.io.a.bits := 0.U.asTypeOf(mesh.A_TYPE) + mesh.io.b.valid := true.B + mesh.io.b.bits := 0.U.asTypeOf(mesh.B_TYPE) + mesh.io.d.valid := true.B + mesh.io.d.bits := 0.U.asTypeOf(mesh.D_TYPE) + + when(mesh.io.req.ready) { + io.cmdResp.valid := true.B + when(io.cmdResp.fire) { + state := sIdle + } + } + } + +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/buckyball/GemminiExCtrlComputeFeedState.scala b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/buckyball/GemminiExCtrlComputeFeedState.scala new file mode 100644 index 0000000..cf7b241 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/buckyball/GemminiExCtrlComputeFeedState.scala @@ -0,0 +1,121 @@ +package examples.balls.gemmini + +import chisel3._ +import chisel3.util._ +import gemmini._ + +trait GemminiExCtrlComputeFeedState { this: GemminiExCtrl => + + protected def handleComputeFeedState(): Unit = { + when(cfg_dataflow === Dataflow.WS.id.U && req_sent) { captureWsOutput() } + // OS: do not collect mesh rows here — preload matmul responses still drain during feed; + // sComputeFlush drops tag=0xff (garbage) resps and collects non-garbage rows only. + + when(!req_sent) { + mesh.io.req.valid := true.B + mesh.io.req.bits.pe_control.dataflow := cfg_dataflow + mesh.io.req.bits.pe_control.propagate := 1.U + mesh.io.req.bits.pe_control.shift := cfg_in_shift + mesh.io.req.bits.a_transpose := Mux( + cfg_dataflow === Dataflow.OS.id.U, + true.B, + cfg_a_transpose + ) + mesh.io.req.bits.bd_transpose := Mux( + cfg_dataflow === Dataflow.OS.id.U, + false.B, + cfg_bd_transpose + ) + mesh.io.req.bits.total_rows := total_rows + mesh.io.req.bits.tag.rob := nextMeshTag + mesh.io.req.bits.flush := 0.U + when(mesh.io.req.fire) { + req_sent := true.B + } + } + + val op1FromBuf = cfg_dataflow === Dataflow.OS.id.U && !cfg_a_transpose + val op2FromBuf = cfg_dataflow === Dataflow.OS.id.U && cfg_bd_transpose + val needXpose = op1FromBuf || (op2FromBuf && !zero_op2) + + when(req_sent && needXpose && !xpose_ready) { + val op1Ready = !op1FromBuf || rdQueue0.io.deq.valid + val op2Ready = !op2FromBuf || zero_op2 || rdQueue1.io.deq.valid + when(xpose_row_cnt < total_rows && op1Ready && op2Ready) { + when(op1FromBuf) { + op1Buf(xpose_row_cnt) := rdQueue0.io.deq.bits.data + .asTypeOf(Vec(DIM, inputType)) + rdQueue0.io.deq.ready := true.B + } + when(op2FromBuf && !zero_op2) { + op2Buf(xpose_row_cnt) := rdQueue1.io.deq.bits.data + .asTypeOf(Vec(DIM, inputType)) + rdQueue1.io.deq.ready := true.B + } + xpose_row_cnt := xpose_row_cnt + 1.U + }.elsewhen(xpose_row_cnt >= total_rows) { + xpose_ready := true.B + } + } + + when(req_sent && (!needXpose || xpose_ready) && feed_row_cnt < total_rows) { + val op1Zero = zero_op1_tail && feed_row_cnt =/= 0.U + when( + (op1Zero || op1FromBuf || rdQueue0.io.deq.valid) && (zero_op2 || op2FromBuf || rdQueue1.io.deq.valid) + ) { + val a_mem_row = rdQueue0.io.deq.bits.data.asTypeOf(Vec(DIM, inputType)) + val x_mem_row = rdQueue1.io.deq.bits.data.asTypeOf(Vec(DIM, inputType)) + val a_col_row = VecInit((0 until DIM).map(i => op1Buf(i)(feed_row_cnt))) + val x_col_row = VecInit((0 until DIM).map(i => op2Buf(i)(feed_row_cnt))) + val a_row = Mux(op1FromBuf, a_col_row, a_mem_row) + val x_row = Mux(op2FromBuf, x_col_row, x_mem_row) + mesh.io.a.valid := true.B + mesh.io.a.bits := Mux( + op1Zero, + 0.U.asTypeOf(mesh.A_TYPE), + VecInit(a_row.grouped(config.tileRows).map(g => VecInit(g)).toSeq) + ) + when(cfg_dataflow === Dataflow.OS.id.U) { + // OS: stream A/B, D=0 + mesh.io.b.valid := true.B + mesh.io.b.bits := VecInit( + x_row.grouped(config.tileColumns).map(g => VecInit(g)).toSeq + ) + mesh.io.d.valid := true.B + mesh.io.d.bits := 0.U.asTypeOf(mesh.D_TYPE) + }.otherwise { + // WS: stream A/D, B comes from preloaded weights + mesh.io.b.valid := true.B + // WS accumulates the incoming bias/partial sum from B. + // D loads the inactive weight register and must not carry bias. + mesh.io.b.bits := Mux( + zero_op2, + 0.U.asTypeOf(mesh.B_TYPE), + VecInit( + x_row.grouped(config.tileColumns).map(g => VecInit(g)).toSeq + ) + ) + mesh.io.d.valid := true.B + mesh.io.d.bits := 0.U.asTypeOf(mesh.D_TYPE) + } + when(mesh.io.a.ready && mesh.io.b.ready && mesh.io.d.ready) { + rdQueue0.io.deq.ready := !op1Zero && !op1FromBuf + rdQueue1.io.deq.ready := !zero_op2 && !op2FromBuf + feed_row_cnt := feed_row_cnt + 1.U + } + } + } + + when(req_sent && feed_row_cnt >= total_rows) { + when(cfg_dataflow === Dataflow.OS.id.U) { + outBufRows := total_rows - 1.U + req_sent := false.B + feed_row_cnt := 0.U + state := sComputeFlush + }.otherwise { + state := sDrain + } + } + } + +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/buckyball/GemminiExCtrlDefs.scala b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/buckyball/GemminiExCtrlDefs.scala new file mode 100644 index 0000000..3c9e65e --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/buckyball/GemminiExCtrlDefs.scala @@ -0,0 +1,132 @@ +package examples.balls.gemmini + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.public +import framework.balldomain.blink.BallStatus +import framework.balldomain.rs.{BallRsComplete, BallRsIssue} +import framework.memdomain.backend.banks.{SramReadReq, SramReadResp, SramWriteIO} +import framework.top.GlobalConfig +import examples.balls.gemmini.configs.GemminiBallParam +import gemmini._ +import gemmini.Util._ + +trait GemminiExCtrlDefs { this: GemminiExCtrl => + val config = GemminiBallParam(b) + val DIM = config.blockSize + + val ballMapping = b.ballDomain.ballIdMappings + .find(_.ballName == "GemminiBall") + .getOrElse( + throw new IllegalArgumentException("GemminiBall not found in config") + ) + + val inBW = ballMapping.inBW + val outBW = ballMapping.outBW + + val inputType = SInt(config.inputWidth.W) + val accType = SInt(config.accWidth.W) + val meshOutputType = SInt(config.spatialOutputWidth.W) + + val ctrlIo = IO(new Bundle { + val cmdReq = Flipped(Decoupled(new BallRsIssue(b))) + val cmdResp = Decoupled(new BallRsComplete(b)) + val bankReadReq = Vec(inBW, Decoupled(new SramReadReq(b))) + val bankReadResp = Vec(inBW, Flipped(Decoupled(new SramReadResp(b)))) + val bankWrite = Vec(outBW, Flipped(new SramWriteIO(b))) + val op1_bank_o = Output(UInt(b.memDomain.vbankIdWidth.W)) + val op2_bank_o = Output(UInt(b.memDomain.vbankIdWidth.W)) + val wr_bank_o = Output(UInt(b.memDomain.vbankIdWidth.W)) + val status = new BallStatus + }) + + val io = ctrlIo + + // Mesh tags are internal request tokens. They must distinguish different + // operations even when loop subcommands share an architectural ROB ID. + // Reserve 255 for Gemmini garbage tags; at most six requests are live. + val nextMeshTag = RegInit(0.U(8.W)) + val lastMeshTag = RegInit(255.U(8.W)) + val wsResultTag = RegInit(255.U(8.W)) + + val mesh = Module( + new MeshWithDelays( + inputType = inputType, + weightType = inputType, + outputType = meshOutputType, + accType = accType, + tagType = new SimpleTag, + df = Dataflow.BOTH, + tree_reduction = false, + tile_latency = config.tileLatency, + output_delay = config.outputDelay, + tileRows = config.tileRows, + tileColumns = config.tileColumns, + meshRows = config.meshRows, + meshColumns = config.meshColumns, + leftBanks = 1, + upBanks = 1 + ) + ) + + protected def widenMeshToAcc(src: Vec[Vec[SInt]]): Vec[Vec[SInt]] = + VecInit(src.map(col => VecInit(col.map(_.asTypeOf(accType))))) + + val cfg_dataflow = RegInit(0.U(1.W)) + val cfg_in_shift = RegInit(0.U(log2Up(config.accWidth).W)) + val cfg_a_transpose = RegInit(false.B) + val cfg_bd_transpose = RegInit(false.B) + val zero_op2 = RegInit(false.B) + val zero_op1_tail = RegInit(false.B) + + val sIdle :: sPreloadRead :: sPreloadFeed :: sComputeRead :: sComputeFeed :: sComputeFlush :: sFlush :: sDrain :: sStore :: sCommit :: Nil = + Enum(10) + val state = RegInit(sIdle) + + val rob_id_reg = RegInit(0.U(log2Up(b.frontend.rob_entries).W)) + val is_sub_reg = RegInit(false.B) + val sub_rob_id_reg = RegInit(0.U(log2Up(b.frontend.sub_rob_depth * 4).W)) + + /** Match SimpleTag.rob (8b); must match mesh req tag bits */ + protected def robIdAsTag8(x: UInt): UInt = { + val w = x.getWidth + if (w >= 8) x(7, 0) else Cat(0.U((8 - w).W), x) + } + + val op1_bank = RegInit(0.U(b.memDomain.vbankIdWidth.W)) + val op2_bank = RegInit(0.U(b.memDomain.vbankIdWidth.W)) + val wr_bank = RegInit(0.U(b.memDomain.vbankIdWidth.W)) + val op1_base = RegInit(0.U(10.W)) + val op2_base = RegInit(0.U(10.W)) + val wr_base = RegInit(0.U(10.W)) + io.op1_bank_o := op1_bank + io.op2_bank_o := op2_bank + io.wr_bank_o := wr_bank + + val read_row_cnt = RegInit(0.U(log2Up(DIM + 1).W)) + val feed_row_cnt = RegInit(0.U(log2Up(DIM + 1).W)) + val store_row_cnt = RegInit(0.U(log2Up(DIM + 1).W)) + val total_rows = RegInit(DIM.U(log2Up(DIM + 1).W)) + val req_sent = RegInit(false.B) + val read_done = RegInit(VecInit(Seq.fill(inBW)(false.B))) + val xpose_ready = RegInit(false.B) + val xpose_row_cnt = RegInit(0.U(log2Up(DIM + 1).W)) + + val sub_cmd = io.cmdReq.bits.cmd.special(3, 0) + + val rdQueue0 = Module(new Queue(new SramReadResp(b), entries = DIM)) + val rdQueue1 = Module(new Queue(new SramReadResp(b), entries = DIM)) + rdQueue0.io.enq <> io.bankReadResp(0) + rdQueue1.io.enq <> io.bankReadResp(1) + + val outBuf = Reg( + Vec(DIM, Vec(config.meshColumns, Vec(config.tileColumns, accType))) + ) + + val outBufRows = RegInit(0.U(log2Up(DIM + 1).W)) + val outBufCollected = RegInit(0.U(log2Up(DIM + 1).W)) + val op1Buf = Reg(Vec(DIM, Vec(DIM, inputType))) + val op2Buf = Reg(Vec(DIM, Vec(DIM, inputType))) + + val port_written = RegInit(VecInit(Seq.fill(outBW)(false.B))) +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/buckyball/GemminiExCtrlPreloadStates.scala b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/buckyball/GemminiExCtrlPreloadStates.scala new file mode 100644 index 0000000..a3221b2 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/buckyball/GemminiExCtrlPreloadStates.scala @@ -0,0 +1,114 @@ +package examples.balls.gemmini + +import chisel3._ +import chisel3.util._ +import gemmini._ + +trait GemminiExCtrlPreloadStates { this: GemminiExCtrl => + + protected def handlePreloadReadState(): Unit = { + when(cfg_dataflow === Dataflow.OS.id.U) { + when(read_row_cnt < total_rows) { + io.bankReadReq(0).valid := true.B + io.bankReadReq(0).bits.addr := op1_base + read_row_cnt + when(io.bankReadReq(0).ready) { + read_row_cnt := read_row_cnt + 1.U + } + }.otherwise { + state := sPreloadFeed + } + }.otherwise { + when(read_row_cnt < total_rows) { + io.bankReadReq(0).valid := true.B + // The mesh expects ordinary WS weights bottom-up. For b_transpose we + // first capture the source matrix in natural row order and explicitly + // feed its columns bottom-up in sPreloadFeed. + io.bankReadReq(0).bits.addr := Mux( + cfg_bd_transpose, + op1_base + read_row_cnt, + op1_base + total_rows - 1.U - read_row_cnt + ) + when(io.bankReadReq(0).ready) { + read_row_cnt := read_row_cnt + 1.U + } + }.otherwise { + state := sPreloadFeed + } + } + } + + protected def handlePreloadFeedState(): Unit = { + val explicitBTranspose = + cfg_dataflow === Dataflow.WS.id.U && cfg_bd_transpose + + when(!req_sent) { + mesh.io.req.valid := true.B + mesh.io.req.bits.pe_control.dataflow := cfg_dataflow + mesh.io.req.bits.pe_control.propagate := 1.U + mesh.io.req.bits.pe_control.shift := cfg_in_shift + mesh.io.req.bits.a_transpose := Mux( + cfg_dataflow === Dataflow.OS.id.U, + true.B, + cfg_a_transpose + ) + // B transpose is materialized in op2Buf below. Keeping the mesh-side + // transposer disabled avoids the unsupported WS transpose request path. + mesh.io.req.bits.bd_transpose := false.B + mesh.io.req.bits.total_rows := total_rows + mesh.io.req.bits.tag.rob := nextMeshTag + mesh.io.req.bits.flush := 0.U + when(mesh.io.req.fire) { + req_sent := true.B + } + } + + when(req_sent && explicitBTranspose && !xpose_ready) { + when(xpose_row_cnt < total_rows && rdQueue0.io.deq.valid) { + op2Buf(xpose_row_cnt) := rdQueue0.io.deq.bits.data + .asTypeOf(Vec(DIM, inputType)) + rdQueue0.io.deq.ready := true.B + xpose_row_cnt := xpose_row_cnt + 1.U + }.elsewhen(xpose_row_cnt >= total_rows) { + xpose_ready := true.B + } + } + + when( + req_sent && (!explicitBTranspose || xpose_ready) && feed_row_cnt < total_rows + ) { + when(explicitBTranspose || rdQueue0.io.deq.valid) { + val row_data = rdQueue0.io.deq.bits.data.asTypeOf(Vec(DIM, inputType)) + val transpose_col = total_rows - 1.U - feed_row_cnt + val transposed_data = + VecInit((0 until DIM).map(i => op2Buf(i)(transpose_col))) + val weight_data = Mux(explicitBTranspose, transposed_data, row_data) + mesh.io.a.valid := true.B + mesh.io.a.bits := 0.U.asTypeOf(mesh.A_TYPE) + mesh.io.b.valid := true.B + mesh.io.b.bits := 0.U.asTypeOf(mesh.B_TYPE) + mesh.io.d.valid := true.B + // OS preload in Buckyball is used to prime pipeline state before compute. + // Feed D=0 to avoid injecting bias-like data into the following matmul. + mesh.io.d.bits := Mux( + cfg_dataflow === Dataflow.OS.id.U, + 0.U.asTypeOf(mesh.D_TYPE), + VecInit( + weight_data.grouped(config.tileColumns).map(g => VecInit(g)).toSeq + ) + ) + when(mesh.io.a.ready && mesh.io.b.ready && mesh.io.d.ready) { + rdQueue0.io.deq.ready := !explicitBTranspose + feed_row_cnt := feed_row_cnt + 1.U + } + } + } + + when(req_sent && feed_row_cnt >= total_rows) { + io.cmdResp.valid := true.B + when(io.cmdResp.fire) { + state := sIdle + } + } + } + +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/buckyball/GemminiExCtrlStoreOps.scala b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/buckyball/GemminiExCtrlStoreOps.scala new file mode 100644 index 0000000..62f9bee --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/buckyball/GemminiExCtrlStoreOps.scala @@ -0,0 +1,139 @@ +package examples.balls.gemmini + +import chisel3._ +import chisel3.util._ +import gemmini._ + +trait GemminiExCtrlStoreOps { this: GemminiExCtrl => + + // WS responses carry the preceding internal mesh request token. + // Collect non-garbage rows during feeding as well as draining: a shorter + // mesh can return its first results before all input rows have been sent. + protected def captureWsOutput(): Unit = { + when(mesh.io.resp.valid && mesh.io.resp.bits.tag.rob === wsResultTag && + wsResultTag =/= 0xff.U && + outBufRows < total_rows) { + outBuf(outBufRows) := widenMeshToAcc(mesh.io.resp.bits.data) + outBufRows := outBufRows + 1.U + } + } + + + protected def handleComputeFlushState(): Unit = { + when(mesh.io.resp.fire && mesh.io.resp.bits.total_rows === total_rows) { + when( + outBufCollected < total_rows && mesh.io.resp.bits.tag.rob =/= 0xff.U + ) { + outBuf(total_rows - 1.U - outBufCollected) := widenMeshToAcc( + mesh.io.resp.bits.data + ) + outBufCollected := outBufCollected + 1.U + }.otherwise {} + } + + when(outBufCollected >= total_rows) { + store_row_cnt := 0.U + port_written.foreach(_ := false.B) + state := sStore + }.otherwise { + // Flush once to drain remaining rows after feeding is complete. + when(!req_sent) { + mesh.io.req.valid := true.B + mesh.io.req.bits.pe_control.dataflow := cfg_dataflow + mesh.io.req.bits.pe_control.propagate := 1.U + mesh.io.req.bits.pe_control.shift := cfg_in_shift + mesh.io.req.bits.a_transpose := Mux( + cfg_dataflow === Dataflow.OS.id.U, + true.B, + cfg_a_transpose + ) + mesh.io.req.bits.bd_transpose := Mux( + cfg_dataflow === Dataflow.OS.id.U, + false.B, + cfg_bd_transpose + ) + mesh.io.req.bits.total_rows := total_rows + mesh.io.req.bits.tag.rob := nextMeshTag + mesh.io.req.bits.flush := 1.U + when(mesh.io.req.fire) { + req_sent := true.B + } + } + } + } + + protected def handleDrainState(): Unit = { + when(mesh.io.resp.valid) { + when(cfg_dataflow === Dataflow.OS.id.U) { + when(mesh.io.resp.bits.total_rows === total_rows) { + outBuf(outBufRows) := widenMeshToAcc(mesh.io.resp.bits.data) + outBufRows := outBufRows - 1.U + outBufCollected := outBufCollected + 1.U + } + } + } + when(cfg_dataflow === Dataflow.WS.id.U) { + captureWsOutput() + } + + when(cfg_dataflow === Dataflow.OS.id.U) { + when(outBufCollected >= total_rows) { + store_row_cnt := 0.U + port_written.foreach(_ := false.B) + state := sStore + } + }.otherwise { + when(outBufRows >= total_rows) { + store_row_cnt := 0.U + port_written.foreach(_ := false.B) + state := sStore + } + } + } + + protected def handleStoreState(): Unit = { + when(store_row_cnt < total_rows) { + // One row = DIM elements; split across outBW ports (group_id 0..outBW-1). + // mvout reads (addr, group 0), (addr, group 1), ... and concatenates as row. + // So port i (group_id=i) must get elements [i*elemsPerPort .. (i+1)*elemsPerPort). + val rowIdx = store_row_cnt + val row = outBuf(rowIdx) + val flat_raw = VecInit(row.flatten) + val flat_scaled = VecInit( + // Match Gemmini's signed nearest-even shift after collecting the final WS result. + // OS already rounds in the PE; its writeback path remains unscaled. + row.flatten.map(value => FpgaRoundShift(value.asSInt, cfg_in_shift).asTypeOf(accType)) + ) + val row_bits = Cat( + Mux(cfg_dataflow === Dataflow.WS.id.U, flat_scaled, flat_raw) + .map(_.asUInt) + .reverse + ) + + val bitsPerPort = b.memDomain.bankWidth + + for (i <- 0 until outBW) { + when(!port_written(i)) { + val slice = row_bits((i + 1) * bitsPerPort - 1, i * bitsPerPort) + io.bankWrite(i).req.valid := true.B + io.bankWrite(i).req.bits.addr := wr_base + store_row_cnt + io.bankWrite(i).req.bits.data := slice + io.bankWrite(i).req.bits.mask := VecInit( + Seq.fill(b.memDomain.bankMaskLen)(true.B) + ) + when(io.bankWrite(i).req.ready) { + port_written(i) := true.B + } + } + } + + when(port_written.asUInt.andR) { + store_row_cnt := store_row_cnt + 1.U + port_written.foreach(_ := false.B) + } + }.otherwise { + state := sCommit + } + } + +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/buckyball/LoopMatmulUnroller.scala b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/buckyball/LoopMatmulUnroller.scala new file mode 100644 index 0000000..ae3fbe4 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/buckyball/LoopMatmulUnroller.scala @@ -0,0 +1,327 @@ +package examples.balls.gemmini + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public} +import framework.top.GlobalConfig +import examples.balls.gemmini.configs.GemminiBallParam + +/** + * LoopMatmulUnroller — expands LOOP_WS into a stream of LoopCmd rows. + * + * FSM: sIdle → sAllocBanks → sPrimeLoad → sMainLoop (Row1/Row2) → sDrainLast → sFreeBanks → sDone + * + * Row layout per iteration: + * Row 1: [PRELOAD(cur), COMPUTE(cur)] + * Row 2: [MVOUT(cur), MVIN_A(next), MVIN_B(next)] + * Last iteration: only Row 1, then sDrainLast handles final MVOUT. + */ +@instantiable +class LoopMatmulUnroller(val b: GlobalConfig) extends Module { + val config = GemminiBallParam(b) + val DIM = config.blockSize + val elemSize = config.inputWidth / 8 + val accBytes = config.accWidth / 8 + val bankBytes = b.memDomain.bankWidth / 8 + val bankIdLen = b.memDomain.vbankIdWidth + + @public + val io = IO(new Bundle { + val start = Flipped(Decoupled(new LoopWsConfig(b))) + val cmd = Decoupled(new LoopCmd(b)) + val busy = Output(Bool()) + val dataflow = Input(Bool()) + }) + + // FSM states + val sIdle :: sAllocBanks :: sPrimeLoad :: sMainRow1 :: sMainRow2 :: sDrainLast :: sFreeBanks :: sDone :: Nil = + Enum(8) + val state = RegInit(sIdle) + + // Config registers (latched at start) + val cfg = Reg(new LoopWsConfig(b)) + val weightStationary = RegInit(false.B) + + // Loop iterator registers + val i_reg = RegInit(0.U(16.W)) + val j_reg = RegInit(0.U(16.W)) + val k_reg = RegInit(0.U(16.W)) + + // Total iterations and current iteration index + val totalIter = cfg.max_i * cfg.max_j * cfg.max_k + val curIter = RegInit(0.U(32.W)) + + // Whether this is the last iteration + val isLastIter = curIter === (totalIter - 1.U) + + // Defaults + io.start.ready := state === sIdle + io.cmd.valid := false.B + io.cmd.bits := 0.U.asTypeOf(new LoopCmd(b)) + io.busy := state =/= sIdle + + // Helper to build an invalid LoopSubCmd slot + def emptySlot(): Valid[LoopSubCmd] = { + val v = Wire(Valid(new LoopSubCmd(b))) + v.valid := false.B + v.bits := 0.U.asTypeOf(new LoopSubCmd(b)) + v + } + + // Helper to build an MSET slot + def msetSlot( + bankId: UInt, + alloc: Boolean, + row: Int, + col: Int + ): Valid[LoopSubCmd] = { + val v = Wire(Valid(new LoopSubCmd(b))) + v.valid := true.B + v.bits := 0.U.asTypeOf(new LoopSubCmd(b)) + v.bits.cmdType := (if (alloc) LoopSubCmdType.MSET_ALLOC + else LoopSubCmdType.MSET_FREE) + v.bits.bank_id := bankId + v.bits.bank_row := row.U + v.bits.bank_col := col.U + v + } + + // Helper to build an MVIN slot + def mvinSlot( + bankId: UInt, + addr: UInt, + iter: UInt, + stride: UInt + ): Valid[LoopSubCmd] = { + val v = Wire(Valid(new LoopSubCmd(b))) + v.valid := true.B + v.bits := 0.U.asTypeOf(new LoopSubCmd(b)) + v.bits.cmdType := LoopSubCmdType.MVIN + v.bits.bank_id := bankId + v.bits.dram_addr := addr + v.bits.stride := stride + v.bits.iter := iter + v + } + + // Helper to build an MVOUT slot + def mvoutSlot( + bankId: UInt, + addr: UInt, + iter: UInt, + stride: UInt + ): Valid[LoopSubCmd] = { + val v = Wire(Valid(new LoopSubCmd(b))) + v.valid := true.B + v.bits := 0.U.asTypeOf(new LoopSubCmd(b)) + v.bits.cmdType := LoopSubCmdType.MVOUT + v.bits.bank_id := bankId + v.bits.dram_addr := addr + v.bits.stride := stride + v.bits.iter := iter + v + } + + // Address computation + // addr_a(i,k) = dram_addr_a + i * stride_a + k * DIM * elemSize + // addr_b(k,j) = dram_addr_b + k * stride_b + j * DIM * elemSize + // addr_c(i,j) = dram_addr_c + i * stride_c + j * DIM * accBytes + def addrA(i: UInt, k: UInt): UInt = + cfg.dram_addr_a + i * cfg.stride_a + k * (DIM * elemSize).U + + def addrB(k: UInt, j: UInt): UInt = + cfg.dram_addr_b + k * cfg.stride_b + j * (DIM * elemSize).U + + def addrC(i: UInt, j: UInt): UInt = + cfg.dram_addr_c + i * cfg.stride_c + j * (DIM * accBytes).U + + def inMemStride(bytes: UInt): UInt = + (bytes / bankBytes.U)(18, 0) + + def outMemStride(bytes: UInt): UInt = + (bytes / (bankBytes * 4).U)(18, 0) + + // Next iterator values (advance k, then j, then i) + val next_k = Wire(UInt(16.W)) + val next_j = Wire(UInt(16.W)) + val next_i = Wire(UInt(16.W)) + + when(k_reg + 1.U < cfg.max_k) { + next_k := k_reg + 1.U + next_j := j_reg + next_i := i_reg + }.elsewhen(j_reg + 1.U < cfg.max_j) { + next_k := 0.U + next_j := j_reg + 1.U + next_i := i_reg + }.otherwise { + next_k := 0.U + next_j := 0.U + next_i := i_reg + 1.U + } + + // Compute mode: first k iteration uses PRELOADED (0), rest use ACCUMULATED (1) + val computeMode = Mux(k_reg === 0.U, 0.U(2.W), 1.U(2.W)) + + switch(state) { + is(sIdle) { + io.start.ready := true.B + when(io.start.fire) { + cfg := io.start.bits + weightStationary := io.dataflow + i_reg := 0.U + j_reg := 0.U + k_reg := 0.U + curIter := 0.U + state := sAllocBanks + } + } + + // Row 0: [MSET_alloc(A), MSET_alloc(B), MSET_alloc(C), --] + is(sAllocBanks) { + io.cmd.valid := true.B + io.cmd.bits + .slots(0) := msetSlot(cfg.bank_a, alloc = true, row = 1, col = 1) + io.cmd.bits + .slots(1) := msetSlot(cfg.bank_b, alloc = true, row = 1, col = 1) + io.cmd.bits.slots(2) := msetSlot( + cfg.bank_c, + alloc = true, + row = 1, + col = 4 + ) // accWidth = 4x inputWidth + io.cmd.bits.slots(3) := emptySlot() + when(io.cmd.fire) { + state := sPrimeLoad + } + } + + // Row 1: [MVIN_A(0), MVIN_B(0), --, --] + is(sPrimeLoad) { + io.cmd.valid := true.B + io.cmd.bits.slots(0) := mvinSlot( + cfg.bank_a, + addrA(0.U, 0.U), + DIM.U, + inMemStride(cfg.stride_a) + ) + io.cmd.bits.slots(1) := mvinSlot( + cfg.bank_b, + addrB(0.U, 0.U), + DIM.U, + inMemStride(cfg.stride_b) + ) + io.cmd.bits.slots(2) := emptySlot() + io.cmd.bits.slots(3) := emptySlot() + when(io.cmd.fire) { + state := sMainRow1 + } + } + + // Main loop Row 1: [PRELOAD(cur), COMPUTE(cur), --, --] + is(sMainRow1) { + io.cmd.valid := true.B + val preSlot = Wire(Valid(new LoopSubCmd(b))) + preSlot.valid := true.B + preSlot.bits := 0.U.asTypeOf(new LoopSubCmd(b)) + preSlot.bits.cmdType := LoopSubCmdType.PRELOAD + preSlot.bits.op1_bank := Mux(weightStationary, cfg.bank_b, cfg.bank_a) + preSlot.bits.wr_bank := cfg.bank_c + preSlot.bits.iter := DIM.U + + val compSlot = Wire(Valid(new LoopSubCmd(b))) + compSlot.valid := true.B + compSlot.bits := 0.U.asTypeOf(new LoopSubCmd(b)) + compSlot.bits.cmdType := LoopSubCmdType.COMPUTE + compSlot.bits.op1_bank := cfg.bank_a + compSlot.bits.op2_bank := cfg.bank_b + compSlot.bits.wr_bank := cfg.bank_c + compSlot.bits.compute_mode := computeMode + // WS weights are already preloaded; B is not a bias matrix. + compSlot.bits.zero_op2 := weightStationary + compSlot.bits.iter := DIM.U + + io.cmd.bits.slots(0) := preSlot + io.cmd.bits.slots(1) := compSlot + io.cmd.bits.slots(2) := emptySlot() + io.cmd.bits.slots(3) := emptySlot() + + when(io.cmd.fire) { + when(isLastIter) { + state := sDrainLast // Skip Row 2 for last iteration + }.otherwise { + state := sMainRow2 + } + } + } + + // Main loop Row 2: [MVOUT(cur), MVIN_A(next), MVIN_B(next), --] + is(sMainRow2) { + io.cmd.valid := true.B + io.cmd.bits.slots(0) := mvoutSlot( + cfg.bank_c, + addrC(i_reg, j_reg), + DIM.U, + outMemStride(cfg.stride_c) + ) + io.cmd.bits.slots(1) := mvinSlot( + cfg.bank_a, + addrA(next_i, next_k), + DIM.U, + inMemStride(cfg.stride_a) + ) + io.cmd.bits.slots(2) := mvinSlot( + cfg.bank_b, + addrB(next_k, next_j), + DIM.U, + inMemStride(cfg.stride_b) + ) + io.cmd.bits.slots(3) := emptySlot() + + when(io.cmd.fire) { + // Advance iterators + i_reg := next_i + j_reg := next_j + k_reg := next_k + curIter := curIter + 1.U + state := sMainRow1 + } + } + + // Drain: emit final MVOUT for last iteration + is(sDrainLast) { + io.cmd.valid := true.B + io.cmd.bits.slots(0) := mvoutSlot( + cfg.bank_c, + addrC(i_reg, j_reg), + DIM.U, + outMemStride(cfg.stride_c) + ) + io.cmd.bits.slots(1) := emptySlot() + io.cmd.bits.slots(2) := emptySlot() + io.cmd.bits.slots(3) := emptySlot() + when(io.cmd.fire) { + state := sFreeBanks + } + } + + // Free: [MSET_free(A), MSET_free(B), MSET_free(C), --] + is(sFreeBanks) { + io.cmd.valid := true.B + io.cmd.bits + .slots(0) := msetSlot(cfg.bank_a, alloc = false, row = 0, col = 0) + io.cmd.bits + .slots(1) := msetSlot(cfg.bank_b, alloc = false, row = 0, col = 0) + io.cmd.bits + .slots(2) := msetSlot(cfg.bank_c, alloc = false, row = 0, col = 0) + io.cmd.bits.slots(3) := emptySlot() + when(io.cmd.fire) { + state := sDone + } + } + + is(sDone) { + state := sIdle + } + } +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/framework/GlobalROB.scala b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/framework/GlobalROB.scala new file mode 100644 index 0000000..2cd7e8d --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/framework/GlobalROB.scala @@ -0,0 +1,603 @@ +package framework.frontend.globalrs + +import chisel3._ +import chisel3.util._ +import chisel3.experimental._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import framework.top.GlobalConfig +import framework.frontend.decoder.{DomainId, PostGDCmd} +import framework.frontend.scoreboard.{BankAccessInfo, BankAliasTable, BankScoreboard} +import framework.memdomain.frontend.cmd.decoder.DISA.MSET_BITPAT +import framework.memdomain.backend.shared.SharedMemLayout +import framework.memdomain.backend.banks.btrace.{BTraceDPI, PhysicalBankHash} + +@instantiable +class GlobalROB(val b: GlobalConfig, useOperandRam: Boolean = GlobalROB.operandRamEnabled) extends Module { + + val robDepth = b.frontend.rob_entries + val idWidth = log2Up(robDepth) + val scoreBankNum = b.memDomain.virtualBankCount + robDepth + val sharedHashCount = if (b.memDomain.sharedEnable) SharedMemLayout.totalBank(b) else 0 + val physicalBankCount = b.memDomain.bankNum + sharedHashCount + + require( + b.frontend.vbank_id_upper_bound < b.memDomain.virtualBankCount, + s"vbank_id_upper_bound(${b.frontend.vbank_id_upper_bound}) must be < virtualBankCount(${b.memDomain.virtualBankCount})" + ) + + @public + val io = IO(new Bundle { + val hart_id = Input(UInt(b.tile.xLen.W)) + val alloc = Flipped(new DecoupledIO(new PostGDCmd(b))) + val issue = new DecoupledIO(new GlobalRobEntry(b)) + val complete = Flipped(new DecoupledIO(UInt(idWidth.W))) + + val empty = Output(Bool()) + val full = Output(Bool()) + val head_ptr = Output(UInt(idWidth.W)) + val issued_count = Output(UInt(log2Up(robDepth + 1).W)) + val entry_valid = Output(Vec(robDepth, Bool())) + val entry_complete = Output(Vec(robDepth, Bool())) + + val subRobActive = Input(Bool()) + val inst_ids = Output(Vec(robDepth, UInt(64.W))) + + val bank_hashes = + if (b.sim.diffTest) { + Some(Input(Vec(physicalBankCount, new PhysicalBankHash(b)))) + } else { + None + } + + }) + + // --------------------------------------------------------------------------- + // BAT + Bank Scoreboard + // --------------------------------------------------------------------------- + val bat: Instance[BankAliasTable] = Instantiate( + new BankAliasTable( + bankIdLen = b.frontend.bank_id_len, + vbankUpper = b.memDomain.virtualBankCount - 1, + robEntries = robDepth + ) + ) + + val scoreboard: Instance[BankScoreboard] = + Instantiate(new BankScoreboard(b.frontend.bank_id_len, scoreBankNum, robDepth)) + + // --------------------------------------------------------------------------- + // Instruction trace (DPI-C, defined in ITraceDPI.scala) + // --------------------------------------------------------------------------- + val itraceAlloc = Module(new ITraceDPI) + val itraceIssue = Module(new ITraceDPI) + val itraceComp = Module(new ITraceDPI) + + for (t <- Seq(itraceAlloc, itraceIssue, itraceComp)) { + t.io.clock := clock + t.io.reset := reset.asBool + t.io.is_issue := 0.U + t.io.hart_id := io.hart_id + t.io.rob_id := 0.U + t.io.inst_id := 0.U + t.io.domain_id := 0.U + t.io.funct := 0.U + t.io.pc := 0.U + t.io.rs1_data := 0.U + t.io.rs2_data := 0.U + t.io.enable := false.B + } + + // --------------------------------------------------------------------------- + // Storage + // --------------------------------------------------------------------------- + val robEntries = RegInit(VecInit(Seq.fill(robDepth)(0.U.asTypeOf(new GlobalRobEntry(b))))) + // Only the issued payload needs the full operands. Keep existing copies for + // trace/commit observation; Vivado removes trace-only bits with DPI disabled. + // MSET's low rs2 bits stay in registers for the parallel commit scan. + private val operandWidth = b.tile.xLen + private val operandRam = if (useOperandRam) { + Some(SyncReadMem(robDepth, UInt((2 * operandWidth).W)).suggestName("robOperands")) + } else None + val robValid = RegInit(VecInit(Seq.fill(robDepth)(false.B))) + val robIssued = RegInit(VecInit(Seq.fill(robDepth)(false.B))) + val robComplete = RegInit(VecInit(Seq.fill(robDepth)(false.B))) + val instIds = RegInit(VecInit(Seq.fill(robDepth)(0.U(64.W)))) + val nextInstId = RegInit(1.U(64.W)) + + val statusHashes = + if (b.sim.diffTest) { + Some(RegInit(VecInit(Seq.fill(robDepth)(VecInit(Seq.fill(3)(0.U(32.W))))))) + } else { + None + } + + io.inst_ids := instIds + + val headPtr = RegInit(0.U(idWidth.W)) + val tailPtr = RegInit(0.U(idWidth.W)) + val issuedCount = RegInit(0.U(log2Up(robDepth + 1).W)) + private val bankColWidth = b.memDomain.groupCountWidth + val bankCols = RegInit(VecInit(Seq.fill(b.memDomain.virtualBankCount)(0.U(bankColWidth.W)))) + // In-flight ownership is tracked in the architectural vbank namespace. + private val vbankMaskWidth = b.memDomain.virtualBankCount + val vbankBusy = RegInit(0.U(vbankMaskWidth.W)) + + // Dependency state is maintained incrementally instead of rebuilding all + // older-entry comparisons every cycle. A bit in slot k names the ROB slot + // that currently blocks k. Ordinary RAW dependencies disappear at complete; + // dependencies involving a mapping/config instruction disappear at commit. + // Keeping one union mask is sufficient because a config dependency is never + // allowed to clear earlier than commit, even when it also looks like a RAW. + val dependencyMask = RegInit(VecInit(Seq.fill(robDepth)(0.U(robDepth.W)))) + + val isEmpty = headPtr === tailPtr && !robValid(headPtr) + val isFull = headPtr === tailPtr && robValid(headPtr) + + def nextPtr(p: UInt): UInt = Mux(p === (robDepth - 1).U, 0.U, p + 1.U) + def wrapPtr(v: UInt): UInt = Mux(v >= robDepth.U, v - robDepth.U, v) + def robIdx(v: UInt): UInt = v(idWidth - 1, 0) + + def isMappingConfig(entry: GlobalRobEntry): Bool = + entry.cmd.domain_id === DomainId.MEM && + (entry.cmd.cmd.funct === MSET_BITPAT) + + def accessUsesBank(access: BankAccessInfo, bank: UInt): Bool = + (access.rd_bank_0_valid && access.rd_bank_0_id === bank) || + (access.rd_bank_1_valid && access.rd_bank_1_id === bank) || + (access.wr_bank_valid && access.wr_bank_id === bank) + + // Build one architectural-vbank mask per ROB slot once, then hazard checks + // become mask intersections instead of repeating ID comparisons. + private val hazardBankCount = b.memDomain.virtualBankCount + + def rawReadMask(access: BankAccessInfo): UInt = { + val rd0 = Mux( + access.rd_bank_0_valid && access.rd_bank_0_id < hazardBankCount.U, + UIntToOH(access.rd_bank_0_id, hazardBankCount), + 0.U(hazardBankCount.W) + ) + val rd1 = Mux( + access.rd_bank_1_valid && access.rd_bank_1_id < hazardBankCount.U, + UIntToOH(access.rd_bank_1_id, hazardBankCount), + 0.U(hazardBankCount.W) + ) + rd0 | rd1 + } + + def rawWriteMask(access: BankAccessInfo): UInt = Mux( + access.wr_bank_valid && access.wr_bank_id < hazardBankCount.U, + UIntToOH(access.wr_bank_id, hazardBankCount), + 0.U(hazardBankCount.W) + ) + + def rawUseMask(access: BankAccessInfo): UInt = + rawReadMask(access) | rawWriteMask(access) + + // --------------------------------------------------------------------------- + // Allocate: enqueue decoded instruction into ROB + // rob_id == tailPtr at allocation time (no separate counter needed) + // --------------------------------------------------------------------------- + val commitMask = Wire(Vec(robDepth, Bool())) + for (i <- 0 until robDepth) { + commitMask(i) := false.B + } + bat.io.free.valid := commitMask.asUInt.orR + bat.io.free.mask := commitMask + + val commitScan = Wire(Vec(robDepth, Bool())) + val commitKeep = Wire(Vec(robDepth + 1, Bool())) + commitKeep(0) := true.B + for (i <- 0 until robDepth) { + val ptr = robIdx(wrapPtr(headPtr + i.U)) + commitScan(i) := commitKeep(i) && robValid(ptr) && robComplete(ptr) + commitKeep(i + 1) := (if (b.sim.diffTest) false.B else commitScan(i)) + } + val hasCommit = commitScan.asUInt.orR + val tailAlias = Wire(UInt(b.frontend.bank_id_len.W)) + tailAlias := + b.memDomain.virtualBankCount.U(b.frontend.bank_id_len.W) + tailPtr + + val tailAliasLive = WireDefault(false.B) + for (i <- 0 until robDepth) { + when(robValid(i) && !robComplete(i) && accessUsesBank(robEntries(i).renamedBankAccess, tailAlias)) { + tailAliasLive := true.B + } + } + + io.alloc.ready := !isFull && !hasCommit && !tailAliasLive + bat.io.alloc.valid := io.alloc.fire + bat.io.alloc.rob_id := tailPtr + bat.io.alloc.raw := io.alloc.bits.bankAccess + + // Mark write alias as busy in scoreboard at alloc time (not issue time). + scoreboard.alloc.valid := io.alloc.fire && io.alloc.bits.bankAccess.wr_bank_valid + scoreboard.alloc.bits := bat.io.alloc_renamed + + // Bank masks are shared by allocation and issue. This avoids rebuilding the + // UIntToOH decoders once for every older-entry comparison at allocation. + val entryRawReads = Wire(Vec(robDepth, UInt(hazardBankCount.W))) + val entryRawWrites = Wire(Vec(robDepth, UInt(hazardBankCount.W))) + val entryIsConfig = Wire(Vec(robDepth, Bool())) + for (slot <- 0 until robDepth) { + entryRawReads(slot) := rawReadMask(robEntries(slot).cmd.bankAccess) + entryRawWrites(slot) := rawWriteMask(robEntries(slot).cmd.bankAccess) + entryIsConfig(slot) := isMappingConfig(robEntries(slot)) + } + + // A newly allocated entry is always younger than all currently valid ROB + // entries (tailPtr points at the first free slot). Capture its older-entry + // dependencies once here; issue no longer repeats pairwise comparisons. + val allocReadMask = rawReadMask(io.alloc.bits.bankAccess) + val allocWriteMask = rawWriteMask(io.alloc.bits.bankAccess) + val allocIsConfig = io.alloc.bits.domain_id === DomainId.MEM && + (io.alloc.bits.cmd.funct === MSET_BITPAT) + val allocIsBall = io.alloc.bits.domain_id === DomainId.BALL + val allocDependencyBits = Wire(Vec(robDepth, Bool())) + for (older <- 0 until robDepth) { + val olderUseMask = entryRawReads(older) | entryRawWrites(older) + val rawConflict = ((allocReadMask & entryRawWrites(older)) | + (allocWriteMask & olderUseMask)).orR + val configConflict = (allocIsConfig && entryIsConfig(older)) || + ((allocIsConfig || entryIsConfig(older)) && ((allocReadMask | allocWriteMask) & olderUseMask).orR) + val sameBall = allocIsBall && + robEntries(older).cmd.domain_id === DomainId.BALL && + robEntries(older).cmd.ball_bid === io.alloc.bits.ball_bid + // Config conflicts include entries that have completed but are waiting to + // commit. RAW conflicts and same-Ball commands release at completion. + allocDependencyBits(older) := + (robValid(older) && !robComplete(older) && (rawConflict || sameBall)) || + (robValid(older) && configConflict) + } + val allocDependencies = allocDependencyBits.asUInt + val allocUsesInstId = io.alloc.bits.cmd.pc =/= 0.U + + when(io.alloc.fire) { + operandRam.foreach(_.write(tailPtr, Cat(io.alloc.bits.cmd.rs1Data, io.alloc.bits.cmd.rs2Data))) + itraceAlloc.io.is_issue := 2.U + itraceAlloc.io.rob_id := tailPtr + itraceAlloc.io.inst_id := Mux(allocUsesInstId, nextInstId, 0.U) + itraceAlloc.io.domain_id := io.alloc.bits.domain_id + itraceAlloc.io.funct := io.alloc.bits.cmd.funct + itraceAlloc.io.pc := io.alloc.bits.cmd.pc + itraceAlloc.io.rs1_data := io.alloc.bits.cmd.rs1Data + itraceAlloc.io.rs2_data := io.alloc.bits.cmd.rs2Data + itraceAlloc.io.enable := true.B + + robEntries(tailPtr).cmd := io.alloc.bits + robEntries(tailPtr).renamedBankAccess := bat.io.alloc_renamed + robEntries(tailPtr).rob_id := tailPtr + instIds(tailPtr) := Mux(allocUsesInstId, nextInstId, 0.U) + robValid(tailPtr) := true.B + robIssued(tailPtr) := false.B + robComplete(tailPtr) := false.B + statusHashes.foreach { hashes => + for (slot <- 0 until 3) { + hashes(tailPtr)(slot) := 0.U + } + } + tailPtr := nextPtr(tailPtr) + when(allocUsesInstId) { + nextInstId := nextInstId + 1.U + } + } + + // --------------------------------------------------------------------------- + // Complete: mark entry as completed, release scoreboard resources + // --------------------------------------------------------------------------- + if (b.sim.diffTest) { + val collecting = RegInit(false.B) + val collectCid = Reg(UInt(idWidth.W)) + val collectSlot = Reg(UInt(2.W)) + val collectGroup = Reg(UInt(32.W)) + val currentHash = Reg(UInt(32.W)) + val hashReady = RegInit(false.B) + val hashCid = Reg(UInt(idWidth.W)) + + val incomingAccess = robEntries(io.complete.bits).cmd.bankAccess + val incomingNeedsHash = instIds(io.complete.bits) =/= 0.U && !isMappingConfig(robEntries(io.complete.bits)) && + (incomingAccess.rd_bank_0_valid || incomingAccess.rd_bank_1_valid || incomingAccess.wr_bank_valid) + io.complete.ready := !incomingNeedsHash || (hashReady && hashCid === io.complete.bits) + + when(!collecting && !hashReady && io.complete.valid && incomingNeedsHash) { + collecting := true.B + collectCid := io.complete.bits + collectSlot := Mux(incomingAccess.rd_bank_0_valid, 0.U, Mux(incomingAccess.rd_bank_1_valid, 1.U, 2.U)) + collectGroup := 0.U + currentHash := 0.U + } + + val access = robEntries(collectCid).cmd.bankAccess + val vbank = MuxLookup(collectSlot, access.wr_bank_id)(Seq( + 0.U -> access.rd_bank_0_id, + 1.U -> access.rd_bank_1_id, + 2.U -> access.wr_bank_id + )) + val hasNextSlot = MuxLookup(collectSlot, false.B)(Seq( + 0.U -> (access.rd_bank_1_valid || access.wr_bank_valid), + 1.U -> access.wr_bank_valid + )) + val nextSlot = Mux(collectSlot === 0.U && access.rd_bank_1_valid, 1.U, 2.U) + val matches = VecInit(io.bank_hashes.get.map { state => + state.valid && state.hartId === io.hart_id && state.vbankId === vbank && state.groupId === collectGroup + }) + val nextMatches = VecInit(io.bank_hashes.get.map { state => + state.valid && state.hartId === io.hart_id && state.vbankId === vbank && state.groupId === collectGroup + 1.U + }) + val physical = Mux1H(matches, io.bank_hashes.get) + def rotateLeft(value: UInt, amount: Int): UInt = Cat(value(31 - amount, 0), value(31, 32 - amount)) + + val mixed = physical.statusHash ^ rotateLeft(physical.groupId, 7) ^ "h9e3779b9".U + val nextHash = rotateLeft(currentHash, 5) ^ mixed ^ rotateLeft(mixed, 13) + + when(collecting) { + assert(PopCount(matches) === 1.U, "BTrace requires exactly one physical bank per vbank group") + when(nextMatches.asUInt.orR) { + currentHash := nextHash + collectGroup := collectGroup + 1.U + }.otherwise { + statusHashes.get(collectCid)(collectSlot) := nextHash + when(hasNextSlot) { + collectSlot := nextSlot + collectGroup := 0.U + currentHash := 0.U + }.otherwise { + collecting := false.B + hashReady := true.B + hashCid := collectCid + } + } + } + + when(io.complete.fire) { + hashReady := false.B + } + } else { + io.complete.ready := true.B + } + + scoreboard.complete.valid := false.B + scoreboard.complete.bits := 0.U.asTypeOf(scoreboard.complete.bits) + + val issueFired = WireDefault(false.B) + val completeIssuedEntry = io.complete.fire && robIssued(io.complete.bits) + + when(io.complete.fire) { + val cid = io.complete.bits + robComplete(cid) := true.B + scoreboard.complete.valid := true.B + scoreboard.complete.bits := robEntries(cid).renamedBankAccess + + itraceComp.io.is_issue := 0.U + itraceComp.io.rob_id := cid + itraceComp.io.inst_id := instIds(cid) + itraceComp.io.domain_id := robEntries(cid).cmd.domain_id + itraceComp.io.funct := robEntries(cid).cmd.cmd.funct + itraceComp.io.pc := robEntries(cid).cmd.cmd.pc + itraceComp.io.rs1_data := robEntries(cid).cmd.cmd.rs1Data + itraceComp.io.rs2_data := robEntries(cid).cmd.cmd.rs2Data + itraceComp.io.enable := true.B + } + + val completedBitMask = Mux( + io.complete.fire, + UIntToOH(io.complete.bits, robDepth), + 0.U(robDepth.W) + ) + + // --------------------------------------------------------------------------- + // Issue: scan from head for first issuable entry (valid && !issued && !complete) + // --------------------------------------------------------------------------- + val scanValid = Wire(Vec(robDepth, Bool())) + val scanReady = Wire(Vec(robDepth, Bool())) + val vbankMasks = Wire(Vec(robDepth, UInt(vbankMaskWidth.W))) + for (slot <- 0 until robDepth) { + // Reuse the raw hazard mask for active-command ownership. + vbankMasks(slot) := entryRawReads(slot) | entryRawWrites(slot) + } + + // Check each candidate against older ROB entries using mask intersections. + // The masks are precomputed once per slot, so this retains the original + // age-sensitive RAW/WAR/WAW semantics without replicating three equality + // comparators for every bank access pair. + for (i <- 0 until robDepth) { + val ptr = robIdx(wrapPtr(headPtr + i.U)) + scanValid(i) := robValid(ptr) && !robIssued(ptr) && !robComplete(ptr) + scoreboard.queryVec(i) := robEntries(ptr).renamedBankAccess + scanReady(i) := scanValid(i) && !scoreboard.hazardVec(i) && + !dependencyMask(ptr).orR && + !(vbankMasks(ptr) & vbankBusy).orR + } + + val hasReady = scanReady.asUInt.orR + val firstReady = PriorityEncoder(scanReady.asUInt) + val actualIssuePtr = robIdx(wrapPtr(headPtr + firstReady)) + + scoreboard.query := robEntries(actualIssuePtr).renamedBankAccess + val canIssue = hasReady + + val issueStageValid = RegInit(false.B) + val issueStageEntry = Reg(new GlobalRobEntry(b)) + val issueStageFire = issueStageValid && !io.subRobActive && io.issue.ready + val issueStageReady = !issueStageValid || issueStageFire + + // Keep the wide ROB entry and bank-column mux one register boundary away + // from the age/scoreboard scan. The pointer stage can accept one candidate + // per cycle; the payload stage drains at one per cycle, so steady-state II + // remains one while the extra latency is hidden by in-flight commands. + val issuePtrValid = RegInit(false.B) + val issuePtr = Reg(UInt(idWidth.W)) + val issuePtrFire = issuePtrValid && issueStageReady + val issuePtrReady = !issuePtrValid || issuePtrFire + val issueLoad = canIssue && !io.subRobActive && issuePtrReady + val issuePayload = Wire(new GlobalRobEntry(b)) + issuePayload := robEntries(issuePtr) + operandRam.foreach { memory => + // Read at pointer selection, then re-read while that pointer is stalled. + // Replacement selects the new pointer; the current response is consumed + // before the next edge. This preserves the existing two-stage issue timing. + val readAddress = Mux(issueLoad, actualIssuePtr, issuePtr) + val readEnable = issueLoad || issuePtrValid + val operands = memory.read(readAddress, readEnable) + issuePayload.cmd.cmd.rs1Data := operands(2 * operandWidth - 1, operandWidth) + issuePayload.cmd.cmd.rs2Data := operands(operandWidth - 1, 0) + when(io.alloc.fire && readEnable) { + assert(tailPtr =/= readAddress, "ROB operand RAM read/write collision") + } + } + issuePayload.cmd.op1_col := Mux( + issuePayload.cmd.bankAccess.rd_bank_0_valid, + bankCols(issuePayload.cmd.bankAccess.rd_bank_0_id(b.memDomain.vbankIdWidth - 1, 0)), + 0.U + ) + issuePayload.cmd.op2_col := Mux( + issuePayload.cmd.bankAccess.rd_bank_1_valid, + bankCols(issuePayload.cmd.bankAccess.rd_bank_1_id(b.memDomain.vbankIdWidth - 1, 0)), + 0.U + ) + issuePayload.cmd.wr_col := Mux( + issuePayload.cmd.bankAccess.wr_bank_valid, + bankCols(issuePayload.cmd.bankAccess.wr_bank_id(b.memDomain.vbankIdWidth - 1, 0)), + 0.U + ) + + io.issue.valid := issueStageValid && !io.subRobActive + io.issue.bits := issueStageEntry + + when(issuePtrReady) { + issuePtrValid := issueLoad + when(issueLoad) { + issuePtr := actualIssuePtr + } + } + when(issueStageReady) { + issueStageValid := issuePtrValid + when(issuePtrFire) { + issueStageEntry := issuePayload + } + } + + scoreboard.issue.valid := false.B + scoreboard.issue.bits := 0.U.asTypeOf(scoreboard.issue.bits) + + when(issueLoad) { + robIssued(actualIssuePtr) := true.B + issueFired := true.B + scoreboard.issue.valid := true.B + scoreboard.issue.bits := robEntries(actualIssuePtr).renamedBankAccess + + itraceIssue.io.is_issue := 1.U + itraceIssue.io.rob_id := robEntries(actualIssuePtr).rob_id + itraceIssue.io.inst_id := instIds(actualIssuePtr) + itraceIssue.io.domain_id := robEntries(actualIssuePtr).cmd.domain_id + itraceIssue.io.funct := robEntries(actualIssuePtr).cmd.cmd.funct + itraceIssue.io.pc := robEntries(actualIssuePtr).cmd.cmd.pc + itraceIssue.io.rs1_data := robEntries(actualIssuePtr).cmd.cmd.rs1Data + itraceIssue.io.rs2_data := robEntries(actualIssuePtr).cmd.cmd.rs2Data + itraceIssue.io.enable := true.B + } + + // Preserve the original update ordering when issue and complete coincide: + // a completion clears ownership after the newly issued transaction marks + // its banks busy. + val issuedVbankMask = Mux(issueLoad, vbankMasks(actualIssuePtr), 0.U) + val completedVbankMask = Mux(io.complete.fire, vbankMasks(io.complete.bits), 0.U) + when(issueLoad || io.complete.fire) { + vbankBusy := + (vbankBusy & ~completedVbankMask) | issuedVbankMask + } + + issuedCount := issuedCount + issueFired.asUInt - completeIssuedEntry.asUInt + + // --------------------------------------------------------------------------- + // Commit: clear completed entries. + // Explicitly skip entries being allocated or completed this cycle. + // --------------------------------------------------------------------------- + for (i <- 0 until robDepth) { + val hits = (0 until robDepth).map { off => + val ptr = robIdx(wrapPtr(headPtr + off.U)) + commitScan(off) && ptr === i.U + } + commitMask(i) := hits.reduce(_ || _) + when(commitMask(i)) { + when(robEntries(i).cmd.domain_id === DomainId.MEM && robEntries(i).cmd.cmd.funct === MSET_BITPAT) { + val bankId = robEntries(i).cmd.bankAccess.wr_bank_id + val bank = bankId(b.memDomain.vbankIdWidth - 1, 0) + val col = robEntries(i).cmd.cmd.rs2Data(9, 5) + when(robEntries(i).cmd.cmd.rs2Data(10)) { + val fullCol = + if (b.memDomain.sharedEnable) { + Mux( + bankId >= b.frontend.shared_bank_id_base.U && bankId < b.memDomain.virtualBankCount.U, + SharedMemLayout.totalBank(b).U(bankColWidth.W), + b.memDomain.bankNum.U(bankColWidth.W) + ) + } else { + b.memDomain.bankNum.U(bankColWidth.W) + } + bankCols(bank) := Mux(col === 0.U, fullCol, col) + }.otherwise { + bankCols(bank) := 0.U + } + } + robValid(i) := false.B + robIssued(i) := false.B + robComplete(i) := false.B + } + } + + if (b.sim.diffTest) { + val commitIndex = PriorityEncoder(commitMask.asUInt) + val commitAccess = robEntries(commitIndex).cmd.bankAccess + val invalidVbank = "hffffffff".U(32.W) + val btrace = Module(new BTraceDPI) + btrace.io.clock := clock + btrace.io.reset := reset.asBool + btrace.io.instId := instIds(commitIndex) + btrace.io.hartId := io.hart_id + btrace.io.r0Vbank := Mux(commitAccess.rd_bank_0_valid, commitAccess.rd_bank_0_id, invalidVbank) + btrace.io.r0Hash := Mux(commitAccess.rd_bank_0_valid, statusHashes.get(commitIndex)(0), 0.U) + btrace.io.r1Vbank := Mux(commitAccess.rd_bank_1_valid, commitAccess.rd_bank_1_id, invalidVbank) + btrace.io.r1Hash := Mux(commitAccess.rd_bank_1_valid, statusHashes.get(commitIndex)(1), 0.U) + btrace.io.w0Vbank := Mux(commitAccess.wr_bank_valid, commitAccess.wr_bank_id, invalidVbank) + btrace.io.w0Hash := Mux(commitAccess.wr_bank_valid, statusHashes.get(commitIndex)(2), 0.U) + btrace.io.fire := hasCommit && instIds(commitIndex) =/= 0.U && !isMappingConfig(robEntries(commitIndex)) && + (commitAccess.rd_bank_0_valid || commitAccess.rd_bank_1_valid || commitAccess.wr_bank_valid) + } + + // Maintain dependency masks at the same architectural events that gate the + // issue scan. A dependency involving a config entry (on either side) clears + // only at commit; all other dependencies clear at complete. This is the + // union-mask form of the former separate RAW/config masks. + val configEntryMask = entryIsConfig.asUInt + for (slot <- 0 until robDepth) { + val isAllocatedSlot = io.alloc.fire && tailPtr === slot.U + val slotIsConfig = Mux(isAllocatedSlot, allocIsConfig, entryIsConfig(slot)) + // Each dependency bit names the older entry that blocks this slot. Keep a + // config-related edge through completion when either endpoint is config. + val configRelated = configEntryMask | Fill(robDepth, slotIsConfig) + val clearMask = commitMask.asUInt | (completedBitMask & ~configRelated) + when(isAllocatedSlot) { + dependencyMask(slot) := allocDependencies & ~clearMask + }.otherwise { + dependencyMask(slot) := dependencyMask(slot) & ~clearMask + } + } + + val commitCount = PopCount(commitScan) + headPtr := wrapPtr(headPtr + commitCount) + + // --------------------------------------------------------------------------- + // Status outputs + // --------------------------------------------------------------------------- + io.empty := isEmpty + io.full := isFull + io.head_ptr := headPtr + io.issued_count := issuedCount + io.entry_valid := robValid + io.entry_complete := robComplete + +} + +object GlobalROB { + def operandRamEnabled: Boolean = java.lang.Boolean.getBoolean("fpga.robOperandRam") +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/framework/MemFrontend.scala b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/framework/MemFrontend.scala new file mode 100644 index 0000000..d84e16f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/framework/MemFrontend.scala @@ -0,0 +1,255 @@ +package framework.memdomain.frontend + +import chisel3._ +import chisel3.util._ +import freechips.rocketchip.tile._ +import framework.memdomain.frontend.mem.dma.{StreamReader, StreamWriter} +import framework.memdomain.frontend.mem.{MemConfiger, MemConfigerIO, MemLoader, MemStorer} +import framework.memdomain.frontend.mem.tlb.{BBTLBCluster, BBTLBExceptionIO, BBTLBIO, BBTLBPTWIO} +import freechips.rocketchip.tilelink.{TLBundle, TLEdgeOut} +import framework.frontend.globalrs.{GlobalSchedComplete, GlobalSchedIssue} +import framework.balldomain.blink.{BankRead, BankWrite} +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import framework.top.GlobalConfig +import framework.memdomain.frontend.cmd.decoder.MemDomainDecoder +import framework.memdomain.frontend.cmd.rs.MemReservationStation +import framework.memdomain.utils.pmc.MemCyclePMC + +/** + * MemFrontend: + * Provides DMA interface and Ball Domain interface + */ +@instantiable +class MemFrontend(val b: GlobalConfig)(edge: TLEdgeOut) extends Module { + + @public + val io = IO(new Bundle { + // Issue interface from global RS (single channel) + val global_issue_i = Flipped(Decoupled(new GlobalSchedIssue(b))) + // Report completion to global RS (single channel) + val global_complete_o = Decoupled(new GlobalSchedComplete(b)) + + // Bank read/write interface - used by load/store + val interdma = new Bundle { + val bankRead = Flipped(new BankRead(b)) + val bankWrite = Flipped(new BankWrite(b)) + val read_is_shared = Output(Bool()) + val write_is_shared = Output(Bool()) + } + + // TLB interfaces for internal DMA modules (Reader/Writer) + // These are NOT exposed to outside - only PTW and TLB exception are exposed + // PTW interface - needs to connect to upper level PTW (shared TLB has only 1 PTW) + val ptw = Vec(1, new BBTLBPTWIO(b)) + // TLB exception interface - exposed to upper level for handling flush, etc. (shared TLB has only 1 exp) + val tlbExp = Vec(1, new BBTLBExceptionIO) + + // TileLink physical connections for DMA (Reader/Writer) + val tl_reader = new TLBundle(edge.bundle) + val tl_writer = new TLBundle(edge.bundle) + + val config = Decoupled(new MemConfigerIO(b)) + + // MMIO outputs (to MmioPool via MemDomain) + val is_mvin_mmio_active = Output(Bool()) + val mmio_addr = Output(UInt(17.W)) + val mmio_col = Output(UInt(8.W)) + + // Query interface to backend for group count + val query_vbank_id = Output(UInt(b.memDomain.vbankIdWidth.W)) + val query_is_shared = Output(Bool()) + val query_group_count = Input(UInt(b.memDomain.groupCountWidth.W)) + + val hartid = Input(UInt(b.tile.xLen.W)) + + // Busy signal + val busy = Output(Bool()) + }) + + val memDecoder: Instance[MemDomainDecoder] = Instantiate(new MemDomainDecoder(b)) + val memRs: Instance[MemReservationStation] = Instantiate(new MemReservationStation(b)) + val memLoader: Instance[MemLoader] = Instantiate(new MemLoader(b)) + val memStorer: Instance[MemStorer] = Instantiate(new MemStorer(b)) + val pmc: Instance[MemCyclePMC] = Instantiate(new MemCyclePMC(b)) + + // TLB cluster - internal TLB management for DMA modules + // Supports 2 clients: StreamReader (client 1) and StreamWriter (client 0) + val tlbCluster = Instantiate(new BBTLBCluster(b)(edge)) + + // DMA Reader and Writer modules - handle actual DMA transfers + val reader: Instance[StreamReader] = Instantiate(new StreamReader(b)(edge)) + val writer: Instance[StreamWriter] = Instantiate(new StreamWriter(b)(edge)) + val configer: Instance[MemConfiger] = Instantiate(new MemConfiger(b)) + +// ----------------------------------------------------------------------------- +// Global RS -> MemDecoder +// ----------------------------------------------------------------------------- + memDecoder.io.cmd_i.valid := io.global_issue_i.valid + memDecoder.io.cmd_i.bits := io.global_issue_i.bits.cmd + io.global_issue_i.ready := memDecoder.io.cmd_i.ready + + // Config signal goes to backend + io.config <> configer.io.config + + // Loader and storer may query different banks concurrently. Each lookup owns + // the registered backend address and reply until its requester consumes it. + val groupQuery = Module(new MemGroupQueryArbiter(b.memDomain.vbankIdWidth, b.memDomain.groupCountWidth)) + groupQuery.io.request(0).valid := memLoader.io.query_valid + groupQuery.io.request(0).bits.bank := memLoader.io.query_vbank_id + groupQuery.io.request(0).bits.shared := memLoader.io.query_is_shared + memLoader.io.query_ready := groupQuery.io.request(0).ready + memLoader.io.query_resp_valid := groupQuery.io.response(0).valid + memLoader.io.query_group_count := groupQuery.io.response(0).bits + groupQuery.io.response(0).ready := memLoader.io.query_resp_ready + groupQuery.io.request(1).valid := memStorer.io.query_valid + groupQuery.io.request(1).bits.bank := memStorer.io.query_vbank_id + groupQuery.io.request(1).bits.shared := memStorer.io.query_is_shared + memStorer.io.query_ready := groupQuery.io.request(1).ready + memStorer.io.query_resp_valid := groupQuery.io.response(1).valid + memStorer.io.query_group_count := groupQuery.io.response(1).bits + groupQuery.io.response(1).ready := memStorer.io.query_resp_ready + io.query_vbank_id := groupQuery.io.backendBank + io.query_is_shared := groupQuery.io.backendShared + groupQuery.io.backendCount := io.query_group_count + +// ----------------------------------------------------------------------------- +// MemDecoder -> MemReservationStation +// ----------------------------------------------------------------------------- + // Connect decoded instruction and global rob_id + memRs.io.mem_decode_cmd_i.valid := memDecoder.io.mem_decode_cmd_o.valid + memRs.io.mem_decode_cmd_i.bits.cmd := memDecoder.io.mem_decode_cmd_o.bits + memRs.io.mem_decode_cmd_i.bits.rob_id := io.global_issue_i.bits.rob_id + memRs.io.mem_decode_cmd_i.bits.is_sub := io.global_issue_i.bits.is_sub + memRs.io.mem_decode_cmd_i.bits.sub_rob_id := io.global_issue_i.bits.sub_rob_id + memDecoder.io.mem_decode_cmd_o.ready := memRs.io.mem_decode_cmd_i.ready + +// ----------------------------------------------------------------------------- +// MemReservationStation -> MemLoader/MemStorer +// ----------------------------------------------------------------------------- + memLoader.io.cmdReq <> memRs.io.issue_o.ld + memStorer.io.cmdReq <> memRs.io.issue_o.st + configer.io.cmdReq <> memRs.io.issue_o.cf + configer.io.hartid := io.hartid + memRs.io.commit_i.ld <> memLoader.io.cmdResp + memRs.io.commit_i.st <> memStorer.io.cmdResp + memRs.io.commit_i.cf <> configer.io.cmdResp + +//===-------------------------------------------------------------------===//-- +// PMC - Performance Monitor Counter +// ----------------------------------------------------------------------------- + pmc.io.ldReq_i.valid := memRs.io.issue_o.ld.fire + pmc.io.ldReq_i.bits := memRs.io.issue_o.ld.bits + pmc.io.stReq_i.valid := memRs.io.issue_o.st.fire + pmc.io.stReq_i.bits := memRs.io.issue_o.st.bits + pmc.io.ldResp_o.valid := memLoader.io.cmdResp.fire + pmc.io.ldResp_o.bits := memLoader.io.cmdResp.bits + pmc.io.stResp_o.valid := memStorer.io.cmdResp.fire + pmc.io.stResp_o.bits := memStorer.io.cmdResp.bits + + // Connect Reader and Writer to MemLoader and MemStorer + memLoader.io.dmaReq <> reader.io.req + reader.io.resp <> memLoader.io.dmaResp + memStorer.io.dmaReq <> writer.io.req + writer.io.resp <> memStorer.io.dmaResp + + // TLB connection - internal TLB cluster connected to DMA modules + // Client 0: StreamWriter, Client 1: StreamReader + // Insert pipeline registers to break combinational loops + tlbCluster.io.clients(1).req.valid := reader.io.tlb.req.valid + tlbCluster.io.clients(1).req.bits := reader.io.tlb.req.bits + reader.io.tlb.req.ready := tlbCluster.io.clients(1).req.ready + + reader.io.tlb.resp.valid := tlbCluster.io.clients(1).resp.valid + reader.io.tlb.resp.bits := tlbCluster.io.clients(1).resp.bits + tlbCluster.io.clients(1).resp.ready := reader.io.tlb.resp.ready + + tlbCluster.io.clients(0).req.valid := writer.io.tlb.req.valid + tlbCluster.io.clients(0).req.bits := writer.io.tlb.req.bits + writer.io.tlb.req.ready := tlbCluster.io.clients(0).req.ready + + writer.io.tlb.resp.valid := tlbCluster.io.clients(0).resp.valid + writer.io.tlb.resp.bits := tlbCluster.io.clients(0).resp.bits + tlbCluster.io.clients(0).resp.ready := writer.io.tlb.resp.ready + + // Connect DMA flush signals to TLB exceptions + reader.io.flush := io.tlbExp(0).flush() + writer.io.flush := io.tlbExp(0).flush() + + // PTW interface - connect to upper level page table walker + io.ptw <> tlbCluster.io.ptw + + // TLB exception interface - connect to upper level for flush handling + tlbCluster.io.exp <> io.tlbExp + + // Connect TileLink physical ports from Reader/Writer to external interface + io.tl_reader <> reader.io.tl + io.tl_writer <> writer.io.tl + + // MemLoader and MSET.clear share the frontend write channel. A source owns + // the channel until its write response returns, preserving BankWrite's + // request/response pairing. + val frontendWriteBusy = RegInit(false.B) + val frontendWriteOwnerConfig = RegInit(false.B) + val selectConfigWrite = configer.io.bankWrite.io.req.valid + val selectConfigOwner = Mux(frontendWriteBusy, frontendWriteOwnerConfig, selectConfigWrite) + + io.interdma.bankWrite.io.req.valid := !frontendWriteBusy && + (configer.io.bankWrite.io.req.valid || memLoader.io.bankWrite.io.req.valid) + io.interdma.bankWrite.io.req.bits := Mux( + selectConfigWrite, + configer.io.bankWrite.io.req.bits, + memLoader.io.bankWrite.io.req.bits + ) + io.interdma.bankWrite.bank_id := Mux(selectConfigWrite, configer.io.bankWrite.bank_id, memLoader.io.bankWrite.bank_id) + io.interdma.bankWrite.rob_id := Mux(selectConfigWrite, configer.io.bankWrite.rob_id, memLoader.io.bankWrite.rob_id) + io.interdma.bankWrite.ball_id := Mux(selectConfigWrite, configer.io.bankWrite.ball_id, memLoader.io.bankWrite.ball_id) + io.interdma.bankWrite.group_id := Mux( + selectConfigWrite, + configer.io.bankWrite.group_id, + memLoader.io.bankWrite.group_id + ) + + configer.io.bankWrite.io.req.ready := !frontendWriteBusy && selectConfigWrite && io.interdma.bankWrite.io.req.ready + memLoader.io.bankWrite.io.req.ready := !frontendWriteBusy && !selectConfigWrite && + memLoader.io.bankWrite.io.req.valid && io.interdma.bankWrite.io.req.ready + + io.interdma.bankWrite.io.resp.ready := frontendWriteBusy && Mux( + frontendWriteOwnerConfig, + configer.io.bankWrite.io.resp.ready, + memLoader.io.bankWrite.io.resp.ready + ) + configer.io.bankWrite.io.resp.valid := frontendWriteBusy && frontendWriteOwnerConfig && + io.interdma.bankWrite.io.resp.valid + configer.io.bankWrite.io.resp.bits := io.interdma.bankWrite.io.resp.bits + memLoader.io.bankWrite.io.resp.valid := frontendWriteBusy && !frontendWriteOwnerConfig && + io.interdma.bankWrite.io.resp.valid + memLoader.io.bankWrite.io.resp.bits := io.interdma.bankWrite.io.resp.bits + + when(io.interdma.bankWrite.io.req.fire) { + frontendWriteBusy := true.B + frontendWriteOwnerConfig := selectConfigWrite + } + when(io.interdma.bankWrite.io.resp.fire) { + frontendWriteBusy := false.B + } + + memStorer.io.bankRead <> io.interdma.bankRead + io.interdma.read_is_shared := memStorer.io.is_shared + io.interdma.write_is_shared := Mux(selectConfigOwner, false.B, memLoader.io.is_shared) + + // MMIO signals from MemConfiger and MemLoader, exposed to MemDomain + io.is_mvin_mmio_active := memLoader.io.is_mvin_mmio_active + io.mmio_addr := memLoader.io.mmio_addr + io.mmio_col := memLoader.io.mmio_col + + // Completion signal connected to global RS + io.global_complete_o.valid := memRs.io.complete_o.valid + io.global_complete_o.bits.rob_id := memRs.io.complete_o.bits.rob_id + io.global_complete_o.bits.is_sub := memRs.io.complete_o.bits.is_sub + io.global_complete_o.bits.sub_rob_id := memRs.io.complete_o.bits.sub_rob_id + memRs.io.complete_o.ready := io.global_complete_o.ready + + // Busy signal + // Simple busy signal + io.busy := !memRs.io.complete_o.ready +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/framework/MemGroupQueryArbiter.scala b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/framework/MemGroupQueryArbiter.scala new file mode 100644 index 0000000..ed820c5 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/framework/MemGroupQueryArbiter.scala @@ -0,0 +1,46 @@ +package framework.memdomain.frontend + +import chisel3._ +import chisel3.util._ + +class MemGroupQuery(val bankWidth: Int) extends Bundle { + val bank = UInt(bankWidth.W) + val shared = Bool() +} + +/** Own the two-cycle backend lookup until the selected client accepts its reply. */ +class MemGroupQueryArbiter(bankWidth: Int, countWidth: Int) extends Module { + val io = IO(new Bundle { + val request = Vec(2, Flipped(Decoupled(new MemGroupQuery(bankWidth)))) + val response = Vec(2, Decoupled(UInt(countWidth.W))) + val backendBank = Output(UInt(bankWidth.W)) + val backendShared = Output(Bool()) + val backendCount = Input(UInt(countWidth.W)) + }) + val idle :: waitFirst :: waitSecond :: reply :: Nil = Enum(4) + val state = RegInit(idle) + val owner = RegInit(0.U(1.W)) + val address = RegInit(0.U.asTypeOf(new MemGroupQuery(bankWidth))) + val count = RegInit(0.U(countWidth.W)) + val arbiter = Module(new RRArbiter(new MemGroupQuery(bankWidth), 2)) + arbiter.io.in <> io.request + arbiter.io.out.ready := state === idle + val query = Mux(state === idle, arbiter.io.out.bits, address) + io.backendBank := query.bank + io.backendShared := query.shared + for (i <- 0 until 2) { + io.response(i).valid := state === reply && owner === i.U + io.response(i).bits := count + } + when(arbiter.io.out.fire) { + owner := arbiter.io.chosen + address := arbiter.io.out.bits + state := waitFirst + } + when(state === waitFirst) { state := waitSecond } + when(state === waitSecond) { + count := io.backendCount + state := reply + } + when(io.response(owner).fire) { state := idle } +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/framework/MemLoader.scala b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/framework/MemLoader.scala new file mode 100644 index 0000000..f9a16c8 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/framework/MemLoader.scala @@ -0,0 +1,236 @@ +package framework.memdomain.frontend.mem + +import chisel3._ +import chisel3.util._ +import framework.memdomain.frontend.cmd.rs.{MemRsComplete, MemRsIssue} +import framework.memdomain.backend.banks.SramWriteIO +import framework.memdomain.frontend.mem.dma.{BBReadRequest, BBReadResponse} +import freechips.rocketchip.rocket.MStatus +import framework.balldomain.blink.BankWrite +import chisel3.experimental.hierarchy.{instantiable, public} +import framework.top.GlobalConfig + +@instantiable +class MemLoader(val b: GlobalConfig) extends Module { + val rob_id_width = log2Up(b.frontend.rob_entries) + + @public + val io = IO(new Bundle { + val cmdReq = Flipped(Decoupled(new MemRsIssue(b))) + val cmdResp = Decoupled(new MemRsComplete(b)) + + val dmaReq = Decoupled(new BBReadRequest()) + val dmaResp = Flipped(Decoupled(new BBReadResponse(b.memDomain.bankWidth))) + + val bankWrite = Flipped(new BankWrite(b)) + + // MMIO routing hint: tells upper level (MemDomain) to route bankWrite to MmioPool + // When is_mvin_mmio_active is true, mmio_addr/col carry MMIO destination info + val is_mvin_mmio_active = Output(Bool()) + val mmio_addr = Output(UInt(17.W)) // rs2[55:39]: MMIO byte address + val mmio_col = Output(UInt(8.W)) // rs2[63:56]: valid bytes per row + + val query_valid = Output(Bool()) + val query_ready = Input(Bool()) + val query_resp_valid = Input(Bool()) + val query_resp_ready = Output(Bool()) + val query_vbank_id = Output(UInt(b.memDomain.vbankIdWidth.W)) + val query_is_shared = Output(Bool()) + val query_group_count = Input(UInt(b.memDomain.groupCountWidth.W)) + + // Propagate decoded shared/private access intent. + val is_shared = Output(Bool()) + }) + + val s_idle :: s_setup :: s_query :: s_query_wait :: s_mul :: s_dma_req :: s_dma_wait :: s_wait_write_resp :: s_done :: Nil = + Enum(9) + val state = RegInit(s_idle) + + val rob_id_reg = RegInit(0.U(rob_id_width.W)) + val is_sub_reg = RegInit(false.B) + val sub_rob_id_reg = RegInit(0.U(log2Up(b.frontend.sub_rob_depth * 4).W)) + val mem_addr_reg = Reg(UInt(b.memDomain.memAddrLen.W)) + val iter_cmd = Reg(UInt(b.frontend.iter_len.W)) + val iter_reg = Reg(UInt(b.frontend.iter_len.W)) + val resp_count = RegInit(0.U(log2Up(16).W)) + val wr_bank_reg = Reg(UInt(b.memDomain.vbankIdWidth.W)) + val stride_reg = Reg(UInt(19.W)) + val is_shared_reg = RegInit(false.B) + + // Group counter for multi-bank writes + val group_counter = RegInit(0.U(b.memDomain.groupCountWidth.W)) + val group_count_reg = RegInit(0.U(b.memDomain.groupCountWidth.W)) + val rowAddr = RegInit(0.U(log2Ceil(b.memDomain.bankEntries).W)) + + // MMIO routing info (latched at cmdReq.fire, exposed to upper level) + val is_mvin_mmio_reg = RegInit(false.B) + val is_mvin_2d_reg = RegInit(false.B) + val valid_bytes_reg = RegInit(16.U(5.W)) + val pixel_bytes_reg = RegInit(0.U(10.W)) + val source_width_reg = RegInit(0.U(10.W)) + val tile_width_reg = RegInit(0.U(4.W)) + val mmio_addr_reg = RegInit(0.U(17.W)) + val mmio_col_reg = RegInit(0.U(8.W)) + + io.is_mvin_mmio_active := is_mvin_mmio_reg + io.mmio_addr := mmio_addr_reg + io.mmio_col := mmio_col_reg + + // ----------------------------- + // pending latch for 1-beat DMA -> bankWrite + // ----------------------------- + val pending = RegInit(false.B) + val latData = Reg(UInt(b.memDomain.bankWidth.W)) + val latLast = RegInit(false.B) + + // ----------------------------- + // defaults + // ----------------------------- + io.cmdReq.ready := (state === s_idle) + + io.dmaReq.valid := (state === s_dma_req) + io.dmaReq.bits.vaddr := mem_addr_reg + io.dmaReq.bits.len := iter_reg * (b.memDomain.bankWidth / 8).U + io.dmaReq.bits.status := 0.U.asTypeOf(new MStatus) + io.dmaReq.bits.stride := stride_reg + io.dmaReq.bits.groups := group_count_reg + io.dmaReq.bits.is_2d := is_mvin_2d_reg + io.dmaReq.bits.pixel_bytes := pixel_bytes_reg + io.dmaReq.bits.source_width := source_width_reg + io.dmaReq.bits.tile_width := tile_width_reg + + // only accept DMA beat when waiting AND no pending beat buffered + io.dmaResp.ready := (state === s_dma_wait) && !pending + + // bank write request driven from pending + io.bankWrite.io.req.valid := pending + io.bankWrite.io.req.bits.addr := rowAddr + + val validDataMask = VecInit( + (0 until b.memDomain.bankWidth / 8).map(i => Mux(i.U < valid_bytes_reg, "hff".U(8.W), 0.U(8.W))) + ).asUInt + + io.bankWrite.io.req.bits.data := Mux(is_mvin_2d_reg, latData & validDataMask, latData) + io.bankWrite.io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(true.B)) + + // IMPORTANT: always ready for write response (avoid deadlock) + io.bankWrite.io.resp.ready := true.B + + io.bankWrite.rob_id := rob_id_reg + io.bankWrite.bank_id := wr_bank_reg + io.bankWrite.ball_id := 0.U + io.bankWrite.group_id := group_counter(b.memDomain.groupIdWidth - 1, 0) + io.is_shared := is_shared_reg + + // cmdResp (Decoupled): hold valid until accepted + io.cmdResp.valid := (state === s_done) + io.cmdResp.bits := 0.U.asTypeOf(new MemRsComplete(b)) + io.cmdResp.bits.rob_id := rob_id_reg + io.cmdResp.bits.is_sub := is_sub_reg + io.cmdResp.bits.sub_rob_id := sub_rob_id_reg + + // ----------------------------- + // Receive load instruction (both mvin and mvin_mmio go through is_load path) + // ----------------------------- + when(io.cmdReq.fire && io.cmdReq.bits.cmd.is_load) { + rob_id_reg := io.cmdReq.bits.rob_id + is_sub_reg := io.cmdReq.bits.is_sub + sub_rob_id_reg := io.cmdReq.bits.sub_rob_id + mem_addr_reg := io.cmdReq.bits.cmd.mem_addr + wr_bank_reg := io.cmdReq.bits.cmd.bank_id + resp_count := 0.U + pending := false.B + latLast := false.B + group_counter := 0.U + rowAddr := Mux( + io.cmdReq.bits.cmd.is_mvin_2d, + io.cmdReq.bits.cmd.special(54, 49), + 0.U + ) + is_shared_reg := io.cmdReq.bits.cmd.is_shared + + is_mvin_mmio_reg := io.cmdReq.bits.cmd.is_mvin_mmio + is_mvin_2d_reg := io.cmdReq.bits.cmd.is_mvin_2d + valid_bytes_reg := Mux(io.cmdReq.bits.cmd.special(61, 58) === 0.U, 16.U, io.cmdReq.bits.cmd.special(61, 58)) + pixel_bytes_reg := io.cmdReq.bits.cmd.special(38, 32) << 3 + source_width_reg := io.cmdReq.bits.cmd.special(48, 39) + tile_width_reg := io.cmdReq.bits.cmd.special(57, 55) +& 1.U + when(io.cmdReq.bits.cmd.is_mvin_mmio) { + mmio_addr_reg := io.cmdReq.bits.cmd.special(55, 39) + mmio_col_reg := io.cmdReq.bits.cmd.special(63, 56) + iter_reg := io.cmdReq.bits.cmd.iter + group_count_reg := 1.U + stride_reg := 1.U + state := s_dma_req + }.elsewhen(io.cmdReq.bits.cmd.is_mvin_2d) { + iter_reg := io.cmdReq.bits.cmd.iter * (io.cmdReq.bits.cmd.special(57, 55) +& 1.U) + group_count_reg := 1.U + stride_reg := 1.U + state := s_dma_req + }.otherwise { + stride_reg := io.cmdReq.bits.cmd.special(57, 39) + iter_cmd := io.cmdReq.bits.cmd.iter + state := s_setup + } + } + + io.query_valid := state === s_setup + io.query_resp_ready := state === s_query_wait + io.query_vbank_id := wr_bank_reg + io.query_is_shared := is_shared_reg && io.query_valid + + when(state === s_setup && io.query_ready) { + state := s_query_wait + } + + when(state === s_query_wait && io.query_resp_valid) { + assert(io.query_group_count >= 1.U, "MemLoader groups must be >= 1") + group_count_reg := io.query_group_count + state := s_mul + } + + when(state === s_mul) { + iter_reg := iter_cmd * group_count_reg + state := s_dma_req + } + + // DMA req accepted + when(io.dmaReq.fire) { + state := s_dma_wait + resp_count := 0.U + } + + // Latch DMA beat into pending buffer + when(io.dmaResp.fire) { + pending := true.B + latData := io.dmaResp.bits.data + latLast := io.dmaResp.bits.last + } + + // When bankWrite request handshakes, consume pending beat + when(io.bankWrite.io.req.fire) { + pending := false.B + resp_count := resp_count + 1.U + + when(latLast) { + state := s_wait_write_resp + }.otherwise { + state := s_wait_write_resp + } + } + + // Wait for each write response before accepting the next DMA beat. + when(state === s_wait_write_resp && io.bankWrite.io.resp.fire) { + when(group_counter + 1.U < group_count_reg) { + group_counter := group_counter + 1.U + }.otherwise { + group_counter := 0.U + rowAddr := rowAddr + 1.U + } + state := Mux(latLast, s_done, s_dma_wait) + } + + when(state === s_done && io.cmdResp.fire) { + state := s_idle + } +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/framework/MemMidend.scala b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/framework/MemMidend.scala new file mode 100644 index 0000000..b62d850 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/framework/MemMidend.scala @@ -0,0 +1,345 @@ +package framework.memdomain.midend + +import chisel3._ +import chisel3.util._ +import framework.top.GlobalConfig +import framework.balldomain.blink.{BankRead, BankWrite} +import chisel3.experimental.hierarchy.{instantiable, public} +import framework.memdomain.backend.MemRequestIO + +// BankRead/BankWrite with is_shared flag, used for unified midend interface +class BankReadWithShared(val b: GlobalConfig) extends Bundle { + val bankRead = new BankRead(b) + val is_shared = Input(Bool()) +} + +class BankWriteWithShared(val b: GlobalConfig) extends Bundle { + val bankWrite = new BankWrite(b) + val is_shared = Input(Bool()) +} + +/** + * MemMidend: Midend module for memory scheduling + * Connects MemFrontend to MemManager + * + * Unified interface: bankRead/bankWrite Vecs include both balldomain and frontend requests. + * The last entry (index totalBallRead / totalBallWrite) is the frontend (DMA). + * All requests go through the same mapping table and channel allocation logic. + */ +@instantiable +class MemMidend(val b: GlobalConfig, fixedRoutes: Boolean = true) extends Module { + val totalBallRead = b.ballDomain.ballIdMappings.map(_.inBW).sum + val totalBallWrite = b.ballDomain.ballIdMappings.map(_.outBW).sum + + // Total slots: balldomain entries + 1 frontend entry + val totalRead = totalBallRead + 1 + val totalWrite = totalBallWrite + 1 + + @public + val io = IO(new Bundle { + // Unified read/write interfaces: indices [0, totalBallRead) are balldomain, + // index totalBallRead is frontend (DMA). Same for write. + val bankRead = Vec(totalRead, new BankReadWithShared(b)) + val bankWrite = Vec(totalWrite, new BankWriteWithShared(b)) + val ballChannelActive = Input(Vec(b.ballDomain.ballNum, Bool())) + val ballChannelReady = Output(Vec(b.ballDomain.ballNum, Bool())) + + val hartid = Input(UInt(b.tile.xLen.W)) + val inst_ids = Input(Vec(b.frontend.rob_entries, UInt(64.W))) + + // Output to backend (MemManager) + val mem_req = Vec(b.memDomain.bankChannel, new MemRequestIO(b)) + }) + + if (fixedRoutes && b.memDomain.bankNum == 8 && + b.ballDomain.ballNum == 1 && !b.memDomain.sharedEnable) { + require(totalBallRead == 2 && totalBallWrite == 4 && b.memDomain.bankChannel == 7) + require(b.ballDomain.ballIdMappings.head.ballName == "GemminiBall") + io.ballChannelReady(0) := io.ballChannelActive(0) + + for (channel <- 0 until 7) { + val request = io.mem_req(channel) + request.read.req.valid := false.B + request.read.req.bits := 0.U.asTypeOf(request.read.req.bits) + request.read.resp.ready := false.B + request.write.req.valid := false.B + request.write.req.bits := 0.U.asTypeOf(request.write.req.bits) + request.write.resp.ready := false.B + request.bank_id := 0.U + request.group_id := 0.U + request.is_shared := false.B + request.hart_id := io.hartid + request.rob_id := 0.U + request.inst_id := 0.U + } + for (port <- 0 until totalBallRead) { + val source = io.bankRead(port) + val request = io.mem_req(port) + request.read <> source.bankRead.io + request.read.req.valid := source.bankRead.io.req.valid && io.ballChannelActive(0) + source.bankRead.io.req.ready := request.read.req.ready && io.ballChannelActive(0) + request.bank_id := source.bankRead.bank_id + request.group_id := source.bankRead.group_id + request.rob_id := source.bankRead.rob_id + request.inst_id := io.inst_ids(source.bankRead.rob_id) + } + for (port <- 0 until totalBallWrite) { + val source = io.bankWrite(port) + val request = io.mem_req(totalBallRead + port) + request.write <> source.bankWrite.io + request.write.req.valid := source.bankWrite.io.req.valid && io.ballChannelActive(0) + source.bankWrite.io.req.ready := request.write.req.ready && io.ballChannelActive(0) + request.bank_id := source.bankWrite.bank_id + request.group_id := source.bankWrite.group_id + request.rob_id := source.bankWrite.rob_id + request.inst_id := io.inst_ids(source.bankWrite.rob_id) + } + + // The private backend captures its bank route BEFORE AccPipe accepts the + // SRAM request. Lock both direction and metadata from selection until the + // response is consumed; a new opposite-direction request must not replace + // the pending route during this one-cycle look-ahead. + val read = io.bankRead(totalBallRead).bankRead + val write = io.bankWrite(totalBallWrite).bankWrite + val dma = io.mem_req(6) + dma.read <> read.io + dma.write <> write.io + val pending = RegInit(false.B) + val accepted = RegInit(false.B) + val writeSelected = RegInit(false.B) + val bank = Reg(UInt(b.memDomain.vbankIdWidth.W)) + val group = Reg(UInt(b.memDomain.groupIdWidth.W)) + val rob = Reg(UInt(log2Up(b.frontend.rob_entries).W)) + when(!pending && (read.io.req.valid || write.io.req.valid)) { + pending := true.B + accepted := false.B + writeSelected := write.io.req.valid + bank := Mux(write.io.req.valid, write.bank_id, read.bank_id) + group := Mux(write.io.req.valid, write.group_id, read.group_id) + rob := Mux(write.io.req.valid, write.rob_id, read.rob_id) + } + dma.read.req.valid := pending && !accepted && !writeSelected && read.io.req.valid + dma.write.req.valid := pending && !accepted && writeSelected && write.io.req.valid + read.io.req.ready := pending && !accepted && !writeSelected && dma.read.req.ready + write.io.req.ready := pending && !accepted && writeSelected && dma.write.req.ready + when(dma.read.req.fire || dma.write.req.fire) { accepted := true.B } + when(dma.read.resp.fire || dma.write.resp.fire) { pending := false.B } + dma.bank_id := bank + dma.group_id := group + dma.rob_id := rob + dma.inst_id := io.inst_ids(dma.rob_id) + assert(!(dma.read.req.fire && dma.write.req.fire)) + } else { + // ----------------------------------------------------------------------------- + // Mapping table for tracking all requests (balldomain + frontend) + // ----------------------------------------------------------------------------- + class MappingTableEntry extends Bundle { + val valid = Bool() + val isRead = Bool() + val id = UInt(log2Ceil(math.max(totalRead, totalWrite)).W) + val isBall = Bool() + val ballId = UInt(log2Up(b.ballDomain.ballNum).W) + } + + val mappingTable = RegInit(VecInit(Seq.fill(b.memDomain.bankChannel)(0.U.asTypeOf(new MappingTableEntry)))) + + // A route stays assigned until its Ball releases it (or a frontend channel + // drains), so maintain the reverse ownership at allocation time. This keeps + // readiness and pending detection from repeatedly scanning every backend + // channel for the same port. + val portSlots = math.max(totalRead, totalWrite) + val readPortAllocated = RegInit(VecInit(Seq.fill(portSlots)(false.B))) + val writePortAllocated = RegInit(VecInit(Seq.fill(portSlots)(false.B))) + + def isAllocated(isRead: Bool, id: UInt): Bool = + Mux(isRead, readPortAllocated(id), writePortAllocated(id)) + + val readPortBall = b.ballDomain.ballIdMappings.zipWithIndex.flatMap { case (mapping, ball) => + Seq.fill(mapping.inBW)(ball) + } + + val writePortBall = b.ballDomain.ballIdMappings.zipWithIndex.flatMap { case (mapping, ball) => + Seq.fill(mapping.outBW)(ball) + } + + for (ball <- 0 until b.ballDomain.ballNum) { + val readReady = readPortBall.zipWithIndex + .filter(_._1 == ball) + .map { case (_, port) => isAllocated(true.B, port.U) } + .foldLeft(true.B)(_ && _) + val writeReady = writePortBall.zipWithIndex + .filter(_._1 == ball) + .map { case (_, port) => isAllocated(false.B, port.U) } + .foldLeft(true.B)(_ && _) + io.ballChannelReady(ball) := io.ballChannelActive(ball) && readReady && writeReady + } + + // Allocate exactly one channel per cycle. Ball channels are allocated before + // their data traffic can start; frontend DMA channels are demand-allocated. + for (i <- 0 until totalRead) { + io.bankRead(i).bankRead.io.req.ready := false.B + io.bankRead(i).bankRead.io.resp.valid := false.B + io.bankRead(i).bankRead.io.resp.bits := DontCare + + } + + for (i <- 0 until totalWrite) { + io.bankWrite(i).bankWrite.io.req.ready := false.B + io.bankWrite(i).bankWrite.io.resp.valid := false.B + io.bankWrite(i).bankWrite.io.resp.bits := DontCare + } + + val pendingReads = VecInit((0 until totalRead).map { i => + val active = + if (i < totalBallRead) { + io.ballChannelActive(readPortBall(i)) + } else { + io.bankRead(i).bankRead.io.req.valid + } + active && !isAllocated(true.B, i.U) + }) + + val pendingWrites = VecInit((0 until totalWrite).map { i => + val active = + if (i < totalBallWrite) { + io.ballChannelActive(writePortBall(i)) + } else { + io.bankWrite(i).bankWrite.io.req.valid + } + active && !isAllocated(false.B, i.U) + }) + + val pending = VecInit(pendingReads ++ pendingWrites) + val freeChannels = mappingTable.map(entry => !entry.valid) + + when(pending.asUInt.orR && freeChannels.reduce(_ || _)) { + val channel = PriorityEncoder(freeChannels) + val port = PriorityEncoder(pending) + mappingTable(channel).valid := true.B + mappingTable(channel).isRead := port < totalRead.U + mappingTable(channel).id := Mux(port < totalRead.U, port, port - totalRead.U) + mappingTable(channel).isBall := Mux( + port < totalRead.U, + MuxLookup(port, false.B)((0 until totalBallRead).map(i => i.U -> true.B).toSeq), + MuxLookup(port - totalRead.U, false.B)((0 until totalBallWrite).map(i => i.U -> true.B).toSeq) + ) + mappingTable(channel).ballId := Mux( + port < totalRead.U, + MuxLookup(port, 0.U)(readPortBall.zipWithIndex.map { case (ball, i) => i.U -> ball.U }.toSeq), + MuxLookup(port - totalRead.U, 0.U)(writePortBall.zipWithIndex.map { case (ball, i) => i.U -> ball.U }.toSeq) + ) + + when(port < totalRead.U) { + readPortAllocated(port) := true.B + }.otherwise { + writePortAllocated(port - totalRead.U) := true.B + } + } + + // Connect mapped entries to backend channels + for (i <- 0 until b.memDomain.bankChannel) { + io.mem_req(i).read.req.valid := false.B + io.mem_req(i).read.req.bits := DontCare + io.mem_req(i).read.resp.ready := false.B + io.mem_req(i).write.req.valid := false.B + io.mem_req(i).write.req.bits := DontCare + io.mem_req(i).write.resp.ready := false.B + io.mem_req(i).bank_id := 0.U + io.mem_req(i).group_id := 0.U + io.mem_req(i).is_shared := false.B + io.mem_req(i).hart_id := io.hartid + io.mem_req(i).rob_id := 0.U + io.mem_req(i).inst_id := 0.U + + val isRead = mappingTable(i).isRead + val rid = mappingTable(i).id + val wid = mappingTable(i).id + val ballRead = io.bankRead(rid).bankRead.io + val ballWrite = io.bankWrite(wid).bankWrite.io + val rbank_id = io.bankRead(rid).bankRead.bank_id + val wbank_id = io.bankWrite(wid).bankWrite.bank_id + val rgroup_id = io.bankRead(rid).bankRead.group_id + val wgroup_id = io.bankWrite(wid).bankWrite.group_id + val r_shared = io.bankRead(rid).is_shared + val w_shared = io.bankWrite(wid).is_shared + val rrob_id = io.bankRead(rid).bankRead.rob_id + val wrob_id = io.bankWrite(wid).bankWrite.rob_id + // A released Ball cannot issue new traffic, but its final bank response + // still needs the existing route until the physical channel drains. + val ballRouteOpen = !mappingTable(i).isBall || + io.ballChannelReady(mappingTable(i).ballId) || + !io.ballChannelActive(mappingTable(i).ballId) + + when(mappingTable(i).valid) { + when(isRead) { + when(ballRouteOpen) { + io.mem_req(i).read <> ballRead + io.mem_req(i).bank_id := rbank_id + io.mem_req(i).group_id := rgroup_id + io.mem_req(i).is_shared := r_shared + io.mem_req(i).rob_id := rrob_id + io.mem_req(i).inst_id := io.inst_ids(rrob_id) + } + }.otherwise { + when(ballRouteOpen) { + io.mem_req(i).write <> ballWrite + io.mem_req(i).bank_id := wbank_id + io.mem_req(i).group_id := wgroup_id + io.mem_req(i).is_shared := w_shared + io.mem_req(i).rob_id := wrob_id + io.mem_req(i).inst_id := io.inst_ids(wrob_id) + } + } + } + } + + // Mapping table release + for (i <- 0 until b.memDomain.bankChannel) { + val releaseCounter = RegInit(0.U(5.W)) + + // Releasing a Ball's logical channel can precede the final bank response. + // Keep its physical route until that response has been consumed; otherwise + // the response loses its consumer and leaves the AccPipe busy. + val ballReleased = mappingTable(i).isBall && + !io.ballChannelActive(mappingTable(i).ballId) + val channelDrained = !(io.mem_req(i).read.resp.valid || + io.mem_req(i).write.resp.valid || io.mem_req(i).read.req.valid || + io.mem_req(i).write.req.valid) + + when(mappingTable(i).valid && ballReleased && channelDrained) { + mappingTable(i).valid := false.B + mappingTable(i).isRead := false.B + mappingTable(i).id := 0.U + mappingTable(i).isBall := false.B + mappingTable(i).ballId := 0.U + when(mappingTable(i).isRead) { + readPortAllocated(mappingTable(i).id) := false.B + }.otherwise { + writePortAllocated(mappingTable(i).id) := false.B + } + releaseCounter := 0.U + }.elsewhen(mappingTable(i).valid && !mappingTable(i).isBall && !(io.mem_req(i).read.resp.valid || + io.mem_req(i).write.resp.valid || io.mem_req(i).read.req.valid || + io.mem_req(i).write.req.valid)) { + releaseCounter := releaseCounter + 1.U + + when(releaseCounter === 16.U) { + releaseCounter := 0.U + mappingTable(i).valid := false.B + mappingTable(i).isRead := false.B + mappingTable(i).id := 0.U + mappingTable(i).isBall := false.B + mappingTable(i).ballId := 0.U + when(mappingTable(i).isRead) { + readPortAllocated(mappingTable(i).id) := false.B + }.otherwise { + writePortAllocated(mappingTable(i).id) := false.B + } + } + }.otherwise { + releaseCounter := 0.U + } + } + + } +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/framework/MemStorer.scala b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/framework/MemStorer.scala new file mode 100644 index 0000000..24af185 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/framework/MemStorer.scala @@ -0,0 +1,271 @@ +package framework.memdomain.frontend.mem + +import chisel3._ +import chisel3.util._ +import framework.top.GlobalConfig +import framework.memdomain.frontend.cmd.rs.{MemRsComplete, MemRsIssue} +import freechips.rocketchip.rocket.MStatus +import framework.memdomain.frontend.mem.dma.{BBWriteRequest, BBWriteResponse} +import framework.balldomain.blink.BankRead +import chisel3.experimental.hierarchy.{instantiable, public} + +@instantiable +class MemStorer(val b: GlobalConfig) extends Module { + val rob_id_width = log2Up(b.frontend.rob_entries) + + // One bank line bytes + private val line_bytes = b.memDomain.bankWidth / 8 + // Pack/send one bank-width aligned beat to DMA. + private val align_bytes = b.memDomain.dma_buswidth / 8 + require(align_bytes == line_bytes, "Bank and DMA beat widths must match") + require(isPow2(line_bytes), "MemStorer line_bytes must be power of 2") + private val lgLine = log2Ceil(line_bytes) + + @public + val io = IO(new Bundle { + val cmdReq = Flipped(Decoupled(new MemRsIssue(b))) + val cmdResp = Decoupled(new MemRsComplete(b)) + + val dmaReq = Decoupled(new BBWriteRequest(b.memDomain.bankWidth)) + val dmaResp = Flipped(Decoupled(new BBWriteResponse)) + + val bankRead = Flipped(new BankRead(b)) + + val query_valid = Output(Bool()) + val query_ready = Input(Bool()) + val query_resp_valid = Input(Bool()) + val query_resp_ready = Output(Bool()) + val query_vbank_id = Output(UInt(b.memDomain.vbankIdWidth.W)) + val query_is_shared = Output(Bool()) + val query_group_count = Input(UInt(b.memDomain.groupCountWidth.W)) + + // Propagate decoded shared/private access intent. + val is_shared = Output(Bool()) + }) + + // ----------------------------- + // State + // ----------------------------- + val s_idle :: s_setup :: s_query :: s_query_wait :: s_mul :: s_issue_sram_req :: s_wait_sram_resp :: s_have_sram_beat :: s_push_dma :: s_wait_dma_resp :: s_done :: Nil = + Enum(11) + val state = RegInit(s_idle) + + val rob_id_reg = RegInit(0.U(rob_id_width.W)) + val is_sub_reg = RegInit(false.B) + val sub_rob_id_reg = RegInit(0.U(log2Up(b.frontend.sub_rob_depth * 4).W)) + val iter_reg = RegInit(0.U(b.frontend.iter_len.W)) + val rd_bank_reg = RegInit(0.U(b.memDomain.vbankIdWidth.W)) + val stride_reg = RegInit(1.U(19.W)) + val group_count_reg = RegInit(1.U(b.memDomain.groupCountWidth.W)) + val is_shared_reg = RegInit(false.B) + + val addr_counter = RegInit(0.U(b.frontend.iter_len.W)) + val group_counter = RegInit(0.U(b.memDomain.groupCountWidth.W)) + val cursor = RegInit(0.U(b.memDomain.memAddrLen.W)) + val rowDelta = RegInit(0.U(b.memDomain.memAddrLen.W)) + + // ----------------------------- + // Pending buffer for SRAM resp + // ----------------------------- + val pending = RegInit(false.B) + val pendData = Reg(UInt(b.memDomain.bankWidth.W)) + val pendIsLast = RegInit(false.B) + + val split_valid = RegInit(false.B) + val split_addr = RegInit(0.U(b.memDomain.memAddrLen.W)) + val split_data = RegInit(0.U((align_bytes * 8).W)) + val split_mask = RegInit(0.U(align_bytes.W)) + + // Convenience + val target_bank = rd_bank_reg + + // ----------------------------- + // Cmd accept + // ----------------------------- + io.cmdReq.ready := (state === s_idle) + + when(io.cmdReq.fire && io.cmdReq.bits.cmd.is_store) { + val strideIn = io.cmdReq.bits.cmd.special(57, 39) + assert(strideIn >= 1.U, "MemStorer stride must be >= 1") + rob_id_reg := io.cmdReq.bits.rob_id + is_sub_reg := io.cmdReq.bits.is_sub + sub_rob_id_reg := io.cmdReq.bits.sub_rob_id + rd_bank_reg := io.cmdReq.bits.cmd.bank_id + stride_reg := strideIn + iter_reg := io.cmdReq.bits.cmd.iter + is_shared_reg := io.cmdReq.bits.cmd.is_shared + + addr_counter := 0.U + group_counter := 0.U + cursor := io.cmdReq.bits.cmd.mem_addr + + pending := false.B + split_valid := false.B + split_addr := 0.U + split_data := 0.U + split_mask := 0.U + + state := s_setup + } + + io.query_valid := state === s_setup + io.query_resp_ready := state === s_query_wait + io.query_vbank_id := rd_bank_reg + io.query_is_shared := is_shared_reg && io.query_valid + + when(state === s_setup && io.query_ready) { + state := s_query_wait + } + + when(state === s_query_wait && io.query_resp_valid) { + assert(io.query_group_count >= 1.U, "MemStorer groups must be >= 1") + group_count_reg := io.query_group_count + state := s_mul + } + + when(state === s_mul) { + rowDelta := ((group_count_reg * (stride_reg - 1.U)) + 1.U) << lgLine + state := s_issue_sram_req + } + + // ----------------------------- + // SRAM read request + // ----------------------------- + io.bankRead.rob_id := rob_id_reg + io.bankRead.bank_id := target_bank + io.bankRead.ball_id := 0.U + io.bankRead.group_id := group_counter(b.memDomain.groupIdWidth - 1, 0) + io.is_shared := is_shared_reg + + io.bankRead.io.req.valid := (state === s_issue_sram_req) + io.bankRead.io.req.bits.addr := addr_counter + + // SRAMBank read resp is a 1-cycle pulse, so we must ALWAYS be ready to take it, + // but only if we don't already hold a pending beat. + io.bankRead.io.resp.ready := !pending + + when(state === s_issue_sram_req) { + // Once request handshakes, wait for resp + when(io.bankRead.io.req.fire) { + state := s_wait_sram_resp + } + } + + // ----------------------------- + // Latch SRAM resp into pending (never drop it) + // ----------------------------- + val bank_resp_fire = io.bankRead.io.resp.fire + when(bank_resp_fire) { + pending := true.B + pendData := io.bankRead.io.resp.bits.data + // Last beat: last row and last group + val is_last_row = addr_counter >= iter_reg - 1.U + val is_last_group = group_counter >= group_count_reg - 1.U + pendIsLast := is_last_row && is_last_group && (iter_reg =/= 0.U) + state := s_have_sram_beat + } + + val addr_offset = cursor(log2Ceil(align_bytes) - 1, 0) + + val aligned_addr = Cat( + cursor(b.memDomain.memAddrLen - 1, log2Ceil(align_bytes)), + 0.U(log2Ceil(align_bytes).W) + ) + + val incoming_data = pendData + val first_bytes = align_bytes.U - addr_offset + val first_mask = (~0.U(align_bytes.W)) << addr_offset + val second_mask = (1.U(align_bytes.W) << addr_offset) - 1.U + + // ----------------------------- + // DMA request (Decoupled correct): hold valid until fire + // ----------------------------- + val dma_v = RegInit(false.B) + val dma_addr = RegInit(0.U(b.memDomain.memAddrLen.W)) + val dma_data = RegInit(0.U((align_bytes * 8).W)) + val dma_mask = RegInit(0.U(align_bytes.W)) + + io.dmaReq.valid := dma_v + io.dmaReq.bits.vaddr := dma_addr + io.dmaReq.bits.data := dma_data + io.dmaReq.bits.len := align_bytes.U + io.dmaReq.bits.mask := dma_mask + io.dmaReq.bits.status := 0.U.asTypeOf(new MStatus) + + io.dmaResp.ready := state === s_wait_dma_resp + + // When we have a pending SRAM beat, prepare one DMA beat (and keep it until fire) + when(state === s_have_sram_beat) { + // Only arm dma_v if not already armed + when(!dma_v) { + dma_v := true.B + dma_addr := aligned_addr + dma_data := Mux(addr_offset === 0.U, incoming_data, incoming_data << (addr_offset * 8.U)) + dma_mask := Mux(addr_offset === 0.U, ~0.U(align_bytes.W), first_mask) + split_valid := addr_offset =/= 0.U + split_addr := aligned_addr + align_bytes.U + split_data := incoming_data >> (first_bytes * 8.U) + split_mask := second_mask + state := s_push_dma + } + } + + // When DMA accepts the beat, consume pending and move forward + when(state === s_push_dma) { + when(io.dmaReq.fire) { + dma_v := false.B + state := s_wait_dma_resp + } + } + + when(state === s_wait_dma_resp && io.dmaResp.fire) { + when(split_valid) { + dma_v := true.B + dma_addr := split_addr + dma_data := split_data + dma_mask := split_mask + split_valid := false.B + state := s_push_dma + }.otherwise { + pending := false.B + + val is_last_row = addr_counter >= iter_reg - 1.U + val is_last_group = group_counter >= group_count_reg - 1.U + val all_done = is_last_row && is_last_group && (iter_reg =/= 0.U) + + when(iter_reg =/= 0.U) { + when(group_counter + 1.U < group_count_reg) { + group_counter := group_counter + 1.U + cursor := cursor + line_bytes.U + }.otherwise { + group_counter := 0.U + addr_counter := addr_counter + 1.U + cursor := cursor + rowDelta + } + } + + when(pendIsLast || iter_reg === 0.U || all_done) { + state := s_done + }.otherwise { + state := s_issue_sram_req + } + } + } + + // If we are waiting for SRAM resp (but resp will pulse), just stay here + when(state === s_wait_sram_resp) { + // nothing; latch happens in bank_resp_fire block above + } + + // ----------------------------- + // Completion + // ----------------------------- + io.cmdResp.valid := (state === s_done) + io.cmdResp.bits.rob_id := rob_id_reg + io.cmdResp.bits.is_sub := is_sub_reg + io.cmdResp.bits.sub_rob_id := sub_rob_id_reg + + when(io.cmdResp.fire) { + state := s_idle + } +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/framework/PrivateMemBackend.scala b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/framework/PrivateMemBackend.scala new file mode 100644 index 0000000..edce8b1 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/framework/PrivateMemBackend.scala @@ -0,0 +1,422 @@ +package framework.memdomain.backend.privatepath + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import framework.memdomain.frontend.mem.MemConfigerIO +import framework.memdomain.backend.{MTraceDPI, MemRequestIO} +import sims.hash.BankHashMonitor +import framework.memdomain.backend.accpipe.AccPipe +import framework.memdomain.backend.banks.SramBank +import framework.memdomain.backend.banks.btrace.PhysicalBankHash +import framework.top.GlobalConfig + +@instantiable +class PrivateMemBackend(val b: GlobalConfig) extends Module { + + @public + val io = IO(new Bundle { + val mem_req = Vec(b.memDomain.bankChannel, Flipped(new MemRequestIO(b))) + val config = Flipped(Decoupled(new MemConfigerIO(b))) + + // Query interface for frontend to get group count + val query_vbank_id = Input(UInt(b.memDomain.vbankIdWidth.W)) + val query_group_count = Output(UInt(b.memDomain.groupCountWidth.W)) + val bank_hashes = if (b.sim.diffTest) Some(Output(Vec(b.memDomain.bankNum, new PhysicalBankHash(b)))) else None + }) + + val banks: Seq[Instance[SramBank]] = Seq.fill(b.memDomain.bankNum)(Instantiate(new SramBank(b))) + val accPipes: Seq[Instance[AccPipe]] = Seq.fill(b.memDomain.bankChannel)(Instantiate(new AccPipe(b))) + + val hashMonitors = + if (b.sim.diffTest) { + Some(Seq.fill(b.memDomain.bankNum)(Instantiate(new BankHashMonitor(b)))) + } else { + None + } + + // Per-channel memory trace DPI-C modules to avoid losing simultaneous events + val mtraces = Seq.fill(b.memDomain.bankChannel)(Module(new MTraceDPI)) + for (mt <- mtraces) { + mt.io.clock := clock + mt.io.reset := reset.asBool + mt.io.is_write := 0.U + mt.io.is_shared := 0.U + mt.io.channel := 0.U + mt.io.hart_id := 0.U + mt.io.rob_id := 0.U + mt.io.inst_id := 0.U + mt.io.vbank_id := 0.U + mt.io.pbank_id := 0.U + mt.io.group_id := 0.U + mt.io.addr := 0.U + mt.io.write_mask := 0.U + mt.io.data_lo := 0.U + mt.io.data_hi := 0.U + mt.io.enable := false.B + } + + // ----------------------------------------------------------------------------- + // Mapping table + // ----------------------------------------------------------------------------- + class MappingTableEntry extends Bundle { + val valid = Bool() + val hart_id = UInt(b.tile.xLen.W) + val vbank_id = UInt(b.memDomain.vbankIdWidth.W) + val is_multi = Bool() + val group_id = UInt(b.memDomain.groupIdWidth.W) + } + + val mappingTable = RegInit(VecInit(Seq.fill(b.memDomain.bankNum)(0.U.asTypeOf(new MappingTableEntry)))) + // The frontend contract reserves [0, vbank_id_upper_bound] for private + // banks. Keep the direct route table at that architectural size. + private val privateVbankCount = b.frontend.vbank_id_upper_bound + 1 + require( + privateVbankCount > 0 && privateVbankCount <= b.memDomain.virtualBankCount, + s"private vbank table size ($privateVbankCount) exceeds virtualBankCount(${b.memDomain.virtualBankCount})" + ) + private val groupIndexWidth = log2Up(b.memDomain.bankNum) + private val pbankIndexWidth = log2Up(b.memDomain.bankNum) + private val privateVbankIdWidth = log2Up(privateVbankCount) + + // A non-multi vbank has exactly one route, so keep that common case as a + // small indexed table. Multi-bank mappings retain their per-group entries + // in mappingTable and use the fallback scan below. This avoids the much + // larger 32x24 valid+pbank register matrix while still removing the full + // mapping scan from the overwhelmingly common single-bank path. + val singleRouteValid = RegInit(VecInit(Seq.fill(privateVbankCount)(false.B))) + + val singleRoutePbank = RegInit( + VecInit(Seq.fill(privateVbankCount)(0.U(pbankIndexWidth.W))) + ) + + // The private namespace is bounded by the frontend contract, while + // multi-bank groups remain represented individually in mappingTable. + val groupCountByVbank = RegInit( + VecInit(Seq.fill(privateVbankCount)(0.U(b.memDomain.groupCountWidth.W))) + ) + + def addEntry( + hart_id: UInt, + vbank_id: UInt, + pbank_id: UInt, + is_multi: Bool, + group_id: UInt + ): Unit = { + val entry = mappingTable(pbank_id) + entry.valid := true.B + entry.hart_id := hart_id + entry.vbank_id := vbank_id + entry.is_multi := is_multi + entry.group_id := group_id + } + + def deleteEntry(vbank_id: UInt): Unit = { + for (i <- 0 until b.memDomain.bankNum) { + when(mappingTable(i).valid && mappingTable(i).vbank_id === vbank_id) { + mappingTable(i).valid := false.B + } + } + } + + // ----------------------------------------------------------------------------- + // Default Value + // ----------------------------------------------------------------------------- + + for (i <- 0 until b.memDomain.bankChannel) { + accPipes(i).io.mem_req.write <> io.mem_req(i).write + accPipes(i).io.mem_req.read <> io.mem_req(i).read + accPipes(i).io.mem_req.bank_id := io.mem_req(i).bank_id + accPipes(i).io.mem_req.group_id := io.mem_req(i).group_id + accPipes(i).io.mem_req.is_shared := io.mem_req(i).is_shared + accPipes(i).io.mem_req.hart_id := io.mem_req(i).hart_id + accPipes(i).io.mem_req.rob_id := io.mem_req(i).rob_id + accPipes(i).io.mem_req.inst_id := io.mem_req(i).inst_id + + // Bank-side defaults (only driven when a bank is actually connected) + accPipes(i).io.sramRead.req.ready := false.B + accPipes(i).io.sramRead.resp.valid := false.B + accPipes(i).io.sramRead.resp.bits := DontCare + + accPipes(i).io.sramWrite.req.ready := false.B + accPipes(i).io.sramWrite.resp.valid := false.B + accPipes(i).io.sramWrite.resp.bits := DontCare + + accPipes(i).io.is_multi := false.B + } + + banks.zipWithIndex.foreach { + case (bank, _) => + bank.io.sramRead.req.valid := false.B + bank.io.sramRead.req.bits := DontCare + bank.io.sramRead.resp.ready := true.B + + bank.io.sramWrite.req.valid := false.B + bank.io.sramWrite.req.bits := DontCare + bank.io.sramWrite.resp.ready := true.B + } + + val realloc = io.config.bits.group_id === 0.U + val freePbankMask = + VecInit(mappingTable.map(entry => !entry.valid || (realloc && entry.vbank_id === io.config.bits.vbank_id))) + val hasFreePbank = freePbankMask.asUInt.orR + io.config.ready := !io.config.bits.alloc || hasFreePbank + when(io.config.valid && io.config.bits.alloc && !hasFreePbank) { + assert(false.B, "PrivateMemBackend allocation failed: no free physical bank\n") + } + + // ----------------------------------------------------------------------------- + // Bank Alloc/Release + // ----------------------------------------------------------------------------- + + hashMonitors.foreach(_.foreach(_.io.bind := false.B)) + + when(io.config.fire) { + val vbank = io.config.bits.vbank_id + val vbankIdx = vbank(privateVbankIdWidth - 1, 0) + when(io.config.bits.alloc) { + val freePbank = PriorityEncoder(freePbankMask) + hashMonitors.foreach { hashes => + for (i <- 0 until b.memDomain.bankNum) { + hashes(i).io.bind := freePbank === i.U + } + } + // Match bemu mset: realloc of the same vbank frees prior physical banks first. + // MemConfiger emits one fire per group; only group 0 drops the old mapping. + when(io.config.bits.group_id === 0.U) { + deleteEntry(io.config.bits.vbank_id) + singleRouteValid(vbankIdx) := false.B + } + addEntry( + io.config.bits.hart_id, + io.config.bits.vbank_id, + freePbank, + io.config.bits.is_multi, + io.config.bits.group_id + ) + when(!io.config.bits.is_multi) { + singleRoutePbank(vbankIdx) := freePbank + singleRouteValid(vbankIdx) := true.B + } + groupCountByVbank(vbankIdx) := Mux(io.config.bits.is_multi, io.config.bits.group_id +& 1.U, 1.U) + }.otherwise { + deleteEntry(io.config.bits.vbank_id) + singleRouteValid(vbankIdx) := false.B + groupCountByVbank(vbankIdx) := 0.U + } + } + + // ----------------------------------------------------------------------------- + // Query interface: return group count for a given vbank_id + // ----------------------------------------------------------------------------- + val queryVbankId = RegNext(io.query_vbank_id, 0.U) + val queryVbank = queryVbankId(privateVbankIdWidth - 1, 0) + io.query_group_count := RegNext(groupCountByVbank(queryVbank), 0.U) + + // ----------------------------------------------------------------------------- + // Connect AccPipe and Banks + // ----------------------------------------------------------------------------- + private def emitTrace( + ch: Int, + isWrite: UInt, + pbankId: UInt, + addr: UInt, + writeMask: UInt, + dataLo: UInt, + dataHi: UInt, + en: Bool + ): Unit = { + mtraces(ch).io.is_write := isWrite + mtraces(ch).io.is_shared := io.mem_req(ch).is_shared.asUInt + mtraces(ch).io.channel := ch.U + mtraces(ch).io.hart_id := io.mem_req(ch).hart_id + mtraces(ch).io.rob_id := io.mem_req(ch).rob_id + mtraces(ch).io.inst_id := io.mem_req(ch).inst_id + mtraces(ch).io.vbank_id := io.mem_req(ch).bank_id + mtraces(ch).io.pbank_id := pbankId + mtraces(ch).io.group_id := io.mem_req(ch).group_id + mtraces(ch).io.addr := addr + mtraces(ch).io.write_mask := writeMask + mtraces(ch).io.data_lo := dataLo + mtraces(ch).io.data_hi := dataHi + mtraces(ch).io.enable := en + } + + // The route is held for the complete AccPipe transaction. Keep the route + // vectors in one place so the bank-side command mux and response demux share + // exactly the same ownership predicate. + val activeRouteOHs = Seq.fill(b.memDomain.bankChannel)(Wire(UInt(b.memDomain.bankNum.W))) + val channelReqValid = Seq.fill(b.memDomain.bankChannel)(Wire(Bool())) + val channelReqIsWrite = Seq.fill(b.memDomain.bankChannel)(Wire(Bool())) + val channelReqAddr = Seq.fill(b.memDomain.bankChannel)(Wire(UInt(log2Ceil(b.memDomain.bankEntries).W))) + val channelReqData = Seq.fill(b.memDomain.bankChannel)(Wire(UInt(b.memDomain.bankWidth.W))) + val channelReqMask = Seq.fill(b.memDomain.bankChannel)(Wire(Vec(b.memDomain.bankMaskLen, Bool()))) + val channelHartId = Seq.fill(b.memDomain.bankChannel)(Wire(UInt(b.tile.xLen.W))) + val channelInstId = Seq.fill(b.memDomain.bankChannel)(Wire(UInt(64.W))) + val channelVbankId = Seq.fill(b.memDomain.bankChannel)(Wire(UInt(b.memDomain.vbankIdWidth.W))) + val channelGroupId = Seq.fill(b.memDomain.bankChannel)(Wire(UInt(b.memDomain.groupIdWidth.W))) + + for (i <- 0 until b.memDomain.bankChannel) { + val routePbankReg = RegInit(0.U(pbankIndexWidth.W)) + val routeValidReg = RegInit(false.B) + val routePending = RegInit(false.B) + val requestVbank = io.mem_req(i).bank_id + val requestVbankIdx = requestVbank(privateVbankIdWidth - 1, 0) + val requestGroup = io.mem_req(i).group_id(groupIndexWidth - 1, 0) + val singleRoute = singleRoutePbank(requestVbankIdx) + val singleValid = singleRouteValid(requestVbankIdx) + val multiRouteMatch = VecInit(mappingTable.map(entry => + entry.valid && entry.is_multi && + entry.vbank_id === requestVbank && entry.group_id === requestGroup + )) + val multiRoute = PriorityEncoder(multiRouteMatch) + val multiValid = multiRouteMatch.asUInt.orR + val requestRoute = Mux(singleValid, singleRoute, multiRoute) + val requestRouteValid = singleValid || multiValid + // Route lookup is deliberately one cycle ahead of the SRAM request. The + // route is captured while the AccPipe is idle, then held through the + // entire request/response lifetime. This removes the live mapping-table + // lookup from every wide bank-side mux select while preserving one request + // per channel per cycle once the pipe is running. + val requestSeen = io.mem_req(i).read.req.valid || io.mem_req(i).write.req.valid + val activeRoute = routePbankReg + val requestActive = routePending || accPipes(i).io.busy + val activeRouteValid = routeValidReg && requestActive + val activeRouteOH = UIntToOH(activeRoute, b.memDomain.bankNum) & + Fill(b.memDomain.bankNum, activeRouteValid) + + activeRouteOHs(i) := activeRouteOH + channelReqValid(i) := accPipes(i).io.sramRead.req.valid || + accPipes(i).io.sramWrite.req.valid + channelReqIsWrite(i) := accPipes(i).io.sramWrite.req.valid + channelReqAddr(i) := Mux( + channelReqIsWrite(i), + accPipes(i).io.sramWrite.req.bits.addr, + accPipes(i).io.sramRead.req.bits.addr + ) + channelReqData(i) := accPipes(i).io.sramWrite.req.bits.data + channelReqMask(i) := accPipes(i).io.sramWrite.req.bits.mask + channelHartId(i) := io.mem_req(i).hart_id + channelInstId(i) := io.mem_req(i).inst_id + channelVbankId(i) := io.mem_req(i).bank_id + channelGroupId(i) := io.mem_req(i).group_id + + // SramBank is a pure single-port SRAM: the selected operation is always + // accepted when its route is active. Using the held route directly avoids + // feeding 24 bank-ready signals back through every channel. + accPipes(i).io.sramRead.req.ready := activeRouteValid + accPipes(i).io.sramWrite.req.ready := activeRouteValid + + when(!routePending && !accPipes(i).io.busy && requestSeen && requestRouteValid) { + routePbankReg := requestRoute + routeValidReg := true.B + routePending := true.B + } + when(io.mem_req(i).read.req.fire || io.mem_req(i).write.req.fire) { + routePending := false.B + } + + // Requests are attributed once the selected SRAM accepts them. + when(accPipes(i).io.sramRead.req.fire) { + emitTrace(i, 0.U, activeRoute, accPipes(i).io.sramRead.req.bits.addr, 0.U, 0.U, 0.U, true.B) + } + + // Arrival trace: the write has crossed arbitration and is accepted by the + // selected SPM SRAM port. Keep attribution metadata from the same AccPipe + // transaction and data from the bank-side request. + when(accPipes(i).io.sramWrite.req.fire) { + emitTrace( + i, + 1.U, + activeRoute, + accPipes(i).io.sramWrite.req.bits.addr, + accPipes(i).io.sramWrite.req.bits.mask.asUInt, + accPipes(i).io.sramWrite.req.bits.data.pad(128)(63, 0), + accPipes(i).io.sramWrite.req.bits.data.pad(128)(127, 64), + true.B + ) + } + + } + + // Bank-side command crossbar. A physical bank is single-port, so both read + // and write requests share one selected channel/address path. The operation + // type then gates the corresponding SRAM request valid. + for (j <- 0 until b.memDomain.bankNum) { + val selectedReq = VecInit((0 until b.memDomain.bankChannel).map { i => + activeRouteOHs(i)(j) && channelReqValid(i) + }).asUInt + val selectedReqValid = selectedReq.orR + // The scheduler guarantees one live owner per physical bank. Express the + // one-hot selection as AND/OR wiring instead of a priority mux tree; this + // keeps the wide address/data path shallow and lets synthesis share the + // route gates across fields. + def oneHotOr(width: Int, values: Seq[UInt]): UInt = + values.zipWithIndex + .map { case (value, i) => Fill(width, selectedReq(i)) & value } + .reduce(_ | _) + + val selectedReqIsWrite = oneHotOr(1, channelReqIsWrite).asBool + val selectedReqAddr = oneHotOr(log2Ceil(b.memDomain.bankEntries), channelReqAddr) + val selectedReqData = oneHotOr(b.memDomain.bankWidth, channelReqData) + val selectedReqMask = VecInit((0 until b.memDomain.bankMaskLen).map { k => + oneHotOr(1, channelReqMask.map(_(k))).asBool + }) + val selectedHartId = oneHotOr(b.tile.xLen, channelHartId) + val selectedInstId = oneHotOr(64, channelInstId) + val selectedVbankId = oneHotOr(b.memDomain.vbankIdWidth, channelVbankId) + val selectedGroupId = oneHotOr(b.memDomain.groupIdWidth, channelGroupId) + + banks(j).io.sramRead.req.valid := selectedReqValid && !selectedReqIsWrite + banks(j).io.sramRead.req.bits.addr := selectedReqAddr + banks(j).io.sramWrite.req.valid := selectedReqValid && selectedReqIsWrite + banks(j).io.sramWrite.req.bits.addr := selectedReqAddr + banks(j).io.sramWrite.req.bits.data := selectedReqData + banks(j).io.sramWrite.req.bits.mask := selectedReqMask + + hashMonitors.foreach { hashes => + val monitor = hashes(j) + monitor.io.write.valid := banks(j).io.sramWrite.req.fire + monitor.io.write.bits.addr := selectedReqAddr + monitor.io.write.bits.mask := selectedReqMask + monitor.io.write.bits.data := selectedReqData + } + + // Only the channel holding this bank can consume its one-cycle response. + banks(j).io.sramRead.resp.ready := VecInit((0 until b.memDomain.bankChannel).map { i => + activeRouteOHs(i)(j) && accPipes(i).io.sramRead.resp.ready + }).asUInt.orR + banks(j).io.sramWrite.resp.ready := VecInit((0 until b.memDomain.bankChannel).map { i => + activeRouteOHs(i)(j) && accPipes(i).io.sramWrite.resp.ready + }).asUInt.orR + } + + // Response demux. Read data remains the only wide bank-to-channel mux; the + // request side above shares its address/data path between read and write. + for (i <- 0 until b.memDomain.bankChannel) { + val readRespSel = VecInit((0 until b.memDomain.bankNum).map { j => + activeRouteOHs(i)(j) && banks(j).io.sramRead.resp.valid + }).asUInt + val writeRespSel = VecInit((0 until b.memDomain.bankNum).map { j => + activeRouteOHs(i)(j) && banks(j).io.sramWrite.resp.valid + }).asUInt + + accPipes(i).io.sramRead.resp.valid := readRespSel.orR + accPipes(i).io.sramRead.resp.bits.data := (0 until b.memDomain.bankNum).map { j => + Fill(b.memDomain.bankWidth, activeRouteOHs(i)(j)) & banks(j).io.sramRead.resp.bits.data + }.reduce(_ | _) + accPipes(i).io.sramWrite.resp.valid := writeRespSel.orR + accPipes(i).io.sramWrite.resp.bits.ok := writeRespSel.orR + } + + io.bank_hashes.foreach { states => + for (i <- 0 until b.memDomain.bankNum) { + states(i).valid := mappingTable(i).valid + states(i).hartId := mappingTable(i).hart_id + states(i).vbankId := mappingTable(i).vbank_id + states(i).pbankId := i.U + states(i).groupId := mappingTable(i).group_id + states(i).statusHash := hashMonitors.get(i).io.statusHash + } + } +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/framework/SubROB.scala b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/framework/SubROB.scala new file mode 100644 index 0000000..178b870 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/framework/SubROB.scala @@ -0,0 +1,200 @@ +package framework.frontend.globalrs + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.hierarchy.{instantiable, public} +import framework.top.GlobalConfig +import framework.balldomain.blink.SubRobRow +import framework.frontend.decoder.PostGDCmd + +@instantiable +class SubROB(val b: GlobalConfig) extends Module { + val subRobDepth = b.frontend.sub_rob_depth + val subIdBits = log2Up(subRobDepth * 4) + val robIdBits = log2Up(b.frontend.rob_entries) + val ballIdBits = log2Up(b.ballDomain.ballNum) + val rowIdBits = log2Up(subRobDepth) + + @public + val io = IO(new Bundle { + // Ball → SubROB: write a row of sub-instructions + val write = Flipped(Decoupled(new SubRobRow(b))) + // SubROB → GlobalRS: issue one slot at a time (PostGDCmd, domain_id determines target) + val issue = Decoupled(new PostGDCmd(b)) + val issueSubId = Output(UInt(subIdBits.W)) + val issueMasterRobId = Output(UInt(robIdBits.W)) + // GlobalRS → SubROB: a sub-instruction completed (sub_rob_id) + val subComplete = Flipped(Decoupled(UInt(subIdBits.W))) + // SubROB → main ROB: all sub-instructions done + val masterComplete = Decoupled(UInt(robIdBits.W)) + // Status + val occupied = Output(Bool()) + val lockedBallId = Output(UInt(ballIdBits.W)) + }) + + // ------------------------------------------------------------------------- + // Storage + // ------------------------------------------------------------------------- + val sram = SyncReadMem(subRobDepth, new SubRobRow(b)) + + val writePtr = RegInit(0.U(rowIdBits.W)) + val readPtr = RegInit(0.U(rowIdBits.W)) + val rowCount = RegInit(0.U((log2Up(subRobDepth) + 1).W)) + val lockedBallId = RegInit(0.U(ballIdBits.W)) + val masterRobId = RegInit(0.U(robIdBits.W)) + + def nextPtr(p: UInt): UInt = Mux(p === (subRobDepth - 1).U, 0.U, p + 1.U) + + val occupied = rowCount > 0.U + val isFull = rowCount === subRobDepth.U + val ballMatch = !occupied || (io.write.bits.ball_id === lockedBallId) + + // Write path: accept if not full AND ball_id matches (or not occupied yet) + io.write.ready := !isFull && ballMatch + + when(io.write.fire) { + when(occupied) { + assert(io.write.bits.master_rob_id === masterRobId, "SubROB row master_rob_id mismatch") + } + sram.write(writePtr, io.write.bits) + writePtr := nextPtr(writePtr) + when(!occupied) { + lockedBallId := io.write.bits.ball_id + masterRobId := io.write.bits.master_rob_id + } + } + + // ------------------------------------------------------------------------- + // FSM + // ------------------------------------------------------------------------- + // States: + // sIdle - nothing to do (rowCount == 0) + // sReadReq - issue SRAM read request for readPtr row + // sReadWait - wait 1 cycle for sramRaw to be latched into sramData + // sReadResp - sramData valid; dispatch valid slots one per cycle + // sWaitSlots - all slots issued; wait for all subCompletes + // sWaitMaster - all rows done; fire masterComplete then return to sIdle + val sIdle :: sReadReq :: sReadWait :: sReadResp :: sWaitSlots :: sWaitMaster :: Nil = Enum(6) + val state = RegInit(sIdle) + + // SyncReadMem: read issued in sReadReq (cycle N), data valid on cycle N+1. + // We latch it into sramData with RegEnable so it stays stable during sReadResp + // and sWaitSlots, even when the read port is not enabled. + val sramReadEn = state === sReadReq + val sramRaw = sram.read(readPtr, sramReadEn) + val dataFresh = RegNext(sramReadEn, false.B) // pulse on first cycle of sReadResp + val sramData = RegEnable(sramRaw, dataFresh) + val readPtrReg = RegEnable(readPtr, sramReadEn) + + // Per-row tracking registers (reset when moving to next row) + // slotIssued: have we already sent this slot to a domain? + // slotDone: have we received subComplete for this slot? + val slotIssued = RegInit(VecInit(Seq.fill(4)(false.B))) + val slotDone = RegInit(VecInit(Seq.fill(4)(false.B))) + + // Combinational: which slots still need to be issued? + val slotNeedsIssue = VecInit((0 until 4).map(i => sramData.slots(i).valid && !slotIssued(i))) + val hasSlotToIssue = slotNeedsIssue.asUInt.orR + val firstSlotIdx = PriorityEncoder(slotNeedsIssue.asUInt) + + // Combinational: are all valid slots done? + val allSlotsDone = VecInit((0 until 4).map(i => !sramData.slots(i).valid || slotDone(i))).asUInt.andR + + // Issue output (valid only in sReadResp when there's a slot to issue) + io.issue.valid := (state === sReadResp) && hasSlotToIssue + io.issue.bits := sramData.slots(firstSlotIdx).cmd + io.issueSubId := readPtrReg * 4.U + firstSlotIdx + io.issueMasterRobId := masterRobId + + // subComplete: always ready, mark the corresponding slot done + io.subComplete.ready := true.B + when(io.subComplete.fire) { + val subId = io.subComplete.bits + val subRow = subId / 4.U + val slotIdx = subId(1, 0) + assert( + state === sReadResp || state === sWaitSlots || state === sWaitMaster, + "SubROB subComplete arrived in invalid state" + ) + assert(subRow === readPtrReg, "SubROB subComplete points to non-active row") + slotDone(slotIdx) := true.B + } + + // masterComplete + io.masterComplete.valid := state === sWaitMaster + io.masterComplete.bits := masterRobId + + // Status outputs + io.occupied := occupied + io.lockedBallId := lockedBallId + + // ------------------------------------------------------------------------- + // FSM transitions + // ------------------------------------------------------------------------- + // Helper: advance past current row (called when row is complete) + val retireRow = WireDefault(false.B) + def advanceRow(): Unit = { + readPtr := nextPtr(readPtr) + retireRow := true.B + slotIssued.foreach(_ := false.B) + slotDone.foreach(_ := false.B) + } + + switch(state) { + is(sIdle) { + when(occupied)(state := sReadReq) + } + is(sReadReq) { + // SRAM read issued, data available on sramRaw next cycle + state := sReadWait + } + is(sReadWait) { + // sramRaw is valid; RegEnable latches it into sramData at this clock edge. + // sramData will be stable starting next cycle (sReadResp). + state := sReadResp + } + is(sReadResp) { + // Fire issued slot + when(io.issue.fire) { + slotIssued(firstSlotIdx) := true.B + } + // Check if all slots have been issued + // After marking current slot issued, recalculate + val allIssued = VecInit((0 until 4).map(i => + !sramData.slots(i).valid || slotIssued(i) || + (io.issue.fire && firstSlotIdx === i.U) + )).asUInt.andR + + when(allIssued) { + // Check fast path: all already done (e.g., empty row or immediate completion) + val allDoneNow = VecInit((0 until 4).map(i => !sramData.slots(i).valid || slotDone(i))).asUInt.andR + when(allDoneNow) { + // Fast path: skip sWaitSlots + advanceRow() + state := Mux(rowCount === 1.U && !io.write.fire, sWaitMaster, sReadReq) + }.otherwise { + state := sWaitSlots + } + } + // else: stay in sReadResp to dispatch remaining slots + } + is(sWaitSlots) { + when(allSlotsDone) { + advanceRow() + state := Mux(rowCount === 1.U && !io.write.fire, sWaitMaster, sReadReq) + } + } + is(sWaitMaster) { + when(io.masterComplete.fire) { + lockedBallId := 0.U + masterRobId := 0.U + state := sIdle + } + } + } + + // A simultaneous row write and retirement leave occupancy unchanged. + when(io.write.fire =/= retireRow) { + rowCount := Mux(io.write.fire, rowCount + 1.U, rowCount - 1.U) + } +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/gemmini/FpgaArithmetic.scala b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/gemmini/FpgaArithmetic.scala new file mode 100644 index 0000000..e5d389d --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/gemmini/FpgaArithmetic.scala @@ -0,0 +1,40 @@ +package gemmini + +import chisel3._ +import chisel3.util._ + +/** Signed round-to-nearest-even. Two low bits carry guard and sticky state. */ +object FpgaRoundShift { + def apply(value: SInt, amount: UInt): SInt = { + require(Set(20, 32)(value.getWidth) && amount.getWidth == 5) + val width = value.getWidth + 2 + var stage = Cat(value.asUInt, 0.U(2.W)) + for (bit <- 0 until amount.getWidth) { + val distance = 1 << bit + val shifted = (stage.asSInt >> distance).pad(width).asUInt + val jammed = Cat(shifted(width - 1, 1), shifted(0) || stage(distance - 1, 0).orR) + stage = Mux(amount(bit), jammed, stage) + } + val integer = stage(width - 1, 2).asSInt + val increment = stage(1) && (stage(0) || stage(2)) + // Rounding a right shift cannot overflow the original signed input range. + (integer + Mux(increment, 1.S(value.getWidth.W), 0.S(value.getWidth.W))).asSInt + } +} + +/** No added registers: preserves the original PE cycle interface. */ +class FpgaDspMac extends BlackBox with HasBlackBoxInline { + val io = IO(new Bundle { + val a = Input(UInt(8.W)) + val b = Input(UInt(8.W)) + val c = Input(UInt(20.W)) + val y = Output(UInt(20.W)) + }) + setInline("FpgaDspMac.v", """ +module FpgaDspMac(input [7:0] a, b, input [19:0] c, output [19:0] y); + (* use_dsp = "yes" *) wire signed [19:0] result; + assign result = $signed(a) * $signed(b) + $signed(c); + assign y = result; +endmodule +""") +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/gemmini/LICENSE b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/gemmini/LICENSE new file mode 100644 index 0000000..17824de --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/gemmini/LICENSE @@ -0,0 +1,24 @@ +Copyright (c) 2018-2019, The Regents of the University of California +(Regents). All Rights Reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the Regents nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, +SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING +OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS +BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED +HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE +MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/gemmini/Mesh.scala b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/gemmini/Mesh.scala new file mode 100644 index 0000000..51c4950 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/gemmini/Mesh.scala @@ -0,0 +1,134 @@ + +package gemmini + +import chisel3._ +import chisel3.util._ +import chisel3.experimental._ + +/** + * A Grid is a 2D array of Tile modules with registers in between each tile and + * registers from the bottom row and rightmost column of tiles to the Grid outputs. + * @param width + * @param tileRows + * @param tileColumns + * @param meshRows + * @param meshColumns + */ +class Mesh[T <: Data : Arithmetic](inputType: T, weightType: T, outputType: T, accType: T, + df: Dataflow.Value, tree_reduction: Boolean, tile_latency: Int, + max_simultaneous_matmuls: Int, output_delay: Int, + val tileRows: Int, val tileColumns: Int, + val meshRows: Int, val meshColumns: Int) extends Module { + val io = IO(new Bundle { + val in_a = Input(Vec(meshRows, Vec(tileRows, inputType))) + val in_b = Input(Vec(meshColumns, Vec(tileColumns, weightType))) + val in_d = Input(Vec(meshColumns, Vec(tileColumns, weightType))) // TODO should this be weightType, inputType, or something like max(inputType, weightType)? + val in_control = Input(Vec(meshColumns, Vec(tileColumns, new PEControl(accType)))) + val in_id = Input(Vec(meshColumns, Vec(tileColumns, UInt(log2Up(max_simultaneous_matmuls).W)))) // The unique id of this particular matmul + val in_last = Input(Vec(meshColumns, Vec(tileColumns, Bool()))) + val out_b = Output(Vec(meshColumns, Vec(tileColumns, outputType))) + val out_c = Output(Vec(meshColumns, Vec(tileColumns, outputType))) + val in_valid = Input(Vec(meshColumns, Vec(tileColumns, Bool()))) + val out_valid = Output(Vec(meshColumns, Vec(tileColumns, Bool()))) + val out_control = Output(Vec(meshColumns, Vec(tileColumns, new PEControl(accType)))) + val out_id = Output(Vec(meshColumns, Vec(tileColumns, UInt(log2Up(max_simultaneous_matmuls).W)))) + val out_last = Output(Vec(meshColumns, Vec(tileColumns, Bool()))) + }) + + // mesh(r)(c) => Tile at row r, column c + val mesh: Seq[Seq[Tile[T]]] = Seq.tabulate(meshRows, meshColumns) { (r, c) => + // Use one DSP MAC per PE in this 8x8 FPGA profile; retain OS/WS timing. + Module(new Tile(inputType, weightType, outputType, accType, df, + tree_reduction, max_simultaneous_matmuls, tileRows, tileColumns, + fpgaDsp = true)) + } + val meshT = mesh.transpose + + def pipe[T <: Data](valid: Bool, t: T, latency: Int): T = { + // The default "Pipe" function apparently resets the valid signals to false.B. We would like to avoid using global + // signals in the Mesh, so over here, we make it clear that the reset signal will never be asserted + chisel3.withReset(false.B) { Pipe(valid, t, latency).bits } + } + + // Chain tile_a_out -> tile_a_in (pipeline a across each row) + // TODO clock-gate A signals with in_garbage + for (r <- 0 until meshRows) { + mesh(r).foldLeft(io.in_a(r)) { + case (in_a, tile) => + tile.io.in_a := ShiftRegister(in_a, tile_latency+1) + tile.io.out_a + } + } + + // Chain tile_out_b -> tile_b_in (pipeline b across each column) + for (c <- 0 until meshColumns) { + meshT(c).foldLeft((io.in_b(c), io.in_valid(c))) { + case ((in_b, valid), tile) => + tile.io.in_b := pipe(valid.head, in_b, tile_latency+1) + (tile.io.out_b, tile.io.out_valid) + } + } + + // Chain tile_out -> tile_propag (pipeline output across each column) + for (c <- 0 until meshColumns) { + meshT(c).foldLeft((io.in_d(c), io.in_valid(c))) { + case ((in_propag, valid), tile) => + tile.io.in_d := pipe(valid.head, in_propag, tile_latency+1) + (tile.io.out_c, tile.io.out_valid) + } + } + + // Chain control signals (pipeline across each column) + assert(!(mesh.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_))) + for (c <- 0 until meshColumns) { + meshT(c).foldLeft((io.in_control(c), io.in_valid(c))) { + case ((in_ctrl, valid), tile) => + (tile.io.in_control, in_ctrl, valid).zipped.foreach { case (tile_ctrl, ctrl, v) => + tile_ctrl.shift := pipe(v, ctrl.shift, tile_latency+1) + tile_ctrl.dataflow := pipe(v, ctrl.dataflow, tile_latency+1) + tile_ctrl.propagate := pipe(v, ctrl.propagate, tile_latency+1) + } + (tile.io.out_control, tile.io.out_valid) + } + } + + // Chain in_valid (pipeline across each column) + for (c <- 0 until meshColumns) { + meshT(c).foldLeft(io.in_valid(c)) { + case (in_v, tile) => + tile.io.in_valid := ShiftRegister(in_v, tile_latency+1) + tile.io.out_valid + } + } + + // Chain in_id (pipeline across each column) + for (c <- 0 until meshColumns) { + meshT(c).foldLeft(io.in_id(c)) { + case (in_id, tile) => + tile.io.in_id := ShiftRegister(in_id, tile_latency+1) + tile.io.out_id + } + } + + // Chain in_last (pipeline across each column) + for (c <- 0 until meshColumns) { + meshT(c).foldLeft(io.in_last(c)) { + case (in_last, tile) => + tile.io.in_last := ShiftRegister(in_last, tile_latency+1) + tile.io.out_last + } + } + + // Capture out_vec and out_control_vec (connect IO to bottom row of mesh) + // (The only reason we have so many zips is because Scala doesn't provide a zipped function for Tuple4) + for (((((((b, c), v), ctrl), id), last), tile) <- io.out_b zip io.out_c zip io.out_valid zip io.out_control zip io.out_id zip io.out_last zip mesh.last) { + // TODO we pipelined this to make physical design easier. Consider removing these if possible + // TODO shouldn't we clock-gate these signals with "garbage" as well? + b := ShiftRegister(tile.io.out_b, output_delay) + c := ShiftRegister(tile.io.out_c, output_delay) + v := ShiftRegister(tile.io.out_valid, output_delay) + ctrl := ShiftRegister(tile.io.out_control, output_delay) + id := ShiftRegister(tile.io.out_id, output_delay) + last := ShiftRegister(tile.io.out_last, output_delay) + } +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/gemmini/PE.scala b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/gemmini/PE.scala new file mode 100644 index 0000000..1a71132 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/gemmini/PE.scala @@ -0,0 +1,162 @@ +// See README.md for license details. +package gemmini + +import chisel3._ +import chisel3.util._ + +class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { + val dataflow = UInt(1.W) // TODO make this an Enum + val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? + val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats + +} + +class MacUnit[T <: Data](inputType: T, weightType: T, cType: T, dType: T, fpgaDsp: Boolean = false) (implicit ev: Arithmetic[T]) extends Module { + import ev._ + val io = IO(new Bundle { + val in_a = Input(inputType) + val in_b = Input(weightType) + val in_c = Input(cType) + val out_d = Output(dType) + }) + + if (fpgaDsp) { + require(inputType.getWidth == 8 && weightType.getWidth == 8 && dType.getWidth == 20) + val mac = Module(new FpgaDspMac) + mac.io.a := io.in_a.asUInt + mac.io.b := io.in_b.asUInt + mac.io.c := io.in_c.asUInt + io.out_d := mac.io.y.asTypeOf(dType) + } else io.out_d := io.in_c.mac(io.in_a, io.in_b) +} + +// TODO update documentation +/** + * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. + * @param width Data width of operands + */ +class PE[T <: Data](inputType: T, weightType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int, fpgaDsp: Boolean = false) + (implicit ev: Arithmetic[T]) extends Module { // Debugging variables + import ev._ + + val io = IO(new Bundle { + val in_a = Input(inputType) + val in_b = Input(outputType) + val in_d = Input(outputType) + val out_a = Output(inputType) + val out_b = Output(outputType) + val out_c = Output(outputType) + + val in_control = Input(new PEControl(accType)) + val out_control = Output(new PEControl(accType)) + + val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) + val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) + + val in_last = Input(Bool()) + val out_last = Output(Bool()) + + val in_valid = Input(Bool()) + val out_valid = Output(Bool()) + + val bad_dataflow = Output(Bool()) + }) + + require(inputType.isInstanceOf[SInt] && inputType.getWidth == 8 && + weightType.getWidth == 8 && outputType.getWidth == 20 && accType.getWidth == 32 && + df == Dataflow.BOTH, "FPGA PE specialization is for the pinned Toy profile") + // Every state update comes from the 20-bit MAC result or 20-bit input d. + // Keep that exact representation; the original 32-bit state is sign extension. + val cType = outputType + + // When creating PEs that support multiple dataflows, the + // elaboration/synthesis tools often fail to consolidate and de-duplicate + // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" + // module here which just performs a single MAC operation + val mac_unit = Module(new MacUnit(inputType, weightType, + cType, outputType, fpgaDsp)) + + val a = io.in_a + val b = io.in_b + val d = io.in_d + val c1 = Reg(cType) + val c2 = Reg(cType) + val dataflow = io.in_control.dataflow + val prop = io.in_control.propagate + val shift = io.in_control.shift + val id = io.in_id + val last = io.in_last + val valid = io.in_valid + + io.out_a := a + io.out_control.dataflow := dataflow + io.out_control.propagate := prop + io.out_control.shift := shift + io.out_id := id + io.out_last := last + io.out_valid := valid + + mac_unit.io.in_a := a + + val last_s = RegEnable(prop, valid) + val flip = last_s =/= prop + val shift_offset = Mux(flip, shift, 0.U) + // Select before rounding: both branches previously duplicated a full quantizer. + val propagated = Mux(prop === 1.U, c1, c2) + val rounded = FpgaRoundShift(propagated.asUInt.asSInt, shift_offset).asTypeOf(outputType) + + // Which dataflow are we using? + val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) + val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) + + // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? + val COMPUTE = 0.U(1.W) + val PROPAGATE = 1.U(1.W) + + io.bad_dataflow := false.B + when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { + when(prop === PROPAGATE) { + io.out_c := rounded + io.out_b := b + mac_unit.io.in_b := b.asTypeOf(weightType) + mac_unit.io.in_c := c2 + c2 := mac_unit.io.out_d + c1 := d.withWidthOf(cType) + }.otherwise { + io.out_c := rounded + io.out_b := b + mac_unit.io.in_b := b.asTypeOf(weightType) + mac_unit.io.in_c := c1 + c1 := mac_unit.io.out_d + c2 := d.withWidthOf(cType) + } + }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { + when(prop === PROPAGATE) { + io.out_c := c1 + mac_unit.io.in_b := c2.asTypeOf(weightType) + mac_unit.io.in_c := b + io.out_b := mac_unit.io.out_d + c1 := d + }.otherwise { + io.out_c := c2 + mac_unit.io.in_b := c1.asTypeOf(weightType) + mac_unit.io.in_c := b + io.out_b := mac_unit.io.out_d + c2 := d + } + }.otherwise { + io.bad_dataflow := true.B + //assert(false.B, "unknown dataflow") + io.out_c := DontCare + io.out_b := DontCare + mac_unit.io.in_b := b.asTypeOf(weightType) + mac_unit.io.in_c := c2 + } + + when (!valid) { + c1 := c1 + c2 := c2 + mac_unit.io.in_b := DontCare + mac_unit.io.in_c := DontCare + } +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/gemmini/Tile.scala b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/gemmini/Tile.scala new file mode 100644 index 0000000..135ae95 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/gemmini/Tile.scala @@ -0,0 +1,132 @@ +// See README.md for license details. + +package gemmini + +import chisel3._ +import chisel3.util._ +import Util._ + +/** + * A Tile is a purely combinational 2D array of passThrough PEs. + * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs + * @param width The data width of each PE in bits + * @param rows Number of PEs on each row + * @param columns Number of PEs on each column + */ +class Tile[T <: Data](inputType: T, weightType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int, fpgaDsp: Boolean = false)(implicit ev: Arithmetic[T]) extends Module { + val io = IO(new Bundle { + val in_a = Input(Vec(rows, inputType)) + val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it + val in_d = Input(Vec(columns, outputType)) + + val in_control = Input(Vec(columns, new PEControl(accType))) + val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) + val in_last = Input(Vec(columns, Bool())) + + val out_a = Output(Vec(rows, inputType)) + val out_c = Output(Vec(columns, outputType)) + val out_b = Output(Vec(columns, outputType)) + + val out_control = Output(Vec(columns, new PEControl(accType))) + val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) + val out_last = Output(Vec(columns, Bool())) + + val in_valid = Input(Vec(columns, Bool())) + val out_valid = Output(Vec(columns, Bool())) + + val bad_dataflow = Output(Bool()) + }) + + import ev._ + + val tile = Seq.fill(rows, columns)(Module(new PE(inputType, weightType, outputType, accType, df, max_simultaneous_matmuls, fpgaDsp))) + val tileT = tile.transpose + + // TODO: abstract hori/vert broadcast, all these connections look the same + // Broadcast 'a' horizontally across the Tile + for (r <- 0 until rows) { + tile(r).foldLeft(io.in_a(r)) { + case (in_a, pe) => + pe.io.in_a := in_a + pe.io.out_a + } + } + + // Broadcast 'b' vertically across the Tile + for (c <- 0 until columns) { + tileT(c).foldLeft(io.in_b(c)) { + case (in_b, pe) => + pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) + pe.io.out_b + } + } + + // Broadcast 'd' vertically across the Tile + for (c <- 0 until columns) { + tileT(c).foldLeft(io.in_d(c)) { + case (in_d, pe) => + pe.io.in_d := in_d + pe.io.out_c + } + } + + // Broadcast 'control' vertically across the Tile + for (c <- 0 until columns) { + tileT(c).foldLeft(io.in_control(c)) { + case (in_ctrl, pe) => + pe.io.in_control := in_ctrl + pe.io.out_control + } + } + + // Broadcast 'garbage' vertically across the Tile + for (c <- 0 until columns) { + tileT(c).foldLeft(io.in_valid(c)) { + case (v, pe) => + pe.io.in_valid := v + pe.io.out_valid + } + } + + // Broadcast 'id' vertically across the Tile + for (c <- 0 until columns) { + tileT(c).foldLeft(io.in_id(c)) { + case (id, pe) => + pe.io.in_id := id + pe.io.out_id + } + } + + // Broadcast 'last' vertically across the Tile + for (c <- 0 until columns) { + tileT(c).foldLeft(io.in_last(c)) { + case (last, pe) => + pe.io.in_last := last + pe.io.out_last + } + } + + // Drive the Tile's bottom IO + for (c <- 0 until columns) { + io.out_c(c) := tile(rows-1)(c).io.out_c + io.out_control(c) := tile(rows-1)(c).io.out_control + io.out_id(c) := tile(rows-1)(c).io.out_id + io.out_last(c) := tile(rows-1)(c).io.out_last + io.out_valid(c) := tile(rows-1)(c).io.out_valid + + io.out_b(c) := { + if (tree_reduction) { + val prods = tileT(c).map(_.io.out_b) + accumulateTree(prods :+ io.in_b(c)) + } else { + tile(rows - 1)(c).io.out_b + } + } + } + io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_) + + // Drive the Tile's right IO + for (r <- 0 until rows) { + io.out_a(r) := tile(r)(columns-1).io.out_a + } +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/rocket/FPU.scala b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/rocket/FPU.scala new file mode 100644 index 0000000..c1eca79 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/rocket/FPU.scala @@ -0,0 +1,1220 @@ +// See LICENSE.Berkeley for license details. +// See LICENSE.SiFive for license details. + +package freechips.rocketchip.tile + +import chisel3._ +import chisel3.util._ +import chisel3.{DontCare, WireInit, withClock, withReset} +import chisel3.experimental.SourceInfo +import chisel3.experimental.dataview._ +import org.chipsalliance.cde.config.{Parameters, Field} +import freechips.rocketchip.rocket._ +import freechips.rocketchip.rocket.Instructions._ +import freechips.rocketchip.util._ +import freechips.rocketchip.util.property + +case object FpgaSharedFma extends Field[Boolean](false) + +case class FPUParams( + minFLen: Int = 32, + fLen: Int = 64, + divSqrt: Boolean = true, + sfmaLatency: Int = 5, + dfmaLatency: Int = 6, + fpmuLatency: Int = 2, + ifpuLatency: Int = 4 +) + +object FPConstants +{ + val RM_SZ = 3 + val FLAGS_SZ = 5 +} + +trait HasFPUCtrlSigs { + val ldst = Bool() + val wen = Bool() + val ren1 = Bool() + val ren2 = Bool() + val ren3 = Bool() + val swap12 = Bool() + val swap23 = Bool() + val typeTagIn = UInt(2.W) + val typeTagOut = UInt(2.W) + val fromint = Bool() + val toint = Bool() + val fastpipe = Bool() + val fma = Bool() + val div = Bool() + val sqrt = Bool() + val wflags = Bool() + val vec = Bool() +} + +class FPUCtrlSigs extends Bundle with HasFPUCtrlSigs + +class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) { + val io = IO(new Bundle { + val inst = Input(Bits(32.W)) + val sigs = Output(new FPUCtrlSigs()) + }) + + private val X2 = BitPat.dontCare(2) + + val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N) + val h: Array[(BitPat, List[BitPat])] = + Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), + FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N), + FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N), + FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), + FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), + FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), + FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), + FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N), + FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N), + FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), + FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), + FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), + FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), + FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N), + FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N), + FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), + FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), + FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), + FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), + FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), + FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), + FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), + FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), + FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), + FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), + FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N), + FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), + FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), + FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), + FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), + FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N), + FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N)) + val f: Array[(BitPat, List[BitPat])] = + Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), + FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N), + FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N), + FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), + FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), + FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), + FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), + FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N), + FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N), + FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), + FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), + FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), + FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), + FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), + FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), + FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), + FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), + FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), + FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), + FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), + FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), + FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), + FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), + FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N), + FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), + FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), + FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), + FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), + FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N), + FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N)) + val d: Array[(BitPat, List[BitPat])] = + Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), + FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N), + FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N), + FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), + FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), + FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), + FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), + FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N), + FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N), + FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), + FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), + FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), + FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), + FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N), + FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N), + FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), + FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), + FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), + FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), + FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), + FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), + FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), + FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), + FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), + FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), + FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N), + FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), + FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), + FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), + FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), + FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N), + FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N)) + val fcvt_hd: Array[(BitPat, List[BitPat])] = + Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N), + FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N)) + val vfmv_f_s: Array[(BitPat, List[BitPat])] = + Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y)) + + val insns = ((minFLen, fLen) match { + case (32, 32) => f + case (16, 32) => h ++ f + case (32, 64) => f ++ d + case (16, 64) => h ++ f ++ d ++ fcvt_hd + case other => throw new Exception(s"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration") + }) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]()) + val decoder = DecodeLogic(io.inst, default, insns) + val s = io.sigs + val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12, + s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint, + s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec) + sigs zip decoder map {case(s,d) => s := d} +} + +class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) { + val hartid = Input(UInt(hartIdLen.W)) + val time = Input(UInt(xLen.W)) + + val inst = Input(Bits(32.W)) + val fromint_data = Input(Bits(xLen.W)) + + val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W)) + val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W)) + + val v_sew = Input(UInt(3.W)) + + val store_data = Output(Bits(fLen.W)) + val toint_data = Output(Bits(xLen.W)) + + val ll_resp_val = Input(Bool()) + val ll_resp_type = Input(Bits(3.W)) + val ll_resp_tag = Input(UInt(5.W)) + val ll_resp_data = Input(Bits(fLen.W)) + + val valid = Input(Bool()) + val fcsr_rdy = Output(Bool()) + val nack_mem = Output(Bool()) + val illegal_rm = Output(Bool()) + val killx = Input(Bool()) + val killm = Input(Bool()) + val dec = Output(new FPUCtrlSigs()) + val sboard_set = Output(Bool()) + val sboard_clr = Output(Bool()) + val sboard_clra = Output(UInt(5.W)) + + val keep_clock_enabled = Input(Bool()) +} + +class FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) { + val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs + val cp_resp = Decoupled(new FPResult()) +} + +class FPResult(implicit p: Parameters) extends CoreBundle()(p) { + val data = Bits((fLen+1).W) + val exc = Bits(FPConstants.FLAGS_SZ.W) +} + +class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { + val rm = Bits(FPConstants.RM_SZ.W) + val typ = Bits(2.W) + val in1 = Bits(xLen.W) +} + +class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { + val rm = Bits(FPConstants.RM_SZ.W) + val fmaCmd = Bits(2.W) + val typ = Bits(2.W) + val fmt = Bits(2.W) + val in1 = Bits((fLen+1).W) + val in2 = Bits((fLen+1).W) + val in3 = Bits((fLen+1).W) + +} + +case class FType(exp: Int, sig: Int) { + def ieeeWidth = exp + sig + def recodedWidth = ieeeWidth + 1 + + def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W) + def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W) + def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR + def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2) + + def classify(x: UInt) = { + val sign = x(sig + exp) + val code = x(exp + sig - 1, exp + sig - 3) + val codeHi = code(2, 1) + val isSpecial = codeHi === 3.U + + val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U + val isSubnormal = code === 1.U || codeHi === 1.U && isHighSubnormalIn + val isNormal = codeHi === 1.U && !isHighSubnormalIn || codeHi === 2.U + val isZero = code === 0.U + val isInf = isSpecial && !code(0) + val isNaN = code.andR + val isSNaN = isNaN && !x(sig-2) + val isQNaN = isNaN && x(sig-2) + + Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign, + isSubnormal && !sign, isZero && !sign, isZero && sign, + isSubnormal && sign, isNormal && sign, isInf && sign) + } + + // convert between formats, ignoring rounding, range, NaN + def unsafeConvert(x: UInt, to: FType) = if (this == to) x else { + val sign = x(sig + exp) + val fractIn = x(sig - 2, 0) + val expIn = x(sig + exp - 1, sig - 1) + val fractOut = fractIn << to.sig >> sig + val expOut = { + val expCode = expIn(exp, exp - 2) + val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U + Mux(expCode === 0.U || expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0)) + } + Cat(sign, expOut, fractOut) + } + + private def ieeeBundle = { + val expWidth = exp + class IEEEBundle extends Bundle { + val sign = Bool() + val exp = UInt(expWidth.W) + val sig = UInt((ieeeWidth-expWidth-1).W) + } + new IEEEBundle + } + + def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle) + + def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x) + def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x) +} + +object FType { + val H = new FType(5, 11) + val S = new FType(8, 24) + val D = new FType(11, 53) + + val all = List(H, S, D) +} + +trait HasFPUParameters { + require(fLen == 0 || FType.all.exists(_.ieeeWidth == fLen)) + val minFLen: Int + val fLen: Int + def xLen: Int + val minXLen = 32 + val nIntTypes = log2Ceil(xLen/minXLen) + 1 + def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen) + def minType = floatTypes.head + def maxType = floatTypes.last + def prevType(t: FType) = floatTypes(typeTag(t) - 1) + def maxExpWidth = maxType.exp + def maxSigWidth = maxType.sig + def typeTag(t: FType) = floatTypes.indexOf(t) + def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U + def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U + // typeTag + def H = typeTagGroup(FType.H) + def S = typeTagGroup(FType.S) + def D = typeTagGroup(FType.D) + def I = typeTag(maxType).U + + private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR + + private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = { + require(xt.ieeeWidth == 2 * yt.ieeeWidth) + val swizzledNaN = Cat( + x(xt.sig + xt.exp, xt.sig + xt.exp - 3), + x(xt.sig - 2, yt.recodedWidth - 1).andR, + x(xt.sig + xt.exp - 5, xt.sig), + y(yt.recodedWidth - 2), + x(xt.sig - 2, yt.recodedWidth - 1), + y(yt.recodedWidth - 1), + y(yt.recodedWidth - 3, 0)) + Mux(xt.isNaN(x), swizzledNaN, x) + } + + // implement NaN unboxing for FU inputs + def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = { + val outType = exactType.getOrElse(maxType) + def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = { + val prev = + if (t == minType) { + Seq() + } else { + val prevT = prevType(t) + val unswizzled = Cat( + x(prevT.sig + prevT.exp - 1), + x(t.sig - 1), + x(prevT.sig + prevT.exp - 2, 0)) + val prev = helper(unswizzled, prevT) + val isbox = isBox(x, t) + prev.map(p => (isbox && p._1, p._2)) + } + prev :+ (true.B, t.unsafeConvert(x, outType)) + } + + val (oks, floats) = helper(x, maxType).unzip + if (exactType.isEmpty || floatTypes.size == 1) { + Mux(oks(tag), floats(tag), maxType.qNaN) + } else { + val t = exactType.get + floats(typeTag(t)) | Mux(oks(typeTag(t)), 0.U, t.qNaN) + } + } + + // make sure that the redundant bits in the NaN-boxed encoding are consistent + def consistent(x: UInt): Bool = { + def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else { + val prevT = prevType(t) + val unswizzled = Cat( + x(prevT.sig + prevT.exp - 1), + x(t.sig - 1), + x(prevT.sig + prevT.exp - 2, 0)) + val prevOK = !isBox(x, t) || helper(unswizzled, prevT) + val curOK = !t.isNaN(x) || x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR + prevOK && curOK + } + helper(x, maxType) + } + + // generate a NaN box from an FU result + def box(x: UInt, t: FType): UInt = { + if (t == maxType) { + x + } else { + val nt = floatTypes(typeTag(t) + 1) + val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t) + bigger | ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U + } + } + + // generate a NaN box from an FU result + def box(x: UInt, tag: UInt): UInt = { + val opts = floatTypes.map(t => box(x, t)) + opts(tag) + } + + // zap bits that hardfloat thinks are don't-cares, but we do care about + def sanitizeNaN(x: UInt, t: FType): UInt = { + if (typeTag(t) == 0) { + x + } else { + val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) | (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W) + Mux(t.isNaN(x), maskedNaN, x) + } + } + + // implement NaN boxing and recoding for FL*/fmv.*.x + def recode(x: UInt, tag: UInt): UInt = { + def helper(x: UInt, t: FType): UInt = { + if (typeTag(t) == 0) { + t.recode(x) + } else { + val prevT = prevType(t) + box(t.recode(x), t, helper(x, prevT), prevT) + } + } + + // fill MSBs of subword loads to emulate a wider load of a NaN-boxed value + val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U) + helper(boxes(tag) | x, maxType) + } + + // implement NaN unboxing and un-recoding for FS*/fmv.x.* + def ieee(x: UInt, t: FType = maxType): UInt = { + if (typeTag(t) == 0) { + t.ieee(x) + } else { + val unrecoded = t.ieee(x) + val prevT = prevType(t) + val prevRecoded = Cat( + x(prevT.recodedWidth-2), + x(t.sig-1), + x(prevT.recodedWidth-3, 0)) + val prevUnrecoded = ieee(prevRecoded, prevT) + Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0))) + } + } +} + +abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters + +class FPToInt(implicit p: Parameters) extends FPUModule()(p) { + class Output extends Bundle { + val in = new FPInput + val lt = Bool() + val store = Bits(fLen.W) + val toint = Bits(xLen.W) + val exc = Bits(FPConstants.FLAGS_SZ.W) + } + val io = IO(new Bundle { + val in = Flipped(Valid(new FPInput)) + val out = Valid(new Output) + }) + + val in = RegEnable(io.in.bits, io.in.valid) + val valid = RegNext(io.in.valid) + + val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth)) + dcmp.io.a := in.in1 + dcmp.io.b := in.in2 + dcmp.io.signaling := !in.rm(1) + + val tag = in.typeTagOut + val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen)) + else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) + + val toint = WireDefault(toint_ieee) + val intType = WireDefault(in.fmt(0)) + io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) + io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType) + io.out.bits.exc := 0.U + + when (in.rm(0)) { + val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag) + toint := classify_out | (toint_ieee >> minXLen << minXLen) + intType := false.B + } + + when (in.wflags) { // feq/flt/fle, fcvt + toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR | (toint_ieee >> minXLen << minXLen) + io.out.bits.exc := dcmp.io.exceptionFlags + intType := false.B + + when (!in.ren2) { // fcvt + val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1) + intType := cvtType + val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen)) + conv.io.in := in.in1 + conv.io.roundingMode := in.rm + conv.io.signedOut := ~in.typ(0) + toint := conv.io.out + io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0)) + + for (i <- 0 until nIntTypes-1) { + val w = minXLen << i + when (cvtType === i.U) { + val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w)) + narrow.io.in := in.in1 + narrow.io.roundingMode := in.rm + narrow.io.signedOut := ~in.typ(0) + + val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1) + val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign)) + val invalid = conv.io.intExceptionFlags(2) || narrow.io.intExceptionFlags(1) + when (invalid) { toint := Cat(conv.io.out >> w, excOut) } + io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0)) + } + } + } + } + + io.out.valid := valid + io.out.bits.lt := dcmp.io.lt || (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S) + io.out.bits.in := in +} + +class PipelinedINToRecFN(intWidth: Int, expWidth: Int, sigWidth: Int) extends Module { + val io = IO(new Bundle { + val validin = Input(Bool()) + val signedIn = Input(Bool()) + val in = Input(Bits(intWidth.W)) + val bypassIn = Input(Bits(intWidth.W)) + val roundingMode = Input(UInt(3.W)) + val detectTininess = Input(UInt(1.W)) + val typeTagIn = Input(UInt(2.W)) + val wflagsIn = Input(Bool()) + val out = Output(Bits((expWidth + sigWidth + 1).W)) + val exceptionFlags = Output(Bits(5.W)) + val typeTagOut = Output(UInt(2.W)) + val wflagsOut = Output(Bool()) + val inOut = Output(Bits(intWidth.W)) + val validout = Output(Bool()) + }) + + val rawExpWidth = log2Up(intWidth) + 1 + val extIntWidth = 1 << (rawExpWidth - 1) + val normalizationLevels = rawExpWidth - 1 + val firstStageLevels = 2 + val secondStageLevels = normalizationLevels - firstStageLevels + require(secondStageLevels > 0) + + val sign = io.signedIn && io.in(intWidth - 1) + val absIn = Mux(sign, -io.in.asUInt, io.in.asUInt) + val extAbsIn = (0.U(extIntWidth.W) ## absIn)(extIntWidth - 1, 0) + + // Complete the 32- and 16-bit normalization decisions before the cut. + val firstNormStages = Wire(Vec(firstStageLevels + 1, UInt(extIntWidth.W))) + val firstNormDist = Wire(Vec(firstStageLevels, Bool())) + firstNormStages(0) := extAbsIn + for (level <- 0 until firstStageLevels) { + val shiftAmt = extIntWidth >> (level + 1) + val upperHalfIsZero = + !firstNormStages(level)(extIntWidth - 1, extIntWidth - shiftAmt).orR + firstNormStages(level + 1) := Mux( + upperHalfIsZero, + (firstNormStages(level) << shiftAmt)(extIntWidth - 1, 0), + firstNormStages(level) + ) + firstNormDist(firstStageLevels - 1 - level) := upperHalfIsZero + } + + val midNormStage = RegEnable(firstNormStages(firstStageLevels), io.validin) + val midNormDist = RegEnable(firstNormDist.asUInt, io.validin) + val midSign = RegEnable(sign, io.validin) + val midRoundingMode = RegEnable(io.roundingMode, io.validin) + val midDetectTininess = RegEnable(io.detectTininess, io.validin) + val midTypeTag = RegEnable(io.typeTagIn, io.validin) + val midWflags = RegEnable(io.wflagsIn, io.validin) + val midIn = RegEnable(io.bypassIn, io.validin) + val midValid = RegNext(io.validin, false.B) + + val secondNormStages = Wire(Vec(secondStageLevels + 1, UInt(extIntWidth.W))) + val secondNormDist = Wire(Vec(secondStageLevels, Bool())) + secondNormStages(0) := midNormStage + for (offset <- 0 until secondStageLevels) { + val level = firstStageLevels + offset + val shiftAmt = extIntWidth >> (level + 1) + val upperHalfIsZero = + !secondNormStages(offset)(extIntWidth - 1, extIntWidth - shiftAmt).orR + secondNormStages(offset + 1) := Mux( + upperHalfIsZero, + (secondNormStages(offset) << shiftAmt)(extIntWidth - 1, 0), + secondNormStages(offset) + ) + secondNormDist(secondStageLevels - 1 - offset) := upperHalfIsZero + } + + val adjustedNormDist = Cat(midNormDist, secondNormDist.asUInt) + val sig = secondNormStages(secondStageLevels)(extIntWidth - 1, extIntWidth - intWidth) + val intAsRawFloat = Wire(new hardfloat.RawFloat(rawExpWidth, intWidth)) + intAsRawFloat.isNaN := false.B + intAsRawFloat.isInf := false.B + intAsRawFloat.isZero := !sig(intWidth - 1) + intAsRawFloat.sign := midSign + intAsRawFloat.sExp := (2.U(2.W) ## ~adjustedNormDist).zext + intAsRawFloat.sig := sig + + // Isolate the remaining normalization and raw-float construction from the + // target-format rounding and packing logic. + val roundInput = RegEnable(intAsRawFloat, midValid) + val roundRoundingMode = RegEnable(midRoundingMode, midValid) + val roundDetectTininess = RegEnable(midDetectTininess, midValid) + val roundTypeTag = RegEnable(midTypeTag, midValid) + val roundWflags = RegEnable(midWflags, midValid) + val roundIn = RegEnable(midIn, midValid) + val roundValid = RegNext(midValid, false.B) + + val roundAnyRawFNToRecFN = Module(new hardfloat.RoundAnyRawFNToRecFN( + rawExpWidth, + intWidth, + expWidth, + sigWidth, + hardfloat.consts.flRoundOpt_sigMSBitAlwaysZero | hardfloat.consts.flRoundOpt_neverUnderflows + )) + roundAnyRawFNToRecFN.io.invalidExc := false.B + roundAnyRawFNToRecFN.io.infiniteExc := false.B + roundAnyRawFNToRecFN.io.in := roundInput + roundAnyRawFNToRecFN.io.roundingMode := roundRoundingMode + roundAnyRawFNToRecFN.io.detectTininess := roundDetectTininess + + io.out := roundAnyRawFNToRecFN.io.out + io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags + io.typeTagOut := roundTypeTag + io.wflagsOut := roundWflags + io.inOut := roundIn + io.validout := roundValid +} + +class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) { + val io = IO(new Bundle { + val in = Flipped(Valid(new IntToFPInput)) + val out = Valid(new FPResult) + }) + + require(latency >= 3) + + val in = Pipe(io.in) + + val intValue = { + val res = WireDefault(in.bits.in1.asSInt) + for (i <- 0 until nIntTypes-1) { + val smallInt = in.bits.in1((minXLen << i) - 1, 0) + when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) { + res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt) + } + } + res.asUInt + } + + val i2f = for (t <- floatTypes) yield { + val converter = Module(new PipelinedINToRecFN(xLen, t.exp, t.sig)) + converter.io.validin := in.valid + converter.io.signedIn := ~in.bits.typ(0) + converter.io.in := intValue + converter.io.bypassIn := in.bits.in1 + converter.io.roundingMode := in.bits.rm + converter.io.detectTininess := hardfloat.consts.tininess_afterRounding + converter.io.typeTagIn := in.bits.typeTagIn + converter.io.wflagsIn := in.bits.wflags + converter + } + val tag = i2f.head.io.typeTagOut + + val mux = Wire(new FPResult) + mux.exc := 0.U + mux.data := recode(i2f.head.io.inOut, tag) + + when (i2f.head.io.wflagsOut) { // fcvt + // could be improved for RVD/RVQ with a single variable-position rounding + // unit, rather than N fixed-position ones + val i2fResults = i2f.zip(floatTypes).map { case (converter, t) => + (sanitizeNaN(converter.io.out, t), converter.io.exceptionFlags) + } + + val (data, exc) = i2fResults.unzip + val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last + mux.data := dataPadded(tag) + mux.exc := exc(tag) + } + + io.out <> Pipe(i2f.head.io.validout, mux, latency-3) +} + +class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) { + val io = IO(new Bundle { + val in = Flipped(Valid(new FPInput)) + val out = Valid(new FPResult) + val lt = Input(Bool()) // from FPToInt + }) + + val in = Pipe(io.in) + + val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2)) + val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0)) + + val fsgnjMux = Wire(new FPResult) + fsgnjMux.exc := 0.U + fsgnjMux.data := fsgnj + + when (in.bits.wflags) { // fmin/fmax + val isnan1 = maxType.isNaN(in.bits.in1) + val isnan2 = maxType.isNaN(in.bits.in2) + val isInvalid = maxType.isSNaN(in.bits.in1) || maxType.isSNaN(in.bits.in2) + val isNaNOut = isnan1 && isnan2 + val isLHS = isnan2 || in.bits.rm(0) =/= io.lt && !isnan1 + fsgnjMux.exc := isInvalid << 4 + fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2)) + } + + val inTag = in.bits.typeTagIn + val outTag = in.bits.typeTagOut + val mux = WireDefault(fsgnjMux) + for (t <- floatTypes.init) { + when (outTag === typeTag(t).U) { + mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t)) + } + } + + when (in.bits.wflags && !in.bits.ren2) { // fcvt + if (floatTypes.size > 1) { + // widening conversions simply canonicalize NaN operands + val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1) + fsgnjMux.data := widened + fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4 + + // narrowing conversions require rounding (for RVQ, this could be + // optimized to use a single variable-position rounding unit, rather + // than two fixed-position ones) + for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B || outTag < inTag)) { + val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig)) + narrower.io.in := in.bits.in1 + narrower.io.roundingMode := in.bits.rm + narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding + val narrowed = sanitizeNaN(narrower.io.out, outType) + mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed) + mux.exc := narrower.io.exceptionFlags + } + } + } + + io.out <> Pipe(in.valid, mux, latency-1) +} + +class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module +{ + override def desiredName = s"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}" + require(latency<=4) + + val io = IO(new Bundle { + val validin = Input(Bool()) + val op = Input(Bits(2.W)) + val a = Input(Bits((expWidth + sigWidth + 1).W)) + val b = Input(Bits((expWidth + sigWidth + 1).W)) + val c = Input(Bits((expWidth + sigWidth + 1).W)) + val roundingMode = Input(UInt(3.W)) + val detectTininess = Input(UInt(1.W)) + val out = Output(Bits((expWidth + sigWidth + 1).W)) + val exceptionFlags = Output(Bits(5.W)) + val validout = Output(Bool()) + }) + + //------------------------------------------------------------------------ + //------------------------------------------------------------------------ + + val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth)) + val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth)) + + mulAddRecFNToRaw_preMul.io.op := io.op + mulAddRecFNToRaw_preMul.io.a := io.a + mulAddRecFNToRaw_preMul.io.b := io.b + mulAddRecFNToRaw_preMul.io.c := io.c + + // Isolate preMul's unpack/alignment logic from the multiplier-add stage. + val preMulRegs = if (latency >= 3) 1 else 0 + val preMulMulAddA = Pipe(io.validin, mulAddRecFNToRaw_preMul.io.mulAddA, preMulRegs) + val preMulMulAddB = Pipe(io.validin, mulAddRecFNToRaw_preMul.io.mulAddB, preMulRegs) + val preMulMulAddC = Pipe(io.validin, mulAddRecFNToRaw_preMul.io.mulAddC, preMulRegs) + val preMulToPostMul = Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, preMulRegs) + + // Keep the full-precision product unrounded while separating multiplication + // from the final addition. The aligned addend and post-processing metadata + // must cross this stage with the product to preserve fused FMA semantics. + val mulRegs = if (latency == 4) 1 else 0 + val mulResult = preMulMulAddA.bits * preMulMulAddB.bits + val mulResultPipe = Pipe(preMulToPostMul.valid, mulResult, mulRegs) + val mulAddCPipe = Pipe(preMulToPostMul.valid, preMulMulAddC.bits, mulRegs) + val mulToPostMul = Pipe(preMulToPostMul.valid, preMulToPostMul.bits, mulRegs) + val mulAddResult = mulResultPipe.bits +& mulAddCPipe.bits + + val valid_stage0 = Wire(Bool()) + val roundingMode_stage0 = Wire(UInt(3.W)) + val detectTininess_stage0 = Wire(UInt(1.W)) + + val postmul_regs = if(latency>0) 1 else 0 + mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(mulToPostMul.valid, mulToPostMul.bits, postmul_regs).bits + mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(mulToPostMul.valid, mulAddResult, postmul_regs).bits + mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, preMulRegs + mulRegs + postmul_regs).bits + roundingMode_stage0 := Pipe(io.validin, io.roundingMode, preMulRegs + mulRegs + postmul_regs).bits + detectTininess_stage0 := Pipe(io.validin, io.detectTininess, preMulRegs + mulRegs + postmul_regs).bits + valid_stage0 := Pipe(io.validin, false.B, preMulRegs + mulRegs + postmul_regs).valid + + //------------------------------------------------------------------------ + //------------------------------------------------------------------------ + + val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0)) + + val round_regs = if(latency>=2) 1 else 0 + roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits + roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits + roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits + roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits + io.validout := Pipe(valid_stage0, false.B, round_regs).valid + + roundRawFNToRecFN.io.infiniteExc := false.B + + io.out := roundRawFNToRecFN.io.out + io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags +} + +class FPUFMAPipe(val latency: Int, val t: FType) + (implicit p: Parameters) extends FPUModule()(p) { + override def desiredName = s"FPUFMAPipe_l${latency}_f${t.ieeeWidth}" + require(latency>0) + + val io = IO(new Bundle { + val in = Flipped(Valid(new FPInput)) + val out = Valid(new FPResult) + }) + + val valid = RegNext(io.in.valid) + val in = Reg(new FPInput) + when (io.in.valid) { + val one = 1.U << (t.sig + t.exp - 1) + val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp)) + val cmd_fma = io.in.bits.ren3 + val cmd_addsub = io.in.bits.swap23 + in := io.in.bits + when (cmd_addsub) { in.in2 := one } + when (!(cmd_fma || cmd_addsub)) { in.in3 := zero } + } + + val fmaLatency = (latency - 1) min 4 + val fma = Module(new MulAddRecFNPipe(fmaLatency, t.exp, t.sig)) + fma.io.validin := valid + fma.io.op := in.fmaCmd + fma.io.roundingMode := in.rm + fma.io.detectTininess := hardfloat.consts.tininess_afterRounding + fma.io.a := in.in1 + fma.io.b := in.in2 + fma.io.c := in.in3 + + val res = Wire(new FPResult) + res.data := sanitizeNaN(fma.io.out, t) + res.exc := fma.io.exceptionFlags + + io.out := Pipe(fma.io.validout, res, (latency - 1 - fmaLatency) max 0) +} + +class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) { + val io = IO(new FPUIO) + + val (useClockGating, useDebugROB) = coreParams match { + case r: RocketCoreParams => + val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1 + (r.clockGate, sz < 1) + case _ => (false, false) + } + val clock_en_reg = Reg(Bool()) + val clock_en = clock_en_reg || io.cp_req.valid + val gated_clock = + if (!useClockGating) clock + else ClockGate(clock, clock_en, "fpu_clock_gate") + + val fp_decoder = Module(new FPUDecoder) + fp_decoder.io.inst := io.inst + val id_ctrl = WireInit(fp_decoder.io.sigs) + coreParams match { case r: RocketCoreParams => r.vector.map(v => { + val v_decode = v.decoder(p) // Only need to get ren1 + v_decode.io.inst := io.inst + v_decode.io.vconfig := DontCare // core deals with this + v_decode.io.vconfig.vtype.vsew := io.v_sew + when (v_decode.io.legal && v_decode.io.read_frs1) { + id_ctrl.ren1 := true.B + id_ctrl.swap12 := false.B + id_ctrl.toint := true.B + id_ctrl.typeTagIn := I + id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S) + } + when (v_decode.io.write_frd) { id_ctrl.wen := true.B } + })} + + val ex_reg_valid = RegNext(io.valid, false.B) + val ex_reg_inst = RegEnable(io.inst, io.valid) + val ex_reg_ctrl = RegEnable(id_ctrl, io.valid) + val ex_ra = List.fill(3)(Reg(UInt())) + + // load/vector response + val load_wb = RegNext(io.ll_resp_val) + val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val) + val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val) + val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val) + + class FPUImpl { // entering gated-clock domain + + val req_valid = ex_reg_valid || io.cp_req.valid + val ex_cp_valid = io.cp_req.fire + val mem_cp_valid = RegNext(ex_cp_valid, false.B) + val wb_cp_valid = RegNext(mem_cp_valid, false.B) + val mem_reg_valid = RegInit(false.B) + val killm = (io.killm || io.nack_mem) && !mem_cp_valid + // Kill X-stage instruction if M-stage is killed. This prevents it from + // speculatively being sent to the div-sqrt unit, which can cause priority + // inversion for two back-to-back divides, the first of which is killed. + val killx = io.killx || mem_reg_valid && killm + mem_reg_valid := ex_reg_valid && !killx || ex_cp_valid + val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid) + val wb_reg_valid = RegNext(mem_reg_valid && (!killm || mem_cp_valid), false.B) + + val cp_ctrl = Wire(new FPUCtrlSigs) + cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs) + io.cp_resp.valid := false.B + io.cp_resp.bits.data := 0.U + io.cp_resp.bits.exc := DontCare + + val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl) + val mem_ctrl = RegEnable(ex_ctrl, req_valid) + val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid) + + // CoreMonitorBundle to monitor fp register file writes + val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare)) + frfWriteBundle.foreach { i => + i.clock := clock + i.reset := reset + i.hartid := io.hartid + i.timer := io.time(31,0) + i.valid := false.B + i.wrenx := false.B + i.wrenf := false.B + i.excpt := false.B + } + + // regfile + val regfile = Mem(32, Bits((fLen+1).W)) + when (load_wb) { + val wdata = recode(load_wb_data, load_wb_typeTag) + regfile(load_wb_tag) := wdata + assert(consistent(wdata)) + if (enableCommitLog) + printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32.U, ieee(wdata)) + if (useDebugROB) + DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata)) + frfWriteBundle(0).wrdst := load_wb_tag + frfWriteBundle(0).wrenf := true.B + frfWriteBundle(0).wrdata := ieee(wdata) + } + + val ex_rs = ex_ra.map(a => regfile(a)) + when (io.valid) { + when (id_ctrl.ren1) { + when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) } + when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) } + } + when (id_ctrl.ren2) { + when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) } + when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) } + when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) } + } + when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) } + } + val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12)) + + def fuInput(minT: Option[FType]): FPInput = { + val req = Wire(new FPInput) + val tag = ex_ctrl.typeTagIn + req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs) + req.rm := ex_rm + req.in1 := unbox(ex_rs(0), tag, minT) + req.in2 := unbox(ex_rs(1), tag, minT) + req.in3 := unbox(ex_rs(2), tag, minT) + req.typ := ex_reg_inst(21,20) + req.fmt := ex_reg_inst(26,25) + req.fmaCmd := ex_reg_inst(3,2) | (!ex_ctrl.ren3 && ex_reg_inst(27)) + when (ex_cp_valid) { + req := io.cp_req.bits + when (io.cp_req.bits.swap12) { + req.in1 := io.cp_req.bits.in2 + req.in2 := io.cp_req.bits.in1 + } + when (io.cp_req.bits.swap23) { + req.in2 := io.cp_req.bits.in3 + req.in3 := io.cp_req.bits.in2 + } + } + req + } + + // FMA units are selected with their writeback metadata below. + + val fpiu = Module(new FPToInt) + fpiu.io.in.valid := req_valid && (ex_ctrl.toint || ex_ctrl.div || ex_ctrl.sqrt || (ex_ctrl.fastpipe && ex_ctrl.wflags)) + fpiu.io.in.bits := fuInput(None) + io.store_data := fpiu.io.out.bits.store + io.toint_data := fpiu.io.out.bits.toint + when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){ + io.cp_resp.bits.data := fpiu.io.out.bits.toint + io.cp_resp.valid := true.B + } + + val ifpu = Module(new IntToFP(cfg.ifpuLatency)) + ifpu.io.in.valid := req_valid && ex_ctrl.fromint + ifpu.io.in.bits := fpiu.io.in.bits + ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data) + + val fpmu = Module(new FPToFP(cfg.fpmuLatency)) + fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe + fpmu.io.in.bits := fpiu.io.in.bits + fpmu.io.lt := fpiu.io.out.bits.lt + + val divSqrt_wen = WireDefault(false.B) + val divSqrt_inFlight = WireDefault(false.B) + val divSqrt_waddr = Reg(UInt(5.W)) + val divSqrt_cp = Reg(Bool()) + val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W)) + val divSqrt_wdata = Wire(UInt((fLen+1).W)) + val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W)) + divSqrt_typeTag := DontCare + divSqrt_wdata := DontCare + divSqrt_flags := DontCare + // writeback arbitration + case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult) + val fmaPipes = if (p(FpgaSharedFma)) { + require(fLen == 64 && minFLen == 16) + require(cfg.sfmaLatency == cfg.dfmaLatency) + val sharedFma = Module(new FPUSharedFMAPipe(cfg.dfmaLatency)) + sharedFma.io.in.valid := req_valid && ex_ctrl.fma + sharedFma.io.in.bits := fuInput(Some(FType.D)) + for (t <- floatTypes.init) { + when (ex_ctrl.typeTagOut === typeTag(t).U) { + sharedFma.io.in.bits := fuInput(Some(t)) + } + } + List(Pipe(sharedFma, sharedFma.latency, (c: FPUCtrlSigs) => c.fma, sharedFma.io.out.bits)) + } else { + val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S)) + sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S + sfma.io.in.bits := fuInput(Some(sfma.t)) + List( + Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++ + (fLen > 32).option({ + val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D)) + dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D + dfma.io.in.bits := fuInput(Some(dfma.t)) + Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits) + }) ++ + (minFLen == 16).option({ + val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H)) + hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H + hfma.io.in.bits := fuInput(Some(hfma.t)) + Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits) + }) + + } + val pipes = List( + Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits), + Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits)) ++ fmaPipes + def latencyMask(c: FPUCtrlSigs, offset: Int) = { + require(pipes.forall(_.lat >= offset)) + pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_|_) + } + def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_|_) + val maxLatency = pipes.map(_.lat).max + val memLatencyMask = latencyMask(mem_ctrl, 2) + + class WBInfo extends Bundle { + val rd = UInt(5.W) + val typeTag = UInt(log2Up(floatTypes.size).W) + val cp = Bool() + val pipeid = UInt(log2Ceil(pipes.size).W) + } + + val wen = RegInit(0.U((maxLatency-1).W)) + val wbInfo = Reg(Vec(maxLatency-1, new WBInfo)) + val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint) + val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, req_valid) + ccover(mem_reg_valid && write_port_busy, "WB_STRUCTURAL", "structural hazard on writeback") + + for (i <- 0 until maxLatency-2) { + when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) } + } + wen := wen >> 1 + when (mem_wen) { + when (!killm) { + wen := wen >> 1 | memLatencyMask + } + for (i <- 0 until maxLatency-1) { + when (!write_port_busy && memLatencyMask(i)) { + wbInfo(i).cp := mem_cp_valid + wbInfo(i).typeTag := mem_ctrl.typeTagOut + wbInfo(i).pipeid := pipeid(mem_ctrl) + wbInfo(i).rd := mem_reg_inst(11,7) + } + } + } + + val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd) + val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp) + val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag) + val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag) + val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid) + when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) { + assert(consistent(wdata)) + regfile(waddr) := wdata + if (enableCommitLog) { + printf("f%d p%d 0x%x\n", waddr, waddr + 32.U, ieee(wdata)) + } + frfWriteBundle(1).wrdst := waddr + frfWriteBundle(1).wrenf := true.B + frfWriteBundle(1).wrdata := ieee(wdata) + } + if (useDebugROB) { + DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) || divSqrt_wen, waddr + 32.U, ieee(wdata)) + } + + when (wb_cp && (wen(0) || divSqrt_wen)) { + io.cp_resp.bits.data := wdata + io.cp_resp.valid := true.B + } + + assert(!io.cp_req.valid || pipes.forall(_.lat == pipes.head.lat).B, + s"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}") + // Avoid structural hazards and nacking of external requests + // toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs + io.cp_req.ready := !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight + + val wb_toint_valid = wb_reg_valid && wb_ctrl.toint + val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint) + io.fcsr_flags.valid := wb_toint_valid || divSqrt_wen || wen(0) + io.fcsr_flags.bits := + Mux(wb_toint_valid, wb_toint_exc, 0.U) | + Mux(divSqrt_wen, divSqrt_flags, 0.U) | + Mux(wen(0), wexc, 0.U) + + val divSqrt_write_port_busy = (mem_ctrl.div || mem_ctrl.sqrt) && wen.orR + io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags || mem_reg_valid && mem_ctrl.wflags || wb_reg_valid && wb_ctrl.toint || wen.orR || divSqrt_inFlight) + io.nack_mem := (write_port_busy || divSqrt_write_port_busy || divSqrt_inFlight || mem_cp_valid) + io.dec <> id_ctrl + def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_||_) + io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt || mem_ctrl.vec) + io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U))) + io.sboard_clra := waddr + ccover(io.sboard_clr && load_wb, "DUAL_WRITEBACK", "load and FMA writeback on same cycle") + // we don't currently support round-max-magnitude (rm=4) + io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) || io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U + + if (cfg.divSqrt) { + val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight + val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B) + when (divSqrt_inValid) { + divSqrt_waddr := mem_reg_inst(11,7) + divSqrt_cp := mem_cp_valid + } + + ccover(divSqrt_inFlight && divSqrt_killed, "DIV_KILLED", "divide killed after issued to divider") + ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt), "DIV_BUSY", "divider structural hazard") + ccover(mem_reg_valid && divSqrt_write_port_busy, "DIV_WB_STRUCTURAL", "structural hazard on division writeback") + + for (t <- floatTypes) { + val tag = mem_ctrl.typeTagOut + val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) } + divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U + divSqrt.io.sqrtOp := mem_ctrl.sqrt + divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t) + divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t) + divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm + divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding + + when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight + + when (divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt) { + divSqrt_wen := !divSqrt_killed + divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t) + divSqrt_flags := divSqrt.io.exceptionFlags + divSqrt_typeTag := typeTag(t).U + } + } + + when (divSqrt_killed) { divSqrt_inFlight := false.B } + } else { + when (id_ctrl.div || id_ctrl.sqrt) { io.illegal_rm := true.B } + } + + // gate the clock + clock_en_reg := !useClockGating.B || + io.keep_clock_enabled || // chicken bit + io.valid || // ID stage + req_valid || // EX stage + mem_reg_valid || mem_cp_valid || // MEM stage + wb_reg_valid || wb_cp_valid || // WB stage + wen.orR || divSqrt_inFlight || // post-WB stage + io.ll_resp_val // load writeback + + } // leaving gated-clock domain + val fpuImpl = withClock (gated_clock) { new FPUImpl } + + def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = + property.cover(cond, s"FPU_$label", "Core;;" + desc) +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/rocket/SharedFma.scala b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/rocket/SharedFma.scala new file mode 100644 index 0000000..a05e40b --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/patches/rocket/SharedFma.scala @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: BSD-3-Clause +package freechips.rocketchip.tile + +import chisel3._ +import chisel3.util._ +import org.chipsalliance.cde.config.Parameters + +/** One unrounded FP64 FMA datapath, with direct H/S/D final rounding. */ +class SharedMulAddRecFNPipe(implicit p: Parameters) extends FPUModule { + require(fLen == 64 && minFLen == 16) + val io = IO(new Bundle { + val validin = Input(Bool()) + val op = Input(UInt(2.W)) + val typeTag = Input(UInt(2.W)) + val a = Input(UInt(65.W)) + val b = Input(UInt(65.W)) + val c = Input(UInt(65.W)) + val roundingMode = Input(UInt(3.W)) + val out = Output(new FPResult) + val validout = Output(Bool()) + }) + val pre = Module(new hardfloat.MulAddRecFNToRaw_preMul(11, 53)) + val post = Module(new hardfloat.MulAddRecFNToRaw_postMul(11, 53)) + pre.io.op := io.op + pre.io.a := io.a + pre.io.b := io.b + pre.io.c := io.c + + // Retain the original four-stage raw FMA partition: align, multiply, add, + // normalize. Full product bits and sticky information survive until rounding. + val mulA = Pipe(io.validin, pre.io.mulAddA, 1) + val mulB = Pipe(io.validin, pre.io.mulAddB, 1) + val alignedC = Pipe(io.validin, pre.io.mulAddC, 1) + val meta = Pipe(io.validin, pre.io.toPostMul, 1) + val product = Pipe(meta.valid, mulA.bits * mulB.bits, 1) + val delayedC = Pipe(meta.valid, alignedC.bits, 1) + val delayedMeta = Pipe(meta.valid, meta.bits, 1) + val sum = product.bits +& delayedC.bits + post.io.fromPreMul := Pipe(delayedMeta.valid, delayedMeta.bits, 1).bits + post.io.mulAddResult := Pipe(delayedMeta.valid, sum, 1).bits + val rmPost = Pipe(io.validin, io.roundingMode, 3) + post.io.roundingMode := rmPost.bits + + val raw = Pipe(rmPost.valid, post.io.rawOut, 1) + val invalid = Pipe(rmPost.valid, post.io.invalidExc, 1) + val rm = Pipe(io.validin, io.roundingMode, 4) + val tag = Pipe(io.validin, io.typeTag, 4) + val results = floatTypes.map { t => + // Do not round to FP64 and convert afterward: that would double-round. + val round = Module(new hardfloat.RoundAnyRawFNToRecFN(11, 55, t.exp, t.sig, 0)) + round.io.in := raw.bits + round.io.invalidExc := invalid.bits + round.io.infiniteExc := false.B + round.io.roundingMode := rm.bits + round.io.detectTininess := hardfloat.consts.tininess_afterRounding + val result = Wire(new FPResult) + result.data := sanitizeNaN(round.io.out, t) + result.exc := round.io.exceptionFlags + result + } + io.out := VecInit(results)(tag.bits) + io.validout := tag.valid +} + +/** The Rocket core issues at most one FMA per cycle; all formats share it. */ +class FPUSharedFMAPipe(val latency: Int)(implicit p: Parameters) extends FPUModule { + require(latency >= 5) + require(fLen == 64 && minFLen == 16) + val io = IO(new Bundle { + val in = Flipped(Valid(new FPInput)) + val out = Valid(new FPResult) + }) + def widen(x: UInt): UInt = { + VecInit(floatTypes.map(t => t.unsafeConvert(x(t.recodedWidth - 1, 0), maxType)))(io.in.bits.typeTagOut) + } + val a = widen(io.in.bits.in1) + val b = widen(io.in.bits.in2) + val c = widen(io.in.bits.in3) + val valid = RegNext(io.in.valid, false.B) + val in = Reg(new FPInput) + when (io.in.valid) { + in := io.in.bits + in.in1 := a + in.in2 := Mux(io.in.bits.swap23, (BigInt(1) << 63).U(65.W), b) + val zero = (a ^ b) & (BigInt(1) << 64).U(65.W) + in.in3 := Mux(io.in.bits.ren3 || io.in.bits.swap23, c, zero) + } + val fma = Module(new SharedMulAddRecFNPipe) + fma.io.validin := valid + fma.io.op := in.fmaCmd + fma.io.typeTag := in.typeTagOut + fma.io.a := in.in1 + fma.io.b := in.in2 + fma.io.c := in.in3 + fma.io.roundingMode := in.rm + io.out := Pipe(fma.io.validout, fma.io.out, latency - 5) +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/rtl/FpuRfLvt.sv b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/rtl/FpuRfLvt.sv new file mode 100644 index 0000000..a929eda --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/rtl/FpuRfLvt.sv @@ -0,0 +1,44 @@ +module FpuRfLvt( + input [4:0] R0_addr, + input R0_en, + R0_clk, + output [64:0] R0_data, + input [4:0] R1_addr, + input R1_en, + R1_clk, + output [64:0] R1_data, + input [4:0] R2_addr, + input R2_en, + R2_clk, + output [64:0] R2_data, + input [4:0] W0_addr, + input W0_en, + W0_clk, + input [64:0] W0_data, + input [4:0] W1_addr, + input W1_en, + W1_clk, + input [64:0] W1_data +); + + // Each data bank has one synchronous write port and three asynchronous reads. + // A 32-bit table identifies the bank containing each register's newest value. + // Match original W1-over-W0 priority when both ports write the same address. + // Original RTL clocks both write ports with W0_clk; retain that contract. + (* ram_style = "distributed" *) reg [64:0] bank0 [0:31]; + (* ram_style = "distributed" *) reg [64:0] bank1 [0:31]; + reg [31:0] latest; + always @(posedge W0_clk) begin + if (W0_en) begin + bank0[W0_addr] <= W0_data; + latest[W0_addr] <= 1'b0; + end + if (W1_en) begin + bank1[W1_addr] <= W1_data; + latest[W1_addr] <= 1'b1; + end + end + assign R0_data = R0_en ? (latest[R0_addr] ? bank1[R0_addr] : bank0[R0_addr]) : 65'bx; + assign R1_data = R1_en ? (latest[R1_addr] ? bank1[R1_addr] : bank0[R1_addr]) : 65'bx; + assign R2_data = R2_en ? (latest[R2_addr] ? bank1[R2_addr] : bank0[R2_addr]) : 65'bx; +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/rtl/FpuRfOriginal.sv b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/rtl/FpuRfOriginal.sv new file mode 100644 index 0000000..582263c --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/rtl/FpuRfOriginal.sv @@ -0,0 +1,34 @@ +module FpuRfOriginal( + input [4:0] R0_addr, + input R0_en, + R0_clk, + output [64:0] R0_data, + input [4:0] R1_addr, + input R1_en, + R1_clk, + output [64:0] R1_data, + input [4:0] R2_addr, + input R2_en, + R2_clk, + output [64:0] R2_data, + input [4:0] W0_addr, + input W0_en, + W0_clk, + input [64:0] W0_data, + input [4:0] W1_addr, + input W1_en, + W1_clk, + input [64:0] W1_data +); + + reg [64:0] Memory[0:31]; + always @(posedge W0_clk) begin + if (W0_en & 1'h1) + Memory[W0_addr] <= W0_data; + if (W1_en & 1'h1) + Memory[W1_addr] <= W1_data; + end // always @(posedge) + assign R0_data = R0_en ? Memory[R0_addr] : 65'bx; + assign R1_data = R1_en ? Memory[R1_addr] : 65'bx; + assign R2_data = R2_en ? Memory[R2_addr] : 65'bx; +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/bind_fpu_rf.py b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/bind_fpu_rf.py new file mode 100644 index 0000000..4646b37 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/bind_fpu_rf.py @@ -0,0 +1,33 @@ +"""Bind the already validated zero-latency FPU RF adapter after SRAM binding.""" + +import hashlib +import json +from pathlib import Path +import re + +ROOT = Path(__file__).resolve().parents[1] +output = ROOT / "build/serial-bound" +core = output / "ToyLinuxChip.sv" +original = core.read_text(encoding="utf-8") +matches = list(re.finditer(r"^module regfile_32x65\(.*?^endmodule", original, re.M | re.S)) +assert len(matches) == 1 +match = matches[0] +reference = (ROOT / "rtl/FpuRfOriginal.sv").read_text(encoding="utf-8").strip() +assert match.group() == reference.replace("module FpuRfOriginal(", "module regfile_32x65(") +replacement = (ROOT / "rtl/FpuRfLvt.sv").read_text(encoding="utf-8").strip() +replacement = replacement.replace("module FpuRfLvt(", "module regfile_32x65(") +adapted = original[:match.start()] + replacement + original[match.end():] +core.write_text(adapted, encoding="utf-8", newline="\n") +assert adapted.replace(replacement, match.group(), 1) == original +manifest = json.loads((output / "MEMORY_MANIFEST.json").read_text()) +manifest["baseline_core_rtl_sha256"] = manifest["core_rtl_sha256"] +manifest["core_rtl_sha256"] = hashlib.sha256(core.read_bytes()).hexdigest() +manifest["additional_memory_adapters"] = [{ + "module": "regfile_32x65", "implementation": "two single-write LUTRAM banks and LVT", + "read_ports": 3, "write_ports": 2, "read_latency": 0, + "same_address_write_priority": "W1", "added_cycles": 0, + "adapter_sha256": hashlib.sha256((ROOT / "rtl/FpuRfLvt.sv").read_bytes()).hexdigest(), +}] +(output / "MEMORY_MANIFEST.json").write_text(json.dumps(manifest, indent=2) + "\n") +print("PASS RF adapter matches original port contract; only RF module body replaced") +print("Final core SHA256:", manifest["core_rtl_sha256"]) diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/build_board_firmware.py b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/build_board_firmware.py new file mode 100644 index 0000000..6232633 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/build_board_firmware.py @@ -0,0 +1,82 @@ +"""Rebuild the pinned OpenSBI payload for the board's actual CLINT frequency. + +Uses the existing pinned Linux+BusyBox image unchanged. Copies OpenSBI and its +platform into this isolated candidate, never modifies the earlier software. +""" +import hashlib +import argparse +import json +from pathlib import Path +import shutil +import subprocess + +ROOT=Path(__file__).resolve().parents[1] +BASE=ROOT +OUT=ROOT/"build/board-software" + + +def sha(path): + return hashlib.sha256(path.read_bytes()).hexdigest() + + +def main(): + global BASE + parser=argparse.ArgumentParser(description=__doc__) + parser.add_argument("--software-base",type=Path,default=ROOT, + help="Root containing build/software from software/build.sh") + parser.add_argument("--cross-compile",default="riscv64-linux-gnu-") + args=parser.parse_args() + BASE=args.software_base.resolve() + OUT.mkdir(parents=True,exist_ok=True) + source=BASE/"build/software/bb-tests/thirdparty/opensbi" + platform=BASE/"build/software/bb-tests/workloads/lib/kernel/opensbi-platform" + image=BASE/"build/software/kernel-build/linux/arch/riscv/boot/Image" + image_sha=sha(image) + for original,target in ((source,OUT/"opensbi-src"),(platform,OUT/"platform")): + if not target.exists(): + shutil.copytree(original,target,ignore=shutil.ignore_patterns(".git","build")) + original=(platform/"buckyball/platform.c").read_text() + assert original.count("#define BUCKYBALL_MTIMER_FREQ 1000000")==1 + adapted=original.replace("#define BUCKYBALL_MTIMER_FREQ 1000000","#define BUCKYBALL_MTIMER_FREQ 500000") + old=""" if (fdt_open_into(src, dst, size) == 0) + return BUCKYBALL_DTB_STAGING_ADDR;""" + new=""" if (fdt_open_into(src, dst, size + 512) == 0) { + int cpus = fdt_path_offset(dst, "/cpus"); + if (cpus >= 0) { + if (fdt_setprop_u32(dst, cpus, "timebase-frequency", + BUCKYBALL_MTIMER_FREQ) != 0) + return 0; + int cpu; + fdt_for_each_subnode(cpu, dst, cpus) { + fdt_setprop_u32(dst, cpu, "timebase-frequency", BUCKYBALL_MTIMER_FREQ); + fdt_setprop_u32(dst, cpu, "clock-frequency", 25000000); + } + } + return BUCKYBALL_DTB_STAGING_ADDR; + }""" + assert adapted.count(old)==1 + adapted=adapted.replace(old,new) + (OUT/"platform/buckyball/platform.c").write_text(adapted) + shutil.copy2(image,OUT/"Image") + command=["make","-C",str(OUT/"opensbi-src"),"-j8","CROSS_COMPILE="+args.cross_compile, + "PLATFORM_DIR="+str(OUT/"platform"),"PLATFORM=buckyball","O="+str(OUT/"opensbi-build"), + "FW_PAYLOAD_PATH="+str(OUT/"Image"),"BUCKYBALL_VISIBLE_HART_COUNT=1", + "BUCKYBALL_TOTAL_HART_COUNT=1","BUCKYBALL_HIDDEN_HART_BASE=1"] + with (OUT/"build.log").open("w") as log: + subprocess.run(command,stdout=log,stderr=log,check=True,timeout=900) + payload=OUT/"opensbi-build/platform/buckyball/firmware/fw_payload.bin" + shutil.copy2(payload,OUT/"fw_payload.bin") + assert sha(image)==image_sha==sha(OUT/"Image") + record=dict(result="PASS_BUILD",payload_sha256=sha(payload),payload_bytes=payload.stat().st_size, + linux_image_sha256=image_sha,linux_image_unchanged=True,clint_frequency_hz=500000, + core_frequency_hz=25000000,console_base="0x60020000",memory_bytes=268435456, + original_platform_sha256=sha(platform/"buckyball/platform.c"), + adapted_platform_sha256=sha(OUT/"platform/buckyball/platform.c"), + original_payload_sha256=sha(BASE/"build/software/kernel-build/opensbi/platform/buckyball/firmware/fw_payload.bin"), + boot_tested=False,command=command) + (OUT/"RESULT.json").write_text(json.dumps(record,indent=2)+"\n") + print(json.dumps(record,indent=2)) + + +if __name__=="__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/build_test_programs.sh b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/build_test_programs.sh new file mode 100644 index 0000000..987fbed --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/build_test_programs.sh @@ -0,0 +1,7 @@ +#!/usr/bin/env bash +set -euo pipefail +cd "$(dirname "$0")/.." +python3 tests/check_cpu_smoke.py +python3 tests/check_gemmini.py +python3 tests/check_loop_stress.py +python3 tests/check_dma_beat64.py diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/check_board.py b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/check_board.py new file mode 100644 index 0000000..1d064ba --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/check_board.py @@ -0,0 +1,77 @@ +"""Test the exact board loader, AXI normalizer and OpenSBI SCU with stalls.""" +import hashlib +import json +from pathlib import Path +import subprocess +from offline_check import run_check + +ROOT=Path(__file__).resolve().parents[1] +OUT=ROOT/"build/board-unit" + + +def run(name, files, marker): + executable=OUT/name + command=["iverilog","-g2012","-s",name,"-o",str(executable)]+[str(f) for f in files] + compiled=subprocess.run(command,capture_output=True,text=True,timeout=60) + (OUT/(name+"-compile.log")).write_text(compiled.stdout+compiled.stderr) + compiled.check_returncode() + result=subprocess.run(["vvp",str(executable)],capture_output=True,text=True,timeout=60) + (OUT/(name+".log")).write_text(result.stdout+result.stderr) + print(result.stdout,end="") + result.check_returncode() + assert marker in result.stdout + + +def main(): + fixture=json.loads((ROOT/"tests/PLATFORM_PORTS_MANIFEST.json").read_text()) + if hashlib.sha256((ROOT/"tests/ToyLinuxChipPorts.sv").read_bytes()).hexdigest()!=fixture["stub_sha256"]: + raise ValueError("CPU port fixture differs from its manifest") + OUT.mkdir(parents=True,exist_ok=True) + run("tb_axi_fullwidth",[ROOT/"board/axi_fullwidth.sv",ROOT/"tests/axi_smoke_memory.sv",ROOT/"tests/tb_axi_fullwidth.sv"],"PASS fullwidth AXI") + run("tb_axi_scu",[ROOT/"board/axi_scu.sv",ROOT/"tests/tb_axi_scu.sv"],"PASS SCU") + platform_files=[ROOT/"board"/name for name in + ("toy_a7_platform.sv","axi_fullwidth.sv","axi_scu.sv","ddr_uart_loader.sv", + "loader_axi.sv","uart_rx.sv","uart_tx.sv","flash_spi_byte.sv")] + run("tb_platform_bresp",platform_files+[ROOT/"tests/ToyLinuxChipPorts.sv",ROOT/"tests/tb_platform_bresp.sv"], + "PASS platform AXI B response") + # Retain the CRC/range/timeout/rejected RUN oracle from the earlier loader, + # but connect its new acknowledgement boundary to AXI, not zero-latency RAM. + template=(ROOT/"tests/board_loader_template.sv").read_text() + template=template.replace("module tb_uart_loader", "module tb_ddr_loader") + template=template.replace("uart_loader #", "ddr_uart_loader #") + template=template.replace("32'h01374150", "32'h02374154") + template=template.replace("axi_bram #(.WORDS(256)) memory(", "/* legacy memory removed\naxi_bram #(.WORDS(256)) memory(") + template=template.replace(" always @(posedge clk) begin\n", "*/\n"+LOADER_MEMORY+"\n always @(posedge clk) begin\n",1) + template=template.replace("wire cpu_run,error_seen,load_en,load_valid;", "wire cpu_run,error_seen,load_en,load_valid,load_error;") + template=template.replace("PASS: UART loader", "PASS: DDR UART loader") + (OUT/"tb_ddr_loader.sv").write_text(template) + run("tb_ddr_loader",[ROOT/"board/ddr_uart_loader.sv",ROOT/"board/loader_axi.sv",ROOT/"tests/axi_smoke_memory.sv",OUT/"tb_ddr_loader.sv"],"PASS: DDR UART loader") + files=[p for p in (ROOT/"board").glob("*.sv")]+[ROOT/"tests/tb_axi_fullwidth.sv",ROOT/"tests/tb_axi_scu.sv"] + files += [ROOT/"tests/ToyLinuxChipPorts.sv",ROOT/"tests/tb_platform_bresp.sv"] + record=dict(result="PASS",tests=4,physical_mig_simulated=False, + sources={str(p.relative_to(ROOT)):hashlib.sha256(p.read_bytes()).hexdigest() for p in files}) + (OUT/"RESULT.json").write_text(json.dumps(record,indent=2)+"\n") + + +LOADER_MEMORY=""" + wire [27:0] awaddr,araddr; + wire awvalid,wvalid,arvalid,bready,rready,awready,wready,arready,bvalid,rvalid; + wire [127:0] wdata,rdata; + wire [15:0] wstrb; + wire [1:0] bresp,rresp; + loader_axi bridge(.clk(clk),.reset(reset),.load_en(load_en),.load_addr({16'd0,load_addr}), + .load_data(load_data),.load_mask(load_mask),.load_valid(load_valid),.load_error(load_error),.load_result(load_result), + .awaddr(awaddr),.araddr(araddr),.awvalid(awvalid),.wvalid(wvalid),.arvalid(arvalid), + .bready(bready),.rready(rready),.awready(awready),.wready(wready),.arready(arready), + .bvalid(bvalid),.rvalid(rvalid),.wdata(wdata),.wstrb(wstrb),.bresp(bresp),.rresp(rresp),.rdata(rdata)); + axi_smoke_memory #(.ADDR_BITS(28),.BASE(0),.CAPACITY(4096)) memory ( + .clock(clk),.reset(reset),.aw_bits_id(4'd0),.aw_bits_addr(awaddr),.aw_bits_len(8'd0),.aw_bits_size(3'd4),.aw_bits_burst(2'd1), + .aw_valid(awvalid),.aw_ready(awready),.w_bits_data(wdata),.w_bits_strb(wstrb),.w_bits_last(1'b1),.w_valid(wvalid),.w_ready(wready), + .b_ready(bready),.b_valid(bvalid),.b_bits_id(),.b_bits_resp(bresp), + .ar_bits_id(4'd0),.ar_bits_addr(araddr),.ar_bits_len(8'd0),.ar_bits_size(3'd4),.ar_bits_burst(2'd1),.ar_valid(arvalid),.ar_ready(arready), + .r_ready(rready),.r_valid(rvalid),.r_bits_id(),.r_bits_data(rdata),.r_bits_resp(rresp),.r_bits_last()); +""" + + +if __name__=="__main__": + run_check(main, OUT) diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/check_board_cdc.py b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/check_board_cdc.py new file mode 100644 index 0000000..0b22eb4 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/check_board_cdc.py @@ -0,0 +1,80 @@ +"""Exercise the actual Xilinx AXI Clock Converter with the adapter oracle. + +The MIG PHY is replaced by the stalled memory model. The converter uses the +same generated IP as the specified board build, copied into a test directory. +""" +import argparse +import hashlib +import json +import os +from pathlib import Path +import re +import shutil +import subprocess + +ROOT = Path(__file__).resolve().parents[1] + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("board_run") + parser.add_argument("--output-name", default="board-cdc") + args = parser.parse_args() + source = ROOT / "build" / args.board_run / "ip/toy_axi_cdc" + assert source.is_dir(), source + assert re.fullmatch(r"board-cdc(?:-[a-zA-Z0-9-]+)?", args.output_name) + out = ROOT / "build" / args.output_name + out.mkdir(parents=True, exist_ok=True) + ip = out / "ip/toy_axi_cdc" + assert not ip.exists(), "Keep previous simulation evidence; use a fresh output" + shutil.copytree(source, ip) + + bench = (ROOT / "tests/tb_axi_fullwidth.sv").read_text() + bench = bench.replace("tb_axi_fullwidth", "tb_board_cdc") + bench = bench.replace("always #5 clk=~clk;", "always #20 clk=~clk;\n reg ui_clk=0; initial begin #3; forever #6 ui_clk=~ui_clk; end") + # Reuse exactly the board's converter instance and port tie-offs. + top = (ROOT / "board/toy_a7_top.sv").read_text() + declarations = top[top.index(" wire [3:0] ui_awid;"):top.index(" toy_a7_platform")] + instance = top[top.index(" toy_axi_cdc memory_cdc"):top.index(" arty_ddr3 ddr_controller")] + instance = instance.replace("ddr_", "m_").replace("ui_aresetn", "!reset") + bench = bench.replace(" axi_fullwidth dut(.*);", declarations + instance + " axi_fullwidth dut(.*);") + first = bench.index(" axi_smoke_memory") + last = bench.index(" always @(posedge clk)", first) + memory = bench[first:last].replace(".clock(clk)", ".clock(ui_clk)").replace("(m_", "(ui_") + bench = bench[:first] + memory + bench[last:] + bench = bench.replace("repeat(5) @(negedge clk);reset=0;", "repeat(20) @(negedge clk);reset=0;repeat(60) @(negedge clk);") + bench = bench.replace("PASS fullwidth AXI:", "PASS BOARD_CDC:") + bench = bench.replace("#2000000", "#10000000") + (out / "tb_board_cdc.sv").write_text(bench) + tcl = f"""create_project -force cdc_test {{{out / 'project'}}} -part xc7a100tcsg324-1 +read_ip {{{ip / 'toy_axi_cdc.xci'}}} +read_verilog -sv {{{ROOT / 'board/axi_fullwidth.sv'}}} +read_verilog -sv {{{ROOT / 'tests/axi_smoke_memory.sv'}}} +read_verilog -sv {{{out / 'tb_board_cdc.sv'}}} +set_property top tb_board_cdc [get_filesets sim_1] +set_property xsim.simulate.runtime all [get_filesets sim_1] +launch_simulation +close_sim +exit +""" + script = out / "simulate.tcl" + script.write_text(tcl) + with (out / "console.log").open("w") as log: + result = subprocess.run([os.environ.get("VIVADO", "vivado"), "-mode", "batch", "-source", str(script), + "-log", str(out / "vivado.log"), "-journal", str(out / "vivado.jou")], + cwd=out, stdout=log, stderr=log, timeout=900) + result.check_returncode() + simulation = out / "project/cdc_test.sim/sim_1/behav/xsim/simulate.log" + transcript = simulation.read_text() + assert "PASS BOARD_CDC:" in transcript, transcript[-2000:] + record = dict(result="PASS_BOARD_CDC", board_run=args.board_run, + core_clock_hz=25000000, ui_clock_hz=83333333, + read_beats=90, physical_mig_simulated=False, + xci_sha256=hashlib.sha256((ip / "toy_axi_cdc.xci").read_bytes()).hexdigest(), + bench_sha256=hashlib.sha256(bench.encode()).hexdigest()) + (out / "RESULT.json").write_text(json.dumps(record, indent=2) + "\n") + print(transcript[-1600:]) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/check_board_cpu.py b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/check_board_cpu.py new file mode 100644 index 0000000..6596ecb --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/check_board_cpu.py @@ -0,0 +1,93 @@ +"""Run the existing CPU/VM/FPU oracle through the real board platform RTL. + +The DDR PHY/CDC is replaced by a stalled AXI memory model here. Loader start is +forced only in this testbench so this separately tests CPU-to-DDR/SCU wiring. +""" +import hashlib +import argparse +import json +from pathlib import Path +import re +import subprocess +import shutil + +ROOT=Path(__file__).resolve().parents[1] +OUT=ROOT/"build/board-cpu" + + +def main(): + global OUT + parser=argparse.ArgumentParser(description=__doc__) + parser.add_argument("--test",choices=("cpu","gemmini","loop","dma"),default="cpu") + args=parser.parse_args() + OUT=ROOT/("build/board-"+args.test) + OUT.mkdir(parents=True,exist_ok=True) + binary=ROOT/"build/cpu-smoke/smoke.bin" + if args.test!="cpu": + subdir={"gemmini":"gemmini-tests","loop":"loop-stress","dma":"dma-beat64"}[args.test] + elf=ROOT/"build"/subdir/"simulation/smoke.elf" + binary=OUT/"program.bin" + subprocess.run(["riscv64-unknown-elf-objcopy","-O","binary",str(elf),str(binary)],check=True) + assert binary.exists() + shutil.copy2(binary,OUT/"smoke.bin") + (OUT/"smoke.hex").write_text("\n".join(f"{b:02x}" for b in binary.read_bytes())+"\n") + platform=ROOT/"board/toy_a7_platform.sv" + header=platform.read_text().split(") (",1)[1].split(");",1)[0] + signals=[] + direction,width=None,"" + for part in header.split(","): + m=re.fullmatch(r"\s*(?:(input|output)\s+wire\s+)?(\[[^]]+\]\s*)?(\w+)\s*",part) + assert m,part + if m[1]:direction,width=m[1],m[2] or "" + signals.append((direction,width,m[3])) + lines=["`timescale 1ns/1ps","module tb_board_cpu;", " reg clk=0;always #5 clk=~clk;", + " reg reset=1,uart_rx_in=1;"] + for _,width,name in signals: + if name not in ("clk","reset","uart_rx_in"):lines.append(f" wire {width}{name};") + lines += [" toy_a7_platform platform(.*);", " initial begin", + " repeat(10) @(negedge clk); force platform.loader.cpu_run=1;reset=0;end", + " integer cycles=0;", + " always @(posedge clk) if(!reset) begin", + " cycles<=cycles+1;", + " if(platform.memory_aw_valid && platform.memory_aw_bits_lock) $fatal(1,\"Unexpected AXI exclusive write\");", + " if(platform.memory_ar_valid && platform.memory_ar_bits_lock) $fatal(1,\"Unexpected AXI exclusive read\");", + " if(ddr_awvalid && ddr_awready && (ddr_awsize!=4 || ddr_awlen!=0)) $fatal(1,\"Narrow DDR write\");", + " if(ddr_arvalid && ddr_arready && (ddr_arsize!=4 || ddr_arlen!=0)) $fatal(1,\"Narrow DDR read\");", + " if(exited && (exit_code & 32'hffff0000)==32'hbad00000) $fatal(1,\"CPU oracle failed stage=%h\",exit_code);", + " if(exited && exit_code==32'h600d600d) begin", + ' $display("PASS CPU Sv39/FPU/AMO/cache/interrupt through board AXI/SCU cycles=%0d",cycles);$finish;end', + " if(cycles>4000000) $fatal(1,\"Board CPU watchdog\");", + " end"] + mapping={"awid":"aw_bits_id","awaddr":"aw_bits_addr","awlen":"aw_bits_len","awsize":"aw_bits_size", + "awburst":"aw_bits_burst","wdata":"w_bits_data","wstrb":"w_bits_strb","wlast":"w_bits_last", + "bid":"b_bits_id","bresp":"b_bits_resp","arid":"ar_bits_id","araddr":"ar_bits_addr", + "arlen":"ar_bits_len","arsize":"ar_bits_size","arburst":"ar_bits_burst","rid":"r_bits_id", + "rdata":"r_bits_data","rresp":"r_bits_resp","rlast":"r_bits_last"} + connections=[".clock(clk)",".reset(reset)"] + for _,_,name in signals: + if name.startswith("ddr_"): + suffix=name[4:] + connections.append(f".{mapping.get(suffix,suffix.replace('ready','_ready').replace('valid','_valid'))}({name})") + lines += [' axi_smoke_memory #(.ADDR_BITS(28),.BASE(0),.CAPACITY(262144),.IMAGE("smoke.hex")) memory (', + " "+",\n ".join(connections)+"\n );","endmodule"] + bench=OUT/"tb_board_cpu.sv" + bench.write_text("\n".join(lines)+"\n") + files=[ROOT/"build/serial-bound/ToyLinuxChip.sv",ROOT/"build/serial-bound/FpgaMemories.sv", + ROOT/"tests/axi_smoke_memory.sv",bench]+[p for p in (ROOT/"board").glob("*.sv") if p.name!="toy_a7_top.sv"] + with (OUT/"compile.log").open("w") as log: + subprocess.run(["verilator","--binary","--timing","-j","8","-Wno-fatal","-DSYNTHESIS", + "-DBUCKYBALL_DISABLE_DPI","--top-module","tb_board_cpu","--Mdir",str(OUT/"obj")]+[str(p) for p in files], + stdout=log,stderr=log,check=True,timeout=900) + result=subprocess.run([str(OUT/"obj/Vtb_board_cpu")],cwd=OUT,capture_output=True,text=True,timeout=180) + (OUT/"simulation.log").write_text(result.stdout+result.stderr) + print(result.stdout) + result.check_returncode() + assert "PASS CPU Sv39/FPU/AMO/cache/interrupt through board AXI/SCU" in result.stdout + record=dict(result="PASS",test=args.test,binary_sha256=hashlib.sha256(binary.read_bytes()).hexdigest(), + original_cpu_oracle=True,ddr_phy_simulated=False,physical_linux_boot_tested=False, + cycles=int(re.search(r"cycles=(\d+)",result.stdout)[1])) + (OUT/"RESULT.json").write_text(json.dumps(record,indent=2)+"\n") + + +if __name__=="__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/check_board_linux.py b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/check_board_linux.py new file mode 100644 index 0000000..9007ba9 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/check_board_linux.py @@ -0,0 +1,91 @@ +"""Boot OpenSBI/Linux/BusyBox on the actual core and board AXI/SCU RTL. + +The external DDR PHY/CDC is a stalled AXI memory model. Loader start is forced +only in this bench; commands enter through the real 1 Mbps UART receiver. +""" +import hashlib +import json +from pathlib import Path +import subprocess + +ROOT=Path(__file__).resolve().parents[1] +OUT=ROOT/"build/board-linux-final" + + +def main(): + OUT.mkdir(parents=True,exist_ok=True) + payload=ROOT/"build/board-software/fw_payload.bin" + # Chunked writes avoid creating a giant intermediate Python string. + with payload.open("rb") as src,(OUT/"payload.hex").open("w") as dst: + while data:=src.read(65536):dst.write("\n".join(f"{b:02x}" for b in data)+"\n") + bench=(ROOT/"build/board-cpu/tb_board_cpu.sv").read_text() + bench=bench.replace("tb_board_cpu","tb_board_linux") + bench=bench.replace("always #5 clk=~clk;", "always #20 clk=~clk;") + first=bench.index(" if(exited &&") + last=bench.index(" end\n axi_smoke_memory",first) + bench=bench[:first]+" if(cycles>500000000) $fatal(1,\"Linux cycle watchdog\");\n"+bench[last:] + bench=bench.replace(".CAPACITY(262144)",".CAPACITY(268435456)") + bench=bench.replace('"smoke.hex"','"payload.hex"') + console=''' + reg [255:0] tail=0; + reg init_seen=0,prompt_seen=0; + integer characters=0; + always @(posedge clk) if(!reset && platform.mmio_tx_valid && platform.tx_ready && cpu_run) begin + tail={tail[247:0],platform.mmio_tx_data};characters=characters+1; + $write("%c",platform.mmio_tx_data);$fflush(); + if(tail[95:0]=="init process") init_seen=1; + if(init_seen && tail[15:0]==16'h2320) prompt_seen=1; + if(tail[183:0]=="PASS LINUX_SYSTEM_CHECK") begin + $display("\\nPASS BOARD_LINUX_USERSPACE cycles=%0d characters=%0d",cycles,characters);$finish; + end + if(tail[95:0]=="Kernel panic") $fatal(1,"Kernel panic"); + end + task automatic send_byte(input [7:0] value); + @(negedge clk);uart_rx_in=0;repeat(25) @(negedge clk); + for(integer n=0;n<8;n=n+1) begin uart_rx_in=value[n];repeat(25) @(negedge clk);end + uart_rx_in=1;repeat(25) @(negedge clk); + // Allow the polled SBI/HVC console to drain its RAM-backed RX FIFO. + repeat(250000) @(negedge clk); + endtask + initial begin + wait(prompt_seen); + $display("\\nSIM_SHELL_PROMPT cycles=%0d",cycles);$fflush(); + send_byte("/");send_byte("r");send_byte("o");send_byte("o");send_byte("t");send_byte("/"); + send_byte("l");send_byte("i");send_byte("n");send_byte("u");send_byte("x");send_byte("_"); + send_byte("s");send_byte("y");send_byte("s");send_byte("t");send_byte("e");send_byte("m");send_byte("_"); + send_byte("c");send_byte("h");send_byte("e");send_byte("c");send_byte("k");send_byte("-"); + send_byte("l");send_byte("i");send_byte("n");send_byte("u");send_byte("x");send_byte(10); + $display("\\nSIM_COMMAND_SENT cycles=%0d overflow=%0d framing=%0d pending_rx=%0d",cycles, + platform.peripherals.overflow,platform.peripherals.framing,platform.peripherals.count);$fflush(); + if(platform.peripherals.overflow || platform.peripherals.framing) $fatal(1,"UART input loss"); + end +''' + bench=bench.replace("endmodule",console+"\nendmodule") + path=OUT/"tb_board_linux.sv" + path.write_text(bench) + files=[ROOT/"build/serial-bound/ToyLinuxChip.sv",ROOT/"build/serial-bound/FpgaMemories.sv", + ROOT/"tests/axi_smoke_memory.sv",path]+[p for p in (ROOT/"board").glob("*.sv") if p.name!="toy_a7_top.sv"] + with (OUT/"compile.log").open("w") as log: + subprocess.run(["verilator","--binary","--timing","-j","8","-Wno-fatal","-DSYNTHESIS", + "-DBUCKYBALL_DISABLE_DPI","--top-module","tb_board_linux","--Mdir",str(OUT/"obj")]+[str(p) for p in files], + stdout=log,stderr=log,check=True,timeout=900) + with (OUT/"simulation.log").open("w") as log: + result=subprocess.run([str(OUT/"obj/Vtb_board_linux")],cwd=OUT,stdout=log,stderr=log,timeout=3000) + transcript=(OUT/"simulation.log").read_text() + result.check_returncode() + required=["OpenSBI","Linux version","PASS VM_COPY_ON_WRITE","PASS VM_PAGE_PROTECTION", + "PASS FP64_PROCESS_CONTEXT","PASS LINUX_TIMER","PASS LINUX_SYSTEM_CHECK","PASS BOARD_LINUX_USERSPACE"] + for marker in required:assert marker in transcript,marker + record=dict(result="PASS_RTL_LINUX_USERSPACE",payload_sha256=hashlib.sha256(payload.read_bytes()).hexdigest(), + checks=required,physical_mig_simulated=False,physical_board_tested=False,uart_rx_command_tested=True) + (OUT/"RESULT.json").write_text(json.dumps(record,indent=2)+"\n") + print(transcript[-2000:]) + + +if __name__=="__main__": + try: + main() + except Exception as error: + OUT.mkdir(parents=True,exist_ok=True) + (OUT/"RESULT.json").write_text(json.dumps(dict(result="FAIL",error=str(error),physical_board_tested=False),indent=2)+"\n") + raise diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/check_board_mmio_error.py b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/check_board_mmio_error.py new file mode 100644 index 0000000..c354ba1 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/check_board_mmio_error.py @@ -0,0 +1,81 @@ +"""真实 CPU→SCU 错误响应回归；记录异常行为，不把总线错误等同于同步 trap。""" + +import argparse +import hashlib +import json +from pathlib import Path +import subprocess +import re +from offline_check import run_check + +ROOT = Path(__file__).resolve().parents[1] +OUT = ROOT / "build/board-mmio-error" + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--platform-file", type=Path, default=ROOT / "board/toy_a7_platform.sv") + args = parser.parse_args() + elf = OUT / "fault.elf" + subprocess.run(["riscv64-unknown-elf-gcc", "-nostdlib", "-nostartfiles", "-mcmodel=medany", + "-march=rv64imafdc_zicsr_zifencei", "-mabi=lp64d", "-Wl,--no-relax", + "-T", str(ROOT / "tests/cpu_smoke.ld"), str(ROOT / "tests/mmio_error.S"), "-o", str(elf)], check=True) + binary = OUT / "fault.bin" + subprocess.run(["riscv64-unknown-elf-objcopy", "-O", "binary", str(elf), str(binary)], check=True) + (OUT / "fault.hex").write_text("\n".join(f"{value:02x}" for value in binary.read_bytes()) + "\n") + bench = (ROOT / "build/board-cpu/tb_board_cpu.sv").read_text().replace("tb_board_cpu", "tb_mmio_error") + bench = bench.replace('"smoke.hex"', '"fault.hex"') + bench = bench.replace('$display("PASS CPU', 'if(bad_b!=1 || bad_r!=1) $fatal(1,"Fault did not traverse AXI/SCU");\n $display("PASS MMIO_ERROR CPU') + bench = bench.replace("PASS MMIO_ERROR CPU Sv39/FPU/AMO/cache/interrupt through board AXI/SCU", + "PASS MMIO_ERROR CPU AXI/SCU response delivery") + monitors = ''' + reg bad_write=0,bad_read=0; + integer bad_b=0,bad_r=0; + integer traps=-1; + always @(posedge clk) if(!reset) begin + if(exited && exit_code[31:16]==16'h7400 && traps<0) begin + traps=exit_code[15:0];$display("MMIO_SYNCHRONOUS_TRAPS %0d",traps); + end + if(platform.peripherals_aw_valid && platform.peripherals_aw_ready) + bad_write<=platform.peripherals_aw_bits_addr==31'h60030000; + if(platform.peripherals_ar_valid && platform.peripherals_ar_ready) + bad_read<=platform.peripherals_ar_bits_addr==31'h60030000; + if(platform.peripherals_b_valid && platform.peripherals_b_ready && bad_write) begin + if(platform.chip.peripherals_b_bits_resp!==2'b10) $fatal(1,"CPU did not receive SLVERR"); + bad_b<=bad_b+1;bad_write<=0; + end + if(platform.peripherals_r_valid && platform.peripherals_r_ready && bad_read) begin + if(platform.chip.peripherals_r_bits_resp!==2'b10) $fatal(1,"CPU did not receive read error"); + bad_r<=bad_r+1;bad_read<=0; + end + end +''' + bench = bench.replace("endmodule", monitors + "\nendmodule") + path = OUT / "tb_mmio_error.sv" + path.write_text(bench) + sources = [ROOT / "build/serial-bound/ToyLinuxChip.sv", ROOT / "build/serial-bound/FpgaMemories.sv", + ROOT / "tests/axi_smoke_memory.sv", path] + sources += [args.platform_file if p.name=="toy_a7_platform.sv" else p + for p in (ROOT / "board").glob("*.sv") if p.name != "toy_a7_top.sv"] + with (OUT / "compile.log").open("w") as log: + subprocess.run(["verilator", "--binary", "--timing", "-j", "4", "-Wno-fatal", "-DSYNTHESIS", + "-DBUCKYBALL_DISABLE_DPI", "--top-module", "tb_mmio_error", "--Mdir", str(OUT / "obj")] + + [str(p) for p in sources], stdout=log, stderr=log, check=True, timeout=900) + result = subprocess.run([str(OUT / "obj/Vtb_mmio_error")], cwd=OUT, capture_output=True, text=True, timeout=180) + (OUT / "simulation.log").write_text(result.stdout + result.stderr) + result.check_returncode() + if "PASS MMIO_ERROR CPU" not in result.stdout: + raise ValueError("Missing CPU fault oracle") + matches = re.findall(r"MMIO_SYNCHRONOUS_TRAPS (\d+)", result.stdout) + if len(matches) != 1: + raise ValueError("Missing synchronous-trap observation") + record = {"result": "PASS_CPU_MMIO_SLVERR", "physical_hardware_tested": False, + "synchronous_traps_observed": int(matches[0]), "synchronous_trap_guaranteed": False, + "invalid_address": "0x60030000", "required_read_write_response": "10", + "binary_sha256": hashlib.sha256(binary.read_bytes()).hexdigest()} + (OUT / "RESULT.json").write_text(json.dumps(record, indent=2) + "\n") + print(result.stdout) + + +if __name__ == "__main__": + run_check(main, OUT) diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/check_board_uart_boot.py b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/check_board_uart_boot.py new file mode 100644 index 0000000..92be1b1 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/check_board_uart_boot.py @@ -0,0 +1,162 @@ +"""Load, byte-verify and boot the original CPU oracle through actual UART RTL. + +Only the external DDR PHY is replaced with the stalled AXI memory model. No +testbench override releases the CPU and no initial image is put into DDR. +""" +import hashlib +import argparse +import json +from pathlib import Path +import re +import subprocess + +ROOT = Path(__file__).resolve().parents[1] +OUT = ROOT / "build/board-uart-boot" + +UART = r''' + reg [7:0] firmware[0:PROGRAM_BYTES-1]; + reg [7:0] reply_bytes[0:511]; + integer received=0; + reg run_requested=0; + initial $readmemh("program.hex",firmware); + // Independent receiver observes real TX transitions, not tx_valid/data. + always begin : receiver + reg [7:0] value; + @(negedge uart_tx_out); + repeat(37) @(negedge clk); + for(integer bit_index=0;bit_index<8;bit_index=bit_index+1) begin + value[bit_index]=uart_tx_out;repeat(25) @(negedge clk); + end + if(uart_tx_out!==1) $fatal(1,"UART TX framing error"); + if(!cpu_run) begin + if(received>=512) $fatal(1,"UART reply overflow"); + reply_bytes[received]=value;received=received+1; + end + end + always @(posedge clk) if(!reset && cpu_run && !run_requested) + $fatal(1,"CPU released before verified RUN request"); + function automatic [15:0] crc_step(input [15:0] previous,input [7:0] value); + reg [15:0] crc; + begin + crc=previous; + for(integer bit_index=7;bit_index>=0;bit_index=bit_index-1) + crc=(crc<<1)^((crc[15]^value[bit_index]) ? 16'h1021 : 16'd0); + crc_step=crc; + end + endfunction + task automatic send_byte(input [7:0] value); + @(negedge clk);uart_rx_in=0;repeat(25) @(negedge clk); + for(integer bit_index=0;bit_index<8;bit_index=bit_index+1) begin + uart_rx_in=value[bit_index];repeat(25) @(negedge clk); + end + uart_rx_in=1;repeat(25) @(negedge clk); + endtask + task automatic request(input [7:0] op,input integer offset,length,input bit corrupt); + reg [15:0] crc;reg [31:0] address;reg [7:0] value; + begin + received=0;crc=16'hffff;address=32'h80000000+offset; + send_byte(8'ha5);send_byte(8'h5a); + send_byte(op);crc=crc_step(crc,op); + send_byte(8'h37);crc=crc_step(crc,8'h37); + for(integer n=0;n<4;n=n+1) begin + value=address>>(8*n);send_byte(value);crc=crc_step(crc,value); + end + value=length&255;send_byte(value);crc=crc_step(crc,value); + value=(length>>8)&255;send_byte(value);crc=crc_step(crc,value); + if(op==1) for(integer n=0;n=length+9); + if(reply_bytes[0]!==8'h5a || reply_bytes[1]!==8'ha5 || reply_bytes[2]!==(op|8'h80) || + reply_bytes[3]!==8'h37 || reply_bytes[4]!==status || {reply_bytes[6],reply_bytes[5]}!==length) + $fatal(1,"UART reply header/status op=%h status=%h count=%0d",op,reply_bytes[4],received); + crc=16'hffff; + for(integer n=2;n256) count=256; + request(1,offset,count,0);reply(1,0,0); + request(2,offset,count,0);reply(2,0,count); + for(integer n=0;n4000000", "cycles>120000000") + bench = bench.replace("endmodule", f" localparam PROGRAM_BYTES={len(data)};\n" + UART + "\nendmodule") + path = OUT / "tb_board_uart_boot.sv" + path.write_text(bench) + core=ROOT/("build/flash-boot/ToyLinuxChip.sv" if args.flash_recovery else "build/serial-bound/ToyLinuxChip.sv") + files = [core, ROOT / "build/serial-bound/FpgaMemories.sv", + ROOT / "tests/axi_smoke_memory.sv", path] + files += [p for p in (ROOT / "board").glob("*.sv") if p.name != "toy_a7_top.sv"] + with (OUT / "compile.log").open("w") as log: + subprocess.run(["verilator", "--binary", "--timing", "-j", "8", "-Wno-fatal", "-DSYNTHESIS", + "-DBUCKYBALL_DISABLE_DPI", "--top-module", "tb_board_uart_boot", "--Mdir", str(OUT / "obj")] + + [str(p) for p in files], stdout=log, stderr=log, check=True, timeout=900,cwd=ROOT) + if args.flash_recovery: + # The bound ROM's readmemh path is relative to the platform directory. + import shutil + (OUT/"build/flash-boot").mkdir(parents=True,exist_ok=True) + shutil.copy2(ROOT/"build/flash-boot/bootrom.hex",OUT/"build/flash-boot/bootrom.hex") + with (OUT / "simulation.log").open("w") as log: + result = subprocess.run([str(OUT / "obj/Vtb_board_uart_boot")], cwd=OUT, + stdout=log, stderr=log, timeout=1200) + result.check_returncode() + transcript = (OUT / "simulation.log").read_text() + for marker in ("PASS UART_PAYLOAD_READBACK", "PASS UART_VERIFIED_RUN", "PASS CPU Sv39/FPU/AMO/cache/interrupt"): + assert marker in transcript, marker + record = dict(result="PASS_UART_LOAD_VERIFY_BOOT", binary_sha256=hashlib.sha256(data).hexdigest(), + bytes_verified=len(data), testbench_cpu_release_override=False, preloaded_ddr_image=False, + physical_mig_simulated=False, physical_board_tested=False, + flash_rom_recovery=args.flash_recovery, + cycles=int(re.search(r"through board AXI/SCU cycles=(\d+)", transcript)[1])) + (OUT / "RESULT.json").write_text(json.dumps(record, indent=2) + "\n") + print(transcript) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/check_core_units.py b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/check_core_units.py new file mode 100644 index 0000000..cb08165 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/check_core_units.py @@ -0,0 +1,73 @@ +"""重新生成并验证 PE、FMA、移位、RF、查询与 SubROB 单元；不连接硬件。""" + +import hashlib +import json +from pathlib import Path +import re +import subprocess +import sys +from offline_check import run_check + +ROOT = Path(__file__).resolve().parents[1] +OUT = ROOT / "build/core-unit-regressions" + + +def execute(name, command, marker=None, cwd=ROOT, timeout=900): + result = subprocess.run(command, cwd=cwd, capture_output=True, text=True, timeout=timeout) + (OUT / (name + ".log")).write_text(result.stdout + result.stderr) + result.check_returncode() + if marker and marker not in result.stdout: + raise ValueError(f"Missing passing marker: {name}") + return result.stdout + + +def unpack(path): + pieces = re.split(r'// ----- 8< ----- FILE "([^"]+)" ----- 8< -----', path.read_text()) + modules = [pieces[0]] + for name, body in zip(pieces[1::2], pieces[2::2]): + if name.endswith((".sv", ".v")): + modules.append(body) + elif name != "firrtl_black_box_resource_files.f": + raise ValueError("Unexpected emitted resource: " + name) + output = OUT / (path.stem + ".sv") + output.write_text("\n".join(modules)) + return output + + +def main(): + emitters = ["EmitPeChecks", "EmitFmaChecks", "EmitRoundShiftChecks", "EmitGroupQueryCheck", "EmitSubRobCheck"] + execute("elaboration", ["sbt", "-batch"] + ["runMain fpga.arty.linux." + name for name in emitters]) + records = {} + for label, raw, bench, marker in [ + ("round", "round-check/RoundShiftChecks.sv", "tb_round_shift.sv", "PASS ROUND_SHIFT"), + ("group", "group-query-check/GroupQueryCheck.sv", "tb_group_query.sv", "PASS: 256 concurrent group queries"), + ("subrob", "subrob-check/SubRobCheck.sv", "tb_subrob.sv", "PASS SUBROB")]: + rtl = unpack(ROOT / "build" / raw) + obj = OUT / (label + "-obj") + execute(label + "-compile", ["verilator", "--binary", "--timing", "--assert", "-j", "4", + "-Wno-fatal", "-DBUCKYBALL_DISABLE_DPI", "--top-module", "tb", "--Mdir", str(obj), + str(rtl), str(ROOT / "tests" / bench)]) + execute(label, [str(obj / "Vtb")], marker, timeout=120) + records[label] = "PASS" + fma = unpack(ROOT / "build/fma-check/FmaPrecisionCheck.sv") + obj = OUT / "fma-obj" + execute("fma-compile", ["verilator", "--cc", "--exe", "--build", "-j", "4", "-Wno-fatal", + "--top-module", "FmaPrecisionCheck", "--Mdir", str(obj), str(fma), + str(ROOT / "tests/fma_differential.cpp")]) + execute("fma", [str(obj / "VFmaPrecisionCheck")], "PASS FMA_SHARED", ROOT / "build/fma-check", 120) + records["fma"] = "PASS" + rf = OUT / "fpu-rf.vvp" + execute("rf-compile", ["iverilog", "-g2012", "-s", "tb", "-o", str(rf), + str(ROOT / "rtl/FpuRfOriginal.sv"), str(ROOT / "rtl/FpuRfLvt.sv"), str(ROOT / "tests/tb_fpu_rf.sv")]) + execute("rf", ["vvp", str(rf)], "PASS FPU_RF_LVT", timeout=120) + records["rf"] = "PASS" + execute("pe", [sys.executable, str(ROOT / "tests/check_pe.py")], "PASS original/LUT/DSP PE") + records["pe"] = "PASS" + record = {"result": "PASS_UNIT_REGRESSIONS", "physical_hardware_tested": False, "tests": records, + "generated_rtl": {path.name: hashlib.sha256(path.read_bytes()).hexdigest() for path in OUT.glob("*.sv")}} + (OUT / "RESULT.json").write_text(json.dumps(record, indent=2) + "\n") + print("PASS core units: PE/formal quantizer, FMA, round shift, FPU RF, group query and SubROB") + + +if __name__ == "__main__": + run_check(main, OUT) diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/check_flash_boot.py b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/check_flash_boot.py new file mode 100644 index 0000000..fbfa17f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/check_flash_boot.py @@ -0,0 +1,182 @@ +"""Real CPU executes ROM -> serial Flash -> decompression -> original oracle. + +DDR starts empty; no forced RUN or CPU reset bypass. SPI Flash and DDR PHY are +simulation models. Two corrupted images must halt in ROM without launching. +""" + +import argparse +import json +from pathlib import Path +import re +import subprocess + +ROOT = Path(__file__).resolve().parents[1] +OUT = ROOT / "build/flash-regression" + + +def main(): + p = argparse.ArgumentParser(description=__doc__) + p.add_argument( + "--image", type=Path, required=True, help="Packed original CPU smoke image" + ) + p.add_argument("--skip-build", action="store_true") + args = p.parse_args() + OUT.mkdir(parents=True, exist_ok=True) + image = args.image.read_bytes() + (OUT / "flash.hex").write_text("\n".join(f"{b:02x}" for b in image) + "\n") + text = (ROOT / "board/toy_a7_platform.sv").read_text() + header = text.split(") (", 1)[1].split(");", 1)[0] + signals = [] + direction, width = None, "" + for part in header.split(","): + m = re.fullmatch( + r"\s*(?:(input|output)\s+wire\s+)?(\[[^]]+\]\s*)?(\w+)\s*", part + ) + assert m, part + if m[1]: + direction, width = m[1], m[2] or "" + signals.append((direction, width, m[3])) + lines = [ + "`timescale 1ns/1ps", + "module tb_flash_boot;", + " reg clk=0;always #20 clk=~clk;", + " reg reset=1;", + " wire uart_rx_in=1,flash_recovery=0;", + ] + for _, width, name in signals: + if name not in ("clk", "reset", "uart_rx_in", "flash_recovery"): + lines.append(f" wire {width}{name};") + lines += [ + " toy_a7_platform #(.FLASH_BOOT(1)) platform(.*);", + " initial begin repeat(10) @(negedge clk);reset=0;end", + f' spi_flash_model #(.BYTES({len(image)}),.IMAGE("{OUT}/flash.hex")) flash', + " (.sck(flash_sck),.cs_n(flash_cs_n),.mosi(flash_mosi),.miso(flash_miso));", + " integer cycles=0;reg [255:0] tail=0;reg verified=0;", + " always @(posedge clk) if(!reset) begin", + " cycles<=cycles+1;", + " if(platform.mmio_tx_valid && platform.tx_ready) begin", + ' $write("%c",platform.mmio_tx_data);$fflush();', + " tail={tail[247:0],platform.mmio_tx_data};", + ' if(tail[175:0]=="PASS FLASH_PAYLOAD_CRC") verified=1;', + " end", + " if(exited && exit_code==32'h600d600d) begin", + ' if(!verified) $fatal(1,"Oracle ran before verified Flash payload");', + ' if($test$plusargs("bad_header") || $test$plusargs("bad_payload")) $fatal(1,"Corrupted image launched");', + ' $display("PASS FLASH_CPU_ORACLE cycles=%0d",cycles);$finish;end', + " if(exited && exit_code==32'hbad0f101) begin", + ' if(!$test$plusargs("bad_header") && !$test$plusargs("bad_payload")) $fatal(1,"Valid image rejected");', + ' if(verified) $fatal(1,"Corrupt image reported verified");', + ' $display("PASS FLASH_CORRUPTION_REJECTED cycles=%0d",cycles);$finish;end', + " if(exited && (exit_code & 32'hffff0000)==32'hbad00000 && exit_code!=32'hbad0f101)", + ' $fatal(1,"CPU/ROM trap %h",exit_code);', + ' if(cycles>40000000) $fatal(1,"Flash boot watchdog");', + " end", + ] + mapping = { + "awid": "aw_bits_id", + "awaddr": "aw_bits_addr", + "awlen": "aw_bits_len", + "awsize": "aw_bits_size", + "awburst": "aw_bits_burst", + "wdata": "w_bits_data", + "wstrb": "w_bits_strb", + "wlast": "w_bits_last", + "bid": "b_bits_id", + "bresp": "b_bits_resp", + "arid": "ar_bits_id", + "araddr": "ar_bits_addr", + "arlen": "ar_bits_len", + "arsize": "ar_bits_size", + "arburst": "ar_bits_burst", + "rid": "r_bits_id", + "rdata": "r_bits_data", + "rresp": "r_bits_resp", + "rlast": "r_bits_last", + } + connections = [".clock(clk)", ".reset(reset)"] + for _, _, name in signals: + if name.startswith("ddr_"): + s = name[4:] + connections.append( + f".{mapping.get(s,s.replace('ready','_ready').replace('valid','_valid'))}({name})" + ) + lines += [ + " axi_smoke_memory #(.ADDR_BITS(28),.BASE(0),.CAPACITY(268435456)) memory (", + " " + ",\n ".join(connections) + "\n );", + "endmodule", + ] + bench = OUT / "tb_flash_boot.sv" + bench.write_text("\n".join(lines) + "\n") + if not args.skip_build: + files = [ + ROOT / "build/flash-boot/ToyLinuxChip.sv", + ROOT / "build/serial-bound/FpgaMemories.sv", + ROOT / "tests/axi_smoke_memory.sv", + ROOT / "tests/spi_flash_model.sv", + bench, + ] + files += [f for f in (ROOT / "board").glob("*.sv") if f.name != "toy_a7_top.sv"] + with (OUT / "compile.log").open("w") as log: + subprocess.run( + [ + "verilator", + "--binary", + "--timing", + "-j", + "8", + "-Wno-fatal", + "-DSYNTHESIS", + "-DBUCKYBALL_DISABLE_DPI", + "--top-module", + "tb_flash_boot", + "--Mdir", + str(OUT / "obj"), + ] + + [str(f) for f in files], + stdout=log, + stderr=log, + check=True, + timeout=900, + cwd=ROOT, + ) + results = {} + for case in ("valid", "bad_header", "bad_payload"): + command = [str(OUT / "obj/Vtb_flash_boot")] + if case != "valid": + command.append("+" + case) + with (OUT / (case + ".log")).open("w") as log: + subprocess.run( + command, + cwd=ROOT, + stdout=log, + stderr=subprocess.STDOUT, + check=True, + timeout=300, + ) + output = (OUT / (case + ".log")).read_text() + print(output) + marker = ( + "PASS FLASH_CPU_ORACLE" + if case == "valid" + else "PASS FLASH_CORRUPTION_REJECTED" + ) + assert marker in output + results[case] = int(re.search(r"cycles=(\d+)", output)[1]) + (OUT / "RESULT.json").write_text( + json.dumps( + dict( + result="PASS", + cycles=results, + empty_ddr=True, + original_cpu_oracle=True, + forced_run=False, + physical_flash_tested=False, + ), + indent=2, + ) + + "\n" + ) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/check_flash_guards.py b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/check_flash_guards.py new file mode 100644 index 0000000..ce63561 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/check_flash_guards.py @@ -0,0 +1,48 @@ +"""验证普通模式与 python -O 下四项预打包镜像校验均有效。""" + +import hashlib +import json +from pathlib import Path +import subprocess +import sys +import tempfile +from offline_check import run_check + +ROOT = Path(__file__).resolve().parents[1] + + +def main(): + out = ROOT / "build/flash-guard-check" + out.mkdir(parents=True, exist_ok=True) + cases = [] + for optimized in [False, True]: + for field in [None, "result", "bitstream_sha256", "packed_payload_sha256", "flash_image_sha256"]: + with tempfile.TemporaryDirectory(dir=out) as directory: + work = Path(directory) + bit, payload, mcs = [work / name for name in ["chip.bit", "payload.bin", "image.mcs"]] + for path in [bit, payload, mcs]: + path.write_bytes(path.name.encode()) + sha = lambda path: hashlib.sha256(path.read_bytes()).hexdigest() + record = {"result": "PASS_VIVADO_FLASH_PACK", "bitstream_sha256": sha(bit), + "packed_payload_sha256": sha(payload), "flash_image_sha256": sha(mcs)} + if field: + record[field] = "FAILED" if field == "result" else "0" * 64 + mcs.with_suffix(".mcs.json").write_text(json.dumps(record)) + expected = "reject" if field else "accept" + command = [sys.executable] + (["-O"] if optimized else []) + command += [str(ROOT / "tests/flash_guard_probe.py"), str(ROOT / "host/flash.py"), + str(bit), str(payload), str(mcs), str(work / "run"), expected] + result = subprocess.run(command, capture_output=True, text=True, timeout=20) + name = f"{'optimized' if optimized else 'normal'}-{field or 'valid'}" + (out / f"{name}.log").write_text(result.stdout + result.stderr, encoding="utf-8") + result.check_returncode() + if ("PASS INVALID_IMAGE_BLOCKED" if field else "PASS VALID_IMAGE_REACHED_OFFLINE_BOUNDARY") not in result.stdout: + raise ValueError("Missing guard oracle") + cases.append({"optimized": optimized, "field": field or "valid", "result": "PASS"}) + (out / "RESULT.json").write_text(json.dumps({"result": "PASS_FLASH_GUARDS_NORMAL_AND_OPTIMIZED", + "physical_hardware_tested": False, "cases": cases}, indent=2) + "\n") + print(f"PASS Flash image guards: {len(cases)} normal/-O tamper/control cases; no hardware") + + +if __name__ == "__main__": + run_check(main, ROOT / "build/flash-guard-check") diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/check_globalrob.py b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/check_globalrob.py new file mode 100644 index 0000000..d563932 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/check_globalrob.py @@ -0,0 +1,64 @@ +"""核验同步 RAM 与原寄存器路径逐周期等价，包括背压、绕回和中途复位。""" + +import argparse +import hashlib +import json +from pathlib import Path +import re +import subprocess + +ROOT = Path(__file__).resolve().parents[1] + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--skip-elaboration", action="store_true") + args = parser.parse_args() + out = ROOT / "build/globalrob-check" + out.mkdir(parents=True, exist_ok=True) + commands = [] + if not args.skip_elaboration: + commands.append((["sbt", "-batch", "runMain fpga.arty.linux.EmitGlobalRobCheck"], + "elaboration.log", 900)) + for command, name, timeout in commands: + with (out / name).open("w") as log: + subprocess.run(command, cwd=ROOT, stdout=log, stderr=subprocess.STDOUT, + timeout=timeout, check=True) + # CIRCT appends named inline resources and the .f index to one emission. + # Keep the untouched emission, compile only Verilog sections. + parts = re.split(r'// ----- 8< ----- FILE "([^"]+)" ----- 8< -----', + (out / "GlobalRobCheck.sv").read_text()) + modules = [parts[0]] + for name, body in zip(parts[1::2], parts[2::2]): + if name.endswith((".sv", ".v")): + modules.append(body) + elif name == "firrtl_black_box_resource_files.f": + if not all(line.strip().endswith(".v") for line in body.splitlines() if line.strip()): + raise ValueError("Unexpected inline resource index") + else: + raise ValueError("Unexpected emitted resource: " + name) + rtl = out / "GlobalRobCheck.sim.sv" + rtl.write_text("\n".join(modules)) + commands = [(["verilator", "--binary", "--timing", "--assert", "-j", "4", "-Wno-fatal", + "-DBUCKYBALL_DISABLE_DPI", "--top-module", "tb", "--Mdir", str(out / "obj"), + str(rtl), str(ROOT / "tests/tb_globalrob.sv")], + "compile.log", 600), + ([str(out / "obj/Vtb")], "simulation.log", 60)] + for command, name, timeout in commands: + with (out / name).open("w") as log: + subprocess.run(command, cwd=ROOT, stdout=log, stderr=subprocess.STDOUT, + timeout=timeout, check=True) + transcript = (out / "simulation.log").read_text() + if "PASS GLOBALROB RAM/register cycle comparison" not in transcript: + raise ValueError("GlobalROB passing marker missing") + record = {"result": "PASS", "cycle_equivalence": True, + "coverage": ["accepted operand integrity", "ROB full", "pointer wrap", + "issue backpressure", "SubROB ownership stall", "mid-flight resets", + "concurrent allocation/issue/completion", "complete drain"], + "rtl_sha256": hashlib.sha256((out / "GlobalRobCheck.sv").read_bytes()).hexdigest()} + (out / "RESULT.json").write_text(json.dumps(record, indent=2) + "\n") + print(transcript) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/check_platform_mutations.py b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/check_platform_mutations.py new file mode 100644 index 0000000..203194c --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/check_platform_mutations.py @@ -0,0 +1,56 @@ +"""只在 build 中注入 RTL 错误，核验 AXI 用例的检错能力；不改生产源码。""" + +import hashlib +import json +from pathlib import Path +import subprocess +from offline_check import run_check + +ROOT = Path(__file__).resolve().parents[1] +OUT = ROOT / "build/backpressure-mutation" +OLD = ROOT / "evidence/2026-10-12/pr10-review" + + +def main(): + original = (ROOT / "board/axi_scu.sv").read_text() + condition = "if(bvalid && bready) bvalid<=0;" + if original.count(condition) != 1: + raise ValueError("SCU mutation target changed; review this oracle") + mutant = OUT / "scu-mutant.sv" + mutant.write_text(original.replace(condition, "if(bvalid) bvalid<=0;")) + common = [ROOT / "board" / name for name in + ["axi_fullwidth.sv", "ddr_uart_loader.sv", "loader_axi.sv", + "uart_rx.sv", "uart_tx.sv", "flash_spi_byte.sv"]] + common += [ROOT / "tests/ToyLinuxChipPorts.sv"] + cases = [] + inputs = [("old-test", ROOT / "board/toy_a7_platform.sv", mutant, + OLD / "sources/tests/tb_platform_bresp.sv", 0), + ("new-test", ROOT / "board/toy_a7_platform.sv", mutant, + ROOT / "tests/tb_platform_bresp.sv", 1), + ("old-response", OLD / "old-platform.sv", ROOT / "board/axi_scu.sv", + ROOT / "tests/tb_platform_bresp.sv", 1)] + for label, platform, scu, bench, expected in inputs: + executable = OUT / label + sources = [platform, scu, bench] + common + compiled = subprocess.run(["iverilog", "-g2012", "-s", "tb_platform_bresp", "-o", + str(executable)] + [str(path) for path in sources], + capture_output=True, text=True, timeout=60) + (OUT / (label + "-compile.log")).write_text(compiled.stdout + compiled.stderr) + compiled.check_returncode() + result = subprocess.run(["vvp", str(executable)], capture_output=True, text=True, timeout=60) + log = result.stdout + result.stderr + (OUT / (label + ".log")).write_text(log) + marker = {"old-test": "PASS platform AXI B response", "new-test": "valid=0", + "old-response": "actual=01 expected=10"}[label] + if result.returncode != expected or marker not in log: + raise ValueError(f"Mutation oracle failed: {label}: {log}") + cases.append({"case": label, "exit_code": result.returncode, "expected_exit_code": expected, + "result": "PASS", "sources": {path.relative_to(ROOT).as_posix(): + hashlib.sha256(path.read_bytes()).hexdigest() for path in sources}}) + record = {"result": "PASS_MUTATION_ORACLES", "physical_hardware_tested": False, "cases": cases} + (OUT / "RESULT.json").write_text(json.dumps(record, indent=2) + "\n") + print("PASS mutation oracles: old test misses premature BVALID drop; new test rejects it and old response bug") + + +if __name__ == "__main__": + run_check(main, OUT) diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/check_programming_scripts.py b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/check_programming_scripts.py new file mode 100644 index 0000000..9e248c0 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/check_programming_scripts.py @@ -0,0 +1,57 @@ +"""离线注入 Vivado API 返回值、异常与配置状态，检查实际 Tcl 入口。""" + +import argparse +import json +from pathlib import Path +import shutil +import subprocess +import tempfile +from offline_check import run_check + +ROOT = Path(__file__).resolve().parents[1] + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--tclsh", default=shutil.which("tclsh")) + args = parser.parse_args() + if not args.tclsh: + raise RuntimeError("Install Tcl or supply --tclsh") + out = ROOT / "build/programming-check" + out.mkdir(parents=True, exist_ok=True) + cases = [] + for script in ["program_arty.tcl", "backup_flash.tcl", "program_flash.tcl"]: + faults = ["none", "device_error", "done_low", "eos_low", "crc_error"] + if script != "program_arty.tcl": + faults += ["readback_error", "short_backup"] + if script == "program_flash.tcl": + faults += ["cfgmem_error"] + for fault in faults: + with tempfile.TemporaryDirectory(dir=out) as directory: + work = Path(directory) + bit = work / "input.bit" + bit.write_bytes(b"offline fixture") + command = [args.tclsh, str(ROOT / "tests/mock_programming.tcl"), + str(ROOT / "board" / script), fault, str(bit), str(work / "backup.bin")] + result = subprocess.run(command, capture_output=True, text=True, timeout=20) + transcript = result.stdout + result.stderr + (out / f"{script}-{fault}.log").write_text(transcript, encoding="utf-8") + if fault == "none": + if result.returncode or "MOCK_SUCCESS" not in transcript: + raise ValueError(f"Documented success return rejected: {script}: {transcript}") + else: + if result.returncode == 0 or "MOCK_FAILURE" not in transcript: + raise ValueError(f"Injected failure accepted: {script}/{fault}") + if "PASS FLASH_PROGRAM_VERIFY" in transcript or "ARTY_JTAG_PROGRAMMED:" in transcript: + raise ValueError("False success marker") + if fault != "cfgmem_error" and "program_flash" in transcript.split("MOCK_EVENTS", 1)[1].splitlines()[0]: + raise ValueError("Flash programming reached after an earlier failure") + cases.append({"script": script, "fault": fault, "result": "PASS"}) + record = {"result": "PASS_OFFLINE_TCL_CONTRACTS", "physical_hardware_tested": False, + "cases": cases} + (out / "RESULT.json").write_text(json.dumps(record, indent=2) + "\n") + print(f"PASS programming scripts: {len(cases)} documented-return/status/error cases; no hardware") + + +if __name__ == "__main__": + run_check(main, ROOT / "build/programming-check") diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/check_runner_status.py b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/check_runner_status.py new file mode 100644 index 0000000..14846cb --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/check_runner_status.py @@ -0,0 +1,71 @@ +"""注入检查失败，验证三种实际入口不会遗留上次 PASS；不连接硬件。""" + +import argparse +import hashlib +import json +from pathlib import Path +import shutil +import subprocess +import sys +import tempfile +from offline_check import run_check + +ROOT = Path(__file__).resolve().parents[1] +OUT = ROOT / "build/runner-status-check" + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--baseline-ref", help="仅用旧源码反测，预期复现遗留 PASS") + args = parser.parse_args() + OUT.mkdir(parents=True, exist_ok=True) + cases = [] + runners = [("check_board.py", "board-unit", "PASS"), + ("check_programming_scripts.py", "programming-check", "PASS_OFFLINE_TCL_CONTRACTS"), + ("check_flash_guards.py", "flash-guard-check", "PASS_FLASH_GUARDS_NORMAL_AND_OPTIMIZED")] + for script, directory, old_pass in runners: + source = ROOT / "scripts" / script + data = source.read_bytes() if not args.baseline_ref else subprocess.check_output( + ["git", "show", f"{args.baseline_ref}:platforms/arty-a7-toy/scripts/{script}"], cwd=ROOT) + with tempfile.TemporaryDirectory(dir=OUT) as temporary: + work = Path(temporary) + (work / "scripts").mkdir() + (work / "tests").mkdir() + (work / "scripts" / script).write_bytes(data) + helper = ROOT / "scripts/offline_check.py" + if helper.exists(): + shutil.copy2(helper, work / "scripts/offline_check.py") + result_file = work / "build" / directory / "RESULT.json" + result_file.parent.mkdir(parents=True) + result_file.write_text(json.dumps({"result": old_pass})) + if script == "check_board.py": + (work / "tests/PLATFORM_PORTS_MANIFEST.json").write_text(json.dumps({"stub_sha256": "0" * 64})) + (work / "tests/ToyLinuxChipPorts.sv").write_text("// injected fixture mismatch\n") + extra = [] + elif script == "check_programming_scripts.py": + # A child fails before any hardware operation; Python is the injected interpreter. + (work / "tests/mock_programming.tcl").write_text("raise RuntimeError('INJECTED_CHECK_FAILURE')\n") + extra = ["--tclsh", sys.executable] + else: + (work / "tests/flash_guard_probe.py").write_text("raise RuntimeError('INJECTED_CHECK_FAILURE')\n") + extra = [] + process = subprocess.run([sys.executable, str(work / "scripts" / script)] + extra, + capture_output=True, text=True, timeout=30) + status = json.loads(result_file.read_text()) + log = process.stdout + process.stderr + "\nOBSERVED_RESULT " + json.dumps(status) + "\n" + (OUT / (script + ".log")).write_text(log, encoding="utf-8") + if process.returncode == 0: + raise ValueError("Failure injection did not reach the actual runner") + expected = old_pass if args.baseline_ref else "FAILED" + if status["result"] != expected: + raise ValueError(f"{script}: expected {expected}, got {status}") + cases.append({"script": script, "source_sha256": hashlib.sha256(data).hexdigest(), + "exit_code": process.returncode, "observed_result": status["result"], "result": "PASS"}) + record = {"result": "PASS_EXPECTED_STALE_BASELINE" if args.baseline_ref else "PASS_RUNNER_FAILURE_STATUS", + "baseline_ref": args.baseline_ref, "physical_hardware_tested": False, "cases": cases} + (OUT / "RESULT.json").write_text(json.dumps(record, indent=2) + "\n") + print(f"PASS runner failure status: {len(cases)} actual entrypoints; baseline={args.baseline_ref or 'current'}") + + +if __name__ == "__main__": + run_check(main, OUT) diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/elaborate.sh b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/elaborate.sh new file mode 100644 index 0000000..a80d469 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/elaborate.sh @@ -0,0 +1,12 @@ +#!/usr/bin/env bash +set -euo pipefail +cd "$(dirname "$0")/.." +python3 scripts/prepare_sources.py "$@" +python3 scripts/resolve_config.py +sbt -batch 'runMain fpga.arty.linux.EmitToyLinux build/serial-raw --fpga-memories --serial-fpga' \ + 'runMain fpga.arty.linux.EmitToyLinux build/serial-reference --serial-fpga' \ + 'runMain fpga.arty.linux.EmitRoutingCheck build/routing-check' +python3 scripts/prepare_fpga_memories.py build/serial-raw/ToyLinuxChip.sv --output-dir build/serial-bound +python3 scripts/bind_fpu_rf.py +python3 scripts/export_capabilities.py +python3 scripts/verify_target.py --core diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/elaborate_rob_candidate.sh b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/elaborate_rob_candidate.sh new file mode 100644 index 0000000..f89674c --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/elaborate_rob_candidate.sh @@ -0,0 +1,13 @@ +#!/usr/bin/env bash +set -euo pipefail +cd "$(dirname "$0")/.." +python3 scripts/prepare_sources.py "$@" +python3 scripts/resolve_config.py +python3 scripts/check_globalrob.py +sbt -Dfpga.robOperandRam=true -batch \ + 'runMain fpga.arty.linux.EmitToyLinux build/serial-raw --fpga-memories --serial-fpga' \ + 'runMain fpga.arty.linux.EmitToyLinux build/serial-reference --serial-fpga' \ + 'runMain fpga.arty.linux.EmitRoutingCheck build/routing-check' +python3 scripts/prepare_rob_candidate.py \ + --baseline-memory-manifest evidence/2026-10-11/MEMORY_MANIFEST.json +python3 scripts/export_capabilities.py diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/export_capabilities.py b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/export_capabilities.py new file mode 100644 index 0000000..a68349c --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/export_capabilities.py @@ -0,0 +1,52 @@ +"""Export software instruction definitions from the actual elaborated profile.""" + +import json +from pathlib import Path + +ROOT = Path(__file__).resolve().parents[1] +profile = json.loads((ROOT / "build/serial-raw/ToyLinuxChip.profile.json").read_text()) +original = json.loads((ROOT / "build/original-toy.json").read_text()) +entries = original["accelerator"]["ballDomain"]["ballISA"] +supported = set(profile["ball_funct7"]) +retained = [e for e in entries if e["funct7"] in supported] +assert {e["funct7"] for e in retained} == supported +assert all(e["bid"] in profile["ball_ids"] for e in retained) +out = ROOT / "build/software" +out.mkdir(parents=True, exist_ok=True) +header = ["#ifndef TOY_FPGA_BALL_ISA_H", "#define TOY_FPGA_BALL_ISA_H"] +header += [f"#define BB_FUNC7_{e['mnemonic']} {e['funct7']}" for e in retained] +header += ["#endif", ""] +(out / "ballISA.h").write_text("\n".join(header), encoding="utf-8", newline="\n") +(out / "CAPABILITIES.json").write_text( + json.dumps( + { + "balls": profile["ball_names"], + "gemmini_dimension": profile["gemmini_rows"], + "physical_bank_count": profile["bank_count"], + "virtual_bank_count": profile["virtual_bank_count"], + "bank_entries": profile["bank_rows"], + "bank_width": profile["bank_width"], + "l2_present": False, + "coherence_manager": profile["coherence_manager"], + "ball_isa": retained, + "removed_ball_isa": [e for e in entries if e["funct7"] not in supported], + "mvin_mmio_supported": profile["accelerator_mmio_scale_pool"], + "automatic_software_emulation": False, + "unsupported_rocc_instruction_trap_guaranteed": False, + }, + indent=2, + ) + + "\n", + encoding="utf-8", + newline="\n", +) +(out / "params.h").write_text( + f"#define BANK_WIDTH {profile['bank_width']}\n" + f"#define VIRTUAL_BANK_NUM {profile['virtual_bank_count']}\n" + f"#define PHYSICAL_BANK_NUM {profile['bank_count']}\n" + f"#define BANK_ENTRIES {profile['bank_rows']}\n" + f"#define GEMMINI_DIM {profile['gemmini_rows']}\n", + encoding="utf-8", + newline="\n", +) +print(f"Exported {len(retained)} Ball opcodes from the elaborated profile") diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/make_flash_image.py b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/make_flash_image.py new file mode 100644 index 0000000..58fcd3d --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/make_flash_image.py @@ -0,0 +1,69 @@ +"""Use Vivado to pack Flash, then record hashes for a separate programming host.""" + +import argparse +import hashlib +import json +from pathlib import Path +import subprocess + +ROOT = Path(__file__).resolve().parents[1] + + +def sha(path): + return hashlib.sha256(path.read_bytes()).hexdigest() + + +def main(): + p = argparse.ArgumentParser(description=__doc__) + p.add_argument("--vivado", default="vivado") + p.add_argument("--bitstream", required=True, type=Path) + p.add_argument("--payload", required=True, type=Path) + p.add_argument("--out", required=True, type=Path) + args = p.parse_args() + bit, payload, out = ( + args.bitstream.resolve(), + args.payload.resolve(), + args.out.resolve(), + ) + out.parent.mkdir(parents=True, exist_ok=True) + command = [ + args.vivado, + "-mode", + "batch", + "-source", + str(ROOT / "board/make_flash_image.tcl"), + "-log", + str(out.with_suffix(".log")), + "-journal", + str(out.with_suffix(".jou")), + "-tclargs", + str(bit), + str(payload), + str(out), + ] + with out.with_suffix(".console.log").open("w") as log: + subprocess.run( + command, + cwd=ROOT, + stdout=log, + stderr=subprocess.STDOUT, + check=True, + timeout=180, + ) + record = dict( + result="PASS_VIVADO_FLASH_PACK", + bitstream_sha256=sha(bit), + packed_payload_sha256=sha(payload), + flash_image_sha256=sha(out), + configuration_offset=0, + software_offset=0x400000, + flash_bytes=0x1000000, + ) + out.with_suffix(out.suffix + ".json").write_text( + json.dumps(record, indent=2) + "\n" + ) + print(json.dumps(record, indent=2)) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/offline_check.py b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/offline_check.py new file mode 100644 index 0000000..2b02125 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/offline_check.py @@ -0,0 +1,23 @@ +"""离线检查启动时撤销旧 PASS，失败时保存本轮状态。""" + +import json +from pathlib import Path + + +def run_check(main, directory): + directory = Path(directory) + directory.mkdir(parents=True, exist_ok=True) + result = directory / "RESULT.json" + + def publish(record): + temporary = result.with_suffix(".tmp") + temporary.write_text(json.dumps(record, indent=2) + "\n", encoding="utf-8") + temporary.replace(result) + + publish({"result": "RUNNING", "physical_hardware_tested": False}) + try: + main() + except (Exception, KeyboardInterrupt) as error: + publish({"result": "FAILED", "physical_hardware_tested": False, + "error_type": type(error).__name__, "error": str(error)}) + raise diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/prepare_flash_boot.py b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/prepare_flash_boot.py new file mode 100644 index 0000000..0fed787 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/prepare_flash_boot.py @@ -0,0 +1,123 @@ +"""Pack an unchanged payload as LZ4 and bind only the boot-ROM module. + +The 4 MiB configuration partition and 12 MiB software partition cannot overlap. +Dependencies: lz4==4.4.5. Compile boot/flash_boot.c and flash_start.S separately. +""" + +import argparse +import hashlib +import json +from pathlib import Path +import re +import struct +import zlib + +ROOT = Path(__file__).resolve().parents[1] +CORE_SHA = "4c6aacf64660bbbf14b1114e8d5e4439d6a4e1427aaf1f681c6a4f618f2d2779" + + +def sha(data): + return hashlib.sha256(data).hexdigest() + + +def main(): + p = argparse.ArgumentParser(description=__doc__) + p.add_argument("--payload", type=Path, required=True) + p.add_argument("--boot-bin", type=Path, required=True) + p.add_argument( + "--core", type=Path, default=ROOT / "build/serial-bound/ToyLinuxChip.sv" + ) + p.add_argument("--out", type=Path, default=ROOT / "build/flash-boot") + args = p.parse_args() + import lz4 + import lz4.block + + raw = args.payload.read_bytes() + if not 0 < len(raw) <= 0x0F000000: + raise ValueError("Payload overlaps the boot stack reservation") + packed = lz4.block.compress( + raw, mode="high_compression", compression=12, store_size=False + ) + assert lz4.block.decompress(packed, uncompressed_size=len(raw)) == raw + head = struct.pack( + "<8s5I", b"TOYFLZ4\0", 1, len(packed), len(raw), zlib.crc32(raw), 0 + ) + image = head + struct.pack(" 0xC00000: + raise ValueError("Compressed software exceeds the 12 MiB partition") + original_bytes = args.core.read_bytes() + assert ( + sha(original_bytes) == CORE_SHA + ), "Unexpected core: use the pinned validated generation" + original = original_bytes.decode() + matches = list(re.finditer(r"^module TLROM\(.*?^endmodule", original, re.M | re.S)) + assert len(matches) == 1 + m = matches[0] + original_rom = m.group() + words = re.findall(r"64'h([0-9A-Fa-f]+)", original_rom.split("TLMonitor")[0]) + rom_bytes = b"".join(int(w, 16).to_bytes(8, "little") for w in words[::-1]) + dtb_start = rom_bytes.index(bytes.fromhex("d00dfeed")) + dtb_size = int.from_bytes(rom_bytes[dtb_start + 4 : dtb_start + 8], "big") + dtb = rom_bytes[dtb_start : dtb_start + dtb_size] + assert len(dtb) == dtb_size and dtb_size <= 4096 + boot = args.boot_bin.read_bytes() + assert 0 < len(boot) <= 4096 + rom = boot.ljust(4096, b"\0") + dtb.ljust(4096, b"\0") + replacement = original_rom.split(");", 1)[0] + """ +); + (* rom_style="block" *) reg [63:0] contents [0:1023]; + initial $readmemh("build/flash-boot/bootrom.hex", contents); + reg valid; + reg [1:0] response_size; + reg [6:0] response_source; + reg [63:0] response_data; + assign auto_in_a_ready=!valid || auto_in_d_ready; + assign auto_in_d_valid=valid; + assign auto_in_d_bits_size=response_size; + assign auto_in_d_bits_source=response_source; + assign auto_in_d_bits_data=response_data; + always @(posedge clock) begin + if(reset) valid<=0; + else if(auto_in_a_ready) valid<=auto_in_a_valid; + if(auto_in_a_ready && auto_in_a_valid) begin + response_size<=auto_in_a_bits_size;response_source<=auto_in_a_bits_source; + response_data<=|auto_in_a_bits_address[15:13] ? 64'd0 : contents[auto_in_a_bits_address[12:3]]; + end + end +endmodule""" + adapted = original[: m.start()] + replacement + original[m.end() :] + assert adapted.replace(replacement, original_rom, 1) == original + args.out.mkdir(parents=True, exist_ok=True) + (args.out / "flash_payload.bin").write_bytes(image) + (args.out / "bootrom.hex").write_text( + "\n".join( + f"{int.from_bytes(rom[i:i+8], 'little'):016x}" + for i in range(0, len(rom), 8) + ) + + "\n" + ) + (args.out / "ToyLinuxChip.sv").write_text(adapted, encoding="utf-8", newline="\n") + record = dict( + payload_bytes=len(raw), + payload_sha256=sha(raw), + lz4_bytes=len(packed), + flash_image_bytes=len(image), + flash_offset=0x400000, + flash_bytes=0x1000000, + lz4_version=lz4.__version__, + boot_code_bytes=len(boot), + boot_sha256=sha(boot), + original_core_sha256=sha(original_bytes), + adapted_core_sha256=sha(adapted.encode()), + only_module_replaced="TLROM", + dtb_sha256=sha(dtb), + dtb_address="0x11000", + rom_bytes=len(rom), + payload_crc32=f"{zlib.crc32(raw):08x}", + ) + (args.out / "MANIFEST.json").write_text(json.dumps(record, indent=2) + "\n") + print(json.dumps(record, indent=2)) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/prepare_fpga_memories.py b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/prepare_fpga_memories.py new file mode 100644 index 0000000..049f434 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/prepare_fpga_memories.py @@ -0,0 +1,197 @@ +"""Bind CIRCT 1RW and 1R1W SRAM macros to synchronous FPGA RAM templates. + +The emitted CPU/operator RTL is not rewritten. Only compiler-declared external +memory modules receive implementations. Undefined read results during a write +or disabled cycle hold their previous value. No memory contents are reset. +""" + +import argparse +import hashlib +import json +import re +from pathlib import Path + + +def unpack_emission(raw): + parts = re.split(r'// ----- 8< ----- FILE "([^"]+)" ----- 8< -----', raw) + rtl = [parts[0]] + metadata = None + config = None + for name, body in zip(parts[1::2], parts[2::2]): + if name.endswith((".sv", ".v")): + rtl.append(body) + elif name == "metadata/seq_mems.json": + assert metadata is None + metadata = json.loads(body) + elif name.endswith("/memories.conf"): + assert config is None + config = body.strip() + "\n" + elif name == "firrtl_black_box_resource_files.f": + assert all(x.strip().endswith(".v") for x in body.splitlines() if x.strip()) + else: + raise ValueError(f"Unrecognized emitted section: {name}") + assert metadata and config, "Elaborate with --fpga-memories first" + return "\n".join(rtl), metadata, config + + +def validate(metadata, config): + entries = {} + for line in config.splitlines(): + words = line.split() + assert len(words) % 2 == 0 + row = dict(zip(words[::2], words[1::2])) + assert set(row) <= {"name", "depth", "width", "ports", "mask_gran"} + assert row["ports"] in ("rw", "mrw", "write,read", "mwrite,read"), row + assert row["name"] not in entries + entries[row["name"]] = row + assert len(entries) == len(metadata) + for mem in metadata: + name = mem["module_name"] + assert re.fullmatch(r"[A-Za-z_][A-Za-z0-9_]*", name) + topology = (mem["read"], mem["write"], mem["readwrite"]) + assert topology in ((0, 0, 1), (1, 1, 0)) + assert not mem["extra_ports"] + row = entries[name] + assert int(row["depth"]) == mem["depth"] > 1 + assert int(row["width"]) == mem["width"] > 0 + assert (row["ports"] in ("mrw", "mwrite,read")) == mem["masked"] + assert ("," in row["ports"]) == (topology == (1, 1, 0)) + if mem["masked"]: + gran = mem["mask_granularity"] + assert int(row["mask_gran"]) == gran and mem["width"] % gran == 0 + + +def emit_dual_memory(mem, style): + name, depth, width = (mem[k] for k in ("module_name", "depth", "width")) + gran = mem.get("mask_granularity", width) + lanes = width // gran + addr = (depth - 1).bit_length() + mask = f",\n input [{lanes-1}:0] W0_mask" if mem["masked"] else "" + lines = [ + f"""module {name}( + input [{addr-1}:0] R0_addr, + input R0_en, R0_clk, + output reg [{width-1}:0] R0_data, + input [{addr-1}:0] W0_addr, + input W0_en, W0_clk, + input [{width-1}:0] W0_data{mask} +);""" + ] + # Split non-native masks into independent RAM lanes; keep both clocks. + write_enable = "W0_en && W0_mask[lane]" if mem["masked"] else "W0_en" + lines += [ + f" for (genvar lane = 0; lane < {lanes}; lane = lane + 1) begin : lanes", + f' (* ram_style = "{style}" *) reg [{gran-1}:0] ram [0:{depth-1}];', + " always @(posedge W0_clk)", + f" if ({write_enable}) ram[W0_addr] <= W0_data[lane*{gran} +: {gran}];", + " always @(posedge R0_clk)", + f" if (R0_en) R0_data[lane*{gran} +: {gran}] <= ram[R0_addr];", + " end", + "endmodule", + "", + ] + return "\n".join(lines), style + + +def emit_memory(mem, force_block=False): + name, depth, width = (mem[k] for k in ("module_name", "depth", "width")) + gran = mem.get("mask_granularity", width) + lanes = width // gran + addr = (depth - 1).bit_length() + # A 64-row bank fits one LUT RAM per bit. Avoid wasting deep BRAM blocks + # on shallow tags, MMIO banks and SubROB; keep 1024-row data banks in BRAM. + style = "block" if force_block else "distributed" if depth <= 64 else "block" + if mem["read"] == 1: + return emit_dual_memory(mem, style) + ports = [ + f" input [{addr-1}:0] RW0_addr", + " input RW0_en, RW0_clk, RW0_wmode", + f" input [{width-1}:0] RW0_wdata", + f" output reg [{width-1}:0] RW0_rdata", + ] + if mem["masked"]: + ports.append(f" input [{lanes-1}:0] RW0_wmask") + lines = [f"module {name}(" + ",\n".join(ports) + "\n);"] + # Native byte masks share a wide array. Other mask widths get independent + # arrays so e.g. 17-bit L2 tags never require unsupported byte enables. + if not mem["masked"] or gran in (8, 9): + lines += [ + f' (* ram_style = "{style}" *) reg [{width-1}:0] ram [0:{depth-1}];', + " always @(posedge RW0_clk) begin", + " if (RW0_en) begin", + " if (RW0_wmode) begin", + ] + if mem["masked"]: + lines += [ + f" for (integer lane = 0; lane < {lanes}; lane = lane + 1)", + " if (RW0_wmask[lane])", + f" ram[RW0_addr][lane*{gran} +: {gran}] <= " + f"RW0_wdata[lane*{gran} +: {gran}];", + ] + else: + lines.append(" ram[RW0_addr] <= RW0_wdata;") + lines += [ + " end else RW0_rdata <= ram[RW0_addr];", + " end", + " end", + ] + else: + lines += [ + f" for (genvar lane = 0; lane < {lanes}; lane = lane + 1) begin : lanes", + f' (* ram_style = "{style}" *) reg [{gran-1}:0] ram [0:{depth-1}];', + " always @(posedge RW0_clk) begin", + " if (RW0_en) begin", + " if (RW0_wmode) begin", + " if (RW0_wmask[lane]) ram[RW0_addr] <= " + f"RW0_wdata[lane*{gran} +: {gran}];", + f" end else RW0_rdata[lane*{gran} +: {gran}] <= ram[RW0_addr];", + " end", + " end", + " end", + ] + return "\n".join(lines + ["endmodule", ""]), style + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("emission", type=Path) + parser.add_argument("--output-dir", type=Path, required=True) + parser.add_argument("--block-memory", action="append", default=[], + help="明确将指定宏映射到 BRAM，包括 ROB 的浅层宽操作数 RAM") + args = parser.parse_args() + raw = args.emission.read_bytes() + rtl, metadata, config = unpack_emission(raw.decode()) + validate(metadata, config) + requested = set(args.block_memory) + available = {mem["module_name"] for mem in metadata} + if not requested <= available: + raise ValueError("Unknown block memory: " + ", ".join(sorted(requested - available))) + modules, mappings = [], [] + for mem in metadata: + module, style = emit_memory(mem, mem["module_name"] in requested) + modules.append(module) + mappings.append({**mem, "ram_style": style}) + macros = "\n".join(modules) + args.output_dir.mkdir(parents=True, exist_ok=True) + (args.output_dir / "ToyLinuxChip.sv").write_bytes(rtl.encode()) + (args.output_dir / "FpgaMemories.sv").write_bytes(macros.encode()) + (args.output_dir / "memories.conf").write_bytes(config.encode()) + record = { + "emitted_sha256": hashlib.sha256(raw).hexdigest(), + "core_rtl_sha256": hashlib.sha256(rtl.encode()).hexdigest(), + "memory_rtl_sha256": hashlib.sha256(macros.encode()).hexdigest(), + "read_latency": 1, + "write_latency": 1, + "undefined_output_policy": "hold on disabled/write cycle", + "dual_port_collision_policy": "read/write same address is undefined", + "memories": mappings, + } + (args.output_dir / "MEMORY_MANIFEST.json").write_text( + json.dumps(record, indent=2) + "\n" + ) + instances = sum(len(m["hierarchy"]) for m in metadata) + print(f"Bound {len(metadata)} memory types, {instances} instances") + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/prepare_rob_candidate.py b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/prepare_rob_candidate.py new file mode 100644 index 0000000..615b19d --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/prepare_rob_candidate.py @@ -0,0 +1,60 @@ +"""为 ROB 操作数候选显式绑定 BRAM，核对 profile 与已有存储器几何参数。""" + +import argparse +import hashlib +import json +from pathlib import Path +import subprocess +import sys + +from prepare_fpga_memories import unpack_emission, validate + +ROOT = Path(__file__).resolve().parents[1] + + +def digest(path): + return hashlib.sha256(path.read_bytes()).hexdigest() + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--baseline-memory-manifest", type=Path, required=True) + args = parser.parse_args() + raw = ROOT / "build/serial-raw/ToyLinuxChip.sv" + profile = json.loads((ROOT / "build/serial-raw/ToyLinuxChip.profile.json").read_text()) + expected = json.loads((ROOT / "evidence/2026-10-11/ToyLinuxChip.profile.json").read_text()) + if profile != expected: + raise ValueError("Optimization changed the architectural hardware profile") + _, memories, config = unpack_emission(raw.read_text()) + validate(memories, config) + operands = [m for m in memories if any("robOperands" in h for h in m["hierarchy"])] + if len(operands) != 1: + raise ValueError("Expected one ROB operand memory type") + operand = operands[0] + if (operand["depth"], operand["width"], operand["read"], operand["write"], + operand["readwrite"], operand["masked"], len(operand["hierarchy"])) != (16, 128, 1, 1, 0, False, 1): + raise ValueError("Unexpected ROB memory geometry or topology") + baseline = json.loads(args.baseline_memory_manifest.read_text()) + if baseline["core_rtl_sha256"] != "4c6aacf64660bbbf14b1114e8d5e4439d6a4e1427aaf1f681c6a4f618f2d2779": + raise ValueError("Wrong baseline memory manifest") + def signature(memory): + return tuple(memory.get(k) for k in + ("depth", "width", "read", "write", "readwrite", "masked", "mask_granularity")) + before = sorted((signature(m), len(m["hierarchy"])) for m in baseline["memories"]) + after = sorted((signature(m), len(m["hierarchy"])) for m in memories if m != operand) + if before != after: + raise ValueError("An existing memory geometry/topology changed") + subprocess.run([sys.executable, str(ROOT / "scripts/prepare_fpga_memories.py"), str(raw), + "--output-dir", str(ROOT / "build/serial-bound"), + "--block-memory", operand["module_name"]], check=True, timeout=60) + subprocess.run([sys.executable, str(ROOT / "scripts/bind_fpu_rf.py")], check=True, timeout=60) + record = {"result": "PREPARED_NOT_VALIDATED", "architectural_profile_unchanged": True, + "existing_memory_geometry_unchanged": True, "rob_operand_memory": operand, + "rob_operand_ram_style": "block", "core_rtl_sha256": digest(ROOT / "build/serial-bound/ToyLinuxChip.sv"), + "memory_rtl_sha256": digest(ROOT / "build/serial-bound/FpgaMemories.sv")} + (ROOT / "build/ROB_RAM_PREPARED.json").write_text(json.dumps(record, indent=2) + "\n") + print(json.dumps(record, indent=2)) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/prepare_sources.py b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/prepare_sources.py new file mode 100644 index 0000000..127051c --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/prepare_sources.py @@ -0,0 +1,151 @@ +"""Prepare pinned Buckyball sources without changing the FPGA checkout. + +Requires Git and curl. Existing exported files are verified, never overwritten. +Use --repository to reuse a local Git repository containing the baseline commit. +""" + +import argparse +import hashlib +import io +import json +import subprocess +import tarfile +from pathlib import Path, PurePosixPath + +ROOT = Path(__file__).resolve().parents[1] + + +def run(*args): + return subprocess.check_output(args, timeout=600) + + +def save(path, data): + if path.exists(): + if path.read_bytes() != data: + raise RuntimeError(f"Refusing to overwrite changed source: {path}") + return + path.parent.mkdir(parents=True, exist_ok=True) + path.write_bytes(data) + + +def prepare_upstream(repository): + manifest = json.loads((ROOT / "UPSTREAM_MANIFEST.json").read_text()) + commit = manifest["commit"] + if repository is None: + try: + checkout = Path( + run("git", "-C", str(ROOT), "rev-parse", "--show-toplevel") + .decode() + .strip() + ) + except subprocess.CalledProcessError: + checkout = None + candidates = [checkout / "thirdparty/buckyball", checkout] if checkout else [] + for candidate in candidates: + if (candidate / ".git").exists() and subprocess.run( + ["git", "-C", str(candidate), "cat-file", "-e", commit], + capture_output=True, + ).returncode == 0: + repository = candidate + break + if repository is None: + repository = ROOT / "build" / "baseline.git" + if not repository.exists(): + repository.mkdir(parents=True) + run("git", "init", "--bare", str(repository)) + if subprocess.run( + ["git", "-C", str(repository), "cat-file", "-e", commit], capture_output=True + ).returncode: + run( + "git", + "-C", + str(repository), + "fetch", + "--no-tags", + "--depth=1", + manifest["upstream_repository"], + commit, + ) + requests = "".join(f"{commit}:{name}\n" for name in manifest["files"]).encode() + output = subprocess.run( + ["git", "-C", str(repository), "cat-file", "--batch"], + input=requests, + stdout=subprocess.PIPE, + check=True, + ).stdout + stream = io.BytesIO(output) + for name, metadata in manifest["files"].items(): + expected = metadata["sha256"] + header = stream.readline().split() + if len(header) != 3 or header[1] != b"blob": + raise RuntimeError(f"Missing Git blob: {name}") + data = stream.read(int(header[2])) + assert stream.read(1) == b"\n" + if hashlib.sha256(data).hexdigest() != expected: + raise RuntimeError(f"Original source hash mismatch: {name}") + save(ROOT / "upstream" / name, data) + print(f"Verified {len(manifest['files'])} original Buckyball files at {commit}") + + +def prepare_dependencies(): + lock = json.loads((ROOT / "dependencies.json").read_text()) + cache = ROOT / "build" / "downloads" + cache.mkdir(parents=True, exist_ok=True) + for name, spec in lock.items(): + archive = cache / f"{name}-{spec['commit']}.tar.gz" + if not archive.exists(): + temporary = archive.with_suffix(".partial") + url = ( + f"https://codeload.github.com/{spec['repository']}" + f"/tar.gz/{spec['commit']}" + ) + run( + "curl", + "--fail", + "--location", + "--retry", + "2", + "--connect-timeout", + "15", + "--max-time", + "300", + "--output", + str(temporary), + url, + ) + temporary.replace(archive) + destination = ROOT / "thirdparty" / name + count = 0 + with tarfile.open(archive) as source: + for member in source: + if not member.isfile(): + continue + relative = PurePosixPath(*PurePosixPath(member.name).parts[1:]) + if ( + relative.is_absolute() + or ".." in relative.parts + or not relative.parts + ): + raise ValueError(f"Unsafe archive path: {member.name}") + subtree = spec.get("subtree") + if subtree and not ( + str(relative).startswith(subtree + "/") + or relative.name.upper().startswith( + ("LICENSE", "COPYING", "NOTICE") + ) + ): + continue + target = (destination / str(relative)).resolve() + if not target.is_relative_to(destination.resolve()): + raise ValueError(f"Archive path escapes destination: {member.name}") + save(target, source.extractfile(member).read()) + count += 1 + print(f"Verified/exported {name}: {count} files at {spec['commit']}") + + +if __name__ == "__main__": + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--repository", type=Path) + arguments = parser.parse_args() + prepare_upstream(arguments.repository) + prepare_dependencies() diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/remote_linux_gemmini.py b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/remote_linux_gemmini.py new file mode 100644 index 0000000..557d76b --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/remote_linux_gemmini.py @@ -0,0 +1,90 @@ +"""从私有 SSH 配置连接，在新目录构建并下载镜像；不保存或输出凭据。""" + +import argparse +import importlib.util +import json +from pathlib import Path +import shlex +import time +import uuid + +import paramiko + +ROOT = Path(__file__).resolve().parents[1] + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--ssh-helper", type=Path, required=True) + parser.add_argument("--cache-base", default="/home/yys/codex-builds/pebble-linux-20261010") + parser.add_argument("--sdk", default="/nix/store/l4dz443kk1rr8m3z0hby213xc2wqpjyc-riscv64-linux-gnu-toolchain") + args = parser.parse_args() + spec = importlib.util.spec_from_file_location("private_ssh", args.ssh_helper) + private = importlib.util.module_from_spec(spec) + spec.loader.exec_module(private) + client = paramiko.SSHClient() + client.load_system_host_keys() + client.set_missing_host_key_policy(paramiko.AutoAddPolicy()) + if not callable(getattr(private, "connect", None)): + raise ValueError("Private SSH module must provide connect(client)") + private.connect(client) + client.get_transport().set_keepalive(30) + started = time.monotonic() + label = "linux-gemmini-" + time.strftime("%Y%m%d") + "-" + uuid.uuid4().hex[:8] + out = ROOT / "build" / label + out.mkdir(parents=True, exist_ok=False) + try: + sftp = client.open_sftp() + remote = sftp.normalize(".") + "/codex-builds/" + label + sftp.mkdir(remote) + files = [ROOT / "SOFTWARE_BASELINE.json", ROOT / "tests/REFERENCE_MANIFEST.json", + ROOT / "evidence/2026-10-11/ToyLinuxChip.profile.json", + ROOT / "scripts/build_board_firmware.py"] + files += list((ROOT / "software").glob("*.py")) + files += [ROOT / "software/build.sh", ROOT / "software/linux_system_check.c", + ROOT / "software/gemmini_linux_check.c"] + files += [path for path in (ROOT / "tests/reference").rglob("*") if path.is_file()] + directories = set() + for path in files: + relative = path.relative_to(ROOT) + for parent in relative.parents: + if str(parent) != ".": + directories.add(parent.as_posix()) + for directory in sorted(directories, key=lambda item: (item.count("/"), item)): + sftp.mkdir(remote + "/" + directory) + for path in files: + sftp.put(str(path), remote + "/" + path.relative_to(ROOT).as_posix()) + command = "cd " + shlex.quote(remote) + " && timeout --signal=TERM --kill-after=10s 3600s python3 -u software/build_gemmini_image.py --cache-base " + shlex.quote(args.cache_base) + " --sdk " + shlex.quote(args.sdk) + print("REMOTE " + remote, flush=True) + _, stdout, _ = client.exec_command(command, timeout=15) + channel = stdout.channel + channel.set_combine_stderr(True) + with (out / "build.log").open("wb") as log: + while not channel.exit_status_ready() or channel.recv_ready(): + if time.monotonic() - started > 3650: + channel.close() + raise TimeoutError("One-hour software build timeout") + if channel.recv_ready(): + data = channel.recv(65536) + log.write(data) + log.flush() + print(data.decode(errors="replace"), end="", flush=True) + else: + time.sleep(0.1) + code = channel.recv_exit_status() + (out / "SESSION.json").write_text(json.dumps({"remote": remote, "exit_code": code, + "timeout_seconds": 3600, "elapsed_seconds": round(time.monotonic() - started, 3)}, indent=2) + "\n") + if code: + raise RuntimeError(f"Remote build failed with exit {code}; see {out / 'build.log'}") + for filename in ["build/LINUX_GEMMINI_BUILD.json", "build/board-software/fw_payload.bin", + "build/board-software/RESULT.json"]: + destination = out / Path(filename).name + sftp.get(remote + "/" + filename, str(destination)) + sftp.close() + print("DOWNLOADED " + str(out), flush=True) + finally: + client.close() + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/resolve_config.py b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/resolve_config.py new file mode 100644 index 0000000..8ca4ee3 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/resolve_config.py @@ -0,0 +1,106 @@ +"""Read the pinned Toy TOMLs; emit inputs to the upstream parameter readers.""" + +import json +from pathlib import Path + +try: + import tomllib +except ModuleNotFoundError: + import tomli as tomllib + +ROOT = Path(__file__).resolve().parents[1] +UPSTREAM = ROOT / "upstream" + + +def read(path): + return tomllib.loads(path.read_text(encoding="utf-8")) + + +def resolve(): + tile_path = UPSTREAM / "examples/chips/toy/configs/designs/tiles/default.toml" + tile = read(tile_path) + assert len(tile["cores"]) == 1 + assert not tile["privateDCache"]["enable"] + assert not tile["sharedMem"]["enable"] + core_path = (tile_path.parent / tile["cores"][0]["include"]).resolve() + core = read(core_path) + cpu_path = core_path.parent / core["cpu"] + cpu_ref = read(cpu_path) + assert cpu_ref["kind"] == "rocket" + cpu = read(cpu_path.parent / cpu_ref["config"]) + mem = read(core_path.parent / core["memdomain"]) + front = read(core_path.parent / core["frontend"]) + domain_path = core_path.parent / core["balldomain"] + balls = read(domain_path) + for mapping in balls["ballIdMappings"]: + config = (domain_path.parent / mapping["config"]).resolve() + assert config.is_file() and config.is_relative_to(UPSTREAM.resolve()) + mapping["config"] = [config.relative_to(UPSTREAM.resolve()).as_posix()] + shared = tile["sharedMem"] + frontend_keys = { + "robEntries": "rob_entries", + "rsOutOfOrderResponse": "rs_out_of_order_response", + "bankIdLen": "bank_id_len", + "vbankIdUpperBound": "vbank_id_upper_bound", + "sharedBankIdBase": "shared_bank_id_base", + "iterLen": "iter_len", + "subRobEnable": "sub_rob_enable", + "subRobDepth": "sub_rob_depth", + } + result = { + "cpu": cpu, + "accelerator": { + "tile": { + k: tile[k] + for k in ( + "coreDataBytes", + "xLen", + "vaddrBits", + "paddrBits", + "pgIdxBits", + "pgLevels", + "nPMPs", + ) + }, + "frontend": {frontend_keys[k]: v for k, v in front.items()}, + "gpDomain": read(core_path.parent / core["gpdomain"]), + "ballDomain": balls, + "sim": {"diffTest": False}, + "memDomain": { + "bankNum": mem["bank"]["num"], + "bankWidth": mem["bank"]["width"], + "bankEntries": mem["bank"]["entries"], + "bankMaskLen": mem["bank"]["maskLen"], + # bbdev 2_parameter_derivation.py: explicit shared override, + # otherwise the largest private-bank count in this tile. + "virtualBankCount": shared.get("virtualBankCount", mem["bank"]["num"]), + "sharedEnable": shared["enable"], + "sharedEntries": shared["entries"], + "sharedBankNum": 0, + "sharedInputChannels": shared["inputChannels"], + "sharedDefaultGroupCount": shared["defaultGroupCount"], + "nCores": 1, + "tlb_size": mem["tlb"]["size"], + "dma_n_xacts": mem["dma"]["nXacts"], + "dma_burst_maxbytes": mem["dma"]["burstMaxBytes"], + "bankChannel": mem["bank"]["channel"], + "max_in_flight_mem_reqs": mem["dma"]["maxInFlightMemReqs"], + "dma_buswidth": mem["dma"]["busWidth"], + "memAddrLen": mem["mem"]["addrLen"], + "tmaReadChannel": mem["tma"]["readChannel"], + "tmaWriteChannel": mem["tma"]["writeChannel"], + **{"mmio" + k[0].upper() + k[1:]: v for k, v in mem["mmio"].items()}, + }, + }, + } + output = ROOT / "build/original-toy.json" + output.parent.mkdir(parents=True, exist_ok=True) + output.write_text(json.dumps(result, indent=2) + "\n", encoding="utf-8") + print( + f"Original Toy: VM={cpu['useVM']}, FPU={cpu['fpu']}, " + f"Balls={balls['ballNum']}, banks={mem['bank']}" + ) + + +if __name__ == "__main__": + resolve() diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/run_board_regression.py b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/run_board_regression.py new file mode 100644 index 0000000..6d17780 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/run_board_regression.py @@ -0,0 +1,14 @@ +"""Repeat the unchanged CPU/Gemmini/loop/DMA oracles through board RTL.""" +import json +from pathlib import Path +import subprocess +import sys + +ROOT=Path(__file__).resolve().parents[1] +subprocess.run([sys.executable,str(ROOT/"scripts/check_board.py")],check=True,timeout=180) +records={} +for name in ("cpu","gemmini","loop","dma"): + subprocess.run([sys.executable,str(ROOT/"scripts/check_board_cpu.py"),"--test",name],check=True,timeout=1000) + records[name]=json.loads((ROOT/("build/board-"+name)/"RESULT.json").read_text()) +(ROOT/"build/BOARD_REGRESSION.json").write_text(json.dumps(dict(result="PASS",tests=records),indent=2)+"\n") +print("PASS BOARD_REGRESSION CPU/Gemmini/loop/DMA") diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/start_board_build.py b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/start_board_build.py new file mode 100644 index 0000000..a8c7b7a --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/start_board_build.py @@ -0,0 +1,92 @@ +"""Run the complete board flow in isolation with a one-hour hard timeout.""" +from datetime import datetime, timedelta, timezone +import argparse +import hashlib +import json +import os +from pathlib import Path +import subprocess +import sys +import time + +ROOT=Path(__file__).resolve().parents[1] +TZ=timezone(timedelta(hours=8)) +EXPECTED="4c6aacf64660bbbf14b1114e8d5e4439d6a4e1427aaf1f681c6a4f618f2d2779" + + +def sha(path): + return hashlib.sha256(path.read_bytes()).hexdigest() + + +def save(path, record): + temp=path.with_suffix(".tmp") + temp.write_text(json.dumps(record,indent=2)+"\n",encoding="utf-8") + temp.replace(path) + + +def worker(out): + manifest=out/"RUN.json" + record=json.loads(manifest.read_text()) + now=datetime.now(TZ) + script=Path(record.get("execution_script",str(ROOT/"board/build_board.tcl"))) + if "execution_script_sha256" in record: + assert sha(script)==record["execution_script_sha256"] + command=["timeout","--signal=TERM","--kill-after=15s","3600s",os.environ.get("VIVADO", "vivado"), + "-mode","batch","-source",str(script), + "-log",str(out/"vivado.log"),"-journal",str(out/"vivado.jou"),"-tclargs",str(out)] + if record.get("flash_boot"): + command.append("flash") + record.update(status="RUNNING",started_at=now.isoformat(),deadline=(now+timedelta(hours=1)).isoformat(), + command=command,worker_pid=os.getpid()) + started=time.monotonic() + try: + with (out/"console.log").open("w") as log: + p=subprocess.Popen(command,cwd=ROOT,stdin=subprocess.DEVNULL,stdout=log, + stderr=subprocess.STDOUT,start_new_session=True) + record["timeout_process_pid"]=p.pid + save(manifest,record) + code=p.wait() + record.update(exit_code=code,status="TIMED_OUT" if code in (124,137) else "COMPLETED" if code==0 else "FAILED") + except Exception as e: + record.update(status="LAUNCH_FAILED",error=str(e)) + record.update(elapsed_seconds=time.monotonic()-started,finished_at=datetime.now(TZ).isoformat(), + core_unchanged=sha(ROOT/"build/serial-bound/ToyLinuxChip.sv")==EXPECTED, + bitstream_generated=(out/"toy_a7.bit").is_file()) + save(manifest,record) + + +def main(): + p=argparse.ArgumentParser(description=__doc__) + p.add_argument("--worker",type=Path) + p.add_argument("--flash",action="store_true",help="Use the validated Flash boot ROM and SPI port") + args=p.parse_args() + if args.worker: + worker(args.worker.resolve());return + assert sha(ROOT/"build/serial-bound/ToyLinuxChip.sv")==EXPECTED + if args.flash: + flash_manifest=json.loads((ROOT/"build/flash-boot/MANIFEST.json").read_text()) + assert flash_manifest["original_core_sha256"]==EXPECTED + assert sha(ROOT/"build/flash-boot/ToyLinuxChip.sv")==flash_manifest["adapted_core_sha256"] + for path in (ROOT/"build").glob("board-*/RUN.json"): + assert json.loads(path.read_text())["status"] not in ("CREATED","RUNNING"),f"Active build: {path}" + out=ROOT/"build"/("board-"+datetime.now(TZ).strftime("%Y%m%d-%H%M%S")) + out.mkdir() + # Snapshot the exact board sources used by this attempt, including failures. + import shutil + shutil.copytree(ROOT/"board",out/"inputs/board") + files={str(p.relative_to(ROOT)):sha(p) for p in (ROOT/"board").rglob("*") if p.is_file()} + record=dict(status="CREATED",timeout_seconds=3600,termination_grace_seconds=15, + output_directory=str(out),part="xc7a100tcsg324-1",core_sha256=EXPECTED, + board_sources=files,core_clock_hz=25000000,uart_baud=1000000, + vendor_revision="E.0",physical_board_revision="unknown",physical_boot_tested=False, + flash_boot=args.flash) + save(out/"RUN.json",record) + with (out/"launcher.log").open("w") as log: + p=subprocess.Popen([sys.executable,str(Path(__file__).resolve()),"--worker",str(out)], + cwd=ROOT,stdout=log,stderr=subprocess.STDOUT,stdin=subprocess.DEVNULL, + start_new_session=True,close_fds=True) + print(json.dumps({"output_directory":str(out),"worker_pid":p.pid,"timeout_seconds":3600})) + + +if __name__=="__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/start_rob_board_build.py b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/start_rob_board_build.py new file mode 100644 index 0000000..de57b6d --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/start_rob_board_build.py @@ -0,0 +1,63 @@ +"""以独立候选记录执行同一整板流程；不继承旧位流的资格结论。""" + +import argparse +from datetime import datetime +import json +import os +from pathlib import Path +import shutil +import subprocess +import sys + +from start_board_build import ROOT, TZ, save, sha, worker + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--worker", type=Path) + args = parser.parse_args() + if args.worker: + out = args.worker.resolve() + worker(out) + record = json.loads((out / "RUN.json").read_text()) + record["candidate_core_unchanged"] = sha(ROOT / "build/serial-bound/ToyLinuxChip.sv") == record["core_sha256"] + record["candidate_memory_unchanged"] = sha(ROOT / "build/serial-bound/FpgaMemories.sv") == record["memory_sha256"] + if not record["candidate_core_unchanged"] or not record["candidate_memory_unchanged"]: + record["status"] = "INPUT_CHANGED_REJECTED" + save(out / "RUN.json", record) + return + prepared = json.loads((ROOT / "build/ROB_RAM_PREPARED.json").read_text()) + for path in ["build/globalrob-check/RESULT.json", "build/BOARD_REGRESSION.json"]: + if json.loads((ROOT / path).read_text())["result"] != "PASS": + raise ValueError("Candidate regression has not passed: " + path) + core = ROOT / "build/serial-bound/ToyLinuxChip.sv" + memories = ROOT / "build/serial-bound/FpgaMemories.sv" + if sha(core) != prepared["core_rtl_sha256"] or sha(memories) != prepared["memory_rtl_sha256"]: + raise ValueError("Candidate inputs changed after preparation") + for path in (ROOT / "build").glob("board-*/RUN.json"): + if json.loads(path.read_text())["status"] in ("CREATED", "RUNNING"): + raise ValueError("An isolated board build is already active") + out = ROOT / "build" / ("board-rob-ram-" + datetime.now(TZ).strftime("%Y%m%d-%H%M%S")) + out.mkdir() + shutil.copytree(ROOT / "board", out / "inputs/board") + files = {str(p.relative_to(ROOT)): sha(p) for p in (ROOT / "board").rglob("*") if p.is_file()} + script = out / "inputs/board/build_board.tcl" + # Keep the input snapshot for audit, execute the identical script at its + # normal root so relative HDL/IP paths resolve without rewriting Tcl. + record = {"status": "CREATED", "optimization": "ROB_OPERAND_BRAM", "timeout_seconds": 3600, + "termination_grace_seconds": 15, "part": "xc7a100tcsg324-1", + "core_sha256": sha(core), "memory_sha256": sha(memories), "board_sources": files, + "execution_script": str(ROOT / "board/build_board.tcl"), "execution_script_sha256": sha(script), + "core_clock_hz": 25000000, "uart_baud": 1000000, + "architectural_profile_unchanged": True, "flash_boot": False, + "physical_boot_tested": False, "inherits_baseline_hardware_qualification": False} + save(out / "RUN.json", record) + with (out / "launcher.log").open("w") as log: + process = subprocess.Popen([sys.executable, str(Path(__file__).resolve()), "--worker", str(out)], + cwd=ROOT, stdout=log, stderr=subprocess.STDOUT, stdin=subprocess.DEVNULL, + start_new_session=True, close_fds=True) + print(json.dumps({"output_directory": str(out), "worker_pid": process.pid, "timeout_seconds": 3600})) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/verify_flash_evidence.py b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/verify_flash_evidence.py new file mode 100644 index 0000000..6ea4096 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/verify_flash_evidence.py @@ -0,0 +1,126 @@ +"""Check the preserved Flash implementation and physical cold-start evidence.""" + +import hashlib +import json +from pathlib import Path +import re + +ROOT = Path(__file__).resolve().parents[1] +ARCHIVE = ROOT / "evidence/2026-10-12/flash" +CHECKS = { + "VM_COPY_ON_WRITE", + "VM_PAGE_PROTECTION", + "FP64_PROCESS_CONTEXT", + "LINUX_TIMER", + "LINUX_SYSTEM_CHECK", +} + + +def read(path): + return json.loads(path.read_text(encoding="utf-8")) + + +def sha(path): + return hashlib.sha256(path.read_bytes()).hexdigest() + + +def verify(): + manifest = read(ARCHIVE / "MANIFEST.json") + for name, expected in manifest["files"].items(): + assert sha(ARCHIVE / name) == expected, name + record = read(ARCHIVE / "FLASH_RESULT.json") + run = read(ARCHIVE / "implementation/RUN.json") + software = read(ARCHIVE / "software/MANIFEST.json") + packed = read(ARCHIVE / "software/FLASH_IMAGE.json") + assert run["status"] == "COMPLETED" and run["exit_code"] == 0 + assert run["flash_boot"] and run["bitstream_generated"] + assert run["timeout_seconds"] == 3600 and run["elapsed_seconds"] < 3600 + for name, expected in run["board_sources"].items(): + assert sha(ARCHIVE / "sources" / name) == expected, name + assert record["part"] == run["part"] == "xc7a100tcsg324-1" + assert run["core_sha256"] == software["original_core_sha256"] + assert software["only_module_replaced"] == "TLROM" + assert software["dtb_address"] == "0x11000" and software["rom_bytes"] == 8192 + assert record["payload_sha256"] == software["payload_sha256"] + assert record["bitstream_sha256"] == packed["bitstream_sha256"] + previous = read(ROOT / "evidence/2026-10-11/BOARD_RESULT.json") + assert record["payload_sha256"] == previous["linux"]["payload_sha256"] + + labels = { + "Slice LUTs": "LUT", + "Slice Registers": "FF", + "Block RAM Tile": "BRAM_tiles", + "DSPs": "DSP", + "Slice": "Slice", + } + area = {} + for line in ( + (ARCHIVE / "implementation/routed-utilization.rpt").read_text().splitlines() + ): + fields = [field.strip() for field in line.split("|")] + if len(fields) > 3 and fields[1] in labels: + area[labels[fields[1]]] = float(fields[2]) + assert area == record["routed_resources"] + timing = (ARCHIVE / "implementation/routed-timing.rpt").read_text() + match = re.search( + r"WNS\(ns\).*?\n\s*-+[^\n]*\n\s*([\d.-]+)\s+([\d.-]+)\s+(\d+)\s+(\d+)\s+([\d.-]+)\s+([\d.-]+)", + timing, + ) + assert match and float(match[1]) == record["wns_ns"] >= 0 + assert float(match[2]) == float(match[6]) == 0 + assert float(match[5]) == record["whs_ns"] >= 0 + route = (ARCHIVE / "implementation/route-status.rpt").read_text() + assert re.search(r"nets with routing errors\.*\s*:\s+0", route) + assert "checking unconstrained_internal_endpoints (0)" in timing + cdc = (ARCHIVE / "implementation/cdc.rpt").read_text() + assert not re.search(r"^CDC-\d+\s+Critical\s+\d+", cdc, re.MULTILINE) + drc = (ARCHIVE / "implementation/drc.rpt").read_text() + assert not re.search( + r"^\|[^|\n]+\|\s*(?:Error|Critical Warning)\s*\|", drc, re.MULTILINE + ) + + hardware = read(ARCHIVE / "hardware/AUTOMATIC_BOOT_RESULT.json") + assert hardware["result"] == "PASS_FLASH_PROGRAM_AND_AUTOMATIC_LINUX_BOOT" + assert hardware["bitstream_sha256"] == record["bitstream_sha256"] + assert hardware["packed_payload_sha256"] == packed["packed_payload_sha256"] + assert hardware["flash_image_sha256"] == packed["flash_image_sha256"] + assert hardware["backup_bytes"] == 16777216 and not hardware["backup_published"] + for name, expected in hardware["evidence_sha256"].items(): + assert sha(ARCHIVE / "hardware" / name) == expected, name + program = (ARCHIVE / "hardware/program.log").read_bytes() + assert b"Program/Verify Operation successful." in program + assert b"FLASH_BOOT_CONFIG_STATUS 01010000000100000111100111111100" in program + + cold = read(ARCHIVE / "hardware/cold-boot-1.json") + assert cold["result"] == "PASS_FLASH_LINUX" and cold["exit_status"] == 0 + assert cold["disconnect_required"] and cold["usb_disconnections"] >= 1 + assert record["operator_confirmed_all_power_removed"] + assert record["physical_cold_boot_tested"] and not record["board_release_ready"] + assert set(cold["checks"]) == {"PASS " + check for check in CHECKS} + for name in ("linux-console.log", "cold-boot-1.log"): + data = (ARCHIVE / "hardware" / name).read_bytes() + assert b"PASS FLASH_PAYLOAD_CRC" in data and b"OpenSBI v1.9" in data + assert b"Linux version 6.6.0" in data and b"Kernel panic" not in data + assert re.search(rb"(?:^|\n)FLASH_LINUX_RC:0\r*\n", data) + for check in CHECKS: + assert ("PASS " + check).encode() in data + assert ( + b"OBSERVER_USB_DISCONNECTED" + in (ARCHIVE / "hardware/cold-boot-1.log").read_bytes() + ) + assert read(ARCHIVE / "tests/flash-regression/RESULT.json")["result"] == "PASS" + recovery = read(ARCHIVE / "tests/board-uart-flash-recovery/RESULT.json") + assert recovery["result"] == "PASS_UART_LOAD_VERIFY_BOOT" + assert recovery["flash_rom_recovery"] and recovery["bytes_verified"] == 110592 + assert ( + not recovery["preloaded_ddr_image"] + and not recovery["testbench_cpu_release_override"] + ) + assert read(ARCHIVE / "tests/board-unit/RESULT.json")["result"] == "PASS" + print( + "PASS Flash evidence: implementation, program/verify and physical cold-start Linux checks" + ) + + +if __name__ == "__main__": + verify() diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/verify_hardware_evidence.py b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/verify_hardware_evidence.py new file mode 100644 index 0000000..c8900a1 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/verify_hardware_evidence.py @@ -0,0 +1,78 @@ +"""Check the immutable physical bring-up archive without contacting hardware.""" +import hashlib +import json +from pathlib import Path +import re + +ROOT = Path(__file__).resolve().parents[1] +ARCHIVE = ROOT / "evidence/2026-10-12/hardware" + + +def read(path): + return json.loads(path.read_text(encoding="utf-8")) + + +def sha(path): + return hashlib.sha256(path.read_bytes()).hexdigest() + + +def verify(): + manifest = read(ARCHIVE / "MANIFEST.json") + assert manifest["run_date"] == "2026-10-12" + assert manifest["time_zone"] == "Asia/Shanghai" + for name, metadata in manifest["files"].items(): + assert sha(ARCHIVE / name) == metadata["sha256"], name + # Historical programming evidence binds the archived script, not later + # revised entry points. Current sources have their own SOURCE_LOCK/tests. + assert sha(ARCHIVE / "program_arty.tcl") == manifest["files"]["program_arty.tcl"]["sha256"] + assert sha(ROOT / "host/load.py") == manifest["host_loader_sha256"] + hardware = read(ARCHIVE / "HARDWARE_RESULT.json") + implementation = read(ROOT / "evidence/2026-10-11/BOARD_RESULT.json") + assert hardware["result"] == "PASS_HARDWARE_LOAD_AND_LINUX_CHECK" + assert hardware["physical_linux_boot_tested"] + assert hardware["bitstream_sha256"] == implementation["bitstream_sha256"] + assert hardware["payload_sha256"] == implementation["linux"]["payload_sha256"] + for name, expected in hardware["evidence_sha256"].items(): + assert sha(ARCHIVE / name) == expected, name + assert hardware["physical_board_revision"] == "unknown" + assert not hardware["hardware_gemmini_operator_tests_run"] + assert not hardware["hardware_fp16_fp32_exhaustive_tests_run"] + assert hardware["configuration"] == "volatile FPGA SRAM" + assert hardware["verified_ddr_bytes"] == hardware["payload_bytes"] == 17409032 + assert hardware["complete_payload_ddr_readback"] == "PASS" + assert hardware["system_check_process_exit_status"] == 0 + assert hardware["live_shell"] == "PASS" + assert hardware["uart_latency_restored_ms"] == 16 + program = (ARCHIVE / "program.log").read_bytes() + assert b"End of startup status: HIGH" in program + assert b"ARTY_JTAG_PROGRAMMED:" in program + assert b"Device xc7a100t" in program + load = (ARCHIVE / "load-and-linux.log").read_bytes() + progress = [(int(done), int(total)) for done, total in + re.findall(rb"Verified (\d+)/(\d+) bytes", load)] + assert progress[0][0] == 256 + assert all(total == hardware["payload_bytes"] for _, total in progress) + assert all(b[0] - a[0] == 65536 for a, b in zip(progress, progress[1:])) + assert progress[-1][0] >= hardware["payload_bytes"] - 65536 + assert b"Full readback passed; CPU started after 544.1s." in load + console = (ARCHIVE / "linux-console.log").read_bytes() + checks = {"VM_COPY_ON_WRITE", "VM_PAGE_PROTECTION", "FP64_PROCESS_CONTEXT", + "LINUX_TIMER", "LINUX_SYSTEM_CHECK"} + assert set(hardware["linux_checks"]) == checks + for check in checks: + assert hardware["linux_checks"][check] == "PASS" + assert ("PASS " + check).encode() in console, check + assert b"OpenSBI v1.9" in console and b"Linux version 6.6.0" in console + assert b"elapsed_ns=103836000" in console + first = (ARCHIVE / "live-console-first.log").read_bytes() + assert re.search(rb"(?:^|\n)HARDWARE_RC:0\r*\n", first) + live = (ARCHIVE / "live-console.log").read_bytes() + assert b"KERNEL:Linux version 6.6.0" in live + assert b"MEMORY:MemTotal: 245784 kB" in live + assert re.search(rb"(?:^|\n)FPGA_LIVE_DONE\r*\n", live) + print(f"PASS physical hardware archive: {len(manifest['files'])} original artifacts; " + "complete DDR image readback, five Linux checks and live shell") + + +if __name__ == "__main__": + verify() diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/verify_linux_gemmini.py b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/verify_linux_gemmini.py new file mode 100644 index 0000000..27aa87d --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/verify_linux_gemmini.py @@ -0,0 +1,125 @@ +"""离线核验标准镜像与实物日志；仅从实际 PASS 行汇总计算耗时。""" + +import argparse +import hashlib +import json +from pathlib import Path +import re + +ROOT = Path(__file__).resolve().parents[1] +SHAPES = [(8, 8, 8), (16, 16, 16), (13, 11, 17), (8, 24, 8)] +CHECKS = [ + "VM_COPY_ON_WRITE", + "VM_PAGE_PROTECTION", + "FP64_PROCESS_CONTEXT", + "LINUX_TIMER", + "LINUX_SYSTEM_CHECK", +] + + +def read(path): + return json.loads(path.read_text(encoding="utf-8")) + + +def require(condition, message): + if not condition: + raise ValueError(message) + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--build-record", type=Path, required=True) + parser.add_argument("--hardware-result", type=Path, required=True) + parser.add_argument("--output", type=Path) + parser.add_argument("--expected-bit-sha256", + help="核验重建位流的新运行；省略时使用历史实测位流摘要") + args = parser.parse_args() + build = read(args.build_record) + result = read(args.hardware_result) + original = read(ROOT / "evidence/2026-10-11/BOARD_RESULT.json") + require(build["result"] == "PASS_BUILD_NOT_HARDWARE_TESTED", "Build did not pass") + require(result["result"] == "PASS_LINUX_AND_GEMMINI_HARDWARE", "Hardware did not pass") + expected_bit = args.expected_bit_sha256 or original["bitstream_sha256"] + require(re.fullmatch(r"[0-9a-f]{64}", expected_bit), "Invalid expected bitstream digest") + require(result["bitstream_sha256"] == expected_bit, "Wrong bitstream") + require(result["payload_sha256"] == build["payload_sha256"], "Payload mismatch") + require(result["ddr_readback_bytes"] == build["payload_bytes"], "Incomplete DDR readback") + require(not result["flash_written"], "Expected temporary deployment") + require(result["elapsed_seconds"] < result["timeout_seconds"] == 3600, "Invalid timeout") + require(len(result["tests"]) == result["test_count"] == 15, "Expected 15 workloads") + tests = {item["name"]: item for item in result["tests"]} + require(set(tests) == set(build["workloads"]), "Workload set mismatch") + raw = (args.hardware_result.parent / "linux-console.log").read_bytes() + console = raw.replace(b"\r", b"").decode(errors="replace") + boot_file = args.hardware_result.parent / "boot-console.log" + boot = boot_file.read_bytes().decode(errors="replace") if boot_file.is_file() else console + require("OpenSBI v1.9" in boot and "Linux version 6.6.0" in boot, "Wrong boot") + if result.get("configuration_reused"): + load = read(args.hardware_result.parent / "LOAD_RESULT.json") + require(load["payload_sha256"] == build["payload_sha256"] + and load["bitstream_sha256"] == result["bitstream_sha256"] + and load["ddr_readback_bytes"] == build["payload_bytes"], "Wrong prior load") + expected_hashes = {name: item["sha256"] for name, item in build["workloads"].items()} + require(result["workload_hashes"] == expected_hashes, "Live workload hash mismatch") + for name, expected in expected_hashes.items(): + require(re.search(rf"^{expected}\s+/root/{re.escape(name)}$", + console, re.MULTILINE), "Missing raw live hash: " + name) + require("Kernel panic" not in console, "Kernel panic in transcript") + for index, item in enumerate(result["tests"]): + require(item["exit_code"] == 0, "Failed workload: " + item["name"]) + require(item["output"] in console, "Structured output differs from raw transcript") + require(re.search(rf"^WB_TEST_RC_{index}:0$", console, re.MULTILINE), + "Missing raw process return code: " + item["name"]) + for label in CHECKS: + require("PASS " + label in tests["linux_system_check-linux"]["output"], label) + sources = ROOT / "tests/reference/examples/balls/gemmini/workloads/ctests" + for source in sources.glob("*.c"): + output = tests[source.stem + "-linux"]["output"] + markers = re.findall(r'printf\("([^"\n]* PASSED)\\n"\)', + source.read_text(encoding="utf-8")) + require(len(markers) == 1 and markers[0] in output, "Missing oracle: " + source.name) + require(markers[0] in console, "Missing raw oracle: " + source.name) + output = tests["gemmini_linux_check-linux"]["output"] + pattern = (r"^PASS GEMMINI_CASE id=(\d+) mode=(OS|WS) m=(\d+) n=(\d+) k=(\d+) " + r"cpu_ns=(\d+) accelerator_end_to_end_ns=(\d+)$") + rows = re.findall(pattern, output, re.MULTILINE) + require(len(rows) == result["blocked_matmul_cases"] == 16, "Missing matrix cases") + measurements = [] + for index, row in enumerate(rows): + case, mode, m, n, k, cpu, accelerator = row + shape = tuple(map(int, (m, n, k))) + require(int(case) == index + 1 and shape == SHAPES[(index % 8) // 2] + and mode == ("WS" if index % 2 else "OS"), "Wrong case order/shape") + require(int(cpu) > 0 and int(accelerator) > 0, "Unusable timing sample") + require("PASS GEMMINI_CASE " + " ".join([ + f"id={case}", f"mode={mode}", f"m={m}", f"n={n}", f"k={k}", + f"cpu_ns={cpu}", f"accelerator_end_to_end_ns={accelerator}", + ]) in console, "Missing raw matrix result") + measurements.append({ + "case": int(case), "mode": mode, "m": int(m), "n": int(n), "k": int(k), + "cpu_ns": int(cpu), "accelerator_end_to_end_ns": int(accelerator), + "cpu_over_accelerator": round(int(cpu) / int(accelerator), 4), + }) + require("PASS GEMMINI_LINUX_CHECK cases=16" in output, "Missing final oracle") + require("PASS GEMMINI_LINUX_CHECK cases=16" in console, "Missing raw final oracle") + summary = { + "result": "PASS_OFFLINE_VERIFICATION", + "console_sha256": hashlib.sha256(raw).hexdigest(), + "payload_sha256": build["payload_sha256"], + "matrix_measurements": measurements, + "timing_scope": "分块、DMA、配置、同步和 CPU 跨 K 累加；不是纯 MAC 延迟", + "model_end_to_end_tested": False, + } + if args.output: + args.output.write_text(json.dumps(summary, ensure_ascii=False, indent=2) + "\n", + encoding="utf-8") + print("PASS offline verification: 15 workloads, five Linux checks, 16 matrix cases") + for item in measurements: + print(f"CASE {item['case']:2} {item['mode']} {item['m']}x{item['n']}x{item['k']} " + f"CPU={item['cpu_ns'] / 1e6:.3f}ms " + f"accelerator={item['accelerator_end_to_end_ns'] / 1e6:.3f}ms " + f"CPU/accelerator={item['cpu_over_accelerator']:.4f}") + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/verify_linux_gemmini_archive.py b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/verify_linux_gemmini_archive.py new file mode 100644 index 0000000..7dc6b27 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/verify_linux_gemmini_archive.py @@ -0,0 +1,75 @@ +"""离线核验本次实物归档的文件、输入、DDR/启动片段和超时保护证据。""" + +import hashlib +import json +from pathlib import Path +import re + +ROOT = Path(__file__).resolve().parents[1] +ARCHIVE = ROOT / "evidence/2026-10-12/linux-gemmini" + + +def read(path): + return json.loads(path.read_text(encoding="utf-8")) + + +def sha(path): + return hashlib.sha256(path.read_bytes()).hexdigest() + + +def require(condition, message): + if not condition: + raise ValueError(message) + + +def main(): + manifest = read(ARCHIVE / "MANIFEST.json") + for name, metadata in manifest["files"].items(): + path = (ARCHIVE / name).resolve() + require(path.is_relative_to(ARCHIVE.resolve()), "Invalid archive path") + require(sha(path) == metadata["sha256"], "Archive hash mismatch: " + name) + inputs = read(ARCHIVE / "build/INPUT_MANIFEST.json") + for name, metadata in inputs["source_files"].items(): + snapshot = ARCHIVE / "sources" / name + path = snapshot if snapshot.is_file() else ROOT / name + require(sha(path) == metadata["sha256"], "Source binding mismatch: " + name) + for name, metadata in inputs["generated_build_inputs"].items(): + require(sha(ARCHIVE / "generated-inputs" / name) == metadata["sha256"], name) + for original in (ROOT / "tests/reference/examples/balls/gemmini/workloads/ctests").glob("*.c"): + expected = original.read_text(encoding="utf-8").replace("#define DIM 16", "#define DIM 8") + actual = (ARCHIVE / "generated-inputs" / original.name).read_text(encoding="utf-8") + require(actual == expected, "Reference oracle changed: " + original.name) + load = read(ARCHIVE / "load/RESULT.json") + build = read(ARCHIVE / "build/LINUX_GEMMINI_BUILD.json") + require(load["result"] == "PASS_DDR_READBACK_AND_LINUX_BOOT", "Load stage did not pass") + require(load["ddr_readback_bytes"] == build["payload_bytes"], "Incomplete DDR image") + transfer = (ARCHIVE / "load/transfer.log").read_bytes() + marker = f"PASS FULL_DDR_READBACK bytes={build['payload_bytes']} seconds={load['ddr_transfer_seconds']}" + require(marker.encode() in transfer, "Missing full readback proof") + require(b"PASS LINUX_BOOT" in transfer, "Missing boot checkpoint") + boot = (ARCHIVE / "load/linux-boot.log").read_bytes() + require(b"OpenSBI v1.9" in boot and b"Linux version 6.6.0" in boot and b"~ # " in boot, + "Missing physical Linux boot") + for directory in ["hardware", "first-pass"]: + require(read(ARCHIVE / directory / "LOAD_RESULT.json") == load, "Different reused load") + require((ARCHIVE / directory / "boot-console.log").read_bytes() == boot, "Different boot prefix") + watchdog = read(ARCHIVE / "watchdog/RESULT.json") + require(watchdog["result"] == "PASS_WATCHDOG_SUCCESS_FAILURE_TIMEOUT_AND_REAP", "Watchdog failed") + require([row["exit_code"] for row in watchdog["cases"]] == [0, 1, 137], "Wrong exit cases") + console = (ARCHIVE / "watchdog/check.log").read_bytes() + for index, row in enumerate(watchdog["cases"]): + require(row["watcher_alive_rc"] == 1, "Watcher not reaped") + require(re.search(rb"(?:^|\n)WATCH_SELF_" + str(index).encode() + rb":" + + str(row["exit_code"]).encode() + rb"\r*\n", console), "Missing exit proof") + require(re.search(rb"(?:^|\n)WATCH_REAP_" + str(index).encode() + rb":1\r*\n", console), + "Missing reap proof") + post = read(ARCHIVE / "hardware/POST_RESULT.json") + require(post["result"] == "PASS_POST_TEST_LIVE_SHELL" and post["watchdog_alive_rc"] == 1, + "Post-test shell/reap check failed") + require(post["uart_latency_restored_ms"] == 16 and not post["flash_written"], "Wrong cleanup") + require(not manifest["flash_written"] and not manifest["model_end_to_end_tested"], "Wrong scope") + print(f"PASS Linux/Gemmini archive: {len(manifest['files'])} files, pinned inputs, DDR/boot and watchdog") + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/verify_pr10_evidence.py b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/verify_pr10_evidence.py new file mode 100644 index 0000000..c55cb2e --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/verify_pr10_evidence.py @@ -0,0 +1,87 @@ +"""离线核验 PR #10 的不可变测试档案，不继承历史实物资格。""" + +import hashlib +import json +from pathlib import Path + +ARCHIVE = Path(__file__).resolve().parents[1] / "evidence/2026-10-12/pr10-review" + + +def read(name): + return json.loads((ARCHIVE / name).read_text(encoding="utf-8")) + + +def require(condition, message): + if not condition: + raise ValueError(message) + + +def main(): + manifest = read("MANIFEST.json") + for name, item in manifest["files"].items(): + data = (ARCHIVE / name).read_bytes() + require(hashlib.sha256(data).hexdigest() == item["sha256"], name) + require(len(data) == item["bytes"], name) + record = read("RESULT.json") + require(record["result"] == "PASS_PR10_EVALUATION_AND_OFFLINE_REGRESSIONS", "review result") + require(not any(record[key] for key in ["physical_hardware_tested", "new_bitstream_generated", + "cpu_behavior_simulated", "physical_mig_simulated"]), "test scope") + require(record["focused_patch_apply_check_exit_code"] == 0, "patch compatibility") + require(len(record["comparison"]) == 5, "compared files") + require(all(item["byte_identical"] and item["base_sha256"] == item["current_sha256"] + for item in record["comparison"].values()), "old/current comparison") + for name, expected in record["sources"].items(): + require(manifest["files"]["sources/" + name]["sha256"] == expected, name) + require(manifest["files"]["old-platform.sv"]["sha256"] == + record["old_platform_expected_negative"]["source_sha256"], "old platform") + board = read("board-unit/RESULT.json") + require(board["result"] == "PASS" and board["tests"] == 4, "interface groups") + ports = read("sources/tests/PLATFORM_PORTS_MANIFEST.json") + require(not ports["cpu_behavior_included"], "CPU fixture scope") + require(ports["stub_sha256"] == record["sources"]["tests/ToyLinuxChipPorts.sv"], "port fixture bytes") + for directory, count in [("programming-check", 20), ("flash-guard-check", 10)]: + cases = read(directory + "/RESULT.json")["cases"] + require(len(cases) == count and all(case["result"] == "PASS" for case in cases), directory) + negative = (ARCHIVE / "old-platform-negative.log").read_text() + require("addr=60030000 actual=01 expected=10" in negative, "old RTL negative oracle") + for name in ["program_arty.tcl", "backup_flash.tcl", "program_flash.tcl"]: + log = (ARCHIVE / "original-pr" / (name + ".log")).read_text() + require("MOCK_FAILURE expected boolean value" in log, name) + print(f"PASS PR10 archive: {len(manifest['files'])} artifacts; 4/20/10 offline checks and expected negatives") + verify_selfcheck() + + +def verify_selfcheck(): + archive = ARCHIVE.parents[1] / "2026-10-13/pr10-selfcheck" + + def load(name): + return json.loads((archive / name).read_text(encoding="utf-8")) + + manifest = load("MANIFEST.json") + for name, item in manifest["files"].items(): + data = (archive / name).read_bytes() + require(hashlib.sha256(data).hexdigest() == item["sha256"] and len(data) == item["bytes"], name) + record = load("RESULT.json") + require(record["result"] == "PASS_PR10_SELFCHECK", "selfcheck result") + require(not record["physical_hardware_tested"] and not record["new_bitstream_generated"], "selfcheck scope") + for name, expected in record["sources"].items(): + require(manifest["files"]["sources/" + name]["sha256"] == expected, name) + require(load("board-unit/RESULT.json")["tests"] == 4, "selfcheck interface groups") + for directory, count in [("programming-check", 20), ("flash-guard-check", 10), + ("runner-status-check", 3), ("backpressure-mutation", 3)]: + cases = load(directory + "/RESULT.json")["cases"] + require(len(cases) == count and all(case["result"] == "PASS" for case in cases), directory) + current = load("runner-status-check/RESULT.json")["cases"] + require(all(case["exit_code"] != 0 and case["observed_result"] == "FAILED" for case in current), "fresh failures") + old = load("stale-baseline/RESULT.json")["cases"] + require(len(old) == 3 and all(case["exit_code"] != 0 and case["observed_result"].startswith("PASS") + for case in old), "stale baseline counterexamples") + mutations = {case["case"]: case for case in load("backpressure-mutation/RESULT.json")["cases"]} + require({name: case["exit_code"] for name, case in mutations.items()} == + {"old-test": 0, "new-test": 1, "old-response": 1}, "mutation outcomes") + require("valid=0" in (archive / "backpressure-mutation/new-test.log").read_text(), "BVALID oracle") + print(f"PASS PR10 selfcheck archive: {len(manifest['files'])} artifacts; fresh failure status and BVALID oracles") + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/verify_rob_evidence.py b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/verify_rob_evidence.py new file mode 100644 index 0000000..bbd395a --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/verify_rob_evidence.py @@ -0,0 +1,94 @@ +"""核验 ROB RAM 候选档案；实物资格不从旧版本继承。""" + +import argparse +import hashlib +import json +from pathlib import Path +import re + +ROOT = Path(__file__).resolve().parents[1] +ARCHIVE = ROOT / "evidence/2026-10-12/rob-ram" + + +def read(path): + return json.loads(path.read_text(encoding="utf-8")) + + +def sha(path): + return hashlib.sha256(path.read_bytes()).hexdigest() + + +def resources(path): + labels = {"Slice LUTs": "LUT", "Slice Registers": "FF", "Slice": "Slice", + "Block RAM Tile": "BRAM_tiles", "DSPs": "DSP"} + values = {} + for line in path.read_text().splitlines(): + fields = [field.strip() for field in line.split("|")] + if len(fields) > 3 and fields[1] in labels: + values[labels[fields[1]]] = float(fields[2]) + assert set(values) == set(labels.values()) + return values + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--core", action="store_true") + args = parser.parse_args() + manifest = read(ARCHIVE / "MANIFEST.json") + for name, expected in manifest["files"].items(): + assert sha(ARCHIVE / name) == expected, name + record = read(ARCHIVE / "RESULT.json") + assert record["result"] == "PASS_ROB_RAM_RTL_AND_BOARD_IMPLEMENTATION" + assert record["physical_board_tested"] is False + assert record["flash_boot_tested"] is False + run = read(ARCHIVE / "implementation/RUN.json") + assert run["status"] == "COMPLETED" and run["exit_code"] == 0 + assert run["bitstream_generated"] and run["timeout_seconds"] == 3600 + assert run["candidate_core_unchanged"] and run["candidate_memory_unchanged"] + assert resources(ARCHIVE / "implementation/routed-utilization.rpt") == record["routed_resources"] + before = read(ROOT / "evidence/2026-10-11/BOARD_RESULT.json")["routed_resources"] + for name, value in record["routed_resources"].items(): + assert value - before[name] == record["resource_delta"][name], name + assert read(ARCHIVE / "ToyLinuxChip.profile.json") == read( + ROOT / "evidence/2026-10-11/ToyLinuxChip.profile.json") + assert read(ARCHIVE / "tests/globalrob/RESULT.json")["result"] == "PASS" + assert "PASS all memory bindings" in (ARCHIVE / "tests/rob-memory-regression.log").read_text() + regressions = read(ARCHIVE / "tests/BOARD_REGRESSION.json") + baseline = read(ROOT / "evidence/2026-10-11/tests/BOARD_REGRESSION.json") + assert regressions["result"] == "PASS" + for name, case in regressions["tests"].items(): + assert case["result"] == "PASS" + assert case["cycles"] == baseline["tests"][name]["cycles"] + assert case["binary_sha256"] == baseline["tests"][name]["binary_sha256"] + linux = read(ARCHIVE / "tests/linux-final/RESULT.json") + assert linux["result"] == "PASS_RTL_LINUX_USERSPACE" and not linux["physical_board_tested"] + transcript = (ARCHIVE / "tests/linux-final/simulation.log").read_text() + for marker in linux["checks"]: + assert marker in transcript, marker + assert "PASS BOARD_LINUX_USERSPACE cycles=273506752" in transcript + timing = (ARCHIVE / "implementation/routed-timing.rpt").read_text() + assert "All user specified timing constraints are met." in timing + rows = timing.split("WNS(ns)", 1)[1].splitlines() + values = next(line.split() for line in rows if re.match(r"\s+-?\d+\.\d+", line)) + assert float(values[0]) == record["timing"]["wns_ns"] >= 0 + assert float(values[4]) == record["timing"]["whs_ns"] >= 0 + assert all(float(values[n]) == 0 for n in [1, 2, 5, 6, 9, 10]) + route = (ARCHIVE / "implementation/route-status.rpt").read_text() + assert re.search(r"nets with routing errors\.+\s*:\s*0\s*:", route) + for name in ["drc.rpt", "cdc.rpt"]: + assert not re.search(r"\b(?:Critical|Error)\b", (ARCHIVE / "implementation" / name).read_text()) + assert read(ARCHIVE / "OPTIN_RESULT.json")["result"] == "PASS_DEFAULT_AND_CANDIDATE_BYTE_IDENTITY" + memory = read(ARCHIVE / "MEMORY_MANIFEST.json") + assert memory["core_rtl_sha256"] == record["core_rtl_sha256"] == run["core_sha256"] + assert memory["memory_rtl_sha256"] == record["memory_rtl_sha256"] == run["memory_sha256"] + for name, expected in record["integration_sources"].items(): + assert sha(ROOT / name) == expected, name + if args.core: + assert sha(ROOT / "build/serial-bound/ToyLinuxChip.sv") == record["core_rtl_sha256"] + assert sha(ROOT / "build/serial-bound/FpgaMemories.sv") == record["memory_rtl_sha256"] + print(f"PASS ROB RAM archive: {len(manifest['files'])} files; unchanged regression cycles; routed candidate") + print("This initial archive predates physical tests; later hardware evidence is in PR #9") + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/verify_target.py b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/verify_target.py new file mode 100644 index 0000000..8c52af8 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/scripts/verify_target.py @@ -0,0 +1,80 @@ +"""Verify published sources/evidence and, optionally, the regenerated core.""" +import argparse +import hashlib +import json +from pathlib import Path +import re +from verify_hardware_evidence import verify as verify_hardware +from verify_flash_evidence import verify as verify_flash + +ROOT = Path(__file__).resolve().parents[1] +EVIDENCE = ROOT / "evidence/2026-10-11" + + +def read(path): + return json.loads(path.read_text(encoding="utf-8")) + + +def sha(path): + return hashlib.sha256(path.read_bytes()).hexdigest() + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--core", action="store_true") + args = parser.parse_args() + lock = read(ROOT / "SOURCE_LOCK.json") + for name, expected in lock["files"].items(): + assert sha(ROOT / name) == expected, name + reference = read(ROOT / "tests/REFERENCE_MANIFEST.json") + for name, expected in reference["files"].items(): + assert sha(ROOT / "tests/reference" / name) == expected, name + vendor = read(ROOT / "board/vendor/MANIFEST.json") + for name, spec in vendor["files"].items(): + assert sha(ROOT / "board/vendor" / name) == spec["sha256"], name + record = read(EVIDENCE / "BOARD_RESULT.json") + assert record["result"] == "PASS_BOARD_IMPLEMENTATION_AND_RTL_REGRESSIONS" + assert record["part"] == "xc7a100tcsg324-1" + assert record["core_rtl_sha256"] == lock["core_rtl_sha256"] + assert record["gemmini_mesh_dsp"] == 64 + # This immutable October 11 record predates the separate physical archive. + assert not record["physical_linux_boot_tested"] and not record["board_release_ready"] + for name, expected in record["board_sources"].items(): + if not name.endswith(".md"): + # Keep the October 11 proof attached to its original board sources; + # later Flash-boot changes require their own implementation evidence. + assert sha(EVIDENCE / "sources" / name) == expected, name + area = {} + labels = {"Slice LUTs": "LUT", "Slice Registers": "FF", "Block RAM Tile": "BRAM_tiles", + "DSPs": "DSP", "Slice": "Slice"} + for line in (EVIDENCE / "implementation/routed-utilization.rpt").read_text().splitlines(): + fields = [field.strip() for field in line.split("|")] + if len(fields) > 3 and fields[1] in labels: + area[labels[fields[1]]] = float(fields[2]) + for name, value in area.items(): + assert value == record["routed_resources"][name], name + assert set(area) == set(labels.values()) + assert record["timing"]["wns_ns"] >= 0 and record["timing"]["whs_ns"] >= 0 + assert all(row["severity"] != "Critical" for row in record["cdc"]) + assert "nets with routing errors" in record["route_status"] + assert record["route_status"]["nets with routing errors"] == 0 + transcript = (EVIDENCE / "tests/linux-final/simulation.log").read_text() + for marker in record["linux"]["checks"]: + assert marker in transcript, marker + assert re.search(r"PASS BOARD_LINUX_USERSPACE cycles=273506752", transcript) + assert read(EVIDENCE / "tests/uart-boot/RESULT.json")["result"] == "PASS_UART_LOAD_VERIFY_BOOT" + verify_hardware() + verify_flash() + if args.core: + assert sha(ROOT / "build/serial-bound/ToyLinuxChip.sv") == lock["core_rtl_sha256"] + assert sha(ROOT / "build/serial-bound/FpgaMemories.sv") == lock["memory_rtl_sha256"] + upstream = read(ROOT / "UPSTREAM_MANIFEST.json") + for name, metadata in upstream["files"].items(): + assert sha(ROOT / "upstream" / name) == metadata["sha256"], name + print(f"PASS Toy target: {len(lock['files'])} source hashes; published implementation and RTL evidence") + if args.core: + print("PASS regenerated Chisel core and FPGA memory/RF binding match the validated bytes") + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/src/main/scala/EmitFmaChecks.scala b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/src/main/scala/EmitFmaChecks.scala new file mode 100644 index 0000000..5cc26c7 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/src/main/scala/EmitFmaChecks.scala @@ -0,0 +1,74 @@ +package fpga.arty.linux + +import chisel3._ +import chisel3.util._ +import _root_.circt.stage.ChiselStage +import org.chipsalliance.cde.config.Parameters +import freechips.rocketchip.tile._ +import freechips.rocketchip.subsystem.{TilesLocated, InSubsystem} +import framework.system.tile.BBTileAttachParams + +class FmaPrecisionCheck(implicit p: Parameters) extends Module { + val valid = IO(Input(Bool())) + val tag = IO(Input(UInt(2.W))) + val kind = IO(Input(UInt(2.W))) // 0=FMA, 1=add/subtract, 2=multiply + val op = IO(Input(UInt(2.W))) + val rm = IO(Input(UInt(3.W))) + val a = IO(Input(UInt(64.W))) + val b = IO(Input(UInt(64.W))) + val c = IO(Input(UInt(64.W))) + val expected = IO(Output(UInt(64.W))) + val actual = IO(Output(UInt(64.W))) + val expectedFlags = IO(Output(UInt(5.W))) + val actualFlags = IO(Output(UInt(5.W))) + val outValid = IO(Output(Bool())) + val equal = IO(Output(Bool())) + val types = Seq(FType.H, FType.S, FType.D) + val inputs = types.zipWithIndex.map { case (t, index) => + val in = Wire(new FPInput) + in := 0.U.asTypeOf(new FPInput) + in.ren3 := kind === 0.U + in.swap23 := kind === 1.U + in.typeTagIn := index.U + in.typeTagOut := index.U + in.fmaCmd := op + in.rm := rm + in.in1 := t.recode(a(t.ieeeWidth - 1, 0)) + in.in2 := t.recode(b(t.ieeeWidth - 1, 0)) + in.in3 := t.recode(c(t.ieeeWidth - 1, 0)) + in + } + val refs = types.zipWithIndex.map { case (t, index) => + val latency = if (t == FType.D) 6 else 5 + val unit = Module(new FPUFMAPipe(latency, t)) + unit.io.in.valid := valid && tag === index.U + unit.io.in.bits := inputs(index) + Pipe(unit.io.out, 6 - latency) + } + val shared = Module(new FPUSharedFMAPipe(6)) + shared.io.in.valid := valid + shared.io.in.bits := VecInit(inputs)(tag) + val outputTag = Pipe(valid, tag, 6) + val originalData = VecInit(types.zip(refs).map { case (t, r) => t.ieee(r.bits.data(t.recodedWidth - 1, 0)).pad(64) }) + val sharedData = VecInit(types.map(t => t.ieee(shared.io.out.bits.data(t.recodedWidth - 1, 0)).pad(64))) + expected := originalData(outputTag.bits) + actual := sharedData(outputTag.bits) + expectedFlags := VecInit(refs.map(_.bits.exc))(outputTag.bits) + actualFlags := shared.io.out.bits.exc + outValid := shared.io.out.valid + equal := shared.io.out.valid === outputTag.valid && + (!outputTag.valid || (expected === actual && expectedFlags === actualFlags)) +} + +object EmitFmaChecks extends App { + val base: Parameters = new ToyLinux8x8Config().toInstance + val tile = base(TilesLocated(InSubsystem)).collect { + case attachment: BBTileAttachParams => attachment.tileParams + }.head + implicit val p: Parameters = base.alterPartial { + case TileKey => tile.copy(core = tile.rocketCorePerCore.head) + } + ChiselStage.emitSystemVerilogFile(new FmaPrecisionCheck, + Array("--target-dir", "build/fma-check"), + Array("-disable-all-randomization", "-strip-debug-info")) +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/src/main/scala/EmitGlobalRobCheck.scala b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/src/main/scala/EmitGlobalRobCheck.scala new file mode 100644 index 0000000..859e462 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/src/main/scala/EmitGlobalRobCheck.scala @@ -0,0 +1,110 @@ +package fpga.arty.linux + +import chisel3._ +import chisel3.util._ +import _root_.circt.stage.ChiselStage +import framework.frontend.globalrs.GlobalROB +import framework.frontend.decoder.{DomainId, PostGDCmd} +import framework.memdomain.frontend.cmd.decoder.DISA.MSET_BITPAT + +/** Cycle comparison of register and synchronous-RAM operand storage. */ +class GlobalRobCheck extends Module { + val seed = IO(Input(UInt(32.W))) + val passed = IO(Output(Bool())) + private val b = OriginalToy.serial + val dut = Module(new GlobalROB(b, useOperandRam = true)) + val reference = Module(new GlobalROB(b, useOperandRam = false)) + val cycle = RegInit(0.U(16.W)) + val random = RegInit(seed) + cycle := cycle + 1.U + random := Cat(random(30, 0), random(31) ^ random(21) ^ random(1) ^ random(0)) + assert(cycle < 9000.U, "GlobalROB drain timeout") + + val source = Module(new Queue(new PostGDCmd(b), 2)) + val generated = Wire(new PostGDCmd(b)) + generated := 0.U.asTypeOf(generated) + val config = random(5, 2) === 0.U + generated.domain_id := Mux(config || random(2), DomainId.MEM, DomainId.BALL) + generated.ball_bid := 0.U + generated.cmd.funct := Mux(config, MSET_BITPAT.value.U(7.W), Mux(random(3), 53.U, 66.U)) + generated.cmd.raw_inst := random + generated.cmd.pc := Cat(random, ~random) + generated.cmd.rs1Data := Cat(random, random ^ "h597bdf03".U) + generated.cmd.rs2Data := Mux(config, + Cat(random, 0.U(21.W), 1.U(1.W), 0.U(3.W), random(1, 0), 0.U(5.W)), + Cat(~random, random ^ "h26ac048e".U)) + generated.bankAccess.rd_bank_0_valid := !config && random(8) + generated.bankAccess.rd_bank_1_valid := !config && random(9) + generated.bankAccess.wr_bank_valid := config || random(10) + generated.bankAccess.rd_bank_0_id := random(14, 11) + generated.bankAccess.rd_bank_1_id := random(18, 15) + generated.bankAccess.wr_bank_id := random(22, 19) + source.io.enq.valid := cycle < 5000.U && random(0) + source.io.enq.bits := generated + dut.io.alloc <> source.io.deq + reference.io.alloc.valid := dut.io.alloc.valid + reference.io.alloc.bits := dut.io.alloc.bits + + val completions = Module(new Queue(UInt(log2Ceil(b.frontend.rob_entries).W), 16)) + val active = cycle(9, 6) === 13.U + val ready = completions.io.enq.ready && random(7) && cycle(8, 5) =/= 7.U + dut.io.issue.ready := ready + reference.io.issue.ready := ready + completions.io.enq.valid := dut.io.issue.fire + completions.io.enq.bits := dut.io.issue.bits.rob_id + dut.io.complete.valid := completions.io.deq.valid && random(4) + dut.io.complete.bits := completions.io.deq.bits + reference.io.complete.valid := dut.io.complete.valid + reference.io.complete.bits := dut.io.complete.bits + completions.io.deq.ready := dut.io.complete.ready && random(4) + dut.io.hart_id := 0.U + reference.io.hart_id := 0.U + dut.io.subRobActive := active + reference.io.subRobActive := active + + assert(dut.io.alloc.ready === reference.io.alloc.ready, "ROB allocation timing mismatch") + assert(dut.io.complete.ready === reference.io.complete.ready, "ROB completion timing mismatch") + assert(dut.io.issue.valid === reference.io.issue.valid, "ROB issue timing mismatch") + when(dut.io.issue.valid) { + assert(dut.io.issue.bits.asUInt === reference.io.issue.bits.asUInt, "ROB issue payload mismatch") + } + assert(dut.io.empty === reference.io.empty && dut.io.full === reference.io.full) + assert(dut.io.head_ptr === reference.io.head_ptr) + assert(dut.io.issued_count === reference.io.issued_count) + assert(dut.io.entry_valid.asUInt === reference.io.entry_valid.asUInt) + assert(dut.io.entry_complete.asUInt === reference.io.entry_complete.asUInt) + assert(dut.io.inst_ids.asUInt === reference.io.inst_ids.asUInt) + + val allocated = RegInit(0.U(16.W)) + val issued = RegInit(0.U(16.W)) + val completed = RegInit(0.U(16.W)) + val sawFull = RegInit(false.B) + val sawStall = RegInit(false.B) + val expected = Reg(Vec(b.frontend.rob_entries, chiselTypeOf(generated.cmd))) + val allocationSlot = RegInit(0.U(log2Ceil(b.frontend.rob_entries).W)) + when(dut.io.alloc.fire) { + allocated := allocated + 1.U + expected(allocationSlot) := dut.io.alloc.bits.cmd + allocationSlot := Mux(allocationSlot === (b.frontend.rob_entries - 1).U, + 0.U, allocationSlot + 1.U) + } + when(dut.io.issue.fire) { + issued := issued + 1.U + assert(dut.io.issue.bits.cmd.cmd.asUInt === expected(dut.io.issue.bits.rob_id).asUInt, + "ROB changed accepted command operands") + } + when(dut.io.complete.fire) { completed := completed + 1.U } + when(dut.io.full) { sawFull := true.B } + when(dut.io.issue.valid && !ready) { sawStall := true.B } + passed := cycle > 5005.U && !source.io.deq.valid && dut.io.empty && !completions.io.deq.valid + when(passed) { + assert(allocated === issued && issued === completed && allocated > 64.U) + assert(sawFull && sawStall, "Missing ROB full/stall coverage") + } +} + +object EmitGlobalRobCheck extends App { + ChiselStage.emitSystemVerilogFile(new GlobalRobCheck, + Array("--target-dir", args.headOption.getOrElse("build/globalrob-check")), + Array("-disable-all-randomization", "-strip-debug-info")) +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/src/main/scala/EmitGroupQueryCheck.scala b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/src/main/scala/EmitGroupQueryCheck.scala new file mode 100644 index 0000000..f247b74 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/src/main/scala/EmitGroupQueryCheck.scala @@ -0,0 +1,45 @@ +package fpga.arty.linux + +import chisel3._ +import chisel3.util._ +import _root_.circt.stage.ChiselStage +import framework.memdomain.frontend.MemGroupQueryArbiter + +class GroupQueryCheck extends Module { + val passed = IO(Output(Bool())) + val dut = Module(new MemGroupQueryArbiter(4, 4)) + val cycle = RegInit(0.U(16.W)) + cycle := cycle + 1.U + assert(cycle < 10000.U, "Group query arbitration timeout") + def lookup(bank: UInt, shared: Bool): UInt = + ((bank ^ Mux(shared, 4.U, 0.U))(2, 0) +& 1.U) + dut.io.backendCount := RegNext(RegNext(lookup(dut.io.backendBank, dut.io.backendShared), 0.U), 0.U) + val sent = RegInit(VecInit(Seq.fill(2)(0.U(8.W)))) + val received = RegInit(VecInit(Seq.fill(2)(0.U(8.W)))) + for (i <- 0 until 2) { + val expected = Module(new Queue(UInt(4.W), 4)) + dut.io.request(i).valid := sent(i) < 128.U + dut.io.request(i).bits.bank := sent(i)(3, 0) ^ (i * 7).U + dut.io.request(i).bits.shared := sent(i)(4) ^ (i == 1).B + expected.io.enq.valid := dut.io.request(i).fire + expected.io.enq.bits := lookup(dut.io.request(i).bits.bank, dut.io.request(i).bits.shared) + dut.io.response(i).ready := cycle(i + 1) && cycle(0) + expected.io.deq.ready := dut.io.response(i).fire + when(dut.io.request(i).fire) { + assert(expected.io.enq.ready) + sent(i) := sent(i) + 1.U + } + when(dut.io.response(i).valid) { + assert(expected.io.deq.valid, "Query reply without an accepted request") + assert(dut.io.response(i).bits === expected.io.deq.bits, "Reply belongs to another bank/client") + } + when(dut.io.response(i).fire) { received(i) := received(i) + 1.U } + } + passed := received.map(_ === 128.U).reduce(_ && _) +} + +object EmitGroupQueryCheck extends App { + ChiselStage.emitSystemVerilogFile(new GroupQueryCheck, + Array("--target-dir", args.headOption.getOrElse("build/group-query-check")), + Array("-disable-all-randomization", "-strip-debug-info")) +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/src/main/scala/EmitPeChecks.scala b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/src/main/scala/EmitPeChecks.scala new file mode 100644 index 0000000..8ee77d7 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/src/main/scala/EmitPeChecks.scala @@ -0,0 +1,59 @@ +package fpga.arty.linux + +import chisel3._ +import circt.stage.ChiselStage +import gemmini._ + +class QuantizerEquivalence extends RawModule { + val value = IO(Input(SInt(20.W))) + val amount = IO(Input(UInt(5.W))) + val equal = IO(Output(Bool())) + val reference = IO(Output(SInt(20.W))) + val actual = IO(Output(SInt(20.W))) + import Arithmetic.SIntArithmetic._ + reference := cast(value.pad(32)).>>(amount).clippedToWidthOf(0.S(20.W)) + actual := FpgaRoundShift(value, amount) + equal := reference === actual +} + +class PeCycleEquivalence extends Module { + val original = Module(new ReferencePE(SInt(8.W), SInt(8.W), SInt(20.W), SInt(32.W), + Dataflow.BOTH, 4)) + val logic = Module(new PE(SInt(8.W), SInt(8.W), SInt(20.W), SInt(32.W), + Dataflow.BOTH, 4, fpgaDsp = false)) + val dsp = Module(new PE(SInt(8.W), SInt(8.W), SInt(20.W), SInt(32.W), + Dataflow.BOTH, 4, fpgaDsp = true)) + val in_a = IO(Input(SInt(8.W))) + val in_b = IO(Input(SInt(20.W))) + val in_d = IO(Input(SInt(20.W))) + val control = IO(Input(new PEControl(SInt(32.W)))) + val id = IO(Input(UInt(2.W))) + val last = IO(Input(Bool())) + val valid = IO(Input(Bool())) + // Explicit wiring keeps all three independently emitted implementations. + original.io.in_a := in_a; logic.io.in_a := in_a; dsp.io.in_a := in_a + original.io.in_b := in_b; logic.io.in_b := in_b; dsp.io.in_b := in_b + original.io.in_d := in_d; logic.io.in_d := in_d; dsp.io.in_d := in_d + original.io.in_control := control; logic.io.in_control := control; dsp.io.in_control := control + original.io.in_id := id; logic.io.in_id := id; dsp.io.in_id := id + original.io.in_last := last; logic.io.in_last := last; dsp.io.in_last := last + original.io.in_valid := valid; logic.io.in_valid := valid; dsp.io.in_valid := valid + val equal = IO(Output(Bool())) + equal := (original.io.out_b === logic.io.out_b && original.io.out_c === logic.io.out_c && + original.io.out_b === dsp.io.out_b && original.io.out_c === dsp.io.out_c && + original.io.out_a === logic.io.out_a && original.io.out_a === dsp.io.out_a && + original.io.out_control.asUInt === logic.io.out_control.asUInt && + original.io.out_control.asUInt === dsp.io.out_control.asUInt && + original.io.out_id === logic.io.out_id && original.io.out_id === dsp.io.out_id && + original.io.out_last === logic.io.out_last && original.io.out_last === dsp.io.out_last && + original.io.out_valid === logic.io.out_valid && original.io.out_valid === dsp.io.out_valid && + original.io.bad_dataflow === logic.io.bad_dataflow && original.io.bad_dataflow === dsp.io.bad_dataflow) +} + +object EmitPeChecks extends App { + val opts = Array("-disable-all-randomization", "-strip-debug-info") + ChiselStage.emitSystemVerilogFile(new QuantizerEquivalence, + Array("--target-dir", "build/pe-checks/quantizer"), opts) + ChiselStage.emitSystemVerilogFile(new PeCycleEquivalence, + Array("--target-dir", "build/pe-checks/cycles"), opts) +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/src/main/scala/EmitRoundShiftChecks.scala b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/src/main/scala/EmitRoundShiftChecks.scala new file mode 100644 index 0000000..27e1a2f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/src/main/scala/EmitRoundShiftChecks.scala @@ -0,0 +1,27 @@ +package fpga.arty.linux + +import chisel3._ +import circt.stage.ChiselStage +import gemmini._ + +/** Check both the existing PE width and the final WS accumulator width. */ +class RoundShiftChecks extends RawModule { + val value20 = IO(Input(SInt(20.W))) + val value32 = IO(Input(SInt(32.W))) + val amount = IO(Input(UInt(5.W))) + val actual20 = IO(Output(SInt(20.W))) + val actual32 = IO(Output(SInt(32.W))) + val original20 = IO(Output(SInt(20.W))) + val original32 = IO(Output(SInt(32.W))) + import Arithmetic.SIntArithmetic._ + actual20 := FpgaRoundShift(value20, amount) + actual32 := FpgaRoundShift(value32, amount) + original20 := cast(value20.pad(32)).>>(amount).clippedToWidthOf(0.S(20.W)) + original32 := cast(value32).>>(amount).clippedToWidthOf(0.S(32.W)) +} + +object EmitRoundShiftChecks extends App { + ChiselStage.emitSystemVerilogFile(new RoundShiftChecks, + Array("--target-dir", "build/round-check"), + Array("-disable-all-randomization", "-strip-debug-info")) +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/src/main/scala/EmitRoutingCheck.scala b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/src/main/scala/EmitRoutingCheck.scala new file mode 100644 index 0000000..d843105 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/src/main/scala/EmitRoutingCheck.scala @@ -0,0 +1,122 @@ +package fpga.arty.linux + +import chisel3._ +import chisel3.util._ +import _root_.circt.stage.ChiselStage +import framework.memdomain.midend.MemMidend +import framework.memdomain.backend.accpipe.AccPipe + +// Real routing and AccPipe modules, with independently checked SRAM endpoints. +// Stalls cover request acceptance, SRAM response, and final response consumption. +class RoutingCheck extends Module { + val passed = IO(Output(Bool())) + val b = OriginalToy.serial + val midend = Module(new MemMidend(b)) + val cycle = RegInit(0.U(16.W)) + cycle := cycle + 1.U + assert(cycle < 20000.U, "Routing regression timeout") + midend.io.hartid := 0.U + midend.io.inst_ids.zipWithIndex.foreach { case (id, index) => id := (100 + index).U } + val readSent = RegInit(VecInit(Seq.fill(3)(0.U(7.W)))) + val readSeen = RegInit(VecInit(Seq.fill(3)(0.U(7.W)))) + val writeSent = RegInit(VecInit(Seq.fill(5)(0.U(7.W)))) + val writeSeen = RegInit(VecInit(Seq.fill(5)(0.U(7.W)))) + val ballAccepted = readSent.take(2).map(_ === 64.U).reduce(_ && _) && + writeSent.take(4).map(_ === 64.U).reduce(_ && _) + // Release the Ball as soon as its final requests are accepted, while responses + // can still be in flight. Fixed routes must keep delivering these responses. + midend.io.ballChannelActive(0) := !ballAccepted + for (port <- 0 until 3) { + val source = midend.io.bankRead(port) + val bank = if (port < 2) port else 6 + source.is_shared := false.B + source.bankRead.bank_id := bank.U + source.bankRead.group_id := 0.U + source.bankRead.ball_id := 0.U + source.bankRead.rob_id := (port % 4).U + source.bankRead.io.req.valid := readSent(port) < 64.U + source.bankRead.io.req.bits.addr := readSent(port) + source.bankRead.io.resp.ready := cycle((port + 1) % 5) + when(source.bankRead.io.req.fire) { readSent(port) := readSent(port) + 1.U } + when(source.bankRead.io.resp.fire) { + assert(source.bankRead.io.resp.bits.data === + (readSeen(port) + (bank << 16).U), "Read response lost or misrouted") + readSeen(port) := readSeen(port) + 1.U + } + } + for (port <- 0 until 5) { + val source = midend.io.bankWrite(port) + val bank = if (port < 4) port + 2 else 7 + source.is_shared := false.B + source.bankWrite.bank_id := bank.U + source.bankWrite.group_id := (port % 4).U + source.bankWrite.ball_id := 0.U + source.bankWrite.rob_id := (port % 4).U + source.bankWrite.io.req.valid := writeSent(port) < 64.U && + (if (port == 4) cycle >= 1.U else true.B) + source.bankWrite.io.req.bits.addr := writeSent(port) + source.bankWrite.io.req.bits.data := writeSent(port) + (bank << 16).U + source.bankWrite.io.req.bits.mask := VecInit(Seq.fill(b.memDomain.bankMaskLen)(true.B)) + source.bankWrite.io.resp.ready := cycle((port + 2) % 5) + when(source.bankWrite.io.req.fire) { writeSent(port) := writeSent(port) + 1.U } + when(source.bankWrite.io.resp.fire) { + assert(source.bankWrite.io.resp.bits.ok, "Write response lost or misrouted") + writeSeen(port) := writeSeen(port) + 1.U + } + } + for (channel <- 0 until 7) { + val request = midend.io.mem_req(channel) + val pipe = Module(new AccPipe(b)) + pipe.io.mem_req <> request + pipe.io.is_multi := false.B + val readPending = RegInit(false.B) + val writePending = RegInit(false.B) + val readData = Reg(UInt(b.memDomain.bankWidth.W)) + val routePending = RegInit(false.B) + val routeBank = Reg(UInt(b.memDomain.vbankIdWidth.W)) + when(!routePending && !pipe.io.busy && + (request.read.req.valid || request.write.req.valid)) { + routePending := true.B + routeBank := request.bank_id + } + when(request.read.req.fire || request.write.req.fire) { routePending := false.B } + pipe.io.sramRead.req.ready := routePending && !readPending && !writePending && cycle(channel % 5) + pipe.io.sramWrite.req.ready := routePending && !readPending && !writePending && cycle((channel + 1) % 5) + pipe.io.sramRead.resp.valid := readPending && cycle((channel + 3) % 5) + pipe.io.sramRead.resp.bits.data := readData + pipe.io.sramWrite.resp.valid := writePending && cycle((channel + 4) % 5) + pipe.io.sramWrite.resp.bits.ok := true.B + when(pipe.io.sramRead.req.fire) { + readPending := true.B + readData := pipe.io.sramRead.req.bits.addr + (routeBank << 16) + assert(request.bank_id === routeBank, "Route metadata changed before SRAM acceptance") + assert(request.bank_id === (if (channel < 2) channel else 6).U) + assert(request.group_id === 0.U) + assert(request.rob_id === (if (channel < 2) channel else 2).U) + assert(request.inst_id === (if (channel < 2) 100 + channel else 102).U) + } + when(pipe.io.sramWrite.req.fire) { + writePending := true.B + assert(request.bank_id === routeBank, "Write replaced a pending read route") + val bank = if (channel < 6) channel else 7 + assert(request.bank_id === bank.U, "Wrong write bank metadata") + assert(pipe.io.sramWrite.req.bits.data === + (pipe.io.sramWrite.req.bits.addr + (bank << 16).U)) + assert(pipe.io.sramWrite.req.bits.mask.asUInt.andR) + val port = if (channel < 6) math.max(0, channel - 2) else 4 + assert(request.group_id === (port % 4).U) + assert(request.rob_id === (port % 4).U) + assert(request.inst_id === (100 + port % 4).U) + } + when(pipe.io.sramRead.resp.fire) { readPending := false.B } + when(pipe.io.sramWrite.resp.fire) { writePending := false.B } + assert(!(pipe.io.sramRead.req.fire && pipe.io.sramWrite.req.fire)) + } + passed := (readSeen ++ writeSeen).map(_ === 64.U).reduce(_ && _) +} + +object EmitRoutingCheck extends App { + ChiselStage.emitSystemVerilogFile(new RoutingCheck, + args = Array("--target-dir", args.head), + firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info")) +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/src/main/scala/EmitSubRobCheck.scala b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/src/main/scala/EmitSubRobCheck.scala new file mode 100644 index 0000000..7d0b2e0 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/src/main/scala/EmitSubRobCheck.scala @@ -0,0 +1,59 @@ +package fpga.arty.linux + +import chisel3._ +import chisel3.util._ +import _root_.circt.stage.ChiselStage +import framework.frontend.globalrs.SubROB + +/** Stream more than the FIFO depth, including empty rows and stalled completion. */ +class SubRobCheck extends Module { + val passed = IO(Output(Bool())) + val sub = Module(new SubROB(OriginalToy.serial)) + val cycle = RegInit(0.U(16.W)) + cycle := cycle + 1.U + assert(cycle < 10000.U, "SubROB streaming timeout") + val sent = RegInit(0.U(6.W)) + val issued = RegInit(0.U(6.W)) + val completed = RegInit(0.U(6.W)) + val masters = RegInit(0.U(2.W)) + val expected = (0 until 40).flatMap { row => + if (row % 3 == 0) Seq.empty else if (row % 3 == 1) Seq(row * 4) else Seq(row * 4, row * 4 + 1) + } + val commands = VecInit(expected.map(_.U(32.W))) + sub.io.write.valid := sent < 40.U + sub.io.write.bits := 0.U.asTypeOf(sub.io.write.bits) + sub.io.write.bits.master_rob_id := 3.U + sub.io.write.bits.ball_id := 0.U + for (slot <- 0 until 4) { + sub.io.write.bits.slots(slot).valid := + (if (slot == 0) sent % 3.U =/= 0.U else if (slot == 1) sent % 3.U === 2.U else false.B) + sub.io.write.bits.slots(slot).cmd.cmd.raw_inst := sent * 4.U + slot.U + } + when(sub.io.write.fire) { sent := sent + 1.U } + val pending = Module(new Queue(UInt(5.W), 8)) + sub.io.issue.ready := pending.io.enq.ready && cycle(0) + pending.io.enq.valid := sub.io.issue.fire + pending.io.enq.bits := sub.io.issueSubId + sub.io.subComplete.valid := pending.io.deq.valid && cycle(1) + sub.io.subComplete.bits := pending.io.deq.bits + pending.io.deq.ready := sub.io.subComplete.ready && cycle(1) + when(sub.io.issue.fire) { + assert(issued < expected.size.U) + assert(sub.io.issue.bits.cmd.raw_inst === commands(issued), "SubROB dropped/reordered a row") + issued := issued + 1.U + } + when(sub.io.subComplete.fire) { completed := completed + 1.U } + sub.io.masterComplete.ready := cycle(2) + when(sub.io.masterComplete.fire) { + assert(sent === 40.U && issued === expected.size.U && completed === expected.size.U, + "SubROB completed master before all accepted rows were executed") + masters := masters + 1.U + } + passed := masters === 1.U +} + +object EmitSubRobCheck extends App { + ChiselStage.emitSystemVerilogFile(new SubRobCheck, + Array("--target-dir", args.headOption.getOrElse("build/subrob-check")), + Array("-disable-all-randomization", "-strip-debug-info")) +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/src/main/scala/ReferencePE.scala b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/src/main/scala/ReferencePE.scala new file mode 100644 index 0000000..463bdda --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/src/main/scala/ReferencePE.scala @@ -0,0 +1,137 @@ +package gemmini +import chisel3._ +import chisel3.util._ +class ReferenceMacUnit[T <: Data](inputType: T, weightType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { + import ev._ + val io = IO(new Bundle { + val in_a = Input(inputType) + val in_b = Input(weightType) + val in_c = Input(cType) + val out_d = Output(dType) + }) + + io.out_d := io.in_c.mac(io.in_a, io.in_b) +} + +// TODO update documentation +/** + * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. + * @param width Data width of operands + */ +class ReferencePE[T <: Data](inputType: T, weightType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) + (implicit ev: Arithmetic[T]) extends Module { // Debugging variables + import ev._ + + val io = IO(new Bundle { + val in_a = Input(inputType) + val in_b = Input(outputType) + val in_d = Input(outputType) + val out_a = Output(inputType) + val out_b = Output(outputType) + val out_c = Output(outputType) + + val in_control = Input(new PEControl(accType)) + val out_control = Output(new PEControl(accType)) + + val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) + val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) + + val in_last = Input(Bool()) + val out_last = Output(Bool()) + + val in_valid = Input(Bool()) + val out_valid = Output(Bool()) + + val bad_dataflow = Output(Bool()) + }) + + val cType = if (df == Dataflow.WS) inputType else accType + + // When creating PEs that support multiple dataflows, the + // elaboration/synthesis tools often fail to consolidate and de-duplicate + // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" + // module here which just performs a single MAC operation + val mac_unit = Module(new ReferenceMacUnit(inputType, weightType, + if (df == Dataflow.WS) outputType else accType, outputType)) + + val a = io.in_a + val b = io.in_b + val d = io.in_d + val c1 = Reg(cType) + val c2 = Reg(cType) + val dataflow = io.in_control.dataflow + val prop = io.in_control.propagate + val shift = io.in_control.shift + val id = io.in_id + val last = io.in_last + val valid = io.in_valid + + io.out_a := a + io.out_control.dataflow := dataflow + io.out_control.propagate := prop + io.out_control.shift := shift + io.out_id := id + io.out_last := last + io.out_valid := valid + + mac_unit.io.in_a := a + + val last_s = RegEnable(prop, valid) + val flip = last_s =/= prop + val shift_offset = Mux(flip, shift, 0.U) + + // Which dataflow are we using? + val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) + val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) + + // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? + val COMPUTE = 0.U(1.W) + val PROPAGATE = 1.U(1.W) + + io.bad_dataflow := false.B + when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { + when(prop === PROPAGATE) { + io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) + io.out_b := b + mac_unit.io.in_b := b.asTypeOf(weightType) + mac_unit.io.in_c := c2 + c2 := mac_unit.io.out_d + c1 := d.withWidthOf(cType) + }.otherwise { + io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) + io.out_b := b + mac_unit.io.in_b := b.asTypeOf(weightType) + mac_unit.io.in_c := c1 + c1 := mac_unit.io.out_d + c2 := d.withWidthOf(cType) + } + }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { + when(prop === PROPAGATE) { + io.out_c := c1 + mac_unit.io.in_b := c2.asTypeOf(weightType) + mac_unit.io.in_c := b + io.out_b := mac_unit.io.out_d + c1 := d + }.otherwise { + io.out_c := c2 + mac_unit.io.in_b := c1.asTypeOf(weightType) + mac_unit.io.in_c := b + io.out_b := mac_unit.io.out_d + c2 := d + } + }.otherwise { + io.bad_dataflow := true.B + //assert(false.B, "unknown dataflow") + io.out_c := DontCare + io.out_b := DontCare + mac_unit.io.in_b := b.asTypeOf(weightType) + mac_unit.io.in_c := c2 + } + + when (!valid) { + c1 := c1 + c2 := c2 + mac_unit.io.in_b := DontCare + mac_unit.io.in_c := DontCare + } +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/src/main/scala/ToyLinuxChip.scala b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/src/main/scala/ToyLinuxChip.scala new file mode 100644 index 0000000..5c9dbb5 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/src/main/scala/ToyLinuxChip.scala @@ -0,0 +1,134 @@ +package fpga.arty.linux + +import java.nio.file.{Files, Paths} +import chisel3._ +import circt.stage.ChiselStage +import org.chipsalliance.cde.config.Parameters +import org.chipsalliance.diplomacy.lazymodule.LazyModule +import freechips.rocketchip.diplomacy.{AddressSet, BufferParams} +import freechips.rocketchip.system.ExampleRocketSystem +import freechips.rocketchip.subsystem.{InSubsystem, InclusiveCacheKey, MBUS, TilesLocated} +import framework.system.tile.BBTileAttachParams +import freechips.rocketchip.tilelink.{TLBuffer, TLFragmenter, TLRAM} +import freechips.rocketchip.resources.{Description, MemoryDevice, ResourceBindings, ResourceString} +import freechips.rocketchip.util.ElaborationArtefacts + +class ToyLinuxSystem(implicit p: Parameters) extends ExampleRocketSystem { + // Optional auxiliary RAM. The Linux boot ROM jumps to DDR at 0x80000000; + // it never uses this separate 0x08000000 region. + if (!p(TrimOptionalPeripherals)) { + val bus = locateTLBusWrapper(MBUS) + val scratchDevice = new MemoryDevice { + override def describe(resources: ResourceBindings): Description = { + val original = super.describe(resources) + original.copy(mapping = original.mapping + ("status" -> Seq(ResourceString("disabled")))) + } + } + val scratchpad = bus { + LazyModule(new TLRAM(AddressSet(BigInt("08000000", 16), 65535), + beatBytes = bus.beatBytes, devOverride = Some(scratchDevice))) + } + bus.coupleTo("toy-scratchpad") { + scratchpad.node := TLFragmenter(bus.beatBytes, bus.blockBytes) := + TLBuffer(BufferParams.default) := TLBuffer(BufferParams.default) := _ + } + } +} + +// Complete CPU/cache/accelerator resource boundary. External AXI ports must +// terminate in real DDR and peripherals before this becomes a board design. +class ToyLinuxChip(implicit p: Parameters) extends Module { + val system = LazyModule(new ToyLinuxSystem) + val core = Module(system.module) + system.io_clocks.get.elements.values.foreach { domain => + domain.clock := clock + domain.reset := reset.asBool + } + val interrupt = IO(Input(Bool())) + core.interrupts := interrupt.asUInt + require(system.mem_axi4.size == 1 && system.mmio_axi4.size == 1) + val memory = IO(chiselTypeOf(system.mem_axi4.head)) + val peripherals = IO(chiselTypeOf(system.mmio_axi4.head)) + memory <> system.mem_axi4.head + peripherals <> system.mmio_axi4.head +} + +object EmitToyLinux extends App { + val serial = args.drop(1).contains("--serial-fpga") + val gemminiOnly = args.drop(1).contains("--gemmini-only") + val compact = gemminiOnly || args.drop(1).contains("--compact-caches") + val trimmed = compact || args.drop(1).contains("--trim-peripherals") + implicit val parameters: Parameters = + (if (serial) new ToyLinux8x8Config + else if (gemminiOnly) new ToyLinuxGemminiOnlyConfig + else if (compact) new ToyLinuxCompactConfig + else if (trimmed) new ToyLinuxTrimmedConfig + else new ToyLinuxConfig).toInstance + val directory = args.headOption.getOrElse("generated") + // Use CIRCT's memory-macro boundary for a board-specific SRAM implementation. + // Original upstream sources stay intact; Gemmini arithmetic uses explicit overlays. + val memoryOptions = if (args.drop(1).contains("--fpga-memories")) { + Array("--repl-seq-mem", s"--repl-seq-mem-file=$directory/memories.conf") + } else Array.empty[String] + ChiselStage.emitSystemVerilogFile( + new ToyLinuxChip, + args = Array("--target-dir", directory), + firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info") ++ memoryOptions + ) + ElaborationArtefacts.files.foreach { case (name, content) => + Files.writeString(Paths.get(directory, s"ToyLinuxChip.$name"), content()) + } + val tiles = parameters(TilesLocated(InSubsystem)).collect { + case attachment: BBTileAttachParams => attachment.tileParams + } + require(tiles.size == 1) + val tile = tiles.head + val core = tile.rocketCorePerCore.headOption.getOrElse(tile.core) + val accelerator = tile.resolvedBuckyballPerCore.flatten.head + val profile = ujson.Obj( + "serial_fpga" -> parameters(SerialFpga), + "gemmini_only_balls" -> parameters(GemminiOnlyBalls), + "ball_count" -> accelerator.ballDomain.ballNum, + "ball_names" -> ujson.Arr.from(accelerator.ballDomain.ballIdMappings.map(_.ballName)), + "ball_ids" -> ujson.Arr.from(accelerator.ballDomain.ballIdMappings.map(_.ballId)), + "ball_funct7" -> ujson.Arr.from(accelerator.ballDomain.ballISA.map(_.funct7)), + "ball_read_ports" -> accelerator.ballDomain.ballIdMappings.map(_.inBW).sum, + "ball_write_ports" -> accelerator.ballDomain.ballIdMappings.map(_.outBW).sum, + "accelerator_mmio_scale_pool" -> accelerator.memDomain.mmioEnable, + "compact_caches" -> parameters(CompactCaches), + "btb_enabled" -> tile.btb.nonEmpty, + "icache_bytes" -> (tile.icache.get.nSets * tile.icache.get.nWays * tile.icache.get.blockBytes), + "icache_ways" -> tile.icache.get.nWays, + "dcache_bytes" -> (tile.dcache.get.nSets * tile.dcache.get.nWays * tile.dcache.get.blockBytes), + "dcache_mshrs" -> tile.dcache.get.nMSHRs, + "l2_ways" -> (if (serial) 0 else parameters(InclusiveCacheKey).ways), + "coherence_manager" -> (if (serial) "broadcast" else "inclusive"), + "rob_entries" -> accelerator.frontend.rob_entries, + "sub_rob_depth" -> accelerator.frontend.sub_rob_depth, + "dma_n_xacts" -> accelerator.memDomain.dma_n_xacts, + "dma_max_in_flight" -> accelerator.memDomain.max_in_flight_mem_reqs, + "tma_read_channels" -> accelerator.memDomain.tmaReadChannel, + "tma_write_channels" -> accelerator.memDomain.tmaWriteChannel, + "cpu_mul_unroll" -> core.mulDiv.get.mulUnroll, + "gemmini_rows" -> examples.balls.gemmini.configs.GemminiBallParam(accelerator).totalRows, + "gemmini_columns" -> examples.balls.gemmini.configs.GemminiBallParam(accelerator).totalColumns, + "virtual_bank_count" -> accelerator.memDomain.virtualBankCount, + "trimmed_optional_peripherals" -> parameters(TrimOptionalPeripherals), + "scratchpad_bytes" -> (if (parameters(TrimOptionalPeripherals)) 0 else 65536), + "cpu_use_debug" -> core.useDebug, + "cpu_breakpoints" -> core.nBreakpoints, + "extra_hpm_counters" -> core.nPerfCounters, + "basic_counters" -> core.haveBasicCounters, + "use_vm" -> core.useVM, + "fpu_shared_fma" -> parameters(freechips.rocketchip.tile.FpgaSharedFma), + "fpu_sfma_latency" -> core.fpu.get.sfmaLatency, + "fpu_dfma_latency" -> core.fpu.get.dfmaLatency, + "fpu_min_flen" -> core.fpu.get.minFLen, + "fpu_flen" -> core.fpu.get.fLen, + "bank_count" -> accelerator.memDomain.bankNum, + "bank_rows" -> accelerator.memDomain.bankEntries, + "bank_width" -> accelerator.memDomain.bankWidth, + "bank_channels" -> accelerator.memDomain.bankChannel + ) + Files.writeString(Paths.get(directory, "ToyLinuxChip.profile.json"), ujson.write(profile, indent = 2)) +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/src/main/scala/ToyLinuxConfig.scala b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/src/main/scala/ToyLinuxConfig.scala new file mode 100644 index 0000000..98a89fd --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/src/main/scala/ToyLinuxConfig.scala @@ -0,0 +1,186 @@ +package fpga.arty.linux + +import java.nio.file.{Files, Paths} +import org.chipsalliance.cde.config.{Config, Field} +import freechips.rocketchip.rocket.RocketCoreParams +import freechips.rocketchip.tile.FpgaSharedFma +import freechips.rocketchip.devices.debug.DebugModuleKey +import freechips.rocketchip.devices.tilelink.{BootROMLocated, BootROMParams} +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.util.SystemFileName +import framework.system.core.rocket.configs.RocketCpuParam +import framework.system.tile.{BBTileAttachParams, WithBBTile} +import framework.top.GlobalConfig + +case object TrimOptionalPeripherals extends Field[Boolean](false) +case object CompactCaches extends Field[Boolean](false) +case object SerialFpga extends Field[Boolean](false) +case object GemminiOnlyBalls extends Field[Boolean](false) + +object OriginalToy { + private val json = ujson.read(Files.readString(Paths.get("build/original-toy.json"))) + val cpu = upickle.default.read[RocketCpuParam](json("cpu")) + private val original = upickle.default.read[GlobalConfig](json("accelerator")) + val accelerator = original.copy(ballDomain = original.ballDomain.copy( + ballIdMappings = original.ballDomain.ballIdMappings.map { mapping => + mapping.copy(config = mapping.config.map(path => Paths.get("upstream", path).toAbsolutePath.toString)) + } + )) + require(cpu.useVM && cpu.fpu.enable && cpu.useZba && cpu.useZbb && cpu.useZbs) + require(accelerator.ballDomain.ballNum == 4) + val gemminiOnly = accelerator.copy( + ballDomain = accelerator.ballDomain.copy( + ballNum = 1, + ballIdMappings = accelerator.ballDomain.ballIdMappings.filter(_.ballId == 0), + ballISA = accelerator.ballDomain.ballISA.filter(_.bid == 0) + ), + // Only the removed MXFP converter consumes this private scale-byte pool. + // This is unrelated to the CPU's external MMIO/peripheral AXI port. + memDomain = accelerator.memDomain.copy(mmioEnable = false) + ) + require(gemminiOnly.ballDomain.ballIdMappings.map(_.ballName) == Seq("GemminiBall")) + require(gemminiOnly.ballDomain.ballIdMappings.forall(m => m.mmioReadBW == 0 && m.mmioWriteBW == 0)) + // Keep all 23 Gemmini instructions and the 8x8 arithmetic profile. + // Eight physical banks hold 64 KiB; architectural virtual IDs stay 0..15. + val serial = gemminiOnly.copy( + ballDomain = gemminiOnly.ballDomain.copy( + ballIdMappings = gemminiOnly.ballDomain.ballIdMappings.map(mapping => + mapping.copy(config = Some(Paths.get("config/gemmini-8.toml").toAbsolutePath.toString)))), + frontend = gemminiOnly.frontend.copy(sub_rob_depth = 8), + memDomain = gemminiOnly.memDomain.copy( + bankNum = 8, bankWidth = 64, bankMaskLen = 8, dma_buswidth = 64, dma_n_xacts = 2, max_in_flight_mem_reqs = 4, + tmaReadChannel = 1, tmaWriteChannel = 1) + ) + require(serial.memDomain.bankChannel == 7) +} + +class WithArtyLinuxPorts extends Config((site, here, up) => { + case FpgaSharedFma => true + case ExtMem => Some(MemoryPortParams( + master = MasterPortParams(BigInt("80000000", 16), BigInt(256) * 1024 * 1024, 16, 4, 64), + nMemoryChannels = 1 + )) + // Reserve the original SCU address range for the physical peripheral bridge. + case ExtBus => Some(MasterPortParams(BigInt("60000000", 16), BigInt("10000000", 16), 8, 2, 8)) + case ExtIn => None + case DebugModuleKey => None + case BootROMLocated(InSubsystem) => Seq(BootROMParams( + hang = BigInt("10000", 16), + appendDTB = true, + contentFileName = SystemFileName("upstream/arch/src/main/resources/bootrom/linux/bootrom.rv64.img") + )) + case SystemBusKey => up(SystemBusKey, site).copy(beatBytes = 16, dtsFrequency = Some(BigInt(50000000))) + case MemoryBusKey => up(MemoryBusKey, site).copy(beatBytes = 16, dtsFrequency = Some(BigInt(50000000))) + case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = Some(BigInt(50000000))) + case ControlBusKey => up(ControlBusKey, site).copy(dtsFrequency = Some(BigInt(50000000))) + case FrontBusKey => up(FrontBusKey, site).copy(dtsFrequency = Some(BigInt(50000000))) + // FPGA clock enables replace ASIC clock gates; execution features stay intact. + case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site).map { + case attachment: BBTileAttachParams => + val tile = attachment.tileParams + attachment.copy(tileParams = tile.copy( + core = tile.core.copy(clockGate = false, haveSimTimeout = false, + fpu = tile.core.fpu.map(f => f.copy(sfmaLatency = f.dfmaLatency))), + rocketCorePerCore = tile.rocketCorePerCore.map(c => c.copy(clockGate = false, haveSimTimeout = false, + fpu = c.fpu.map(f => f.copy(sfmaLatency = f.dfmaLatency)))), + dcache = tile.dcache.map(_.copy(clockGate = false)) + )) + case other => other + } +}) + +class ToyLinuxConfig(accelerator: GlobalConfig = OriginalToy.accelerator, withL2: Boolean = true) extends Config( + new WithArtyLinuxPorts ++ + new WithBBTile( + tileParam = accelerator.tile, + buckyballConfig = accelerator, + rocketCpuPerCore = Some(Seq(OriginalToy.cpu)) + ) ++ + new WithNExtTopInterrupts(1) ++ + new WithDTS("ucb-bar,buckyball", Nil) ++ + (if (withL2) new WithInclusiveCache(capacityKB = 64) else new Config((site, here, up) => PartialFunction.empty)) ++ + new WithCoherentBusTopology ++ + new freechips.rocketchip.system.BaseConfig +) + +// Remove optional debug facilities and unused auxiliary RAM only. +// Linux privilege levels, MMU, FPU, caches and architectural counters stay intact. +class WithTrimOptionalPeripherals extends Config((site, here, up) => { + case TrimOptionalPeripherals => true + case TilesLocated(InSubsystem) => + def trim(core: RocketCoreParams): RocketCoreParams = { + require(core.nPerfCounters == 0, "The baseline already has no extra HPM counters") + require(core.haveBasicCounters && core.useVM && core.fpu.nonEmpty) + core.copy(useDebug = false, nBreakpoints = 0, useBPWatch = false) + } + up(TilesLocated(InSubsystem), site).map { + case attachment: BBTileAttachParams => + val tile = attachment.tileParams + attachment.copy(tileParams = tile.copy( + core = trim(tile.core), + rocketCorePerCore = tile.rocketCorePerCore.map(trim) + )) + case other => other + } +}) + +class ToyLinuxTrimmedConfig extends Config( + new WithTrimOptionalPeripherals ++ new ToyLinuxConfig +) + +// Capacity and speculation tradeoffs only; keep the ISA and coherence protocol. +class WithCompactCaches extends Config((site, here, up) => { + case CompactCaches => true + case InclusiveCacheKey => + val cache = up(InclusiveCacheKey, site) + require(cache.ways == 8 && cache.sets == 128) + cache.copy(ways = 4) // 128 sets * 4 ways * 64 bytes = 32 KiB. + case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site).map { + case attachment: BBTileAttachParams => + val tile = attachment.tileParams + attachment.copy(tileParams = tile.copy( + btb = None, + icache = tile.icache.map(_.copy(nWays = 2)), // 64 sets, 8 KiB. + dcache = tile.dcache.map(_.copy(nMSHRs = 1)) // Capacity stays 8 KiB. + )) + case other => other + } +}) + +class ToyLinuxCompactConfig extends Config( + new WithCompactCaches ++ new ToyLinuxTrimmedConfig +) + +class WithGemminiOnlyMarker extends Config((site, here, up) => { + case GemminiOnlyBalls => true +}) + +class ToyLinuxGemminiOnlyConfig extends Config( + new WithGemminiOnlyMarker ++ new WithCompactCaches ++ + new WithTrimOptionalPeripherals ++ new ToyLinuxConfig(OriginalToy.gemminiOnly) +) + + +// Broadcast coherence still probes dirty CPU cache lines for accelerator DMA. +// It replaces the inclusive data cache, not the coherence protocol. +class WithSerialFpga extends Config((site, here, up) => { + case SerialFpga => true + case GemminiOnlyBalls => true + case CompactCaches => true + case BroadcastKey => up(BroadcastKey).copy(nTrackers = 2) + case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site).map { + case attachment: BBTileAttachParams => + val tile = attachment.tileParams + attachment.copy(tileParams = tile.copy( + btb = None, + icache = tile.icache.map(_.copy(nWays = 2)), + dcache = tile.dcache.map(_.copy(nMSHRs = 1)) + )) + case other => other + } +}) + +class ToyLinux8x8Config extends Config( + new WithSerialFpga ++ new WithTrimOptionalPeripherals ++ + new ToyLinuxConfig(OriginalToy.serial, withL2 = false) +) diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/PLATFORM_PORTS_MANIFEST.json b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/PLATFORM_PORTS_MANIFEST.json new file mode 100644 index 0000000..3c892d5 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/PLATFORM_PORTS_MANIFEST.json @@ -0,0 +1,7 @@ +{ + "source_core_sha256": "31e7e07f94d08208dbb564edf9546240df26ff834935bfb646b71b541d875fb9", + "port_header_sha256": "3329804932f5a7632f78bbe56797f9bff35fb6f94910f0a474c59a9a0a90bf5d", + "stub_sha256": "e4c06220cd7025972d432b06c452e85c62bd2cfccad618b2b993499b62e6621a", + "cpu_behavior_included": false, + "port_header_hash_encoding": "UTF-8 with LF newlines" +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/REFERENCE_MANIFEST.json b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/REFERENCE_MANIFEST.json new file mode 100644 index 0000000..b6d0d0c --- /dev/null +++ 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diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/ToyLinuxChipPorts.sv b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/ToyLinuxChipPorts.sv new file mode 100644 index 0000000..6e07c67 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/ToyLinuxChipPorts.sv @@ -0,0 +1,134 @@ +// Port-only fixture from the Chisel-generated core; no CPU behavior. +// Outputs idle at zero. The testbench drives the real platform AXI port. +module ToyLinuxChip( + input clock, + reset, + interrupt, + memory_aw_ready, + output memory_aw_valid, + output [3:0] memory_aw_bits_id, + output [31:0] memory_aw_bits_addr, + output [7:0] memory_aw_bits_len, + output [2:0] memory_aw_bits_size, + output [1:0] memory_aw_bits_burst, + output memory_aw_bits_lock, + output [3:0] memory_aw_bits_cache, + output [2:0] memory_aw_bits_prot, + output [3:0] memory_aw_bits_qos, + input memory_w_ready, + output memory_w_valid, + output [127:0] memory_w_bits_data, + output [15:0] memory_w_bits_strb, + output memory_w_bits_last, + memory_b_ready, + input memory_b_valid, + input [3:0] memory_b_bits_id, + input [1:0] memory_b_bits_resp, + input memory_ar_ready, + output memory_ar_valid, + output [3:0] memory_ar_bits_id, + output [31:0] memory_ar_bits_addr, + output [7:0] memory_ar_bits_len, + output [2:0] memory_ar_bits_size, + output [1:0] memory_ar_bits_burst, + output memory_ar_bits_lock, + output [3:0] memory_ar_bits_cache, + output [2:0] memory_ar_bits_prot, + output [3:0] memory_ar_bits_qos, + output memory_r_ready, + input memory_r_valid, + input [3:0] memory_r_bits_id, + input [127:0] memory_r_bits_data, + input [1:0] memory_r_bits_resp, + input memory_r_bits_last, + peripherals_aw_ready, + output peripherals_aw_valid, + output [1:0] peripherals_aw_bits_id, + output [30:0] peripherals_aw_bits_addr, + output [7:0] peripherals_aw_bits_len, + output [2:0] peripherals_aw_bits_size, + output [1:0] peripherals_aw_bits_burst, + output peripherals_aw_bits_lock, + output [3:0] peripherals_aw_bits_cache, + output [2:0] peripherals_aw_bits_prot, + output [3:0] peripherals_aw_bits_qos, + input peripherals_w_ready, + output peripherals_w_valid, + output [63:0] peripherals_w_bits_data, + output [7:0] peripherals_w_bits_strb, + output peripherals_w_bits_last, + peripherals_b_ready, + input peripherals_b_valid, + input [1:0] peripherals_b_bits_id, + peripherals_b_bits_resp, + input peripherals_ar_ready, + output peripherals_ar_valid, + output [1:0] peripherals_ar_bits_id, + output [30:0] peripherals_ar_bits_addr, + output [7:0] peripherals_ar_bits_len, + output [2:0] peripherals_ar_bits_size, + output [1:0] peripherals_ar_bits_burst, + output peripherals_ar_bits_lock, + output [3:0] peripherals_ar_bits_cache, + output [2:0] peripherals_ar_bits_prot, + output [3:0] peripherals_ar_bits_qos, + output peripherals_r_ready, + input peripherals_r_valid, + input [1:0] peripherals_r_bits_id, + input [63:0] peripherals_r_bits_data, + input [1:0] peripherals_r_bits_resp, + input peripherals_r_bits_last +); + assign memory_aw_valid = '0; + assign memory_aw_bits_id = '0; + assign memory_aw_bits_addr = '0; + assign memory_aw_bits_len = '0; + assign memory_aw_bits_size = '0; + assign memory_aw_bits_burst = '0; + assign memory_aw_bits_lock = '0; + assign memory_aw_bits_cache = '0; + assign memory_aw_bits_prot = '0; + assign memory_aw_bits_qos = '0; + assign memory_w_valid = '0; + assign memory_w_bits_data = '0; + assign memory_w_bits_strb = '0; + assign memory_w_bits_last = '0; + assign memory_b_ready = '0; + assign memory_ar_valid = '0; + assign memory_ar_bits_id = '0; + assign memory_ar_bits_addr = '0; + assign memory_ar_bits_len = '0; + assign memory_ar_bits_size = '0; + assign memory_ar_bits_burst = '0; + assign memory_ar_bits_lock = '0; + assign memory_ar_bits_cache = '0; + assign memory_ar_bits_prot = '0; + assign memory_ar_bits_qos = '0; + assign memory_r_ready = '0; + assign peripherals_aw_valid = '0; + assign peripherals_aw_bits_id = '0; + assign peripherals_aw_bits_addr = '0; + assign peripherals_aw_bits_len = '0; + assign peripherals_aw_bits_size = '0; + assign peripherals_aw_bits_burst = '0; + assign peripherals_aw_bits_lock = '0; + assign peripherals_aw_bits_cache = '0; + assign peripherals_aw_bits_prot = '0; + assign peripherals_aw_bits_qos = '0; + assign peripherals_w_valid = '0; + assign peripherals_w_bits_data = '0; + assign peripherals_w_bits_strb = '0; + assign peripherals_w_bits_last = '0; + assign peripherals_b_ready = '0; + assign peripherals_ar_valid = '0; + assign peripherals_ar_bits_id = '0; + assign peripherals_ar_bits_addr = '0; + assign peripherals_ar_bits_len = '0; + assign peripherals_ar_bits_size = '0; + assign peripherals_ar_bits_burst = '0; + assign peripherals_ar_bits_lock = '0; + assign peripherals_ar_bits_cache = '0; + assign peripherals_ar_bits_prot = '0; + assign peripherals_ar_bits_qos = '0; + assign peripherals_r_ready = '0; +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/axi_smoke_memory.sv b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/axi_smoke_memory.sv new file mode 100644 index 0000000..f8e7dc6 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/axi_smoke_memory.sv @@ -0,0 +1,115 @@ +// Single outstanding read and write, with independent AXI channels. +// Backpressure is legal: W is accepted after AW; R/B are held until accepted. +module axi_smoke_memory #( + parameter DATA_BITS=128, ID_BITS=4, ADDR_BITS=32, + parameter BASE=32'h80000000, CAPACITY=262144, + parameter IMAGE="", parameter MONITOR=0, + parameter TEST_LABEL="whole Toy CPU smoke" +) ( + input clock, reset, + output aw_ready, input aw_valid, + input [ID_BITS-1:0] aw_bits_id, + input [ADDR_BITS-1:0] aw_bits_addr, + input [7:0] aw_bits_len, input [2:0] aw_bits_size, + input [1:0] aw_bits_burst, + output w_ready, input w_valid, + input [DATA_BITS-1:0] w_bits_data, + input [DATA_BITS/8-1:0] w_bits_strb, input w_bits_last, + input b_ready, output reg b_valid, + output reg [ID_BITS-1:0] b_bits_id, output [1:0] b_bits_resp, + output ar_ready, input ar_valid, + input [ID_BITS-1:0] ar_bits_id, + input [ADDR_BITS-1:0] ar_bits_addr, + input [7:0] ar_bits_len, input [2:0] ar_bits_size, + input [1:0] ar_bits_burst, + input r_ready, output reg r_valid, + output reg [ID_BITS-1:0] r_bits_id, + output reg [DATA_BITS-1:0] r_bits_data, + output [1:0] r_bits_resp, output reg r_bits_last +); + localparam LANES=DATA_BITS/8; + reg [7:0] mem [0:CAPACITY-1]; + reg write_active; + reg [ADDR_BITS-1:0] write_addr, read_addr; + reg [7:0] write_remaining, read_remaining; + reg [2:0] write_size, read_size; + reg [3:0] stall_cycle; + integer read_bursts, write_bursts; + assign aw_ready = !write_active && !b_valid && stall_cycle[1:0]!=0; + assign w_ready = write_active && !b_valid && stall_cycle[2:0]!=0; + assign ar_ready = !r_valid && stall_cycle[1:0]!=1; + assign b_bits_resp = 0; + assign r_bits_resp = 0; + + initial begin + for (integer i=0; iCAPACITY) + $fatal(1,"AXI read out of range: %h",addr); + for (integer lane=0; laneCAPACITY) + $fatal(1,"AXI write out of range: %h",write_addr); + if (w_bits_last != (write_remaining==0)) $fatal(1,"WLAST mismatch"); + for (integer lane=0; lane=0;n=n-1) c=(c<<1)^((c[15]^value[n]) ? 16'h1021 : 16'd0); + crc_step=c; + end + endfunction + task automatic byte_send(input [7:0] value); + begin @(negedge clk);rx_data=value;rx_valid=1;@(negedge clk);rx_valid=0;end + endtask + task automatic request(input [7:0] op,input [31:0] address,input [15:0] length,input bit corrupt); + reg [15:0] crc; + reg [7:0] value; + begin + received=0;crc=16'hffff; + byte_send(8'ha5);byte_send(8'h5a); + byte_send(op);crc=crc_step(crc,op); + byte_send(8'h37);crc=crc_step(crc,8'h37); + for(integer n=0;n<4;n=n+1) begin + value=address>>(n*8);byte_send(value);crc=crc_step(crc,value); + end + byte_send(length[7:0]);crc=crc_step(crc,length[7:0]); + byte_send(length[15:8]);crc=crc_step(crc,length[15:8]); + if(op==1) for(integer n=0;n 0, "The test did not exercise dirty writeback to external memory" + record = { + "result": "PASS", + "test_label": args.label, + "core_rtl_sha256": hashlib.sha256(core.read_bytes()).hexdigest(), + "test_binary_sha256": hashlib.sha256(binary.read_bytes()).hexdigest(), + "cycles_including_boot": cycles, + "memory_read_bursts": reads, + "memory_write_bursts": writes, + "linux_boot_tested": False, + } + (out / "RESULT.json").write_text(json.dumps(record, indent=2) + "\n") + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/check_dma_beat64.py b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/check_dma_beat64.py new file mode 100644 index 0000000..b29cc80 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/check_dma_beat64.py @@ -0,0 +1,55 @@ +"""Check unaligned and strided DMA round trips, with guards and page crossings.""" + +import subprocess +import sys +from pathlib import Path + +ROOT = Path(__file__).resolve().parents[1] +out = ROOT / "build/dma-beat64" +out.mkdir(parents=True, exist_ok=True) +library = ROOT / "tests/reference/bb-tests/workloads/lib" +elf = out / "dma.elf" +subprocess.run( + [ + "riscv64-unknown-elf-gcc", + "-O2", + "-ffreestanding", + "-fno-builtin", + "-ffunction-sections", + "-fdata-sections", + "-msmall-data-limit=0", + "-mcmodel=medany", + "-march=rv64imafdc_zicsr_zifencei_zfh", + "-mabi=lp64d", + "-I", + str(ROOT / "build/software"), + "-I", + str(library), + "-nostdlib", + "-nostartfiles", + "-Wl,--no-relax,--gc-sections", + "-T", + str(ROOT / "tests/cpu_smoke.ld"), + str(ROOT / "tests/gemmini_start.S"), + str(ROOT / "tests/dma_beat64.c"), + str(ROOT / "tests/gemmini_runtime.c"), + str(library / "buckyball.c"), + "-lgcc", + "-o", + str(elf), + ], + check=True, +) +subprocess.run( + [ + sys.executable, + str(ROOT / "tests/check_cpu_smoke.py"), + "--program-elf", + str(elf), + "--output-dir", + str(out / "simulation"), + "--label", + "whole Toy unaligned DMA 64 bit beats", + ], + check=True, +) diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/check_fpga_memories.py b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/check_fpga_memories.py new file mode 100644 index 0000000..6e41a8c --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/check_fpga_memories.py @@ -0,0 +1,213 @@ +"""Compare FPGA SRAM macros with the actual pre-mapping Chisel memory RTL. + +Initialize every row, exercise every write-mask lane, disabled writes, random +transactions, and read back the full memory. Check only defined read cycles. +""" + +import argparse +import json +import re +import subprocess +from pathlib import Path + + +def find_reference(original, mem): + for match in re.finditer(r"^module (\w+)\(.*?^endmodule", original, re.M | re.S): + body = match.group() + width, depth = mem["width"], mem["depth"] + pattern = rf"reg\s+\[{width-1}:0\]\s+Memory\[0:{depth-1}\]" + data_port = "R0_data" if mem["read"] else "RW0_wmode" + mask_name = "W0_mask" if mem["read"] else "RW0_wmask" + if not re.search(pattern, body) or data_port not in body: + continue + if mem["masked"]: + lanes = width // mem["mask_granularity"] + if not re.search(rf"input\s+\[{lanes-1}:0\]\s+{mask_name}", body): + continue + elif mask_name in body: + continue + name = mem["module_name"] + "_reference" + return re.sub(r"^module \w+", "module " + name, body), name + raise ValueError(f"No original Chisel memory matches {mem['module_name']}") + + +def dual_bench(mem, reference): + name, width, depth = mem["module_name"], mem["width"], mem["depth"] + gran = mem.get("mask_granularity", width) + lanes = width // gran + mask_port = ", .W0_mask(mask)" if mem["masked"] else "" + connections = ( + ".R0_addr(ra), .R0_clk(clk), .R0_en(re), " + ".W0_addr(wa), .W0_clk(clk), .W0_en(we), .W0_data(data)" + ) + return f""" +module test_{name}(output reg done = 0); + localparam W={width}, D={depth}, G={gran}, M={lanes}; + reg clk=0; + always #5 clk=~clk; + reg [{(depth-1).bit_length()-1}:0] ra=0, wa=0; + reg re=0, we=0; + reg [W-1:0] data=0; + reg [M-1:0] mask=0; + wire [W-1:0] actual, reference; + reg [W-1:0] model[0:D-1]; + integer seed=98765; + {name} dut({connections}{mask_port}, .R0_data(actual)); + {reference} original({connections}{mask_port}, .R0_data(reference)); + task step(input integer r, input integer w, input bit ren, + input bit wen, input [M-1:0] m); + reg [W-1:0] expected; + begin + @(negedge clk); + ra=r; wa=w; re=ren; we=wen; mask=m; + for (integer b=0; b", + "struct Vector { uint64_t a,b,c,expected; unsigned tag,kind,op,rm,flags; };", + "static const struct Vector vectors[] = {"] +for tag, kind, op, rm, a, b, c, expected, flags in rows: + code.append(f" {{0x{a:x}ULL,0x{b:x}ULL,0x{c:x}ULL,0x{expected:x}ULL,{tag},{kind},{op},{rm},{flags}}},") +code += ["};", "static uint64_t execute(const struct Vector *v, uint64_t *flags) {", + " uint64_t result = 0, f;", ' asm volatile("csrw frm, %0" :: "r"((uint64_t)v->rm));'] +for tag, precision, load, store in ((0, "h", "flh", "fsh"), (1, "s", "flw", "fsw"), (2, "d", "fld", "fsd")): + code += [f" {'if' if tag == 0 else 'else if'} (v->tag == {tag}) {{"] + for kind, op, instruction, operands in ( + (0, 0, "fmadd", "ft3, ft0, ft1, ft2, dyn"), + (0, 1, "fmsub", "ft3, ft0, ft1, ft2, dyn"), + (0, 2, "fnmsub", "ft3, ft0, ft1, ft2, dyn"), + (0, 3, "fnmadd", "ft3, ft0, ft1, ft2, dyn"), + (1, 0, "fadd", "ft3, ft0, ft2, dyn"), + (1, 1, "fsub", "ft3, ft0, ft2, dyn"), + (2, 0, "fmul", "ft3, ft0, ft1, dyn"), + ): + code += [f" if (v->kind == {kind} && v->op == {op}) {{", + ' asm volatile("csrw fflags, zero\\n"', + f' "{load} ft0, 0(%2)\\n{load} ft1, 8(%2)\\n{load} ft2, 16(%2)\\n"', + f' "{instruction}.{precision} {operands}\\n{store} ft3, 0(%1)\\nfrflags %0\\n"', + ' : "=r"(f) : "r"(&result), "r"(v)', + ' : "memory", "ft0", "ft1", "ft2", "ft3");', + " }"] + code += [" }"] +code += [" *flags = f; return result;", "}", "static int dependency_benchmark(void) {", + " volatile uint64_t *status = (volatile uint64_t *)0x60000000ULL;"] +for tag, precision, load, store, one, expected in ( + (0, "h", "flh", "fsh", 0x3c00, 0x6401), + (1, "s", "flw", "fsw", 0x3f800000, 0x44802000), + (2, "d", "fld", "fsd", 0x3ff0000000000000, 0x4090040000000000), +): + code += [" {", f" uint64_t one=0x{one:x}ULL, result=0, begin, end;", + f' asm volatile("{load} ft0, 0(%2)\\n{load} ft1, 0(%2)\\nli t0, 32\\ncsrr %0, cycle\\n"', + f' "1: .rept 32\\nfadd.{precision} ft0, ft0, ft1, rne\\n.endr\\n"', + f' "addi t0, t0, -1\\nbnez t0, 1b\\n{store} ft0, 0(%3)\\ncsrr %1, cycle\\n"', + ' : "=&r"(begin), "=&r"(end) : "r"(&one), "r"(&result)', + ' : "memory", "t0", "ft0", "ft1");', + f" if (result != 0x{expected:x}ULL) return 32;", + f" status[0] = 0x{0x7300000000000000 | (tag << 32):016x}ULL | (end-begin);", " }"] +code += [" return 0;", "}", "int main(void) {", + " volatile uint64_t *status = (volatile uint64_t *)0x60000000ULL;", + " for (unsigned i = 0; i < sizeof(vectors)/sizeof(vectors[0]); ++i) {", + " uint64_t flags; uint64_t actual = execute(&vectors[i], &flags);", + " if (actual != vectors[i].expected || flags != vectors[i].flags) {", + " status[2] = i; status[3] = actual; status[4] = vectors[i].expected;", + " status[5] = flags; status[6] = vectors[i].flags; return 31;", " }", " }", + " return dependency_benchmark();", "}"] +source = out / "fpu_vectors.c" +source.write_text("\n".join(code) + "\n") +elf = out / "fpu_vectors.elf" +subprocess.run([ + "riscv64-unknown-elf-gcc", "-O2", "-ffreestanding", "-fno-builtin", "-ffunction-sections", + "-fdata-sections", "-msmall-data-limit=0", "-mcmodel=medany", "-march=rv64imafdc_zicsr_zifencei_zfh", + "-mabi=lp64d", "-nostdlib", "-nostartfiles", "-Wl,--no-relax,--gc-sections", "-T", + str(ROOT / "tests/cpu_smoke.ld"), str(ROOT / "tests/gemmini_start.S"), str(source), + str(ROOT / "tests/gemmini_runtime.c"), "-lgcc", "-o", str(elf)], check=True) +subprocess.run([sys.executable, str(ROOT / "tests/check_cpu_smoke.py"), "--program-elf", str(elf), + "--output-dir", str(out / "simulation"), "--label", "whole Toy shared FPU 1536 oracle vectors"], check=True) +baseline_output = out / "baseline-simulation" +subprocess.run([sys.executable, str(ROOT / "tests/check_cpu_smoke.py"), "--program-elf", str(elf), + "--core-dir", str(args.baseline_core), + "--output-dir", str(baseline_output), "--label", "whole Toy baseline FPU 1536 oracle vectors"], check=True) +def measures(path): + log = (path / "simulation.log").read_text() + cycles = {int(tag): int(value, 16) for tag, value in re.findall(r"CPU status = 7300000([012])([0-9a-f]{8})", log)} + assert set(cycles) == {0, 1, 2} + return cycles +new_cycles = measures(out / "simulation") +old_cycles = measures(baseline_output) +record = {"result": "PASS", "vector_count": len(rows), "precision_counts": [sum(row[0] == tag for row in rows) for tag in range(3)], + "rounding_modes": sorted({row[3] for row in rows}), "vector_sha256": hashlib.sha256(vectors.read_bytes()).hexdigest(), + "oracle": "unchanged original H/S/D FPUFMAPipe data and exception flags", + "regression": json.loads((out / "simulation/RESULT.json").read_text()), + "baseline_regression": json.loads((baseline_output / "RESULT.json").read_text()), + "dependency_benchmark": {"operation": "1024 dependent FADD; groups of 32, including loop overhead and final store", + "baseline_cycles_HSD": old_cycles, "candidate_cycles_HSD": new_cycles, + "delta_cycles_HSD": {tag: new_cycles[tag] - old_cycles[tag] for tag in range(3)}}} +assert record["regression"]["test_binary_sha256"] == record["baseline_regression"]["test_binary_sha256"] +(out / "RESULT.json").write_text(json.dumps(record, indent=2) + "\n") diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/check_gemmini.py b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/check_gemmini.py new file mode 100644 index 0000000..a501064 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/check_gemmini.py @@ -0,0 +1,165 @@ +"""Run pinned upstream Gemmini C tests on the complete emitted chip.""" + +import argparse +import hashlib +import json +import re +import subprocess +import sys +from pathlib import Path + +ROOT = Path(__file__).resolve().parents[1] + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--core-dir", type=Path, default=ROOT / "build/serial-bound") + parser.add_argument("--output-dir", type=Path, default=ROOT / "build/gemmini-tests") + parser.add_argument("--cases", nargs="+") + parser.add_argument("--diagnostic", action="store_true") + args = parser.parse_args() + out = args.output_dir.resolve() + out.mkdir(parents=True, exist_ok=True) + reference = ROOT / "tests/reference" + manifest = json.loads((ROOT / "tests/REFERENCE_MANIFEST.json").read_text()) + for name, expected in manifest["files"].items(): + assert hashlib.sha256((reference / name).read_bytes()).hexdigest() == expected + library = reference / "bb-tests/workloads/lib" + workloads = reference / "examples/balls/gemmini/workloads" + config = json.loads((ROOT / "build/original-toy.json").read_text()) + entries = config["accelerator"]["ballDomain"]["ballISA"] + (out / "ballISA.h").write_text( + "// Retained Gemmini encodings, unchanged from upstream.\n" + + "\n".join( + f"#define BB_FUNC7_{e['mnemonic']} {e['funct7']}" + for e in entries + if e["bid"] == 0 + ) + + "\n" + ) + (out / "params.h").write_text( + "#define BANK_WIDTH 64\n#define VIRTUAL_BANK_NUM 16\n" + ) + sources = sorted((workloads / "ctests").glob("*.c")) + if args.cases: + sources = [p for p in sources if p.stem in args.cases] + assert {p.stem for p in sources} == set(args.cases) + adapted = out / "dimension-8-sources" + adapted.mkdir(exist_ok=True) + adapted_sources = [] + for source in sources: + text = source.read_text() + assert "#define DIM 16" in text, source + target = adapted / source.name + target.write_text(text.replace("#define DIM 16", "#define DIM 8")) + adapted_sources.append(target) + sources = adapted_sources + common = [ + "riscv64-unknown-elf-gcc", + "-O2", + "-ffreestanding", + "-fno-builtin", + "-ffunction-sections", + "-fdata-sections", + "-msmall-data-limit=0", + "-mcmodel=medany", + "-march=rv64imafdc_zicsr_zifencei_zfh", + "-mabi=lp64d", + "-I", + str(out), + "-I", + str(library), + "-I", + str(workloads), + ] + objects = [] + for i, source in enumerate(sources, 1): + obj = out / f"case_{i}.o" + subprocess.run( + common + [f"-Dmain=case_{i}", "-c", str(source), "-o", str(obj)], check=True + ) + objects.append(obj) + runner = out / "runner.c" + lines = ["#include "] + lines += [f"int case_{i}(void);" for i in range(1, len(sources) + 1)] + lines += ["int main(void) {", " volatile uint64_t *status=(void *)0x60000000;"] + for i in range(1, len(sources) + 1): + lines += [ + f" *status=0x71000000u+{i};", + f" if (case_{i}()) return {i};", + f" *status=0x72000000u+{i};", + ] + lines += [" return 0;", "}"] + runner.write_text("\n".join(lines) + "\n") + elf = out / "gemmini.elf" + subprocess.run( + common + + [ + "-nostdlib", + "-nostartfiles", + "-Wl,--no-relax,--gc-sections", + "-T", + str(ROOT / "tests/cpu_smoke.ld"), + str(ROOT / "tests/gemmini_start.S"), + str(runner), + str(ROOT / "tests/gemmini_runtime.c"), + str(library / "buckyball.c"), + *map(str, objects), + "-lgcc", + "-o", + str(elf), + ], + check=True, + ) + (out / "CASES.json").write_text( + json.dumps({i: p.stem for i, p in enumerate(sources, 1)}, indent=2) + "\n" + ) + simulation = subprocess.run( + [ + sys.executable, + str(ROOT / "tests/check_cpu_smoke.py"), + "--program-elf", + str(elf), + "--core-dir", + str(args.core_dir.resolve()), + "--output-dir", + str(out / "simulation"), + "--label", + "whole Toy Gemmini regression", + *(["--diagnostic-accelerator"] if args.diagnostic else []), + ], + check=False, + ) + output = (out / "simulation/simulation.log").read_text() + passed = [ + int(x, 16) & 0xFFFF + for x in re.findall(r"CPU status = (0000000072[0-9a-f]+)", output) + ] + succeeded = simulation.returncode == 0 and passed == list( + range(1, len(sources) + 1) + ) + failures = [ + int(x, 16) & 0xFFFF + for x in re.findall(r"CPU status = (00000000bad0[0-9a-f]+)", output) + ] + record = { + "result": "PASS" if succeeded else "FAIL", + "upstream_commit": manifest["commit"], + "tests": [p.stem for p in sources], + "test_count": len(sources), + "passed_tests": [sources[i - 1].stem for i in passed], + "failed_status_codes": failures, + "runtime": ( + "bare-metal adapter; dimension adapted 16->8; " + "unchanged upstream test bodies/ISA/matrix reference" + ), + "simulation_returncode": simulation.returncode, + } + (out / "RESULT.json").write_text(json.dumps(record, indent=2) + "\n") + print(f"{len(passed)}/{len(sources)} upstream Gemmini workloads passed") + if not succeeded: + raise SystemExit(1) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/check_loop_stress.py b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/check_loop_stress.py new file mode 100644 index 0000000..509dceb --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/check_loop_stress.py @@ -0,0 +1,58 @@ +"""Run alternating OS/WS multi-tile loops across internal mesh-tag wrap.""" + +import subprocess +import sys +from pathlib import Path + +ROOT = Path(__file__).resolve().parents[1] +out = ROOT / "build/loop-stress" +out.mkdir(parents=True, exist_ok=True) +library = ROOT / "tests/reference/bb-tests/workloads/lib" +workloads = ROOT / "tests/reference/examples/balls/gemmini/workloads" +elf = out / "stress.elf" +subprocess.run( + [ + "riscv64-unknown-elf-gcc", + "-O2", + "-ffreestanding", + "-fno-builtin", + "-ffunction-sections", + "-fdata-sections", + "-msmall-data-limit=0", + "-mcmodel=medany", + "-march=rv64imafdc_zicsr_zifencei_zfh", + "-mabi=lp64d", + "-I", + str(ROOT / "build/software"), + "-I", + str(library), + "-I", + str(workloads), + "-nostdlib", + "-nostartfiles", + "-Wl,--no-relax,--gc-sections", + "-T", + str(ROOT / "tests/cpu_smoke.ld"), + str(ROOT / "tests/gemmini_start.S"), + str(ROOT / "tests/serial_loop_stress.c"), + str(ROOT / "tests/gemmini_runtime.c"), + str(library / "buckyball.c"), + "-lgcc", + "-o", + str(elf), + ], + check=True, +) +subprocess.run( + [ + sys.executable, + str(ROOT / "tests/check_cpu_smoke.py"), + "--program-elf", + str(elf), + "--output-dir", + str(out / "simulation"), + "--label", + "whole Toy 40 alternating multi tile OS WS loops", + ], + check=True, +) diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/check_pe.py b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/check_pe.py new file mode 100644 index 0000000..5f54ca1 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/check_pe.py @@ -0,0 +1,129 @@ +"""Prove the quantizer and compare original/LUT/DSP PEs cycle by cycle.""" + +import argparse +import subprocess +from pathlib import Path + +ROOT = Path(__file__).resolve().parents[1] + + +def rtl(path): + data = path.read_text() + marker = '// ----- 8< ----- FILE "firrtl_black_box_resource_files.f" ----- 8< -----' + if marker in data: + data, filelist = data.split(marker) + assert all(x.strip().endswith(".v") for x in filelist.splitlines() if x.strip()) + output = path.with_name(path.stem + "_rtl.sv") + output.write_text(data) + return output + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--yosys", default="yosys") + args = parser.parse_args() + out = ROOT / "build/pe-checks" + quant = rtl(out / "quantizer/QuantizerEquivalence.sv") + command = ( + f"read_verilog -sv {quant}; prep -top QuantizerEquivalence -flatten; " + "sat -prove equal 1 -verify -show-inputs -show-outputs" + ) + with (out / "quantizer-proof.log").open("w") as log: + subprocess.run( + [args.yosys, "-p", command], stdout=log, stderr=log, check=True, timeout=180 + ) + cycles = rtl(out / "cycles/PeCycleEquivalence.sv") + bench = out / "tb_pe.sv" + bench.write_text( + """ +`timescale 1ns/1ps +module tb; + reg clock=0; + always #5 clock=~clock; + reg reset=0; + reg [7:0] in_a=0; + reg [19:0] in_b=0, in_d=0; + reg control_dataflow=0, control_propagate=0; + reg [4:0] control_shift=0; + reg [1:0] id=0; + reg last=0, valid=1; + wire equal; + integer checked=0; + integer seed=57201; + PeCycleEquivalence dut(.*); + task step(input bit df, input bit prop, input integer shift, + input integer a, input integer b, input integer d, + input bit v, input bit check); + begin + @(negedge clock); + control_dataflow=df; control_propagate=prop; control_shift=shift; + in_a=a; in_b=b; in_d=d; valid=v; + id=$random(seed); last=$random(seed); + #1; + if (check && v) begin + if (equal !== 1'b1) begin + $display("PE mismatch df=%0d prop=%0d shift=%0d",df,prop,shift); + $fatal(1,"a=%0d b=%0d d=%0d cycle=%0d",a,b,d,checked); + end + checked=checked+1; + end + @(posedge clock); #1; + end + endtask + initial begin + // Initialize both original accumulator registers through legal loading. + step(0,1,0,0,0,0,1,0); + step(0,0,0,0,0,0,1,0); + for (integer shift=0; shift<32; shift=shift+1) + for (integer df=0; df<2; df=df+1) + for (integer p=0; p<2; p=p+1) + for (integer n=0; n<16; n=n+1) begin + step(df,p,shift,(n&1)?-128:127,(n&2)?-524288:524287, + (n&4)?-524288:524287,1,1); + step(df,!p,shift,(n&1)?-1:1,(n&2)?-3:3,(n&4)?-1:1,1,1); + step(df,p,shift,0,0,0,0,1); + end + for (integer n=0; n<100000; n=n+1) + step($random(seed)&1,$random(seed)&1,$random(seed)&31, + $random(seed),$random(seed),$random(seed),($random(seed)&7)!=0,1); + $display("PASS original/LUT/DSP PE: %0d valid-cycle comparisons",checked); + $finish; + end + initial begin #2000000; $fatal(1,"PE test timeout"); end +endmodule +""" + ) + obj = out / "obj" + with (out / "verilator-build.log").open("w") as log: + subprocess.run( + [ + "verilator", + "--binary", + "--timing", + "-j", + "8", + "-Wno-fatal", + "-DSYNTHESIS", + "--top-module", + "tb", + "--Mdir", + str(obj), + str(cycles), + str(bench), + ], + stdout=log, + stderr=log, + check=True, + timeout=180, + ) + result = subprocess.run( + [str(obj / "Vtb")], capture_output=True, text=True, check=True, timeout=120 + ) + (out / "cycles-test.log").write_text(result.stdout + result.stderr) + assert "PASS original/LUT/DSP PE" in result.stdout + print("PASS formal quantizer equivalence for all 2^25 input/shift pairs") + print(result.stdout) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/check_routing.py b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/check_routing.py new file mode 100644 index 0000000..c34e412 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/check_routing.py @@ -0,0 +1,76 @@ +"""Exercise fixed routes using the real AccPipe and delayed SRAM responses.""" + +import hashlib +import json +import subprocess +from pathlib import Path + +ROOT = Path(__file__).resolve().parents[1] +out = ROOT / "build/routing-check" +rtl = out / "RoutingCheck.sv" +tb = out / "tb.sv" +tb.write_text( + """`timescale 1ns/1ps +module tb; + reg clock=0, reset=1; + wire passed; + RoutingCheck dut(.*); + always #5 clock=~clock; + initial begin + repeat(10) @(negedge clock); + reset=0; + wait(passed); + $display("PASS fixed routing: 512 transactions, DMA arbitration, stalls"); + $finish; + end + initial begin + repeat(20000) @(posedge clock); + $fatal(1, "Routing check timeout"); + end +endmodule +""" +) +subprocess.run( + [ + "verilator", + "--binary", + "--timing", + "--assert", + "-j", + "8", + "-Wno-fatal", + "--top-module", + "tb", + "--Mdir", + str(out / "obj"), + str(rtl), + str(tb), + ], + check=True, + stdout=subprocess.DEVNULL, +) +result = subprocess.run([str(out / "obj/Vtb")], capture_output=True, text=True) +(out / "simulation.log").write_text(result.stdout + result.stderr) +print(result.stdout) +assert result.returncode == 0 and "PASS fixed routing" in result.stdout +(out / "RESULT.json").write_text( + json.dumps( + { + "result": "PASS", + "transactions": 512, + "coverage": [ + "two Gemmini reads", + "four Gemmini writes", + "concurrent DMA requests", + "request stalls", + "response stalls", + "backend route look-ahead", + "opposite-direction request arriving during pending route", + "Ball release with responses pending", + ], + "rtl_sha256": hashlib.sha256(rtl.read_bytes()).hexdigest(), + }, + indent=2, + ) + + "\n" +) diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/check_ws_round.py b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/check_ws_round.py new file mode 100644 index 0000000..5b7b2db --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/check_ws_round.py @@ -0,0 +1,26 @@ +"""Run signed/tie/boundary shift cases on the full CPU/Gemmini chip.""" +import subprocess +import sys +from pathlib import Path + +ROOT = Path(__file__).resolve().parents[1] +out = ROOT / "build/ws-round-edges" +out.mkdir(parents=True, exist_ok=True) +library = ROOT / "tests/reference/bb-tests/workloads/lib" +workloads = ROOT / "tests/reference/examples/balls/gemmini/workloads" +elf = out / "edges.elf" +subprocess.run([ + "riscv64-unknown-elf-gcc", "-O2", "-ffreestanding", "-fno-builtin", + "-ffunction-sections", "-fdata-sections", "-msmall-data-limit=0", "-mcmodel=medany", + "-march=rv64imafdc_zicsr_zifencei_zfh", "-mabi=lp64d", + "-I", str(ROOT / "build/software"), "-I", str(library), "-I", str(workloads), + "-nostdlib", "-nostartfiles", "-Wl,--no-relax,--gc-sections", + "-T", str(ROOT / "tests/cpu_smoke.ld"), str(ROOT / "tests/gemmini_start.S"), + str(ROOT / "tests/ws_round_edges.c"), str(ROOT / "tests/gemmini_runtime.c"), + str(library / "buckyball.c"), "-lgcc", "-o", str(elf) +], check=True) +subprocess.run([ + sys.executable, str(ROOT / "tests/check_cpu_smoke.py"), "--program-elf", str(elf), + "--output-dir", str(out / "simulation"), + "--label", "whole Toy 64 OS WS RNE edge cases 4096 results" +], check=True) diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/check_ws_shift_edges.py b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/check_ws_shift_edges.py new file mode 100644 index 0000000..43ffe56 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/check_ws_shift_edges.py @@ -0,0 +1,26 @@ +"""Run signed/tie/boundary shift cases on the full CPU/Gemmini chip.""" +import subprocess +import sys +from pathlib import Path + +ROOT = Path(__file__).resolve().parents[1] +out = ROOT / "build/ws-shift-edges" +out.mkdir(parents=True, exist_ok=True) +library = ROOT / "tests/reference/bb-tests/workloads/lib" +workloads = ROOT / "tests/reference/examples/balls/gemmini/workloads" +elf = out / "edges.elf" +subprocess.run([ + "riscv64-unknown-elf-gcc", "-O2", "-ffreestanding", "-fno-builtin", + "-ffunction-sections", "-fdata-sections", "-msmall-data-limit=0", "-mcmodel=medany", + "-march=rv64imafdc_zicsr_zifencei_zfh", "-mabi=lp64d", + "-I", str(ROOT / "build/software"), "-I", str(library), "-I", str(workloads), + "-nostdlib", "-nostartfiles", "-Wl,--no-relax,--gc-sections", + "-T", str(ROOT / "tests/cpu_smoke.ld"), str(ROOT / "tests/gemmini_start.S"), + str(ROOT / "tests/ws_shift_edges.c"), str(ROOT / "tests/gemmini_runtime.c"), + str(library / "buckyball.c"), "-lgcc", "-o", str(elf) +], check=True) +subprocess.run([ + sys.executable, str(ROOT / "tests/check_cpu_smoke.py"), "--program-elf", str(elf), + "--output-dir", str(out / "simulation"), + "--label", "whole Toy 64 OS WS RNE edge cases 4096 results" +], check=True) diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/cpu_smoke.S b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/cpu_smoke.S new file mode 100644 index 0000000..c3caf3a --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/cpu_smoke.S @@ -0,0 +1,248 @@ +.option norvc +.option norelax +.section .text.init,"ax",@progbits +.globl _start +_start: + la t0, trap_handler + csrw mtvec, t0 + csrw medeleg, zero + csrw mie, zero + li s10, 0 + li s11, 0 + li gp, 1 + li t0, 0x60000000 + li t1, 0xb007 + sd t1, 0(t0) + + # EBREAK remains an ordinary architectural breakpoint exception. + li s10, 3 + ebreak + li t0, 1 + bne s11, t0, fail + # Debug CSR access is illegal when useDebug=false. + li s10, 2 + csrr t0, 0x7b0 + li t0, 2 + bne s11, t0, fail + # The removed auxiliary RAM must fault rather than hang or alias DDR. + li s10, 5 + li t0, 0x08000000 + ld t1, 0(t0) + li t0, 3 + bne s11, t0, fail + li s10, 0 + + li gp, 2 + csrr s0, mcycle + csrr s1, minstret + li t0, 256 +1: addi t0, t0, -1 + bnez t0, 1b + csrr t0, mcycle + bgeu s0, t0, fail + csrr t0, minstret + bgeu s1, t0, fail + + li gp, 3 + li t0, 0x0200bff8 + ld s0, 0(t0) + li t1, 256 +2: addi t1, t1, -1 + bnez t1, 2b + ld t1, 0(t0) + bgeu s0, t1, fail + li t0, 0x0c000004 + li t1, 1 + sw t1, 0(t0) + lw t2, 0(t0) + bne t1, t2, fail + + li gp, 4 + li t0, 0x6000 + csrs mstatus, t0 + li t0, 3 + fcvt.d.w f0, t0 + fadd.d f1, f0, f0 + fcvt.w.d t1, f1, rtz + li t2, 6 + bne t1, t2, fail + fcvt.s.w f0, t0 + fmul.s f1, f0, f0 + fcvt.w.s t1, f1, rtz + li t2, 9 + bne t1, t2, fail + fcvt.h.w f0, t0 + fadd.h f1, f0, f0 + fcvt.w.h t1, f1, rtz + li t2, 6 + bne t1, t2, fail + la t0, datum + fsd f1, 8(t0) + fld f2, 8(t0) + fmv.x.d t1, f1 + fmv.x.d t2, f2 + bne t1, t2, fail + + li gp, 5 + la t0, datum + li t1, 35 + sd t1, 0(t0) + li t2, 7 + amoadd.d t3, t2, (t0) + bne t1, t3, fail + ld t3, 0(t0) + li t1, 42 + bne t1, t3, fail + mul t3, t1, t2 + div t3, t3, t2 + bne t1, t3, fail + + # Indirect calls and returns at 512-byte spacing force I-cache conflicts. + # Each of 64 stubs is called three times, including with no BTB/RAS. + li gp, 9 + li s2, 0 + li s3, 3 +icache_pass: + la s0, instruction_stubs + li s1, 64 +icache_call: + jalr ra, s0, 0 + addi s0, s0, 512 + addi s1, s1, -1 + bnez s1, icache_call + addi s3, s3, -1 + bnez s3, icache_pass + li t0, 192 + bne s2, t0, fail + + # 64 KiB of dirty lines exceeds both L1 and the compact 32 KiB L2. + # Write/read both directions and repeat with a changed data pattern. + li gp, 10 + li s3, 2 +cache_pass: + la s0, cache_data + li s1, 8192 + li s2, 0 +cache_fill: + xor t0, s2, s3 + sd t0, 0(s0) + addi s0, s0, 8 + addi s2, s2, 1 + addi s1, s1, -1 + bnez s1, cache_fill + fence rw, rw + li s1, 8192 +cache_read_reverse: + addi s0, s0, -8 + addi s2, s2, -1 + ld t0, 0(s0) + xor t1, s2, s3 + bne t0, t1, fail + addi s1, s1, -1 + bnez s1, cache_read_reverse + li s1, 8192 +cache_read_forward: + ld t0, 0(s0) + xor t1, s2, s3 + bne t0, t1, fail + addi s0, s0, 8 + addi s2, s2, 1 + addi s1, s1, -1 + bnez s1, cache_read_forward + addi s3, s3, -1 + bnez s3, cache_pass + + li gp, 6 + # Three identity 1 GiB mappings plus a virtual DDR alias at 0xc0000000. + la t0, root_page + li t1, 0xcf + sd t1, 0(t0) + li t1, 0x100000cf + sd t1, 8(t0) + li t1, 0x200000cf + sd t1, 16(t0) + sd t1, 24(t0) + fence rw, rw + li t1, -1 + csrw pmpaddr0, t1 + li t1, 0xf + csrw pmpcfg0, t1 + li t1, 7 + csrw mcounteren, t1 + srli t0, t0, 12 + li t1, 0x8000000000000000 + or t0, t0, t1 + csrw satp, t0 + sfence.vma + la t0, supervisor + csrw mepc, t0 + li t0, 0x1800 + csrc mstatus, t0 + li t0, 0x800 + csrs mstatus, t0 + mret + +supervisor: + li gp, 7 + la t0, datum + li t1, 0x40000000 + add t0, t0, t1 + ld t2, 0(t0) + li t3, 42 + bne t2, t3, fail + li t2, 43 + sd t2, 0(t0) + la t0, datum + ld t3, 0(t0) + bne t2, t3, fail + csrr t0, cycle + beqz t0, fail + li gp, 8 + li s10, 9 + ecall + j fail + +trap_handler: + csrr t0, mcause + bne t0, s10, fail + addi s11, s11, 1 + li t1, 9 + beq t0, t1, passed + csrr t0, mepc + addi t0, t0, 4 + csrw mepc, t0 + mret + +passed: + li t0, 4 + bne s11, t0, fail + li t0, 0x60000000 + li t1, 0x600d600d + sd t1, 0(t0) +3: j 3b + +fail: + li t0, 0x60000000 + li t1, 0xbad00000 + or t1, t1, gp + sd t1, 0(t0) +4: j 4b + +.balign 512 +instruction_stubs: +.rept 64 + addi s2, s2, 1 + ret + .space 504 +.endr + +.section .data,"aw",@progbits +.balign 16 +datum: + .dword 0, 0 +.balign 4096 +root_page: + .zero 4096 +.balign 4096 +cache_data: + .zero 65536 diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/cpu_smoke.ld b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/cpu_smoke.ld new file mode 100644 index 0000000..b262154 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/cpu_smoke.ld @@ -0,0 +1,10 @@ +OUTPUT_ARCH(riscv) +ENTRY(_start) +SECTIONS { + . = 0x80000000; + .text : { *(.text.init) *(.text*) } + . = ALIGN(16); + .data : { *(.data*) } + .bss : { *(.bss*) *(COMMON) } + /DISCARD/ : { *(.comment) *(.riscv.attributes) } +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/dma_beat64.c b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/dma_beat64.c new file mode 100644 index 0000000..7dc30d1 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/dma_beat64.c @@ -0,0 +1,36 @@ +// Exercise the actual CPU/DMA/cache path after adapting DMA beats to eight bytes. +#include "buckyball.h" +#include +#include + +static uint8_t source[8192] __attribute__((aligned(4096))); +static uint8_t destination[8192] __attribute__((aligned(4096))); + +int main(void) { + const int rows = 9; + const int offsets[] = {0, 1, 3, 7, 4093}; + for (unsigned t = 0; t < sizeof(offsets) / sizeof(offsets[0]); ++t) { + const int in = offsets[t]; + const int out = offsets[(t + 2) % 5]; + const int stride = (t & 1) + 1; + for (int i = 0; i < 8192; ++i) { + source[i] = (uint8_t)(i * 37 + t * 19); + destination[i] = 0xa5; + } + // Four groups exercise splitting and the row skip independently of matrix math. + bb_mem_alloc(0, 1, 4); + bb_mvin((uintptr_t)(source + in), 0, rows, stride); + bb_mvout((uintptr_t)(destination + out), 0, rows, stride); + bb_fence(); + bb_mem_release(0); + for (int i = 0; i < 8192; ++i) { + int relative = i - out; + int row = relative >= 0 ? relative / (stride * 32) : -1; + int column = relative >= 0 ? relative % (stride * 32) : -1; + uint8_t expected = row >= 0 && row < rows && column < 32 + ? source[in + row * stride * 32 + column] : 0xa5; + if (destination[i] != expected) return (int)t + 1; + } + } + return 0; +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/flash_guard_probe.py b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/flash_guard_probe.py new file mode 100644 index 0000000..7931bfb --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/flash_guard_probe.py @@ -0,0 +1,37 @@ +"""隔离进程内替代编程边界，确保测试永不访问串口或启动 Vivado。""" + +import json +from pathlib import Path +import runpy +import sys +import types + + +class ProgrammingBoundary(Exception): + pass + + +class OfflineObserver: + def __init__(self, *args, **kwargs): + raise ProgrammingBoundary("Guard accepted the valid image") + + +fake = types.ModuleType("observe_flash_boot") +fake.Observer = OfflineObserver +sys.modules["observe_flash_boot"] = fake +script, bit, payload, mcs, out, expected = sys.argv[1:] +sys.argv = [script, "--bitstream", bit, "--payload", payload, "--mcs", mcs, + "--part", "mt25ql128-spi-x1_x2_x4", "--port", "OFFLINE_NO_DEVICE", + "--vivado", "OFFLINE_NO_VIVADO", "--out", out] +try: + runpy.run_path(script, run_name="__main__") +except ValueError as error: + if expected != "reject": + raise + print("PASS INVALID_IMAGE_BLOCKED", str(error)) +except ProgrammingBoundary: + if expected != "accept": + raise + print("PASS VALID_IMAGE_REACHED_OFFLINE_BOUNDARY") +else: + raise RuntimeError("Missing verification boundary") diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/fma_differential.cpp b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/fma_differential.cpp new file mode 100644 index 0000000..d3aee18 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/fma_differential.cpp @@ -0,0 +1,122 @@ +#include "VFmaPrecisionCheck.h" +#include "verilated.h" +#include +#include +#include +#include +#include +#include +#include +#include + +struct Request { + int tag, kind, op, rm; + uint64_t a, b, c; + bool random; +}; + +int main(int argc, char **argv) { + Verilated::commandArgs(argc, argv); + VFmaPrecisionCheck dut; + std::mt19937_64 rng(0xf00d531124ULL); + std::deque pending; + std::ofstream vectors("vectors.csv"); + std::array comparisons{}; + std::array, 3> saved{}; + uint64_t cycles = 0, resets = 0, dropped = 0; + bool failed = false; + auto tick = [&](bool valid, Request r, bool reset = false) { + dut.clock = 0; + dut.reset = reset; + dut.valid = valid && !reset; + dut.tag = r.tag; + dut.kind = r.kind; + dut.op = r.op; + dut.rm = r.rm; + dut.a = r.a; dut.b = r.b; dut.c = r.c; + if (reset) { dropped += pending.size(); pending.clear(); } + else if (valid) pending.push_back(r); + dut.eval(); + dut.clock = 1; + dut.eval(); + ++cycles; + if (reset) return; + if (!dut.equal) { + std::cerr << "FAIL cycle=" << cycles << " expected=0x" << std::hex + << dut.expected << " actual=0x" << dut.actual + << " expectedFlags=" << unsigned(dut.expectedFlags) + << " actualFlags=" << unsigned(dut.actualFlags) << std::dec << "\n"; + if (!pending.empty()) { + auto x = pending.front(); + std::cerr << "tag=" << x.tag << " kind=" << x.kind << " op=" << x.op << " rm=" << x.rm + << " a=" << std::hex << x.a << " b=" << x.b << " c=" << x.c << std::dec << "\n"; + } + failed = true; + return; + } + if (dut.outValid) { + if (pending.empty()) { std::cerr << "FAIL unexpected response\n"; failed = true; return; } + auto x = pending.front(); pending.pop_front(); + auto n = ++comparisons[x.tag]; + int cohort = x.random ? 1 : 0; + if (saved[x.tag][cohort] < 256 && n % (x.random ? 41 : 61) == 0) { + vectors << x.tag << ',' << x.kind << ',' << x.op << ',' << x.rm << ',' << std::hex + << x.a << ',' << x.b << ',' << x.c << ',' << dut.expected << ',' + << unsigned(dut.expectedFlags) << std::dec << '\n'; + ++saved[x.tag][cohort]; + } + } + }; + Request empty{}; + for (int i = 0; i < 8; ++i) tick(false, empty, true); + for (int tag = 0; tag < 3 && !failed; ++tag) { + int sig = tag == 0 ? 11 : tag == 1 ? 24 : 53; + int exp = tag == 0 ? 5 : tag == 1 ? 8 : 11; + int bits = sig + exp; + uint64_t sign = uint64_t(1) << (bits - 1); + uint64_t inf = ((uint64_t(1) << exp) - 1) << (sig - 1); + uint64_t one = ((uint64_t(1) << (exp - 1)) - 1) << (sig - 1); + uint64_t minNormal = uint64_t(1) << (sig - 1); + std::vector edge{ + 0, sign, 1, sign | 1, minNormal - 1, sign | (minNormal - 1), minNormal, sign | minNormal, + one, sign | one, one + 1, one - 1, one + (uint64_t(1) << (sig - 1)), + one - (uint64_t(1) << (sig - 1)), inf - 1, sign | (inf - 1), + inf, sign | inf, inf | (uint64_t(1) << (sig - 2)), inf | 1, + sign | inf | (uint64_t(1) << (sig - 2)), sign | inf | 1 + }; + for (int rm = 0; rm < 5 && !failed; ++rm) + for (int kind = 0; kind < 3 && !failed; ++kind) + for (int op = 0; op < (kind == 0 ? 4 : kind == 1 ? 2 : 1) && !failed; ++op) + for (size_t i = 0; i < edge.size() && !failed; ++i) + for (size_t j = 0; j < edge.size() && !failed; ++j) { + tick(true, {tag, kind, op, rm, edge[i], edge[j], edge[(i * 3 + j * 5) % edge.size()], false}); + if ((rng() & 15) == 0) tick(false, empty); + } + // Fusion cancellation: (1+ulp)*(1-ulp)-1 must retain its tiny exact residue. + for (int rm = 0; rm < 5 && !failed; ++rm) { + tick(true, {tag, 0, 0, rm, one + 1, one - 2, sign | one, false}); + tick(true, {tag, 0, 0, rm, inf - 1, one + (uint64_t(1) << (sig - 1)), 0, false}); + } + } + for (int i = 0; i < 200000 && !failed; ++i) { + int tag = rng() % 3, kind = rng() % 3; + int op = rng() % (kind == 0 ? 4 : kind == 1 ? 2 : 1); + tick(true, {tag, kind, op, int(rng() % 5), rng(), rng(), rng(), true}); + if ((rng() & 7) == 0) tick(false, empty); + if (i != 0 && i % 25000 == 0) { + ++resets; + for (int j = 0; j < 8; ++j) tick(false, empty, true); + } + } + for (int i = 0; i < 12 && !failed; ++i) tick(false, empty); + if (failed || !pending.empty()) return 1; + vectors.close(); + dut.final(); + for (int tag = 0; tag < 3; ++tag) { + if (saved[tag][0] != 256 || saved[tag][1] != 256) return 2; + } + std::cout << "PASS FMA_SHARED cycles=" << cycles << " comparisons=" + << comparisons[0] + comparisons[1] + comparisons[2] + << " H=" << comparisons[0] << " S=" << comparisons[1] << " D=" << comparisons[2] + << " resets=" << resets << " reset_discarded=" << dropped << " cpu_vectors=1536\n"; +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/gemmini_runtime.c b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/gemmini_runtime.c new file mode 100644 index 0000000..8d7eb15 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/gemmini_runtime.c @@ -0,0 +1,31 @@ +// Bare-metal test adapter only. Test C bodies, ISA headers and matrix reference +// functions come unchanged from the pinned upstream repository. +#include +#include + +static uint32_t bank_columns[16]; + +void bb_dma_bank_set_cols(uint32_t bank, uint32_t columns) { + if (bank >= 16) { + *(volatile uint64_t *)0x60000000 = 0xbad0ee01; + for (;;) {} + } + bank_columns[bank] = columns; +} + +uint32_t bb_dma_bank_cols(uint32_t bank) { + return bank_columns[bank]; +} + +// Console formatting is irrelevant to the return-value checks. Progress and +// pass/fail events are emitted explicitly by the test runner over MMIO. +int printf(const char *format, ...) { + (void)format; + return 0; +} + +void *memset(void *destination, int value, size_t size) { + unsigned char *bytes = destination; + for (size_t i = 0; i < size; ++i) bytes[i] = (unsigned char)value; + return destination; +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/gemmini_start.S b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/gemmini_start.S new file mode 100644 index 0000000..7bfe8f1 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/gemmini_start.S @@ -0,0 +1,28 @@ +.option norvc +.option norelax +.section .text.init,"ax",@progbits +.globl _start +_start: + li sp, 0x8003fff0 + la t0, trap_failure + csrw mtvec, t0 + csrw mie, zero + csrw medeleg, zero + li t0, 0x1e000 + csrs mstatus, t0 + call main + li t0, 0x60000000 + li t1, 0x600d600d + beqz a0, passed + li t1, 0xbad00000 + or t1, t1, a0 +passed: + sd t1, 0(t0) +1: j 1b +trap_failure: + csrr t2, mcause + li t0, 0x60000000 + li t1, 0xbad0f000 + or t1, t1, t2 + sd t1, 0(t0) +2: j 2b diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/mmio_error.S b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/mmio_error.S new file mode 100644 index 0000000..43d197e --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/mmio_error.S @@ -0,0 +1,49 @@ +.option norvc +.option norelax +.section .text.init,"ax",@progbits +.globl _start +_start: + la t0, trap_handler + csrw mtvec, t0 + csrw medeleg, zero + csrw mie, zero + li s1, 0 + li t0, 0x60030000 + sd zero, 0(t0) + fence iorw, iorw + ld t1, 0(t0) + fence iorw, iorw + # Record synchronous traps without assuming the cache supplies them. + li t0, 0x60000000 + li t1, 0x74000000 + or t1, t1, s1 + sd t1, 0(t0) + li t0, 0x60000000 + li t1, 0x600d600d + sd t1, 0(t0) +1: j 1b + +.balign 4 +trap_handler: + csrr a0, mcause + li a2, 5 + beq a0, a2, check_address + li a2, 7 + bne a0, a2, fail +check_address: + csrr a1, mtval + beqz a1, resume + li a2, 0x60030000 + bne a1, a2, fail +resume: + addi s1, s1, 1 + csrr a0, mepc + addi a0, a0, 4 + csrw mepc, a0 + mret + +fail: + li t0, 0x60000000 + li t1, 0xbad00007 + sd t1, 0(t0) +2: j 2b diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/mock_programming.tcl b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/mock_programming.tcl new file mode 100644 index 0000000..7efa6f7 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/mock_programming.tcl @@ -0,0 +1,71 @@ +# Offline API contract fixture. Never load Vivado or connect to hardware. +lassign $argv script fault bitfile backup +set events {} +proc event {name} {lappend ::events $name} +proc open_hw_manager {} {} +proc connect_hw_server {args} {} +proc get_hw_targets {args} {return target_0} +proc open_hw_target {args} {} +proc get_hw_devices {args} {return xc7a100t_0} +proc current_hw_device {args} {} +proc get_cfgmem_parts {args} {return mt25ql128-spi-x1_x2_x4} +proc create_hw_cfgmem {args} {} +proc create_hw_bitstream {args} {} +proc set_property {args} {} +proc refresh_hw_device {args} {} +proc close_hw_target {} {} +proc disconnect_hw_server {} {} +proc close_hw_manager {} {} +proc program_hw_devices {args} { + event program_device + if {$::fault eq "device_error"} {error "injected programming exception"} + return xc7a100t_0 +} +proc get_property {name device} { + switch -- $name { + PROGRAM.HW_CFGMEM {return cfgmem_0} + PROGRAM.HW_CFGMEM_BITFILE {return bridge.bit} + REGISTER.CONFIG_STATUS.BIT14_DONE_PIN {return [expr {$::fault ne "done_low"}]} + REGISTER.CONFIG_STATUS.BIT04_END_OF_STARTUP_(EOS)_STATUS {return [expr {$::fault ne "eos_low"}]} + REGISTER.CONFIG_STATUS.BIT00_CRC_ERROR {return [expr {$::fault eq "crc_error"}]} + REGISTER.CONFIG_STATUS {return {DONE=1 EOS=1 CRC=0}} + default {error "Unexpected property: $name"} + } +} +proc readback_hw_cfgmem {args} { + event readback + if {$::fault eq "readback_error"} {error "injected readback exception"} + set path [lindex $args [expr {[lsearch -exact $args -file]+1}]] + set f [open $path wb] + set bytes [expr {$::fault eq "short_backup" ? 127 : 16777216}] + seek $f [expr {$bytes-1}] + puts -nonewline $f "\0" + close $f + return "" +} +proc program_hw_cfgmem {args} { + event program_flash + if {$::fault eq "cfgmem_error"} {error "injected Flash verify exception"} + return "Program and verification completed" +} +proc boot_hw_device {args} {event boot; return 1} + +# Replace exit so source can report its result without killing this fixture. +rename exit fixture_exit +proc exit {args} {return} +set part mt25ql128-spi-x1_x2_x4 +switch -- [file tail $script] { + program_arty.tcl {set argv [list $bitfile]} + backup_flash.tcl {set argv [list $part $backup]} + program_flash.tcl {set argv [list $bitfile $part $backup]} + default {error "Unexpected script"} +} +set argc [llength $argv] +set code [catch {source $script} message] +puts "MOCK_EVENTS $events" +if {$code} { + puts "MOCK_FAILURE $message" + fixture_exit 1 +} +puts "MOCK_SUCCESS" +fixture_exit 0 diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/bb-tests/workloads/lib/bbhw/isa/00_fence.c b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/bb-tests/workloads/lib/bbhw/isa/00_fence.c new file mode 100644 index 0000000..78c87a9 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/bb-tests/workloads/lib/bbhw/isa/00_fence.c @@ -0,0 +1,23 @@ +#ifndef _BB_FENCE_H_ +#define _BB_FENCE_H_ + +#include "isa.h" + +#define BB_FENCE_FUNC7 0 + +#if defined(BUCKYBALL_RUSHB) +#define bb_dma_cache_flush() \ + do { \ + } while (0) +#define bb_fence() BUCKYBALL_INSTRUCTION_R_R(0, 0, BB_FENCE_FUNC7) +#else +#define bb_dma_cache_flush() asm volatile("fence.i" ::: "memory") +#define bb_fence() \ + do { \ + BUCKYBALL_INSTRUCTION_R_R(0, 0, BB_FENCE_FUNC7); \ + asm volatile("fence rw, rw" ::: "memory"); \ + bb_dma_cache_flush(); \ + } while (0) +#endif + +#endif // _BB_FENCE_H_ diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/bb-tests/workloads/lib/bbhw/isa/01_barrier.c b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/bb-tests/workloads/lib/bbhw/isa/01_barrier.c new file mode 100644 index 0000000..5bfbff3 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/bb-tests/workloads/lib/bbhw/isa/01_barrier.c @@ -0,0 +1,22 @@ +#ifndef _BB_BARRIER_H_ +#define _BB_BARRIER_H_ + +#include "isa.h" + +#define BB_BARRIER_FUNC7 1 + +/** + * bb_barrier() - hardware multi-core barrier synchronization. + * + * Semantics: + * 1. Waits for this core's own instruction ROB to drain (implicit fence). + * 2. Signals arrive to the tile-level BarrierUnit. + * 3. Stalls until all nCores cores have arrived (hardware all-reduce). + * + * All cores in the same BBTile must call bb_barrier() at the same point. + * Mixing bb_barrier() with bb_fence() within the same barrier epoch is + * undefined behaviour. + */ +#define bb_barrier() BUCKYBALL_INSTRUCTION_R_R(0, 0, BB_BARRIER_FUNC7) + +#endif // _BB_BARRIER_H_ diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/bb-tests/workloads/lib/bbhw/isa/16_mvout.c b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/bb-tests/workloads/lib/bbhw/isa/16_mvout.c new file mode 100644 index 0000000..04dedb1 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/bb-tests/workloads/lib/bbhw/isa/16_mvout.c @@ -0,0 +1,50 @@ +#ifndef _BB_MVOUT_H_ +#define _BB_MVOUT_H_ + +#include "isa.h" +#include + +#define BB_MVOUT_FUNC7 16 + +/* Linux needs private destination pages before a DMA store. */ +#if defined(__linux__) +#define BB_MVOUT_TOUCH(addr, depth, stride, bank) \ + bb_dma_touch_mvout((void *)(addr), (depth), (stride), (bank)) +#else +#define BB_MVOUT_TOUCH(addr, depth, stride, bank) \ + do { \ + } while (0) +#endif + +#if defined(BUCKYBALL_RUSHB) +#define bb_mvout(mem_addr, bank_id, depth, stride) \ + do { \ + uintptr_t _bb_mo_addr = (uintptr_t)(mem_addr); \ + uint32_t _bb_mo_bank = (uint32_t)(bank_id); \ + uint64_t _bb_mo_depth = (uint64_t)(depth); \ + uint64_t _bb_mo_stride = (uint64_t)(stride); \ + BB_MVOUT_TOUCH(_bb_mo_addr, _bb_mo_depth, _bb_mo_stride, _bb_mo_bank); \ + bb_dma_cache_flush(); \ + rushb_mvout( \ + BUCKYBALL_RUSHB_CORE, \ + (uint64_t)(BB_BANK0(_bb_mo_bank) | BB_ITER(_bb_mo_depth)), \ + (uint64_t)(FIELD(_bb_mo_addr, 0, 38) | FIELD(_bb_mo_stride, 39, 57)), \ + (void *)_bb_mo_addr); \ + } while (0) +#else +#define bb_mvout(mem_addr, bank_id, depth, stride) \ + do { \ + uintptr_t _bb_mo_addr = (uintptr_t)(mem_addr); \ + uint32_t _bb_mo_bank = (uint32_t)(bank_id); \ + uint64_t _bb_mo_depth = (uint64_t)(depth); \ + uint64_t _bb_mo_stride = (uint64_t)(stride); \ + BB_MVOUT_TOUCH(_bb_mo_addr, _bb_mo_depth, _bb_mo_stride, _bb_mo_bank); \ + bb_dma_cache_flush(); \ + BUCKYBALL_INSTRUCTION_R_R( \ + (BB_BANK0(_bb_mo_bank) | BB_ITER(_bb_mo_depth)), \ + (FIELD(_bb_mo_addr, 0, 38) | FIELD(_bb_mo_stride, 39, 57)), \ + BB_MVOUT_FUNC7); \ + } while (0) +#endif + +#endif // _BB_MVOUT_H_ diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/bb-tests/workloads/lib/bbhw/isa/32_mset.c b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/bb-tests/workloads/lib/bbhw/isa/32_mset.c new file mode 100644 index 0000000..f3b1bf9 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/bb-tests/workloads/lib/bbhw/isa/32_mset.c @@ -0,0 +1,46 @@ +#ifndef _BB_MSET_H_ +#define _BB_MSET_H_ + +#include "isa.h" +#include + +#define BB_MSET_FUNC7 32 + +#define BB_MSET_CLEAR_BIT 11 + +#define BB_MSET_RS2(row, col, alloc, clear) \ + (FIELD(row, 0, 4) | FIELD(col, 5, 9) | FIELD(alloc, 10, 10) | \ + FIELD(clear, BB_MSET_CLEAR_BIT, BB_MSET_CLEAR_BIT)) + +#if defined(BUCKYBALL_RUSHB) +#define bb_mset(bank_id, alloc, row, col) \ + rushb_mset(BUCKYBALL_RUSHB_CORE, (uint64_t)BB_BANK0(bank_id), \ + (uint64_t)BB_MSET_RS2(row, col, alloc, 0)) +#define bb_mset_clear(bank_id, row, col) \ + rushb_mset(BUCKYBALL_RUSHB_CORE, (uint64_t)BB_BANK0(bank_id), \ + (uint64_t)BB_MSET_RS2(row, col, 1, 1)) +#else +#define bb_mset(bank_id, alloc, row, col) \ + BUCKYBALL_INSTRUCTION_R_R(BB_BANK0(bank_id), \ + BB_MSET_RS2(row, col, alloc, 0), BB_MSET_FUNC7) +#define bb_mset_clear(bank_id, row, col) \ + BUCKYBALL_INSTRUCTION_R_R(BB_BANK0(bank_id), BB_MSET_RS2(row, col, 1, 1), \ + BB_MSET_FUNC7) +#endif + +#define bb_mem_release(bank_id) \ + do { \ + uint32_t _bb_mr_bank = (uint32_t)(bank_id); \ + bb_dma_bank_set_cols(_bb_mr_bank, 1); \ + bb_mset(_bb_mr_bank, 0, 0, 0); \ + } while (0) + +#define bb_mem_alloc(bank_id, row, col) \ + do { \ + uint32_t _bb_ma_bank = (uint32_t)(bank_id); \ + uint32_t _bb_ma_col = (uint32_t)(col); \ + bb_dma_bank_set_cols(_bb_ma_bank, _bb_ma_col); \ + bb_mset(_bb_ma_bank, 1, (row), _bb_ma_col); \ + } while (0) + +#endif // _BB_MSET_H_ diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/bb-tests/workloads/lib/bbhw/isa/33_mvin.c b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/bb-tests/workloads/lib/bbhw/isa/33_mvin.c new file mode 100644 index 0000000..feb39b9 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/bb-tests/workloads/lib/bbhw/isa/33_mvin.c @@ -0,0 +1,27 @@ +#ifndef _BB_MVIN_H_ +#define _BB_MVIN_H_ + +#include "isa.h" + +#define BB_MVIN_FUNC7 33 + +#if defined(BUCKYBALL_RUSHB) +#define bb_mvin(mem_addr, bank_id, depth, stride) \ + do { \ + bb_dma_cache_flush(); \ + rushb_mvin(BUCKYBALL_RUSHB_CORE, \ + (uint64_t)(BB_BANK2(bank_id) | BB_ITER(depth)), \ + (uint64_t)(FIELD(mem_addr, 0, 38) | FIELD(stride, 39, 57)), \ + (const void *)(uintptr_t)(mem_addr)); \ + } while (0) +#else +#define bb_mvin(mem_addr, bank_id, depth, stride) \ + do { \ + bb_dma_cache_flush(); \ + BUCKYBALL_INSTRUCTION_R_R( \ + (BB_BANK2(bank_id) | BB_ITER(depth)), \ + (FIELD(mem_addr, 0, 38) | FIELD(stride, 39, 57)), BB_MVIN_FUNC7); \ + } while (0) +#endif + +#endif // _BB_MVIN_H_ diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/bb-tests/workloads/lib/bbhw/isa/34_mvin_2d.c b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/bb-tests/workloads/lib/bbhw/isa/34_mvin_2d.c new file mode 100644 index 0000000..ae62a65 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/bb-tests/workloads/lib/bbhw/isa/34_mvin_2d.c @@ -0,0 +1,25 @@ +#ifndef _BB_MVIN_2D_H_ +#define _BB_MVIN_2D_H_ + +#include "isa.h" + +#define BB_MVIN_2D_FUNC7 34 + +// rs1: write bank in BANK2 and tile height. +// rs2: [31:0] address, [38:32] physical pixel bytes / 8, +// [48:39] source width, [54:49] destination row base, +// [57:55] tile width - 1, [61:58] valid bytes (0 encodes 16). +#define bb_mvin_2d(mem_addr, bank_id, height, pixel_bytes, source_width, \ + dst_base, tile_width, valid_bytes) \ + do { \ + bb_dma_cache_flush(); \ + BUCKYBALL_INSTRUCTION_R_R( \ + (BB_BANK2(bank_id) | BB_ITER(height)), \ + (FIELD(mem_addr, 0, 31) | FIELD((pixel_bytes) / 8, 32, 38) | \ + FIELD(source_width, 39, 48) | FIELD(dst_base, 49, 54) | \ + FIELD((tile_width) - 1, 55, 57) | \ + FIELD((valid_bytes) == 16 ? 0 : (valid_bytes), 58, 61)), \ + BB_MVIN_2D_FUNC7); \ + } while (0) + +#endif // _BB_MVIN_2D_H_ diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/bb-tests/workloads/lib/bbhw/isa/35_mvin_mmio.c b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/bb-tests/workloads/lib/bbhw/isa/35_mvin_mmio.c new file mode 100644 index 0000000..91cbb0c --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/bb-tests/workloads/lib/bbhw/isa/35_mvin_mmio.c @@ -0,0 +1,46 @@ +#ifndef _BB_MVIN_MMIO_H_ +#define _BB_MVIN_MMIO_H_ + +#include "isa.h" + +#define BB_MVIN_MMIO_FUNC7 35 + +// mvin_mmio: DMA-load metadata from DRAM into MMIO SRAM. +// DMA transfers full 128-bit rows (16 bytes each); `col` controls the per-row +// byte mask written into MMIO (first `col` bytes written, rest zero-masked). +// +// dram_addr : source DRAM virtual address (39-bit) +// mmio_addr : destination MMIO byte address (17-bit) +// row : number of 128-bit rows to load (uses BB_ITER) +// col : valid bytes per row (1..16); rest is mask-zeroed in MMIO +// +// rs1 (dependencies): +// [9:0] = 0 (no main bank dependency) +// [63:30] = row (BB_ITER, also serves as DMA beat count) +// +// rs2 (logic): +// [38:0] = dram_addr +// [55:39] = mmio_addr (17-bit byte address) +// [63:56] = col (write mask: valid bytes per row, 1..16) +// +// funct7 = 0x23 (35 decimal) +#if defined(BUCKYBALL_RUSHB) +#define bb_mvin_mmio(dram_addr, mmio_addr, row, col) \ + do { \ + rushb_mvin_mmio(BUCKYBALL_RUSHB_CORE, (uint64_t)BB_ITER(row), \ + (uint64_t)(FIELD(dram_addr, 0, 38) | \ + FIELD(mmio_addr, 39, 55) | FIELD(col, 56, 63)), \ + (const void *)(uintptr_t)(dram_addr)); \ + } while (0) +#else +#define bb_mvin_mmio(dram_addr, mmio_addr, row, col) \ + do { \ + bb_dma_cache_flush(); \ + BUCKYBALL_INSTRUCTION_R_R(BB_ITER(row), \ + (FIELD(dram_addr, 0, 38) | \ + FIELD(mmio_addr, 39, 55) | FIELD(col, 56, 63)), \ + BB_MVIN_MMIO_FUNC7); \ + } while (0) +#endif + +#endif // _BB_MVIN_MMIO_H_ diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/bb-tests/workloads/lib/bbhw/isa/bb_func7.h b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/bb-tests/workloads/lib/bbhw/isa/bb_func7.h new file mode 100644 index 0000000..5b712fd --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/bb-tests/workloads/lib/bbhw/isa/bb_func7.h @@ -0,0 +1,8 @@ +#ifndef BB_FUNC7_H +#define BB_FUNC7_H + +#include "ballISA.h" + +#define BB_FUNC7(mne) BB_FUNC7_##mne + +#endif diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/bb-tests/workloads/lib/bbhw/isa/isa.c b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/bb-tests/workloads/lib/bbhw/isa/isa.c new file mode 100644 index 0000000..2831564 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/bb-tests/workloads/lib/bbhw/isa/isa.c @@ -0,0 +1 @@ +#include "isa.h" diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/bb-tests/workloads/lib/bbhw/isa/isa.h b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/bb-tests/workloads/lib/bbhw/isa/isa.h new file mode 100644 index 0000000..365653b --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/bb-tests/workloads/lib/bbhw/isa/isa.h @@ -0,0 +1,69 @@ +#ifndef BUCKYBALL_ISA_H +#define BUCKYBALL_ISA_H + +#include +#include + +#if defined(BUCKYBALL_RUSHB) +#include +#if !defined(BUCKYBALL_RUSHB_CORE_ID) +#error "RushB workloads require a Core ID" +#endif +#define BUCKYBALL_RUSHB_CORE (uint32_t)BUCKYBALL_RUSHB_CORE_ID +#endif + +// Data type for matrix elements +typedef int8_t elem_t; +typedef int32_t result_t; + +// Custom instruction opcodes +#define CUSTOM_3 0x7b + +// String macros +#define STR1(x) #x +#ifndef STR +#define STR(x) STR1(x) +#endif + +// Field encoding macro with start and end bit +#define FIELD(val, start_bit, end_bit) \ + (((val) & ((2UL << ((end_bit) - (start_bit))) - 1)) << (start_bit)) + +// rs1 bank field helpers (10-bit each) +#define BB_BANK0(id) FIELD(id, 0, 9) +#define BB_BANK1(id) FIELD(id, 10, 19) +#define BB_BANK2(id) FIELD(id, 20, 29) + +// rs1 iter field (34-bit, bits 30-63) +#define BB_ITER(n) FIELD(n, 30, 63) + +// funct7 encoding: [6:4]=enable, [3:0]=opcode +// enable: 000=none, 001=1rd, 010=1wr, 011=1rd+1wr, 100=2rd+1wr +// 101/110/111 = none (extended opcode space) + +// Generic RISC-V custom instruction macro (funct3 always 0x3 = CUSTOM3_RS1_RS2) +#if defined(BUCKYBALL_RUSHB) +#define BUCKYBALL_INSTRUCTION_R_R(rs1_val, rs2_val, func7) \ + do { \ + rushb_custom(BUCKYBALL_RUSHB_CORE, (uint64_t)(rs1_val), \ + (uint64_t)(rs2_val), (uint32_t)(func7)); \ + } while (0) +#else +#define BUCKYBALL_INSTRUCTION_R_R(rs1_val, rs2_val, func7) \ + asm volatile(".insn r " STR(CUSTOM_3) ", 3, %c2, x0, %0, %1" \ + : \ + : "r"(rs1_val), "r"(rs2_val), "i"(func7) \ + : "memory") +#endif + +// Base (mem/frontend) instruction definitions only. +// Ball-specific ISA macros live under examples/balls//workloads/isa/. +#include "00_fence.c" +#include "01_barrier.c" +#include "16_mvout.c" +#include "32_mset.c" +#include "33_mvin.c" +#include "34_mvin_2d.c" +#include "35_mvin_mmio.c" + +#endif // BUCKYBALL_ISA_H diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/bb-tests/workloads/lib/bbhw/mem/mem.c b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/bb-tests/workloads/lib/bbhw/mem/mem.c new file mode 100644 index 0000000..c573193 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/bb-tests/workloads/lib/bbhw/mem/mem.c @@ -0,0 +1,51 @@ +#include + +#include +#include + +static uint8_t bank_cols[VIRTUAL_BANK_NUM]; +static uint8_t bank_cols_init; + +static void ensure_bank_cols(void) { + uint32_t i; + + if (bank_cols_init) + return; + for (i = 0; i < VIRTUAL_BANK_NUM; i++) + bank_cols[i] = 1; + bank_cols_init = 1; +} + +void bb_dma_bank_set_cols(uint32_t bank_id, uint32_t cols) { + ensure_bank_cols(); + if (bank_id >= VIRTUAL_BANK_NUM) { + fprintf(stderr, "bb_dma_bank_set_cols: bank_id %u out of range\n", bank_id); + exit(1); + } + bank_cols[bank_id] = cols < 1 ? 1 : (cols > 255 ? 255 : (uint8_t)cols); +} + +uint32_t bb_dma_bank_cols(uint32_t bank_id) { + ensure_bank_cols(); + if (bank_id >= VIRTUAL_BANK_NUM) { + fprintf(stderr, "bb_dma_bank_cols: bank_id %u out of range\n", bank_id); + exit(1); + } + return bank_cols[bank_id]; +} + +void bb_dma_touch(void *p, size_t n) { + volatile uint8_t *b = (volatile uint8_t *)p; + size_t i; + + if (n == 0) + return; + for (i = 0; i < n; i += 4096) + b[i] = b[i]; + b[n - 1] = b[n - 1]; +} + +void bb_dma_touch_mvout(void *p, uint64_t depth, uint64_t stride, + uint32_t bank_id) { + bb_dma_touch(p, bb_dma_span_bytes(depth, stride, bb_dma_bank_cols(bank_id))); +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/bb-tests/workloads/lib/bbhw/mem/mem.h b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/bb-tests/workloads/lib/bbhw/mem/mem.h new file mode 100644 index 0000000..8914f6e --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/bb-tests/workloads/lib/bbhw/mem/mem.h @@ -0,0 +1,43 @@ +#ifndef _MEM_H_ +#define _MEM_H_ + +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Bytes covered by mvin/mvout for a bank with `groups` (= alloc col, min 1). */ +static inline size_t bb_dma_span_bytes(uint64_t depth, uint64_t stride, + uint32_t groups) { + size_t row_bytes = (size_t)BANK_WIDTH / 8; + uint32_t g = groups < 1 ? 1 : groups; + + if (depth == 0) + return 0; + return ((size_t)(depth - 1) * (size_t)stride + 1) * row_bytes * (size_t)g; +} + +void bb_dma_bank_set_cols(uint32_t bank_id, uint32_t cols); +uint32_t bb_dma_bank_cols(uint32_t bank_id); + +/* + * Force private writable pages for a DMA buffer under Linux. + * Untouched BSS is CoW-mapped to the shared zero page; accelerator stores + * translate to that PPN and do not install a private page, so CPU reads stay 0. + * Prefer clear_* or memset when the buffer should also be zeroed. + */ +void bb_dma_touch(void *p, size_t n); + +/* Touch host span for mvout using cols recorded by bb_mem_alloc. */ +void bb_dma_touch_mvout(void *p, uint64_t depth, uint64_t stride, + uint32_t bank_id); + +#ifdef __cplusplus +} +#endif + +#endif // _MEM_H_ diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/bb-tests/workloads/lib/buckyball.c b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/bb-tests/workloads/lib/buckyball.c new file mode 100644 index 0000000..bd0e10a --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/bb-tests/workloads/lib/buckyball.c @@ -0,0 +1,325 @@ +#include "buckyball.h" +#include +#include +#include +#include +#include + +#define DIM (BANK_WIDTH / sizeof(elem_t)) + +/* Read cycle counter (rdcycle) helper. Works on RV64 with a single rdcycle. + On RV32 we read low/high and detect rollover to produce a 64-bit value. */ +unsigned long long read_rdcycle(void) { +#if defined(BUCKYBALL_RUSHB) + return rushb_cycles(BUCKYBALL_RUSHB_CORE); +#elif defined(__riscv_xlen) && __riscv_xlen == 64 + unsigned long long cycles; + asm volatile("rdcycle %0" : "=r"(cycles)); + return cycles; +#else + unsigned int lo1, hi, lo2; + /* Loop until two consecutive low reads are equal to avoid rollover window */ + asm volatile("1: rdcycle %0\n" + " rdcycleh %1\n" + " rdcycle %2\n" + " bne %0, %2, 1b\n" + : "=&r"(lo1), "=&r"(hi), "=&r"(lo2)); + return ((unsigned long long)hi << 32) | lo1; +#endif +} + +void init_u8_random_matrix(elem_t *matrix, int rows, int cols, int seed) { + srand(seed); + for (int i = 0; i < rows * cols; i++) { + matrix[i] = rand() % 128; + } +} + +// Initialize matrix with incrementing values for debugging +void init_u8_incremental_matrix(elem_t *matrix, int rows, int cols, + int start_value) { + for (int i = 0; i < rows * cols; i++) { + matrix[i] = (start_value + i) & 0xFF; // Keep values in 0-255 range + } +} + +void init_u32_random_matrix(result_t *matrix, int rows, int cols, int seed) { + srand(seed); + for (int i = 0; i < rows * cols; i++) { + matrix[i] = rand() % 256; + } +} +int compare_u8_matrices(elem_t *a, elem_t *b, int rows, int cols) { + for (int i = 0; i < rows * cols; i++) { + if (a[i] != b[i]) { + printf("Mismatch at index %d: expected %d, got %d\n", i, b[i], a[i]); + // print_matrix("Expected", b, 1, cols); + // print_matrix("Actual", a, 1, cols); + return 0; + } + } + return 1; +} +int compare_u32_matrices(result_t *a, result_t *b, int rows, int cols) { + for (int i = 0; i <= rows * cols - 1; i++) { + if (a[i] != b[i]) { + printf("Mismatch at index %d: expected %d, got %d\n", i, b[i], a[i]); + return 0; + } + } + return 1; +} + +void init_i8_random_matrix(elem_t *matrix, int rows, int cols, int seed) { + srand(seed); + for (int i = 0; i < rows * cols; i++) { + /* produce values in range -128 .. 127 */ + matrix[i] = (elem_t)((rand() % 256) - 128); + } +} +void init_i32_random_matrix(result_t *matrix, int rows, int cols, int seed) { + srand(seed); + for (int i = 0; i < rows * cols; i++) { + /* produce values in a reasonable 16-bit signed range -32768 .. 32767 */ + matrix[i] = (result_t)((rand() % 65536) - 32768); + } +} +int compare_i8_matrices(elem_t *a, elem_t *b, int rows, int cols) { + for (int i = 0; i < rows * cols; i++) { + if (a[i] != b[i]) { + printf("Mismatch at index %d: expected %d, got %d\n", i, b[i], a[i]); + return 0; + } + } + return 1; +} +int compare_i32_matrices(result_t *a, result_t *b, int rows, int cols) { + for (int i = 0; i < rows * cols; i++) { + if (a[i] != b[i]) { + printf("Mismatch at index %d: expected %d, got %d\n", i, b[i], a[i]); + return 0; + } + } + return 1; +} + +void print_u32_matrix(const char *name, result_t *matrix, int rows, int cols) { + printf("Matrix %s:\n", name); + for (int i = 0; i < rows; i++) { + for (int j = 0; j < cols; j++) { + printf("%4d ", matrix[i * cols + j]); + } + printf("\n"); + } + printf("\n"); +} +void print_u8_matrix(const char *name, elem_t *matrix, int rows, int cols) { + printf("Matrix %s:\n", name); + for (int i = 0; i < rows; i++) { + for (int j = 0; j < cols; j++) { + printf("%4d ", matrix[i * cols + j]); + } + printf("\n"); + } + printf("\n"); +} +// Signed print variants +void print_i32_matrix(const char *name, result_t *matrix, int rows, int cols) { + printf("Matrix %s:\n", name); + for (int i = 0; i < rows; i++) { + for (int j = 0; j < cols; j++) { + printf("%4d ", matrix[i * cols + j]); + } + printf("\n"); + } + printf("\n"); +} + +void print_i8_matrix(const char *name, elem_t *matrix, int rows, int cols) { + printf("Matrix %s:\n", name); + for (int i = 0; i < rows; i++) { + for (int j = 0; j < cols; j++) { + /* cast to int to avoid printing as char */ + printf("%4d ", (int)matrix[i * cols + j]); + } + printf("\n"); + } + printf("\n"); +} +void clear_u32_matrix(result_t *matrix, int rows, int cols) { + memset(matrix, 0, rows * cols * sizeof(result_t)); +} +void clear_u8_matrix(elem_t *matrix, int rows, int cols) { + memset(matrix, 0, rows * cols * sizeof(elem_t)); +} +void clear_i32_matrix(result_t *matrix, int rows, int cols) { + memset(matrix, 0, rows * cols * sizeof(result_t)); +} +void clear_i8_matrix(elem_t *matrix, int rows, int cols) { + memset(matrix, 0, rows * cols * sizeof(elem_t)); +} + +void init_ones_matrix(elem_t *matrix, int rows, int cols) { + for (int i = 0; i < rows * cols; i++) { + matrix[i] = 1; + } +} + +void init_identity_matrix(elem_t *matrix, int size) { + clear_u8_matrix(matrix, size, size); + for (int i = 0; i < size; i++) { + matrix[i * size + i] = 1; + } +} + +void init_row_vector(elem_t *matrix, int cols, elem_t value) { + clear_u8_matrix(matrix, DIM, DIM); + for (int j = 0; j < cols; j++) { + matrix[j] = value; + } +} + +void init_col_vector(elem_t *matrix, int rows, elem_t value) { + clear_u8_matrix(matrix, DIM, DIM); + for (int i = 0; i < rows; i++) { + matrix[i * DIM] = value; + } +} + +void init_random_matrix(elem_t *matrix, int rows, int cols, int seed) { + srand(seed); + for (int i = 0; i < rows; i++) { + for (int j = 0; j < cols; j++) { + // Random number in range 0-4 + matrix[i * cols + j] = (rand() % 5); + } + } +} + +void init_matrix_random_matrix(elem_t *matrix, int rows, int cols, int seed) { + srand(seed); + for (int i = 0; i < rows; i++) { + for (int j = 0; j < cols; j++) { + matrix[i * cols + j] = (rand() % 16); + } + } +} + +void init_sequence_matrix(elem_t *matrix, int rows, int cols) { + for (int i = 0; i < rows; i++) { + for (int j = 0; j < cols; j++) { + matrix[i * cols + j] = i + j; + } + } +} +// Initialize column-aligned random matrix and original matrix +void init_col_aligned_random_matrix(elem_t *aligned_matrix, elem_t *matrix, + int align, int rows, int cols, int seed) { + srand(seed); + int aligned_cols = (cols + align - 1) / align * align; + for (int i = 0; i < rows; i++) { + for (int j = 0; j < aligned_cols; j++) { + aligned_matrix[i * aligned_cols + j] = (j < cols) ? (rand() % 128) : 0; + } + } + for (int i = 0; i < rows; i++) { + for (int j = 0; j < cols; j++) { + matrix[i * cols + j] = aligned_matrix[i * aligned_cols + j]; + } + } +} +// Transpose matrix +void transpose_u8_matrix(elem_t *src, elem_t *dst, int rows, int cols) { + for (int i = 0; i < rows; i++) { + for (int j = 0; j < cols; j++) { + dst[j * rows + i] = src[i * cols + j]; + } + } +} +void transpose_u32_matrix(result_t *src, result_t *dst, int rows, int cols) { + for (int i = 0; i < rows; i++) { + for (int j = 0; j < cols; j++) { + dst[j * rows + i] = src[i * cols + j]; + } + } +} + +result_t gemmini_in_shift(result_t v, int shift) { + if (shift <= 0) + return v; + if (shift >= 32) + return 0; + + uint32_t s = (uint32_t)shift; + uint32_t bits = (uint32_t)v; + uint32_t point_five = (bits >> (s - 1)) & 1; + uint32_t zeros = (s <= 1) ? 0 : ((bits & ((1u << (s - 1)) - 1)) != 0); + uint32_t ones_digit = (bits >> s) & 1; + uint32_t r = point_five & (zeros | ones_digit); + return (v >> s) + (result_t)r; +} + +// CPU matrix multiplication (used to generate expected results) +void cpu_matmul(elem_t *a, elem_t *b, result_t *c, int rows, int cols, + int inner) { + clear_u32_matrix(c, rows, cols); + for (int i = 0; i < rows; i++) { + for (int j = 0; j < cols; j++) { + for (int k = 0; k < inner; k++) { + c[i * cols + j] += a[i * inner + k] * b[k * cols + j]; + } + } + } +} + +// CPU ReLU activation function +void cpu_relu(elem_t *a, elem_t *matrix, int rows, int cols) { + for (int i = 0; i < rows * cols; i++) { + matrix[i] = (a[i] > 0) ? a[i] : 0; + } +} + +// CPU transfer from elem_t to result_t +void cpu_transfer(elem_t *src, elem_t *dst, int rows, int cols) { + for (int i = 0; i < rows * cols; i++) { + dst[i] = (result_t)src[i]; + } +} +unsigned long long read_cycle(void) { +#if defined(BUCKYBALL_RUSHB) + return rushb_cycles(BUCKYBALL_RUSHB_CORE); +#else + unsigned long long c; + asm volatile("csrr %0, cycle" : "=r"(c)); + return c; +#endif +} + +// MMIO stubs are for baremetal/BBSim only. +// Linux user-mode tests (`*-linux` under `spike pk`) must use libc/syscall exit +// path. +#if !defined(__linux__) +// MMIO address map (BBSimHarness, WithDefaultMMIOPort base=0x6000_0000): +// 0x6000_0000 : simulation exit — write triggers sim_exit() +// 0x6002_0000 : UART0 TX — write low byte → putchar in C++ +#define MMIO_SIM_EXIT ((volatile uint32_t *)0x60000000UL) +#define MMIO_UART_TX ((volatile uint32_t *)0x60020000UL) + +// _write: route stdout/stderr through MMIO UART so printf works in simulation. +// nosys.specs provides a weak _write stub; we override it here. +int _write(int fd, const char *buf, int len) { + (void)fd; + for (int i = 0; i < len; i++) { + *MMIO_UART_TX = (uint32_t)(unsigned char)buf[i]; + } + return len; +} + +// _exit: write exit code to MMIO sim-exit register; C++ mmio_tick() detects +// this and calls sim_exit(). +void __attribute__((noreturn)) _exit(int code) { + *MMIO_SIM_EXIT = (uint32_t)code; + while (1) { + } // wait for C++ to process the MMIO write and call sim_exit() +} +#endif diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/bb-tests/workloads/lib/buckyball.h b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/bb-tests/workloads/lib/buckyball.h new file mode 100644 index 0000000..f0aa3e6 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/bb-tests/workloads/lib/buckyball.h @@ -0,0 +1,90 @@ +#ifndef BUCKYBALL_H +#define BUCKYBALL_H + +#include + +// String macros (from xcustom.h) +// #define STR1(x) #x +// #ifndef STR +// #define STR(x) STR1(x) +// #endif + +#define CAT_(A, B) A##B +#define CAT(A, B) CAT_(A, B) + +// Data type for matrix elements +typedef int8_t elem_t; +typedef int32_t result_t; + +#if defined(BUCKYBALL_RUSHB) +#define MULTICORE_INIT(hart_id) + +static inline void multicore(int target_hart_id) { (void)target_hart_id; } +#else +#define MULTICORE_INIT(hart_id) \ + __attribute__((constructor)) static void _multicore_init() { \ + multicore(hart_id); \ + } + +static inline void multicore(int target_hart_id) { + int hart_id; + asm volatile("csrr %0, mhartid" : "=r"(hart_id)); + + if (hart_id != target_hart_id) { + while (1) { + asm volatile("wfi"); // Wait for interrupt + } + } + // If hart_id == target_hart_id, continue execution +} +#endif + +// Utility functions + +/* Read CPU cycle counter (64-bit). Implemented in buckyball.c for global use */ +unsigned long long read_rdcycle(void); + +void print_u32_matrix(const char *name, result_t *matrix, int rows, int cols); +void print_u8_matrix(const char *name, elem_t *matrix, int rows, int cols); +void print_i32_matrix(const char *name, result_t *matrix, int rows, int cols); +void print_i8_matrix(const char *name, elem_t *matrix, int rows, int cols); + +void init_u8_random_matrix(elem_t *matrix, int rows, int cols, int seed); +void init_u8_incremental_matrix(elem_t *matrix, int rows, int cols, + int start_value); +void init_u32_random_matrix(result_t *matrix, int rows, int cols, int seed); +void init_i8_random_matrix(elem_t *matrix, int rows, int cols, int seed); +void init_i32_random_matrix(result_t *matrix, int rows, int cols, int seed); + +int compare_u8_matrices(elem_t *a, elem_t *b, int rows, int cols); +int compare_u32_matrices(result_t *a, result_t *b, int rows, int cols); +int compare_i8_matrices(elem_t *a, elem_t *b, int rows, int cols); +int compare_i32_matrices(result_t *a, result_t *b, int rows, int cols); +int compare_u32_matrices_with_tolerance(result_t *a, result_t *b, int rows, + int cols, double tolerance); +void clear_u32_matrix(result_t *matrix, int rows, int cols); +void clear_u8_matrix(elem_t *matrix, int rows, int cols); +void clear_i32_matrix(result_t *matrix, int rows, int cols); +void clear_i8_matrix(elem_t *matrix, int rows, int cols); + +void init_ones_matrix(elem_t *matrix, int rows, int cols); +void init_identity_matrix(elem_t *matrix, int size); +void init_row_vector(elem_t *matrix, int cols, elem_t value); +void init_col_vector(elem_t *matrix, int rows, elem_t value); +void init_random_matrix(elem_t *matrix, int rows, int cols, int seed); +void init_matrix_random_matrix(elem_t *matrix, int rows, int cols, int seed); +void init_sequence_matrix(elem_t *matrix, int rows, int cols); +void init_col_aligned_random_matrix(elem_t *aligned_matrix, elem_t *matrix, + int align, int rows, int cols, int seed); +/* Matrix operation functions */ +void transpose_u8_matrix(elem_t *src, elem_t *dst, int rows, int cols); +void transpose_u32_matrix(result_t *src, result_t *dst, int rows, int cols); +void cpu_matmul(elem_t *a, elem_t *b, result_t *c, int rows, int cols, + int inner); +result_t gemmini_in_shift(result_t v, int shift); +void cpu_relu(elem_t *a, elem_t *matrix, int rows, int cols); +void cpu_transfer(elem_t *src, elem_t *dst, int rows, int cols); + +unsigned long long read_cycle(void); + +#endif diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/ctests/CMakeLists.txt b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/ctests/CMakeLists.txt new file mode 100644 index 0000000..a144971 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/ctests/CMakeLists.txt @@ -0,0 +1,15 @@ +add_buckyball_ctests( + gemmini_os_cisc_atranspose_test.c + gemmini_os_cisc_basic_test.c + gemmini_os_cisc_btranspose_test.c + gemmini_os_cisc_shift_test.c + gemmini_os_risc_abtranspose_test.c + gemmini_os_risc_atranspose_test.c + gemmini_os_risc_basic_test.c + gemmini_os_risc_btranspose_test.c + gemmini_os_risc_shift_test.c + gemmini_ws_cisc_conv_test.c + gemmini_ws_risc_basic_test.c + gemmini_ws_risc_btranspose_test.c + gemmini_ws_risc_shift_test.c +) diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_cisc_atranspose_test.c b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_cisc_atranspose_test.c new file mode 100644 index 0000000..424b541 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_cisc_atranspose_test.c @@ -0,0 +1,47 @@ +#include "buckyball.h" +#include +#include +#include +#include + +#define DIM 16 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_at[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + + printf("=== Gemmini OS CISC a_transpose Test ===\n"); + + for (int row = 0; row < DIM; ++row) + for (int col = 0; col < DIM; ++col) { + mat_a[row * DIM + col] = (3 * row + 5 * col) % 11 - 5; + mat_b[row * DIM + col] = (7 * row + 2 * col) % 13 - 6; + } + transpose_u8_matrix(mat_a, mat_at, DIM, DIM); + cpu_matmul(mat_at, mat_b, expected, DIM, DIM, DIM); + + bb_gemmini_config(0, 0, 1, 0, 0); + bb_gemmini_loop_ws_config_bounds(1, 1, 1); + bb_gemmini_loop_ws_config_addr_a((uintptr_t)mat_a); + bb_gemmini_loop_ws_config_addr_b((uintptr_t)mat_b); + bb_gemmini_loop_ws_config_addr_d(0); + bb_gemmini_loop_ws_config_addr_c((uintptr_t)mat_c); + bb_gemmini_loop_ws_config_strides_ab(DIM, DIM); + bb_gemmini_loop_ws_config_strides_dc(0, DIM * 4); + bb_gemmini_loop_ws(0, 1, 2, 1); + bb_fence(); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Gemmini OS CISC a_transpose Test PASSED\n"); + return 0; + } + printf("Gemmini OS CISC a_transpose Test FAILED\n"); + return 1; +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_cisc_basic_test.c b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_cisc_basic_test.c new file mode 100644 index 0000000..0eee2d3 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_cisc_basic_test.c @@ -0,0 +1,45 @@ +#include "buckyball.h" +#include +#include +#include +#include + +#define DIM 16 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + + printf("=== Gemmini OS CISC Basic Test ===\n"); + + for (int row = 0; row < DIM; ++row) + for (int col = 0; col < DIM; ++col) { + mat_a[row * DIM + col] = (3 * row + 5 * col) % 11 - 5; + mat_b[row * DIM + col] = (7 * row + 2 * col) % 13 - 6; + } + cpu_matmul(mat_a, mat_b, expected, DIM, DIM, DIM); + + bb_gemmini_config(0, 0, 0, 0, 0); + bb_gemmini_loop_ws_config_bounds(1, 1, 1); + bb_gemmini_loop_ws_config_addr_a((uintptr_t)mat_a); + bb_gemmini_loop_ws_config_addr_b((uintptr_t)mat_b); + bb_gemmini_loop_ws_config_addr_d(0); + bb_gemmini_loop_ws_config_addr_c((uintptr_t)mat_c); + bb_gemmini_loop_ws_config_strides_ab(DIM, DIM); + bb_gemmini_loop_ws_config_strides_dc(0, DIM * 4); + bb_gemmini_loop_ws(0, 1, 2, 1); + bb_fence(); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Gemmini OS CISC Basic Test PASSED\n"); + return 0; + } + printf("Gemmini OS CISC Basic Test FAILED\n"); + return 1; +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_cisc_btranspose_test.c b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_cisc_btranspose_test.c new file mode 100644 index 0000000..9e29309 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_cisc_btranspose_test.c @@ -0,0 +1,47 @@ +#include "buckyball.h" +#include +#include +#include +#include + +#define DIM 16 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_bt[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + + printf("=== Gemmini OS CISC b_transpose Test ===\n"); + + for (int row = 0; row < DIM; ++row) + for (int col = 0; col < DIM; ++col) { + mat_a[row * DIM + col] = (3 * row + 5 * col) % 11 - 5; + mat_b[row * DIM + col] = (7 * row + 2 * col) % 13 - 6; + } + transpose_u8_matrix(mat_b, mat_bt, DIM, DIM); + cpu_matmul(mat_a, mat_bt, expected, DIM, DIM, DIM); + + bb_gemmini_config(0, 0, 0, 1, 0); + bb_gemmini_loop_ws_config_bounds(1, 1, 1); + bb_gemmini_loop_ws_config_addr_a((uintptr_t)mat_a); + bb_gemmini_loop_ws_config_addr_b((uintptr_t)mat_b); + bb_gemmini_loop_ws_config_addr_d(0); + bb_gemmini_loop_ws_config_addr_c((uintptr_t)mat_c); + bb_gemmini_loop_ws_config_strides_ab(DIM, DIM); + bb_gemmini_loop_ws_config_strides_dc(0, DIM * 4); + bb_gemmini_loop_ws(0, 1, 2, 1); + bb_fence(); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Gemmini OS CISC b_transpose Test PASSED\n"); + return 0; + } + printf("Gemmini OS CISC b_transpose Test FAILED\n"); + return 1; +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_cisc_shift_test.c b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_cisc_shift_test.c new file mode 100644 index 0000000..098d48f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_cisc_shift_test.c @@ -0,0 +1,48 @@ +#include "buckyball.h" +#include +#include +#include +#include + +#define DIM 16 +#define SHIFT 4 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + + printf("=== Gemmini OS CISC in_shift Test ===\n"); + + for (int row = 0; row < DIM; ++row) + for (int col = 0; col < DIM; ++col) { + mat_a[row * DIM + col] = (3 * row + 5 * col) % 11 - 5; + mat_b[row * DIM + col] = (7 * row + 2 * col) % 13 - 6; + } + cpu_matmul(mat_a, mat_b, expected, DIM, DIM, DIM); + for (int i = 0; i < DIM * DIM; i++) + expected[i] = gemmini_in_shift(expected[i], SHIFT); + + bb_gemmini_config(0, 0, 0, 0, SHIFT); + bb_gemmini_loop_ws_config_bounds(1, 1, 1); + bb_gemmini_loop_ws_config_addr_a((uintptr_t)mat_a); + bb_gemmini_loop_ws_config_addr_b((uintptr_t)mat_b); + bb_gemmini_loop_ws_config_addr_d(0); + bb_gemmini_loop_ws_config_addr_c((uintptr_t)mat_c); + bb_gemmini_loop_ws_config_strides_ab(DIM, DIM); + bb_gemmini_loop_ws_config_strides_dc(0, DIM * 4); + bb_gemmini_loop_ws(0, 1, 2, 1); + bb_fence(); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Gemmini OS CISC in_shift Test PASSED\n"); + return 0; + } + printf("Gemmini OS CISC in_shift Test FAILED\n"); + return 1; +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_risc_abtranspose_test.c b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_risc_abtranspose_test.c new file mode 100644 index 0000000..73ce600 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_risc_abtranspose_test.c @@ -0,0 +1,53 @@ +#include "buckyball.h" +#include +#include +#include +#include + +#define DIM 16 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_at[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_bt[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + + printf("=== Gemmini OS RISC ab_transpose Test ===\n"); + + for (int row = 0; row < DIM; ++row) + for (int col = 0; col < DIM; ++col) { + mat_a[row * DIM + col] = (3 * row + 5 * col) % 11 - 5; + mat_b[row * DIM + col] = (7 * row + 2 * col) % 13 - 6; + } + transpose_u8_matrix(mat_a, mat_at, DIM, DIM); + transpose_u8_matrix(mat_b, mat_bt, DIM, DIM); + cpu_matmul(mat_at, mat_bt, expected, DIM, DIM, DIM); + + uint32_t bank_a = 0, bank_b = 1, bank_c = 2; + bb_mem_alloc(bank_a, 1, 1); + bb_mem_alloc(bank_b, 1, 1); + bb_mem_alloc(bank_c, 1, 4); + bb_mvin((uintptr_t)mat_a, bank_a, DIM, 1); + bb_mvin((uintptr_t)mat_b, bank_b, DIM, 1); + bb_gemmini_config(0, 0, 1, 1, 0); + bb_gemmini_preload(bank_a, bank_c, DIM, 0, 0); + bb_gemmini_compute_preloaded(bank_a, bank_b, bank_c, DIM, 0, 0, 0); + bb_mvout((uintptr_t)mat_c, bank_c, DIM, 1); + bb_fence(); + bb_mem_release(bank_a); + bb_mem_release(bank_b); + bb_mem_release(bank_c); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Gemmini OS RISC ab_transpose Test PASSED\n"); + return 0; + } + printf("Gemmini OS RISC ab_transpose Test FAILED\n"); + return 1; +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_risc_atranspose_test.c b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_risc_atranspose_test.c new file mode 100644 index 0000000..e7d2fa4 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_risc_atranspose_test.c @@ -0,0 +1,51 @@ +#include "buckyball.h" +#include +#include +#include +#include + +#define DIM 16 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_at[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + + printf("=== Gemmini OS RISC a_transpose Test ===\n"); + + for (int row = 0; row < DIM; ++row) + for (int col = 0; col < DIM; ++col) { + mat_a[row * DIM + col] = (3 * row + 5 * col) % 11 - 5; + mat_b[row * DIM + col] = (7 * row + 2 * col) % 13 - 6; + } + transpose_u8_matrix(mat_a, mat_at, DIM, DIM); + cpu_matmul(mat_at, mat_b, expected, DIM, DIM, DIM); + + uint32_t bank_a = 0, bank_b = 1, bank_c = 2; + bb_mem_alloc(bank_a, 1, 1); + bb_mem_alloc(bank_b, 1, 1); + bb_mem_alloc(bank_c, 1, 4); + bb_mvin((uintptr_t)mat_a, bank_a, DIM, 1); + bb_mvin((uintptr_t)mat_b, bank_b, DIM, 1); + bb_gemmini_config(0, 0, 1, 0, 0); + bb_gemmini_preload(bank_a, bank_c, DIM, 0, 0); + bb_gemmini_compute_preloaded(bank_a, bank_b, bank_c, DIM, 0, 0, 0); + bb_mvout((uintptr_t)mat_c, bank_c, DIM, 1); + bb_fence(); + bb_mem_release(bank_a); + bb_mem_release(bank_b); + bb_mem_release(bank_c); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Gemmini OS RISC a_transpose Test PASSED\n"); + return 0; + } + printf("Gemmini OS RISC a_transpose Test FAILED\n"); + return 1; +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_risc_basic_test.c b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_risc_basic_test.c new file mode 100644 index 0000000..7effed4 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_risc_basic_test.c @@ -0,0 +1,71 @@ +#include "buckyball.h" +#include +#include +#include +#include + +#define DIM 16 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static elem_t zeros[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + printf("=== Gemmini OS RISC Basic Test ===\n"); + + for (int row = 0; row < DIM; ++row) + for (int col = 0; col < DIM; ++col) { + mat_a[row * DIM + col] = (3 * row + 5 * col) % 11 - 5; + mat_b[row * DIM + col] = (7 * row + 2 * col) % 13 - 6; + } + cpu_matmul(mat_a, mat_b, expected, DIM, DIM, DIM); + + uint32_t bank_a = 0, bank_b = 1, bank_c = 2, bank_d_zeros = 3; + bb_mem_alloc(bank_a, 1, 1); + bb_mem_alloc(bank_b, 1, 1); + bb_mem_alloc(bank_c, 1, 4); + bb_mem_alloc(bank_d_zeros, 1, 1); + bb_mvin((uintptr_t)mat_a, bank_a, DIM, 1); + bb_mvin((uintptr_t)mat_b, bank_b, DIM, 1); + bb_mvin((uintptr_t)zeros, bank_d_zeros, DIM, 1); + bb_gemmini_config(0, 0, 0, 0, 0); + /* Preload D from zeros bank so C = A*B + D = A*B (not A*B + A) */ + bb_gemmini_preload(bank_d_zeros, bank_c, DIM, 0, 0); + bb_gemmini_compute_preloaded(bank_a, bank_b, bank_c, DIM, 0, 0, 0); + bb_mvout((uintptr_t)mat_c, bank_c, DIM, 1); + bb_fence(); + bb_mem_release(bank_a); + bb_mem_release(bank_b); + bb_mem_release(bank_c); + bb_mem_release(bank_d_zeros); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Gemmini OS RISC Basic Test PASSED\n"); + return 0; + } + + printf("got mat_c: "); + for (int i = 0; i < DIM; i++) { + printf("%d ", mat_c[i]); + } + printf("\n"); + // for (int i = 0; i < DIM; i++) { + // for (int j = 0; j < DIM; j++) { + // printf("%d ", mat_c[i * DIM + j]); + // } + // printf("\n"); + // } + + printf("exp row0: "); + for (int i = 0; i < DIM; i++) { + printf("%d ", expected[i]); + } + printf("\n"); + printf("Gemmini OS RISC Basic Test FAILED\n"); + return 1; +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_risc_btranspose_test.c b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_risc_btranspose_test.c new file mode 100644 index 0000000..ac88ccb --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_risc_btranspose_test.c @@ -0,0 +1,51 @@ +#include "buckyball.h" +#include +#include +#include +#include + +#define DIM 16 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_bt[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + + printf("=== Gemmini OS RISC b_transpose Test ===\n"); + + for (int row = 0; row < DIM; ++row) + for (int col = 0; col < DIM; ++col) { + mat_a[row * DIM + col] = (3 * row + 5 * col) % 11 - 5; + mat_b[row * DIM + col] = (7 * row + 2 * col) % 13 - 6; + } + transpose_u8_matrix(mat_b, mat_bt, DIM, DIM); + cpu_matmul(mat_a, mat_bt, expected, DIM, DIM, DIM); + + uint32_t bank_a = 0, bank_b = 1, bank_c = 2; + bb_mem_alloc(bank_a, 1, 1); + bb_mem_alloc(bank_b, 1, 1); + bb_mem_alloc(bank_c, 1, 4); + bb_mvin((uintptr_t)mat_a, bank_a, DIM, 1); + bb_mvin((uintptr_t)mat_b, bank_b, DIM, 1); + bb_gemmini_config(0, 0, 0, 1, 0); + bb_gemmini_preload(bank_a, bank_c, DIM, 0, 0); + bb_gemmini_compute_preloaded(bank_a, bank_b, bank_c, DIM, 0, 0, 0); + bb_mvout((uintptr_t)mat_c, bank_c, DIM, 1); + bb_fence(); + bb_mem_release(bank_a); + bb_mem_release(bank_b); + bb_mem_release(bank_c); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Gemmini OS RISC b_transpose Test PASSED\n"); + return 0; + } + printf("Gemmini OS RISC b_transpose Test FAILED\n"); + return 1; +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_risc_shift_test.c b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_risc_shift_test.c new file mode 100644 index 0000000..d6ad4c9 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_risc_shift_test.c @@ -0,0 +1,52 @@ +#include "buckyball.h" +#include +#include +#include +#include + +#define DIM 16 +#define SHIFT 4 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + + printf("=== Gemmini OS RISC in_shift Test ===\n"); + + for (int row = 0; row < DIM; ++row) + for (int col = 0; col < DIM; ++col) { + mat_a[row * DIM + col] = (3 * row + 5 * col) % 11 - 5; + mat_b[row * DIM + col] = (7 * row + 2 * col) % 13 - 6; + } + cpu_matmul(mat_a, mat_b, expected, DIM, DIM, DIM); + for (int i = 0; i < DIM * DIM; i++) + expected[i] = gemmini_in_shift(expected[i], SHIFT); + + uint32_t bank_a = 0, bank_b = 1, bank_c = 2; + bb_mem_alloc(bank_a, 1, 1); + bb_mem_alloc(bank_b, 1, 1); + bb_mem_alloc(bank_c, 1, 4); + bb_mvin((uintptr_t)mat_a, bank_a, DIM, 1); + bb_mvin((uintptr_t)mat_b, bank_b, DIM, 1); + bb_gemmini_config(0, 0, 0, 0, SHIFT); + bb_gemmini_preload(bank_a, bank_c, DIM, 0, 0); + bb_gemmini_compute_preloaded(bank_a, bank_b, bank_c, DIM, 0, 0, 0); + bb_mvout((uintptr_t)mat_c, bank_c, DIM, 1); + bb_fence(); + bb_mem_release(bank_a); + bb_mem_release(bank_b); + bb_mem_release(bank_c); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Gemmini OS RISC in_shift Test PASSED\n"); + return 0; + } + printf("Gemmini OS RISC in_shift Test FAILED\n"); + return 1; +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_ws_cisc_conv_test.c b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_ws_cisc_conv_test.c new file mode 100644 index 0000000..d990afd --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_ws_cisc_conv_test.c @@ -0,0 +1,74 @@ +#include "buckyball.h" +#include +#include +#include +#include + +// Pointwise conv: batch=1, in_dim=1, in_channels=DIM, out_channels=DIM, +// kernel=1 Degenerates to a single DIM x DIM matmul (input[1x1xIC] * +// weight[1x1xICxOC]) +#define DIM 16 +#define BATCH 1 +#define IN_DIM 1 +#define OUT_DIM 1 +#define IN_CH DIM +#define OUT_CH DIM +#define KERNEL_DIM 1 + +// input layout: [batch, in_dim, in_dim, in_ch] = [1, 1, 1, 16] = 16 bytes +// weight layout: [krow, kcol, in_ch, out_ch] = [1, 1, 16, 16] = 256 bytes +// output layout: [batch, out_dim, out_dim, out_ch] = [1, 1, 1, 16] x 4 bytes = +// 64 bytes +static elem_t input[BATCH * IN_DIM * IN_DIM * IN_CH] + __attribute__((aligned(64))); +static elem_t weight[KERNEL_DIM * KERNEL_DIM * IN_CH * OUT_CH] + __attribute__((aligned(64))); +static result_t output[BATCH * OUT_DIM * OUT_DIM * OUT_CH] + __attribute__((aligned(64))); +static result_t expected[BATCH * OUT_DIM * OUT_DIM * OUT_CH] + __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + + printf("=== Gemmini WS CISC Loop Conv Test ===\n"); + + for (int k = 0; k < IN_CH; ++k) { + input[k] = k % 7 - 3; + for (int out = 0; out < OUT_CH; ++out) + weight[k * OUT_CH + out] = (2 * k + 3 * out) % 5 - 2; + } + + // CPU reference: output[0..OUT_CH] = sum_k(input[k] * weight[k][j]) + // cpu_matmul(A[M×K], B[K×N], C[M×N]) — here A=input(1×IN_CH), + // B=weight(IN_CH×OUT_CH) + cpu_matmul(input, weight, expected, 1, OUT_CH, IN_CH); + + // Strides: + // input_stride = in_ch * elemSize = 16 * 1 = 16 (bytes per spatial step) + // weight_stride = in_ch * out_ch * elemSize = 16 * 16 * 1 = 256 (bytes per + // kernel step) output_stride = out_ch * accBytes = 16 * 4 = 64 + bb_gemmini_config(1, 0, 0, 0, 0); + bb_gemmini_loop_conv_ws_config_1(BATCH, IN_DIM, IN_CH); + bb_gemmini_loop_conv_ws_config_2(OUT_CH, OUT_DIM, 1, 0); + bb_gemmini_loop_conv_ws_config_3(KERNEL_DIM, 0, 0, 0); + bb_gemmini_loop_conv_ws_config_4(0); // no bias + bb_gemmini_loop_conv_ws_config_5((uintptr_t)input); + bb_gemmini_loop_conv_ws_config_6((uintptr_t)weight); + bb_gemmini_loop_conv_ws_config_7((uintptr_t)output); + bb_gemmini_loop_conv_ws_config_8( + IN_CH, IN_CH * OUT_CH); // input_stride, weight_stride + bb_gemmini_loop_conv_ws_config_9(OUT_CH * 4); // output_stride (accBytes=4) + bb_gemmini_loop_conv_ws( + 0, 1, 2, 1); // bank_input=0, bank_weight=1, bank_output=2, no_bias=1 + bb_fence(); + + if (compare_u32_matrices(output, expected, 1, OUT_CH)) { + printf("Gemmini WS CISC Loop Conv Test PASSED\n"); + return 0; + } + printf("Gemmini WS CISC Loop Conv Test FAILED\n"); + return 1; +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_ws_risc_basic_test.c b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_ws_risc_basic_test.c new file mode 100644 index 0000000..6c8f7df --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_ws_risc_basic_test.c @@ -0,0 +1,53 @@ +#include "buckyball.h" +#include +#include +#include +#include + +#define DIM 16 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_d[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + printf("=== Gemmini WS RISC Basic Test ===\n"); + + for (int row = 0; row < DIM; ++row) + for (int col = 0; col < DIM; ++col) { + mat_a[row * DIM + col] = (3 * row + 5 * col) % 11 - 5; + mat_b[row * DIM + col] = (7 * row + 2 * col) % 13 - 6; + } + clear_u8_matrix(mat_d, DIM, DIM); + cpu_matmul(mat_a, mat_b, expected, DIM, DIM, DIM); + + // WS: bank_w=weights(B), bank_a=activations(A), bank_d=bias(0), bank_c=output + uint32_t bank_w = 0, bank_a = 1, bank_d = 2, bank_c = 3; + bb_mem_alloc(bank_w, 1, 1); + bb_mem_alloc(bank_a, 1, 1); + bb_mem_alloc(bank_d, 1, 1); + bb_mem_alloc(bank_c, 1, 4); + bb_mvin((uintptr_t)mat_b, bank_w, DIM, 1); + bb_mvin((uintptr_t)mat_a, bank_a, DIM, 1); + bb_mvin((uintptr_t)mat_d, bank_d, DIM, 1); + bb_gemmini_config(1, 0, 0, 0, 0); + bb_gemmini_preload(bank_w, bank_c, DIM, 0, 0); + bb_gemmini_compute_preloaded(bank_a, bank_d, bank_c, DIM, 0, 0, 0); + bb_mvout((uintptr_t)mat_c, bank_c, DIM, 1); + bb_fence(); + bb_mem_release(bank_w); + bb_mem_release(bank_a); + bb_mem_release(bank_d); + bb_mem_release(bank_c); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Gemmini WS RISC Basic Test PASSED\n"); + return 0; + } + return 1; +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_ws_risc_btranspose_test.c b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_ws_risc_btranspose_test.c new file mode 100644 index 0000000..e4c3149 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_ws_risc_btranspose_test.c @@ -0,0 +1,56 @@ +#include "buckyball.h" +#include +#include +#include +#include + +#define DIM 16 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_bt[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_d[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + + printf("=== Gemmini WS RISC b_transpose Test ===\n"); + + for (int row = 0; row < DIM; ++row) + for (int col = 0; col < DIM; ++col) { + mat_a[row * DIM + col] = (3 * row + 5 * col) % 11 - 5; + mat_b[row * DIM + col] = (7 * row + 2 * col) % 13 - 6; + } + transpose_u8_matrix(mat_b, mat_bt, DIM, DIM); + clear_u8_matrix(mat_d, DIM, DIM); + cpu_matmul(mat_a, mat_bt, expected, DIM, DIM, DIM); + + uint32_t bank_w = 0, bank_a = 1, bank_d = 2, bank_c = 3; + bb_mem_alloc(bank_w, 1, 1); + bb_mem_alloc(bank_a, 1, 1); + bb_mem_alloc(bank_d, 1, 1); + bb_mem_alloc(bank_c, 1, 4); + bb_mvin((uintptr_t)mat_b, bank_w, DIM, 1); + bb_mvin((uintptr_t)mat_a, bank_a, DIM, 1); + bb_mvin((uintptr_t)mat_d, bank_d, DIM, 1); + bb_gemmini_config(1, 0, 0, 1, 0); + bb_gemmini_preload(bank_w, bank_c, DIM, 0, 0); + bb_gemmini_compute_preloaded(bank_a, bank_d, bank_c, DIM, 0, 0, 0); + bb_mvout((uintptr_t)mat_c, bank_c, DIM, 1); + bb_fence(); + bb_mem_release(bank_w); + bb_mem_release(bank_a); + bb_mem_release(bank_d); + bb_mem_release(bank_c); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Gemmini WS RISC b_transpose Test PASSED\n"); + return 0; + } + printf("Gemmini WS RISC b_transpose Test FAILED\n"); + return 1; +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_ws_risc_shift_test.c b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_ws_risc_shift_test.c new file mode 100644 index 0000000..905824e --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_ws_risc_shift_test.c @@ -0,0 +1,57 @@ +#include "buckyball.h" +#include +#include +#include +#include + +#define DIM 16 +#define SHIFT 4 + +static elem_t mat_a[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_b[DIM * DIM] __attribute__((aligned(64))); +static elem_t mat_d[DIM * DIM] __attribute__((aligned(64))); +static result_t mat_c[DIM * DIM] __attribute__((aligned(64))); +static result_t expected[DIM * DIM] __attribute__((aligned(64))); + +int main() { +#ifdef MULTICORE + multicore(MULTICORE); +#endif + + printf("=== Gemmini WS RISC in_shift Test ===\n"); + + for (int row = 0; row < DIM; ++row) + for (int col = 0; col < DIM; ++col) { + mat_a[row * DIM + col] = (3 * row + 5 * col) % 11 - 5; + mat_b[row * DIM + col] = (7 * row + 2 * col) % 13 - 6; + } + clear_u8_matrix(mat_d, DIM, DIM); + cpu_matmul(mat_a, mat_b, expected, DIM, DIM, DIM); + for (int i = 0; i < DIM * DIM; i++) + expected[i] = gemmini_in_shift(expected[i], SHIFT); + + uint32_t bank_w = 0, bank_a = 1, bank_d = 2, bank_c = 3; + bb_mem_alloc(bank_w, 1, 1); + bb_mem_alloc(bank_a, 1, 1); + bb_mem_alloc(bank_d, 1, 1); + bb_mem_alloc(bank_c, 1, 4); + bb_mvin((uintptr_t)mat_b, bank_w, DIM, 1); + bb_mvin((uintptr_t)mat_a, bank_a, DIM, 1); + bb_mvin((uintptr_t)mat_d, bank_d, DIM, 1); + bb_gemmini_config(1, 0, 0, 0, SHIFT); + bb_gemmini_preload(bank_w, bank_c, DIM, 0, 0); + bb_gemmini_compute_preloaded(bank_a, bank_d, bank_c, DIM, 0, 0, 0); + bb_mvout((uintptr_t)mat_c, bank_c, DIM, 1); + bb_fence(); + bb_mem_release(bank_w); + bb_mem_release(bank_a); + bb_mem_release(bank_d); + bb_mem_release(bank_c); + + if (compare_u32_matrices(mat_c, expected, DIM, DIM)) { + printf("Gemmini WS RISC in_shift Test PASSED\n"); + return 0; + } + printf("Gemmini WS RISC in_shift Test FAILED\n"); + return 1; +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/isa/gemmini.h b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/isa/gemmini.h new file mode 100644 index 0000000..2994d8f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/isa/gemmini.h @@ -0,0 +1,12 @@ +#ifndef _BB_GEMMINI_ISA_H_ +#define _BB_GEMMINI_ISA_H_ + +#include "gemmini_compute_accumulated.h" +#include "gemmini_compute_preloaded.h" +#include "gemmini_config.h" +#include "gemmini_flush.h" +#include "gemmini_loop_conv_ws.h" +#include "gemmini_loop_ws.h" +#include "gemmini_preload.h" + +#endif // _BB_GEMMINI_ISA_H_ diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/isa/gemmini_compute_accumulated.h b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/isa/gemmini_compute_accumulated.h new file mode 100644 index 0000000..d3fda03 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/isa/gemmini_compute_accumulated.h @@ -0,0 +1,23 @@ +#ifndef _BB_GEMMINI_COMPUTE_ACCUMULATED_H_ +#define _BB_GEMMINI_COMPUTE_ACCUMULATED_H_ + +#include +#include + +#define BB_GEMMINI_COMPUTE_ACCUMULATED_RS2 3ULL + +// Compute matmul reusing previously accumulated results +// op1_bank_id: bank for A matrix +// op2_bank_id: bank for B/D matrix +// wr_bank_id: bank for C output +// iter: number of rows +#define bb_gemmini_compute_accumulated(op1_bank_id, op2_bank_id, wr_bank_id, \ + iter, op1_base, op2_base, wr_base) \ + BUCKYBALL_INSTRUCTION_R_R( \ + (BB_BANK0(op1_bank_id) | BB_BANK1(op2_bank_id) | BB_BANK2(wr_bank_id) | \ + BB_ITER(iter)), \ + BB_GEMMINI_COMPUTE_ACCUMULATED_RS2 | ((uint64_t)(op1_base) << 6) | \ + ((uint64_t)(op2_base) << 16) | ((uint64_t)(wr_base) << 26), \ + BB_FUNC7(GEMMINI_COMPUTE_ACCUMULATED)) + +#endif // _BB_GEMMINI_COMPUTE_ACCUMULATED_H_ diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/isa/gemmini_compute_preloaded.h b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/isa/gemmini_compute_preloaded.h new file mode 100644 index 0000000..c39d3b1 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/isa/gemmini_compute_preloaded.h @@ -0,0 +1,23 @@ +#ifndef _BB_GEMMINI_COMPUTE_PRELOADED_H_ +#define _BB_GEMMINI_COMPUTE_PRELOADED_H_ + +#include +#include + +#define BB_GEMMINI_COMPUTE_PRELOADED_RS2 2ULL + +// Compute matmul using preloaded data: C = A * B + D(preloaded) +// op1_bank_id: bank for A matrix +// op2_bank_id: bank for B matrix (OS) or D matrix (WS) +// wr_bank_id: bank for C output +// iter: number of rows +#define bb_gemmini_compute_preloaded(op1_bank_id, op2_bank_id, wr_bank_id, \ + iter, op1_base, op2_base, wr_base) \ + BUCKYBALL_INSTRUCTION_R_R( \ + (BB_BANK0(op1_bank_id) | BB_BANK1(op2_bank_id) | BB_BANK2(wr_bank_id) | \ + BB_ITER(iter)), \ + BB_GEMMINI_COMPUTE_PRELOADED_RS2 | ((uint64_t)(op1_base) << 6) | \ + ((uint64_t)(op2_base) << 16) | ((uint64_t)(wr_base) << 26), \ + BB_FUNC7(GEMMINI_COMPUTE_PRELOADED)) + +#endif // _BB_GEMMINI_COMPUTE_PRELOADED_H_ diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/isa/gemmini_config.h b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/isa/gemmini_config.h new file mode 100644 index 0000000..fc50c07 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/isa/gemmini_config.h @@ -0,0 +1,23 @@ +#ifndef _BB_GEMMINI_CONFIG_H_ +#define _BB_GEMMINI_CONFIG_H_ + +#include +#include + +// Configure Gemmini matrix array +// All config parameters go in rs2 (special), starting from bit 4. +// rs2[3:0] is the sub-command field and remains 0 for this instruction. +// dataflow: 0=OS, 1=WS +// activation: 0=none, 1=relu +// a_transpose, b_transpose: transpose flags +// in_shift: right-shift amount for output +#define bb_gemmini_config(dataflow, activation, a_transpose, b_transpose, \ + in_shift) \ + BUCKYBALL_INSTRUCTION_R_R(0, \ + (FIELD(dataflow, 4, 4) | FIELD(activation, 5, 6) | \ + FIELD(a_transpose, 7, 7) | \ + FIELD(b_transpose, 8, 8) | \ + FIELD(in_shift, 9, 40)), \ + BB_FUNC7(GEMMINI_CONFIG)) + +#endif // _BB_GEMMINI_CONFIG_H_ diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/isa/gemmini_flush.h b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/isa/gemmini_flush.h new file mode 100644 index 0000000..2c55b62 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/isa/gemmini_flush.h @@ -0,0 +1,13 @@ +#ifndef _BB_GEMMINI_FLUSH_H_ +#define _BB_GEMMINI_FLUSH_H_ + +#include +#include + +#define BB_GEMMINI_FLUSH_RS2 4ULL + +// Flush the matrix array state +#define bb_gemmini_flush() \ + BUCKYBALL_INSTRUCTION_R_R(0, BB_GEMMINI_FLUSH_RS2, BB_FUNC7(GEMMINI_FLUSH)) + +#endif // _BB_GEMMINI_FLUSH_H_ diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/isa/gemmini_loop_conv_ws.h b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/isa/gemmini_loop_conv_ws.h new file mode 100644 index 0000000..5f04089 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/isa/gemmini_loop_conv_ws.h @@ -0,0 +1,62 @@ +#ifndef _BB_GEMMINI_LOOP_CONV_WS_H +#define _BB_GEMMINI_LOOP_CONV_WS_H + +#include +#include + +#define bb_gemmini_loop_conv_ws_config_1(batch_size, in_dim, in_channels) \ + BUCKYBALL_INSTRUCTION_R_R(0, \ + (FIELD(batch_size, 0, 15) | \ + FIELD(in_dim, 16, 31) | \ + FIELD(in_channels, 32, 47)), \ + BB_FUNC7(GEMMINI_LOOP_CONV_WS_CONFIG_1)) + +#define bb_gemmini_loop_conv_ws_config_2(out_channels, out_dim, stride, \ + padding) \ + BUCKYBALL_INSTRUCTION_R_R(0, \ + (FIELD(out_channels, 0, 15) | \ + FIELD(out_dim, 16, 31) | FIELD(stride, 32, 39) | \ + FIELD(padding, 40, 47)), \ + BB_FUNC7(GEMMINI_LOOP_CONV_WS_CONFIG_2)) + +#define bb_gemmini_loop_conv_ws_config_3(kernel_dim, pool_size, pool_stride, \ + pool_padding) \ + BUCKYBALL_INSTRUCTION_R_R( \ + 0, \ + (FIELD(kernel_dim, 0, 7) | FIELD(pool_size, 8, 15) | \ + FIELD(pool_stride, 16, 23) | FIELD(pool_padding, 24, 31)), \ + BB_FUNC7(GEMMINI_LOOP_CONV_WS_CONFIG_3)) + +#define bb_gemmini_loop_conv_ws_config_4(addr_bias) \ + BUCKYBALL_INSTRUCTION_R_R(0, FIELD(addr_bias, 0, 38), \ + BB_FUNC7(GEMMINI_LOOP_CONV_WS_CONFIG_4)) + +#define bb_gemmini_loop_conv_ws_config_5(addr_input) \ + BUCKYBALL_INSTRUCTION_R_R(0, FIELD(addr_input, 0, 38), \ + BB_FUNC7(GEMMINI_LOOP_CONV_WS_CONFIG_5)) + +#define bb_gemmini_loop_conv_ws_config_6(addr_weight) \ + BUCKYBALL_INSTRUCTION_R_R(0, FIELD(addr_weight, 0, 38), \ + BB_FUNC7(GEMMINI_LOOP_CONV_WS_CONFIG_6)) + +#define bb_gemmini_loop_conv_ws_config_7(addr_output) \ + BUCKYBALL_INSTRUCTION_R_R(0, FIELD(addr_output, 0, 38), \ + BB_FUNC7(GEMMINI_LOOP_CONV_WS_CONFIG_7)) + +#define bb_gemmini_loop_conv_ws_config_8(input_stride, weight_stride) \ + BUCKYBALL_INSTRUCTION_R_R( \ + 0, (FIELD(input_stride, 0, 31) | FIELD(weight_stride, 32, 63)), \ + BB_FUNC7(GEMMINI_LOOP_CONV_WS_CONFIG_8)) + +#define bb_gemmini_loop_conv_ws_config_9(output_stride) \ + BUCKYBALL_INSTRUCTION_R_R(0, FIELD(output_stride, 0, 31), \ + BB_FUNC7(GEMMINI_LOOP_CONV_WS_CONFIG_9)) + +#define bb_gemmini_loop_conv_ws(bank_input, bank_weight, bank_output, no_bias) \ + BUCKYBALL_INSTRUCTION_R_R( \ + 0, \ + (FIELD(bank_input, 0, 9) | FIELD(bank_weight, 10, 19) | \ + FIELD(bank_output, 20, 29) | FIELD(no_bias, 30, 30)), \ + BB_FUNC7(GEMMINI_LOOP_CONV_WS)) + +#endif diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/isa/gemmini_loop_ws.h b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/isa/gemmini_loop_ws.h new file mode 100644 index 0000000..769c1f6 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/isa/gemmini_loop_ws.h @@ -0,0 +1,44 @@ +#ifndef _BB_GEMMINI_LOOP_WS_H +#define _BB_GEMMINI_LOOP_WS_H + +#include +#include + +#define bb_gemmini_loop_ws_config_bounds(max_i, max_j, max_k) \ + BUCKYBALL_INSTRUCTION_R_R( \ + 0, (FIELD(max_k, 0, 15) | FIELD(max_j, 16, 31) | FIELD(max_i, 32, 47)), \ + BB_FUNC7(GEMMINI_LOOP_WS_CONFIG_BOUNDS)) + +#define bb_gemmini_loop_ws_config_addr_a(addr) \ + BUCKYBALL_INSTRUCTION_R_R(0, FIELD(addr, 0, 38), \ + BB_FUNC7(GEMMINI_LOOP_WS_CONFIG_ADDR_A)) + +#define bb_gemmini_loop_ws_config_addr_b(addr) \ + BUCKYBALL_INSTRUCTION_R_R(0, FIELD(addr, 0, 38), \ + BB_FUNC7(GEMMINI_LOOP_WS_CONFIG_ADDR_B)) + +#define bb_gemmini_loop_ws_config_addr_d(addr) \ + BUCKYBALL_INSTRUCTION_R_R(0, FIELD(addr, 0, 38), \ + BB_FUNC7(GEMMINI_LOOP_WS_CONFIG_ADDR_D)) + +#define bb_gemmini_loop_ws_config_addr_c(addr) \ + BUCKYBALL_INSTRUCTION_R_R(0, FIELD(addr, 0, 38), \ + BB_FUNC7(GEMMINI_LOOP_WS_CONFIG_ADDR_C)) + +#define bb_gemmini_loop_ws_config_strides_ab(stride_a, stride_b) \ + BUCKYBALL_INSTRUCTION_R_R( \ + 0, (FIELD(stride_a, 0, 31) | FIELD(stride_b, 32, 63)), \ + BB_FUNC7(GEMMINI_LOOP_WS_CONFIG_STRIDES_AB)) + +#define bb_gemmini_loop_ws_config_strides_dc(stride_d, stride_c) \ + BUCKYBALL_INSTRUCTION_R_R( \ + 0, (FIELD(stride_d, 0, 31) | FIELD(stride_c, 32, 63)), \ + BB_FUNC7(GEMMINI_LOOP_WS_CONFIG_STRIDES_DC)) + +#define bb_gemmini_loop_ws(bank_a, bank_b, bank_c, low_d) \ + BUCKYBALL_INSTRUCTION_R_R(0, \ + (FIELD(bank_a, 0, 9) | FIELD(bank_b, 10, 19) | \ + FIELD(bank_c, 20, 29) | FIELD(low_d, 30, 30)), \ + BB_FUNC7(GEMMINI_LOOP_WS)) + +#endif diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/isa/gemmini_preload.h b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/isa/gemmini_preload.h new file mode 100644 index 0000000..f1f578b --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/reference/examples/balls/gemmini/workloads/isa/gemmini_preload.h @@ -0,0 +1,20 @@ +#ifndef _BB_GEMMINI_PRELOAD_H_ +#define _BB_GEMMINI_PRELOAD_H_ + +#include +#include + +#define BB_GEMMINI_PRELOAD_RS2 1ULL + +// Preload D/B matrix into matrix array +// op1_bank_id: source bank for D (OS) or B (WS) +// wr_bank_id: destination bank for C output +// iter: number of rows to preload +#define bb_gemmini_preload(op1_bank_id, wr_bank_id, iter, op1_base, wr_base) \ + BUCKYBALL_INSTRUCTION_R_R( \ + (BB_BANK0(op1_bank_id) | BB_BANK2(wr_bank_id) | BB_ITER(iter)), \ + BB_GEMMINI_PRELOAD_RS2 | ((uint64_t)(op1_base) << 6) | \ + ((uint64_t)(wr_base) << 26), \ + BB_FUNC7(GEMMINI_PRELOAD)) + +#endif // _BB_GEMMINI_PRELOAD_H_ diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/serial_loop_stress.c b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/serial_loop_stress.c new file mode 100644 index 0000000..380f87b --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/serial_loop_stress.c @@ -0,0 +1,39 @@ +// Four 8x8 column tiles: 11 loop rows exceed the 8-row SubROB. +// Forty alternating OS/WS loops cross the 255-token mesh-tag wrap point. +// Compare every INT32 result against the pinned CPU matrix reference. +#include "buckyball.h" +#include +#include +#include + +#define M 8 +#define N 32 +#define K 8 +static elem_t a[M * K] __attribute__((aligned(64))); +static elem_t b[K * N] __attribute__((aligned(64))); +static result_t c[M * N] __attribute__((aligned(64))); +static result_t expected[M * N] __attribute__((aligned(64))); + +int main(void) { + for (int r = 0; r < M; ++r) + for (int k = 0; k < K; ++k) a[r * K + k] = (r * 3 + k * 5) % 9 - 4; + for (int k = 0; k < K; ++k) + for (int n = 0; n < N; ++n) b[k * N + n] = (k * 7 + n * 2) % 11 - 5; + cpu_matmul(a, b, expected, M, N, K); + for (int run = 0; run < 40; ++run) { + int mode = run & 1; + clear_u32_matrix(c, M, N); + bb_gemmini_config(mode, 0, 0, 0, 0); + bb_gemmini_loop_ws_config_bounds(1, 4, 1); + bb_gemmini_loop_ws_config_addr_a((uintptr_t)a); + bb_gemmini_loop_ws_config_addr_b((uintptr_t)b); + bb_gemmini_loop_ws_config_addr_d(0); + bb_gemmini_loop_ws_config_addr_c((uintptr_t)c); + bb_gemmini_loop_ws_config_strides_ab(K, N); + bb_gemmini_loop_ws_config_strides_dc(0, N * 4); + bb_gemmini_loop_ws(0, 1, 2, 1); + bb_fence(); + if (!compare_u32_matrices(c, expected, M, N)) return run + 1; + } + return 0; +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/spi_flash_model.sv b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/spi_flash_model.sv new file mode 100644 index 0000000..477b37f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/spi_flash_model.sv @@ -0,0 +1,42 @@ +// Simulation-only standard 03h read / 9fh JEDEC model, no Flash writes. +module spi_flash_model #(parameter BYTES=1024, parameter IMAGE="flash.hex") ( + input wire sck, cs_n, mosi, output reg miso=1 +); + reg [7:0] contents [0:BYTES-1]; + reg [7:0] received; + integer bit_count=0, state=0, address_bytes=0, address=0, id_index=0; + reg [7:0] command; + reg [7:0] response; + initial begin + $readmemh(IMAGE,contents); + if($test$plusargs("bad_header")) contents[0]=contents[0]^1; + if($test$plusargs("bad_payload")) contents[BYTES-1]=contents[BYTES-1]^1; + end + always @(posedge sck or posedge cs_n) begin + if(cs_n) begin state=0;bit_count=0;address=0;address_bytes=0;id_index=0;received=0;command=0;end + else begin + received={received[6:0],mosi}; + if(bit_count==7) begin + if(state==0) begin + command=received; + if(received==8'h03) state=1; + else if(received==8'h9f) begin state=2;response=8'h01;end + else state=3; + end else if(state==1) begin + address=(address<<8)|received;address_bytes=address_bytes+1; + if(address_bytes==3) begin state=2;response=contents[0];end + end else if(state==2) begin + if(command==8'h9f) begin + id_index=id_index+1; + response=id_index==1 ? 8'h20 : id_index==2 ? 8'h18 : 8'hff; + end else begin + address=address+1; + response=(address-32'h400000)>(addr[2:0]*8) & 255)!==expected) + $fatal(1,"SCU read addr=%h data=%h resp=%h",addr,rdata,rresp); + @(negedge clk); + end + rready=1;@(negedge clk);rready=0; + end + endtask + initial begin + repeat(4) @(negedge clk);reset=0; + @(negedge clk);rx_data=8'h71;rx_valid=1;@(negedge clk);rx_valid=0; + read_byte(31'h60020005,1,0); + if(!interrupt) $fatal(1,"RX IRQ missing"); + read_byte(31'h60020004,8'h71,0); + if(interrupt) $fatal(1,"RX not popped exactly once"); + read_byte(31'h60020005,0,0); + // A whole pasted command must survive a long interval between SBI polls. + for(integer j=0;j<200;j=j+1) begin + @(negedge clk);rx_data=j;rx_valid=1;@(negedge clk);rx_valid=0; + end + if(dut.overflow) $fatal(1,"FIFO overflow on a 200-byte paste"); + for(integer j=0;j<200;j=j+1) read_byte(31'h60020004,j[7:0],0); + if(interrupt) $fatal(1,"FIFO not drained after paste"); + read_byte(31'h60030000,0,2); + @(negedge clk);awaddr=31'h60020000;awid=3;awvalid=1; + @(negedge clk);awvalid=0;wdata=64'h53;wstrb=1;wvalid=1; + repeat(10) begin @(negedge clk);if(wready || bvalid) $fatal(1,"SCU lost TX backpressure");end + tx_ready=1;@(negedge clk);wvalid=0; + repeat(4) @(negedge clk); + if(!bvalid || bid!==3 || bresp!==0 || tx_count!=1) $fatal(1,"SCU TX response/count"); + bready=1;@(negedge clk);bready=0; + awaddr=31'h60000000;awsize=2;awvalid=1;@(negedge clk);awvalid=0; + wdata=64'h12345678;wstrb=15;wvalid=1;@(negedge clk);wvalid=0; + if(!exited || exit_code!==32'h12345678) $fatal(1,"SCU EXIT decode"); + $display("PASS SCU OpenSBI byte addresses, AXI lanes, RX pop/IRQ, TX backpressure, EXIT");$finish; + end + initial begin #100000;$fatal(1,"SCU watchdog");end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/tb_fpu_rf.sv b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/tb_fpu_rf.sv new file mode 100644 index 0000000..482c44c --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/tb_fpu_rf.sv @@ -0,0 +1,98 @@ +`timescale 1ns/1ps +module tb; + reg clk = 0; + always #5 clk = ~clk; + reg [4:0] ra0 = 0, ra1 = 0, ra2 = 0, wa0 = 0, wa1 = 0; + reg re0 = 0, re1 = 0, re2 = 0, we0 = 0, we1 = 0; + reg [64:0] wd0 = 0, wd1 = 0; + wire [64:0] old0, old1, old2, new0, new1, new2; + reg [64:0] expected [0:31]; + reg [31:0] valid = 0; + integer seed = 99127; + integer comparisons = 0, dual_writes = 0, same_address_writes = 0; + + FpuRfOriginal original( + .R0_addr(ra0), .R0_en(re0), .R0_clk(clk), .R0_data(old0), + .R1_addr(ra1), .R1_en(re1), .R1_clk(clk), .R1_data(old1), + .R2_addr(ra2), .R2_en(re2), .R2_clk(clk), .R2_data(old2), + .W0_addr(wa0), .W0_en(we0), .W0_clk(clk), .W0_data(wd0), + .W1_addr(wa1), .W1_en(we1), .W1_clk(clk), .W1_data(wd1) + ); + FpuRfLvt candidate( + .R0_addr(ra0), .R0_en(re0), .R0_clk(clk), .R0_data(new0), + .R1_addr(ra1), .R1_en(re1), .R1_clk(clk), .R1_data(new1), + .R2_addr(ra2), .R2_en(re2), .R2_clk(clk), .R2_data(new2), + .W0_addr(wa0), .W0_en(we0), .W0_clk(clk), .W0_data(wd0), + .W1_addr(wa1), .W1_en(we1), .W1_clk(clk), .W1_data(wd1) + ); + + function [64:0] random_data; + reg [31:0] lo, hi, extra; + begin + lo = $random(seed); hi = $random(seed); extra = $random(seed); + random_data = {extra[0], hi, lo}; + end + endfunction + + task check; + begin + if (re0 && valid[ra0]) begin + if (old0 !== expected[ra0] || new0 !== expected[ra0]) + $fatal(1, "R0 mismatch at %0d", ra0); + comparisons = comparisons + 1; + end + if (re1 && valid[ra1]) begin + if (old1 !== expected[ra1] || new1 !== expected[ra1]) + $fatal(1, "R1 mismatch at %0d", ra1); + comparisons = comparisons + 1; + end + if (re2 && valid[ra2]) begin + if (old2 !== expected[ra2] || new2 !== expected[ra2]) + $fatal(1, "R2 mismatch at %0d", ra2); + comparisons = comparisons + 1; + end + end + endtask + + task edge_and_check; + begin + #1; check(); + @(posedge clk); + if (we0) begin expected[wa0] = wd0; valid[wa0] = 1; end + if (we1) begin expected[wa1] = wd1; valid[wa1] = 1; end + if (we0 && we1) begin + dual_writes = dual_writes + 1; + if (wa0 == wa1) same_address_writes = same_address_writes + 1; + end + #1; check(); + // Asynchronous reads must follow new addresses without a clock edge. + ra0 = ra0 + 1; ra1 = ra1 + 3; ra2 = ra2 + 7; + #1; check(); + end + endtask + + initial begin + for (integer i = 0; i < 32; i = i + 1) begin + @(negedge clk); + wa0 = i; we0 = 1; we1 = 0; wd0 = random_data(); + re0 = 1; re1 = 1; re2 = 1; + edge_and_check(); + end + for (integer i = 0; i < 20000; i = i + 1) begin + @(negedge clk); + wa0 = $random(seed); wa1 = $random(seed); + if (i % 4 == 0) wa1 = wa0; + we0 = (i % 8 != 0); we1 = (i % 8 != 1); + wd0 = random_data(); wd1 = random_data(); + ra0 = wa0; ra1 = wa1; ra2 = $random(seed); + re0 = (i % 5 != 0); re1 = (i % 5 != 1); re2 = (i % 5 != 2); + edge_and_check(); + end + if (dual_writes < 10000 || same_address_writes < 2000 || comparisons < 100000) + $fatal(1, "Insufficient conflict/asynchronous read coverage"); + $display("PASS FPU_RF_LVT cycles=20032 comparisons=%0d dual_writes=%0d same_address_writes=%0d", + comparisons, dual_writes, same_address_writes); + $finish; + end + initial begin #1000000; $fatal(1, "RF test timeout"); end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/tb_globalrob.sv b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/tb_globalrob.sv new file mode 100644 index 0000000..8213b7d --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/tb_globalrob.sv @@ -0,0 +1,29 @@ +`timescale 1ns/1ps +module tb; + reg clock = 0, reset = 1; + reg [31:0] seed = 32'h12345678; + wire passed; + integer cycles = 0; + GlobalRobCheck dut(.*); + always #5 clock = ~clock; + initial begin + repeat (5) @(negedge clock); + reset = 0; + repeat (1200) @(negedge clock); + reset = 1; seed = 32'hda7a0319; + repeat (5) @(negedge clock); + reset = 0; + repeat (1800) @(negedge clock); + reset = 1; seed = 32'habcdef01; + repeat (5) @(negedge clock); + reset = 0; + end + always @(posedge clock) begin + cycles <= cycles + 1; + if (!reset && passed) begin + $display("PASS GLOBALROB RAM/register cycle comparison, payloads, wrap, stalls, resets cycles=%0d", cycles); + $finish; + end + if (cycles > 15000) $fatal(1, "GlobalROB test timeout"); + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/tb_group_query.sv b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/tb_group_query.sv new file mode 100644 index 0000000..c340835 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/tb_group_query.sv @@ -0,0 +1,23 @@ +module tb; + reg clock = 0; + reg reset = 1; + wire passed; + GroupQueryCheck dut(.clock(clock), .reset(reset), .passed(passed)); + always #5 clock = ~clock; + initial begin + repeat (5) @(negedge clock); + reset = 0; + wait(passed); + @(negedge clock); + reset = 1; + repeat (5) @(negedge clock); + reset = 0; + wait(passed); + $display("PASS: 256 concurrent group queries, stalls, shared/private selection, reset and repeat"); + $finish; + end + initial begin + #200000; + $fatal(1, "Group query timeout"); + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/tb_platform_bresp.sv b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/tb_platform_bresp.sv new file mode 100644 index 0000000..f3c0490 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/tb_platform_bresp.sv @@ -0,0 +1,58 @@ +`timescale 1ns/1ps +module tb_platform_bresp; + reg clk=0; + always #5 clk=~clk; + reg reset=1; + reg [30:0] address=0; + reg [2:0] size=2; + reg [7:0] length=0; + reg awvalid=0,wvalid=0,last=1,bready=0; + toy_a7_platform dut(.clk(clk),.reset(reset),.uart_rx_in(1'b1), + .ddr_awready(1'b1),.ddr_wready(1'b1),.ddr_bid(4'd0),.ddr_bresp(2'd0),.ddr_bvalid(1'b0), + .ddr_arready(1'b1),.ddr_rid(4'd0),.ddr_rdata(128'd0),.ddr_rresp(2'd0),.ddr_rlast(1'b1),.ddr_rvalid(1'b0), + .flash_miso(1'b0),.flash_recovery(1'b0)); + task automatic write_case(input [30:0] addr,input [2:0] width,input [7:0] len,input [1:0] expected); + @(negedge clk);address=addr;size=width;length=len;awvalid=1; + do @(posedge clk);while(!dut.peripherals_aw_ready); + @(negedge clk);awvalid=0; + for(integer beat=0;beat<=len;beat=beat+1) begin + wvalid=1;last=beat==len; + do @(posedge clk);while(!dut.peripherals_w_ready); + @(negedge clk);wvalid=0; + end + while(!dut.peripherals_b_valid) @(negedge clk); + repeat(5) begin + // Observe the CPU input, through actual platform wiring and real SCU. + if(dut.chip.peripherals_b_valid!==1 || dut.chip.peripherals_b_bits_resp!==expected || + dut.chip.peripherals_b_bits_id!==2) + $fatal(1,"Platform B response addr=%h valid=%b id=%b actual=%b expected=%b",addr, + dut.chip.peripherals_b_valid,dut.chip.peripherals_b_bits_id,dut.chip.peripherals_b_bits_resp,expected); + @(negedge clk); + end + bready=1;@(negedge clk);bready=0; + if(dut.chip.peripherals_b_valid!==0) $fatal(1,"BVALID not cleared after handshake"); + endtask + initial begin + force dut.cpu_run=1; + force dut.peripherals_aw_valid=awvalid; + force dut.peripherals_aw_bits_addr=address; + force dut.peripherals_aw_bits_size=size; + force dut.peripherals_aw_bits_len=length; + force dut.peripherals_aw_bits_id=2; + force dut.peripherals_aw_bits_burst=1; + force dut.peripherals_w_valid=wvalid; + force dut.peripherals_w_bits_last=last; + force dut.peripherals_w_bits_data=64'h13572468; + force dut.peripherals_w_bits_strb=8'h0f; + force dut.peripherals_b_ready=bready; + repeat(5) @(negedge clk);reset=0; + write_case(31'h60000000,2,0,0); + if(!dut.exited || dut.exit_code!==32'h13572468) $fatal(1,"Valid MMIO changed"); + write_case(31'h60030000,2,0,2); + write_case(31'h60000002,2,0,2); + write_case(31'h60000000,2,1,2); + $display("PASS platform AXI B response: valid, invalid address, unaligned, burst, ID and backpressure"); + $finish; + end + initial begin #100000;$fatal(1,"Platform response watchdog");end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/tb_round_shift.sv b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/tb_round_shift.sv new file mode 100644 index 0000000..725a304 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/tb_round_shift.sv @@ -0,0 +1,59 @@ +module tb; + logic signed [19:0] value20; + logic signed [31:0] value32; + logic [4:0] amount; + wire signed [19:0] actual20, original20; + wire signed [31:0] actual32, original32; + RoundShiftChecks dut(.*); + integer comparisons = 0; + logic [63:0] rng = 64'h17339cab28eaf641; + + // Independent oracle: magnitude division/remainder, not a barrel-shift copy. + function automatic longint signed nearest_even(input longint signed v, + input integer s); + longint signed magnitude, divisor, quotient, remainder; + if (s == 0) return v; + magnitude = v < 0 ? -v : v; + divisor = 64'sd1 << s; + quotient = magnitude / divisor; + remainder = magnitude % divisor; + if (2 * remainder > divisor || + (2 * remainder == divisor && quotient % 2 != 0)) quotient++; + return v < 0 ? -quotient : quotient; + endfunction + + task automatic check(input longint signed v, input integer s); + longint signed expected20, expected32; + value20 = v[19:0]; + value32 = v[31:0]; + amount = s[4:0]; + #1; + expected20 = nearest_even(longint'(value20), s); + expected32 = nearest_even(longint'(value32), s); + if (actual20 !== expected20[19:0] || actual32 !== expected32[31:0] || + actual20 !== original20 || actual32 !== original32) + $fatal(1, "RNE v=%0d s=%0d actual20=%0d gold20=%0d actual32=%0d gold32=%0d", + v, s, actual20, expected20, actual32, expected32); + comparisons += 2; + endtask + + initial begin + for (integer s = 0; s < 32; s++) begin + check(0, s); check(1, s); check(-1, s); + check(2147483647, s); check(-2147483648, s); + check(524287, s); check(-524288, s); + if (s > 0) begin + // Halfway and adjacent values on either side, odd/even positive/negative. + for (integer q = -6; q <= 6; q++) + for (integer delta = -1; delta <= 1; delta++) + check(q * (64'sd1 << s) + (64'sd1 << (s - 1)) + delta, s); + end + end + for (integer i = 0; i < 200000; i++) begin + rng ^= rng << 13; rng ^= rng >> 7; rng ^= rng << 17; + check(longint'(int'(rng[31:0])), int'(rng[36:32])); + end + $display("PASS ROUND_SHIFT comparisons=%0d widths=20,32 shifts=0..31", comparisons); + $finish; + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/tb_subrob.sv b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/tb_subrob.sv new file mode 100644 index 0000000..90d00a7 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/tb_subrob.sv @@ -0,0 +1,16 @@ +module tb; + reg clock = 0, reset = 1; + wire passed; + integer cycles = 0; + SubRobCheck dut(.*); + always #5 clock = ~clock; + initial begin repeat(5) @(negedge clock); reset=0; end + always @(posedge clock) if (!reset) begin + cycles <= cycles + 1; + if (passed) begin + $display("PASS SUBROB streaming rows=40 commands=39 cycles=%0d", cycles); + $finish; + end + if (cycles > 10000) $fatal(1, "SubROB timeout"); + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/ws_round_edges.c b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/ws_round_edges.c new file mode 100644 index 0000000..fa5cced --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/ws_round_edges.c @@ -0,0 +1,63 @@ +// Independent integer oracle and alternating OS/WS cases on the real CPU. +#include "buckyball.h" +#include +#include +#include + +#define DIM 8 +static elem_t a[DIM * DIM] __attribute__((aligned(64))); +static elem_t b[DIM * DIM] __attribute__((aligned(64))); +static elem_t d[DIM * DIM] __attribute__((aligned(64))); +static result_t c[DIM * DIM] __attribute__((aligned(64))); +static const int shifts[] = {0, 1, 2, 4, 8, 19, 20, 31}; +static const int ties[] = {-41, -40, -39, -25, -24, -23, -9, -8, + -7, -3, -2, -1, 0, 1, 2, 3, + 7, 8, 9, 23, 24, 25, 39, 40, 41}; + +static int32_t nearest_even(int32_t value, int shift) { + if (!shift) return value; + int64_t magnitude = value < 0 ? -(int64_t)value : value; + int64_t divisor = (int64_t)1 << shift; + int64_t quotient = magnitude / divisor; + int64_t remainder = magnitude % divisor; + if (2 * remainder > divisor || + (2 * remainder == divisor && quotient % 2)) quotient++; + return value < 0 ? -quotient : quotient; +} + +int main(void) { + int run = 0; + for (unsigned si = 0; si < sizeof(shifts) / sizeof(shifts[0]); si++) + for (int pattern = 0; pattern < 4; pattern++) + for (int mode = 0; mode < 2; mode++, run++) { + for (int r = 0; r < DIM; r++) + for (int k = 0; k < DIM; k++) { + int index = r * DIM + k; + a[index] = pattern == 3 ? -128 : (r == k ? (pattern == 2 ? 4 : 1) : 0); + b[index] = pattern == 3 ? ((k & 1) ? 127 : -128) : ties[(index + 7 * pattern) % 25]; + d[index] = mode && pattern == 1 ? (index % 7 - 3) : 0; + c[index] = 0x12345678; + } + bb_mem_alloc(0, 1, 1); + bb_mem_alloc(1, 1, 1); + bb_mem_alloc(2, 1, 1); + bb_mem_alloc(3, 1, 4); + bb_mvin((uintptr_t)b, 0, DIM, 1); + bb_mvin((uintptr_t)a, 1, DIM, 1); + bb_mvin((uintptr_t)d, 2, DIM, 1); + bb_gemmini_config(mode, 0, 0, 0, shifts[si]); + bb_gemmini_preload(mode ? 0 : 1, 3, DIM, 0, 0); + bb_gemmini_compute_preloaded(1, mode ? 2 : 0, 3, DIM, 0, 0, 0); + bb_mvout((uintptr_t)c, 3, DIM, 1); + bb_fence(); + for (int r = 0; r < DIM; r++) + for (int col = 0; col < DIM; col++) { + int32_t sum = d[r * DIM + col]; + for (int k = 0; k < DIM; k++) + sum += (int32_t)a[r * DIM + k] * b[k * DIM + col]; + if (c[r * DIM + col] != nearest_even(sum, shifts[si])) return run + 1; + } + for (int bank = 0; bank < 4; bank++) bb_mem_release(bank); + } + return 0; +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/ws_shift_edges.c b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/ws_shift_edges.c new file mode 100644 index 0000000..bbeccdf --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/sources/tests/ws_shift_edges.c @@ -0,0 +1,63 @@ +// Focused RNE regression with zero bias; nonzero bias stays in ws_round_edges.c. +#include "buckyball.h" +#include +#include +#include + +#define DIM 8 +static elem_t a[DIM * DIM] __attribute__((aligned(64))); +static elem_t b[DIM * DIM] __attribute__((aligned(64))); +static elem_t d[DIM * DIM] __attribute__((aligned(64))); +static result_t c[DIM * DIM] __attribute__((aligned(64))); +static const int shifts[] = {0, 1, 2, 4, 8, 19, 20, 31}; +static const int ties[] = {-41, -40, -39, -25, -24, -23, -9, -8, + -7, -3, -2, -1, 0, 1, 2, 3, + 7, 8, 9, 23, 24, 25, 39, 40, 41}; + +static int32_t nearest_even(int32_t value, int shift) { + if (!shift) return value; + int64_t magnitude = value < 0 ? -(int64_t)value : value; + int64_t divisor = (int64_t)1 << shift; + int64_t quotient = magnitude / divisor; + int64_t remainder = magnitude % divisor; + if (2 * remainder > divisor || + (2 * remainder == divisor && quotient % 2)) quotient++; + return value < 0 ? -quotient : quotient; +} + +int main(void) { + int run = 0; + for (unsigned si = 0; si < sizeof(shifts) / sizeof(shifts[0]); si++) + for (int pattern = 0; pattern < 4; pattern++) + for (int mode = 0; mode < 2; mode++, run++) { + for (int r = 0; r < DIM; r++) + for (int k = 0; k < DIM; k++) { + int index = r * DIM + k; + a[index] = pattern == 3 ? -128 : (r == k ? (pattern == 2 ? 4 : 1) : 0); + b[index] = pattern == 3 ? ((k & 1) ? 127 : -128) : ties[(index + 7 * pattern) % 25]; + d[index] = 0; + c[index] = 0x12345678; + } + bb_mem_alloc(0, 1, 1); + bb_mem_alloc(1, 1, 1); + bb_mem_alloc(2, 1, 1); + bb_mem_alloc(3, 1, 4); + bb_mvin((uintptr_t)b, 0, DIM, 1); + bb_mvin((uintptr_t)a, 1, DIM, 1); + bb_mvin((uintptr_t)d, 2, DIM, 1); + bb_gemmini_config(mode, 0, 0, 0, shifts[si]); + bb_gemmini_preload(mode ? 0 : 1, 3, DIM, 0, 0); + bb_gemmini_compute_preloaded(1, mode ? 2 : 0, 3, DIM, 0, 0, 0); + bb_mvout((uintptr_t)c, 3, DIM, 1); + bb_fence(); + for (int r = 0; r < DIM; r++) + for (int col = 0; col < DIM; col++) { + int32_t sum = d[r * DIM + col]; + for (int k = 0; k < DIM; k++) + sum += (int32_t)a[r * DIM + k] * b[k * DIM + col]; + if (c[r * DIM + col] != nearest_even(sum, shifts[si])) return run + 1; + } + for (int bank = 0; bank < 4; bank++) bb_mem_release(bank); + } + return 0; +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/backpressure-mutation/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/backpressure-mutation/RESULT.json new file mode 100644 index 0000000..4bc58dc --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/backpressure-mutation/RESULT.json @@ -0,0 +1,60 @@ +{ + "result": "PASS_MUTATION_ORACLES", + "physical_hardware_tested": false, + "cases": [ + { + "case": "old-test", + "exit_code": 0, + "expected_exit_code": 0, + "result": "PASS", + "sources": { + "board/toy_a7_platform.sv": "f9bc06535b7de19a6b1b501f06effe90519fd43a78e669ab7425d301662540b8", + "build/backpressure-mutation/scu-mutant.sv": "71386c725d8406dd15b8b4ee9c07d8b5d4f48ec9ffd5fc699b6d6da1f5127302", + "evidence/2026-10-12/pr10-review/sources/tests/tb_platform_bresp.sv": "e69671fb9a5ea6a77ccc0ec8d7a8ca0afa07e9e8b035d0e107530032beabe1a0", + "board/axi_fullwidth.sv": "bf07ae27724dbd0a361d732dfb57109f06beef207c47a066d400cb06d7f07d5a", + "board/ddr_uart_loader.sv": "980f4cd2e3fa2a00b66143f879bc749ed952c2c1e54331460821bac0300c43d6", + "board/loader_axi.sv": "05609b0870054ea675aedb406f6215cd456f18db6d6428b461cbae03d9a662f4", + "board/uart_rx.sv": "0b35263884577324f146ff7fd516e5b561dcc8787e0d8ad599669bac1958406d", + "board/uart_tx.sv": "c20d420fc20be4f6313bdde5abc45ef0b9f8e93bf75350dd9951bc8868b3b65c", + "board/flash_spi_byte.sv": "4d1fac5238f31fb3a69a58d1aca9ccec722e833d788113b94d86c6a1b861045a", + "tests/ToyLinuxChipPorts.sv": "e4c06220cd7025972d432b06c452e85c62bd2cfccad618b2b993499b62e6621a" + } + }, + { + "case": "new-test", + "exit_code": 1, + "expected_exit_code": 1, + "result": "PASS", + "sources": { + "board/toy_a7_platform.sv": "f9bc06535b7de19a6b1b501f06effe90519fd43a78e669ab7425d301662540b8", + "build/backpressure-mutation/scu-mutant.sv": "71386c725d8406dd15b8b4ee9c07d8b5d4f48ec9ffd5fc699b6d6da1f5127302", + "tests/tb_platform_bresp.sv": "289875c2e92800307aa0b7fc5186c946ba127835473b30f626aef7baa67b4fe8", + "board/axi_fullwidth.sv": "bf07ae27724dbd0a361d732dfb57109f06beef207c47a066d400cb06d7f07d5a", + "board/ddr_uart_loader.sv": "980f4cd2e3fa2a00b66143f879bc749ed952c2c1e54331460821bac0300c43d6", + "board/loader_axi.sv": "05609b0870054ea675aedb406f6215cd456f18db6d6428b461cbae03d9a662f4", + "board/uart_rx.sv": "0b35263884577324f146ff7fd516e5b561dcc8787e0d8ad599669bac1958406d", + "board/uart_tx.sv": "c20d420fc20be4f6313bdde5abc45ef0b9f8e93bf75350dd9951bc8868b3b65c", + "board/flash_spi_byte.sv": "4d1fac5238f31fb3a69a58d1aca9ccec722e833d788113b94d86c6a1b861045a", + "tests/ToyLinuxChipPorts.sv": "e4c06220cd7025972d432b06c452e85c62bd2cfccad618b2b993499b62e6621a" + } + }, + { + "case": "old-response", + "exit_code": 1, + "expected_exit_code": 1, + "result": "PASS", + "sources": { + "evidence/2026-10-12/pr10-review/old-platform.sv": "01fe1f8e2621a1a023ac3b8d91758868b190760f6e706ae1d34a67857b96d846", + "board/axi_scu.sv": "ee77bf641d61811b4c1faea845752850c22461a63b4cdfd3d6f9cd223e6c2fc2", + "tests/tb_platform_bresp.sv": "289875c2e92800307aa0b7fc5186c946ba127835473b30f626aef7baa67b4fe8", + "board/axi_fullwidth.sv": "bf07ae27724dbd0a361d732dfb57109f06beef207c47a066d400cb06d7f07d5a", + "board/ddr_uart_loader.sv": "980f4cd2e3fa2a00b66143f879bc749ed952c2c1e54331460821bac0300c43d6", + "board/loader_axi.sv": "05609b0870054ea675aedb406f6215cd456f18db6d6428b461cbae03d9a662f4", + "board/uart_rx.sv": "0b35263884577324f146ff7fd516e5b561dcc8787e0d8ad599669bac1958406d", + "board/uart_tx.sv": "c20d420fc20be4f6313bdde5abc45ef0b9f8e93bf75350dd9951bc8868b3b65c", + "board/flash_spi_byte.sv": "4d1fac5238f31fb3a69a58d1aca9ccec722e833d788113b94d86c6a1b861045a", + "tests/ToyLinuxChipPorts.sv": "e4c06220cd7025972d432b06c452e85c62bd2cfccad618b2b993499b62e6621a" + } + } + ] +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/backpressure-mutation/new-test-compile.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/backpressure-mutation/new-test-compile.log new file mode 100644 index 0000000..e69de29 diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/backpressure-mutation/new-test.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/backpressure-mutation/new-test.log new file mode 100644 index 0000000..b16aaca --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/backpressure-mutation/new-test.log @@ -0,0 +1,2 @@ +FATAL: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/tb_platform_bresp.sv:28: Platform B response addr=60000000 valid=0 id=10 actual=00 expected=00 + Time: 90000 Scope: tb_platform_bresp.write_case diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/backpressure-mutation/old-response-compile.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/backpressure-mutation/old-response-compile.log new file mode 100644 index 0000000..e69de29 diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/backpressure-mutation/old-response.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/backpressure-mutation/old-response.log new file mode 100644 index 0000000..ccf34b9 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/backpressure-mutation/old-response.log @@ -0,0 +1,2 @@ +FATAL: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/tb_platform_bresp.sv:28: Platform B response addr=60030000 valid=1 id=10 actual=01 expected=10 + Time: 170000 Scope: tb_platform_bresp.write_case diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/backpressure-mutation/old-test-compile.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/backpressure-mutation/old-test-compile.log new file mode 100644 index 0000000..e69de29 diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/backpressure-mutation/old-test.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/backpressure-mutation/old-test.log new file mode 100644 index 0000000..491da15 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/backpressure-mutation/old-test.log @@ -0,0 +1,2 @@ +PASS platform AXI B response: valid, invalid address, unaligned, burst, ID and backpressure +/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/evidence/2026-10-12/pr10-review/sources/tests/tb_platform_bresp.sv:52: $finish called at 420000 (1ps) diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/backpressure-mutation/scu-mutant.sv b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/backpressure-mutation/scu-mutant.sv new file mode 100644 index 0000000..feb65be --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/backpressure-mutation/scu-mutant.sv @@ -0,0 +1,109 @@ +// Single-hart SCU console used by the pinned Buckyball OpenSBI platform. +// EXIT 0x60000000, TX 0x60020000, RX 0x60020004, STATUS 0x60020005. +// Reads use AXI lane positions; RX pops only after its R response is accepted. +module axi_scu #(parameter FLASH_BOOT=0) ( + input wire clk, reset, + input wire [1:0] awid, arid, + input wire [30:0] awaddr, araddr, + input wire [7:0] awlen, arlen, + input wire [2:0] awsize, arsize, + input wire [1:0] awburst, arburst, + input wire awvalid, arvalid, wvalid, wlast, bready, rready, + output wire awready, arready, wready, + input wire [63:0] wdata, input wire [7:0] wstrb, + output reg [1:0] bid, rid, bresp, rresp, + output reg bvalid, rvalid, rlast, output reg [63:0] rdata, + input wire rx_valid, rx_error, input wire [7:0] rx_data, + output wire tx_valid, output wire [7:0] tx_data, input wire tx_ready, + output reg exited, output reg [31:0] exit_code, output wire interrupt, + input wire flash_miso, flash_recovery, + output wire flash_mosi, flash_sck, + output reg flash_cs_n +); + // SBI/HVC is polled. A paste may otherwise overflow a 16-byte FIFO before + // Linux's next console poll; use RAM-backed 256-byte buffering. + (* ram_style="distributed" *) reg [7:0] fifo[0:255]; + reg [7:0] rp, wp; + reg [8:0] count; + reg overflow, framing, pop_on_read, wa, bad; + reg [7:0] wr_left, rd_left; + reg [30:0] wr_addr; + wire pop=rvalid && rready && pop_on_read; + wire push=rx_valid && (count<256 || pop); + wire wr_tx=wr_addr==31'h60020000 && !bad && wstrb[0]; + wire wr_spi=FLASH_BOOT && wr_addr==31'h60020008 && !bad && wstrb[0]; + wire wr_cs=FLASH_BOOT && wr_addr==31'h6002000c && !bad && wstrb[4]; + wire spi_busy; + wire [7:0] spi_rx; + generate if(FLASH_BOOT) begin : spi_enabled + flash_spi_byte flash (.clk(clk),.reset(reset),.start(wvalid && wready && wr_spi), + .tx_data(wdata[7:0]),.miso(flash_miso),.mosi(flash_mosi),.sck(flash_sck), + .busy(spi_busy),.rx_data(spi_rx)); + end else begin + assign spi_busy=0;assign spi_rx=0;assign flash_mosi=0;assign flash_sck=0; + end endgenerate + assign awready=!reset && !wa && !bvalid; + assign arready=!reset && !rvalid; + assign wready=!reset && wa && (!wr_tx || tx_ready) && (!(wr_spi || wr_cs) || !spi_busy); + assign tx_valid=!reset && wa && wvalid && wr_tx; + assign tx_data=wdata[7:0]; + assign interrupt=count!=0; + always @(posedge clk) begin + if(reset) begin + rp<=0;wp<=0;count<=0;overflow<=0;framing<=0;pop_on_read<=0; + wa<=0;bad<=0;wr_left<=0;rd_left<=0;wr_addr<=0; + bid<=0;rid<=0;bresp<=0;rresp<=0;bvalid<=0;rvalid<=0;rlast<=0;rdata<=0; + exited<=0;exit_code<=0; + flash_cs_n<=1; + end else begin + if(bvalid) bvalid<=0; + if(awvalid && awready) begin + wa<=1;bid<=awid;wr_addr<=awaddr;wr_left<=awlen; + bad<=awlen!=0 || awsize>3 || awburst>1 || + (awaddr & ((31'd1<3 || arburst>1 || (araddr & ((31'd1<=3) rdata[47:40]<={5'd0,framing,overflow,count!=0}; + end else rresp<=2; + end + if(push) begin fifo[wp]<=rx_data;wp<=wp+1'b1;end + if(pop) rp<=rp+1'b1; + case({push,pop}) + 2'b10:count<=count+1'b1; + 2'b01:count<=count-1'b1; + default:count<=count; + endcase + if(rx_valid && !push) overflow<=1; + if(rx_error) framing<=1; + end + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-cdc/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-cdc/RESULT.json new file mode 100644 index 0000000..14d57f7 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-cdc/RESULT.json @@ -0,0 +1,10 @@ +{ + "result": "PASS_BOARD_CDC", + "board_run": "board-rob-ram-20261013-010921", + "core_clock_hz": 25000000, + "ui_clock_hz": 83333333, + "read_beats": 90, + "physical_mig_simulated": false, + "xci_sha256": "33a73fd614db8bd3daf6d45a6c747e087caacd7e7ef6f610f3cc894120eac025", + "bench_sha256": "0903001dfe5bb2d8d5a36eb84545f6e08a2eb3c8bd86c8f20a1ff37c9bb51de2" +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-cdc/console.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-cdc/console.log new file mode 100644 index 0000000..2fe4c2c --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-cdc/console.log @@ -0,0 +1,128 @@ + +****** Vivado v2024.1 (64-bit) + **** SW Build 5076996 on Wed May 22 18:36:09 MDT 2024 + **** IP Build 5075265 on Wed May 22 21:45:21 MDT 2024 + **** SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024 + **** Start of session at: Tue Oct 13 01:53:28 2026 + ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. + ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. + +source /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cdc/simulate.tcl +# create_project -force cdc_test {/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cdc/project} -part xc7a100tcsg324-1 +create_project: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1452.602 ; gain = 17.871 ; free physical = 120755 ; free virtual = 492259 +# read_ip {/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cdc/ip/toy_axi_cdc/toy_axi_cdc.xci} +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data0/tools/Xilinx/Vivado/2024.1/data/ip'. +WARNING: [Vivado 12-13650] The IP file '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cdc/ip/toy_axi_cdc/toy_axi_cdc.xci' has been moved from its original location, as a result the outputs for this IP will now be generated in '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cdc/ip/toy_axi_cdc'. Alternatively a copy of the IP can be imported into the project using one of the 'import_ip' or 'import_files' commands. +# read_verilog -sv {/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/axi_fullwidth.sv} +# read_verilog -sv {/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv} +# read_verilog -sv {/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cdc/tb_board_cdc.sv} +# set_property top tb_board_cdc [get_filesets sim_1] +# set_property xsim.simulate.runtime all [get_filesets sim_1] +# launch_simulation +Command: launch_simulation +INFO: [Vivado 12-12493] Simulation top is 'tb_board_cdc' +INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator... +INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cdc/project/cdc_test.sim/sim_1/behav/xsim' +INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order. +INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs +INFO: [SIM-utils-51] Simulation object is 'sim_1' +INFO: [SIM-utils-72] Using boost library from '/data0/tools/Xilinx/Vivado/2024.1/tps/boost_1_72_0' +INFO: [USF-XSim-7] Finding pre-compiled libraries... +INFO: [USF-XSim-11] File '/data0/tools/Xilinx/Vivado/2024.1/data/xsim/xsim.ini' copied to run dir:'/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cdc/project/cdc_test.sim/sim_1/behav/xsim' +INFO: [SIM-utils-54] Inspecting design source files for 'tb_board_cdc' in fileset 'sim_1'... +INFO: [USF-XSim-97] Finding global include files... +INFO: [USF-XSim-98] Fetching design files from 'sim_1'... +INFO: [USF-XSim-2] XSim::Compile design +INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cdc/project/cdc_test.sim/sim_1/behav/xsim' +xvlog --incr --relax -L uvm -prj tb_board_cdc_vlog.prj +INFO: [VRFC 10-2263] Analyzing Verilog file "/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cdc/ip/toy_axi_cdc/sim/toy_axi_cdc.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module toy_axi_cdc +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/axi_fullwidth.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module axi_fullwidth +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module axi_smoke_memory +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cdc/tb_board_cdc.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module tb_board_cdc +INFO: [VRFC 10-2263] Analyzing Verilog file "/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cdc/project/cdc_test.sim/sim_1/behav/xsim/glbl.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module glbl +xvhdl --incr --relax -prj tb_board_cdc_vhdl.prj +Waiting for jobs to finish... +No pending jobs, compilation finished. +INFO: [USF-XSim-69] 'compile' step finished in '3' seconds +INFO: [USF-XSim-3] XSim::Elaborate design +INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cdc/project/cdc_test.sim/sim_1/behav/xsim' +xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L axi_infrastructure_v1_1_0 -L fifo_generator_v13_2_10 -L axi_clock_converter_v2_1_30 -L uvm -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_board_cdc_behav xil_defaultlib.tb_board_cdc xil_defaultlib.glbl -log elaborate.log +Vivado Simulator v2024.1 +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +Running: /data0/tools/Xilinx/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L axi_infrastructure_v1_1_0 -L fifo_generator_v13_2_10 -L axi_clock_converter_v2_1_30 -L uvm -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_board_cdc_behav xil_defaultlib.tb_board_cdc xil_defaultlib.glbl -log elaborate.log +Using 8 slave threads. +Starting static elaboration +Pass Through NonSizing Optimizer +Completed static elaboration +Starting simulation data flow analysis +WARNING: [XSIM 43-4099] "/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/axi_fullwidth.sv" Line 4. Module axi_fullwidth doesn't have a timescale but at least one module in design has a timescale. +WARNING: [XSIM 43-4099] "/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv" Line 3. Module axi_smoke_memory(ADDR_BITS=28,BASE=0,CAPACITY=4096) doesn't have a timescale but at least one module in design has a timescale. +WARNING: [XSIM 43-4099] "/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/axi_fullwidth.sv" Line 4. Module axi_fullwidth doesn't have a timescale but at least one module in design has a timescale. +WARNING: [XSIM 43-4099] "/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv" Line 3. Module axi_smoke_memory(ADDR_BITS=28,BASE=0,CAPACITY=4096) doesn't have a timescale but at least one module in design has a timescale. +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling module fifo_generator_v13_2_10.fifo_generator_v13_2_10_sync_sta... +Compiling module fifo_generator_v13_2_10.fifo_generator_v13_2_10_bhv_ver_... +Compiling module fifo_generator_v13_2_10.fifo_generator_v13_2_10_bhv_ver_... +Compiling module fifo_generator_v13_2_10.fifo_generator_v13_2_10_CONV_VER... +Compiling module fifo_generator_v13_2_10.fifo_generator_vlog_beh(C_DATA_C... +Compiling module fifo_generator_v13_2_10.fifo_generator_v13_2_10_bhv_ver_... +Compiling module fifo_generator_v13_2_10.fifo_generator_v13_2_10_bhv_ver_... +Compiling module fifo_generator_v13_2_10.fifo_generator_v13_2_10_CONV_VER... +Compiling module fifo_generator_v13_2_10.fifo_generator_vlog_beh(C_DATA_C... +Compiling module fifo_generator_v13_2_10.fifo_generator_v13_2_10_bhv_ver_... +Compiling module fifo_generator_v13_2_10.fifo_generator_v13_2_10_bhv_ver_... +Compiling module fifo_generator_v13_2_10.fifo_generator_v13_2_10_CONV_VER... +Compiling module fifo_generator_v13_2_10.fifo_generator_vlog_beh(C_DATA_C... +Compiling module fifo_generator_v13_2_10.fifo_generator_vlog_beh(C_DATA_C... +Compiling module fifo_generator_v13_2_10.fifo_generator_v13_2_10_bhv_ver_... +Compiling module fifo_generator_v13_2_10.fifo_generator_v13_2_10_bhv_ver_... +Compiling module fifo_generator_v13_2_10.fifo_generator_v13_2_10_CONV_VER... +Compiling module fifo_generator_v13_2_10.fifo_generator_vlog_beh(C_DATA_C... +Compiling module axi_clock_converter_v2_1_30.axi_clock_converter_v2_1_30_axi_... +Compiling module xil_defaultlib.toy_axi_cdc +Compiling module xil_defaultlib.axi_fullwidth +Compiling module xil_defaultlib.axi_smoke_memory(ADDR_BITS=28,BA... +Compiling module xil_defaultlib.tb_board_cdc +Compiling module xil_defaultlib.glbl +Built simulation snapshot tb_board_cdc_behav +INFO: [USF-XSim-69] 'elaborate' step finished in '5' seconds +INFO: [USF-XSim-4] XSim::Simulate design +INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cdc/project/cdc_test.sim/sim_1/behav/xsim' +INFO: [USF-XSim-98] *** Running xsim + with args "tb_board_cdc_behav -key {Behavioral:sim_1:Functional:tb_board_cdc} -tclbatch {tb_board_cdc.tcl} -log {simulate.log}" +INFO: [USF-XSim-8] Loading simulator feature +Time resolution is 1 ps +source tb_board_cdc.tcl +## set curr_wave [current_wave_config] +## if { [string length $curr_wave] == 0 } { +## if { [llength [get_objects]] > 0} { +## add_wave / +## set_property needs_save false [current_wave_config] +## } else { +## send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +## } +## } +## run all +WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information. +WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information. +WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information. +WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information. +WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information. +PASS BOARD_CDC: sizes 8..128 bits, INCR/FIXED, strobes, concurrent R/W, stalls, IDs, range/4KiB rejection; read beats=90 +$finish called at time : 100800 ns : File "/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cdc/tb_board_cdc.sv" Line 221 +INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_board_cdc_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for all +launch_simulation: Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1581.262 ; gain = 115.785 ; free physical = 119468 ; free virtual = 491146 +# close_sim +INFO: [Simtcl 6-16] Simulation closed +# exit +INFO: [Common 17-206] Exiting Vivado at Tue Oct 13 01:53:48 2026... diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-cdc/project/cdc_test.sim/sim_1/behav/xsim/simulate.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-cdc/project/cdc_test.sim/sim_1/behav/xsim/simulate.log new file mode 100644 index 0000000..deb2ba3 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-cdc/project/cdc_test.sim/sim_1/behav/xsim/simulate.log @@ -0,0 +1,8 @@ +Time resolution is 1 ps +WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information. +WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information. +WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information. +WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information. +WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information. +PASS BOARD_CDC: sizes 8..128 bits, INCR/FIXED, strobes, concurrent R/W, stalls, IDs, range/4KiB rejection; read beats=90 +$finish called at time : 100800 ns : File "/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cdc/tb_board_cdc.sv" Line 221 diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-cdc/tb_board_cdc.sv b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-cdc/tb_board_cdc.sv new file mode 100644 index 0000000..68dfddb --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-cdc/tb_board_cdc.sv @@ -0,0 +1,224 @@ +`timescale 1ns/1ps +module tb_board_cdc; + reg clk=0;always #20 clk=~clk; + reg ui_clk=0; initial begin #3; forever #6 ui_clk=~ui_clk; end + reg reset=1; + reg [3:0] s_awid=0,s_arid=0; + reg [31:0] s_awaddr=0,s_araddr=0; + reg [7:0] s_awlen=0,s_arlen=0; + reg [2:0] s_awsize=0,s_arsize=0; + reg [1:0] s_awburst=1,s_arburst=1; + reg s_awvalid=0,s_arvalid=0,s_wvalid=0,s_wlast=0,s_bready=0,s_rready=0; + wire s_awready,s_arready,s_wready; + reg [127:0] s_wdata=0;reg [15:0] s_wstrb=0; + wire [3:0] s_bid,s_rid;wire [1:0] s_bresp,s_rresp; + wire s_bvalid,s_rvalid,s_rlast;wire [127:0] s_rdata; + wire [3:0] m_awid,m_arid; + wire [27:0] m_awaddr,m_araddr;wire [7:0] m_awlen,m_arlen; + wire [2:0] m_awsize,m_arsize;wire [1:0] m_awburst,m_arburst; + wire m_awvalid,m_arvalid,m_wvalid,m_wlast,m_bready,m_rready; + wire m_awready,m_arready,m_wready; + wire [127:0] m_wdata;wire [15:0] m_wstrb; + wire [3:0] m_bid,m_rid;wire [1:0] m_bresp,m_rresp; + wire m_bvalid,m_rvalid,m_rlast;wire [127:0] m_rdata; + reg [7:0] expected[0:4095]; + integer beats=0; + wire [3:0] ui_awid; + wire [27:0] ui_awaddr; + wire [7:0] ui_awlen; + wire [2:0] ui_awsize; + wire [1:0] ui_awburst; + wire ui_awvalid; + wire ui_awready; + wire [127:0] ui_wdata; + wire [15:0] ui_wstrb; + wire ui_wlast; + wire ui_wvalid; + wire ui_wready; + wire [3:0] ui_bid; + wire [1:0] ui_bresp; + wire ui_bvalid; + wire ui_bready; + wire [3:0] ui_arid; + wire [27:0] ui_araddr; + wire [7:0] ui_arlen; + wire [2:0] ui_arsize; + wire [1:0] ui_arburst; + wire ui_arvalid; + wire ui_arready; + wire [3:0] ui_rid; + wire [127:0] ui_rdata; + wire [1:0] ui_rresp; + wire ui_rlast; + wire ui_rvalid; + wire ui_rready; + toy_axi_cdc memory_cdc ( + .s_axi_aclk(clk), + .s_axi_aresetn(!reset), + .m_axi_aclk(ui_clk), + .m_axi_aresetn(!reset), + .s_axi_awid(m_awid), + .s_axi_awaddr(m_awaddr), + .s_axi_awlen(m_awlen), + .s_axi_awsize(m_awsize), + .s_axi_awburst(m_awburst), + .s_axi_awvalid(m_awvalid), + .s_axi_awready(m_awready), + .s_axi_wdata(m_wdata), + .s_axi_wstrb(m_wstrb), + .s_axi_wlast(m_wlast), + .s_axi_wvalid(m_wvalid), + .s_axi_wready(m_wready), + .s_axi_bid(m_bid), + .s_axi_bresp(m_bresp), + .s_axi_bvalid(m_bvalid), + .s_axi_bready(m_bready), + .s_axi_arid(m_arid), + .s_axi_araddr(m_araddr), + .s_axi_arlen(m_arlen), + .s_axi_arsize(m_arsize), + .s_axi_arburst(m_arburst), + .s_axi_arvalid(m_arvalid), + .s_axi_arready(m_arready), + .s_axi_rid(m_rid), + .s_axi_rdata(m_rdata), + .s_axi_rresp(m_rresp), + .s_axi_rlast(m_rlast), + .s_axi_rvalid(m_rvalid), + .s_axi_rready(m_rready), + .s_axi_awlock(1'b0), + .s_axi_arlock(1'b0), + .s_axi_awcache(4'b0011), + .s_axi_arcache(4'b0011), + .s_axi_awprot(3'd0), + .s_axi_arprot(3'd0), + .s_axi_awqos(4'd0), + .s_axi_arqos(4'd0), + .s_axi_awregion(4'd0), + .s_axi_arregion(4'd0), + .m_axi_awid(ui_awid), + .m_axi_awaddr(ui_awaddr), + .m_axi_awlen(ui_awlen), + .m_axi_awsize(ui_awsize), + .m_axi_awburst(ui_awburst), + .m_axi_awvalid(ui_awvalid), + .m_axi_awready(ui_awready), + .m_axi_wdata(ui_wdata), + .m_axi_wstrb(ui_wstrb), + .m_axi_wlast(ui_wlast), + .m_axi_wvalid(ui_wvalid), + .m_axi_wready(ui_wready), + .m_axi_bid(ui_bid), + .m_axi_bresp(ui_bresp), + .m_axi_bvalid(ui_bvalid), + .m_axi_bready(ui_bready), + .m_axi_arid(ui_arid), + .m_axi_araddr(ui_araddr), + .m_axi_arlen(ui_arlen), + .m_axi_arsize(ui_arsize), + .m_axi_arburst(ui_arburst), + .m_axi_arvalid(ui_arvalid), + .m_axi_arready(ui_arready), + .m_axi_rid(ui_rid), + .m_axi_rdata(ui_rdata), + .m_axi_rresp(ui_rresp), + .m_axi_rlast(ui_rlast), + .m_axi_rvalid(ui_rvalid), + .m_axi_rready(ui_rready), + .m_axi_awlock(), + .m_axi_arlock(), + .m_axi_awcache(), + .m_axi_arcache(), + .m_axi_awprot(), + .m_axi_arprot(), + .m_axi_awqos(), + .m_axi_arqos(), + .m_axi_awregion(), + .m_axi_arregion() + ); + axi_fullwidth dut(.*); + axi_smoke_memory #(.ADDR_BITS(28),.BASE(0),.CAPACITY(4096)) memory ( + .clock(ui_clk),.reset(reset), + .aw_ready(ui_awready),.aw_valid(ui_awvalid),.aw_bits_id(ui_awid),.aw_bits_addr(ui_awaddr), + .aw_bits_len(ui_awlen),.aw_bits_size(ui_awsize),.aw_bits_burst(ui_awburst), + .w_ready(ui_wready),.w_valid(ui_wvalid),.w_bits_data(ui_wdata),.w_bits_strb(ui_wstrb),.w_bits_last(ui_wlast), + .b_ready(ui_bready),.b_valid(ui_bvalid),.b_bits_id(ui_bid),.b_bits_resp(ui_bresp), + .ar_ready(ui_arready),.ar_valid(ui_arvalid),.ar_bits_id(ui_arid),.ar_bits_addr(ui_araddr), + .ar_bits_len(ui_arlen),.ar_bits_size(ui_arsize),.ar_bits_burst(ui_arburst), + .r_ready(ui_rready),.r_valid(ui_rvalid),.r_bits_id(ui_rid),.r_bits_data(ui_rdata),.r_bits_resp(ui_rresp),.r_bits_last(ui_rlast)); + always @(posedge clk) begin + if(m_awvalid && m_awready && (m_awaddr[3:0]!=0 || m_awsize!=4 || m_awlen!=0)) $fatal(1,"MIG narrow write"); + if(m_arvalid && m_arready && (m_araddr[3:0]!=0 || m_arsize!=4 || m_arlen!=0)) $fatal(1,"MIG narrow read"); + end + task automatic write_burst(input integer address,z,n,id,input bit fixed_addr,input [1:0] response); + integer a; + begin + @(negedge clk);s_awaddr=address;s_awsize=z;s_awlen=n-1;s_awid=id;s_awburst=!fixed_addr;s_awvalid=1; + do @(posedge clk);while(!s_awready); + @(negedge clk);s_awvalid=0; + for(integer b=0;b 0} { +## add_wave / +## set_property needs_save false [current_wave_config] +## } else { +## send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." +## } +## } +## run all +WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information. +WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information. +WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information. +WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information. +WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information. +PASS BOARD_CDC: sizes 8..128 bits, INCR/FIXED, strobes, concurrent R/W, stalls, IDs, range/4KiB rejection; read beats=90 +$finish called at time : 100800 ns : File "/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cdc/tb_board_cdc.sv" Line 221 +INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_board_cdc_behav' loaded. +INFO: [USF-XSim-97] XSim simulation ran for all +launch_simulation: Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1581.262 ; gain = 115.785 ; free physical = 119468 ; free virtual = 491146 +# close_sim +INFO: [Simtcl 6-16] Simulation closed +# exit +INFO: [Common 17-206] Exiting Vivado at Tue Oct 13 01:53:48 2026... diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-cpu/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-cpu/RESULT.json new file mode 100644 index 0000000..8849267 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-cpu/RESULT.json @@ -0,0 +1,9 @@ +{ + "result": "PASS", + "test": "cpu", + "binary_sha256": "3bbf33f7bf2b6bb0f3888ab4a649a11272de3f74458f6ea36b266f9670df75f5", + "original_cpu_oracle": true, + "ddr_phy_simulated": false, + "physical_linux_boot_tested": false, + "cycles": 709434 +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-cpu/compile.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-cpu/compile.log new file mode 100644 index 0000000..e7fcd3c --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-cpu/compile.log @@ -0,0 +1,2193 @@ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 31 | module NonSyncResetSynchronizerPrimitiveShiftReg_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ + ... For warning description see https://verilator.org/warn/TIMESCALEMOD?v=5.050 + ... Use "/* verilator lint_off TIMESCALEMOD */" and lint_on around source to disable this message. +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:48:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 48 | module SynchronizerShiftReg_w1_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:61:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 61 | module IntSyncAsyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:74:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 74 | module AsyncResetRegVec_w1_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 103 | module IntSyncCrossingSource_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:118:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 118 | module FixedClockBroadcast_3( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:139:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 139 | module TLMonitor( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:987:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 987 | module TLMonitor_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:2434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 2434 | module TLXbar_sbus_i2_o3_a32d128s3k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:3195:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3195 | module TLMonitor_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4151 | module Repeater_TLBundleA_a28d128s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4218 | module TLWidthWidget16( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4386 | module TLInterconnectCoupler_sbus_to_bus_named_cbus( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4478:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4478 | module ram_2x58( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4497:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4497 | module Queue2_AXI4BundleAW( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4581:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4581 | module ram_2x73( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4600:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4600 | module Queue2_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4657:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4657 | module ram_2x4( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4676:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4676 | module Queue2_AXI4BundleB( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4729:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4729 | module Queue2_AXI4BundleAR( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4813:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4813 | module ram_2x69( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4832:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4832 | module Queue2_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4891:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4891 | module AXI4Buffer( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5067:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5067 | module ram_2x8( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5086:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5086 | module Queue2_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5143:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5143 | module Queue1_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5178 | module AXI4UserYanker( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5540:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5540 | module ram_8x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5559:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5559 | module Queue8_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5631 | module AXI4Deinterleaver( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:6073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6073 | module AXI4IdIndexer( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:6219:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6219 | module TLMonitor_3( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7048:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7048 | module Queue1_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7082:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7082 | module Queue1_AXI4BundleARW( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7148:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7148 | module TLToAXI4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7529:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7529 | module TLMonitor_4( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8396:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8396 | module Repeater_TLBundleA_a31d128s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8463 | module TLWidthWidget16_2( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8623:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8623 | module TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:9400:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 9400 | module SystemBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10050 | module FixedClockBroadcast_4( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10073 | module TLMonitor_5( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10975:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10975 | module TLXbar_cbus_out_i1_o4_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:11288:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +11288 | module TLMonitor_6( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12202:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12202 | module ram_2x114( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12221 | module Queue2_TLBundleA_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12301 | module ram_2x79( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12320:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12320 | module Queue2_TLBundleD_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12399:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12399 | module TLBuffer_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12534:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12534 | module TLMonitor_7( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:13449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13449 | module TLAtomicAutomata_cbus( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:13973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13973 | module TLMonitor_8( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14799 | module Queue1_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14846:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14846 | module TLError( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14953 | module TLMonitor_9( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15857 | module ram_2x100( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15876:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15876 | module Queue2_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15955:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15955 | module Queue2_TLBundleD_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16028 | module TLBuffer_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16155 | module ErrorDeviceWrapper( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16258 | module TLMonitor_10( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17017:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17017 | module Repeater_TLBundleA_a26d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17081:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17081 | module TLFragmenter_CLINT( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17261:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17261 | module TLInterconnectCoupler_cbus_to_clint( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17336:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17336 | module TLMonitor_11( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18106:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18106 | module Repeater_TLBundleA_a28d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18170:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18170 | module TLFragmenter_PLIC( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18350 | module TLInterconnectCoupler_cbus_to_plic( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18425:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18425 | module TLMonitor_12( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19040 | module Repeater_TLBundleA_a17d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19104:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19104 | module TLFragmenter_bootrom( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19263:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19263 | module TLInterconnectCoupler_cbus_to_bootrom( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19330:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19330 | module PeripheryBus_cbus( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19882 | module TLMonitor_13( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20610:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20610 | module ProbePicker( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20688:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20688 | module ram_2x10( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20707:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20707 | module Queue2_BundleMap_6( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20764:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20764 | module AXI4UserYanker_1( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:21713:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21713 | module AXI4IdIndexer_1( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:21859:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21859 | module TLMonitor_14( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22587:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22587 | module Queue1_AXI4BundleW_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22621 | module Queue1_AXI4BundleARW_1( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22687:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22687 | module TLToAXI4_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:23555:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +23555 | module TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:24031:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24031 | module MemoryBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:24349:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24349 | module TLMonitor_15( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25732:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25732 | module BroadcastFilter( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25756:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25756 | module ram_4x144( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25775:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25775 | module Queue4_TLBroadcastData( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25828:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25828 | module TLBroadcastTracker( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25964:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25964 | module TLBroadcastTracker_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:26100:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26100 | module TLBroadcast( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:26686:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26686 | module TLMonitor_16( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27414 | module BankBinder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27491:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27491 | module CoherenceManagerWrapper( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27669:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27669 | module TLMonitor_17( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29229:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29229 | module TLMonitor_18( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29635:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29635 | module TLXbar_MasterXbar_BBTile_i2_o1_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29898 | module IntXbar_i4_o1( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29918:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29918 | module WritebackUnit( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30014:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30014 | module ProbeUnit( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30154:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30154 | module Arbiter1_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30168:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30168 | module Arbiter1_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30191 | module Arbiter1_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30214 | module Arbiter1_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30249:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30249 | module Arbiter1_Bool( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30258 | module ram_16x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30277:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30277 | module Queue16_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30360:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30360 | module Queue1_TLBundleE_a32d128s1k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30388:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30388 | module MSHR( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30835:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30835 | module Arbiter1_HellaCacheResp( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30879:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30879 | module IOMSHR( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31790:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31790 | module sdq_17x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31809 | module MSHRFile( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32350 | module OptimizationBarrier_TLBEntryData( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32406:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32406 | module PMPChecker_s3( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32691:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32691 | module PMAChecker( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32731:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32731 | module DTLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:35923:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35923 | module L1MetadataArray( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:35990:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35990 | module Arbiter5_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36023:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36023 | module Arbiter2_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36055 | module DataArray( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36151 | module Arbiter4_L1DataReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36180:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36180 | module Arbiter2_L1DataWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36206:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36206 | module AMOALU( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36248:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36248 | module MaxPeriodFibonacciLFSR( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36342:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36342 | module Arbiter2_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36377:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36377 | module NonBlockingDCache( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:37660:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37660 | module ICache( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:37914:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37914 | module ShiftQueue( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:38054:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38054 | module PMPChecker_s2( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:38215:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38215 | module ITLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:41129:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41129 | module Frontend( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:41494:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41494 | module TLMonitor_19( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:42301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +42301 | module TLMonitor_20( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43108:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43108 | module TLXbar_i2_o1_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43343 | module TLMonitor_21( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43851:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43851 | module ram_2x116( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43870:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43870 | module Queue2_TLBundleA_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43947:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43947 | module ram_2x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43966:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43966 | module Queue2_TLBundleD_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44045:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44045 | module TLBuffer_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44158:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44158 | module TLMonitor_22( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44783 | module TLBuffer_a32d64s1k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44892:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44892 | module TLMonitor_23( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:45699:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45699 | module Repeater_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:45766:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45766 | module TLWidthWidget8_4( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46074:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46074 | module TLMonitor_24( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46882 | module ram_2x117( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46901:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46901 | module Queue2_TLBundleA_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46981:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46981 | module ram_2x78( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47000:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47000 | module Queue2_TLBundleD_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47079:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47079 | module TLBuffer_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47214 | module HellaCacheArbiter( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47381 | module Arbiter3_Valid_PTWReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47419:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47419 | module OptimizationBarrier_UInt( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47427 | module OptimizationBarrier_PTE( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47459 | module PTW( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:48434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +48434 | module FPUDecoder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49794:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49794 | module CompareRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49824:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49824 | module RecFNToIN_e11_s53_i64( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49873:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49873 | module RecFNToIN_e11_s53_i32( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49912:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49912 | module FPToInt( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50375:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50375 | module RoundAnyRawFNToRecFN_ie7_is64_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50410:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50410 | module PipelinedINToRecFN( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50513:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50513 | module RoundAnyRawFNToRecFN_ie7_is64_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50539 | module PipelinedINToRecFN_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50614 | module RoundAnyRawFNToRecFN_ie7_is64_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50642:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50642 | module PipelinedINToRecFN_2( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50717 | module IntToFP( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51072:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51072 | module RoundAnyRawFNToRecFN_ie11_is53_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51199:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51199 | module RecFNToRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51221 | module RoundAnyRawFNToRecFN_ie11_is53_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51321:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51321 | module RecFNToRecFN_1( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51343 | module FPToFP( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51469:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51469 | module MulAddRecFNToRaw_preMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51569 | module MulAddRecFNToRaw_postMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51822:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51822 | module RoundAnyRawFNToRecFN_ie11_is55_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51953 | module RoundAnyRawFNToRecFN_ie11_is55_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52060:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52060 | module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52194:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52194 | module SharedMulAddRecFNPipe( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52551:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52551 | module FPUSharedFMAPipe( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52682:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52682 | module DivSqrtRawFN_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52852:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52852 | module DivSqrtRecFMToRaw_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52907:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52907 | module RoundAnyRawFNToRecFN_ie5_is13_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53039:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53039 | module RoundRawFNToRecFN_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53068:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53068 | module DivSqrtRecFM_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53128:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53128 | module DivSqrtRawFN_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53297:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53297 | module DivSqrtRecFMToRaw_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53352:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53352 | module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53456:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53456 | module RoundRawFNToRecFN_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53485:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53485 | module DivSqrtRecFM_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53545:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53545 | module DivSqrtRawFN_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53715:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53715 | module DivSqrtRecFMToRaw_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53770:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53770 | module RoundRawFNToRecFN_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53799 | module DivSqrtRecFM_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53860:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53860 | module regfile_32x65( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53905:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53905 | module FPU( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:54820:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +54820 | module RVCExpander( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:55183:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55183 | module IBuf( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:55307:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55307 | module CSRFile( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:57223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57223 | module RocketALU( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:57809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57809 | module MulDiv( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:58107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58107 | module Arbiter3_LLWB( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:58125:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58125 | module rf_31x64( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:58149:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58149 | module RocketBB( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62838:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62838 | module GlobalDecoder( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62928:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62928 | module BankAliasTable( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:64252:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64252 | module BankScoreboard( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:64627:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64627 | module GlobalROB( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68674:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68674 | module Arbiter3_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68717 | module ram_16x4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68736:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68736 | module Queue16_UInt4( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68782:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68782 | module SubROB( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:69357:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69357 | module Arbiter1_SubRobRow( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:69722:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69722 | module GlobalScheduler( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:70973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +70973 | module BootRom( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:71013:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71013 | module Frontend_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:71637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71637 | module PE( + | ^~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:71656:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71656 | module AlwaysOutTransposer( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72411:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72411 | module MacUnit( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72426:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72426 | module PE_64( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72524:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72524 | module Tile( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72571:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72571 | module Mesh( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76050 | module TagQueue( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76191 | module ram_6x7( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76210:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76210 | module Queue6_TagWithIdAndTotalRows( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76271:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76271 | module MeshWithDelays( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77318:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77318 | module ram_data_8x64( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77337 | module Queue8_SramReadResp( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77385:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77385 | module GemminiExCtrl( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79354:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79354 | module LoopMatmulUnroller( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79637 | module LoopConvAddrGen( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79690:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79690 | module LoopConvUnroller( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:80113:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80113 | module LoopCmdEncoder( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:80402:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80402 | module Arbiter2_LoopCmd( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:80598:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80598 | module GemminiBall( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:81783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81783 | module RRArbiter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:81857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81857 | module CmdRouter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:81985:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81985 | module BallCyclePMC( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:82095:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82095 | module BBus( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:82898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82898 | module BallDomainDecoder( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83028 | module ram_4x281( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83047:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83047 | module Queue4_BallReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83178 | module Arbiter1_BallRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83198:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83198 | module BallReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83328:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83328 | module BallDomain( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84141:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84141 | module MemDomainDecoder( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84300:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84300 | module ram_4x158( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84319:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84319 | module Queue4_MemReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84421:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84421 | module Arbiter3_MemRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84463 | module MemReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84631 | module MemLoader( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84869:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84869 | module MemStorer( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85122:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85122 | module MemCyclePMC( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85241:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85241 | module TLB( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85621 | module RRArbiter_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85649:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85649 | module BBTLBCluster( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85777 | module StreamReader( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86142:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86142 | module StreamWriter( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86223 | module ZeroLineGenerator( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86264:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86264 | module MemConfiger( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86433:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86433 | module RRArbiter_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86465:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86465 | module MemGroupQueryArbiter( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86543:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86543 | module MemFrontend( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87160 | module MemMidend( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87621 | module SramBank( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87672:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87672 | module AccPipe( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87781 | module PrivateMemBackend( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:90777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +90777 | module MemBackend( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:91055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91055 | module MemDomain( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:91973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91973 | module Queue1_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92008:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92008 | module GpDomain( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92040 | module ram_8x21( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92059 | module Queue8_BuckyballAccelerator_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92123:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92123 | module BuckyballAccelerator( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93569 | module Queue3_UInt2( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93614 | module SimpleHellaCacheIFReplayQueue( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93667:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93667 | module Arbiter2_HellaCacheReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93678:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93678 | module SimpleHellaCacheIF( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93768:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93768 | module BarrierUnit( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93785:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93785 | module BBTile( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:95579:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +95579 | module TLMonitor_25( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:96427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +96427 | module TLMonitor_26( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98184:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98184 | module ram_2x189( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98203:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98203 | module Queue2_TLBundleA_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98283:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98283 | module ram_2x142( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98302:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98302 | module Queue2_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98381 | module Queue2_TLBundleA_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98459 | module Queue2_TLBundleD_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98539 | module ram_2x60( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98558:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98558 | module Queue2_TLBundleB_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98622:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98622 | module ram_2x173( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98641:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98641 | module Queue2_TLBundleC_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98716:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98716 | module ram_sink_2x1( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98735:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98735 | module Queue2_TLBundleE_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98781 | module TLBuffer_a32d128s2k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99162:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99162 | module IntSyncSyncCrossingSink_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99173:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99173 | module IntSyncSyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99181:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99181 | module TilePRCIDomain( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99589:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99589 | module BundleBridgeNexus_UInt1_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99597:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99597 | module TLMonitor_27( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100216:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100216 | module CLINT( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100337 | module AsyncResetRegVec_w2_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100366:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100366 | module IntSyncCrossingSource_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100386 | module CLINTClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100449 | module TLMonitor_28( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101080:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101080 | module LevelGateway( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101099:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101099 | module PLICFanIn( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101111:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101111 | module Queue1_RegMapperInput_i23_m8( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101160 | module TLPLIC( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101389:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101389 | module PLICClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101452:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101452 | module TLMonitor_29( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101973 | module TLROM( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:102530:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102530 | module bootromClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:102569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102569 | module ToyLinuxSystem( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103817:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103817 | module ToyLinuxChip( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103984:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103984 | module tag_array( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104007:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104007 | module array_0_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104034:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104034 | module array_0_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104059 | module array_2_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104084:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104084 | module array_2_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104109:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104109 | module bbtile_icache_tag_array( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104132:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104132 | module bbtile_icache_data_arrays_0( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104155 | module bbtile_icache_data_arrays_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104176:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104176 | module bbtile_icache_data_arrays_2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104197:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104197 | module bbtile_icache_data_arrays_3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104218 | module robOperands( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104243:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104243 | module sram( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104268:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104268 | module mem( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104301 | module plusarg_reader #( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104326:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104326 | module ITraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104404:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104404 | module FpgaDspMac(input [7:0] a, b, input [19:0] c, output [19:0] y); + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104414 | module PMCTraceDPI( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104464:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104464 | module MemPMCTraceDPI( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104514:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104514 | module MTraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:1:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 1 | module tag_array_ext( input [4:0] RW0_addr, + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 19 | module array_0_0_ext( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:37:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 37 | module bbtile_icache_tag_array_ext( input [5:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:55:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 55 | module bbtile_icache_data_arrays_0_ext( input [7:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:73:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 73 | module robOperands_ext( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:90:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 90 | module sram_ext( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 107 | module mem_ext( input [9:0] RW0_addr, + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:3:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3 | module axi_smoke_memory #( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_tx.sv:27:15: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.transmitter' + 27 | count <= DIVISOR - 1; + | ^~ + ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=5.050 + ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_tx.sv:32:13: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.transmitter' + 32 | count <= DIVISOR - 1; + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_rx.sv:23:55: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.receiver' + 23 | IDLE: if (!rx_sync) begin state <= START; count <= DIVISOR/2 - 1; end + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_rx.sv:26:57: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.receiver' + 26 | else begin state <= DATA; bit_index <= 0; count <= DIVISOR - 1; end + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_rx.sv:29:46: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.receiver' + 29 | shift[bit_index] <= rx_sync; count <= DIVISOR - 1; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:32:43: Operator ADD expects 33 bits on the RHS, but RHS's VARREF 'length' generates 16 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 32 | wire [32:0] end_address = {1'b0,address}+length; + | ^ + ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=5.050 + ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:35:38: Operator ADD expects 32 bits on the RHS, but RHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 35 | wire [31:0] byte_address = address + cursor; + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:67:32: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's SHIFTR generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 67 | 11,12,13,14:tx_data=RAM_BYTES >> ((reply_index-11)*8); + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:68:32: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's SHIFTR generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 68 | 15,16,17,18:tx_data=CLOCK_HZ >> ((reply_index-15)*8); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:73:28: Operator EQ expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 73 | else if(reply_index==7+reply_length) tx_data=crc[7:0]; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:64:23: Operator LT expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 64 | if(reply_index<7+reply_length) begin + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:119:20: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 119 | if(cursor+1==length) state<=CRC0; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:144:25: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 144 | else if(cursor+1==length) begin image_loaded<=1;state<=REPLY;end + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:152:20: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 152 | if(cursor+1==length) state<=REPLY; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:157:43: Operator LT expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 157 | if(reply_index>=2 && reply_index<7+reply_length) crc<=crc_next(crc,tx_data); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:158:25: Operator EQ expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 158 | if(reply_index==8+reply_length) state<=DRAIN; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:87:37: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'timeout_count' generates 22 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 87 | if((receiving && timeout_count==RX_TIMEOUT-1) || (receiving && rx_error)) begin + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:52:20: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'addr' generates 28 bits. + : ... note: In instance 'tb_board_cpu.memory' + 52 | offset=(addr & ~(LANES-1))-BASE; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:78:28: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'write_addr' generates 28 bits. + : ... note: In instance 'tb_board_cpu.memory' + 78 | offset=(write_addr & ~(LANES-1))-BASE; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:86:26: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'h600d600d' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 86 | if (w_bits_data==64'h600d600d) begin + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:91:66: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 91 | $fatal(1,"CPU smoke failed at stage %0d",w_bits_data & 64'hffff); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:90:28: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff0000' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:90:43: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'hbad00000' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^~ +make: Entering directory '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/obj' +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_timing.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_timing.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_threads.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_threads.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb_board_cpu__pch.h -o Vtb_board_cpu__pch.h.fast.gch +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb_board_cpu__pch.h -o Vtb_board_cpu__pch.h.slow.gch +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__0.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__1.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__2.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__3.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__4.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__5.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__6.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__7.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__8.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__9.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu__main.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu__ConstPool__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__1__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__2__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__3__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu__Syms__Slow.cpp +g++ verilated.o verilated_timing.o verilated_threads.o Vtb_board_cpu__ALL.a -pthread -lpthread -latomic -o Vtb_board_cpu +rm Vtb_board_cpu__ALL.verilator_deplist.tmp +make: Leaving directory '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/obj' +- V e r i l a t i o n R e p o r t: Verilator 5.050 2026-07-01 rev v5.050 +- Verilator: Built from 46.540 MB sources in 354 modules, into 26.450 MB in 19 C++ files needing 0.019 MB +- Verilator: Walltime 14.551 s (elab=0.735, cvt=3.978, bld=9.128); cpu 5.710 s on 8 threads; allocated 437.312 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-cpu/simulation.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-cpu/simulation.log new file mode 100644 index 0000000..44e7b38 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-cpu/simulation.log @@ -0,0 +1,5 @@ +PASS CPU Sv39/FPU/AMO/cache/interrupt through board AXI/SCU cycles=709434 +- /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-cpu/tb_board_cpu.sv:56: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 7ms; walltime 6.002 s; speed 1.182 ms/s +- Verilator: cpu 6.001 s on 1 threads; allocated 8 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-cpu/smoke.bin b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-cpu/smoke.bin new file mode 100644 index 0000000..f634740 Binary files /dev/null and b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-cpu/smoke.bin differ diff --git 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b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-cpu/tb_board_cpu.sv @@ -0,0 +1,92 @@ +`timescale 1ns/1ps +module tb_board_cpu; + reg clk=0;always #5 clk=~clk; + reg reset=1,uart_rx_in=1; + wire uart_tx_out; + wire cpu_run; + wire exited; + wire loader_error; + wire [31:0] exit_code; + wire [3:0] ddr_awid; + wire [27:0] ddr_awaddr; + wire [7:0] ddr_awlen; + wire [2:0] ddr_awsize; + wire [1:0] ddr_awburst; + wire ddr_awvalid; + wire ddr_awready; + wire [127:0] ddr_wdata; + wire [15:0] ddr_wstrb; + wire ddr_wlast; + wire ddr_wvalid; + wire ddr_wready; + wire [3:0] ddr_bid; + wire [1:0] ddr_bresp; + wire ddr_bvalid; + wire ddr_bready; + wire [3:0] ddr_arid; + wire [27:0] ddr_araddr; + wire [7:0] ddr_arlen; + wire [2:0] ddr_arsize; + wire [1:0] ddr_arburst; + wire ddr_arvalid; + wire ddr_arready; + wire [3:0] ddr_rid; + wire [127:0] ddr_rdata; + wire [1:0] ddr_rresp; + wire ddr_rlast; + wire ddr_rvalid; + wire ddr_rready; + wire flash_miso; + wire flash_recovery; + wire flash_mosi; + wire flash_sck; + wire flash_cs_n; + toy_a7_platform platform(.*); + initial begin + repeat(10) @(negedge clk); force platform.loader.cpu_run=1;reset=0;end + integer cycles=0; + always @(posedge clk) if(!reset) begin + cycles<=cycles+1; + if(platform.memory_aw_valid && platform.memory_aw_bits_lock) $fatal(1,"Unexpected AXI exclusive write"); + if(platform.memory_ar_valid && platform.memory_ar_bits_lock) $fatal(1,"Unexpected AXI exclusive read"); + if(ddr_awvalid && ddr_awready && (ddr_awsize!=4 || ddr_awlen!=0)) $fatal(1,"Narrow DDR write"); + if(ddr_arvalid && ddr_arready && (ddr_arsize!=4 || ddr_arlen!=0)) $fatal(1,"Narrow DDR read"); + if(exited && (exit_code & 32'hffff0000)==32'hbad00000) $fatal(1,"CPU oracle failed stage=%h",exit_code); + if(exited && exit_code==32'h600d600d) begin + $display("PASS CPU Sv39/FPU/AMO/cache/interrupt through board AXI/SCU cycles=%0d",cycles);$finish;end + if(cycles>4000000) $fatal(1,"Board CPU watchdog"); + end + axi_smoke_memory #(.ADDR_BITS(28),.BASE(0),.CAPACITY(262144),.IMAGE("smoke.hex")) memory ( + .clock(clk), + .reset(reset), + .aw_bits_id(ddr_awid), + .aw_bits_addr(ddr_awaddr), + .aw_bits_len(ddr_awlen), + .aw_bits_size(ddr_awsize), + .aw_bits_burst(ddr_awburst), + .aw_valid(ddr_awvalid), + .aw_ready(ddr_awready), + .w_bits_data(ddr_wdata), + .w_bits_strb(ddr_wstrb), + .w_bits_last(ddr_wlast), + .w_valid(ddr_wvalid), + .w_ready(ddr_wready), + .b_bits_id(ddr_bid), + .b_bits_resp(ddr_bresp), + .b_valid(ddr_bvalid), + .b_ready(ddr_bready), + .ar_bits_id(ddr_arid), + .ar_bits_addr(ddr_araddr), + .ar_bits_len(ddr_arlen), + .ar_bits_size(ddr_arsize), + .ar_bits_burst(ddr_arburst), + .ar_valid(ddr_arvalid), + .ar_ready(ddr_arready), + .r_bits_id(ddr_rid), + .r_bits_data(ddr_rdata), + .r_bits_resp(ddr_rresp), + .r_bits_last(ddr_rlast), + .r_valid(ddr_rvalid), + .r_ready(ddr_rready) + ); +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-dma/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-dma/RESULT.json new file mode 100644 index 0000000..7f02844 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-dma/RESULT.json @@ -0,0 +1,9 @@ +{ + "result": "PASS", + "test": "dma", + "binary_sha256": "082965476d4dcc98cc556b8f79fa2fdf659cea501665e207d04349d40469e9d2", + "original_cpu_oracle": true, + "ddr_phy_simulated": false, + "physical_linux_boot_tested": false, + "cycles": 1914839 +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-dma/compile.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-dma/compile.log new file mode 100644 index 0000000..090105d --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-dma/compile.log @@ -0,0 +1,2193 @@ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 31 | module NonSyncResetSynchronizerPrimitiveShiftReg_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ + ... For warning description see https://verilator.org/warn/TIMESCALEMOD?v=5.050 + ... Use "/* verilator lint_off TIMESCALEMOD */" and lint_on around source to disable this message. +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:48:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 48 | module SynchronizerShiftReg_w1_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:61:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 61 | module IntSyncAsyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:74:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 74 | module AsyncResetRegVec_w1_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 103 | module IntSyncCrossingSource_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:118:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 118 | module FixedClockBroadcast_3( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:139:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 139 | module TLMonitor( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:987:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 987 | module TLMonitor_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:2434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 2434 | module TLXbar_sbus_i2_o3_a32d128s3k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:3195:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3195 | module TLMonitor_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4151 | module Repeater_TLBundleA_a28d128s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4218 | module TLWidthWidget16( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4386 | module TLInterconnectCoupler_sbus_to_bus_named_cbus( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4478:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4478 | module ram_2x58( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4497:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4497 | module Queue2_AXI4BundleAW( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4581:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4581 | module ram_2x73( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4600:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4600 | module Queue2_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4657:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4657 | module ram_2x4( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4676:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4676 | module Queue2_AXI4BundleB( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4729:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4729 | module Queue2_AXI4BundleAR( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4813:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4813 | module ram_2x69( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4832:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4832 | module Queue2_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4891:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4891 | module AXI4Buffer( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5067:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5067 | module ram_2x8( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5086:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5086 | module Queue2_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5143:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5143 | module Queue1_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5178 | module AXI4UserYanker( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5540:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5540 | module ram_8x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5559:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5559 | module Queue8_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5631 | module AXI4Deinterleaver( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:6073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6073 | module AXI4IdIndexer( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:6219:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6219 | module TLMonitor_3( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7048:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7048 | module Queue1_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7082:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7082 | module Queue1_AXI4BundleARW( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7148:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7148 | module TLToAXI4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7529:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7529 | module TLMonitor_4( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8396:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8396 | module Repeater_TLBundleA_a31d128s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8463 | module TLWidthWidget16_2( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8623:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8623 | module TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:9400:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 9400 | module SystemBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10050 | module FixedClockBroadcast_4( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10073 | module TLMonitor_5( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10975:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10975 | module TLXbar_cbus_out_i1_o4_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:11288:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +11288 | module TLMonitor_6( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12202:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12202 | module ram_2x114( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12221 | module Queue2_TLBundleA_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12301 | module ram_2x79( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12320:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12320 | module Queue2_TLBundleD_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12399:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12399 | module TLBuffer_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12534:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12534 | module TLMonitor_7( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:13449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13449 | module TLAtomicAutomata_cbus( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:13973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13973 | module TLMonitor_8( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14799 | module Queue1_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14846:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14846 | module TLError( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14953 | module TLMonitor_9( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15857 | module ram_2x100( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15876:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15876 | module Queue2_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15955:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15955 | module Queue2_TLBundleD_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16028 | module TLBuffer_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16155 | module ErrorDeviceWrapper( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16258 | module TLMonitor_10( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17017:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17017 | module Repeater_TLBundleA_a26d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17081:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17081 | module TLFragmenter_CLINT( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17261:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17261 | module TLInterconnectCoupler_cbus_to_clint( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17336:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17336 | module TLMonitor_11( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18106:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18106 | module Repeater_TLBundleA_a28d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18170:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18170 | module TLFragmenter_PLIC( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18350 | module TLInterconnectCoupler_cbus_to_plic( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18425:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18425 | module TLMonitor_12( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19040 | module Repeater_TLBundleA_a17d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19104:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19104 | module TLFragmenter_bootrom( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19263:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19263 | module TLInterconnectCoupler_cbus_to_bootrom( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19330:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19330 | module PeripheryBus_cbus( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19882 | module TLMonitor_13( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20610:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20610 | module ProbePicker( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20688:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20688 | module ram_2x10( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20707:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20707 | module Queue2_BundleMap_6( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20764:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20764 | module AXI4UserYanker_1( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:21713:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21713 | module AXI4IdIndexer_1( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:21859:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21859 | module TLMonitor_14( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22587:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22587 | module Queue1_AXI4BundleW_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22621 | module Queue1_AXI4BundleARW_1( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22687:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22687 | module TLToAXI4_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:23555:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +23555 | module TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:24031:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24031 | module MemoryBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:24349:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24349 | module TLMonitor_15( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25732:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25732 | module BroadcastFilter( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25756:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25756 | module ram_4x144( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25775:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25775 | module Queue4_TLBroadcastData( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25828:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25828 | module TLBroadcastTracker( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25964:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25964 | module TLBroadcastTracker_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:26100:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26100 | module TLBroadcast( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:26686:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26686 | module TLMonitor_16( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27414 | module BankBinder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27491:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27491 | module CoherenceManagerWrapper( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27669:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27669 | module TLMonitor_17( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29229:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29229 | module TLMonitor_18( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29635:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29635 | module TLXbar_MasterXbar_BBTile_i2_o1_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29898 | module IntXbar_i4_o1( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29918:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29918 | module WritebackUnit( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30014:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30014 | module ProbeUnit( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30154:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30154 | module Arbiter1_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30168:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30168 | module Arbiter1_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30191 | module Arbiter1_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30214 | module Arbiter1_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30249:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30249 | module Arbiter1_Bool( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30258 | module ram_16x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30277:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30277 | module Queue16_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30360:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30360 | module Queue1_TLBundleE_a32d128s1k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30388:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30388 | module MSHR( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30835:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30835 | module Arbiter1_HellaCacheResp( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30879:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30879 | module IOMSHR( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31790:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31790 | module sdq_17x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31809 | module MSHRFile( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32350 | module OptimizationBarrier_TLBEntryData( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32406:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32406 | module PMPChecker_s3( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32691:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32691 | module PMAChecker( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32731:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32731 | module DTLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:35923:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35923 | module L1MetadataArray( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:35990:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35990 | module Arbiter5_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36023:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36023 | module Arbiter2_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36055 | module DataArray( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36151 | module Arbiter4_L1DataReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36180:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36180 | module Arbiter2_L1DataWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36206:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36206 | module AMOALU( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36248:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36248 | module MaxPeriodFibonacciLFSR( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36342:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36342 | module Arbiter2_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36377:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36377 | module NonBlockingDCache( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:37660:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37660 | module ICache( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:37914:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37914 | module ShiftQueue( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:38054:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38054 | module PMPChecker_s2( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:38215:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38215 | module ITLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:41129:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41129 | module Frontend( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:41494:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41494 | module TLMonitor_19( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:42301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +42301 | module TLMonitor_20( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43108:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43108 | module TLXbar_i2_o1_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43343 | module TLMonitor_21( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43851:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43851 | module ram_2x116( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43870:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43870 | module Queue2_TLBundleA_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43947:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43947 | module ram_2x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43966:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43966 | module Queue2_TLBundleD_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44045:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44045 | module TLBuffer_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44158:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44158 | module TLMonitor_22( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44783 | module TLBuffer_a32d64s1k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44892:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44892 | module TLMonitor_23( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:45699:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45699 | module Repeater_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:45766:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45766 | module TLWidthWidget8_4( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46074:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46074 | module TLMonitor_24( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46882 | module ram_2x117( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46901:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46901 | module Queue2_TLBundleA_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46981:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46981 | module ram_2x78( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47000:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47000 | module Queue2_TLBundleD_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47079:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47079 | module TLBuffer_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47214 | module HellaCacheArbiter( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47381 | module Arbiter3_Valid_PTWReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47419:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47419 | module OptimizationBarrier_UInt( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47427 | module OptimizationBarrier_PTE( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47459 | module PTW( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:48434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +48434 | module FPUDecoder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49794:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49794 | module CompareRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49824:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49824 | module RecFNToIN_e11_s53_i64( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49873:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49873 | module RecFNToIN_e11_s53_i32( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49912:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49912 | module FPToInt( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50375:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50375 | module RoundAnyRawFNToRecFN_ie7_is64_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50410:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50410 | module PipelinedINToRecFN( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50513:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50513 | module RoundAnyRawFNToRecFN_ie7_is64_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50539 | module PipelinedINToRecFN_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50614 | module RoundAnyRawFNToRecFN_ie7_is64_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50642:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50642 | module PipelinedINToRecFN_2( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50717 | module IntToFP( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51072:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51072 | module RoundAnyRawFNToRecFN_ie11_is53_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51199:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51199 | module RecFNToRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51221 | module RoundAnyRawFNToRecFN_ie11_is53_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51321:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51321 | module RecFNToRecFN_1( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51343 | module FPToFP( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51469:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51469 | module MulAddRecFNToRaw_preMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51569 | module MulAddRecFNToRaw_postMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51822:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51822 | module RoundAnyRawFNToRecFN_ie11_is55_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51953 | module RoundAnyRawFNToRecFN_ie11_is55_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52060:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52060 | module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52194:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52194 | module SharedMulAddRecFNPipe( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52551:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52551 | module FPUSharedFMAPipe( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52682:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52682 | module DivSqrtRawFN_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52852:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52852 | module DivSqrtRecFMToRaw_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52907:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52907 | module RoundAnyRawFNToRecFN_ie5_is13_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53039:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53039 | module RoundRawFNToRecFN_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53068:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53068 | module DivSqrtRecFM_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53128:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53128 | module DivSqrtRawFN_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53297:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53297 | module DivSqrtRecFMToRaw_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53352:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53352 | module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53456:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53456 | module RoundRawFNToRecFN_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53485:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53485 | module DivSqrtRecFM_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53545:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53545 | module DivSqrtRawFN_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53715:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53715 | module DivSqrtRecFMToRaw_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53770:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53770 | module RoundRawFNToRecFN_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53799 | module DivSqrtRecFM_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53860:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53860 | module regfile_32x65( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53905:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53905 | module FPU( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:54820:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +54820 | module RVCExpander( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:55183:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55183 | module IBuf( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:55307:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55307 | module CSRFile( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:57223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57223 | module RocketALU( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:57809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57809 | module MulDiv( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:58107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58107 | module Arbiter3_LLWB( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:58125:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58125 | module rf_31x64( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:58149:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58149 | module RocketBB( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62838:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62838 | module GlobalDecoder( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62928:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62928 | module BankAliasTable( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:64252:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64252 | module BankScoreboard( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:64627:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64627 | module GlobalROB( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68674:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68674 | module Arbiter3_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68717 | module ram_16x4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68736:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68736 | module Queue16_UInt4( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68782:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68782 | module SubROB( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:69357:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69357 | module Arbiter1_SubRobRow( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:69722:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69722 | module GlobalScheduler( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:70973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +70973 | module BootRom( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:71013:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71013 | module Frontend_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:71637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71637 | module PE( + | ^~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:71656:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71656 | module AlwaysOutTransposer( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72411:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72411 | module MacUnit( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72426:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72426 | module PE_64( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72524:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72524 | module Tile( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72571:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72571 | module Mesh( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76050 | module TagQueue( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76191 | module ram_6x7( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76210:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76210 | module Queue6_TagWithIdAndTotalRows( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76271:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76271 | module MeshWithDelays( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77318:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77318 | module ram_data_8x64( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77337 | module Queue8_SramReadResp( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77385:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77385 | module GemminiExCtrl( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79354:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79354 | module LoopMatmulUnroller( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79637 | module LoopConvAddrGen( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79690:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79690 | module LoopConvUnroller( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:80113:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80113 | module LoopCmdEncoder( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:80402:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80402 | module Arbiter2_LoopCmd( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:80598:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80598 | module GemminiBall( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:81783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81783 | module RRArbiter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:81857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81857 | module CmdRouter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:81985:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81985 | module BallCyclePMC( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:82095:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82095 | module BBus( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:82898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82898 | module BallDomainDecoder( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83028 | module ram_4x281( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83047:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83047 | module Queue4_BallReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83178 | module Arbiter1_BallRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83198:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83198 | module BallReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83328:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83328 | module BallDomain( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84141:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84141 | module MemDomainDecoder( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84300:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84300 | module ram_4x158( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84319:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84319 | module Queue4_MemReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84421:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84421 | module Arbiter3_MemRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84463 | module MemReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84631 | module MemLoader( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84869:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84869 | module MemStorer( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85122:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85122 | module MemCyclePMC( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85241:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85241 | module TLB( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85621 | module RRArbiter_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85649:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85649 | module BBTLBCluster( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85777 | module StreamReader( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86142:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86142 | module StreamWriter( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86223 | module ZeroLineGenerator( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86264:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86264 | module MemConfiger( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86433:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86433 | module RRArbiter_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86465:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86465 | module MemGroupQueryArbiter( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86543:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86543 | module MemFrontend( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87160 | module MemMidend( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87621 | module SramBank( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87672:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87672 | module AccPipe( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87781 | module PrivateMemBackend( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:90777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +90777 | module MemBackend( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:91055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91055 | module MemDomain( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:91973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91973 | module Queue1_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92008:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92008 | module GpDomain( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92040 | module ram_8x21( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92059 | module Queue8_BuckyballAccelerator_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92123:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92123 | module BuckyballAccelerator( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93569 | module Queue3_UInt2( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93614 | module SimpleHellaCacheIFReplayQueue( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93667:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93667 | module Arbiter2_HellaCacheReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93678:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93678 | module SimpleHellaCacheIF( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93768:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93768 | module BarrierUnit( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93785:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93785 | module BBTile( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:95579:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +95579 | module TLMonitor_25( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:96427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +96427 | module TLMonitor_26( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98184:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98184 | module ram_2x189( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98203:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98203 | module Queue2_TLBundleA_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98283:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98283 | module ram_2x142( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98302:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98302 | module Queue2_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98381 | module Queue2_TLBundleA_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98459 | module Queue2_TLBundleD_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98539 | module ram_2x60( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98558:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98558 | module Queue2_TLBundleB_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98622:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98622 | module ram_2x173( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98641:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98641 | module Queue2_TLBundleC_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98716:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98716 | module ram_sink_2x1( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98735:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98735 | module Queue2_TLBundleE_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98781 | module TLBuffer_a32d128s2k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99162:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99162 | module IntSyncSyncCrossingSink_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99173:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99173 | module IntSyncSyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99181:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99181 | module TilePRCIDomain( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99589:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99589 | module BundleBridgeNexus_UInt1_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99597:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99597 | module TLMonitor_27( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100216:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100216 | module CLINT( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100337 | module AsyncResetRegVec_w2_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100366:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100366 | module IntSyncCrossingSource_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100386 | module CLINTClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100449 | module TLMonitor_28( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101080:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101080 | module LevelGateway( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101099:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101099 | module PLICFanIn( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101111:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101111 | module Queue1_RegMapperInput_i23_m8( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101160 | module TLPLIC( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101389:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101389 | module PLICClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101452:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101452 | module TLMonitor_29( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101973 | module TLROM( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:102530:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102530 | module bootromClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:102569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102569 | module ToyLinuxSystem( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103817:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103817 | module ToyLinuxChip( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103984:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103984 | module tag_array( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104007:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104007 | module array_0_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104034:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104034 | module array_0_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104059 | module array_2_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104084:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104084 | module array_2_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104109:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104109 | module bbtile_icache_tag_array( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104132:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104132 | module bbtile_icache_data_arrays_0( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104155 | module bbtile_icache_data_arrays_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104176:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104176 | module bbtile_icache_data_arrays_2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104197:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104197 | module bbtile_icache_data_arrays_3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104218 | module robOperands( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104243:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104243 | module sram( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104268:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104268 | module mem( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104301 | module plusarg_reader #( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104326:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104326 | module ITraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104404:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104404 | module FpgaDspMac(input [7:0] a, b, input [19:0] c, output [19:0] y); + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104414 | module PMCTraceDPI( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104464:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104464 | module MemPMCTraceDPI( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104514:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104514 | module MTraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:1:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 1 | module tag_array_ext( input [4:0] RW0_addr, + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 19 | module array_0_0_ext( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:37:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 37 | module bbtile_icache_tag_array_ext( input [5:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:55:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 55 | module bbtile_icache_data_arrays_0_ext( input [7:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:73:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 73 | module robOperands_ext( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:90:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 90 | module sram_ext( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 107 | module mem_ext( input [9:0] RW0_addr, + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:3:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3 | module axi_smoke_memory #( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_tx.sv:27:15: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.transmitter' + 27 | count <= DIVISOR - 1; + | ^~ + ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=5.050 + ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_tx.sv:32:13: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.transmitter' + 32 | count <= DIVISOR - 1; + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_rx.sv:23:55: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.receiver' + 23 | IDLE: if (!rx_sync) begin state <= START; count <= DIVISOR/2 - 1; end + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_rx.sv:26:57: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.receiver' + 26 | else begin state <= DATA; bit_index <= 0; count <= DIVISOR - 1; end + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_rx.sv:29:46: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.receiver' + 29 | shift[bit_index] <= rx_sync; count <= DIVISOR - 1; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:32:43: Operator ADD expects 33 bits on the RHS, but RHS's VARREF 'length' generates 16 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 32 | wire [32:0] end_address = {1'b0,address}+length; + | ^ + ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=5.050 + ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:35:38: Operator ADD expects 32 bits on the RHS, but RHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 35 | wire [31:0] byte_address = address + cursor; + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:67:32: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's SHIFTR generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 67 | 11,12,13,14:tx_data=RAM_BYTES >> ((reply_index-11)*8); + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:68:32: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's SHIFTR generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 68 | 15,16,17,18:tx_data=CLOCK_HZ >> ((reply_index-15)*8); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:73:28: Operator EQ expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 73 | else if(reply_index==7+reply_length) tx_data=crc[7:0]; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:64:23: Operator LT expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 64 | if(reply_index<7+reply_length) begin + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:119:20: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 119 | if(cursor+1==length) state<=CRC0; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:144:25: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 144 | else if(cursor+1==length) begin image_loaded<=1;state<=REPLY;end + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:152:20: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 152 | if(cursor+1==length) state<=REPLY; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:157:43: Operator LT expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 157 | if(reply_index>=2 && reply_index<7+reply_length) crc<=crc_next(crc,tx_data); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:158:25: Operator EQ expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 158 | if(reply_index==8+reply_length) state<=DRAIN; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:87:37: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'timeout_count' generates 22 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 87 | if((receiving && timeout_count==RX_TIMEOUT-1) || (receiving && rx_error)) begin + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:52:20: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'addr' generates 28 bits. + : ... note: In instance 'tb_board_cpu.memory' + 52 | offset=(addr & ~(LANES-1))-BASE; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:78:28: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'write_addr' generates 28 bits. + : ... note: In instance 'tb_board_cpu.memory' + 78 | offset=(write_addr & ~(LANES-1))-BASE; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:86:26: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'h600d600d' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 86 | if (w_bits_data==64'h600d600d) begin + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:91:66: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 91 | $fatal(1,"CPU smoke failed at stage %0d",w_bits_data & 64'hffff); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:90:28: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff0000' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:90:43: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'hbad00000' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^~ +make: Entering directory '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/obj' +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_timing.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_timing.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_threads.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_threads.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb_board_cpu__pch.h -o Vtb_board_cpu__pch.h.fast.gch +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb_board_cpu__pch.h -o Vtb_board_cpu__pch.h.slow.gch +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu__ConstPool__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__1__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__2__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__3__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu__Syms__Slow.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__0.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__1.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__2.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__3.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__4.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__5.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__6.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__7.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__8.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__9.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu__main.cpp +g++ verilated.o verilated_timing.o verilated_threads.o Vtb_board_cpu__ALL.a -pthread -lpthread -latomic -o Vtb_board_cpu +rm Vtb_board_cpu__ALL.verilator_deplist.tmp +make: Leaving directory '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/obj' +- V e r i l a t i o n R e p o r t: Verilator 5.050 2026-07-01 rev v5.050 +- Verilator: Built from 46.540 MB sources in 354 modules, into 26.450 MB in 19 C++ files needing 0.019 MB +- Verilator: Walltime 13.140 s (elab=0.604, cvt=3.406, bld=8.538); cpu 4.858 s on 8 threads; allocated 565.281 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-dma/program.bin b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-dma/program.bin new file mode 100644 index 0000000..c678df9 Binary files /dev/null and b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-dma/program.bin differ diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-dma/simulation.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-dma/simulation.log new file mode 100644 index 0000000..181806b --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-dma/simulation.log @@ -0,0 +1,5 @@ +PASS CPU Sv39/FPU/AMO/cache/interrupt through board AXI/SCU cycles=1914839 +- /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-dma/tb_board_cpu.sv:56: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 19ms; walltime 14.179 s; speed 1.351 ms/s +- Verilator: cpu 14.175 s on 1 threads; allocated 8 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-dma/smoke.bin b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-dma/smoke.bin new file mode 100644 index 0000000..c678df9 Binary files /dev/null and b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-dma/smoke.bin differ diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-dma/smoke.hex b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-dma/smoke.hex new file mode 100644 index 0000000..a3f7961 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-dma/smoke.hex @@ -0,0 +1,608 @@ +37 +21 +00 +00 +1b +01 +11 +00 +13 +11 +21 +01 +13 +01 +01 +ff +97 +02 +00 +00 +93 +82 +c2 +04 +73 +90 +52 +30 +73 +10 +40 +30 +73 +10 +20 +30 +b7 +e2 +01 +00 +73 +a0 +02 +30 +97 +00 +00 +00 +e7 +80 +00 +05 +b7 +02 +00 +60 +37 +63 +0d +60 +1b +03 +d3 +00 +63 +0a +05 +00 +37 +13 +00 +00 +1b +03 +d3 +ba +13 +13 +43 +01 +33 +63 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+97 +57 +00 +00 +93 +87 +a7 +db +aa +97 +8c +c3 +41 +01 +82 +80 +00 +00 +01 +ee +d0 +ba +00 +00 +00 +00 diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-dma/tb_board_cpu.sv b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-dma/tb_board_cpu.sv new file mode 100644 index 0000000..800fb37 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-dma/tb_board_cpu.sv @@ -0,0 +1,92 @@ +`timescale 1ns/1ps +module tb_board_cpu; + reg clk=0;always #5 clk=~clk; + reg reset=1,uart_rx_in=1; + wire uart_tx_out; + wire cpu_run; + wire exited; + wire loader_error; + wire [31:0] exit_code; + wire [3:0] ddr_awid; + wire [27:0] ddr_awaddr; + wire [7:0] ddr_awlen; + wire [2:0] ddr_awsize; + wire [1:0] ddr_awburst; + wire ddr_awvalid; + wire ddr_awready; + wire [127:0] ddr_wdata; + wire [15:0] ddr_wstrb; + wire ddr_wlast; + wire ddr_wvalid; + wire ddr_wready; + wire [3:0] ddr_bid; + wire [1:0] ddr_bresp; + wire ddr_bvalid; + wire ddr_bready; + wire [3:0] ddr_arid; + wire [27:0] ddr_araddr; + wire [7:0] ddr_arlen; + wire [2:0] ddr_arsize; + wire [1:0] ddr_arburst; + wire ddr_arvalid; + wire ddr_arready; + wire [3:0] ddr_rid; + wire [127:0] ddr_rdata; + wire [1:0] ddr_rresp; + wire ddr_rlast; + wire ddr_rvalid; + wire ddr_rready; + wire flash_miso; + wire flash_recovery; + wire flash_mosi; + wire flash_sck; + wire flash_cs_n; + toy_a7_platform platform(.*); + initial begin + repeat(10) @(negedge clk); force platform.loader.cpu_run=1;reset=0;end + integer cycles=0; + always @(posedge clk) if(!reset) begin + cycles<=cycles+1; + if(platform.memory_aw_valid && platform.memory_aw_bits_lock) $fatal(1,"Unexpected AXI exclusive write"); + if(platform.memory_ar_valid && platform.memory_ar_bits_lock) $fatal(1,"Unexpected AXI exclusive read"); + if(ddr_awvalid && ddr_awready && (ddr_awsize!=4 || ddr_awlen!=0)) $fatal(1,"Narrow DDR write"); + if(ddr_arvalid && ddr_arready && (ddr_arsize!=4 || ddr_arlen!=0)) $fatal(1,"Narrow DDR read"); + if(exited && (exit_code & 32'hffff0000)==32'hbad00000) $fatal(1,"CPU oracle failed stage=%h",exit_code); + if(exited && exit_code==32'h600d600d) begin + $display("PASS CPU Sv39/FPU/AMO/cache/interrupt through board AXI/SCU cycles=%0d",cycles);$finish;end + if(cycles>4000000) $fatal(1,"Board CPU watchdog"); + end + axi_smoke_memory #(.ADDR_BITS(28),.BASE(0),.CAPACITY(262144),.IMAGE("smoke.hex")) memory ( + .clock(clk), + .reset(reset), + .aw_bits_id(ddr_awid), + .aw_bits_addr(ddr_awaddr), + .aw_bits_len(ddr_awlen), + .aw_bits_size(ddr_awsize), + .aw_bits_burst(ddr_awburst), + .aw_valid(ddr_awvalid), + .aw_ready(ddr_awready), + .w_bits_data(ddr_wdata), + .w_bits_strb(ddr_wstrb), + .w_bits_last(ddr_wlast), + .w_valid(ddr_wvalid), + .w_ready(ddr_wready), + .b_bits_id(ddr_bid), + .b_bits_resp(ddr_bresp), + .b_valid(ddr_bvalid), + .b_ready(ddr_bready), + .ar_bits_id(ddr_arid), + .ar_bits_addr(ddr_araddr), + .ar_bits_len(ddr_arlen), + .ar_bits_size(ddr_arsize), + .ar_bits_burst(ddr_arburst), + .ar_valid(ddr_arvalid), + .ar_ready(ddr_arready), + .r_bits_id(ddr_rid), + .r_bits_data(ddr_rdata), + .r_bits_resp(ddr_rresp), + .r_bits_last(ddr_rlast), + .r_valid(ddr_rvalid), + .r_ready(ddr_rready) + ); +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-gemmini/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-gemmini/RESULT.json new file mode 100644 index 0000000..e935317 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-gemmini/RESULT.json @@ -0,0 +1,9 @@ +{ + "result": "PASS", + "test": "gemmini", + "binary_sha256": "d6307d194aadb9f23e14edf695ce98ab1ea361881237576b15c251573af2826e", + "original_cpu_oracle": true, + "ddr_phy_simulated": false, + "physical_linux_boot_tested": false, + "cycles": 251063 +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-gemmini/compile.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-gemmini/compile.log new file mode 100644 index 0000000..260a897 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-gemmini/compile.log @@ -0,0 +1,2193 @@ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 31 | module NonSyncResetSynchronizerPrimitiveShiftReg_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ + ... For warning description see https://verilator.org/warn/TIMESCALEMOD?v=5.050 + ... Use "/* verilator lint_off TIMESCALEMOD */" and lint_on around source to disable this message. +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:48:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 48 | module SynchronizerShiftReg_w1_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:61:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 61 | module IntSyncAsyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:74:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 74 | module AsyncResetRegVec_w1_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 103 | module IntSyncCrossingSource_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:118:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 118 | module FixedClockBroadcast_3( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:139:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 139 | module TLMonitor( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:987:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 987 | module TLMonitor_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:2434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 2434 | module TLXbar_sbus_i2_o3_a32d128s3k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:3195:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3195 | module TLMonitor_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4151 | module Repeater_TLBundleA_a28d128s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4218 | module TLWidthWidget16( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4386 | module TLInterconnectCoupler_sbus_to_bus_named_cbus( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4478:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4478 | module ram_2x58( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4497:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4497 | module Queue2_AXI4BundleAW( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4581:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4581 | module ram_2x73( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4600:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4600 | module Queue2_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4657:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4657 | module ram_2x4( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4676:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4676 | module Queue2_AXI4BundleB( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4729:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4729 | module Queue2_AXI4BundleAR( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4813:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4813 | module ram_2x69( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4832:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4832 | module Queue2_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4891:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4891 | module AXI4Buffer( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5067:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5067 | module ram_2x8( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5086:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5086 | module Queue2_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5143:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5143 | module Queue1_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5178 | module AXI4UserYanker( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5540:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5540 | module ram_8x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5559:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5559 | module Queue8_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5631 | module AXI4Deinterleaver( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:6073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6073 | module AXI4IdIndexer( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:6219:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6219 | module TLMonitor_3( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7048:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7048 | module Queue1_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7082:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7082 | module Queue1_AXI4BundleARW( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7148:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7148 | module TLToAXI4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7529:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7529 | module TLMonitor_4( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8396:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8396 | module Repeater_TLBundleA_a31d128s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8463 | module TLWidthWidget16_2( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8623:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8623 | module TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:9400:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 9400 | module SystemBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10050 | module FixedClockBroadcast_4( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10073 | module TLMonitor_5( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10975:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10975 | module TLXbar_cbus_out_i1_o4_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:11288:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +11288 | module TLMonitor_6( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12202:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12202 | module ram_2x114( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12221 | module Queue2_TLBundleA_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12301 | module ram_2x79( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12320:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12320 | module Queue2_TLBundleD_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12399:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12399 | module TLBuffer_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12534:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12534 | module TLMonitor_7( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:13449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13449 | module TLAtomicAutomata_cbus( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:13973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13973 | module TLMonitor_8( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14799 | module Queue1_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14846:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14846 | module TLError( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14953 | module TLMonitor_9( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15857 | module ram_2x100( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15876:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15876 | module Queue2_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15955:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15955 | module Queue2_TLBundleD_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16028 | module TLBuffer_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16155 | module ErrorDeviceWrapper( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16258 | module TLMonitor_10( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17017:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17017 | module Repeater_TLBundleA_a26d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17081:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17081 | module TLFragmenter_CLINT( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17261:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17261 | module TLInterconnectCoupler_cbus_to_clint( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17336:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17336 | module TLMonitor_11( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18106:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18106 | module Repeater_TLBundleA_a28d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18170:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18170 | module TLFragmenter_PLIC( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18350 | module TLInterconnectCoupler_cbus_to_plic( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18425:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18425 | module TLMonitor_12( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19040 | module Repeater_TLBundleA_a17d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19104:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19104 | module TLFragmenter_bootrom( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19263:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19263 | module TLInterconnectCoupler_cbus_to_bootrom( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19330:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19330 | module PeripheryBus_cbus( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19882 | module TLMonitor_13( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20610:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20610 | module ProbePicker( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20688:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20688 | module ram_2x10( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20707:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20707 | module Queue2_BundleMap_6( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20764:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20764 | module AXI4UserYanker_1( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:21713:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21713 | module AXI4IdIndexer_1( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:21859:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21859 | module TLMonitor_14( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22587:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22587 | module Queue1_AXI4BundleW_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22621 | module Queue1_AXI4BundleARW_1( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22687:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22687 | module TLToAXI4_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:23555:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +23555 | module TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:24031:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24031 | module MemoryBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:24349:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24349 | module TLMonitor_15( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25732:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25732 | module BroadcastFilter( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25756:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25756 | module ram_4x144( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25775:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25775 | module Queue4_TLBroadcastData( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25828:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25828 | module TLBroadcastTracker( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25964:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25964 | module TLBroadcastTracker_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:26100:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26100 | module TLBroadcast( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:26686:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26686 | module TLMonitor_16( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27414 | module BankBinder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27491:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27491 | module CoherenceManagerWrapper( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27669:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27669 | module TLMonitor_17( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29229:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29229 | module TLMonitor_18( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29635:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29635 | module TLXbar_MasterXbar_BBTile_i2_o1_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29898 | module IntXbar_i4_o1( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29918:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29918 | module WritebackUnit( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30014:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30014 | module ProbeUnit( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30154:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30154 | module Arbiter1_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30168:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30168 | module Arbiter1_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30191 | module Arbiter1_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30214 | module Arbiter1_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30249:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30249 | module Arbiter1_Bool( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30258 | module ram_16x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30277:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30277 | module Queue16_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30360:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30360 | module Queue1_TLBundleE_a32d128s1k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30388:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30388 | module MSHR( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30835:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30835 | module Arbiter1_HellaCacheResp( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30879:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30879 | module IOMSHR( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31790:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31790 | module sdq_17x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31809 | module MSHRFile( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32350 | module OptimizationBarrier_TLBEntryData( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32406:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32406 | module PMPChecker_s3( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32691:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32691 | module PMAChecker( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32731:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32731 | module DTLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:35923:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35923 | module L1MetadataArray( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:35990:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35990 | module Arbiter5_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36023:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36023 | module Arbiter2_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36055 | module DataArray( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36151 | module Arbiter4_L1DataReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36180:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36180 | module Arbiter2_L1DataWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36206:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36206 | module AMOALU( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36248:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36248 | module MaxPeriodFibonacciLFSR( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36342:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36342 | module Arbiter2_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36377:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36377 | module NonBlockingDCache( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:37660:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37660 | module ICache( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:37914:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37914 | module ShiftQueue( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:38054:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38054 | module PMPChecker_s2( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:38215:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38215 | module ITLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:41129:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41129 | module Frontend( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:41494:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41494 | module TLMonitor_19( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:42301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +42301 | module TLMonitor_20( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43108:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43108 | module TLXbar_i2_o1_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43343 | module TLMonitor_21( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43851:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43851 | module ram_2x116( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43870:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43870 | module Queue2_TLBundleA_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43947:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43947 | module ram_2x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43966:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43966 | module Queue2_TLBundleD_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44045:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44045 | module TLBuffer_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44158:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44158 | module TLMonitor_22( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44783 | module TLBuffer_a32d64s1k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44892:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44892 | module TLMonitor_23( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:45699:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45699 | module Repeater_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:45766:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45766 | module TLWidthWidget8_4( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46074:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46074 | module TLMonitor_24( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46882 | module ram_2x117( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46901:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46901 | module Queue2_TLBundleA_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46981:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46981 | module ram_2x78( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47000:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47000 | module Queue2_TLBundleD_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47079:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47079 | module TLBuffer_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47214 | module HellaCacheArbiter( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47381 | module Arbiter3_Valid_PTWReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47419:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47419 | module OptimizationBarrier_UInt( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47427 | module OptimizationBarrier_PTE( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47459 | module PTW( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:48434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +48434 | module FPUDecoder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49794:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49794 | module CompareRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49824:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49824 | module RecFNToIN_e11_s53_i64( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49873:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49873 | module RecFNToIN_e11_s53_i32( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49912:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49912 | module FPToInt( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50375:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50375 | module RoundAnyRawFNToRecFN_ie7_is64_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50410:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50410 | module PipelinedINToRecFN( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50513:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50513 | module RoundAnyRawFNToRecFN_ie7_is64_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50539 | module PipelinedINToRecFN_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50614 | module RoundAnyRawFNToRecFN_ie7_is64_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50642:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50642 | module PipelinedINToRecFN_2( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50717 | module IntToFP( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51072:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51072 | module RoundAnyRawFNToRecFN_ie11_is53_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51199:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51199 | module RecFNToRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51221 | module RoundAnyRawFNToRecFN_ie11_is53_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51321:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51321 | module RecFNToRecFN_1( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51343 | module FPToFP( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51469:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51469 | module MulAddRecFNToRaw_preMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51569 | module MulAddRecFNToRaw_postMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51822:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51822 | module RoundAnyRawFNToRecFN_ie11_is55_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51953 | module RoundAnyRawFNToRecFN_ie11_is55_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52060:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52060 | module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52194:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52194 | module SharedMulAddRecFNPipe( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52551:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52551 | module FPUSharedFMAPipe( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52682:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52682 | module DivSqrtRawFN_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52852:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52852 | module DivSqrtRecFMToRaw_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52907:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52907 | module RoundAnyRawFNToRecFN_ie5_is13_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53039:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53039 | module RoundRawFNToRecFN_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53068:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53068 | module DivSqrtRecFM_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53128:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53128 | module DivSqrtRawFN_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53297:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53297 | module DivSqrtRecFMToRaw_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53352:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53352 | module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53456:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53456 | module RoundRawFNToRecFN_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53485:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53485 | module DivSqrtRecFM_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53545:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53545 | module DivSqrtRawFN_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53715:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53715 | module DivSqrtRecFMToRaw_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53770:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53770 | module RoundRawFNToRecFN_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53799 | module DivSqrtRecFM_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53860:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53860 | module regfile_32x65( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53905:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53905 | module FPU( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:54820:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +54820 | module RVCExpander( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:55183:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55183 | module IBuf( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:55307:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55307 | module CSRFile( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:57223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57223 | module RocketALU( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:57809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57809 | module MulDiv( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:58107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58107 | module Arbiter3_LLWB( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:58125:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58125 | module rf_31x64( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:58149:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58149 | module RocketBB( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62838:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62838 | module GlobalDecoder( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62928:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62928 | module BankAliasTable( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:64252:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64252 | module BankScoreboard( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:64627:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64627 | module GlobalROB( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68674:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68674 | module Arbiter3_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68717 | module ram_16x4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68736:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68736 | module Queue16_UInt4( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68782:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68782 | module SubROB( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:69357:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69357 | module Arbiter1_SubRobRow( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:69722:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69722 | module GlobalScheduler( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:70973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +70973 | module BootRom( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:71013:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71013 | module Frontend_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:71637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71637 | module PE( + | ^~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:71656:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71656 | module AlwaysOutTransposer( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72411:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72411 | module MacUnit( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72426:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72426 | module PE_64( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72524:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72524 | module Tile( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72571:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72571 | module Mesh( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76050 | module TagQueue( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76191 | module ram_6x7( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76210:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76210 | module Queue6_TagWithIdAndTotalRows( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76271:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76271 | module MeshWithDelays( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77318:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77318 | module ram_data_8x64( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77337 | module Queue8_SramReadResp( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77385:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77385 | module GemminiExCtrl( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79354:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79354 | module LoopMatmulUnroller( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79637 | module LoopConvAddrGen( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79690:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79690 | module LoopConvUnroller( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:80113:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80113 | module LoopCmdEncoder( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:80402:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80402 | module Arbiter2_LoopCmd( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:80598:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80598 | module GemminiBall( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:81783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81783 | module RRArbiter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:81857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81857 | module CmdRouter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:81985:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81985 | module BallCyclePMC( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:82095:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82095 | module BBus( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:82898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82898 | module BallDomainDecoder( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83028 | module ram_4x281( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83047:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83047 | module Queue4_BallReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83178 | module Arbiter1_BallRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83198:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83198 | module BallReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83328:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83328 | module BallDomain( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84141:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84141 | module MemDomainDecoder( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84300:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84300 | module ram_4x158( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84319:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84319 | module Queue4_MemReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84421:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84421 | module Arbiter3_MemRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84463 | module MemReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84631 | module MemLoader( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84869:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84869 | module MemStorer( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85122:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85122 | module MemCyclePMC( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85241:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85241 | module TLB( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85621 | module RRArbiter_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85649:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85649 | module BBTLBCluster( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85777 | module StreamReader( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86142:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86142 | module StreamWriter( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86223 | module ZeroLineGenerator( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86264:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86264 | module MemConfiger( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86433:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86433 | module RRArbiter_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86465:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86465 | module MemGroupQueryArbiter( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86543:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86543 | module MemFrontend( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87160 | module MemMidend( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87621 | module SramBank( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87672:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87672 | module AccPipe( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87781 | module PrivateMemBackend( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:90777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +90777 | module MemBackend( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:91055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91055 | module MemDomain( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:91973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91973 | module Queue1_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92008:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92008 | module GpDomain( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92040 | module ram_8x21( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92059 | module Queue8_BuckyballAccelerator_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92123:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92123 | module BuckyballAccelerator( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93569 | module Queue3_UInt2( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93614 | module SimpleHellaCacheIFReplayQueue( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93667:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93667 | module Arbiter2_HellaCacheReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93678:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93678 | module SimpleHellaCacheIF( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93768:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93768 | module BarrierUnit( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93785:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93785 | module BBTile( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:95579:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +95579 | module TLMonitor_25( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:96427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +96427 | module TLMonitor_26( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98184:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98184 | module ram_2x189( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98203:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98203 | module Queue2_TLBundleA_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98283:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98283 | module ram_2x142( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98302:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98302 | module Queue2_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98381 | module Queue2_TLBundleA_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98459 | module Queue2_TLBundleD_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98539 | module ram_2x60( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98558:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98558 | module Queue2_TLBundleB_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98622:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98622 | module ram_2x173( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98641:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98641 | module Queue2_TLBundleC_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98716:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98716 | module ram_sink_2x1( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98735:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98735 | module Queue2_TLBundleE_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98781 | module TLBuffer_a32d128s2k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99162:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99162 | module IntSyncSyncCrossingSink_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99173:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99173 | module IntSyncSyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99181:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99181 | module TilePRCIDomain( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99589:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99589 | module BundleBridgeNexus_UInt1_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99597:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99597 | module TLMonitor_27( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100216:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100216 | module CLINT( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100337 | module AsyncResetRegVec_w2_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100366:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100366 | module IntSyncCrossingSource_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100386 | module CLINTClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100449 | module TLMonitor_28( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101080:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101080 | module LevelGateway( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101099:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101099 | module PLICFanIn( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101111:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101111 | module Queue1_RegMapperInput_i23_m8( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101160 | module TLPLIC( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101389:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101389 | module PLICClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101452:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101452 | module TLMonitor_29( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101973 | module TLROM( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:102530:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102530 | module bootromClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:102569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102569 | module ToyLinuxSystem( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103817:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103817 | module ToyLinuxChip( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103984:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103984 | module tag_array( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104007:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104007 | module array_0_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104034:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104034 | module array_0_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104059 | module array_2_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104084:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104084 | module array_2_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104109:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104109 | module bbtile_icache_tag_array( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104132:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104132 | module bbtile_icache_data_arrays_0( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104155 | module bbtile_icache_data_arrays_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104176:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104176 | module bbtile_icache_data_arrays_2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104197:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104197 | module bbtile_icache_data_arrays_3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104218 | module robOperands( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104243:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104243 | module sram( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104268:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104268 | module mem( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104301 | module plusarg_reader #( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104326:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104326 | module ITraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104404:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104404 | module FpgaDspMac(input [7:0] a, b, input [19:0] c, output [19:0] y); + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104414 | module PMCTraceDPI( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104464:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104464 | module MemPMCTraceDPI( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104514:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104514 | module MTraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:1:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 1 | module tag_array_ext( input [4:0] RW0_addr, + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 19 | module array_0_0_ext( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:37:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 37 | module bbtile_icache_tag_array_ext( input [5:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:55:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 55 | module bbtile_icache_data_arrays_0_ext( input [7:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:73:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 73 | module robOperands_ext( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:90:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 90 | module sram_ext( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 107 | module mem_ext( input [9:0] RW0_addr, + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:3:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3 | module axi_smoke_memory #( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_tx.sv:27:15: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.transmitter' + 27 | count <= DIVISOR - 1; + | ^~ + ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=5.050 + ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_tx.sv:32:13: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.transmitter' + 32 | count <= DIVISOR - 1; + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_rx.sv:23:55: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.receiver' + 23 | IDLE: if (!rx_sync) begin state <= START; count <= DIVISOR/2 - 1; end + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_rx.sv:26:57: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.receiver' + 26 | else begin state <= DATA; bit_index <= 0; count <= DIVISOR - 1; end + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_rx.sv:29:46: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.receiver' + 29 | shift[bit_index] <= rx_sync; count <= DIVISOR - 1; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:32:43: Operator ADD expects 33 bits on the RHS, but RHS's VARREF 'length' generates 16 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 32 | wire [32:0] end_address = {1'b0,address}+length; + | ^ + ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=5.050 + ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:35:38: Operator ADD expects 32 bits on the RHS, but RHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 35 | wire [31:0] byte_address = address + cursor; + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:67:32: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's SHIFTR generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 67 | 11,12,13,14:tx_data=RAM_BYTES >> ((reply_index-11)*8); + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:68:32: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's SHIFTR generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 68 | 15,16,17,18:tx_data=CLOCK_HZ >> ((reply_index-15)*8); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:73:28: Operator EQ expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 73 | else if(reply_index==7+reply_length) tx_data=crc[7:0]; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:64:23: Operator LT expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 64 | if(reply_index<7+reply_length) begin + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:119:20: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 119 | if(cursor+1==length) state<=CRC0; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:144:25: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 144 | else if(cursor+1==length) begin image_loaded<=1;state<=REPLY;end + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:152:20: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 152 | if(cursor+1==length) state<=REPLY; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:157:43: Operator LT expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 157 | if(reply_index>=2 && reply_index<7+reply_length) crc<=crc_next(crc,tx_data); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:158:25: Operator EQ expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 158 | if(reply_index==8+reply_length) state<=DRAIN; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:87:37: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'timeout_count' generates 22 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 87 | if((receiving && timeout_count==RX_TIMEOUT-1) || (receiving && rx_error)) begin + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:52:20: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'addr' generates 28 bits. + : ... note: In instance 'tb_board_cpu.memory' + 52 | offset=(addr & ~(LANES-1))-BASE; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:78:28: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'write_addr' generates 28 bits. + : ... note: In instance 'tb_board_cpu.memory' + 78 | offset=(write_addr & ~(LANES-1))-BASE; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:86:26: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'h600d600d' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 86 | if (w_bits_data==64'h600d600d) begin + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:91:66: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 91 | $fatal(1,"CPU smoke failed at stage %0d",w_bits_data & 64'hffff); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:90:28: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff0000' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:90:43: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'hbad00000' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^~ +make: Entering directory '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/obj' +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_timing.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_timing.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_threads.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_threads.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb_board_cpu__pch.h -o Vtb_board_cpu__pch.h.fast.gch +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb_board_cpu__pch.h -o Vtb_board_cpu__pch.h.slow.gch +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu__ConstPool__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__1__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__2__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__3__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu__Syms__Slow.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__0.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__1.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__2.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__3.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__4.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__5.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__6.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__7.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__8.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__9.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu__main.cpp +g++ verilated.o verilated_timing.o verilated_threads.o Vtb_board_cpu__ALL.a -pthread -lpthread -latomic -o Vtb_board_cpu +rm Vtb_board_cpu__ALL.verilator_deplist.tmp +make: Leaving directory '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/obj' +- V e r i l a t i o n R e p o r t: Verilator 5.050 2026-07-01 rev v5.050 +- Verilator: Built from 46.540 MB sources in 354 modules, into 26.450 MB in 19 C++ files needing 0.019 MB +- Verilator: Walltime 14.294 s (elab=0.625, cvt=3.762, bld=9.275); cpu 5.309 s on 8 threads; allocated 565.301 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-gemmini/program.bin b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-gemmini/program.bin new file mode 100644 index 0000000..cf62a30 Binary files /dev/null and b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-gemmini/program.bin differ diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-gemmini/simulation.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-gemmini/simulation.log new file mode 100644 index 0000000..637a899 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-gemmini/simulation.log @@ -0,0 +1,5 @@ +PASS CPU Sv39/FPU/AMO/cache/interrupt through board AXI/SCU cycles=251063 +- /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-gemmini/tb_board_cpu.sv:56: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 3ms; walltime 1.874 s; speed 1.340 ms/s +- Verilator: cpu 1.874 s on 1 threads; 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+69 +66 +74 +20 +54 +65 +73 +74 +20 +50 +41 +53 +53 +45 +44 +0a +00 +00 +00 +47 +65 +6d +6d +69 +6e +69 +20 +57 +53 +20 +52 +49 +53 +43 +20 +69 +6e +5f +73 +68 +69 +66 +74 +20 +54 +65 +73 +74 +20 +46 +41 +49 +4c +45 +44 +0a +00 diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-gemmini/tb_board_cpu.sv b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-gemmini/tb_board_cpu.sv new file mode 100644 index 0000000..800fb37 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-gemmini/tb_board_cpu.sv @@ -0,0 +1,92 @@ +`timescale 1ns/1ps +module tb_board_cpu; + reg clk=0;always #5 clk=~clk; + reg reset=1,uart_rx_in=1; + wire uart_tx_out; + wire cpu_run; + wire exited; + wire loader_error; + wire [31:0] exit_code; + wire [3:0] ddr_awid; + wire [27:0] ddr_awaddr; + wire [7:0] ddr_awlen; + wire [2:0] ddr_awsize; + wire [1:0] ddr_awburst; + wire ddr_awvalid; + wire ddr_awready; + wire [127:0] ddr_wdata; + wire [15:0] ddr_wstrb; + wire ddr_wlast; + wire ddr_wvalid; + wire ddr_wready; + wire [3:0] ddr_bid; + wire [1:0] ddr_bresp; + wire ddr_bvalid; + wire ddr_bready; + wire [3:0] ddr_arid; + wire [27:0] ddr_araddr; + wire [7:0] ddr_arlen; + wire [2:0] ddr_arsize; + wire [1:0] ddr_arburst; + wire ddr_arvalid; + wire ddr_arready; + wire [3:0] ddr_rid; + wire [127:0] ddr_rdata; + wire [1:0] ddr_rresp; + wire ddr_rlast; + wire ddr_rvalid; + wire ddr_rready; + wire flash_miso; + wire flash_recovery; + wire flash_mosi; + wire flash_sck; + wire flash_cs_n; + toy_a7_platform platform(.*); + initial begin + repeat(10) @(negedge clk); force platform.loader.cpu_run=1;reset=0;end + integer cycles=0; + always @(posedge clk) if(!reset) begin + cycles<=cycles+1; + if(platform.memory_aw_valid && platform.memory_aw_bits_lock) $fatal(1,"Unexpected AXI exclusive write"); + if(platform.memory_ar_valid && platform.memory_ar_bits_lock) $fatal(1,"Unexpected AXI exclusive read"); + if(ddr_awvalid && ddr_awready && (ddr_awsize!=4 || ddr_awlen!=0)) $fatal(1,"Narrow DDR write"); + if(ddr_arvalid && ddr_arready && (ddr_arsize!=4 || ddr_arlen!=0)) $fatal(1,"Narrow DDR read"); + if(exited && (exit_code & 32'hffff0000)==32'hbad00000) $fatal(1,"CPU oracle failed stage=%h",exit_code); + if(exited && exit_code==32'h600d600d) begin + $display("PASS CPU Sv39/FPU/AMO/cache/interrupt through board AXI/SCU cycles=%0d",cycles);$finish;end + if(cycles>4000000) $fatal(1,"Board CPU watchdog"); + end + axi_smoke_memory #(.ADDR_BITS(28),.BASE(0),.CAPACITY(262144),.IMAGE("smoke.hex")) memory ( + .clock(clk), + .reset(reset), + .aw_bits_id(ddr_awid), + .aw_bits_addr(ddr_awaddr), + .aw_bits_len(ddr_awlen), + .aw_bits_size(ddr_awsize), + .aw_bits_burst(ddr_awburst), + .aw_valid(ddr_awvalid), + .aw_ready(ddr_awready), + .w_bits_data(ddr_wdata), + .w_bits_strb(ddr_wstrb), + .w_bits_last(ddr_wlast), + .w_valid(ddr_wvalid), + .w_ready(ddr_wready), + .b_bits_id(ddr_bid), + .b_bits_resp(ddr_bresp), + .b_valid(ddr_bvalid), + .b_ready(ddr_bready), + .ar_bits_id(ddr_arid), + .ar_bits_addr(ddr_araddr), + .ar_bits_len(ddr_arlen), + .ar_bits_size(ddr_arsize), + .ar_bits_burst(ddr_arburst), + .ar_valid(ddr_arvalid), + .ar_ready(ddr_arready), + .r_bits_id(ddr_rid), + .r_bits_data(ddr_rdata), + .r_bits_resp(ddr_rresp), + .r_bits_last(ddr_rlast), + .r_valid(ddr_rvalid), + .r_ready(ddr_rready) + ); +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-linux-final/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-linux-final/RESULT.json new file mode 100644 index 0000000..ac44720 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-linux-final/RESULT.json @@ -0,0 +1,17 @@ +{ + "result": "PASS_RTL_LINUX_USERSPACE", + "payload_sha256": "e2282b5a7ddf1aa01579919aa92df483ed79e739bf5d39530e07532e164118b0", + "checks": [ + "OpenSBI", + "Linux version", + "PASS VM_COPY_ON_WRITE", + "PASS VM_PAGE_PROTECTION", + "PASS FP64_PROCESS_CONTEXT", + "PASS LINUX_TIMER", + "PASS LINUX_SYSTEM_CHECK", + "PASS BOARD_LINUX_USERSPACE" + ], + "physical_mig_simulated": false, + "physical_board_tested": false, + "uart_rx_command_tested": true +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-linux-final/compile.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-linux-final/compile.log new file mode 100644 index 0000000..0935a71 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-linux-final/compile.log @@ -0,0 +1,2193 @@ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 31 | module NonSyncResetSynchronizerPrimitiveShiftReg_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ + ... For warning description see https://verilator.org/warn/TIMESCALEMOD?v=5.050 + ... Use "/* verilator lint_off TIMESCALEMOD */" and lint_on around source to disable this message. +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:48:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 48 | module SynchronizerShiftReg_w1_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:61:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 61 | module IntSyncAsyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:74:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 74 | module AsyncResetRegVec_w1_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 103 | module IntSyncCrossingSource_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:118:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 118 | module FixedClockBroadcast_3( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:139:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 139 | module TLMonitor( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:987:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 987 | module TLMonitor_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:2434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 2434 | module TLXbar_sbus_i2_o3_a32d128s3k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:3195:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3195 | module TLMonitor_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4151 | module Repeater_TLBundleA_a28d128s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4218 | module TLWidthWidget16( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4386 | module TLInterconnectCoupler_sbus_to_bus_named_cbus( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4478:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4478 | module ram_2x58( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4497:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4497 | module Queue2_AXI4BundleAW( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4581:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4581 | module ram_2x73( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4600:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4600 | module Queue2_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4657:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4657 | module ram_2x4( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4676:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4676 | module Queue2_AXI4BundleB( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4729:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4729 | module Queue2_AXI4BundleAR( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4813:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4813 | module ram_2x69( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4832:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4832 | module Queue2_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4891:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4891 | module AXI4Buffer( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5067:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5067 | module ram_2x8( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5086:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5086 | module Queue2_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5143:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5143 | module Queue1_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5178 | module AXI4UserYanker( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5540:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5540 | module ram_8x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5559:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5559 | module Queue8_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5631 | module AXI4Deinterleaver( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:6073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6073 | module AXI4IdIndexer( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:6219:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6219 | module TLMonitor_3( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7048:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7048 | module Queue1_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7082:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7082 | module Queue1_AXI4BundleARW( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7148:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7148 | module TLToAXI4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7529:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7529 | module TLMonitor_4( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8396:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8396 | module Repeater_TLBundleA_a31d128s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8463 | module TLWidthWidget16_2( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8623:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8623 | module TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:9400:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 9400 | module SystemBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10050 | module FixedClockBroadcast_4( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10073 | module TLMonitor_5( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10975:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10975 | module TLXbar_cbus_out_i1_o4_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:11288:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +11288 | module TLMonitor_6( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12202:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12202 | module ram_2x114( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12221 | module Queue2_TLBundleA_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12301 | module ram_2x79( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12320:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12320 | module Queue2_TLBundleD_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12399:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12399 | module TLBuffer_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12534:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12534 | module TLMonitor_7( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:13449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13449 | module TLAtomicAutomata_cbus( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:13973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13973 | module TLMonitor_8( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14799 | module Queue1_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14846:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14846 | module TLError( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14953 | module TLMonitor_9( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15857 | module ram_2x100( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15876:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15876 | module Queue2_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15955:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15955 | module Queue2_TLBundleD_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16028 | module TLBuffer_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16155 | module ErrorDeviceWrapper( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16258 | module TLMonitor_10( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17017:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17017 | module Repeater_TLBundleA_a26d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17081:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17081 | module TLFragmenter_CLINT( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17261:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17261 | module TLInterconnectCoupler_cbus_to_clint( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17336:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17336 | module TLMonitor_11( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18106:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18106 | module Repeater_TLBundleA_a28d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18170:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18170 | module TLFragmenter_PLIC( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18350 | module TLInterconnectCoupler_cbus_to_plic( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18425:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18425 | module TLMonitor_12( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19040 | module Repeater_TLBundleA_a17d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19104:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19104 | module TLFragmenter_bootrom( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19263:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19263 | module TLInterconnectCoupler_cbus_to_bootrom( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19330:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19330 | module PeripheryBus_cbus( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19882 | module TLMonitor_13( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20610:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20610 | module ProbePicker( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20688:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20688 | module ram_2x10( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20707:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20707 | module Queue2_BundleMap_6( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20764:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20764 | module AXI4UserYanker_1( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:21713:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21713 | module AXI4IdIndexer_1( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:21859:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21859 | module TLMonitor_14( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22587:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22587 | module Queue1_AXI4BundleW_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22621 | module Queue1_AXI4BundleARW_1( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22687:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22687 | module TLToAXI4_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:23555:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +23555 | module TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:24031:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24031 | module MemoryBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:24349:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24349 | module TLMonitor_15( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25732:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25732 | module BroadcastFilter( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25756:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25756 | module ram_4x144( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25775:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25775 | module Queue4_TLBroadcastData( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25828:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25828 | module TLBroadcastTracker( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25964:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25964 | module TLBroadcastTracker_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:26100:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26100 | module TLBroadcast( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:26686:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26686 | module TLMonitor_16( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27414 | module BankBinder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27491:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27491 | module CoherenceManagerWrapper( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27669:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27669 | module TLMonitor_17( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29229:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29229 | module TLMonitor_18( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29635:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29635 | module TLXbar_MasterXbar_BBTile_i2_o1_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29898 | module IntXbar_i4_o1( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29918:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29918 | module WritebackUnit( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30014:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30014 | module ProbeUnit( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30154:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30154 | module Arbiter1_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30168:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30168 | module Arbiter1_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30191 | module Arbiter1_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30214 | module Arbiter1_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30249:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30249 | module Arbiter1_Bool( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30258 | module ram_16x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30277:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30277 | module Queue16_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30360:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30360 | module Queue1_TLBundleE_a32d128s1k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30388:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30388 | module MSHR( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30835:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30835 | module Arbiter1_HellaCacheResp( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30879:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30879 | module IOMSHR( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31790:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31790 | module sdq_17x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31809 | module MSHRFile( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32350 | module OptimizationBarrier_TLBEntryData( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32406:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32406 | module PMPChecker_s3( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32691:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32691 | module PMAChecker( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32731:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32731 | module DTLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:35923:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35923 | module L1MetadataArray( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:35990:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35990 | module Arbiter5_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36023:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36023 | module Arbiter2_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36055 | module DataArray( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36151 | module Arbiter4_L1DataReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36180:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36180 | module Arbiter2_L1DataWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36206:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36206 | module AMOALU( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36248:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36248 | module MaxPeriodFibonacciLFSR( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36342:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36342 | module Arbiter2_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36377:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36377 | module NonBlockingDCache( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:37660:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37660 | module ICache( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:37914:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37914 | module ShiftQueue( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:38054:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38054 | module PMPChecker_s2( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:38215:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38215 | module ITLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:41129:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41129 | module Frontend( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:41494:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41494 | module TLMonitor_19( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:42301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +42301 | module TLMonitor_20( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43108:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43108 | module TLXbar_i2_o1_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43343 | module TLMonitor_21( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43851:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43851 | module ram_2x116( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43870:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43870 | module Queue2_TLBundleA_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43947:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43947 | module ram_2x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43966:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43966 | module Queue2_TLBundleD_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44045:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44045 | module TLBuffer_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44158:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44158 | module TLMonitor_22( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44783 | module TLBuffer_a32d64s1k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44892:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44892 | module TLMonitor_23( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:45699:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45699 | module Repeater_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:45766:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45766 | module TLWidthWidget8_4( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46074:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46074 | module TLMonitor_24( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46882 | module ram_2x117( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46901:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46901 | module Queue2_TLBundleA_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46981:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46981 | module ram_2x78( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47000:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47000 | module Queue2_TLBundleD_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47079:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47079 | module TLBuffer_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47214 | module HellaCacheArbiter( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47381 | module Arbiter3_Valid_PTWReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47419:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47419 | module OptimizationBarrier_UInt( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47427 | module OptimizationBarrier_PTE( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47459 | module PTW( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:48434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +48434 | module FPUDecoder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49794:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49794 | module CompareRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49824:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49824 | module RecFNToIN_e11_s53_i64( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49873:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49873 | module RecFNToIN_e11_s53_i32( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49912:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49912 | module FPToInt( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50375:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50375 | module RoundAnyRawFNToRecFN_ie7_is64_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50410:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50410 | module PipelinedINToRecFN( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50513:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50513 | module RoundAnyRawFNToRecFN_ie7_is64_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50539 | module PipelinedINToRecFN_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50614 | module RoundAnyRawFNToRecFN_ie7_is64_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50642:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50642 | module PipelinedINToRecFN_2( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50717 | module IntToFP( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51072:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51072 | module RoundAnyRawFNToRecFN_ie11_is53_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51199:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51199 | module RecFNToRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51221 | module RoundAnyRawFNToRecFN_ie11_is53_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51321:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51321 | module RecFNToRecFN_1( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51343 | module FPToFP( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51469:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51469 | module MulAddRecFNToRaw_preMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51569 | module MulAddRecFNToRaw_postMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51822:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51822 | module RoundAnyRawFNToRecFN_ie11_is55_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51953 | module RoundAnyRawFNToRecFN_ie11_is55_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52060:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52060 | module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52194:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52194 | module SharedMulAddRecFNPipe( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52551:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52551 | module FPUSharedFMAPipe( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52682:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52682 | module DivSqrtRawFN_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52852:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52852 | module DivSqrtRecFMToRaw_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52907:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52907 | module RoundAnyRawFNToRecFN_ie5_is13_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53039:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53039 | module RoundRawFNToRecFN_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53068:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53068 | module DivSqrtRecFM_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53128:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53128 | module DivSqrtRawFN_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53297:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53297 | module DivSqrtRecFMToRaw_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53352:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53352 | module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53456:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53456 | module RoundRawFNToRecFN_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53485:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53485 | module DivSqrtRecFM_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53545:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53545 | module DivSqrtRawFN_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53715:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53715 | module DivSqrtRecFMToRaw_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53770:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53770 | module RoundRawFNToRecFN_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53799 | module DivSqrtRecFM_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53860:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53860 | module regfile_32x65( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53905:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53905 | module FPU( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:54820:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +54820 | module RVCExpander( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:55183:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55183 | module IBuf( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:55307:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55307 | module CSRFile( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:57223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57223 | module RocketALU( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:57809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57809 | module MulDiv( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:58107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58107 | module Arbiter3_LLWB( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:58125:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58125 | module rf_31x64( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:58149:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58149 | module RocketBB( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62838:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62838 | module GlobalDecoder( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62928:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62928 | module BankAliasTable( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:64252:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64252 | module BankScoreboard( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:64627:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64627 | module GlobalROB( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68674:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68674 | module Arbiter3_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68717 | module ram_16x4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68736:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68736 | module Queue16_UInt4( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68782:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68782 | module SubROB( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:69357:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69357 | module Arbiter1_SubRobRow( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:69722:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69722 | module GlobalScheduler( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:70973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +70973 | module BootRom( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:71013:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71013 | module Frontend_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:71637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71637 | module PE( + | ^~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:71656:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71656 | module AlwaysOutTransposer( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72411:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72411 | module MacUnit( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72426:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72426 | module PE_64( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72524:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72524 | module Tile( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72571:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72571 | module Mesh( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76050 | module TagQueue( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76191 | module ram_6x7( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76210:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76210 | module Queue6_TagWithIdAndTotalRows( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76271:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76271 | module MeshWithDelays( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77318:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77318 | module ram_data_8x64( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77337 | module Queue8_SramReadResp( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77385:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77385 | module GemminiExCtrl( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79354:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79354 | module LoopMatmulUnroller( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79637 | module LoopConvAddrGen( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79690:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79690 | module LoopConvUnroller( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:80113:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80113 | module LoopCmdEncoder( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:80402:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80402 | module Arbiter2_LoopCmd( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:80598:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80598 | module GemminiBall( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:81783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81783 | module RRArbiter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:81857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81857 | module CmdRouter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:81985:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81985 | module BallCyclePMC( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:82095:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82095 | module BBus( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:82898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82898 | module BallDomainDecoder( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83028 | module ram_4x281( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83047:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83047 | module Queue4_BallReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83178 | module Arbiter1_BallRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83198:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83198 | module BallReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83328:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83328 | module BallDomain( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84141:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84141 | module MemDomainDecoder( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84300:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84300 | module ram_4x158( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84319:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84319 | module Queue4_MemReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84421:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84421 | module Arbiter3_MemRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84463 | module MemReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84631 | module MemLoader( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84869:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84869 | module MemStorer( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85122:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85122 | module MemCyclePMC( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85241:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85241 | module TLB( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85621 | module RRArbiter_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85649:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85649 | module BBTLBCluster( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85777 | module StreamReader( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86142:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86142 | module StreamWriter( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86223 | module ZeroLineGenerator( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86264:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86264 | module MemConfiger( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86433:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86433 | module RRArbiter_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86465:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86465 | module MemGroupQueryArbiter( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86543:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86543 | module MemFrontend( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87160 | module MemMidend( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87621 | module SramBank( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87672:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87672 | module AccPipe( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87781 | module PrivateMemBackend( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:90777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +90777 | module MemBackend( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:91055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91055 | module MemDomain( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:91973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91973 | module Queue1_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92008:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92008 | module GpDomain( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92040 | module ram_8x21( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92059 | module Queue8_BuckyballAccelerator_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92123:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92123 | module BuckyballAccelerator( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93569 | module Queue3_UInt2( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93614 | module SimpleHellaCacheIFReplayQueue( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93667:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93667 | module Arbiter2_HellaCacheReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93678:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93678 | module SimpleHellaCacheIF( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93768:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93768 | module BarrierUnit( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93785:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93785 | module BBTile( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:95579:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +95579 | module TLMonitor_25( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:96427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +96427 | module TLMonitor_26( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98184:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98184 | module ram_2x189( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98203:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98203 | module Queue2_TLBundleA_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98283:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98283 | module ram_2x142( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98302:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98302 | module Queue2_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98381 | module Queue2_TLBundleA_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98459 | module Queue2_TLBundleD_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98539 | module ram_2x60( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98558:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98558 | module Queue2_TLBundleB_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98622:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98622 | module ram_2x173( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98641:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98641 | module Queue2_TLBundleC_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98716:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98716 | module ram_sink_2x1( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98735:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98735 | module Queue2_TLBundleE_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98781 | module TLBuffer_a32d128s2k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99162:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99162 | module IntSyncSyncCrossingSink_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99173:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99173 | module IntSyncSyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99181:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99181 | module TilePRCIDomain( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99589:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99589 | module BundleBridgeNexus_UInt1_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99597:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99597 | module TLMonitor_27( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100216:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100216 | module CLINT( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100337 | module AsyncResetRegVec_w2_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100366:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100366 | module IntSyncCrossingSource_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100386 | module CLINTClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100449 | module TLMonitor_28( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101080:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101080 | module LevelGateway( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101099:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101099 | module PLICFanIn( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101111:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101111 | module Queue1_RegMapperInput_i23_m8( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101160 | module TLPLIC( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101389:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101389 | module PLICClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101452:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101452 | module TLMonitor_29( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101973 | module TLROM( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:102530:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102530 | module bootromClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:102569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102569 | module ToyLinuxSystem( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103817:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103817 | module ToyLinuxChip( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103984:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103984 | module tag_array( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104007:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104007 | module array_0_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104034:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104034 | module array_0_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104059 | module array_2_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104084:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104084 | module array_2_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104109:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104109 | module bbtile_icache_tag_array( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104132:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104132 | module bbtile_icache_data_arrays_0( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104155 | module bbtile_icache_data_arrays_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104176:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104176 | module bbtile_icache_data_arrays_2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104197:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104197 | module bbtile_icache_data_arrays_3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104218 | module robOperands( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104243:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104243 | module sram( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104268:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104268 | module mem( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104301 | module plusarg_reader #( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104326:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104326 | module ITraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104404:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104404 | module FpgaDspMac(input [7:0] a, b, input [19:0] c, output [19:0] y); + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104414 | module PMCTraceDPI( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104464:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104464 | module MemPMCTraceDPI( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104514:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104514 | module MTraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:1:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 1 | module tag_array_ext( input [4:0] RW0_addr, + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 19 | module array_0_0_ext( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:37:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 37 | module bbtile_icache_tag_array_ext( input [5:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:55:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 55 | module bbtile_icache_data_arrays_0_ext( input [7:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:73:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 73 | module robOperands_ext( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:90:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 90 | module sram_ext( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 107 | module mem_ext( input [9:0] RW0_addr, + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:3:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3 | module axi_smoke_memory #( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_tx.sv:27:15: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_linux.platform.transmitter' + 27 | count <= DIVISOR - 1; + | ^~ + ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=5.050 + ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_tx.sv:32:13: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_linux.platform.transmitter' + 32 | count <= DIVISOR - 1; + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_rx.sv:23:55: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_linux.platform.receiver' + 23 | IDLE: if (!rx_sync) begin state <= START; count <= DIVISOR/2 - 1; end + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_rx.sv:26:57: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_linux.platform.receiver' + 26 | else begin state <= DATA; bit_index <= 0; count <= DIVISOR - 1; end + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_rx.sv:29:46: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_linux.platform.receiver' + 29 | shift[bit_index] <= rx_sync; count <= DIVISOR - 1; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:32:43: Operator ADD expects 33 bits on the RHS, but RHS's VARREF 'length' generates 16 bits. + : ... note: In instance 'tb_board_linux.platform.loader' + 32 | wire [32:0] end_address = {1'b0,address}+length; + | ^ + ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=5.050 + ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:35:38: Operator ADD expects 32 bits on the RHS, but RHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_linux.platform.loader' + 35 | wire [31:0] byte_address = address + cursor; + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:67:32: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's SHIFTR generates 32 bits. + : ... note: In instance 'tb_board_linux.platform.loader' + 67 | 11,12,13,14:tx_data=RAM_BYTES >> ((reply_index-11)*8); + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:68:32: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's SHIFTR generates 32 bits. + : ... note: In instance 'tb_board_linux.platform.loader' + 68 | 15,16,17,18:tx_data=CLOCK_HZ >> ((reply_index-15)*8); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:73:28: Operator EQ expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_linux.platform.loader' + 73 | else if(reply_index==7+reply_length) tx_data=crc[7:0]; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:64:23: Operator LT expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_linux.platform.loader' + 64 | if(reply_index<7+reply_length) begin + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:119:20: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_linux.platform.loader' + 119 | if(cursor+1==length) state<=CRC0; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:144:25: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_linux.platform.loader' + 144 | else if(cursor+1==length) begin image_loaded<=1;state<=REPLY;end + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:152:20: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_linux.platform.loader' + 152 | if(cursor+1==length) state<=REPLY; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:157:43: Operator LT expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_linux.platform.loader' + 157 | if(reply_index>=2 && reply_index<7+reply_length) crc<=crc_next(crc,tx_data); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:158:25: Operator EQ expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_linux.platform.loader' + 158 | if(reply_index==8+reply_length) state<=DRAIN; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:87:37: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'timeout_count' generates 22 bits. + : ... note: In instance 'tb_board_linux.platform.loader' + 87 | if((receiving && timeout_count==RX_TIMEOUT-1) || (receiving && rx_error)) begin + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:52:20: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'addr' generates 28 bits. + : ... note: In instance 'tb_board_linux.memory' + 52 | offset=(addr & ~(LANES-1))-BASE; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:78:28: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'write_addr' generates 28 bits. + : ... note: In instance 'tb_board_linux.memory' + 78 | offset=(write_addr & ~(LANES-1))-BASE; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:86:26: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'h600d600d' generates 64 bits. + : ... note: In instance 'tb_board_linux.memory' + 86 | if (w_bits_data==64'h600d600d) begin + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:91:66: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff' generates 64 bits. + : ... note: In instance 'tb_board_linux.memory' + 91 | $fatal(1,"CPU smoke failed at stage %0d",w_bits_data & 64'hffff); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:90:28: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff0000' generates 64 bits. + : ... note: In instance 'tb_board_linux.memory' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:90:43: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'hbad00000' generates 64 bits. + : ... note: In instance 'tb_board_linux.memory' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^~ +make: Entering directory '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/obj' +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_timing.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_timing.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_threads.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_threads.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb_board_linux__pch.h -o Vtb_board_linux__pch.h.fast.gch +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb_board_linux__pch.h -o Vtb_board_linux__pch.h.slow.gch +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.slow -c Vtb_board_linux__ConstPool__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.slow -c Vtb_board_linux___024root__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.slow -c Vtb_board_linux___024root__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.slow -c Vtb_board_linux___024root__1__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.slow -c Vtb_board_linux___024root__2__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.slow -c Vtb_board_linux___024root__3__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.slow -c Vtb_board_linux__Syms__Slow.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.fast -c Vtb_board_linux.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.fast -c Vtb_board_linux___024root__0.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.fast -c Vtb_board_linux___024root__1.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.fast -c Vtb_board_linux___024root__2.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.fast -c Vtb_board_linux___024root__3.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.fast -c Vtb_board_linux___024root__4.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.fast -c Vtb_board_linux___024root__5.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.fast -c Vtb_board_linux___024root__6.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.fast -c Vtb_board_linux___024root__7.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.fast -c Vtb_board_linux___024root__8.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.fast -c Vtb_board_linux___024root__9.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.fast -c Vtb_board_linux__main.cpp +g++ verilated.o verilated_timing.o verilated_threads.o Vtb_board_linux__ALL.a -pthread -lpthread -latomic -o Vtb_board_linux +rm Vtb_board_linux__ALL.verilator_deplist.tmp +make: Leaving directory '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/obj' +- V e r i l a t i o n R e p o r t: Verilator 5.050 2026-07-01 rev v5.050 +- Verilator: Built from 46.556 MB sources in 354 modules, into 26.899 MB in 19 C++ files needing 0.021 MB +- Verilator: Walltime 18.545 s (elab=0.677, cvt=3.934, bld=13.223); cpu 5.638 s on 8 threads; allocated 438.199 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-linux-final/simulation.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-linux-final/simulation.log new file mode 100644 index 0000000..1c96b20 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-linux-final/simulation.log @@ -0,0 +1,172 @@ + +OpenSBI v1.9 + ____ _____ ____ _____ + / __ \ / ____| _ \_ _| + | | | |_ __ ___ _ __ | (___ | |_) || | + | | | | '_ \ / _ \ '_ \ \___ \| _ < | | + | |__| | |_) | __/ | | |____) | |_) || |_ + \____/| .__/ \___|_| |_|_____/|____/_____| + | | + |_| + +Platform Name : Buckyball +Platform Features : medeleg +Platform HART Count : 1 +Platform HART Protection : pmp +Platform IPI Device : aclint-mswi +Platform Timer Device : aclint-mtimer @ 500000Hz +Platform Console Device : buckyball-scu +Platform HSM Device : --- +Platform PMU Device : --- +Platform Reboot Device : buckyball-scu-reset +Platform Shutdown Device : buckyball-scu-reset +Platform Suspend Device : --- +Platform CPPC Device : --- +Firmware Base : 0x80000000 +Firmware Size : 312 KB +Firmware RW Offset : 0x40000 +Firmware RW Size : 56 KB +Firmware Heap Offset : 0x45000 +Firmware Heap Size : 36 KB (total), 0 KB (reserved), 12 KB (used), 23 KB (free) +Firmware Scratch Size : 4096 B (total), 496 B (used), 3600 B (free) +Runtime SBI Version : 3.0 +Standard SBI Extensions : time,rfnc,ipi,base,hsm,srst,pmu,dbcn,fwft,legacy,sse +Experimental SBI Extensions : none + +Domain0 Name : root +Domain0 Boot HART : 0 +Domain0 HARTs : 0x0* +Domain0 Region00 : 0x0000000080040000-0x000000008004ffff M: (F,R,W) S/U: () +Domain0 Region01 : 0x0000000080000000-0x000000008003ffff M: (F,R,X) S/U: () +Domain0 Region02 : 0x0000000002008000-0x000000000200bfff M: (I,R,W) S/U: () +Domain0 Region03 : 0x0000000002000000-0x0000000002007fff M: (I,R,W) S/U: () +Domain0 Region04 : 0x000000000c000000-0x000000000fffffff M: (I,R,W) S/U: (R,W) +Domain0 Region05 : 0x0000000000000000-0xffffffffffffffff M: () S/U: (R,W,X) +Domain0 Next Address : 0x0000000080200000 +Domain0 Next Arg1 : 0x0000000088000000 +Domain0 Next Mode : S-mode +Domain0 SysReset : yes +Domain0 SysSuspend : yes + +Boot HART ID : 0 +Boot HART Domain : root +Boot HART Priv Version : v1.12 +Boot HART Base ISA : rv64imafdcx +Boot HART ISA Extensions : sdtrig +Boot HART PMP Count : 8 +Boot HART PMP Granularity : 2 bits +Boot HART PMP Address Bits : 30 +Boot HART MHPM Info : 0 (0x00000000) +Boot HART Debug Triggers : 0 triggers +Boot HART MIDELEG : 0x0000000000000222 +Boot HART MEDELEG : 0x000000000000b109 +Linux version 6.6.0 (yys@amax) (riscv64-unknown-linux-gnu-gcc (GCC) 15.3.0, GNU ld (GNU Binutils) 2.46) #1 Mon Oct 12 12:10:02 CST 2026 +Machine model: ucb-bar,buckyball +Forcing kernel command line to: console=hvc0 earlycon=sbi loglevel=8 ignore_loglevel panic=1 mem=256M +SBI specification v3.0 detected +SBI implementation ID=0x1 Version=0x10009 +SBI TIME extension detected +SBI IPI extension detected +SBI RFENCE extension detected +SBI SRST extension detected +earlycon: sbi0 at I/O port 0x0 (options '') +printk: bootconsole [sbi0] enabled +printk: debug: ignoring loglevel setting. +Memory limited to 256MB +efi: UEFI not found. +OF: reserved mem: 0x0000000080000000..0x000000008003ffff (256 KiB) nomap non-reusable mmode_resv1@80000000 +OF: reserved mem: 0x0000000080040000..0x000000008004ffff (64 KiB) nomap non-reusable mmode_resv0@80040000 +Zone ranges: + DMA32 [mem 0x0000000080000000-0x000000008fffffff] + Normal empty +Movable zone start for each node +Early memory node ranges + node 0: [mem 0x0000000080000000-0x000000008004ffff] + node 0: [mem 0x0000000080050000-0x000000008fffffff] +Initmem setup node 0 [mem 0x0000000080000000-0x000000008fffffff] +Falling back to deprecated "riscv,isa" +riscv: base ISA extensions abcdfim +riscv: ELF capabilities acdfim +pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768 +pcpu-alloc: [0] 0 +Kernel command line: console=hvc0 earlycon=sbi loglevel=8 ignore_loglevel panic=1 mem=256M +Dentry cache hash table entries: 32768 (order: 6, 262144 bytes, linear) +Inode-cache hash table entries: 16384 (order: 5, 131072 bytes, linear) +Built 1 zonelists, mobility grouping on. Total pages: 64640 +mem auto-init: stack:all(zero), heap alloc:off, heap free:off +Memory: 233208K/262144K available (2126K kernel code, 4319K rwdata, 2048K rodata, 12681K init, 299K bss, 28936K reserved, 0K cma-reserved) +SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 +NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 +riscv-intc: 64 local interrupts mapped +plic: interrupt-controller@c000000: mapped 1 interrupts with 1 handlers for 2 contexts. +clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1d854df40, max_idle_ns: 7052723233920 ns +sched_clock: 64 bits at 500kHz, resolution 2000ns, wraps every 4398046511000ns +Console: colour dummy device 80x25 +printk: console [hvc0] enabled +printk: console [hvc0] enabled +printk: bootconsole [sbi0] disabled +printk: bootconsole [sbi0] disabled +Calibrating delay loop (skipped), value calculated using timer frequency.. 1.00 BogoMIPS (lpj=2000) +pid_max: default: 32768 minimum: 301 +Mount-cache hash table entries: 512 (order: 0, 4096 bytes, linear) +Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes, linear) +riscv: ELF compat mode unsupported +ASID allocator disabled (0 bits) +EFI services will not be available. +devtmpfs: initialized +clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns +futex hash table entries: 256 (order: 0, 6144 bytes, linear) +DMA: preallocated 128 KiB GFP_KERNEL pool for atomic allocations +DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations +cpu0: Ratio of byte access time to unaligned word access is 0.01, unaligned accesses are slow +clocksource: Switched to clocksource riscv_clocksource +workingset: timestamp_bits=62 max_order=16 bucket_order=0 +io scheduler mq-deadline registered +io scheduler kyber registered +clk: Disabling unused clocks +Freeing unused kernel image (initmem) memory: 12680K +Run /init as init process + with arguments: + /init + with environment: + HOME=/ + TERM=linux + + __ __ __ ____ + / / / /___ __ _____ ____ _ / /_ ____ _/ / / + / /_/ / __ `/ | / / _ \ / __ `/ / __ \/ __ `/ / / + / __ / /_/ /| |/ / __/ / /_/ / / /_/ / /_/ / / / + /_/ /_/\__,_/ |___/\___/ \__,_/ /_.___/\__,_/_/_/ + +/bin/sh: can't access tty; job control turned off +~ # +SIM_SHELL_PROMPT cycles=309244118 +/root/linux_system_check-linux +SIM_COMMAND_SENT cycles=317001898 overflow=0 framing=0 pending_rx=1 + +BEGIN LINUX_SYSTEM_CHECK +PASS VM_COPY_ON_WRITE +linux_system_ch[25]: unhandled signal 11 code 0x2 at 0x0000003fac65e000 in linux_system_check-linux[10000+7a000] +CPU: 0 PID: 25 Comm: linux_system_ch Not tainted 6.6.0 #1 +Hardware name: ucb-bar,buckyball (DT) +epc : 00000000000105c6 ra : 000000000001041e sp : 0000003fecfb5b50 + gp : 0000000000090078 tp : 0000000000096760 t0 : 0000000000000000 + t1 : 0000000000000000 t2 : 0000000000000000 s0 : 0000003fecfb5bd0 + s1 : 0000003fac65d000 a0 : 0000000000000000 a1 : 0000000000000000 + a2 : 0000000000000000 a3 : 0000000000000000 a4 : 0000000000000000 + a5 : 0000000000000000 a6 : 0000000000000000 a7 : 0000000000000000 + s2 : 0000000000000042 s3 : 0000000000001000 s4 : 0000003fac65e000 + s5 : 0000003fecfb5d88 s6 : 0000000000000002 s7 : 00000000000106ba + s8 : 00000000000101e0 s9 : 000000000000003a s10: 0000000000094e28 + s11: 0000000000000000 t3 : 0000000000000000 t4 : 0000000000000000 + t5 : 0000000000000000 t6 : 0000000000000000 +status: 800000020001e020 badaddr: 0000003fac65e000 cause: 000000000000000d +PASS VM_PAGE_PROTECTION +PASS FP64_PROCESS_CONTEXT +PASS LINUX_TIMER elapsed_ns=104208000 +PASS LINUX_SYSTEM_CHECK +PASS BOARD_LINUX_USERSPACE cycles=340774843 characters=7994 +- /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-linux-final/tb_board_linux.sv:99: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 14s; walltime 2622.251 s; speed 5.198 ms/s +- Verilator: cpu 2621.942 s on 1 threads; allocated 264 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-linux-final/tb_board_linux.sv b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-linux-final/tb_board_linux.sv new file mode 100644 index 0000000..f101b77 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-linux-final/tb_board_linux.sv @@ -0,0 +1,123 @@ +`timescale 1ns/1ps +module tb_board_linux; + reg clk=0;always #20 clk=~clk; + reg reset=1,uart_rx_in=1; + wire uart_tx_out; + wire cpu_run; + wire exited; + wire loader_error; + wire [31:0] exit_code; + wire [3:0] ddr_awid; + wire [27:0] ddr_awaddr; + wire [7:0] ddr_awlen; + wire [2:0] ddr_awsize; + wire [1:0] ddr_awburst; + wire ddr_awvalid; + wire ddr_awready; + wire [127:0] ddr_wdata; + wire [15:0] ddr_wstrb; + wire ddr_wlast; + wire ddr_wvalid; + wire ddr_wready; + wire [3:0] ddr_bid; + wire [1:0] ddr_bresp; + wire ddr_bvalid; + wire ddr_bready; + wire [3:0] ddr_arid; + wire [27:0] ddr_araddr; + wire [7:0] ddr_arlen; + wire [2:0] ddr_arsize; + wire [1:0] ddr_arburst; + wire ddr_arvalid; + wire ddr_arready; + wire [3:0] ddr_rid; + wire [127:0] ddr_rdata; + wire [1:0] ddr_rresp; + wire ddr_rlast; + wire ddr_rvalid; + wire ddr_rready; + wire flash_miso; + wire flash_recovery; + wire flash_mosi; + wire flash_sck; + wire flash_cs_n; + toy_a7_platform platform(.*); + initial begin + repeat(10) @(negedge clk); force platform.loader.cpu_run=1;reset=0;end + integer cycles=0; + always @(posedge clk) if(!reset) begin + cycles<=cycles+1; + if(platform.memory_aw_valid && platform.memory_aw_bits_lock) $fatal(1,"Unexpected AXI exclusive write"); + if(platform.memory_ar_valid && platform.memory_ar_bits_lock) $fatal(1,"Unexpected AXI exclusive read"); + if(ddr_awvalid && ddr_awready && (ddr_awsize!=4 || ddr_awlen!=0)) $fatal(1,"Narrow DDR write"); + if(ddr_arvalid && ddr_arready && (ddr_arsize!=4 || ddr_arlen!=0)) $fatal(1,"Narrow DDR read"); + if(cycles>500000000) $fatal(1,"Linux cycle watchdog"); + end + axi_smoke_memory #(.ADDR_BITS(28),.BASE(0),.CAPACITY(268435456),.IMAGE("payload.hex")) memory ( + .clock(clk), + .reset(reset), + .aw_bits_id(ddr_awid), + .aw_bits_addr(ddr_awaddr), + .aw_bits_len(ddr_awlen), + .aw_bits_size(ddr_awsize), + .aw_bits_burst(ddr_awburst), + .aw_valid(ddr_awvalid), + .aw_ready(ddr_awready), + .w_bits_data(ddr_wdata), + .w_bits_strb(ddr_wstrb), + .w_bits_last(ddr_wlast), + .w_valid(ddr_wvalid), + .w_ready(ddr_wready), + .b_bits_id(ddr_bid), + .b_bits_resp(ddr_bresp), + .b_valid(ddr_bvalid), + .b_ready(ddr_bready), + .ar_bits_id(ddr_arid), + .ar_bits_addr(ddr_araddr), + .ar_bits_len(ddr_arlen), + .ar_bits_size(ddr_arsize), + .ar_bits_burst(ddr_arburst), + .ar_valid(ddr_arvalid), + .ar_ready(ddr_arready), + .r_bits_id(ddr_rid), + .r_bits_data(ddr_rdata), + .r_bits_resp(ddr_rresp), + .r_bits_last(ddr_rlast), + .r_valid(ddr_rvalid), + .r_ready(ddr_rready) + ); + + reg [255:0] tail=0; + reg init_seen=0,prompt_seen=0; + integer characters=0; + always @(posedge clk) if(!reset && platform.mmio_tx_valid && platform.tx_ready && cpu_run) begin + tail={tail[247:0],platform.mmio_tx_data};characters=characters+1; + $write("%c",platform.mmio_tx_data);$fflush(); + if(tail[95:0]=="init process") init_seen=1; + if(init_seen && tail[15:0]==16'h2320) prompt_seen=1; + if(tail[183:0]=="PASS LINUX_SYSTEM_CHECK") begin + $display("\nPASS BOARD_LINUX_USERSPACE cycles=%0d characters=%0d",cycles,characters);$finish; + end + if(tail[95:0]=="Kernel panic") $fatal(1,"Kernel panic"); + end + task automatic send_byte(input [7:0] value); + @(negedge clk);uart_rx_in=0;repeat(25) @(negedge clk); + for(integer n=0;n<8;n=n+1) begin uart_rx_in=value[n];repeat(25) @(negedge clk);end + uart_rx_in=1;repeat(25) @(negedge clk); + // Allow the polled SBI/HVC console to drain its RAM-backed RX FIFO. + repeat(250000) @(negedge clk); + endtask + initial begin + wait(prompt_seen); + $display("\nSIM_SHELL_PROMPT cycles=%0d",cycles);$fflush(); + send_byte("/");send_byte("r");send_byte("o");send_byte("o");send_byte("t");send_byte("/"); + send_byte("l");send_byte("i");send_byte("n");send_byte("u");send_byte("x");send_byte("_"); + send_byte("s");send_byte("y");send_byte("s");send_byte("t");send_byte("e");send_byte("m");send_byte("_"); + send_byte("c");send_byte("h");send_byte("e");send_byte("c");send_byte("k");send_byte("-"); + send_byte("l");send_byte("i");send_byte("n");send_byte("u");send_byte("x");send_byte(10); + $display("\nSIM_COMMAND_SENT cycles=%0d overflow=%0d framing=%0d pending_rx=%0d",cycles, + platform.peripherals.overflow,platform.peripherals.framing,platform.peripherals.count);$fflush(); + if(platform.peripherals.overflow || platform.peripherals.framing) $fatal(1,"UART input loss"); + end + +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-loop/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-loop/RESULT.json new file mode 100644 index 0000000..c426992 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-loop/RESULT.json @@ -0,0 +1,9 @@ +{ + "result": "PASS", + "test": "loop", + "binary_sha256": "bbe9646dc565ac9ac1188c6b3d53d24b1b37985ee158ee2ac918df04c3267ce2", + "original_cpu_oracle": true, + "ddr_phy_simulated": false, + "physical_linux_boot_tested": false, + "cycles": 684219 +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-loop/compile.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-loop/compile.log new file mode 100644 index 0000000..5084ad7 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-loop/compile.log @@ -0,0 +1,2193 @@ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 31 | module NonSyncResetSynchronizerPrimitiveShiftReg_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ + ... For warning description see https://verilator.org/warn/TIMESCALEMOD?v=5.050 + ... Use "/* verilator lint_off TIMESCALEMOD */" and lint_on around source to disable this message. +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:48:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 48 | module SynchronizerShiftReg_w1_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:61:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 61 | module IntSyncAsyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:74:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 74 | module AsyncResetRegVec_w1_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 103 | module IntSyncCrossingSource_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:118:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 118 | module FixedClockBroadcast_3( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:139:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 139 | module TLMonitor( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:987:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 987 | module TLMonitor_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:2434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 2434 | module TLXbar_sbus_i2_o3_a32d128s3k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:3195:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3195 | module TLMonitor_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4151 | module Repeater_TLBundleA_a28d128s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4218 | module TLWidthWidget16( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4386 | module TLInterconnectCoupler_sbus_to_bus_named_cbus( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4478:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4478 | module ram_2x58( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4497:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4497 | module Queue2_AXI4BundleAW( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4581:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4581 | module ram_2x73( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4600:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4600 | module Queue2_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4657:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4657 | module ram_2x4( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4676:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4676 | module Queue2_AXI4BundleB( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4729:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4729 | module Queue2_AXI4BundleAR( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4813:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4813 | module ram_2x69( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4832:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4832 | module Queue2_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4891:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4891 | module AXI4Buffer( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5067:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5067 | module ram_2x8( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5086:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5086 | module Queue2_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5143:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5143 | module Queue1_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5178 | module AXI4UserYanker( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5540:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5540 | module ram_8x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5559:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5559 | module Queue8_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5631 | module AXI4Deinterleaver( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:6073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6073 | module AXI4IdIndexer( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:6219:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6219 | module TLMonitor_3( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7048:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7048 | module Queue1_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7082:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7082 | module Queue1_AXI4BundleARW( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7148:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7148 | module TLToAXI4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7529:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7529 | module TLMonitor_4( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8396:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8396 | module Repeater_TLBundleA_a31d128s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8463 | module TLWidthWidget16_2( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8623:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8623 | module TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:9400:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 9400 | module SystemBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10050 | module FixedClockBroadcast_4( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10073 | module TLMonitor_5( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10975:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10975 | module TLXbar_cbus_out_i1_o4_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:11288:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +11288 | module TLMonitor_6( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12202:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12202 | module ram_2x114( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12221 | module Queue2_TLBundleA_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12301 | module ram_2x79( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12320:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12320 | module Queue2_TLBundleD_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12399:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12399 | module TLBuffer_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12534:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12534 | module TLMonitor_7( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:13449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13449 | module TLAtomicAutomata_cbus( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:13973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13973 | module TLMonitor_8( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14799 | module Queue1_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14846:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14846 | module TLError( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14953 | module TLMonitor_9( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15857 | module ram_2x100( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15876:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15876 | module Queue2_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15955:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15955 | module Queue2_TLBundleD_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16028 | module TLBuffer_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16155 | module ErrorDeviceWrapper( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16258 | module TLMonitor_10( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17017:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17017 | module Repeater_TLBundleA_a26d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17081:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17081 | module TLFragmenter_CLINT( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17261:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17261 | module TLInterconnectCoupler_cbus_to_clint( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17336:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17336 | module TLMonitor_11( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18106:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18106 | module Repeater_TLBundleA_a28d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18170:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18170 | module TLFragmenter_PLIC( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18350 | module TLInterconnectCoupler_cbus_to_plic( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18425:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18425 | module TLMonitor_12( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19040 | module Repeater_TLBundleA_a17d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19104:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19104 | module TLFragmenter_bootrom( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19263:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19263 | module TLInterconnectCoupler_cbus_to_bootrom( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19330:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19330 | module PeripheryBus_cbus( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19882 | module TLMonitor_13( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20610:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20610 | module ProbePicker( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20688:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20688 | module ram_2x10( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20707:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20707 | module Queue2_BundleMap_6( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20764:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20764 | module AXI4UserYanker_1( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:21713:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21713 | module AXI4IdIndexer_1( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:21859:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21859 | module TLMonitor_14( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22587:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22587 | module Queue1_AXI4BundleW_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22621 | module Queue1_AXI4BundleARW_1( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22687:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22687 | module TLToAXI4_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:23555:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +23555 | module TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:24031:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24031 | module MemoryBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:24349:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24349 | module TLMonitor_15( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25732:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25732 | module BroadcastFilter( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25756:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25756 | module ram_4x144( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25775:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25775 | module Queue4_TLBroadcastData( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25828:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25828 | module TLBroadcastTracker( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25964:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25964 | module TLBroadcastTracker_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:26100:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26100 | module TLBroadcast( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:26686:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26686 | module TLMonitor_16( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27414 | module BankBinder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27491:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27491 | module CoherenceManagerWrapper( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27669:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27669 | module TLMonitor_17( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29229:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29229 | module TLMonitor_18( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29635:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29635 | module TLXbar_MasterXbar_BBTile_i2_o1_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29898 | module IntXbar_i4_o1( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29918:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29918 | module WritebackUnit( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30014:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30014 | module ProbeUnit( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30154:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30154 | module Arbiter1_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30168:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30168 | module Arbiter1_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30191 | module Arbiter1_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30214 | module Arbiter1_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30249:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30249 | module Arbiter1_Bool( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30258 | module ram_16x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30277:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30277 | module Queue16_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30360:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30360 | module Queue1_TLBundleE_a32d128s1k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30388:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30388 | module MSHR( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30835:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30835 | module Arbiter1_HellaCacheResp( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30879:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30879 | module IOMSHR( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31790:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31790 | module sdq_17x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31809 | module MSHRFile( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32350 | module OptimizationBarrier_TLBEntryData( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32406:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32406 | module PMPChecker_s3( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32691:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32691 | module PMAChecker( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32731:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32731 | module DTLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:35923:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35923 | module L1MetadataArray( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:35990:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35990 | module Arbiter5_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36023:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36023 | module Arbiter2_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36055 | module DataArray( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36151 | module Arbiter4_L1DataReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36180:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36180 | module Arbiter2_L1DataWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36206:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36206 | module AMOALU( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36248:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36248 | module MaxPeriodFibonacciLFSR( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36342:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36342 | module Arbiter2_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36377:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36377 | module NonBlockingDCache( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:37660:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37660 | module ICache( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:37914:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37914 | module ShiftQueue( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:38054:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38054 | module PMPChecker_s2( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:38215:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38215 | module ITLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:41129:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41129 | module Frontend( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:41494:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41494 | module TLMonitor_19( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:42301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +42301 | module TLMonitor_20( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43108:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43108 | module TLXbar_i2_o1_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43343 | module TLMonitor_21( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43851:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43851 | module ram_2x116( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43870:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43870 | module Queue2_TLBundleA_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43947:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43947 | module ram_2x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43966:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43966 | module Queue2_TLBundleD_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44045:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44045 | module TLBuffer_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44158:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44158 | module TLMonitor_22( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44783 | module TLBuffer_a32d64s1k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44892:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44892 | module TLMonitor_23( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:45699:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45699 | module Repeater_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:45766:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45766 | module TLWidthWidget8_4( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46074:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46074 | module TLMonitor_24( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46882 | module ram_2x117( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46901:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46901 | module Queue2_TLBundleA_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46981:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46981 | module ram_2x78( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47000:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47000 | module Queue2_TLBundleD_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47079:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47079 | module TLBuffer_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47214 | module HellaCacheArbiter( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47381 | module Arbiter3_Valid_PTWReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47419:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47419 | module OptimizationBarrier_UInt( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47427 | module OptimizationBarrier_PTE( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47459 | module PTW( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:48434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +48434 | module FPUDecoder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49794:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49794 | module CompareRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49824:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49824 | module RecFNToIN_e11_s53_i64( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49873:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49873 | module RecFNToIN_e11_s53_i32( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49912:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49912 | module FPToInt( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50375:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50375 | module RoundAnyRawFNToRecFN_ie7_is64_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50410:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50410 | module PipelinedINToRecFN( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50513:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50513 | module RoundAnyRawFNToRecFN_ie7_is64_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50539 | module PipelinedINToRecFN_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50614 | module RoundAnyRawFNToRecFN_ie7_is64_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50642:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50642 | module PipelinedINToRecFN_2( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50717 | module IntToFP( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51072:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51072 | module RoundAnyRawFNToRecFN_ie11_is53_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51199:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51199 | module RecFNToRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51221 | module RoundAnyRawFNToRecFN_ie11_is53_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51321:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51321 | module RecFNToRecFN_1( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51343 | module FPToFP( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51469:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51469 | module MulAddRecFNToRaw_preMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51569 | module MulAddRecFNToRaw_postMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51822:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51822 | module RoundAnyRawFNToRecFN_ie11_is55_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51953 | module RoundAnyRawFNToRecFN_ie11_is55_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52060:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52060 | module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52194:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52194 | module SharedMulAddRecFNPipe( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52551:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52551 | module FPUSharedFMAPipe( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52682:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52682 | module DivSqrtRawFN_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52852:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52852 | module DivSqrtRecFMToRaw_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52907:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52907 | module RoundAnyRawFNToRecFN_ie5_is13_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53039:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53039 | module RoundRawFNToRecFN_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53068:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53068 | module DivSqrtRecFM_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53128:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53128 | module DivSqrtRawFN_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53297:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53297 | module DivSqrtRecFMToRaw_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53352:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53352 | module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53456:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53456 | module RoundRawFNToRecFN_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53485:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53485 | module DivSqrtRecFM_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53545:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53545 | module DivSqrtRawFN_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53715:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53715 | module DivSqrtRecFMToRaw_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53770:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53770 | module RoundRawFNToRecFN_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53799 | module DivSqrtRecFM_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53860:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53860 | module regfile_32x65( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53905:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53905 | module FPU( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:54820:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +54820 | module RVCExpander( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:55183:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55183 | module IBuf( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:55307:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55307 | module CSRFile( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:57223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57223 | module RocketALU( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:57809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57809 | module MulDiv( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:58107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58107 | module Arbiter3_LLWB( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:58125:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58125 | module rf_31x64( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:58149:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58149 | module RocketBB( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62838:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62838 | module GlobalDecoder( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62928:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62928 | module BankAliasTable( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:64252:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64252 | module BankScoreboard( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:64627:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64627 | module GlobalROB( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68674:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68674 | module Arbiter3_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68717 | module ram_16x4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68736:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68736 | module Queue16_UInt4( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68782:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68782 | module SubROB( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:69357:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69357 | module Arbiter1_SubRobRow( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:69722:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69722 | module GlobalScheduler( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:70973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +70973 | module BootRom( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:71013:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71013 | module Frontend_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:71637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71637 | module PE( + | ^~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:71656:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71656 | module AlwaysOutTransposer( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72411:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72411 | module MacUnit( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72426:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72426 | module PE_64( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72524:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72524 | module Tile( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72571:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72571 | module Mesh( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76050 | module TagQueue( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76191 | module ram_6x7( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76210:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76210 | module Queue6_TagWithIdAndTotalRows( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76271:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76271 | module MeshWithDelays( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77318:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77318 | module ram_data_8x64( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77337 | module Queue8_SramReadResp( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77385:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77385 | module GemminiExCtrl( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79354:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79354 | module LoopMatmulUnroller( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79637 | module LoopConvAddrGen( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79690:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79690 | module LoopConvUnroller( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:80113:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80113 | module LoopCmdEncoder( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:80402:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80402 | module Arbiter2_LoopCmd( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:80598:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80598 | module GemminiBall( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:81783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81783 | module RRArbiter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:81857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81857 | module CmdRouter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:81985:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81985 | module BallCyclePMC( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:82095:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82095 | module BBus( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:82898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82898 | module BallDomainDecoder( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83028 | module ram_4x281( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83047:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83047 | module Queue4_BallReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83178 | module Arbiter1_BallRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83198:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83198 | module BallReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83328:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83328 | module BallDomain( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84141:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84141 | module MemDomainDecoder( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84300:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84300 | module ram_4x158( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84319:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84319 | module Queue4_MemReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84421:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84421 | module Arbiter3_MemRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84463 | module MemReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84631 | module MemLoader( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84869:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84869 | module MemStorer( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85122:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85122 | module MemCyclePMC( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85241:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85241 | module TLB( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85621 | module RRArbiter_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85649:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85649 | module BBTLBCluster( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85777 | module StreamReader( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86142:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86142 | module StreamWriter( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86223 | module ZeroLineGenerator( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86264:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86264 | module MemConfiger( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86433:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86433 | module RRArbiter_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86465:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86465 | module MemGroupQueryArbiter( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86543:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86543 | module MemFrontend( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87160 | module MemMidend( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87621 | module SramBank( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87672:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87672 | module AccPipe( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87781 | module PrivateMemBackend( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:90777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +90777 | module MemBackend( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:91055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91055 | module MemDomain( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:91973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91973 | module Queue1_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92008:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92008 | module GpDomain( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92040 | module ram_8x21( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92059 | module Queue8_BuckyballAccelerator_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92123:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92123 | module BuckyballAccelerator( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93569 | module Queue3_UInt2( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93614 | module SimpleHellaCacheIFReplayQueue( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93667:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93667 | module Arbiter2_HellaCacheReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93678:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93678 | module SimpleHellaCacheIF( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93768:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93768 | module BarrierUnit( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93785:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93785 | module BBTile( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:95579:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +95579 | module TLMonitor_25( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:96427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +96427 | module TLMonitor_26( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98184:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98184 | module ram_2x189( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98203:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98203 | module Queue2_TLBundleA_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98283:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98283 | module ram_2x142( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98302:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98302 | module Queue2_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98381 | module Queue2_TLBundleA_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98459 | module Queue2_TLBundleD_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98539 | module ram_2x60( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98558:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98558 | module Queue2_TLBundleB_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98622:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98622 | module ram_2x173( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98641:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98641 | module Queue2_TLBundleC_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98716:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98716 | module ram_sink_2x1( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98735:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98735 | module Queue2_TLBundleE_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98781 | module TLBuffer_a32d128s2k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99162:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99162 | module IntSyncSyncCrossingSink_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99173:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99173 | module IntSyncSyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99181:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99181 | module TilePRCIDomain( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99589:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99589 | module BundleBridgeNexus_UInt1_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99597:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99597 | module TLMonitor_27( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100216:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100216 | module CLINT( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100337 | module AsyncResetRegVec_w2_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100366:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100366 | module IntSyncCrossingSource_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100386 | module CLINTClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100449 | module TLMonitor_28( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101080:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101080 | module LevelGateway( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101099:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101099 | module PLICFanIn( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101111:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101111 | module Queue1_RegMapperInput_i23_m8( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101160 | module TLPLIC( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101389:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101389 | module PLICClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101452:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101452 | module TLMonitor_29( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101973 | module TLROM( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:102530:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102530 | module bootromClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:102569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102569 | module ToyLinuxSystem( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103817:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103817 | module ToyLinuxChip( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103984:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103984 | module tag_array( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104007:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104007 | module array_0_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104034:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104034 | module array_0_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104059 | module array_2_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104084:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104084 | module array_2_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104109:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104109 | module bbtile_icache_tag_array( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104132:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104132 | module bbtile_icache_data_arrays_0( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104155 | module bbtile_icache_data_arrays_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104176:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104176 | module bbtile_icache_data_arrays_2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104197:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104197 | module bbtile_icache_data_arrays_3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104218 | module robOperands( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104243:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104243 | module sram( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104268:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104268 | module mem( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104301 | module plusarg_reader #( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104326:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104326 | module ITraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104404:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104404 | module FpgaDspMac(input [7:0] a, b, input [19:0] c, output [19:0] y); + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104414 | module PMCTraceDPI( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104464:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104464 | module MemPMCTraceDPI( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104514:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104514 | module MTraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:1:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 1 | module tag_array_ext( input [4:0] RW0_addr, + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 19 | module array_0_0_ext( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:37:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 37 | module bbtile_icache_tag_array_ext( input [5:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:55:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 55 | module bbtile_icache_data_arrays_0_ext( input [7:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:73:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 73 | module robOperands_ext( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:90:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 90 | module sram_ext( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 107 | module mem_ext( input [9:0] RW0_addr, + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:3:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3 | module axi_smoke_memory #( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_tx.sv:27:15: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.transmitter' + 27 | count <= DIVISOR - 1; + | ^~ + ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=5.050 + ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_tx.sv:32:13: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.transmitter' + 32 | count <= DIVISOR - 1; + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_rx.sv:23:55: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.receiver' + 23 | IDLE: if (!rx_sync) begin state <= START; count <= DIVISOR/2 - 1; end + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_rx.sv:26:57: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.receiver' + 26 | else begin state <= DATA; bit_index <= 0; count <= DIVISOR - 1; end + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_rx.sv:29:46: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.receiver' + 29 | shift[bit_index] <= rx_sync; count <= DIVISOR - 1; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:32:43: Operator ADD expects 33 bits on the RHS, but RHS's VARREF 'length' generates 16 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 32 | wire [32:0] end_address = {1'b0,address}+length; + | ^ + ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=5.050 + ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:35:38: Operator ADD expects 32 bits on the RHS, but RHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 35 | wire [31:0] byte_address = address + cursor; + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:67:32: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's SHIFTR generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 67 | 11,12,13,14:tx_data=RAM_BYTES >> ((reply_index-11)*8); + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:68:32: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's SHIFTR generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 68 | 15,16,17,18:tx_data=CLOCK_HZ >> ((reply_index-15)*8); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:73:28: Operator EQ expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 73 | else if(reply_index==7+reply_length) tx_data=crc[7:0]; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:64:23: Operator LT expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 64 | if(reply_index<7+reply_length) begin + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:119:20: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 119 | if(cursor+1==length) state<=CRC0; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:144:25: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 144 | else if(cursor+1==length) begin image_loaded<=1;state<=REPLY;end + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:152:20: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 152 | if(cursor+1==length) state<=REPLY; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:157:43: Operator LT expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 157 | if(reply_index>=2 && reply_index<7+reply_length) crc<=crc_next(crc,tx_data); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:158:25: Operator EQ expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 158 | if(reply_index==8+reply_length) state<=DRAIN; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:87:37: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'timeout_count' generates 22 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 87 | if((receiving && timeout_count==RX_TIMEOUT-1) || (receiving && rx_error)) begin + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:52:20: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'addr' generates 28 bits. + : ... note: In instance 'tb_board_cpu.memory' + 52 | offset=(addr & ~(LANES-1))-BASE; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:78:28: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'write_addr' generates 28 bits. + : ... note: In instance 'tb_board_cpu.memory' + 78 | offset=(write_addr & ~(LANES-1))-BASE; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:86:26: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'h600d600d' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 86 | if (w_bits_data==64'h600d600d) begin + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:91:66: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 91 | $fatal(1,"CPU smoke failed at stage %0d",w_bits_data & 64'hffff); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:90:28: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff0000' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:90:43: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'hbad00000' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^~ +make: Entering directory '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/obj' +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_timing.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_timing.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_threads.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_threads.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb_board_cpu__pch.h -o Vtb_board_cpu__pch.h.fast.gch +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb_board_cpu__pch.h -o Vtb_board_cpu__pch.h.slow.gch +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__0.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__1.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__2.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__3.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__4.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__5.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__6.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__7.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__8.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__9.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu__main.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu__ConstPool__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__1__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__2__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__3__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu__Syms__Slow.cpp +g++ verilated.o verilated_timing.o verilated_threads.o Vtb_board_cpu__ALL.a -pthread -lpthread -latomic -o Vtb_board_cpu +rm Vtb_board_cpu__ALL.verilator_deplist.tmp +make: Leaving directory '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/obj' +- V e r i l a t i o n R e p o r t: Verilator 5.050 2026-07-01 rev v5.050 +- Verilator: Built from 46.540 MB sources in 354 modules, into 26.450 MB in 19 C++ files needing 0.019 MB +- Verilator: Walltime 13.525 s (elab=0.591, cvt=3.838, bld=8.460); cpu 5.373 s on 8 threads; allocated 565.281 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-loop/program.bin b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-loop/program.bin new file mode 100644 index 0000000..d985179 Binary files /dev/null and b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-loop/program.bin differ diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-loop/simulation.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-loop/simulation.log new file mode 100644 index 0000000..e52914c --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-loop/simulation.log @@ -0,0 +1,5 @@ +PASS CPU Sv39/FPU/AMO/cache/interrupt through board AXI/SCU cycles=684219 +- /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-loop/tb_board_cpu.sv:56: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 7ms; walltime 5.045 s; speed 1.356 ms/s +- Verilator: cpu 5.045 s on 1 threads; allocated 8 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-loop/smoke.bin b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-loop/smoke.bin new file mode 100644 index 0000000..d985179 Binary files /dev/null and b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-loop/smoke.bin differ diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-loop/smoke.hex b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-loop/smoke.hex new file mode 100644 index 0000000..2139bdc --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-loop/smoke.hex @@ -0,0 +1,987 @@ +37 +21 +00 +00 +1b +01 +11 +00 +13 +11 +21 +01 +13 +01 +01 +ff +97 +02 +00 +00 +93 +82 +c2 +04 +73 +90 +52 +30 +73 +10 +40 +30 +73 +10 +20 +30 +b7 +e2 +01 +00 +73 +a0 +02 +30 +97 +00 +00 +00 +e7 +80 +00 +05 +b7 +02 +00 +60 +37 +63 +0d +60 +1b +03 +d3 +00 +63 +0a +05 +00 +37 +13 +00 +00 +1b +03 +d3 +ba +13 +13 +43 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+`timescale 1ns/1ps +module tb_board_cpu; + reg clk=0;always #5 clk=~clk; + reg reset=1,uart_rx_in=1; + wire uart_tx_out; + wire cpu_run; + wire exited; + wire loader_error; + wire [31:0] exit_code; + wire [3:0] ddr_awid; + wire [27:0] ddr_awaddr; + wire [7:0] ddr_awlen; + wire [2:0] ddr_awsize; + wire [1:0] ddr_awburst; + wire ddr_awvalid; + wire ddr_awready; + wire [127:0] ddr_wdata; + wire [15:0] ddr_wstrb; + wire ddr_wlast; + wire ddr_wvalid; + wire ddr_wready; + wire [3:0] ddr_bid; + wire [1:0] ddr_bresp; + wire ddr_bvalid; + wire ddr_bready; + wire [3:0] ddr_arid; + wire [27:0] ddr_araddr; + wire [7:0] ddr_arlen; + wire [2:0] ddr_arsize; + wire [1:0] ddr_arburst; + wire ddr_arvalid; + wire ddr_arready; + wire [3:0] ddr_rid; + wire [127:0] ddr_rdata; + wire [1:0] ddr_rresp; + wire ddr_rlast; + wire ddr_rvalid; + wire ddr_rready; + wire flash_miso; + wire flash_recovery; + wire flash_mosi; + wire flash_sck; + wire flash_cs_n; + toy_a7_platform platform(.*); + initial begin + repeat(10) @(negedge clk); force platform.loader.cpu_run=1;reset=0;end + integer cycles=0; + always @(posedge clk) if(!reset) begin + cycles<=cycles+1; + if(platform.memory_aw_valid && platform.memory_aw_bits_lock) $fatal(1,"Unexpected AXI exclusive write"); + if(platform.memory_ar_valid && platform.memory_ar_bits_lock) $fatal(1,"Unexpected AXI exclusive read"); + if(ddr_awvalid && ddr_awready && (ddr_awsize!=4 || ddr_awlen!=0)) $fatal(1,"Narrow DDR write"); + if(ddr_arvalid && ddr_arready && (ddr_arsize!=4 || ddr_arlen!=0)) $fatal(1,"Narrow DDR read"); + if(exited && (exit_code & 32'hffff0000)==32'hbad00000) $fatal(1,"CPU oracle failed stage=%h",exit_code); + if(exited && exit_code==32'h600d600d) begin + $display("PASS CPU Sv39/FPU/AMO/cache/interrupt through board AXI/SCU cycles=%0d",cycles);$finish;end + if(cycles>4000000) $fatal(1,"Board CPU watchdog"); + end + axi_smoke_memory #(.ADDR_BITS(28),.BASE(0),.CAPACITY(262144),.IMAGE("smoke.hex")) memory ( + .clock(clk), + .reset(reset), + .aw_bits_id(ddr_awid), + .aw_bits_addr(ddr_awaddr), + .aw_bits_len(ddr_awlen), + .aw_bits_size(ddr_awsize), + .aw_bits_burst(ddr_awburst), + .aw_valid(ddr_awvalid), + .aw_ready(ddr_awready), + .w_bits_data(ddr_wdata), + .w_bits_strb(ddr_wstrb), + .w_bits_last(ddr_wlast), + .w_valid(ddr_wvalid), + .w_ready(ddr_wready), + .b_bits_id(ddr_bid), + .b_bits_resp(ddr_bresp), + .b_valid(ddr_bvalid), + .b_ready(ddr_bready), + .ar_bits_id(ddr_arid), + .ar_bits_addr(ddr_araddr), + .ar_bits_len(ddr_arlen), + .ar_bits_size(ddr_arsize), + .ar_bits_burst(ddr_arburst), + .ar_valid(ddr_arvalid), + .ar_ready(ddr_arready), + .r_bits_id(ddr_rid), + .r_bits_data(ddr_rdata), + .r_bits_resp(ddr_rresp), + .r_bits_last(ddr_rlast), + .r_valid(ddr_rvalid), + .r_ready(ddr_rready) + ); +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-mmio-error/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-mmio-error/RESULT.json new file mode 100644 index 0000000..c14463a --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-mmio-error/RESULT.json @@ -0,0 +1,9 @@ +{ + "result": "PASS_CPU_MMIO_SLVERR", + "physical_hardware_tested": false, + "synchronous_traps_observed": 0, + "synchronous_trap_guaranteed": false, + "invalid_address": "0x60030000", + "required_read_write_response": "10", + "binary_sha256": "d1951159e9fe5dc05adfdb2b35eed6ff37eae04c5c255c1e07c853c9c1fa2247" +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-mmio-error/compile.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-mmio-error/compile.log new file mode 100644 index 0000000..4eee68a --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-mmio-error/compile.log @@ -0,0 +1,2197 @@ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 31 | module NonSyncResetSynchronizerPrimitiveShiftReg_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ + ... For warning description see https://verilator.org/warn/TIMESCALEMOD?v=5.050 + ... Use "/* verilator lint_off TIMESCALEMOD */" and lint_on around source to disable this message. +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:48:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 48 | module SynchronizerShiftReg_w1_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:61:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 61 | module IntSyncAsyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:74:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 74 | module AsyncResetRegVec_w1_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 103 | module IntSyncCrossingSource_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:118:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 118 | module FixedClockBroadcast_3( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:139:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 139 | module TLMonitor( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:987:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 987 | module TLMonitor_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:2434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 2434 | module TLXbar_sbus_i2_o3_a32d128s3k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:3195:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3195 | module TLMonitor_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4151 | module Repeater_TLBundleA_a28d128s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4218 | module TLWidthWidget16( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4386 | module TLInterconnectCoupler_sbus_to_bus_named_cbus( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4478:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4478 | module ram_2x58( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4497:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4497 | module Queue2_AXI4BundleAW( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4581:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4581 | module ram_2x73( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4600:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4600 | module Queue2_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4657:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4657 | module ram_2x4( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4676:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4676 | module Queue2_AXI4BundleB( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4729:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4729 | module Queue2_AXI4BundleAR( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4813:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4813 | module ram_2x69( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4832:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4832 | module Queue2_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4891:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4891 | module AXI4Buffer( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5067:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5067 | module ram_2x8( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5086:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5086 | module Queue2_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5143:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5143 | module Queue1_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5178 | module AXI4UserYanker( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5540:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5540 | module ram_8x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5559:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5559 | module Queue8_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5631 | module AXI4Deinterleaver( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:6073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6073 | module AXI4IdIndexer( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:6219:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6219 | module TLMonitor_3( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7048:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7048 | module Queue1_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7082:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7082 | module Queue1_AXI4BundleARW( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7148:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7148 | module TLToAXI4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7529:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7529 | module TLMonitor_4( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8396:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8396 | module Repeater_TLBundleA_a31d128s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8463 | module TLWidthWidget16_2( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8623:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8623 | module TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:9400:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 9400 | module SystemBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10050 | module FixedClockBroadcast_4( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10073 | module TLMonitor_5( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10975:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10975 | module TLXbar_cbus_out_i1_o4_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:11288:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +11288 | module TLMonitor_6( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12202:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12202 | module ram_2x114( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12221 | module Queue2_TLBundleA_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12301 | module ram_2x79( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12320:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12320 | module Queue2_TLBundleD_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12399:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12399 | module TLBuffer_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12534:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12534 | module TLMonitor_7( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:13449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13449 | module TLAtomicAutomata_cbus( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:13973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13973 | module TLMonitor_8( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14799 | module Queue1_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14846:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14846 | module TLError( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14953 | module TLMonitor_9( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15857 | module ram_2x100( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15876:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15876 | module Queue2_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15955:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15955 | module Queue2_TLBundleD_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16028 | module TLBuffer_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16155 | module ErrorDeviceWrapper( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16258 | module TLMonitor_10( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17017:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17017 | module Repeater_TLBundleA_a26d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17081:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17081 | module TLFragmenter_CLINT( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17261:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17261 | module TLInterconnectCoupler_cbus_to_clint( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17336:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17336 | module TLMonitor_11( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18106:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18106 | module Repeater_TLBundleA_a28d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18170:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18170 | module TLFragmenter_PLIC( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18350 | module TLInterconnectCoupler_cbus_to_plic( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18425:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18425 | module TLMonitor_12( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19040 | module Repeater_TLBundleA_a17d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19104:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19104 | module TLFragmenter_bootrom( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19263:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19263 | module TLInterconnectCoupler_cbus_to_bootrom( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19330:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19330 | module PeripheryBus_cbus( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19882 | module TLMonitor_13( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20610:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20610 | module ProbePicker( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20688:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20688 | module ram_2x10( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20707:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20707 | module Queue2_BundleMap_6( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20764:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20764 | module AXI4UserYanker_1( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:21713:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21713 | module AXI4IdIndexer_1( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:21859:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21859 | module TLMonitor_14( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22587:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22587 | module Queue1_AXI4BundleW_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22621 | module Queue1_AXI4BundleARW_1( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22687:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22687 | module TLToAXI4_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:23555:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +23555 | module TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:24031:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24031 | module MemoryBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:24349:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24349 | module TLMonitor_15( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25732:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25732 | module BroadcastFilter( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25756:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25756 | module ram_4x144( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25775:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25775 | module Queue4_TLBroadcastData( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25828:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25828 | module TLBroadcastTracker( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25964:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25964 | module TLBroadcastTracker_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:26100:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26100 | module TLBroadcast( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:26686:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26686 | module TLMonitor_16( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27414 | module BankBinder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27491:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27491 | module CoherenceManagerWrapper( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27669:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27669 | module TLMonitor_17( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29229:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29229 | module TLMonitor_18( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29635:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29635 | module TLXbar_MasterXbar_BBTile_i2_o1_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29898 | module IntXbar_i4_o1( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29918:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29918 | module WritebackUnit( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30014:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30014 | module ProbeUnit( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30154:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30154 | module Arbiter1_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30168:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30168 | module Arbiter1_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30191 | module Arbiter1_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30214 | module Arbiter1_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30249:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30249 | module Arbiter1_Bool( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30258 | module ram_16x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30277:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30277 | module Queue16_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30360:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30360 | module Queue1_TLBundleE_a32d128s1k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30388:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30388 | module MSHR( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30835:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30835 | module Arbiter1_HellaCacheResp( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30879:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30879 | module IOMSHR( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31790:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31790 | module sdq_17x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31809 | module MSHRFile( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32350 | module OptimizationBarrier_TLBEntryData( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32406:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32406 | module PMPChecker_s3( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32691:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32691 | module PMAChecker( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32731:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32731 | module DTLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:35923:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35923 | module L1MetadataArray( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:35990:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35990 | module Arbiter5_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36023:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36023 | module Arbiter2_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36055 | module DataArray( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36151 | module Arbiter4_L1DataReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36180:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36180 | module Arbiter2_L1DataWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36206:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36206 | module AMOALU( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36248:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36248 | module MaxPeriodFibonacciLFSR( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36342:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36342 | module Arbiter2_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36377:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36377 | module NonBlockingDCache( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:37660:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37660 | module ICache( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:37914:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37914 | module ShiftQueue( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:38054:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38054 | module PMPChecker_s2( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:38215:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38215 | module ITLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:41129:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41129 | module Frontend( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:41494:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41494 | module TLMonitor_19( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:42301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +42301 | module TLMonitor_20( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43108:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43108 | module TLXbar_i2_o1_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43343 | module TLMonitor_21( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43851:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43851 | module ram_2x116( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43870:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43870 | module Queue2_TLBundleA_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43947:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43947 | module ram_2x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43966:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43966 | module Queue2_TLBundleD_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44045:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44045 | module TLBuffer_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44158:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44158 | module TLMonitor_22( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44783 | module TLBuffer_a32d64s1k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44892:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44892 | module TLMonitor_23( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:45699:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45699 | module Repeater_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:45766:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45766 | module TLWidthWidget8_4( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46074:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46074 | module TLMonitor_24( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46882 | module ram_2x117( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46901:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46901 | module Queue2_TLBundleA_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46981:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46981 | module ram_2x78( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47000:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47000 | module Queue2_TLBundleD_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47079:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47079 | module TLBuffer_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47214 | module HellaCacheArbiter( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47381 | module Arbiter3_Valid_PTWReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47419:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47419 | module OptimizationBarrier_UInt( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47427 | module OptimizationBarrier_PTE( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47459 | module PTW( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:48434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +48434 | module FPUDecoder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49794:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49794 | module CompareRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49824:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49824 | module RecFNToIN_e11_s53_i64( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49873:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49873 | module RecFNToIN_e11_s53_i32( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49912:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49912 | module FPToInt( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50375:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50375 | module RoundAnyRawFNToRecFN_ie7_is64_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50410:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50410 | module PipelinedINToRecFN( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50513:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50513 | module RoundAnyRawFNToRecFN_ie7_is64_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50539 | module PipelinedINToRecFN_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50614 | module RoundAnyRawFNToRecFN_ie7_is64_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50642:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50642 | module PipelinedINToRecFN_2( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50717 | module IntToFP( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51072:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51072 | module RoundAnyRawFNToRecFN_ie11_is53_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51199:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51199 | module RecFNToRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51221 | module RoundAnyRawFNToRecFN_ie11_is53_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51321:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51321 | module RecFNToRecFN_1( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51343 | module FPToFP( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51469:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51469 | module MulAddRecFNToRaw_preMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51569 | module MulAddRecFNToRaw_postMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51822:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51822 | module RoundAnyRawFNToRecFN_ie11_is55_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51953 | module RoundAnyRawFNToRecFN_ie11_is55_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52060:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52060 | module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52194:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52194 | module SharedMulAddRecFNPipe( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52551:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52551 | module FPUSharedFMAPipe( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52682:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52682 | module DivSqrtRawFN_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52852:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52852 | module DivSqrtRecFMToRaw_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52907:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52907 | module RoundAnyRawFNToRecFN_ie5_is13_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53039:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53039 | module RoundRawFNToRecFN_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53068:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53068 | module DivSqrtRecFM_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53128:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53128 | module DivSqrtRawFN_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53297:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53297 | module DivSqrtRecFMToRaw_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53352:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53352 | module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53456:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53456 | module RoundRawFNToRecFN_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53485:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53485 | module DivSqrtRecFM_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53545:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53545 | module DivSqrtRawFN_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53715:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53715 | module DivSqrtRecFMToRaw_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53770:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53770 | module RoundRawFNToRecFN_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53799 | module DivSqrtRecFM_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53860:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53860 | module regfile_32x65( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53905:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53905 | module FPU( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:54820:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +54820 | module RVCExpander( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:55183:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55183 | module IBuf( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:55307:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55307 | module CSRFile( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:57223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57223 | module RocketALU( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:57809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57809 | module MulDiv( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:58107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58107 | module Arbiter3_LLWB( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:58125:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58125 | module rf_31x64( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:58149:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58149 | module RocketBB( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62838:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62838 | module GlobalDecoder( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62928:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62928 | module BankAliasTable( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:64252:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64252 | module BankScoreboard( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:64627:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64627 | module GlobalROB( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68674:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68674 | module Arbiter3_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68717 | module ram_16x4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68736:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68736 | module Queue16_UInt4( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68782:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68782 | module SubROB( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:69357:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69357 | module Arbiter1_SubRobRow( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:69722:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69722 | module GlobalScheduler( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:70973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +70973 | module BootRom( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:71013:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71013 | module Frontend_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:71637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71637 | module PE( + | ^~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:71656:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71656 | module AlwaysOutTransposer( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72411:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72411 | module MacUnit( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72426:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72426 | module PE_64( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72524:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72524 | module Tile( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72571:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72571 | module Mesh( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76050 | module TagQueue( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76191 | module ram_6x7( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76210:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76210 | module Queue6_TagWithIdAndTotalRows( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76271:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76271 | module MeshWithDelays( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77318:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77318 | module ram_data_8x64( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77337 | module Queue8_SramReadResp( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77385:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77385 | module GemminiExCtrl( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79354:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79354 | module LoopMatmulUnroller( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79637 | module LoopConvAddrGen( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79690:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79690 | module LoopConvUnroller( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:80113:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80113 | module LoopCmdEncoder( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:80402:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80402 | module Arbiter2_LoopCmd( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:80598:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80598 | module GemminiBall( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:81783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81783 | module RRArbiter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:81857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81857 | module CmdRouter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:81985:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81985 | module BallCyclePMC( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:82095:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82095 | module BBus( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:82898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82898 | module BallDomainDecoder( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83028 | module ram_4x281( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83047:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83047 | module Queue4_BallReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83178 | module Arbiter1_BallRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83198:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83198 | module BallReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83328:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83328 | module BallDomain( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84141:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84141 | module MemDomainDecoder( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84300:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84300 | module ram_4x158( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84319:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84319 | module Queue4_MemReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84421:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84421 | module Arbiter3_MemRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84463 | module MemReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84631 | module MemLoader( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84869:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84869 | module MemStorer( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85122:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85122 | module MemCyclePMC( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85241:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85241 | module TLB( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85621 | module RRArbiter_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85649:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85649 | module BBTLBCluster( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85777 | module StreamReader( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86142:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86142 | module StreamWriter( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86223 | module ZeroLineGenerator( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86264:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86264 | module MemConfiger( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86433:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86433 | module RRArbiter_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86465:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86465 | module MemGroupQueryArbiter( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86543:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86543 | module MemFrontend( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87160 | module MemMidend( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87621 | module SramBank( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87672:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87672 | module AccPipe( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87781 | module PrivateMemBackend( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:90777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +90777 | module MemBackend( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:91055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91055 | module MemDomain( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:91973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91973 | module Queue1_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92008:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92008 | module GpDomain( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92040 | module ram_8x21( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92059 | module Queue8_BuckyballAccelerator_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92123:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92123 | module BuckyballAccelerator( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93569 | module Queue3_UInt2( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93614 | module SimpleHellaCacheIFReplayQueue( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93667:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93667 | module Arbiter2_HellaCacheReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93678:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93678 | module SimpleHellaCacheIF( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93768:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93768 | module BarrierUnit( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93785:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93785 | module BBTile( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:95579:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +95579 | module TLMonitor_25( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:96427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +96427 | module TLMonitor_26( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98184:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98184 | module ram_2x189( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98203:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98203 | module Queue2_TLBundleA_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98283:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98283 | module ram_2x142( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98302:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98302 | module Queue2_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98381 | module Queue2_TLBundleA_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98459 | module Queue2_TLBundleD_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98539 | module ram_2x60( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98558:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98558 | module Queue2_TLBundleB_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98622:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98622 | module ram_2x173( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98641:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98641 | module Queue2_TLBundleC_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98716:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98716 | module ram_sink_2x1( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98735:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98735 | module Queue2_TLBundleE_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98781 | module TLBuffer_a32d128s2k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99162:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99162 | module IntSyncSyncCrossingSink_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99173:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99173 | module IntSyncSyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99181:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99181 | module TilePRCIDomain( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99589:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99589 | module BundleBridgeNexus_UInt1_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99597:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99597 | module TLMonitor_27( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100216:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100216 | module CLINT( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100337 | module AsyncResetRegVec_w2_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100366:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100366 | module IntSyncCrossingSource_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100386 | module CLINTClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100449 | module TLMonitor_28( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101080:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101080 | module LevelGateway( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101099:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101099 | module PLICFanIn( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101111:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101111 | module Queue1_RegMapperInput_i23_m8( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101160 | module TLPLIC( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101389:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101389 | module PLICClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101452:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101452 | module TLMonitor_29( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101973 | module TLROM( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:102530:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102530 | module bootromClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:102569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102569 | module ToyLinuxSystem( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103817:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103817 | module ToyLinuxChip( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103984:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103984 | module tag_array( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104007:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104007 | module array_0_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104034:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104034 | module array_0_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104059 | module array_2_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104084:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104084 | module array_2_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104109:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104109 | module bbtile_icache_tag_array( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104132:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104132 | module bbtile_icache_data_arrays_0( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104155 | module bbtile_icache_data_arrays_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104176:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104176 | module bbtile_icache_data_arrays_2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104197:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104197 | module bbtile_icache_data_arrays_3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104218 | module robOperands( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104243:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104243 | module sram( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104268:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104268 | module mem( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104301 | module plusarg_reader #( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104326:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104326 | module ITraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104404:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104404 | module FpgaDspMac(input [7:0] a, b, input [19:0] c, output [19:0] y); + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104414 | module PMCTraceDPI( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104464:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104464 | module MemPMCTraceDPI( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104514:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104514 | module MTraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:1:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 1 | module tag_array_ext( input [4:0] RW0_addr, + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 19 | module array_0_0_ext( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:37:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 37 | module bbtile_icache_tag_array_ext( input [5:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:55:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 55 | module bbtile_icache_data_arrays_0_ext( input [7:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:73:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 73 | module robOperands_ext( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:90:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 90 | module sram_ext( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 107 | module mem_ext( input [9:0] RW0_addr, + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:3:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3 | module axi_smoke_memory #( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_tx.sv:27:15: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_mmio_error.platform.transmitter' + 27 | count <= DIVISOR - 1; + | ^~ + ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=5.050 + ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_tx.sv:32:13: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_mmio_error.platform.transmitter' + 32 | count <= DIVISOR - 1; + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_rx.sv:23:55: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_mmio_error.platform.receiver' + 23 | IDLE: if (!rx_sync) begin state <= START; count <= DIVISOR/2 - 1; end + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_rx.sv:26:57: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_mmio_error.platform.receiver' + 26 | else begin state <= DATA; bit_index <= 0; count <= DIVISOR - 1; end + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_rx.sv:29:46: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_mmio_error.platform.receiver' + 29 | shift[bit_index] <= rx_sync; count <= DIVISOR - 1; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:32:43: Operator ADD expects 33 bits on the RHS, but RHS's VARREF 'length' generates 16 bits. + : ... note: In instance 'tb_mmio_error.platform.loader' + 32 | wire [32:0] end_address = {1'b0,address}+length; + | ^ + ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=5.050 + ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:35:38: Operator ADD expects 32 bits on the RHS, but RHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_mmio_error.platform.loader' + 35 | wire [31:0] byte_address = address + cursor; + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:67:32: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's SHIFTR generates 32 bits. + : ... note: In instance 'tb_mmio_error.platform.loader' + 67 | 11,12,13,14:tx_data=RAM_BYTES >> ((reply_index-11)*8); + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:68:32: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's SHIFTR generates 32 bits. + : ... note: In instance 'tb_mmio_error.platform.loader' + 68 | 15,16,17,18:tx_data=CLOCK_HZ >> ((reply_index-15)*8); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:73:28: Operator EQ expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_mmio_error.platform.loader' + 73 | else if(reply_index==7+reply_length) tx_data=crc[7:0]; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:64:23: Operator LT expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_mmio_error.platform.loader' + 64 | if(reply_index<7+reply_length) begin + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:119:20: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_mmio_error.platform.loader' + 119 | if(cursor+1==length) state<=CRC0; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:144:25: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_mmio_error.platform.loader' + 144 | else if(cursor+1==length) begin image_loaded<=1;state<=REPLY;end + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:152:20: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_mmio_error.platform.loader' + 152 | if(cursor+1==length) state<=REPLY; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:157:43: Operator LT expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_mmio_error.platform.loader' + 157 | if(reply_index>=2 && reply_index<7+reply_length) crc<=crc_next(crc,tx_data); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:158:25: Operator EQ expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_mmio_error.platform.loader' + 158 | if(reply_index==8+reply_length) state<=DRAIN; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:87:37: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'timeout_count' generates 22 bits. + : ... note: In instance 'tb_mmio_error.platform.loader' + 87 | if((receiving && timeout_count==RX_TIMEOUT-1) || (receiving && rx_error)) begin + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:52:20: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'addr' generates 28 bits. + : ... note: In instance 'tb_mmio_error.memory' + 52 | offset=(addr & ~(LANES-1))-BASE; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:78:28: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'write_addr' generates 28 bits. + : ... note: In instance 'tb_mmio_error.memory' + 78 | offset=(write_addr & ~(LANES-1))-BASE; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:86:26: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'h600d600d' generates 64 bits. + : ... note: In instance 'tb_mmio_error.memory' + 86 | if (w_bits_data==64'h600d600d) begin + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:91:66: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff' generates 64 bits. + : ... note: In instance 'tb_mmio_error.memory' + 91 | $fatal(1,"CPU smoke failed at stage %0d",w_bits_data & 64'hffff); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:90:28: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff0000' generates 64 bits. + : ... note: In instance 'tb_mmio_error.memory' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:90:43: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'hbad00000' generates 64 bits. + : ... note: In instance 'tb_mmio_error.memory' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:99:12: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's SEL generates 16 bits. + : ... note: In instance 'tb_mmio_error' + 99 | traps=exit_code[15:0];$display("MMIO_SYNCHRONOUS_TRAPS %0d",traps); + | ^ +make: Entering directory '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/obj' +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_timing.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_timing.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_threads.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_threads.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb_mmio_error__pch.h -o Vtb_mmio_error__pch.h.fast.gch +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb_mmio_error__pch.h -o Vtb_mmio_error__pch.h.slow.gch +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_mmio_error__pch.h.fast -c Vtb_mmio_error.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_mmio_error__pch.h.fast -c Vtb_mmio_error___024root__0.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_mmio_error__pch.h.fast -c Vtb_mmio_error___024root__1.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_mmio_error__pch.h.fast -c Vtb_mmio_error___024root__2.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_mmio_error__pch.h.fast -c Vtb_mmio_error___024root__3.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_mmio_error__pch.h.fast -c Vtb_mmio_error___024root__4.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_mmio_error__pch.h.fast -c Vtb_mmio_error___024root__5.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_mmio_error__pch.h.fast -c Vtb_mmio_error___024root__6.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_mmio_error__pch.h.fast -c Vtb_mmio_error___024root__7.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_mmio_error__pch.h.fast -c Vtb_mmio_error___024root__8.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_mmio_error__pch.h.fast -c Vtb_mmio_error___024root__9.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_mmio_error__pch.h.fast -c Vtb_mmio_error__main.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_mmio_error__pch.h.slow -c Vtb_mmio_error__ConstPool__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_mmio_error__pch.h.slow -c Vtb_mmio_error___024root__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_mmio_error__pch.h.slow -c Vtb_mmio_error___024root__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_mmio_error__pch.h.slow -c Vtb_mmio_error___024root__1__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_mmio_error__pch.h.slow -c Vtb_mmio_error___024root__2__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_mmio_error__pch.h.slow -c Vtb_mmio_error___024root__3__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_mmio_error__pch.h.slow -c Vtb_mmio_error__Syms__Slow.cpp +g++ verilated.o verilated_timing.o verilated_threads.o Vtb_mmio_error__ALL.a -pthread -lpthread -latomic -o Vtb_mmio_error +rm Vtb_mmio_error__ALL.verilator_deplist.tmp +make: Leaving directory '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/obj' +- V e r i l a t i o n R e p o r t: Verilator 5.050 2026-07-01 rev v5.050 +- Verilator: Built from 46.552 MB sources in 354 modules, into 26.554 MB in 19 C++ files needing 0.019 MB +- Verilator: Walltime 18.767 s (elab=0.635, cvt=3.824, bld=13.634); cpu 5.397 s on 4 threads; allocated 557.445 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-mmio-error/fault.bin b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-mmio-error/fault.bin new file mode 100644 index 0000000..adb2d4a Binary files /dev/null and b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-mmio-error/fault.bin differ diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-mmio-error/fault.elf b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-mmio-error/fault.elf new file mode 100644 index 0000000..b393893 Binary files /dev/null and b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-mmio-error/fault.elf differ diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-mmio-error/fault.hex b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-mmio-error/fault.hex new file mode 100644 index 0000000..c3dc26c --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-mmio-error/fault.hex @@ -0,0 +1,164 @@ +97 +02 +00 +00 +93 +82 +02 +05 +73 +90 +52 +30 +73 +10 +20 +30 +73 +10 +40 +30 +93 +04 +00 +00 +b7 +02 +03 +60 +23 +b0 +02 +00 +0f +00 +f0 +0f +03 +b3 +02 +00 +0f +00 +f0 +0f +b7 +02 +00 +60 +37 +03 +00 +74 +33 +63 +93 +00 +23 +b0 +62 +00 +b7 +02 +00 +60 +37 +63 +0d +60 +1b +03 +d3 +00 +23 +b0 +62 +00 +6f +00 +00 +00 +73 +25 +20 +34 +13 +06 +50 +00 +63 +06 +c5 +00 +13 +06 +70 +00 +63 +14 +c5 +02 +f3 +25 +30 +34 +63 +86 +05 +00 +37 +06 +03 +60 +63 +9c +c5 +00 +93 +84 +14 +00 +73 +25 +10 +34 +13 +05 +45 +00 +73 +10 +15 +34 +73 +00 +20 +30 +b7 +02 +00 +60 +37 +13 +00 +00 +1b +03 +d3 +ba +13 +13 +43 +01 +13 +03 +73 +00 +23 +b0 +62 +00 +6f +00 +00 +00 diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-mmio-error/simulation.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-mmio-error/simulation.log new file mode 100644 index 0000000..a6020f9 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-mmio-error/simulation.log @@ -0,0 +1,6 @@ +MMIO_SYNCHRONOUS_TRAPS 0 +PASS MMIO_ERROR CPU AXI/SCU response delivery cycles=208 +- /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:57: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 2us; walltime 0.002 s; speed 1.005 ms/s +- Verilator: cpu 0.002 s on 1 threads; allocated 8 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-mmio-error/tb_mmio_error.sv b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-mmio-error/tb_mmio_error.sv new file mode 100644 index 0000000..61e125f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-mmio-error/tb_mmio_error.sv @@ -0,0 +1,115 @@ +`timescale 1ns/1ps +module tb_mmio_error; + reg clk=0;always #5 clk=~clk; + reg reset=1,uart_rx_in=1; + wire uart_tx_out; + wire cpu_run; + wire exited; + wire loader_error; + wire [31:0] exit_code; + wire [3:0] ddr_awid; + wire [27:0] ddr_awaddr; + wire [7:0] ddr_awlen; + wire [2:0] ddr_awsize; + wire [1:0] ddr_awburst; + wire ddr_awvalid; + wire ddr_awready; + wire [127:0] ddr_wdata; + wire [15:0] ddr_wstrb; + wire ddr_wlast; + wire ddr_wvalid; + wire ddr_wready; + wire [3:0] ddr_bid; + wire [1:0] ddr_bresp; + wire ddr_bvalid; + wire ddr_bready; + wire [3:0] ddr_arid; + wire [27:0] ddr_araddr; + wire [7:0] ddr_arlen; + wire [2:0] ddr_arsize; + wire [1:0] ddr_arburst; + wire ddr_arvalid; + wire ddr_arready; + wire [3:0] ddr_rid; + wire [127:0] ddr_rdata; + wire [1:0] ddr_rresp; + wire ddr_rlast; + wire ddr_rvalid; + wire ddr_rready; + wire flash_miso; + wire flash_recovery; + wire flash_mosi; + wire flash_sck; + wire flash_cs_n; + toy_a7_platform platform(.*); + initial begin + repeat(10) @(negedge clk); force platform.loader.cpu_run=1;reset=0;end + integer cycles=0; + always @(posedge clk) if(!reset) begin + cycles<=cycles+1; + if(platform.memory_aw_valid && platform.memory_aw_bits_lock) $fatal(1,"Unexpected AXI exclusive write"); + if(platform.memory_ar_valid && platform.memory_ar_bits_lock) $fatal(1,"Unexpected AXI exclusive read"); + if(ddr_awvalid && ddr_awready && (ddr_awsize!=4 || ddr_awlen!=0)) $fatal(1,"Narrow DDR write"); + if(ddr_arvalid && ddr_arready && (ddr_arsize!=4 || ddr_arlen!=0)) $fatal(1,"Narrow DDR read"); + if(exited && (exit_code & 32'hffff0000)==32'hbad00000) $fatal(1,"CPU oracle failed stage=%h",exit_code); + if(exited && exit_code==32'h600d600d) begin + if(bad_b!=1 || bad_r!=1) $fatal(1,"Fault did not traverse AXI/SCU"); + $display("PASS MMIO_ERROR CPU AXI/SCU response delivery cycles=%0d",cycles);$finish;end + if(cycles>4000000) $fatal(1,"Board CPU watchdog"); + end + axi_smoke_memory #(.ADDR_BITS(28),.BASE(0),.CAPACITY(262144),.IMAGE("fault.hex")) memory ( + .clock(clk), + .reset(reset), + .aw_bits_id(ddr_awid), + .aw_bits_addr(ddr_awaddr), + .aw_bits_len(ddr_awlen), + .aw_bits_size(ddr_awsize), + .aw_bits_burst(ddr_awburst), + .aw_valid(ddr_awvalid), + .aw_ready(ddr_awready), + .w_bits_data(ddr_wdata), + .w_bits_strb(ddr_wstrb), + .w_bits_last(ddr_wlast), + .w_valid(ddr_wvalid), + .w_ready(ddr_wready), + .b_bits_id(ddr_bid), + .b_bits_resp(ddr_bresp), + .b_valid(ddr_bvalid), + .b_ready(ddr_bready), + .ar_bits_id(ddr_arid), + .ar_bits_addr(ddr_araddr), + .ar_bits_len(ddr_arlen), + .ar_bits_size(ddr_arsize), + .ar_bits_burst(ddr_arburst), + .ar_valid(ddr_arvalid), + .ar_ready(ddr_arready), + .r_bits_id(ddr_rid), + .r_bits_data(ddr_rdata), + .r_bits_resp(ddr_rresp), + .r_bits_last(ddr_rlast), + .r_valid(ddr_rvalid), + .r_ready(ddr_rready) + ); + + reg bad_write=0,bad_read=0; + integer bad_b=0,bad_r=0; + integer traps=-1; + always @(posedge clk) if(!reset) begin + if(exited && exit_code[31:16]==16'h7400 && traps<0) begin + traps=exit_code[15:0];$display("MMIO_SYNCHRONOUS_TRAPS %0d",traps); + end + if(platform.peripherals_aw_valid && platform.peripherals_aw_ready) + bad_write<=platform.peripherals_aw_bits_addr==31'h60030000; + if(platform.peripherals_ar_valid && platform.peripherals_ar_ready) + bad_read<=platform.peripherals_ar_bits_addr==31'h60030000; + if(platform.peripherals_b_valid && platform.peripherals_b_ready && bad_write) begin + if(platform.chip.peripherals_b_bits_resp!==2'b10) $fatal(1,"CPU did not receive SLVERR"); + bad_b<=bad_b+1;bad_write<=0; + end + if(platform.peripherals_r_valid && platform.peripherals_r_ready && bad_read) begin + if(platform.chip.peripherals_r_bits_resp!==2'b10) $fatal(1,"CPU did not receive read error"); + bad_r<=bad_r+1;bad_read<=0; + end + end + +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-uart-boot/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-uart-boot/RESULT.json new file mode 100644 index 0000000..ba18d86 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-uart-boot/RESULT.json @@ -0,0 +1,11 @@ +{ + "result": "PASS_UART_LOAD_VERIFY_BOOT", + "binary_sha256": "3bbf33f7bf2b6bb0f3888ab4a649a11272de3f74458f6ea36b266f9670df75f5", + "bytes_verified": 110592, + "testbench_cpu_release_override": false, + "preloaded_ddr_image": false, + "physical_mig_simulated": false, + "physical_board_tested": false, + "flash_rom_recovery": false, + "cycles": 61853990 +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-uart-boot/compile.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-uart-boot/compile.log new file mode 100644 index 0000000..aa20d77 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-uart-boot/compile.log @@ -0,0 +1,2210 @@ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 31 | module NonSyncResetSynchronizerPrimitiveShiftReg_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ + ... For warning description see https://verilator.org/warn/TIMESCALEMOD?v=5.050 + ... Use "/* verilator lint_off TIMESCALEMOD */" and lint_on around source to disable this message. +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:48:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 48 | module SynchronizerShiftReg_w1_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:61:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 61 | module IntSyncAsyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:74:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 74 | module AsyncResetRegVec_w1_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 103 | module IntSyncCrossingSource_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:118:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 118 | module FixedClockBroadcast_3( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:139:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 139 | module TLMonitor( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:987:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 987 | module TLMonitor_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:2434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 2434 | module TLXbar_sbus_i2_o3_a32d128s3k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:3195:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3195 | module TLMonitor_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4151 | module Repeater_TLBundleA_a28d128s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4218 | module TLWidthWidget16( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4386 | module TLInterconnectCoupler_sbus_to_bus_named_cbus( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4478:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4478 | module ram_2x58( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4497:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4497 | module Queue2_AXI4BundleAW( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4581:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4581 | module ram_2x73( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4600:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4600 | module Queue2_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4657:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4657 | module ram_2x4( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4676:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4676 | module Queue2_AXI4BundleB( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4729:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4729 | module Queue2_AXI4BundleAR( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4813:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4813 | module ram_2x69( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4832:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4832 | module Queue2_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4891:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4891 | module AXI4Buffer( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5067:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5067 | module ram_2x8( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5086:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5086 | module Queue2_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5143:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5143 | module Queue1_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5178 | module AXI4UserYanker( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5540:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5540 | module ram_8x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5559:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5559 | module Queue8_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5631 | module AXI4Deinterleaver( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:6073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6073 | module AXI4IdIndexer( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:6219:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6219 | module TLMonitor_3( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7048:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7048 | module Queue1_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7082:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7082 | module Queue1_AXI4BundleARW( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7148:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7148 | module TLToAXI4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7529:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7529 | module TLMonitor_4( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8396:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8396 | module Repeater_TLBundleA_a31d128s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8463 | module TLWidthWidget16_2( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8623:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8623 | module TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:9400:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 9400 | module SystemBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10050 | module FixedClockBroadcast_4( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10073 | module TLMonitor_5( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10975:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10975 | module TLXbar_cbus_out_i1_o4_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:11288:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +11288 | module TLMonitor_6( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12202:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12202 | module ram_2x114( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12221 | module Queue2_TLBundleA_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12301 | module ram_2x79( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12320:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12320 | module Queue2_TLBundleD_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12399:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12399 | module TLBuffer_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12534:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12534 | module TLMonitor_7( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:13449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13449 | module TLAtomicAutomata_cbus( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:13973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13973 | module TLMonitor_8( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14799 | module Queue1_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14846:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14846 | module TLError( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14953 | module TLMonitor_9( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15857 | module ram_2x100( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15876:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15876 | module Queue2_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15955:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15955 | module Queue2_TLBundleD_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16028 | module TLBuffer_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16155 | module ErrorDeviceWrapper( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16258 | module TLMonitor_10( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17017:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17017 | module Repeater_TLBundleA_a26d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17081:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17081 | module TLFragmenter_CLINT( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17261:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17261 | module TLInterconnectCoupler_cbus_to_clint( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17336:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17336 | module TLMonitor_11( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18106:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18106 | module Repeater_TLBundleA_a28d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18170:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18170 | module TLFragmenter_PLIC( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18350 | module TLInterconnectCoupler_cbus_to_plic( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18425:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18425 | module TLMonitor_12( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19040 | module Repeater_TLBundleA_a17d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19104:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19104 | module TLFragmenter_bootrom( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19263:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19263 | module TLInterconnectCoupler_cbus_to_bootrom( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19330:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19330 | module PeripheryBus_cbus( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19882 | module TLMonitor_13( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20610:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20610 | module ProbePicker( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20688:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20688 | module ram_2x10( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20707:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20707 | module Queue2_BundleMap_6( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20764:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20764 | module AXI4UserYanker_1( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:21713:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21713 | module AXI4IdIndexer_1( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:21859:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21859 | module TLMonitor_14( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22587:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22587 | module Queue1_AXI4BundleW_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22621 | module Queue1_AXI4BundleARW_1( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22687:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22687 | module TLToAXI4_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:23555:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +23555 | module TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:24031:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24031 | module MemoryBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:24349:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24349 | module TLMonitor_15( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25732:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25732 | module BroadcastFilter( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25756:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25756 | module ram_4x144( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25775:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25775 | module Queue4_TLBroadcastData( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25828:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25828 | module TLBroadcastTracker( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25964:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25964 | module TLBroadcastTracker_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:26100:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26100 | module TLBroadcast( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:26686:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26686 | module TLMonitor_16( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27414 | module BankBinder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27491:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27491 | module CoherenceManagerWrapper( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27669:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27669 | module TLMonitor_17( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29229:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29229 | module TLMonitor_18( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29635:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29635 | module TLXbar_MasterXbar_BBTile_i2_o1_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29898 | module IntXbar_i4_o1( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29918:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29918 | module WritebackUnit( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30014:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30014 | module ProbeUnit( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30154:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30154 | module Arbiter1_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30168:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30168 | module Arbiter1_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30191 | module Arbiter1_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30214 | module Arbiter1_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30249:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30249 | module Arbiter1_Bool( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30258 | module ram_16x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30277:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30277 | module Queue16_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30360:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30360 | module Queue1_TLBundleE_a32d128s1k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30388:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30388 | module MSHR( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30835:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30835 | module Arbiter1_HellaCacheResp( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30879:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30879 | module IOMSHR( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31790:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31790 | module sdq_17x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31809 | module MSHRFile( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32350 | module OptimizationBarrier_TLBEntryData( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32406:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32406 | module PMPChecker_s3( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32691:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32691 | module PMAChecker( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32731:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32731 | module DTLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:35923:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35923 | module L1MetadataArray( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:35990:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35990 | module Arbiter5_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36023:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36023 | module Arbiter2_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36055 | module DataArray( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36151 | module Arbiter4_L1DataReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36180:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36180 | module Arbiter2_L1DataWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36206:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36206 | module AMOALU( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36248:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36248 | module MaxPeriodFibonacciLFSR( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36342:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36342 | module Arbiter2_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36377:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36377 | module NonBlockingDCache( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:37660:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37660 | module ICache( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:37914:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37914 | module ShiftQueue( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:38054:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38054 | module PMPChecker_s2( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:38215:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38215 | module ITLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:41129:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41129 | module Frontend( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:41494:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41494 | module TLMonitor_19( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:42301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +42301 | module TLMonitor_20( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43108:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43108 | module TLXbar_i2_o1_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43343 | module TLMonitor_21( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43851:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43851 | module ram_2x116( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43870:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43870 | module Queue2_TLBundleA_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43947:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43947 | module ram_2x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43966:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43966 | module Queue2_TLBundleD_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44045:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44045 | module TLBuffer_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44158:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44158 | module TLMonitor_22( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44783 | module TLBuffer_a32d64s1k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44892:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44892 | module TLMonitor_23( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:45699:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45699 | module Repeater_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:45766:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45766 | module TLWidthWidget8_4( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46074:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46074 | module TLMonitor_24( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46882 | module ram_2x117( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46901:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46901 | module Queue2_TLBundleA_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46981:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46981 | module ram_2x78( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47000:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47000 | module Queue2_TLBundleD_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47079:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47079 | module TLBuffer_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47214 | module HellaCacheArbiter( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47381 | module Arbiter3_Valid_PTWReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47419:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47419 | module OptimizationBarrier_UInt( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47427 | module OptimizationBarrier_PTE( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47459 | module PTW( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:48434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +48434 | module FPUDecoder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49794:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49794 | module CompareRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49824:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49824 | module RecFNToIN_e11_s53_i64( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49873:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49873 | module RecFNToIN_e11_s53_i32( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49912:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49912 | module FPToInt( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50375:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50375 | module RoundAnyRawFNToRecFN_ie7_is64_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50410:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50410 | module PipelinedINToRecFN( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50513:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50513 | module RoundAnyRawFNToRecFN_ie7_is64_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50539 | module PipelinedINToRecFN_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50614 | module RoundAnyRawFNToRecFN_ie7_is64_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50642:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50642 | module PipelinedINToRecFN_2( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50717 | module IntToFP( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51072:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51072 | module RoundAnyRawFNToRecFN_ie11_is53_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51199:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51199 | module RecFNToRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51221 | module RoundAnyRawFNToRecFN_ie11_is53_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51321:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51321 | module RecFNToRecFN_1( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51343 | module FPToFP( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51469:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51469 | module MulAddRecFNToRaw_preMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51569 | module MulAddRecFNToRaw_postMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51822:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51822 | module RoundAnyRawFNToRecFN_ie11_is55_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51953 | module RoundAnyRawFNToRecFN_ie11_is55_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52060:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52060 | module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52194:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52194 | module SharedMulAddRecFNPipe( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52551:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52551 | module FPUSharedFMAPipe( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52682:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52682 | module DivSqrtRawFN_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52852:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52852 | module DivSqrtRecFMToRaw_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52907:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52907 | module RoundAnyRawFNToRecFN_ie5_is13_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53039:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53039 | module RoundRawFNToRecFN_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53068:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53068 | module DivSqrtRecFM_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53128:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53128 | module DivSqrtRawFN_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53297:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53297 | module DivSqrtRecFMToRaw_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53352:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53352 | module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53456:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53456 | module RoundRawFNToRecFN_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53485:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53485 | module DivSqrtRecFM_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53545:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53545 | module DivSqrtRawFN_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53715:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53715 | module DivSqrtRecFMToRaw_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53770:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53770 | module RoundRawFNToRecFN_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53799 | module DivSqrtRecFM_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53860:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53860 | module regfile_32x65( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53905:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53905 | module FPU( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:54820:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +54820 | module RVCExpander( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:55183:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55183 | module IBuf( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:55307:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55307 | module CSRFile( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:57223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57223 | module RocketALU( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:57809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57809 | module MulDiv( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:58107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58107 | module Arbiter3_LLWB( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:58125:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58125 | module rf_31x64( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:58149:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58149 | module RocketBB( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62838:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62838 | module GlobalDecoder( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62928:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62928 | module BankAliasTable( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:64252:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64252 | module BankScoreboard( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:64627:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64627 | module GlobalROB( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68674:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68674 | module Arbiter3_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68717 | module ram_16x4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68736:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68736 | module Queue16_UInt4( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68782:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68782 | module SubROB( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:69357:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69357 | module Arbiter1_SubRobRow( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:69722:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69722 | module GlobalScheduler( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:70973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +70973 | module BootRom( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:71013:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71013 | module Frontend_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:71637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71637 | module PE( + | ^~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:71656:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71656 | module AlwaysOutTransposer( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72411:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72411 | module MacUnit( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72426:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72426 | module PE_64( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72524:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72524 | module Tile( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72571:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72571 | module Mesh( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76050 | module TagQueue( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76191 | module ram_6x7( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76210:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76210 | module Queue6_TagWithIdAndTotalRows( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76271:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76271 | module MeshWithDelays( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77318:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77318 | module ram_data_8x64( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77337 | module Queue8_SramReadResp( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77385:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77385 | module GemminiExCtrl( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79354:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79354 | module LoopMatmulUnroller( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79637 | module LoopConvAddrGen( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79690:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79690 | module LoopConvUnroller( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:80113:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80113 | module LoopCmdEncoder( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:80402:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80402 | module Arbiter2_LoopCmd( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:80598:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80598 | module GemminiBall( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:81783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81783 | module RRArbiter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:81857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81857 | module CmdRouter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:81985:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81985 | module BallCyclePMC( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:82095:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82095 | module BBus( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:82898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82898 | module BallDomainDecoder( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83028 | module ram_4x281( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83047:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83047 | module Queue4_BallReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83178 | module Arbiter1_BallRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83198:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83198 | module BallReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83328:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83328 | module BallDomain( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84141:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84141 | module MemDomainDecoder( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84300:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84300 | module ram_4x158( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84319:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84319 | module Queue4_MemReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84421:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84421 | module Arbiter3_MemRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84463 | module MemReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84631 | module MemLoader( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84869:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84869 | module MemStorer( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85122:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85122 | module MemCyclePMC( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85241:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85241 | module TLB( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85621 | module RRArbiter_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85649:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85649 | module BBTLBCluster( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85777 | module StreamReader( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86142:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86142 | module StreamWriter( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86223 | module ZeroLineGenerator( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86264:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86264 | module MemConfiger( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86433:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86433 | module RRArbiter_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86465:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86465 | module MemGroupQueryArbiter( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86543:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86543 | module MemFrontend( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87160 | module MemMidend( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87621 | module SramBank( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87672:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87672 | module AccPipe( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87781 | module PrivateMemBackend( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:90777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +90777 | module MemBackend( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:91055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91055 | module MemDomain( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:91973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91973 | module Queue1_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92008:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92008 | module GpDomain( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92040 | module ram_8x21( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92059 | module Queue8_BuckyballAccelerator_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92123:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92123 | module BuckyballAccelerator( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93569 | module Queue3_UInt2( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93614 | module SimpleHellaCacheIFReplayQueue( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93667:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93667 | module Arbiter2_HellaCacheReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93678:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93678 | module SimpleHellaCacheIF( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93768:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93768 | module BarrierUnit( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93785:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93785 | module BBTile( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:95579:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +95579 | module TLMonitor_25( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:96427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +96427 | module TLMonitor_26( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98184:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98184 | module ram_2x189( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98203:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98203 | module Queue2_TLBundleA_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98283:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98283 | module ram_2x142( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98302:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98302 | module Queue2_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98381 | module Queue2_TLBundleA_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98459 | module Queue2_TLBundleD_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98539 | module ram_2x60( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98558:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98558 | module Queue2_TLBundleB_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98622:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98622 | module ram_2x173( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98641:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98641 | module Queue2_TLBundleC_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98716:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98716 | module ram_sink_2x1( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98735:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98735 | module Queue2_TLBundleE_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98781 | module TLBuffer_a32d128s2k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99162:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99162 | module IntSyncSyncCrossingSink_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99173:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99173 | module IntSyncSyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99181:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99181 | module TilePRCIDomain( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99589:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99589 | module BundleBridgeNexus_UInt1_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99597:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99597 | module TLMonitor_27( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100216:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100216 | module CLINT( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100337 | module AsyncResetRegVec_w2_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100366:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100366 | module IntSyncCrossingSource_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100386 | module CLINTClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100449 | module TLMonitor_28( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101080:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101080 | module LevelGateway( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101099:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101099 | module PLICFanIn( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101111:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101111 | module Queue1_RegMapperInput_i23_m8( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101160 | module TLPLIC( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101389:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101389 | module PLICClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101452:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101452 | module TLMonitor_29( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101973 | module TLROM( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:102530:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102530 | module bootromClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:102569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102569 | module ToyLinuxSystem( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103817:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103817 | module ToyLinuxChip( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103984:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103984 | module tag_array( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104007:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104007 | module array_0_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104034:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104034 | module array_0_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104059 | module array_2_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104084:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104084 | module array_2_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104109:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104109 | module bbtile_icache_tag_array( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104132:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104132 | module bbtile_icache_data_arrays_0( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104155 | module bbtile_icache_data_arrays_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104176:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104176 | module bbtile_icache_data_arrays_2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104197:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104197 | module bbtile_icache_data_arrays_3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104218 | module robOperands( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104243:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104243 | module sram( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104268:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104268 | module mem( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104301 | module plusarg_reader #( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104326:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104326 | module ITraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104404:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104404 | module FpgaDspMac(input [7:0] a, b, input [19:0] c, output [19:0] y); + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104414 | module PMCTraceDPI( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104464:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104464 | module MemPMCTraceDPI( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104514:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104514 | module MTraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:1:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 1 | module tag_array_ext( input [4:0] RW0_addr, + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 19 | module array_0_0_ext( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:37:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 37 | module bbtile_icache_tag_array_ext( input [5:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:55:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 55 | module bbtile_icache_data_arrays_0_ext( input [7:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:73:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 73 | module robOperands_ext( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:90:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 90 | module sram_ext( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 107 | module mem_ext( input [9:0] RW0_addr, + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:3:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3 | module axi_smoke_memory #( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:2:8: ... Location of module with timescale + 2 | module tb_board_uart_boot; + | ^~~~~~~~~~~~~~~~~~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_tx.sv:27:15: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_uart_boot.platform.transmitter' + 27 | count <= DIVISOR - 1; + | ^~ + ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=5.050 + ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_tx.sv:32:13: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_uart_boot.platform.transmitter' + 32 | count <= DIVISOR - 1; + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_rx.sv:23:55: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_uart_boot.platform.receiver' + 23 | IDLE: if (!rx_sync) begin state <= START; count <= DIVISOR/2 - 1; end + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_rx.sv:26:57: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_uart_boot.platform.receiver' + 26 | else begin state <= DATA; bit_index <= 0; count <= DIVISOR - 1; end + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_rx.sv:29:46: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_uart_boot.platform.receiver' + 29 | shift[bit_index] <= rx_sync; count <= DIVISOR - 1; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:32:43: Operator ADD expects 33 bits on the RHS, but RHS's VARREF 'length' generates 16 bits. + : ... note: In instance 'tb_board_uart_boot.platform.loader' + 32 | wire [32:0] end_address = {1'b0,address}+length; + | ^ + ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=5.050 + ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:35:38: Operator ADD expects 32 bits on the RHS, but RHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_uart_boot.platform.loader' + 35 | wire [31:0] byte_address = address + cursor; + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:67:32: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's SHIFTR generates 32 bits. + : ... note: In instance 'tb_board_uart_boot.platform.loader' + 67 | 11,12,13,14:tx_data=RAM_BYTES >> ((reply_index-11)*8); + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:68:32: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's SHIFTR generates 32 bits. + : ... note: In instance 'tb_board_uart_boot.platform.loader' + 68 | 15,16,17,18:tx_data=CLOCK_HZ >> ((reply_index-15)*8); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:73:28: Operator EQ expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_uart_boot.platform.loader' + 73 | else if(reply_index==7+reply_length) tx_data=crc[7:0]; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:64:23: Operator LT expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_uart_boot.platform.loader' + 64 | if(reply_index<7+reply_length) begin + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:119:20: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_uart_boot.platform.loader' + 119 | if(cursor+1==length) state<=CRC0; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:144:25: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_uart_boot.platform.loader' + 144 | else if(cursor+1==length) begin image_loaded<=1;state<=REPLY;end + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:152:20: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_uart_boot.platform.loader' + 152 | if(cursor+1==length) state<=REPLY; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:157:43: Operator LT expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_uart_boot.platform.loader' + 157 | if(reply_index>=2 && reply_index<7+reply_length) crc<=crc_next(crc,tx_data); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:158:25: Operator EQ expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_uart_boot.platform.loader' + 158 | if(reply_index==8+reply_length) state<=DRAIN; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:87:37: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'timeout_count' generates 22 bits. + : ... note: In instance 'tb_board_uart_boot.platform.loader' + 87 | if((receiving && timeout_count==RX_TIMEOUT-1) || (receiving && rx_error)) begin + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:52:20: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'addr' generates 28 bits. + : ... note: In instance 'tb_board_uart_boot.memory' + 52 | offset=(addr & ~(LANES-1))-BASE; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:78:28: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'write_addr' generates 28 bits. + : ... note: In instance 'tb_board_uart_boot.memory' + 78 | offset=(write_addr & ~(LANES-1))-BASE; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:86:26: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'h600d600d' generates 64 bits. + : ... note: In instance 'tb_board_uart_boot.memory' + 86 | if (w_bits_data==64'h600d600d) begin + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:91:66: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff' generates 64 bits. + : ... note: In instance 'tb_board_uart_boot.memory' + 91 | $fatal(1,"CPU smoke failed at stage %0d",w_bits_data & 64'hffff); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:90:28: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff0000' generates 64 bits. + : ... note: In instance 'tb_board_uart_boot.memory' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:90:43: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'hbad00000' generates 64 bits. + : ... note: In instance 'tb_board_uart_boot.memory' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:139:14: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's SHIFTR generates 32 bits. + : ... note: In instance 'tb_board_uart_boot' + 139 | value=address>>(8*n);send_byte(value);crc=crc_step(crc,value); + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:141:12: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's AND generates 32 bits. + : ... note: In instance 'tb_board_uart_boot' + 141 | value=length&255;send_byte(value);crc=crc_step(crc,value); + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:142:12: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's AND generates 32 bits. + : ... note: In instance 'tb_board_uart_boot' + 142 | value=(length>>8)&255;send_byte(value);crc=crc_step(crc,value); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/tb_board_uart_boot.sv:154:94: Operator NEQCASE expects 32 bits on the LHS, but LHS's REPLICATE generates 16 bits. + : ... note: In instance 'tb_board_uart_boot' + 154 | reply_bytes[3]!==8'h37 || reply_bytes[4]!==status || {reply_bytes[6],reply_bytes[5]}!==length) + | ^~~ +make: Entering directory '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/obj' +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_timing.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_timing.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_threads.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_threads.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb_board_uart_boot__pch.h -o Vtb_board_uart_boot__pch.h.fast.gch +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb_board_uart_boot__pch.h -o Vtb_board_uart_boot__pch.h.slow.gch +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_uart_boot__pch.h.slow -c Vtb_board_uart_boot__ConstPool__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_uart_boot__pch.h.slow -c Vtb_board_uart_boot___024root__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_uart_boot__pch.h.slow -c Vtb_board_uart_boot___024root__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_uart_boot__pch.h.slow -c Vtb_board_uart_boot___024root__1__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_uart_boot__pch.h.slow -c Vtb_board_uart_boot___024root__2__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_uart_boot__pch.h.slow -c Vtb_board_uart_boot___024root__3__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_uart_boot__pch.h.slow -c Vtb_board_uart_boot__Syms__Slow.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_uart_boot__pch.h.fast -c Vtb_board_uart_boot.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_uart_boot__pch.h.fast -c Vtb_board_uart_boot___024root__0.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_uart_boot__pch.h.fast -c Vtb_board_uart_boot___024root__1.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_uart_boot__pch.h.fast -c Vtb_board_uart_boot___024root__2.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_uart_boot__pch.h.fast -c Vtb_board_uart_boot___024root__3.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_uart_boot__pch.h.fast -c Vtb_board_uart_boot___024root__4.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_uart_boot__pch.h.fast -c Vtb_board_uart_boot___024root__5.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_uart_boot__pch.h.fast -c Vtb_board_uart_boot___024root__6.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_uart_boot__pch.h.fast -c Vtb_board_uart_boot___024root__7.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_uart_boot__pch.h.fast -c Vtb_board_uart_boot___024root__8.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_uart_boot__pch.h.fast -c Vtb_board_uart_boot___024root__9.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_uart_boot__pch.h.fast -c Vtb_board_uart_boot___024root__10.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_uart_boot__pch.h.fast -c Vtb_board_uart_boot__main.cpp +g++ verilated.o verilated_timing.o verilated_threads.o Vtb_board_uart_boot__ALL.a -pthread -lpthread -latomic -o Vtb_board_uart_boot +rm Vtb_board_uart_boot__ALL.verilator_deplist.tmp +make: Leaving directory '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-uart-boot/obj' +- V e r i l a t i o n R e p o r t: Verilator 5.050 2026-07-01 rev v5.050 +- Verilator: Built from 46.574 MB sources in 354 modules, into 27.800 MB in 20 C++ files needing 0.022 MB +- Verilator: Walltime 15.098 s (elab=0.679, cvt=4.110, bld=9.588); cpu 5.819 s on 8 threads; allocated 502.324 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-uart-boot/program.hex b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-uart-boot/program.hex new file mode 100644 index 0000000..249f375 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-uart-boot/program.hex @@ -0,0 +1,110592 @@ +97 +02 +00 +00 +93 +82 +c2 +2f +73 +90 +52 +30 +73 +10 +20 +30 +73 +10 +40 +30 +13 +0d +00 +00 +93 +0d +00 +00 +93 +01 +10 +00 +b7 +02 +00 +60 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walltime 415.489 s; speed 5.955 ms/s +- Verilator: cpu 415.438 s on 1 threads; allocated 8 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-uart-boot/tb_board_uart_boot.sv b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-uart-boot/tb_board_uart_boot.sv new file mode 100644 index 0000000..8d0e995 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/board-uart-boot/tb_board_uart_boot.sv @@ -0,0 +1,182 @@ +`timescale 1ns/1ps +module tb_board_uart_boot; + reg clk=0;always #20 clk=~clk; + reg reset=1,uart_rx_in=1; + wire uart_tx_out; + wire cpu_run; + wire exited; + wire loader_error; + wire [31:0] exit_code; + wire [3:0] ddr_awid; + wire [27:0] ddr_awaddr; + wire [7:0] ddr_awlen; + wire [2:0] ddr_awsize; + wire [1:0] ddr_awburst; + wire ddr_awvalid; + wire ddr_awready; + wire [127:0] ddr_wdata; + wire [15:0] ddr_wstrb; + wire ddr_wlast; + wire ddr_wvalid; + wire ddr_wready; + wire [3:0] ddr_bid; + wire [1:0] ddr_bresp; + wire ddr_bvalid; + wire ddr_bready; + wire [3:0] ddr_arid; + wire [27:0] ddr_araddr; + wire [7:0] ddr_arlen; + wire [2:0] ddr_arsize; + wire [1:0] ddr_arburst; + wire ddr_arvalid; + wire ddr_arready; + wire [3:0] ddr_rid; + wire [127:0] ddr_rdata; + wire [1:0] ddr_rresp; + wire ddr_rlast; + wire ddr_rvalid; + wire ddr_rready; + wire flash_miso; + wire flash_recovery; + wire flash_mosi; + wire flash_sck; + wire flash_cs_n; + toy_a7_platform platform(.*); + initial begin + repeat(10) @(negedge clk); reset=0;end + integer cycles=0; + always @(posedge clk) if(!reset) begin + cycles<=cycles+1; + if(platform.memory_aw_valid && platform.memory_aw_bits_lock) $fatal(1,"Unexpected AXI exclusive write"); + if(platform.memory_ar_valid && platform.memory_ar_bits_lock) $fatal(1,"Unexpected AXI exclusive read"); + if(ddr_awvalid && ddr_awready && (ddr_awsize!=4 || ddr_awlen!=0)) $fatal(1,"Narrow DDR write"); + if(ddr_arvalid && ddr_arready && (ddr_arsize!=4 || ddr_arlen!=0)) $fatal(1,"Narrow DDR read"); + if(exited && (exit_code & 32'hffff0000)==32'hbad00000) $fatal(1,"CPU oracle failed stage=%h",exit_code); + if(exited && exit_code==32'h600d600d) begin + $display("PASS CPU Sv39/FPU/AMO/cache/interrupt through board AXI/SCU cycles=%0d",cycles);$finish;end + if(cycles>120000000) $fatal(1,"Board CPU watchdog"); + end + axi_smoke_memory #(.ADDR_BITS(28),.BASE(0),.CAPACITY(262144),.IMAGE("")) memory ( + .clock(clk), + .reset(reset), + .aw_bits_id(ddr_awid), + .aw_bits_addr(ddr_awaddr), + .aw_bits_len(ddr_awlen), + .aw_bits_size(ddr_awsize), + .aw_bits_burst(ddr_awburst), + .aw_valid(ddr_awvalid), + .aw_ready(ddr_awready), + .w_bits_data(ddr_wdata), + .w_bits_strb(ddr_wstrb), + .w_bits_last(ddr_wlast), + .w_valid(ddr_wvalid), + .w_ready(ddr_wready), + .b_bits_id(ddr_bid), + .b_bits_resp(ddr_bresp), + .b_valid(ddr_bvalid), + .b_ready(ddr_bready), + .ar_bits_id(ddr_arid), + .ar_bits_addr(ddr_araddr), + .ar_bits_len(ddr_arlen), + .ar_bits_size(ddr_arsize), + .ar_bits_burst(ddr_arburst), + .ar_valid(ddr_arvalid), + .ar_ready(ddr_arready), + .r_bits_id(ddr_rid), + .r_bits_data(ddr_rdata), + .r_bits_resp(ddr_rresp), + .r_bits_last(ddr_rlast), + .r_valid(ddr_rvalid), + .r_ready(ddr_rready) + ); + localparam PROGRAM_BYTES=110592; + + reg [7:0] firmware[0:PROGRAM_BYTES-1]; + reg [7:0] reply_bytes[0:511]; + integer received=0; + reg run_requested=0; + initial $readmemh("program.hex",firmware); + // Independent receiver observes real TX transitions, not tx_valid/data. + always begin : receiver + reg [7:0] value; + @(negedge uart_tx_out); + repeat(37) @(negedge clk); + for(integer bit_index=0;bit_index<8;bit_index=bit_index+1) begin + value[bit_index]=uart_tx_out;repeat(25) @(negedge clk); + end + if(uart_tx_out!==1) $fatal(1,"UART TX framing error"); + if(!cpu_run) begin + if(received>=512) $fatal(1,"UART reply overflow"); + reply_bytes[received]=value;received=received+1; + end + end + always @(posedge clk) if(!reset && cpu_run && !run_requested) + $fatal(1,"CPU released before verified RUN request"); + function automatic [15:0] crc_step(input [15:0] previous,input [7:0] value); + reg [15:0] crc; + begin + crc=previous; + for(integer bit_index=7;bit_index>=0;bit_index=bit_index-1) + crc=(crc<<1)^((crc[15]^value[bit_index]) ? 16'h1021 : 16'd0); + crc_step=crc; + end + endfunction + task automatic send_byte(input [7:0] value); + @(negedge clk);uart_rx_in=0;repeat(25) @(negedge clk); + for(integer bit_index=0;bit_index<8;bit_index=bit_index+1) begin + uart_rx_in=value[bit_index];repeat(25) @(negedge clk); + end + uart_rx_in=1;repeat(25) @(negedge clk); + endtask + task automatic request(input [7:0] op,input integer offset,length,input bit corrupt); + reg [15:0] crc;reg [31:0] address;reg [7:0] value; + begin + received=0;crc=16'hffff;address=32'h80000000+offset; + send_byte(8'ha5);send_byte(8'h5a); + send_byte(op);crc=crc_step(crc,op); + send_byte(8'h37);crc=crc_step(crc,8'h37); + for(integer n=0;n<4;n=n+1) begin + value=address>>(8*n);send_byte(value);crc=crc_step(crc,value); + end + value=length&255;send_byte(value);crc=crc_step(crc,value); + value=(length>>8)&255;send_byte(value);crc=crc_step(crc,value); + if(op==1) for(integer n=0;n=length+9); + if(reply_bytes[0]!==8'h5a || reply_bytes[1]!==8'ha5 || reply_bytes[2]!==(op|8'h80) || + reply_bytes[3]!==8'h37 || reply_bytes[4]!==status || {reply_bytes[6],reply_bytes[5]}!==length) + $fatal(1,"UART reply header/status op=%h status=%h count=%0d",op,reply_bytes[4],received); + crc=16'hffff; + for(integer n=2;n256) count=256; + request(1,offset,count,0);reply(1,0,0); + request(2,offset,count,0);reply(2,0,count); + for(integer n=0;n=0;n=n-1) c=(c<<1)^((c[15]^value[n]) ? 16'h1021 : 16'd0); + crc_step=c; + end + endfunction + task automatic byte_send(input [7:0] value); + begin @(negedge clk);rx_data=value;rx_valid=1;@(negedge clk);rx_valid=0;end + endtask + task automatic request(input [7:0] op,input [31:0] address,input [15:0] length,input bit corrupt); + reg [15:0] crc; + reg [7:0] value; + begin + received=0;crc=16'hffff; + byte_send(8'ha5);byte_send(8'h5a); + byte_send(op);crc=crc_step(crc,op); + byte_send(8'h37);crc=crc_step(crc,8'h37); + for(integer n=0;n<4;n=n+1) begin + value=address>>(n*8);byte_send(value);crc=crc_step(crc,value); + end + byte_send(length[7:0]);crc=crc_step(crc,length[7:0]); + byte_send(length[15:8]);crc=crc_step(crc,length[15:8]); + if(op==1) for(integer n=0;n>> CAlignDist); + wire [16:0] reduced4CExtra_shift = $signed(17'sh10000 >>> CAlignDist[5:2]); + wire [1:0] _GEN = + {|(io_c[7:4]), |(io_c[3:0])} & {reduced4CExtra_shift[8], reduced4CExtra_shift[9]}; + assign io_mulAddA = {|(io_a[15:13]), io_a[9:0]}; + assign io_mulAddB = {|(io_b[15:13]), io_b[9:0]}; + assign io_mulAddC = mainAlignedSigC[24:3]; + assign io_toPostMul_isSigNaNAny = + rawA_isNaN & ~(io_a[9]) | rawB_isNaN & ~(io_b[9]) | rawC_isNaN & ~(io_c[9]); + assign io_toPostMul_isNaNAOrB = rawA_isNaN | rawB_isNaN; + assign io_toPostMul_isInfA = (&(io_a[15:14])) & ~(io_a[13]); + assign io_toPostMul_isZeroA = ~(|(io_a[15:13])); + assign io_toPostMul_isInfB = (&(io_b[15:14])) & ~(io_b[13]); + assign io_toPostMul_isZeroB = ~(|(io_b[15:13])); + assign io_toPostMul_signProd = signProd; + assign io_toPostMul_isNaNC = rawC_isNaN; + assign io_toPostMul_isInfC = (&(io_c[15:14])) & ~(io_c[13]); + assign io_toPostMul_isZeroC = ~(|(io_c[15:13])); + assign io_toPostMul_sExpSum = + CIsDominant ? {1'h0, io_c[15:10]} : _sExpAlignedProd_T_1[6:0] - 7'hB; + assign io_toPostMul_doSubMags = doSubMags; + assign io_toPostMul_CIsDominant = CIsDominant; + assign io_toPostMul_CDom_CAlignDist = CAlignDist[3:0]; + assign io_toPostMul_highAlignedSigC = mainAlignedSigC[37:25]; + assign io_toPostMul_bit0AlignedSigC = + doSubMags + ? (&(mainAlignedSigC[2:0])) & ~(|_GEN) + : (|(mainAlignedSigC[2:0])) | (|_GEN); +endmodule + +module MulAddRecFNToRaw_postMul_e5_s11( + input io_fromPreMul_isSigNaNAny, + io_fromPreMul_isNaNAOrB, + io_fromPreMul_isInfA, + io_fromPreMul_isZeroA, + io_fromPreMul_isInfB, + io_fromPreMul_isZeroB, + io_fromPreMul_signProd, + io_fromPreMul_isNaNC, + io_fromPreMul_isInfC, + io_fromPreMul_isZeroC, + input [6:0] io_fromPreMul_sExpSum, + input io_fromPreMul_doSubMags, + io_fromPreMul_CIsDominant, + input [3:0] io_fromPreMul_CDom_CAlignDist, + input [12:0] io_fromPreMul_highAlignedSigC, + input io_fromPreMul_bit0AlignedSigC, + input [22:0] io_mulAddResult, + input [2:0] io_roundingMode, + output io_invalidExc, + io_rawOut_isNaN, + io_rawOut_isInf, + io_rawOut_isZero, + io_rawOut_sign, + output [6:0] io_rawOut_sExp, + output [13:0] io_rawOut_sig +); + + wire roundingMode_min = io_roundingMode == 3'h2; + wire opSignC = io_fromPreMul_signProd ^ io_fromPreMul_doSubMags; + wire [12:0] _sigSum_T_3 = + io_mulAddResult[22] + ? io_fromPreMul_highAlignedSigC + 13'h1 + : io_fromPreMul_highAlignedSigC; + wire [23:0] CDom_absSigSum = + io_fromPreMul_doSubMags + ? ~{_sigSum_T_3, io_mulAddResult[21:11]} + : {1'h0, + io_fromPreMul_highAlignedSigC[12:11], + _sigSum_T_3[10:0], + io_mulAddResult[21:12]}; + wire [38:0] _CDom_mainSig_T = {15'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist; + wire [4:0] CDom_reduced4SigExtra_shift = + $signed(5'sh10 >>> ~(io_fromPreMul_CDom_CAlignDist[3:2])); + wire [24:0] notCDom_absSigSum = + _sigSum_T_3[2] + ? ~{_sigSum_T_3[1:0], io_mulAddResult[21:0], io_fromPreMul_bit0AlignedSigC} + : {_sigSum_T_3[1:0], io_mulAddResult[21:0], io_fromPreMul_bit0AlignedSigC} + + {24'h0, io_fromPreMul_doSubMags}; + wire [3:0] notCDom_normDistReduced2 = + notCDom_absSigSum[24] + ? 4'h0 + : (|(notCDom_absSigSum[23:22])) + ? 4'h1 + : (|(notCDom_absSigSum[21:20])) + ? 4'h2 + : (|(notCDom_absSigSum[19:18])) + ? 4'h3 + : (|(notCDom_absSigSum[17:16])) + ? 4'h4 + : (|(notCDom_absSigSum[15:14])) + ? 4'h5 + : (|(notCDom_absSigSum[13:12])) + ? 4'h6 + : (|(notCDom_absSigSum[11:10])) + ? 4'h7 + : (|(notCDom_absSigSum[9:8])) + ? 4'h8 + : (|(notCDom_absSigSum[7:6])) + ? 4'h9 + : (|(notCDom_absSigSum[5:4])) + ? 4'hA + : (|(notCDom_absSigSum[3:2])) ? 4'hB : 4'hC; + wire [55:0] _notCDom_mainSig_T = + {31'h0, notCDom_absSigSum} << {51'h0, notCDom_normDistReduced2, 1'h0}; + wire [8:0] notCDom_reduced4SigExtra_shift = + $signed(9'sh100 >>> ~(notCDom_normDistReduced2[3:1])); + wire notCDom_completeCancellation = _notCDom_mainSig_T[25:24] == 2'h0; + wire notNaN_isInfProd = io_fromPreMul_isInfA | io_fromPreMul_isInfB; + wire notNaN_isInfOut = notNaN_isInfProd | io_fromPreMul_isInfC; + wire notNaN_addZeros = + (io_fromPreMul_isZeroA | io_fromPreMul_isZeroB) & io_fromPreMul_isZeroC; + assign io_invalidExc = + io_fromPreMul_isSigNaNAny | io_fromPreMul_isInfA & io_fromPreMul_isZeroB + | io_fromPreMul_isZeroA & io_fromPreMul_isInfB | ~io_fromPreMul_isNaNAOrB + & notNaN_isInfProd & io_fromPreMul_isInfC & io_fromPreMul_doSubMags; + assign io_rawOut_isNaN = io_fromPreMul_isNaNAOrB | io_fromPreMul_isNaNC; + assign io_rawOut_isInf = notNaN_isInfOut; + assign io_rawOut_isZero = + notNaN_addZeros | ~io_fromPreMul_CIsDominant & notCDom_completeCancellation; + assign io_rawOut_sign = + notNaN_isInfProd & io_fromPreMul_signProd | io_fromPreMul_isInfC & opSignC + | notNaN_addZeros & ~roundingMode_min & io_fromPreMul_signProd & opSignC + | notNaN_addZeros & roundingMode_min & (io_fromPreMul_signProd | opSignC) + | ~notNaN_isInfOut & ~notNaN_addZeros + & (io_fromPreMul_CIsDominant + ? opSignC + : notCDom_completeCancellation + ? roundingMode_min + : io_fromPreMul_signProd ^ _sigSum_T_3[2]); + assign io_rawOut_sExp = + io_fromPreMul_CIsDominant + ? io_fromPreMul_sExpSum - {6'h0, io_fromPreMul_doSubMags} + : io_fromPreMul_sExpSum - {2'h0, notCDom_normDistReduced2, 1'h0}; + assign io_rawOut_sig = + io_fromPreMul_CIsDominant + ? {_CDom_mainSig_T[23:11], + (|(_CDom_mainSig_T[10:8])) + | (|({|(CDom_absSigSum[7:4]), |(CDom_absSigSum[3:0])} + & {CDom_reduced4SigExtra_shift[1], CDom_reduced4SigExtra_shift[2]})) + | (io_fromPreMul_doSubMags + ? io_mulAddResult[10:0] != 11'h7FF + : (|(io_mulAddResult[11:0])))} + : {_notCDom_mainSig_T[25:13], + (|(_notCDom_mainSig_T[12:10])) + | (|({|{|(notCDom_absSigSum[9:8]), |(notCDom_absSigSum[7:6])}, + |{|(notCDom_absSigSum[5:4]), |(notCDom_absSigSum[3:2])}, + |(notCDom_absSigSum[1:0])} + & {notCDom_reduced4SigExtra_shift[1], + notCDom_reduced4SigExtra_shift[2], + notCDom_reduced4SigExtra_shift[3]}))}; +endmodule + +module RoundAnyRawFNToRecFN_ie5_is13_oe5_os11( + input io_invalidExc, + io_in_isNaN, + io_in_isInf, + io_in_isZero, + io_in_sign, + input [6:0] io_in_sExp, + input [13:0] io_in_sig, + input [2:0] io_roundingMode, + output [16:0] io_out, + output [4:0] io_exceptionFlags +); + + wire roundingMode_near_even = io_roundingMode == 3'h0; + wire roundingMode_odd = io_roundingMode == 3'h6; + wire roundMagUp = + io_roundingMode == 3'h2 & io_in_sign | io_roundingMode == 3'h3 & ~io_in_sign; + wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> ~(io_in_sExp[5:0])); + wire [1:0] _GEN = {roundMask_shift[10], roundMask_shift[11]}; + wire _common_underflow_T_4 = roundMask_shift[18] | io_in_sig[13]; + wire [12:0] _GEN_0 = + {1'h1, + ~(roundMask_shift[7]), + ~(roundMask_shift[8]), + ~(roundMask_shift[9]), + ~_GEN, + ~(roundMask_shift[12]), + ~(roundMask_shift[13]), + ~(roundMask_shift[14]), + ~(roundMask_shift[15]), + ~(roundMask_shift[16]), + ~(roundMask_shift[17]), + ~_common_underflow_T_4}; + wire [12:0] _GEN_1 = + {roundMask_shift[7], + roundMask_shift[8], + roundMask_shift[9], + roundMask_shift[10], + roundMask_shift[11], + roundMask_shift[12], + roundMask_shift[13], + roundMask_shift[14], + roundMask_shift[15], + roundMask_shift[16], + roundMask_shift[17], + _common_underflow_T_4, + 1'h1}; + wire [12:0] _roundPosBit_T = io_in_sig[13:1] & _GEN_0 & _GEN_1; + wire [12:0] _anyRoundExtra_T = io_in_sig[12:0] & _GEN_1; + wire anyRound = (|_roundPosBit_T) | (|_anyRoundExtra_T); + wire _overflow_roundMagUp_T = roundingMode_near_even | io_roundingMode == 3'h4; + wire [12:0] roundedSig = + _overflow_roundMagUp_T & (|_roundPosBit_T) | roundMagUp & anyRound + ? {1'h0, + io_in_sig[13:2] + | {roundMask_shift[7], + roundMask_shift[8], + roundMask_shift[9], + roundMask_shift[10], + roundMask_shift[11], + roundMask_shift[12], + roundMask_shift[13], + roundMask_shift[14], + roundMask_shift[15], + roundMask_shift[16], + roundMask_shift[17], + _common_underflow_T_4}} + 13'h1 + & ~(roundingMode_near_even & (|_roundPosBit_T) & ~(|_anyRoundExtra_T) + ? {roundMask_shift[7], + roundMask_shift[8], + roundMask_shift[9], + roundMask_shift[10], + roundMask_shift[11], + roundMask_shift[12], + roundMask_shift[13], + roundMask_shift[14], + roundMask_shift[15], + roundMask_shift[16], + roundMask_shift[17], + _common_underflow_T_4, + 1'h1} + : 13'h0) + : {1'h0, + io_in_sig[13:2] + & {~(roundMask_shift[7]), + ~(roundMask_shift[8]), + ~(roundMask_shift[9]), + ~_GEN, + ~(roundMask_shift[12]), + ~(roundMask_shift[13]), + ~(roundMask_shift[14]), + ~(roundMask_shift[15]), + ~(roundMask_shift[16]), + ~(roundMask_shift[17]), + ~_common_underflow_T_4}} + | (roundingMode_odd & anyRound ? _GEN_0 & _GEN_1 : 13'h0); + wire [7:0] sRoundedExp = {io_in_sExp[6], io_in_sExp} + {6'h0, roundedSig[12:11]}; + wire common_totalUnderflow = $signed(sRoundedExp) < 8'sh8; + wire isNaNOut = io_invalidExc | io_in_isNaN; + wire commonCase = ~isNaNOut & ~io_in_isInf & ~io_in_isZero; + wire overflow = commonCase & $signed(sRoundedExp[7:4]) > 4'sh2; + wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp; + wire pegMinNonzeroMagOut = + commonCase & common_totalUnderflow & (roundMagUp | roundingMode_odd); + wire pegMaxFiniteMagOut = overflow & ~overflow_roundMagUp; + wire notNaN_isInfOut = io_in_isInf | overflow & overflow_roundMagUp; + assign io_out = + {~isNaNOut & io_in_sign, + sRoundedExp[5:0] & ~(io_in_isZero | common_totalUnderflow ? 6'h38 : 6'h0) + & ~(pegMinNonzeroMagOut ? 6'h37 : 6'h0) & {1'h1, ~pegMaxFiniteMagOut, 4'hF} + & {2'h3, ~notNaN_isInfOut, 3'h7} | {2'h0, pegMinNonzeroMagOut, 3'h0} + | (pegMaxFiniteMagOut ? 6'h2F : 6'h0) | (notNaN_isInfOut ? 6'h30 : 6'h0) + | (isNaNOut ? 6'h38 : 6'h0), + (isNaNOut | io_in_isZero | common_totalUnderflow + ? {isNaNOut, 9'h0} + : io_in_sig[13] ? roundedSig[10:1] : roundedSig[9:0]) | {10{pegMaxFiniteMagOut}}}; + assign io_exceptionFlags = + {io_invalidExc, + 1'h0, + overflow, + commonCase + & (common_totalUnderflow | anyRound & io_in_sExp[6:5] != 2'h1 + & (io_in_sig[13] ? roundMask_shift[17] : _common_underflow_T_4) + & ~(~(io_in_sig[13] ? roundMask_shift[16] : roundMask_shift[17]) + & (io_in_sig[13] ? roundedSig[12] : roundedSig[11]) & (|_roundPosBit_T) + & (_overflow_roundMagUp_T & (io_in_sig[13] ? io_in_sig[2] : io_in_sig[1]) + | roundMagUp & (io_in_sig[13] & io_in_sig[2] | (|(io_in_sig[1:0])))))), + overflow | commonCase & (common_totalUnderflow | anyRound)}; +endmodule + +module RoundRawFNToRecFN_e5_s11( + input io_invalidExc, + io_in_isNaN, + io_in_isInf, + io_in_isZero, + io_in_sign, + input [6:0] io_in_sExp, + input [13:0] io_in_sig, + input [2:0] io_roundingMode, + output [16:0] io_out, + output [4:0] io_exceptionFlags +); + + RoundAnyRawFNToRecFN_ie5_is13_oe5_os11 roundAnyRawFNToRecFN ( + .io_invalidExc (io_invalidExc), + .io_in_isNaN (io_in_isNaN), + .io_in_isInf (io_in_isInf), + .io_in_isZero (io_in_isZero), + .io_in_sign (io_in_sign), + .io_in_sExp (io_in_sExp), + .io_in_sig (io_in_sig), + .io_roundingMode (io_roundingMode), + .io_out (io_out), + .io_exceptionFlags (io_exceptionFlags) + ); +endmodule + +module MulAddRecFNPipe_l4_e5_s11( + input clock, + reset, + io_validin, + input [1:0] io_op, + input [16:0] io_a, + io_b, + io_c, + input [2:0] io_roundingMode, + output [16:0] io_out, + output [4:0] io_exceptionFlags, + output io_validout +); + + wire _mulAddRecFNToRaw_postMul_io_invalidExc; + wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; + wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; + wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; + wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; + wire [6:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; + wire [13:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; + wire [10:0] _mulAddRecFNToRaw_preMul_io_mulAddA; + wire [10:0] _mulAddRecFNToRaw_preMul_io_mulAddB; + wire [21:0] _mulAddRecFNToRaw_preMul_io_mulAddC; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; + wire [6:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; + wire [3:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; + wire [12:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; + reg [10:0] preMulMulAddA_pipe_b; + reg [10:0] preMulMulAddB_pipe_b; + reg [21:0] preMulMulAddC_pipe_b; + reg preMulToPostMul_pipe_v; + reg preMulToPostMul_pipe_b_isSigNaNAny; + reg preMulToPostMul_pipe_b_isNaNAOrB; + reg preMulToPostMul_pipe_b_isInfA; + reg preMulToPostMul_pipe_b_isZeroA; + reg preMulToPostMul_pipe_b_isInfB; + reg preMulToPostMul_pipe_b_isZeroB; + reg preMulToPostMul_pipe_b_signProd; + reg preMulToPostMul_pipe_b_isNaNC; + reg preMulToPostMul_pipe_b_isInfC; + reg preMulToPostMul_pipe_b_isZeroC; + reg [6:0] preMulToPostMul_pipe_b_sExpSum; + reg preMulToPostMul_pipe_b_doSubMags; + reg preMulToPostMul_pipe_b_CIsDominant; + reg [3:0] preMulToPostMul_pipe_b_CDom_CAlignDist; + reg [12:0] preMulToPostMul_pipe_b_highAlignedSigC; + reg preMulToPostMul_pipe_b_bit0AlignedSigC; + reg [21:0] mulResultPipe_pipe_b; + reg [21:0] mulAddCPipe_pipe_b; + reg mulToPostMul_pipe_v; + reg mulToPostMul_pipe_b_isSigNaNAny; + reg mulToPostMul_pipe_b_isNaNAOrB; + reg mulToPostMul_pipe_b_isInfA; + reg mulToPostMul_pipe_b_isZeroA; + reg mulToPostMul_pipe_b_isInfB; + reg mulToPostMul_pipe_b_isZeroB; + reg mulToPostMul_pipe_b_signProd; + reg mulToPostMul_pipe_b_isNaNC; + reg mulToPostMul_pipe_b_isInfC; + reg mulToPostMul_pipe_b_isZeroC; + reg [6:0] mulToPostMul_pipe_b_sExpSum; + reg mulToPostMul_pipe_b_doSubMags; + reg mulToPostMul_pipe_b_CIsDominant; + reg [3:0] mulToPostMul_pipe_b_CDom_CAlignDist; + reg [12:0] mulToPostMul_pipe_b_highAlignedSigC; + reg mulToPostMul_pipe_b_bit0AlignedSigC; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC; + reg [6:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant; + reg [3:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist; + reg [12:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC; + reg [22:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b; + reg mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v; + reg [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b; + reg mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_v; + reg [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_b; + reg [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_pipe_b; + reg roundingMode_stage0_pipe_v; + reg [2:0] roundingMode_stage0_pipe_b; + reg roundingMode_stage0_pipe_pipe_v; + reg [2:0] roundingMode_stage0_pipe_pipe_b; + reg [2:0] roundingMode_stage0_pipe_pipe_pipe_b; + reg valid_stage0_pipe_v; + reg valid_stage0_pipe_pipe_v; + reg valid_stage0_pipe_pipe_pipe_v; + reg roundRawFNToRecFN_io_invalidExc_pipe_b; + reg roundRawFNToRecFN_io_in_pipe_b_isNaN; + reg roundRawFNToRecFN_io_in_pipe_b_isInf; + reg roundRawFNToRecFN_io_in_pipe_b_isZero; + reg roundRawFNToRecFN_io_in_pipe_b_sign; + reg [6:0] roundRawFNToRecFN_io_in_pipe_b_sExp; + reg [13:0] roundRawFNToRecFN_io_in_pipe_b_sig; + reg [2:0] roundRawFNToRecFN_io_roundingMode_pipe_b; + reg io_validout_pipe_v; + always @(posedge clock) begin + if (io_validin) begin + preMulMulAddA_pipe_b <= _mulAddRecFNToRaw_preMul_io_mulAddA; + preMulMulAddB_pipe_b <= _mulAddRecFNToRaw_preMul_io_mulAddB; + preMulMulAddC_pipe_b <= _mulAddRecFNToRaw_preMul_io_mulAddC; + preMulToPostMul_pipe_b_isSigNaNAny <= + _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; + preMulToPostMul_pipe_b_isNaNAOrB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; + preMulToPostMul_pipe_b_isInfA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; + preMulToPostMul_pipe_b_isZeroA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; + preMulToPostMul_pipe_b_isInfB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; + preMulToPostMul_pipe_b_isZeroB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; + preMulToPostMul_pipe_b_signProd <= _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; + preMulToPostMul_pipe_b_isNaNC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; + preMulToPostMul_pipe_b_isInfC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; + preMulToPostMul_pipe_b_isZeroC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; + preMulToPostMul_pipe_b_sExpSum <= _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; + preMulToPostMul_pipe_b_doSubMags <= _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; + preMulToPostMul_pipe_b_CIsDominant <= + _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; + preMulToPostMul_pipe_b_CDom_CAlignDist <= + _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; + preMulToPostMul_pipe_b_highAlignedSigC <= + _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; + preMulToPostMul_pipe_b_bit0AlignedSigC <= + _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b <= io_roundingMode; + roundingMode_stage0_pipe_b <= io_roundingMode; + end + if (preMulToPostMul_pipe_v) begin + mulResultPipe_pipe_b <= + {11'h0, preMulMulAddA_pipe_b} * {11'h0, preMulMulAddB_pipe_b}; + mulAddCPipe_pipe_b <= preMulMulAddC_pipe_b; + mulToPostMul_pipe_b_isSigNaNAny <= preMulToPostMul_pipe_b_isSigNaNAny; + mulToPostMul_pipe_b_isNaNAOrB <= preMulToPostMul_pipe_b_isNaNAOrB; + mulToPostMul_pipe_b_isInfA <= preMulToPostMul_pipe_b_isInfA; + mulToPostMul_pipe_b_isZeroA <= preMulToPostMul_pipe_b_isZeroA; + mulToPostMul_pipe_b_isInfB <= preMulToPostMul_pipe_b_isInfB; + mulToPostMul_pipe_b_isZeroB <= preMulToPostMul_pipe_b_isZeroB; + mulToPostMul_pipe_b_signProd <= preMulToPostMul_pipe_b_signProd; + mulToPostMul_pipe_b_isNaNC <= preMulToPostMul_pipe_b_isNaNC; + mulToPostMul_pipe_b_isInfC <= preMulToPostMul_pipe_b_isInfC; + mulToPostMul_pipe_b_isZeroC <= preMulToPostMul_pipe_b_isZeroC; + mulToPostMul_pipe_b_sExpSum <= preMulToPostMul_pipe_b_sExpSum; + mulToPostMul_pipe_b_doSubMags <= preMulToPostMul_pipe_b_doSubMags; + mulToPostMul_pipe_b_CIsDominant <= preMulToPostMul_pipe_b_CIsDominant; + mulToPostMul_pipe_b_CDom_CAlignDist <= preMulToPostMul_pipe_b_CDom_CAlignDist; + mulToPostMul_pipe_b_highAlignedSigC <= preMulToPostMul_pipe_b_highAlignedSigC; + mulToPostMul_pipe_b_bit0AlignedSigC <= preMulToPostMul_pipe_b_bit0AlignedSigC; + end + if (mulToPostMul_pipe_v) begin + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny <= + mulToPostMul_pipe_b_isSigNaNAny; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB <= + mulToPostMul_pipe_b_isNaNAOrB; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA <= mulToPostMul_pipe_b_isInfA; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA <= + mulToPostMul_pipe_b_isZeroA; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB <= mulToPostMul_pipe_b_isInfB; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB <= + mulToPostMul_pipe_b_isZeroB; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd <= + mulToPostMul_pipe_b_signProd; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC <= mulToPostMul_pipe_b_isNaNC; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC <= mulToPostMul_pipe_b_isInfC; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC <= + mulToPostMul_pipe_b_isZeroC; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum <= + mulToPostMul_pipe_b_sExpSum; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags <= + mulToPostMul_pipe_b_doSubMags; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant <= + mulToPostMul_pipe_b_CIsDominant; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist <= + mulToPostMul_pipe_b_CDom_CAlignDist; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC <= + mulToPostMul_pipe_b_highAlignedSigC; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC <= + mulToPostMul_pipe_b_bit0AlignedSigC; + mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b <= + {1'h0, mulResultPipe_pipe_b} + {1'h0, mulAddCPipe_pipe_b}; + end + if (mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v) + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_b <= + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b; + if (mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_v) + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_pipe_b <= + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_b; + if (roundingMode_stage0_pipe_v) + roundingMode_stage0_pipe_pipe_b <= roundingMode_stage0_pipe_b; + if (roundingMode_stage0_pipe_pipe_v) + roundingMode_stage0_pipe_pipe_pipe_b <= roundingMode_stage0_pipe_pipe_b; + if (valid_stage0_pipe_pipe_pipe_v) begin + roundRawFNToRecFN_io_invalidExc_pipe_b <= _mulAddRecFNToRaw_postMul_io_invalidExc; + roundRawFNToRecFN_io_in_pipe_b_isNaN <= _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; + roundRawFNToRecFN_io_in_pipe_b_isInf <= _mulAddRecFNToRaw_postMul_io_rawOut_isInf; + roundRawFNToRecFN_io_in_pipe_b_isZero <= _mulAddRecFNToRaw_postMul_io_rawOut_isZero; + roundRawFNToRecFN_io_in_pipe_b_sign <= _mulAddRecFNToRaw_postMul_io_rawOut_sign; + roundRawFNToRecFN_io_in_pipe_b_sExp <= _mulAddRecFNToRaw_postMul_io_rawOut_sExp; + roundRawFNToRecFN_io_in_pipe_b_sig <= _mulAddRecFNToRaw_postMul_io_rawOut_sig; + roundRawFNToRecFN_io_roundingMode_pipe_b <= roundingMode_stage0_pipe_pipe_pipe_b; + end + if (reset) begin + preMulToPostMul_pipe_v <= 1'h0; + mulToPostMul_pipe_v <= 1'h0; + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v <= 1'h0; + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_v <= 1'h0; + roundingMode_stage0_pipe_v <= 1'h0; + roundingMode_stage0_pipe_pipe_v <= 1'h0; + valid_stage0_pipe_v <= 1'h0; + valid_stage0_pipe_pipe_v <= 1'h0; + valid_stage0_pipe_pipe_pipe_v <= 1'h0; + io_validout_pipe_v <= 1'h0; + end + else begin + preMulToPostMul_pipe_v <= io_validin; + mulToPostMul_pipe_v <= preMulToPostMul_pipe_v; + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v <= io_validin; + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_v <= + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v; + roundingMode_stage0_pipe_v <= io_validin; + roundingMode_stage0_pipe_pipe_v <= roundingMode_stage0_pipe_v; + valid_stage0_pipe_v <= io_validin; + valid_stage0_pipe_pipe_v <= valid_stage0_pipe_v; + valid_stage0_pipe_pipe_pipe_v <= valid_stage0_pipe_pipe_v; + io_validout_pipe_v <= valid_stage0_pipe_pipe_pipe_v; + end + end // always @(posedge) + MulAddRecFNToRaw_preMul_e5_s11 mulAddRecFNToRaw_preMul ( + .io_op (io_op), + .io_a (io_a), + .io_b (io_b), + .io_c (io_c), + .io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA), + .io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB), + .io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC), + .io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), + .io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), + .io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), + .io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), + .io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB), + .io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB), + .io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), + .io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), + .io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), + .io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), + .io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), + .io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), + .io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), + .io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), + .io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), + .io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC) + ); + MulAddRecFNToRaw_postMul_e5_s11 mulAddRecFNToRaw_postMul ( + .io_fromPreMul_isSigNaNAny + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny), + .io_fromPreMul_isNaNAOrB + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB), + .io_fromPreMul_isInfA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA), + .io_fromPreMul_isZeroA + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA), + .io_fromPreMul_isInfB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB), + .io_fromPreMul_isZeroB + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB), + .io_fromPreMul_signProd + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd), + .io_fromPreMul_isNaNC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC), + .io_fromPreMul_isInfC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC), + .io_fromPreMul_isZeroC + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC), + .io_fromPreMul_sExpSum + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum), + .io_fromPreMul_doSubMags + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags), + .io_fromPreMul_CIsDominant + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant), + .io_fromPreMul_CDom_CAlignDist + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist), + .io_fromPreMul_highAlignedSigC + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC), + .io_fromPreMul_bit0AlignedSigC + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC), + .io_mulAddResult (mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b), + .io_roundingMode + (mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_pipe_b), + .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), + .io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), + .io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), + .io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), + .io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), + .io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), + .io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig) + ); + RoundRawFNToRecFN_e5_s11 roundRawFNToRecFN ( + .io_invalidExc (roundRawFNToRecFN_io_invalidExc_pipe_b), + .io_in_isNaN (roundRawFNToRecFN_io_in_pipe_b_isNaN), + .io_in_isInf (roundRawFNToRecFN_io_in_pipe_b_isInf), + .io_in_isZero (roundRawFNToRecFN_io_in_pipe_b_isZero), + .io_in_sign (roundRawFNToRecFN_io_in_pipe_b_sign), + .io_in_sExp (roundRawFNToRecFN_io_in_pipe_b_sExp), + .io_in_sig (roundRawFNToRecFN_io_in_pipe_b_sig), + .io_roundingMode (roundRawFNToRecFN_io_roundingMode_pipe_b), + .io_out (io_out), + .io_exceptionFlags (io_exceptionFlags) + ); + assign io_validout = io_validout_pipe_v; +endmodule + +module FPUFMAPipe_l5_f16( + input clock, + reset, + io_in_valid, + io_in_bits_ren3, + io_in_bits_swap23, + input [2:0] io_in_bits_rm, + input [1:0] io_in_bits_fmaCmd, + input [64:0] io_in_bits_in1, + io_in_bits_in2, + io_in_bits_in3, + output io_out_valid, + output [64:0] io_out_bits_data, + output [4:0] io_out_bits_exc +); + + wire [16:0] _fma_io_out; + reg valid; + reg [2:0] in_rm; + reg [1:0] in_fmaCmd; + reg [64:0] in_in1; + reg [64:0] in_in2; + reg [64:0] in_in3; + always @(posedge clock) begin + valid <= io_in_valid; + if (io_in_valid) begin + in_rm <= io_in_bits_rm; + in_fmaCmd <= io_in_bits_fmaCmd; + in_in1 <= io_in_bits_in1; + in_in2 <= io_in_bits_swap23 ? 65'h8000 : io_in_bits_in2; + in_in3 <= + io_in_bits_ren3 | io_in_bits_swap23 + ? io_in_bits_in3 + : {48'h0, (io_in_bits_in1[16:0] ^ io_in_bits_in2[16:0]) & 17'h10000}; + end + end // always @(posedge) + MulAddRecFNPipe_l4_e5_s11 fma ( + .clock (clock), + .reset (reset), + .io_validin (valid), + .io_op (in_fmaCmd), + .io_a (in_in1[16:0]), + .io_b (in_in2[16:0]), + .io_c (in_in3[16:0]), + .io_roundingMode (in_rm), + .io_out (_fma_io_out), + .io_exceptionFlags (io_out_bits_exc), + .io_validout (io_out_valid) + ); + assign io_out_bits_data = {48'h0, _fma_io_out}; +endmodule + +module MulAddRecFNToRaw_preMul_e8_s24( + input [1:0] io_op, + input [32:0] io_a, + io_b, + io_c, + output [23:0] io_mulAddA, + io_mulAddB, + output [47:0] io_mulAddC, + output io_toPostMul_isSigNaNAny, + io_toPostMul_isNaNAOrB, + io_toPostMul_isInfA, + io_toPostMul_isZeroA, + io_toPostMul_isInfB, + io_toPostMul_isZeroB, + io_toPostMul_signProd, + io_toPostMul_isNaNC, + io_toPostMul_isInfC, + io_toPostMul_isZeroC, + output [9:0] io_toPostMul_sExpSum, + output io_toPostMul_doSubMags, + io_toPostMul_CIsDominant, + output [4:0] io_toPostMul_CDom_CAlignDist, + output [25:0] io_toPostMul_highAlignedSigC, + output io_toPostMul_bit0AlignedSigC +); + + wire rawA_isNaN = (&(io_a[31:30])) & io_a[29]; + wire rawB_isNaN = (&(io_b[31:30])) & io_b[29]; + wire rawC_isNaN = (&(io_c[31:30])) & io_c[29]; + wire signProd = io_a[32] ^ io_b[32] ^ io_op[1]; + wire [10:0] _sExpAlignedProd_T_1 = {2'h0, io_a[31:23]} + {2'h0, io_b[31:23]} - 11'hE5; + wire doSubMags = signProd ^ io_c[32] ^ io_op[0]; + wire [10:0] _sNatCAlignDist_T = _sExpAlignedProd_T_1 - {2'h0, io_c[31:23]}; + wire isMinCAlign = + ~(|(io_a[31:29])) | ~(|(io_b[31:29])) | $signed(_sNatCAlignDist_T) < 11'sh0; + wire CIsDominant = + (|(io_c[31:29])) & (isMinCAlign | _sNatCAlignDist_T[9:0] < 10'h19); + wire [6:0] CAlignDist = + isMinCAlign ? 7'h0 : _sNatCAlignDist_T[9:0] < 10'h4A ? _sNatCAlignDist_T[6:0] : 7'h4A; + wire [77:0] mainAlignedSigC = + $signed($signed({doSubMags + ? {1'h1, ~(|(io_c[31:29])), ~(io_c[22:0])} + : {1'h0, |(io_c[31:29]), io_c[22:0]}, + {53{doSubMags}}}) >>> CAlignDist); + wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> CAlignDist[6:2]); + wire [5:0] _GEN = + {|(io_c[21:18]), + |(io_c[17:14]), + |(io_c[13:10]), + |(io_c[9:6]), + |(io_c[5:2]), + |(io_c[1:0])} + & {reduced4CExtra_shift[14], + reduced4CExtra_shift[15], + reduced4CExtra_shift[16], + reduced4CExtra_shift[17], + reduced4CExtra_shift[18], + reduced4CExtra_shift[19]}; + assign io_mulAddA = {|(io_a[31:29]), io_a[22:0]}; + assign io_mulAddB = {|(io_b[31:29]), io_b[22:0]}; + assign io_mulAddC = mainAlignedSigC[50:3]; + assign io_toPostMul_isSigNaNAny = + rawA_isNaN & ~(io_a[22]) | rawB_isNaN & ~(io_b[22]) | rawC_isNaN & ~(io_c[22]); + assign io_toPostMul_isNaNAOrB = rawA_isNaN | rawB_isNaN; + assign io_toPostMul_isInfA = (&(io_a[31:30])) & ~(io_a[29]); + assign io_toPostMul_isZeroA = ~(|(io_a[31:29])); + assign io_toPostMul_isInfB = (&(io_b[31:30])) & ~(io_b[29]); + assign io_toPostMul_isZeroB = ~(|(io_b[31:29])); + assign io_toPostMul_signProd = signProd; + assign io_toPostMul_isNaNC = rawC_isNaN; + assign io_toPostMul_isInfC = (&(io_c[31:30])) & ~(io_c[29]); + assign io_toPostMul_isZeroC = ~(|(io_c[31:29])); + assign io_toPostMul_sExpSum = + CIsDominant ? {1'h0, io_c[31:23]} : _sExpAlignedProd_T_1[9:0] - 10'h18; + assign io_toPostMul_doSubMags = doSubMags; + assign io_toPostMul_CIsDominant = CIsDominant; + assign io_toPostMul_CDom_CAlignDist = CAlignDist[4:0]; + assign io_toPostMul_highAlignedSigC = mainAlignedSigC[76:51]; + assign io_toPostMul_bit0AlignedSigC = + doSubMags + ? (&(mainAlignedSigC[2:0])) & ~(|_GEN) + : (|(mainAlignedSigC[2:0])) | (|_GEN); +endmodule + +module MulAddRecFNToRaw_postMul_e8_s24( + input io_fromPreMul_isSigNaNAny, + io_fromPreMul_isNaNAOrB, + io_fromPreMul_isInfA, + io_fromPreMul_isZeroA, + io_fromPreMul_isInfB, + io_fromPreMul_isZeroB, + io_fromPreMul_signProd, + io_fromPreMul_isNaNC, + io_fromPreMul_isInfC, + io_fromPreMul_isZeroC, + input [9:0] io_fromPreMul_sExpSum, + input io_fromPreMul_doSubMags, + io_fromPreMul_CIsDominant, + input [4:0] io_fromPreMul_CDom_CAlignDist, + input [25:0] io_fromPreMul_highAlignedSigC, + input io_fromPreMul_bit0AlignedSigC, + input [48:0] io_mulAddResult, + input [2:0] io_roundingMode, + output io_invalidExc, + io_rawOut_isNaN, + io_rawOut_isInf, + io_rawOut_isZero, + io_rawOut_sign, + output [9:0] io_rawOut_sExp, + output [26:0] io_rawOut_sig +); + + wire roundingMode_min = io_roundingMode == 3'h2; + wire opSignC = io_fromPreMul_signProd ^ io_fromPreMul_doSubMags; + wire [25:0] _sigSum_T_3 = + io_mulAddResult[48] + ? io_fromPreMul_highAlignedSigC + 26'h1 + : io_fromPreMul_highAlignedSigC; + wire [49:0] CDom_absSigSum = + io_fromPreMul_doSubMags + ? ~{_sigSum_T_3, io_mulAddResult[47:24]} + : {1'h0, + io_fromPreMul_highAlignedSigC[25:24], + _sigSum_T_3[23:0], + io_mulAddResult[47:25]}; + wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist; + wire [8:0] CDom_reduced4SigExtra_shift = + $signed(9'sh100 >>> ~(io_fromPreMul_CDom_CAlignDist[4:2])); + wire [50:0] notCDom_absSigSum = + _sigSum_T_3[2] + ? ~{_sigSum_T_3[1:0], io_mulAddResult[47:0], io_fromPreMul_bit0AlignedSigC} + : {_sigSum_T_3[1:0], io_mulAddResult[47:0], io_fromPreMul_bit0AlignedSigC} + + {50'h0, io_fromPreMul_doSubMags}; + wire [4:0] notCDom_normDistReduced2 = + notCDom_absSigSum[50] + ? 5'h0 + : (|(notCDom_absSigSum[49:48])) + ? 5'h1 + : (|(notCDom_absSigSum[47:46])) + ? 5'h2 + : (|(notCDom_absSigSum[45:44])) + ? 5'h3 + : (|(notCDom_absSigSum[43:42])) + ? 5'h4 + : (|(notCDom_absSigSum[41:40])) + ? 5'h5 + : (|(notCDom_absSigSum[39:38])) + ? 5'h6 + : (|(notCDom_absSigSum[37:36])) + ? 5'h7 + : (|(notCDom_absSigSum[35:34])) + ? 5'h8 + : (|(notCDom_absSigSum[33:32])) + ? 5'h9 + : (|(notCDom_absSigSum[31:30])) + ? 5'hA + : (|(notCDom_absSigSum[29:28])) + ? 5'hB + : (|(notCDom_absSigSum[27:26])) + ? 5'hC + : (|(notCDom_absSigSum[25:24])) + ? 5'hD + : (|(notCDom_absSigSum[23:22])) + ? 5'hE + : (|(notCDom_absSigSum[21:20])) + ? 5'hF + : (|(notCDom_absSigSum[19:18])) + ? 5'h10 + : (|(notCDom_absSigSum[17:16])) + ? 5'h11 + : (|(notCDom_absSigSum[15:14])) + ? 5'h12 + : (|(notCDom_absSigSum[13:12])) + ? 5'h13 + : (|(notCDom_absSigSum[11:10])) + ? 5'h14 + : (|(notCDom_absSigSum[9:8])) + ? 5'h15 + : (|(notCDom_absSigSum[7:6])) + ? 5'h16 + : (|(notCDom_absSigSum[5:4])) + ? 5'h17 + : {4'hC, + ~(|(notCDom_absSigSum[3:2]))}; + wire [113:0] _notCDom_mainSig_T = + {63'h0, notCDom_absSigSum} << {108'h0, notCDom_normDistReduced2, 1'h0}; + wire [16:0] notCDom_reduced4SigExtra_shift = + $signed(17'sh10000 >>> ~(notCDom_normDistReduced2[4:1])); + wire notCDom_completeCancellation = _notCDom_mainSig_T[51:50] == 2'h0; + wire notNaN_isInfProd = io_fromPreMul_isInfA | io_fromPreMul_isInfB; + wire notNaN_isInfOut = notNaN_isInfProd | io_fromPreMul_isInfC; + wire notNaN_addZeros = + (io_fromPreMul_isZeroA | io_fromPreMul_isZeroB) & io_fromPreMul_isZeroC; + assign io_invalidExc = + io_fromPreMul_isSigNaNAny | io_fromPreMul_isInfA & io_fromPreMul_isZeroB + | io_fromPreMul_isZeroA & io_fromPreMul_isInfB | ~io_fromPreMul_isNaNAOrB + & notNaN_isInfProd & io_fromPreMul_isInfC & io_fromPreMul_doSubMags; + assign io_rawOut_isNaN = io_fromPreMul_isNaNAOrB | io_fromPreMul_isNaNC; + assign io_rawOut_isInf = notNaN_isInfOut; + assign io_rawOut_isZero = + notNaN_addZeros | ~io_fromPreMul_CIsDominant & notCDom_completeCancellation; + assign io_rawOut_sign = + notNaN_isInfProd & io_fromPreMul_signProd | io_fromPreMul_isInfC & opSignC + | notNaN_addZeros & ~roundingMode_min & io_fromPreMul_signProd & opSignC + | notNaN_addZeros & roundingMode_min & (io_fromPreMul_signProd | opSignC) + | ~notNaN_isInfOut & ~notNaN_addZeros + & (io_fromPreMul_CIsDominant + ? opSignC + : notCDom_completeCancellation + ? roundingMode_min + : io_fromPreMul_signProd ^ _sigSum_T_3[2]); + assign io_rawOut_sExp = + io_fromPreMul_CIsDominant + ? io_fromPreMul_sExpSum - {9'h0, io_fromPreMul_doSubMags} + : io_fromPreMul_sExpSum - {4'h0, notCDom_normDistReduced2, 1'h0}; + assign io_rawOut_sig = + io_fromPreMul_CIsDominant + ? {_CDom_mainSig_T[49:24], + (|(_CDom_mainSig_T[23:21])) + | (|({|(CDom_absSigSum[20:17]), + |(CDom_absSigSum[16:13]), + |(CDom_absSigSum[12:9]), + |(CDom_absSigSum[8:5]), + |(CDom_absSigSum[4:1]), + CDom_absSigSum[0]} + & {CDom_reduced4SigExtra_shift[1], + CDom_reduced4SigExtra_shift[2], + CDom_reduced4SigExtra_shift[3], + CDom_reduced4SigExtra_shift[4], + CDom_reduced4SigExtra_shift[5], + CDom_reduced4SigExtra_shift[6]})) + | (io_fromPreMul_doSubMags + ? io_mulAddResult[23:0] != 24'hFFFFFF + : (|(io_mulAddResult[24:0])))} + : {_notCDom_mainSig_T[51:26], + (|(_notCDom_mainSig_T[25:23])) + | (|({|{|(notCDom_absSigSum[23:22]), |(notCDom_absSigSum[21:20])}, + |{|(notCDom_absSigSum[19:18]), |(notCDom_absSigSum[17:16])}, + |{|(notCDom_absSigSum[15:14]), |(notCDom_absSigSum[13:12])}, + |{|(notCDom_absSigSum[11:10]), |(notCDom_absSigSum[9:8])}, + |{|(notCDom_absSigSum[7:6]), |(notCDom_absSigSum[5:4])}, + |{|(notCDom_absSigSum[3:2]), |(notCDom_absSigSum[1:0])}} + & {notCDom_reduced4SigExtra_shift[1], + notCDom_reduced4SigExtra_shift[2], + notCDom_reduced4SigExtra_shift[3], + notCDom_reduced4SigExtra_shift[4], + notCDom_reduced4SigExtra_shift[5], + notCDom_reduced4SigExtra_shift[6]}))}; +endmodule + +module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24( + input io_invalidExc, + io_in_isNaN, + io_in_isInf, + io_in_isZero, + io_in_sign, + input [9:0] io_in_sExp, + input [26:0] io_in_sig, + input [2:0] io_roundingMode, + output [32:0] io_out, + output [4:0] io_exceptionFlags +); + + wire roundingMode_near_even = io_roundingMode == 3'h0; + wire roundingMode_odd = io_roundingMode == 3'h6; + wire roundMagUp = + io_roundingMode == 3'h2 & io_in_sign | io_roundingMode == 3'h3 & ~io_in_sign; + wire [8:0] _roundMask_T_1 = ~(io_in_sExp[8:0]); + wire [64:0] _GEN = {59'h0, _roundMask_T_1[5:0]}; + wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> _GEN); + wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> _GEN); + wire [24:0] _roundMask_T_73 = + _roundMask_T_1[8] + ? (_roundMask_T_1[7] + ? {~(_roundMask_T_1[6] + ? 22'h0 + : ~{roundMask_shift[42], + roundMask_shift[43], + roundMask_shift[44], + roundMask_shift[45], + roundMask_shift[46], + {{roundMask_shift[47:46], roundMask_shift[49]} & 3'h5, 1'h0} + | {roundMask_shift[49:48], roundMask_shift[51:50]} & 4'h5, + roundMask_shift[51], + roundMask_shift[52], + roundMask_shift[53], + roundMask_shift[54], + roundMask_shift[55], + roundMask_shift[56], + roundMask_shift[57], + roundMask_shift[58], + roundMask_shift[59], + roundMask_shift[60], + roundMask_shift[61], + roundMask_shift[62], + roundMask_shift[63]}), + 3'h7} + : {22'h0, + _roundMask_T_1[6] + ? {roundMask_shift_1[0], roundMask_shift_1[1], roundMask_shift_1[2]} + : 3'h0}) + : 25'h0; + wire _common_underflow_T_4 = _roundMask_T_73[0] | io_in_sig[26]; + wire [25:0] _GEN_0 = {1'h1, ~(_roundMask_T_73[24:1]), ~_common_underflow_T_4}; + wire [25:0] _GEN_1 = {_roundMask_T_73[24:1], _common_underflow_T_4, 1'h1}; + wire [25:0] _roundPosBit_T = io_in_sig[26:1] & _GEN_0 & _GEN_1; + wire [25:0] _anyRoundExtra_T = io_in_sig[25:0] & _GEN_1; + wire anyRound = (|_roundPosBit_T) | (|_anyRoundExtra_T); + wire _overflow_roundMagUp_T = roundingMode_near_even | io_roundingMode == 3'h4; + wire [25:0] roundedSig = + _overflow_roundMagUp_T & (|_roundPosBit_T) | roundMagUp & anyRound + ? {1'h0, io_in_sig[26:2] | {_roundMask_T_73[24:1], _common_underflow_T_4}} + 26'h1 + & ~(roundingMode_near_even & (|_roundPosBit_T) & ~(|_anyRoundExtra_T) + ? {_roundMask_T_73[24:1], _common_underflow_T_4, 1'h1} + : 26'h0) + : {1'h0, io_in_sig[26:2] & {~(_roundMask_T_73[24:1]), ~_common_underflow_T_4}} + | (roundingMode_odd & anyRound ? _GEN_0 & _GEN_1 : 26'h0); + wire [10:0] sRoundedExp = {io_in_sExp[9], io_in_sExp} + {9'h0, roundedSig[25:24]}; + wire common_totalUnderflow = $signed(sRoundedExp) < 11'sh6B; + wire isNaNOut = io_invalidExc | io_in_isNaN; + wire commonCase = ~isNaNOut & ~io_in_isInf & ~io_in_isZero; + wire overflow = commonCase & $signed(sRoundedExp[10:7]) > 4'sh2; + wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp; + wire pegMinNonzeroMagOut = + commonCase & common_totalUnderflow & (roundMagUp | roundingMode_odd); + wire pegMaxFiniteMagOut = overflow & ~overflow_roundMagUp; + wire notNaN_isInfOut = io_in_isInf | overflow & overflow_roundMagUp; + assign io_out = + {~isNaNOut & io_in_sign, + sRoundedExp[8:0] & ~(io_in_isZero | common_totalUnderflow ? 9'h1C0 : 9'h0) + & ~(pegMinNonzeroMagOut ? 9'h194 : 9'h0) & {1'h1, ~pegMaxFiniteMagOut, 7'h7F} + & {2'h3, ~notNaN_isInfOut, 6'h3F} | (pegMinNonzeroMagOut ? 9'h6B : 9'h0) + | (pegMaxFiniteMagOut ? 9'h17F : 9'h0) | (notNaN_isInfOut ? 9'h180 : 9'h0) + | (isNaNOut ? 9'h1C0 : 9'h0), + (isNaNOut | io_in_isZero | common_totalUnderflow + ? {isNaNOut, 22'h0} + : io_in_sig[26] ? roundedSig[23:1] : roundedSig[22:0]) + | {23{pegMaxFiniteMagOut}}}; + assign io_exceptionFlags = + {io_invalidExc, + 1'h0, + overflow, + commonCase + & (common_totalUnderflow | anyRound & io_in_sExp[9:8] != 2'h1 + & (io_in_sig[26] ? _roundMask_T_73[1] : _common_underflow_T_4) + & ~(~(io_in_sig[26] ? _roundMask_T_73[2] : _roundMask_T_73[1]) + & (io_in_sig[26] ? roundedSig[25] : roundedSig[24]) & (|_roundPosBit_T) + & (_overflow_roundMagUp_T & (io_in_sig[26] ? io_in_sig[2] : io_in_sig[1]) + | roundMagUp & (io_in_sig[26] & io_in_sig[2] | (|(io_in_sig[1:0])))))), + overflow | commonCase & (common_totalUnderflow | anyRound)}; +endmodule + +module RoundRawFNToRecFN_e8_s24( + input io_invalidExc, + io_in_isNaN, + io_in_isInf, + io_in_isZero, + io_in_sign, + input [9:0] io_in_sExp, + input [26:0] io_in_sig, + input [2:0] io_roundingMode, + output [32:0] io_out, + output [4:0] io_exceptionFlags +); + + RoundAnyRawFNToRecFN_ie8_is26_oe8_os24 roundAnyRawFNToRecFN ( + .io_invalidExc (io_invalidExc), + .io_in_isNaN (io_in_isNaN), + .io_in_isInf (io_in_isInf), + .io_in_isZero (io_in_isZero), + .io_in_sign (io_in_sign), + .io_in_sExp (io_in_sExp), + .io_in_sig (io_in_sig), + .io_roundingMode (io_roundingMode), + .io_out (io_out), + .io_exceptionFlags (io_exceptionFlags) + ); +endmodule + +module MulAddRecFNPipe_l4_e8_s24( + input clock, + reset, + io_validin, + input [1:0] io_op, + input [32:0] io_a, + io_b, + io_c, + input [2:0] io_roundingMode, + output [32:0] io_out, + output [4:0] io_exceptionFlags, + output io_validout +); + + wire _mulAddRecFNToRaw_postMul_io_invalidExc; + wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; + wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; + wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; + wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; + wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; + wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; + wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddA; + wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddB; + wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; + wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; + wire [4:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; + wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; + reg [23:0] preMulMulAddA_pipe_b; + reg [23:0] preMulMulAddB_pipe_b; + reg [47:0] preMulMulAddC_pipe_b; + reg preMulToPostMul_pipe_v; + reg preMulToPostMul_pipe_b_isSigNaNAny; + reg preMulToPostMul_pipe_b_isNaNAOrB; + reg preMulToPostMul_pipe_b_isInfA; + reg preMulToPostMul_pipe_b_isZeroA; + reg preMulToPostMul_pipe_b_isInfB; + reg preMulToPostMul_pipe_b_isZeroB; + reg preMulToPostMul_pipe_b_signProd; + reg preMulToPostMul_pipe_b_isNaNC; + reg preMulToPostMul_pipe_b_isInfC; + reg preMulToPostMul_pipe_b_isZeroC; + reg [9:0] preMulToPostMul_pipe_b_sExpSum; + reg preMulToPostMul_pipe_b_doSubMags; + reg preMulToPostMul_pipe_b_CIsDominant; + reg [4:0] preMulToPostMul_pipe_b_CDom_CAlignDist; + reg [25:0] preMulToPostMul_pipe_b_highAlignedSigC; + reg preMulToPostMul_pipe_b_bit0AlignedSigC; + reg [47:0] mulResultPipe_pipe_b; + reg [47:0] mulAddCPipe_pipe_b; + reg mulToPostMul_pipe_v; + reg mulToPostMul_pipe_b_isSigNaNAny; + reg mulToPostMul_pipe_b_isNaNAOrB; + reg mulToPostMul_pipe_b_isInfA; + reg mulToPostMul_pipe_b_isZeroA; + reg mulToPostMul_pipe_b_isInfB; + reg mulToPostMul_pipe_b_isZeroB; + reg mulToPostMul_pipe_b_signProd; + reg mulToPostMul_pipe_b_isNaNC; + reg mulToPostMul_pipe_b_isInfC; + reg mulToPostMul_pipe_b_isZeroC; + reg [9:0] mulToPostMul_pipe_b_sExpSum; + reg mulToPostMul_pipe_b_doSubMags; + reg mulToPostMul_pipe_b_CIsDominant; + reg [4:0] mulToPostMul_pipe_b_CDom_CAlignDist; + reg [25:0] mulToPostMul_pipe_b_highAlignedSigC; + reg mulToPostMul_pipe_b_bit0AlignedSigC; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC; + reg [9:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant; + reg [4:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist; + reg [25:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC; + reg [48:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b; + reg mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v; + reg [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b; + reg mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_v; + reg [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_b; + reg [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_pipe_b; + reg roundingMode_stage0_pipe_v; + reg [2:0] roundingMode_stage0_pipe_b; + reg roundingMode_stage0_pipe_pipe_v; + reg [2:0] roundingMode_stage0_pipe_pipe_b; + reg [2:0] roundingMode_stage0_pipe_pipe_pipe_b; + reg valid_stage0_pipe_v; + reg valid_stage0_pipe_pipe_v; + reg valid_stage0_pipe_pipe_pipe_v; + reg roundRawFNToRecFN_io_invalidExc_pipe_b; + reg roundRawFNToRecFN_io_in_pipe_b_isNaN; + reg roundRawFNToRecFN_io_in_pipe_b_isInf; + reg roundRawFNToRecFN_io_in_pipe_b_isZero; + reg roundRawFNToRecFN_io_in_pipe_b_sign; + reg [9:0] roundRawFNToRecFN_io_in_pipe_b_sExp; + reg [26:0] roundRawFNToRecFN_io_in_pipe_b_sig; + reg [2:0] roundRawFNToRecFN_io_roundingMode_pipe_b; + reg io_validout_pipe_v; + always @(posedge clock) begin + if (io_validin) begin + preMulMulAddA_pipe_b <= _mulAddRecFNToRaw_preMul_io_mulAddA; + preMulMulAddB_pipe_b <= _mulAddRecFNToRaw_preMul_io_mulAddB; + preMulMulAddC_pipe_b <= _mulAddRecFNToRaw_preMul_io_mulAddC; + preMulToPostMul_pipe_b_isSigNaNAny <= + _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; + preMulToPostMul_pipe_b_isNaNAOrB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; + preMulToPostMul_pipe_b_isInfA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; + preMulToPostMul_pipe_b_isZeroA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; + preMulToPostMul_pipe_b_isInfB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; + preMulToPostMul_pipe_b_isZeroB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; + preMulToPostMul_pipe_b_signProd <= _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; + preMulToPostMul_pipe_b_isNaNC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; + preMulToPostMul_pipe_b_isInfC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; + preMulToPostMul_pipe_b_isZeroC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; + preMulToPostMul_pipe_b_sExpSum <= _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; + preMulToPostMul_pipe_b_doSubMags <= _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; + preMulToPostMul_pipe_b_CIsDominant <= + _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; + preMulToPostMul_pipe_b_CDom_CAlignDist <= + _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; + preMulToPostMul_pipe_b_highAlignedSigC <= + _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; + preMulToPostMul_pipe_b_bit0AlignedSigC <= + _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b <= io_roundingMode; + roundingMode_stage0_pipe_b <= io_roundingMode; + end + if (preMulToPostMul_pipe_v) begin + mulResultPipe_pipe_b <= + {24'h0, preMulMulAddA_pipe_b} * {24'h0, preMulMulAddB_pipe_b}; + mulAddCPipe_pipe_b <= preMulMulAddC_pipe_b; + mulToPostMul_pipe_b_isSigNaNAny <= preMulToPostMul_pipe_b_isSigNaNAny; + mulToPostMul_pipe_b_isNaNAOrB <= preMulToPostMul_pipe_b_isNaNAOrB; + mulToPostMul_pipe_b_isInfA <= preMulToPostMul_pipe_b_isInfA; + mulToPostMul_pipe_b_isZeroA <= preMulToPostMul_pipe_b_isZeroA; + mulToPostMul_pipe_b_isInfB <= preMulToPostMul_pipe_b_isInfB; + mulToPostMul_pipe_b_isZeroB <= preMulToPostMul_pipe_b_isZeroB; + mulToPostMul_pipe_b_signProd <= preMulToPostMul_pipe_b_signProd; + mulToPostMul_pipe_b_isNaNC <= preMulToPostMul_pipe_b_isNaNC; + mulToPostMul_pipe_b_isInfC <= preMulToPostMul_pipe_b_isInfC; + mulToPostMul_pipe_b_isZeroC <= preMulToPostMul_pipe_b_isZeroC; + mulToPostMul_pipe_b_sExpSum <= preMulToPostMul_pipe_b_sExpSum; + mulToPostMul_pipe_b_doSubMags <= preMulToPostMul_pipe_b_doSubMags; + mulToPostMul_pipe_b_CIsDominant <= preMulToPostMul_pipe_b_CIsDominant; + mulToPostMul_pipe_b_CDom_CAlignDist <= preMulToPostMul_pipe_b_CDom_CAlignDist; + mulToPostMul_pipe_b_highAlignedSigC <= preMulToPostMul_pipe_b_highAlignedSigC; + mulToPostMul_pipe_b_bit0AlignedSigC <= preMulToPostMul_pipe_b_bit0AlignedSigC; + end + if (mulToPostMul_pipe_v) begin + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny <= + mulToPostMul_pipe_b_isSigNaNAny; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB <= + mulToPostMul_pipe_b_isNaNAOrB; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA <= mulToPostMul_pipe_b_isInfA; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA <= + mulToPostMul_pipe_b_isZeroA; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB <= mulToPostMul_pipe_b_isInfB; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB <= + mulToPostMul_pipe_b_isZeroB; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd <= + mulToPostMul_pipe_b_signProd; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC <= mulToPostMul_pipe_b_isNaNC; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC <= mulToPostMul_pipe_b_isInfC; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC <= + mulToPostMul_pipe_b_isZeroC; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum <= + mulToPostMul_pipe_b_sExpSum; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags <= + mulToPostMul_pipe_b_doSubMags; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant <= + mulToPostMul_pipe_b_CIsDominant; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist <= + mulToPostMul_pipe_b_CDom_CAlignDist; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC <= + mulToPostMul_pipe_b_highAlignedSigC; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC <= + mulToPostMul_pipe_b_bit0AlignedSigC; + mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b <= + {1'h0, mulResultPipe_pipe_b} + {1'h0, mulAddCPipe_pipe_b}; + end + if (mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v) + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_b <= + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b; + if (mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_v) + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_pipe_b <= + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_b; + if (roundingMode_stage0_pipe_v) + roundingMode_stage0_pipe_pipe_b <= roundingMode_stage0_pipe_b; + if (roundingMode_stage0_pipe_pipe_v) + roundingMode_stage0_pipe_pipe_pipe_b <= roundingMode_stage0_pipe_pipe_b; + if (valid_stage0_pipe_pipe_pipe_v) begin + roundRawFNToRecFN_io_invalidExc_pipe_b <= _mulAddRecFNToRaw_postMul_io_invalidExc; + roundRawFNToRecFN_io_in_pipe_b_isNaN <= _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; + roundRawFNToRecFN_io_in_pipe_b_isInf <= _mulAddRecFNToRaw_postMul_io_rawOut_isInf; + roundRawFNToRecFN_io_in_pipe_b_isZero <= _mulAddRecFNToRaw_postMul_io_rawOut_isZero; + roundRawFNToRecFN_io_in_pipe_b_sign <= _mulAddRecFNToRaw_postMul_io_rawOut_sign; + roundRawFNToRecFN_io_in_pipe_b_sExp <= _mulAddRecFNToRaw_postMul_io_rawOut_sExp; + roundRawFNToRecFN_io_in_pipe_b_sig <= _mulAddRecFNToRaw_postMul_io_rawOut_sig; + roundRawFNToRecFN_io_roundingMode_pipe_b <= roundingMode_stage0_pipe_pipe_pipe_b; + end + if (reset) begin + preMulToPostMul_pipe_v <= 1'h0; + mulToPostMul_pipe_v <= 1'h0; + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v <= 1'h0; + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_v <= 1'h0; + roundingMode_stage0_pipe_v <= 1'h0; + roundingMode_stage0_pipe_pipe_v <= 1'h0; + valid_stage0_pipe_v <= 1'h0; + valid_stage0_pipe_pipe_v <= 1'h0; + valid_stage0_pipe_pipe_pipe_v <= 1'h0; + io_validout_pipe_v <= 1'h0; + end + else begin + preMulToPostMul_pipe_v <= io_validin; + mulToPostMul_pipe_v <= preMulToPostMul_pipe_v; + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v <= io_validin; + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_v <= + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v; + roundingMode_stage0_pipe_v <= io_validin; + roundingMode_stage0_pipe_pipe_v <= roundingMode_stage0_pipe_v; + valid_stage0_pipe_v <= io_validin; + valid_stage0_pipe_pipe_v <= valid_stage0_pipe_v; + valid_stage0_pipe_pipe_pipe_v <= valid_stage0_pipe_pipe_v; + io_validout_pipe_v <= valid_stage0_pipe_pipe_pipe_v; + end + end // always @(posedge) + MulAddRecFNToRaw_preMul_e8_s24 mulAddRecFNToRaw_preMul ( + .io_op (io_op), + .io_a (io_a), + .io_b (io_b), + .io_c (io_c), + .io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA), + .io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB), + .io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC), + .io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), + .io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), + .io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), + .io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), + .io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB), + .io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB), + .io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), + .io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), + .io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), + .io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), + .io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), + .io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), + .io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), + .io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), + .io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), + .io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC) + ); + MulAddRecFNToRaw_postMul_e8_s24 mulAddRecFNToRaw_postMul ( + .io_fromPreMul_isSigNaNAny + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny), + .io_fromPreMul_isNaNAOrB + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB), + .io_fromPreMul_isInfA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA), + .io_fromPreMul_isZeroA + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA), + .io_fromPreMul_isInfB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB), + .io_fromPreMul_isZeroB + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB), + .io_fromPreMul_signProd + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd), + .io_fromPreMul_isNaNC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC), + .io_fromPreMul_isInfC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC), + .io_fromPreMul_isZeroC + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC), + .io_fromPreMul_sExpSum + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum), + .io_fromPreMul_doSubMags + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags), + .io_fromPreMul_CIsDominant + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant), + .io_fromPreMul_CDom_CAlignDist + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist), + .io_fromPreMul_highAlignedSigC + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC), + .io_fromPreMul_bit0AlignedSigC + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC), + .io_mulAddResult (mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b), + .io_roundingMode + (mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_pipe_b), + .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), + .io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), + .io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), + .io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), + .io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), + .io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), + .io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig) + ); + RoundRawFNToRecFN_e8_s24 roundRawFNToRecFN ( + .io_invalidExc (roundRawFNToRecFN_io_invalidExc_pipe_b), + .io_in_isNaN (roundRawFNToRecFN_io_in_pipe_b_isNaN), + .io_in_isInf (roundRawFNToRecFN_io_in_pipe_b_isInf), + .io_in_isZero (roundRawFNToRecFN_io_in_pipe_b_isZero), + .io_in_sign (roundRawFNToRecFN_io_in_pipe_b_sign), + .io_in_sExp (roundRawFNToRecFN_io_in_pipe_b_sExp), + .io_in_sig (roundRawFNToRecFN_io_in_pipe_b_sig), + .io_roundingMode (roundRawFNToRecFN_io_roundingMode_pipe_b), + .io_out (io_out), + .io_exceptionFlags (io_exceptionFlags) + ); + assign io_validout = io_validout_pipe_v; +endmodule + +module FPUFMAPipe_l5_f32( + input clock, + reset, + io_in_valid, + io_in_bits_ren3, + io_in_bits_swap23, + input [2:0] io_in_bits_rm, + input [1:0] io_in_bits_fmaCmd, + input [64:0] io_in_bits_in1, + io_in_bits_in2, + io_in_bits_in3, + output io_out_valid, + output [64:0] io_out_bits_data, + output [4:0] io_out_bits_exc +); + + wire [32:0] _fma_io_out; + reg valid; + reg [2:0] in_rm; + reg [1:0] in_fmaCmd; + reg [64:0] in_in1; + reg [64:0] in_in2; + reg [64:0] in_in3; + always @(posedge clock) begin + valid <= io_in_valid; + if (io_in_valid) begin + in_rm <= io_in_bits_rm; + in_fmaCmd <= io_in_bits_fmaCmd; + in_in1 <= io_in_bits_in1; + in_in2 <= io_in_bits_swap23 ? 65'h80000000 : io_in_bits_in2; + in_in3 <= + io_in_bits_ren3 | io_in_bits_swap23 + ? io_in_bits_in3 + : {32'h0, (io_in_bits_in1[32:0] ^ io_in_bits_in2[32:0]) & 33'h100000000}; + end + end // always @(posedge) + MulAddRecFNPipe_l4_e8_s24 fma ( + .clock (clock), + .reset (reset), + .io_validin (valid), + .io_op (in_fmaCmd), + .io_a (in_in1[32:0]), + .io_b (in_in2[32:0]), + .io_c (in_in3[32:0]), + .io_roundingMode (in_rm), + .io_out (_fma_io_out), + .io_exceptionFlags (io_out_bits_exc), + .io_validout (io_out_valid) + ); + assign io_out_bits_data = + {32'h0, ({33{_fma_io_out[31:29] != 3'h7}} | 33'h1EF7FFFFF) & _fma_io_out}; +endmodule + +module MulAddRecFNToRaw_preMul_e11_s53( + input [1:0] io_op, + input [64:0] io_a, + io_b, + io_c, + output [52:0] io_mulAddA, + io_mulAddB, + output [105:0] io_mulAddC, + output io_toPostMul_isSigNaNAny, + io_toPostMul_isNaNAOrB, + io_toPostMul_isInfA, + io_toPostMul_isZeroA, + io_toPostMul_isInfB, + io_toPostMul_isZeroB, + io_toPostMul_signProd, + io_toPostMul_isNaNC, + io_toPostMul_isInfC, + io_toPostMul_isZeroC, + output [12:0] io_toPostMul_sExpSum, + output io_toPostMul_doSubMags, + io_toPostMul_CIsDominant, + output [5:0] io_toPostMul_CDom_CAlignDist, + output [54:0] io_toPostMul_highAlignedSigC, + output io_toPostMul_bit0AlignedSigC +); + + wire rawA_isNaN = (&(io_a[63:62])) & io_a[61]; + wire rawB_isNaN = (&(io_b[63:62])) & io_b[61]; + wire rawC_isNaN = (&(io_c[63:62])) & io_c[61]; + wire signProd = io_a[64] ^ io_b[64] ^ io_op[1]; + wire [13:0] _sExpAlignedProd_T_1 = {2'h0, io_a[63:52]} + {2'h0, io_b[63:52]} - 14'h7C8; + wire doSubMags = signProd ^ io_c[64] ^ io_op[0]; + wire [13:0] _sNatCAlignDist_T = _sExpAlignedProd_T_1 - {2'h0, io_c[63:52]}; + wire isMinCAlign = + ~(|(io_a[63:61])) | ~(|(io_b[63:61])) | $signed(_sNatCAlignDist_T) < 14'sh0; + wire CIsDominant = + (|(io_c[63:61])) & (isMinCAlign | _sNatCAlignDist_T[12:0] < 13'h36); + wire [7:0] CAlignDist = + isMinCAlign + ? 8'h0 + : _sNatCAlignDist_T[12:0] < 13'hA1 ? _sNatCAlignDist_T[7:0] : 8'hA1; + wire [164:0] mainAlignedSigC = + $signed($signed({doSubMags + ? {1'h1, ~(|(io_c[63:61])), ~(io_c[51:0])} + : {1'h0, |(io_c[63:61]), io_c[51:0]}, + {111{doSubMags}}}) >>> CAlignDist); + wire [64:0] reduced4CExtra_shift = $signed(65'sh10000000000000000 >>> CAlignDist[7:2]); + wire [12:0] _GEN = + {|(io_c[51:48]), + |(io_c[47:44]), + |(io_c[43:40]), + |(io_c[39:36]), + |(io_c[35:32]), + |(io_c[31:28]), + |(io_c[27:24]), + |(io_c[23:20]), + |(io_c[19:16]), + |(io_c[15:12]), + |(io_c[11:8]), + |(io_c[7:4]), + |(io_c[3:0])} + & {reduced4CExtra_shift[24], + reduced4CExtra_shift[25], + reduced4CExtra_shift[26], + reduced4CExtra_shift[27], + reduced4CExtra_shift[28], + reduced4CExtra_shift[29], + reduced4CExtra_shift[30], + reduced4CExtra_shift[31], + reduced4CExtra_shift[32], + reduced4CExtra_shift[33], + reduced4CExtra_shift[34], + reduced4CExtra_shift[35], + reduced4CExtra_shift[36]}; + assign io_mulAddA = {|(io_a[63:61]), io_a[51:0]}; + assign io_mulAddB = {|(io_b[63:61]), io_b[51:0]}; + assign io_mulAddC = mainAlignedSigC[108:3]; + assign io_toPostMul_isSigNaNAny = + rawA_isNaN & ~(io_a[51]) | rawB_isNaN & ~(io_b[51]) | rawC_isNaN & ~(io_c[51]); + assign io_toPostMul_isNaNAOrB = rawA_isNaN | rawB_isNaN; + assign io_toPostMul_isInfA = (&(io_a[63:62])) & ~(io_a[61]); + assign io_toPostMul_isZeroA = ~(|(io_a[63:61])); + assign io_toPostMul_isInfB = (&(io_b[63:62])) & ~(io_b[61]); + assign io_toPostMul_isZeroB = ~(|(io_b[63:61])); + assign io_toPostMul_signProd = signProd; + assign io_toPostMul_isNaNC = rawC_isNaN; + assign io_toPostMul_isInfC = (&(io_c[63:62])) & ~(io_c[61]); + assign io_toPostMul_isZeroC = ~(|(io_c[63:61])); + assign io_toPostMul_sExpSum = + CIsDominant ? {1'h0, io_c[63:52]} : _sExpAlignedProd_T_1[12:0] - 13'h35; + assign io_toPostMul_doSubMags = doSubMags; + assign io_toPostMul_CIsDominant = CIsDominant; + assign io_toPostMul_CDom_CAlignDist = CAlignDist[5:0]; + assign io_toPostMul_highAlignedSigC = mainAlignedSigC[163:109]; + assign io_toPostMul_bit0AlignedSigC = + doSubMags + ? (&(mainAlignedSigC[2:0])) & ~(|_GEN) + : (|(mainAlignedSigC[2:0])) | (|_GEN); +endmodule + +module MulAddRecFNToRaw_postMul_e11_s53( + input io_fromPreMul_isSigNaNAny, + io_fromPreMul_isNaNAOrB, + io_fromPreMul_isInfA, + io_fromPreMul_isZeroA, + io_fromPreMul_isInfB, + io_fromPreMul_isZeroB, + io_fromPreMul_signProd, + io_fromPreMul_isNaNC, + io_fromPreMul_isInfC, + io_fromPreMul_isZeroC, + input [12:0] io_fromPreMul_sExpSum, + input io_fromPreMul_doSubMags, + io_fromPreMul_CIsDominant, + input [5:0] io_fromPreMul_CDom_CAlignDist, + input [54:0] io_fromPreMul_highAlignedSigC, + input io_fromPreMul_bit0AlignedSigC, + input [106:0] io_mulAddResult, + input [2:0] io_roundingMode, + output io_invalidExc, + io_rawOut_isNaN, + io_rawOut_isInf, + io_rawOut_isZero, + io_rawOut_sign, + output [12:0] io_rawOut_sExp, + output [55:0] io_rawOut_sig +); + + wire roundingMode_min = io_roundingMode == 3'h2; + wire opSignC = io_fromPreMul_signProd ^ io_fromPreMul_doSubMags; + wire [54:0] _sigSum_T_3 = + io_mulAddResult[106] + ? io_fromPreMul_highAlignedSigC + 55'h1 + : io_fromPreMul_highAlignedSigC; + wire [107:0] CDom_absSigSum = + io_fromPreMul_doSubMags + ? ~{_sigSum_T_3, io_mulAddResult[105:53]} + : {1'h0, + io_fromPreMul_highAlignedSigC[54:53], + _sigSum_T_3[52:0], + io_mulAddResult[105:54]}; + wire [170:0] _CDom_mainSig_T = {63'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist; + wire [16:0] CDom_reduced4SigExtra_shift = + $signed(17'sh10000 >>> ~(io_fromPreMul_CDom_CAlignDist[5:2])); + wire [108:0] notCDom_absSigSum = + _sigSum_T_3[2] + ? ~{_sigSum_T_3[1:0], io_mulAddResult[105:0], io_fromPreMul_bit0AlignedSigC} + : {_sigSum_T_3[1:0], io_mulAddResult[105:0], io_fromPreMul_bit0AlignedSigC} + + {108'h0, io_fromPreMul_doSubMags}; + wire [5:0] notCDom_normDistReduced2 = + notCDom_absSigSum[108] + ? 6'h0 + : (|(notCDom_absSigSum[107:106])) + ? 6'h1 + : (|(notCDom_absSigSum[105:104])) + ? 6'h2 + : (|(notCDom_absSigSum[103:102])) + ? 6'h3 + : (|(notCDom_absSigSum[101:100])) + ? 6'h4 + : (|(notCDom_absSigSum[99:98])) + ? 6'h5 + : (|(notCDom_absSigSum[97:96])) + ? 6'h6 + : (|(notCDom_absSigSum[95:94])) + ? 6'h7 + : (|(notCDom_absSigSum[93:92])) + ? 6'h8 + : (|(notCDom_absSigSum[91:90])) + ? 6'h9 + : (|(notCDom_absSigSum[89:88])) + ? 6'hA + : (|(notCDom_absSigSum[87:86])) + ? 6'hB + : (|(notCDom_absSigSum[85:84])) + ? 6'hC + : (|(notCDom_absSigSum[83:82])) + ? 6'hD + : (|(notCDom_absSigSum[81:80])) + ? 6'hE + : (|(notCDom_absSigSum[79:78])) + ? 6'hF + : (|(notCDom_absSigSum[77:76])) + ? 6'h10 + : (|(notCDom_absSigSum[75:74])) + ? 6'h11 + : (|(notCDom_absSigSum[73:72])) + ? 6'h12 + : (|(notCDom_absSigSum[71:70])) + ? 6'h13 + : (|(notCDom_absSigSum[69:68])) + ? 6'h14 + : (|(notCDom_absSigSum[67:66])) + ? 6'h15 + : (|(notCDom_absSigSum[65:64])) + ? 6'h16 + : (|(notCDom_absSigSum[63:62])) + ? 6'h17 + : (|(notCDom_absSigSum[61:60])) + ? 6'h18 + : (|(notCDom_absSigSum[59:58])) + ? 6'h19 + : (|(notCDom_absSigSum[57:56])) + ? 6'h1A + : (|(notCDom_absSigSum[55:54])) + ? 6'h1B + : (|(notCDom_absSigSum[53:52])) + ? 6'h1C + : (|(notCDom_absSigSum[51:50])) + ? 6'h1D + : (|(notCDom_absSigSum[49:48])) + ? 6'h1E + : (|(notCDom_absSigSum[47:46])) + ? 6'h1F + : (|(notCDom_absSigSum[45:44])) + ? 6'h20 + : (|(notCDom_absSigSum[43:42])) + ? 6'h21 + : (|(notCDom_absSigSum[41:40])) + ? 6'h22 + : (|(notCDom_absSigSum[39:38])) + ? 6'h23 + : (|(notCDom_absSigSum[37:36])) + ? 6'h24 + : (|(notCDom_absSigSum[35:34])) + ? 6'h25 + : (|(notCDom_absSigSum[33:32])) + ? 6'h26 + : (|(notCDom_absSigSum[31:30])) + ? 6'h27 + : (|(notCDom_absSigSum[29:28])) + ? 6'h28 + : (|(notCDom_absSigSum[27:26])) + ? 6'h29 + : (|(notCDom_absSigSum[25:24])) + ? 6'h2A + : (|(notCDom_absSigSum[23:22])) + ? 6'h2B + : (|(notCDom_absSigSum[21:20])) + ? 6'h2C + : (|(notCDom_absSigSum[19:18])) + ? 6'h2D + : (|(notCDom_absSigSum[17:16])) + ? 6'h2E + : (|(notCDom_absSigSum[15:14])) + ? 6'h2F + : (|(notCDom_absSigSum[13:12])) + ? 6'h30 + : (|(notCDom_absSigSum[11:10])) + ? 6'h31 + : (|(notCDom_absSigSum[9:8])) + ? 6'h32 + : (|(notCDom_absSigSum[7:6])) + ? 6'h33 + : (|(notCDom_absSigSum[5:4])) + ? 6'h34 + : (|(notCDom_absSigSum[3:2])) + ? 6'h35 + : 6'h36; + wire [235:0] _notCDom_mainSig_T = + {127'h0, notCDom_absSigSum} << {229'h0, notCDom_normDistReduced2, 1'h0}; + wire [32:0] notCDom_reduced4SigExtra_shift = + $signed(33'sh100000000 >>> ~(notCDom_normDistReduced2[5:1])); + wire notCDom_completeCancellation = _notCDom_mainSig_T[109:108] == 2'h0; + wire notNaN_isInfProd = io_fromPreMul_isInfA | io_fromPreMul_isInfB; + wire notNaN_isInfOut = notNaN_isInfProd | io_fromPreMul_isInfC; + wire notNaN_addZeros = + (io_fromPreMul_isZeroA | io_fromPreMul_isZeroB) & io_fromPreMul_isZeroC; + assign io_invalidExc = + io_fromPreMul_isSigNaNAny | io_fromPreMul_isInfA & io_fromPreMul_isZeroB + | io_fromPreMul_isZeroA & io_fromPreMul_isInfB | ~io_fromPreMul_isNaNAOrB + & notNaN_isInfProd & io_fromPreMul_isInfC & io_fromPreMul_doSubMags; + assign io_rawOut_isNaN = io_fromPreMul_isNaNAOrB | io_fromPreMul_isNaNC; + assign io_rawOut_isInf = notNaN_isInfOut; + assign io_rawOut_isZero = + notNaN_addZeros | ~io_fromPreMul_CIsDominant & notCDom_completeCancellation; + assign io_rawOut_sign = + notNaN_isInfProd & io_fromPreMul_signProd | io_fromPreMul_isInfC & opSignC + | notNaN_addZeros & ~roundingMode_min & io_fromPreMul_signProd & opSignC + | notNaN_addZeros & roundingMode_min & (io_fromPreMul_signProd | opSignC) + | ~notNaN_isInfOut & ~notNaN_addZeros + & (io_fromPreMul_CIsDominant + ? opSignC + : notCDom_completeCancellation + ? roundingMode_min + : io_fromPreMul_signProd ^ _sigSum_T_3[2]); + assign io_rawOut_sExp = + io_fromPreMul_CIsDominant + ? io_fromPreMul_sExpSum - {12'h0, io_fromPreMul_doSubMags} + : io_fromPreMul_sExpSum - {6'h0, notCDom_normDistReduced2, 1'h0}; + assign io_rawOut_sig = + io_fromPreMul_CIsDominant + ? {_CDom_mainSig_T[107:53], + (|(_CDom_mainSig_T[52:50])) + | (|({|(CDom_absSigSum[49:46]), + |(CDom_absSigSum[45:42]), + |(CDom_absSigSum[41:38]), + |(CDom_absSigSum[37:34]), + |(CDom_absSigSum[33:30]), + |(CDom_absSigSum[29:26]), + |(CDom_absSigSum[25:22]), + |(CDom_absSigSum[21:18]), + |(CDom_absSigSum[17:14]), + |(CDom_absSigSum[13:10]), + |(CDom_absSigSum[9:6]), + |(CDom_absSigSum[5:2]), + |(CDom_absSigSum[1:0])} + & {CDom_reduced4SigExtra_shift[1], + CDom_reduced4SigExtra_shift[2], + CDom_reduced4SigExtra_shift[3], + CDom_reduced4SigExtra_shift[4], + CDom_reduced4SigExtra_shift[5], + CDom_reduced4SigExtra_shift[6], + CDom_reduced4SigExtra_shift[7], + CDom_reduced4SigExtra_shift[8], + CDom_reduced4SigExtra_shift[9], + CDom_reduced4SigExtra_shift[10], + CDom_reduced4SigExtra_shift[11], + CDom_reduced4SigExtra_shift[12], + CDom_reduced4SigExtra_shift[13]})) + | (io_fromPreMul_doSubMags + ? io_mulAddResult[52:0] != 53'h1FFFFFFFFFFFFF + : (|(io_mulAddResult[53:0])))} + : {_notCDom_mainSig_T[109:55], + (|(_notCDom_mainSig_T[54:52])) + | (|({|{|(notCDom_absSigSum[51:50]), |(notCDom_absSigSum[49:48])}, + |{|(notCDom_absSigSum[47:46]), |(notCDom_absSigSum[45:44])}, + |{|(notCDom_absSigSum[43:42]), |(notCDom_absSigSum[41:40])}, + |{|(notCDom_absSigSum[39:38]), |(notCDom_absSigSum[37:36])}, + |{|(notCDom_absSigSum[35:34]), |(notCDom_absSigSum[33:32])}, + |{|(notCDom_absSigSum[31:30]), |(notCDom_absSigSum[29:28])}, + |{|(notCDom_absSigSum[27:26]), |(notCDom_absSigSum[25:24])}, + |{|(notCDom_absSigSum[23:22]), |(notCDom_absSigSum[21:20])}, + |{|(notCDom_absSigSum[19:18]), |(notCDom_absSigSum[17:16])}, + |{|(notCDom_absSigSum[15:14]), |(notCDom_absSigSum[13:12])}, + |{|(notCDom_absSigSum[11:10]), |(notCDom_absSigSum[9:8])}, + |{|(notCDom_absSigSum[7:6]), |(notCDom_absSigSum[5:4])}, + |{|(notCDom_absSigSum[3:2]), |(notCDom_absSigSum[1:0])}} + & {notCDom_reduced4SigExtra_shift[1], + notCDom_reduced4SigExtra_shift[2], + notCDom_reduced4SigExtra_shift[3], + notCDom_reduced4SigExtra_shift[4], + notCDom_reduced4SigExtra_shift[5], + notCDom_reduced4SigExtra_shift[6], + notCDom_reduced4SigExtra_shift[7], + notCDom_reduced4SigExtra_shift[8], + notCDom_reduced4SigExtra_shift[9], + notCDom_reduced4SigExtra_shift[10], + notCDom_reduced4SigExtra_shift[11], + notCDom_reduced4SigExtra_shift[12], + notCDom_reduced4SigExtra_shift[13]}))}; +endmodule + +module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53( + input io_invalidExc, + io_in_isNaN, + io_in_isInf, + io_in_isZero, + io_in_sign, + input [12:0] io_in_sExp, + input [55:0] io_in_sig, + input [2:0] io_roundingMode, + output [64:0] io_out, + output [4:0] io_exceptionFlags +); + + wire roundingMode_near_even = io_roundingMode == 3'h0; + wire roundingMode_odd = io_roundingMode == 3'h6; + wire roundMagUp = + io_roundingMode == 3'h2 & io_in_sign | io_roundingMode == 3'h3 & ~io_in_sign; + wire [11:0] _roundMask_T_1 = ~(io_in_sExp[11:0]); + wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> _roundMask_T_1[5:0]); + wire [7:0] _GEN = + {{roundMask_shift[24:21], roundMask_shift[28:27]} & 6'h33, 2'h0} + | {roundMask_shift[28:25], roundMask_shift[32:29]} & 8'h33; + wire [18:0] _GEN_0 = + {roundMask_shift[18:17], + roundMask_shift[20:19], + roundMask_shift[22:21], + _GEN, + roundMask_shift[32:31], + roundMask_shift[34:33], + roundMask_shift[36]} & 19'h55555; + wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> _roundMask_T_1[5:0]); + wire [53:0] _roundMask_T_128 = + _roundMask_T_1[11] + ? (_roundMask_T_1[10] + ? {~(_roundMask_T_1[9] | _roundMask_T_1[8] | _roundMask_T_1[7] + | _roundMask_T_1[6] + ? 51'h0 + : ~{roundMask_shift[13], + roundMask_shift[14], + roundMask_shift[15], + roundMask_shift[16], + roundMask_shift[17], + _GEN_0[18:15] | {roundMask_shift[20:19], roundMask_shift[22:21]} + & 4'h5, + _GEN_0[14:7] | _GEN & 8'h55, + _GEN[1], + _GEN_0[5] | roundMask_shift[31], + roundMask_shift[32], + roundMask_shift[33], + {_GEN_0[2:0], 1'h0} + | {roundMask_shift[36:35], roundMask_shift[38:37]} & 4'h5, + roundMask_shift[38], + roundMask_shift[39], + roundMask_shift[40], + roundMask_shift[41], + roundMask_shift[42], + roundMask_shift[43], + roundMask_shift[44], + roundMask_shift[45], + roundMask_shift[46], + roundMask_shift[47], + roundMask_shift[48], + roundMask_shift[49], + {{roundMask_shift[50:49], roundMask_shift[52]} & 3'h5, 1'h0} + | {roundMask_shift[52:51], roundMask_shift[54:53]} & 4'h5, + roundMask_shift[54], + roundMask_shift[55], + roundMask_shift[56], + roundMask_shift[57], + roundMask_shift[58], + roundMask_shift[59], + roundMask_shift[60], + roundMask_shift[61], + roundMask_shift[62], + roundMask_shift[63]}), + 3'h7} + : {51'h0, + _roundMask_T_1[9] & _roundMask_T_1[8] & _roundMask_T_1[7] + & _roundMask_T_1[6] + ? {roundMask_shift_1[0], roundMask_shift_1[1], roundMask_shift_1[2]} + : 3'h0}) + : 54'h0; + wire _common_underflow_T_4 = _roundMask_T_128[0] | io_in_sig[55]; + wire [54:0] _GEN_1 = {1'h1, ~(_roundMask_T_128[53:1]), ~_common_underflow_T_4}; + wire [54:0] _GEN_2 = {_roundMask_T_128[53:1], _common_underflow_T_4, 1'h1}; + wire [54:0] _roundPosBit_T = io_in_sig[55:1] & _GEN_1 & _GEN_2; + wire [54:0] _anyRoundExtra_T = io_in_sig[54:0] & _GEN_2; + wire anyRound = (|_roundPosBit_T) | (|_anyRoundExtra_T); + wire _overflow_roundMagUp_T = roundingMode_near_even | io_roundingMode == 3'h4; + wire [54:0] roundedSig = + _overflow_roundMagUp_T & (|_roundPosBit_T) | roundMagUp & anyRound + ? {1'h0, io_in_sig[55:2] | {_roundMask_T_128[53:1], _common_underflow_T_4}} + 55'h1 + & ~(roundingMode_near_even & (|_roundPosBit_T) & ~(|_anyRoundExtra_T) + ? {_roundMask_T_128[53:1], _common_underflow_T_4, 1'h1} + : 55'h0) + : {1'h0, io_in_sig[55:2] & {~(_roundMask_T_128[53:1]), ~_common_underflow_T_4}} + | (roundingMode_odd & anyRound ? _GEN_1 & _GEN_2 : 55'h0); + wire [13:0] sRoundedExp = {io_in_sExp[12], io_in_sExp} + {12'h0, roundedSig[54:53]}; + wire common_totalUnderflow = $signed(sRoundedExp) < 14'sh3CE; + wire isNaNOut = io_invalidExc | io_in_isNaN; + wire commonCase = ~isNaNOut & ~io_in_isInf & ~io_in_isZero; + wire overflow = commonCase & $signed(sRoundedExp[13:10]) > 4'sh2; + wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp; + wire pegMinNonzeroMagOut = + commonCase & common_totalUnderflow & (roundMagUp | roundingMode_odd); + wire pegMaxFiniteMagOut = overflow & ~overflow_roundMagUp; + wire notNaN_isInfOut = io_in_isInf | overflow & overflow_roundMagUp; + assign io_out = + {~isNaNOut & io_in_sign, + sRoundedExp[11:0] & ~(io_in_isZero | common_totalUnderflow ? 12'hE00 : 12'h0) + & ~(pegMinNonzeroMagOut ? 12'hC31 : 12'h0) & {1'h1, ~pegMaxFiniteMagOut, 10'h3FF} + & {2'h3, ~notNaN_isInfOut, 9'h1FF} | (pegMinNonzeroMagOut ? 12'h3CE : 12'h0) + | (pegMaxFiniteMagOut ? 12'hBFF : 12'h0) | (notNaN_isInfOut ? 12'hC00 : 12'h0) + | (isNaNOut ? 12'hE00 : 12'h0), + (isNaNOut | io_in_isZero | common_totalUnderflow + ? {isNaNOut, 51'h0} + : io_in_sig[55] ? roundedSig[52:1] : roundedSig[51:0]) + | {52{pegMaxFiniteMagOut}}}; + assign io_exceptionFlags = + {io_invalidExc, + 1'h0, + overflow, + commonCase + & (common_totalUnderflow | anyRound & io_in_sExp[12:11] != 2'h1 + & (io_in_sig[55] ? _roundMask_T_128[1] : _common_underflow_T_4) + & ~(~(io_in_sig[55] ? _roundMask_T_128[2] : _roundMask_T_128[1]) + & (io_in_sig[55] ? roundedSig[54] : roundedSig[53]) & (|_roundPosBit_T) + & (_overflow_roundMagUp_T & (io_in_sig[55] ? io_in_sig[2] : io_in_sig[1]) + | roundMagUp & (io_in_sig[55] & io_in_sig[2] | (|(io_in_sig[1:0])))))), + overflow | commonCase & (common_totalUnderflow | anyRound)}; +endmodule + +module RoundRawFNToRecFN_e11_s53( + input io_invalidExc, + io_in_isNaN, + io_in_isInf, + io_in_isZero, + io_in_sign, + input [12:0] io_in_sExp, + input [55:0] io_in_sig, + input [2:0] io_roundingMode, + output [64:0] io_out, + output [4:0] io_exceptionFlags +); + + RoundAnyRawFNToRecFN_ie11_is55_oe11_os53 roundAnyRawFNToRecFN ( + .io_invalidExc (io_invalidExc), + .io_in_isNaN (io_in_isNaN), + .io_in_isInf (io_in_isInf), + .io_in_isZero (io_in_isZero), + .io_in_sign (io_in_sign), + .io_in_sExp (io_in_sExp), + .io_in_sig (io_in_sig), + .io_roundingMode (io_roundingMode), + .io_out (io_out), + .io_exceptionFlags (io_exceptionFlags) + ); +endmodule + +module MulAddRecFNPipe_l4_e11_s53( + input clock, + reset, + io_validin, + input [1:0] io_op, + input [64:0] io_a, + io_b, + io_c, + input [2:0] io_roundingMode, + output [64:0] io_out, + output [4:0] io_exceptionFlags, + output io_validout +); + + wire _mulAddRecFNToRaw_postMul_io_invalidExc; + wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; + wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; + wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; + wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; + wire [12:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; + wire [55:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; + wire [52:0] _mulAddRecFNToRaw_preMul_io_mulAddA; + wire [52:0] _mulAddRecFNToRaw_preMul_io_mulAddB; + wire [105:0] _mulAddRecFNToRaw_preMul_io_mulAddC; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; + wire [12:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; + wire [5:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; + wire [54:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; + reg [52:0] preMulMulAddA_pipe_b; + reg [52:0] preMulMulAddB_pipe_b; + reg [105:0] preMulMulAddC_pipe_b; + reg preMulToPostMul_pipe_v; + reg preMulToPostMul_pipe_b_isSigNaNAny; + reg preMulToPostMul_pipe_b_isNaNAOrB; + reg preMulToPostMul_pipe_b_isInfA; + reg preMulToPostMul_pipe_b_isZeroA; + reg preMulToPostMul_pipe_b_isInfB; + reg preMulToPostMul_pipe_b_isZeroB; + reg preMulToPostMul_pipe_b_signProd; + reg preMulToPostMul_pipe_b_isNaNC; + reg preMulToPostMul_pipe_b_isInfC; + reg preMulToPostMul_pipe_b_isZeroC; + reg [12:0] preMulToPostMul_pipe_b_sExpSum; + reg preMulToPostMul_pipe_b_doSubMags; + reg preMulToPostMul_pipe_b_CIsDominant; + reg [5:0] preMulToPostMul_pipe_b_CDom_CAlignDist; + reg [54:0] preMulToPostMul_pipe_b_highAlignedSigC; + reg preMulToPostMul_pipe_b_bit0AlignedSigC; + reg [105:0] mulResultPipe_pipe_b; + reg [105:0] mulAddCPipe_pipe_b; + reg mulToPostMul_pipe_v; + reg mulToPostMul_pipe_b_isSigNaNAny; + reg mulToPostMul_pipe_b_isNaNAOrB; + reg mulToPostMul_pipe_b_isInfA; + reg mulToPostMul_pipe_b_isZeroA; + reg mulToPostMul_pipe_b_isInfB; + reg mulToPostMul_pipe_b_isZeroB; + reg mulToPostMul_pipe_b_signProd; + reg mulToPostMul_pipe_b_isNaNC; + reg mulToPostMul_pipe_b_isInfC; + reg mulToPostMul_pipe_b_isZeroC; + reg [12:0] mulToPostMul_pipe_b_sExpSum; + reg mulToPostMul_pipe_b_doSubMags; + reg mulToPostMul_pipe_b_CIsDominant; + reg [5:0] mulToPostMul_pipe_b_CDom_CAlignDist; + reg [54:0] mulToPostMul_pipe_b_highAlignedSigC; + reg mulToPostMul_pipe_b_bit0AlignedSigC; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC; + reg [12:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant; + reg [5:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist; + reg [54:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC; + reg [106:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b; + reg mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v; + reg [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b; + reg mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_v; + reg [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_b; + reg [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_pipe_b; + reg roundingMode_stage0_pipe_v; + reg [2:0] roundingMode_stage0_pipe_b; + reg roundingMode_stage0_pipe_pipe_v; + reg [2:0] roundingMode_stage0_pipe_pipe_b; + reg [2:0] roundingMode_stage0_pipe_pipe_pipe_b; + reg valid_stage0_pipe_v; + reg valid_stage0_pipe_pipe_v; + reg valid_stage0_pipe_pipe_pipe_v; + reg roundRawFNToRecFN_io_invalidExc_pipe_b; + reg roundRawFNToRecFN_io_in_pipe_b_isNaN; + reg roundRawFNToRecFN_io_in_pipe_b_isInf; + reg roundRawFNToRecFN_io_in_pipe_b_isZero; + reg roundRawFNToRecFN_io_in_pipe_b_sign; + reg [12:0] roundRawFNToRecFN_io_in_pipe_b_sExp; + reg [55:0] roundRawFNToRecFN_io_in_pipe_b_sig; + reg [2:0] roundRawFNToRecFN_io_roundingMode_pipe_b; + reg io_validout_pipe_v; + always @(posedge clock) begin + if (io_validin) begin + preMulMulAddA_pipe_b <= _mulAddRecFNToRaw_preMul_io_mulAddA; + preMulMulAddB_pipe_b <= _mulAddRecFNToRaw_preMul_io_mulAddB; + preMulMulAddC_pipe_b <= _mulAddRecFNToRaw_preMul_io_mulAddC; + preMulToPostMul_pipe_b_isSigNaNAny <= + _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; + preMulToPostMul_pipe_b_isNaNAOrB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; + preMulToPostMul_pipe_b_isInfA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; + preMulToPostMul_pipe_b_isZeroA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; + preMulToPostMul_pipe_b_isInfB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; + preMulToPostMul_pipe_b_isZeroB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; + preMulToPostMul_pipe_b_signProd <= _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; + preMulToPostMul_pipe_b_isNaNC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; + preMulToPostMul_pipe_b_isInfC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; + preMulToPostMul_pipe_b_isZeroC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; + preMulToPostMul_pipe_b_sExpSum <= _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; + preMulToPostMul_pipe_b_doSubMags <= _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; + preMulToPostMul_pipe_b_CIsDominant <= + _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; + preMulToPostMul_pipe_b_CDom_CAlignDist <= + _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; + preMulToPostMul_pipe_b_highAlignedSigC <= + _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; + preMulToPostMul_pipe_b_bit0AlignedSigC <= + _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b <= io_roundingMode; + roundingMode_stage0_pipe_b <= io_roundingMode; + end + if (preMulToPostMul_pipe_v) begin + mulResultPipe_pipe_b <= + {53'h0, preMulMulAddA_pipe_b} * {53'h0, preMulMulAddB_pipe_b}; + mulAddCPipe_pipe_b <= preMulMulAddC_pipe_b; + mulToPostMul_pipe_b_isSigNaNAny <= preMulToPostMul_pipe_b_isSigNaNAny; + mulToPostMul_pipe_b_isNaNAOrB <= preMulToPostMul_pipe_b_isNaNAOrB; + mulToPostMul_pipe_b_isInfA <= preMulToPostMul_pipe_b_isInfA; + mulToPostMul_pipe_b_isZeroA <= preMulToPostMul_pipe_b_isZeroA; + mulToPostMul_pipe_b_isInfB <= preMulToPostMul_pipe_b_isInfB; + mulToPostMul_pipe_b_isZeroB <= preMulToPostMul_pipe_b_isZeroB; + mulToPostMul_pipe_b_signProd <= preMulToPostMul_pipe_b_signProd; + mulToPostMul_pipe_b_isNaNC <= preMulToPostMul_pipe_b_isNaNC; + mulToPostMul_pipe_b_isInfC <= preMulToPostMul_pipe_b_isInfC; + mulToPostMul_pipe_b_isZeroC <= preMulToPostMul_pipe_b_isZeroC; + mulToPostMul_pipe_b_sExpSum <= preMulToPostMul_pipe_b_sExpSum; + mulToPostMul_pipe_b_doSubMags <= preMulToPostMul_pipe_b_doSubMags; + mulToPostMul_pipe_b_CIsDominant <= preMulToPostMul_pipe_b_CIsDominant; + mulToPostMul_pipe_b_CDom_CAlignDist <= preMulToPostMul_pipe_b_CDom_CAlignDist; + mulToPostMul_pipe_b_highAlignedSigC <= preMulToPostMul_pipe_b_highAlignedSigC; + mulToPostMul_pipe_b_bit0AlignedSigC <= preMulToPostMul_pipe_b_bit0AlignedSigC; + end + if (mulToPostMul_pipe_v) begin + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny <= + mulToPostMul_pipe_b_isSigNaNAny; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB <= + mulToPostMul_pipe_b_isNaNAOrB; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA <= mulToPostMul_pipe_b_isInfA; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA <= + mulToPostMul_pipe_b_isZeroA; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB <= mulToPostMul_pipe_b_isInfB; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB <= + mulToPostMul_pipe_b_isZeroB; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd <= + mulToPostMul_pipe_b_signProd; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC <= mulToPostMul_pipe_b_isNaNC; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC <= mulToPostMul_pipe_b_isInfC; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC <= + mulToPostMul_pipe_b_isZeroC; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum <= + mulToPostMul_pipe_b_sExpSum; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags <= + mulToPostMul_pipe_b_doSubMags; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant <= + mulToPostMul_pipe_b_CIsDominant; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist <= + mulToPostMul_pipe_b_CDom_CAlignDist; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC <= + mulToPostMul_pipe_b_highAlignedSigC; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC <= + mulToPostMul_pipe_b_bit0AlignedSigC; + mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b <= + {1'h0, mulResultPipe_pipe_b} + {1'h0, mulAddCPipe_pipe_b}; + end + if (mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v) + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_b <= + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b; + if (mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_v) + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_pipe_b <= + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_b; + if (roundingMode_stage0_pipe_v) + roundingMode_stage0_pipe_pipe_b <= roundingMode_stage0_pipe_b; + if (roundingMode_stage0_pipe_pipe_v) + roundingMode_stage0_pipe_pipe_pipe_b <= roundingMode_stage0_pipe_pipe_b; + if (valid_stage0_pipe_pipe_pipe_v) begin + roundRawFNToRecFN_io_invalidExc_pipe_b <= _mulAddRecFNToRaw_postMul_io_invalidExc; + roundRawFNToRecFN_io_in_pipe_b_isNaN <= _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; + roundRawFNToRecFN_io_in_pipe_b_isInf <= _mulAddRecFNToRaw_postMul_io_rawOut_isInf; + roundRawFNToRecFN_io_in_pipe_b_isZero <= _mulAddRecFNToRaw_postMul_io_rawOut_isZero; + roundRawFNToRecFN_io_in_pipe_b_sign <= _mulAddRecFNToRaw_postMul_io_rawOut_sign; + roundRawFNToRecFN_io_in_pipe_b_sExp <= _mulAddRecFNToRaw_postMul_io_rawOut_sExp; + roundRawFNToRecFN_io_in_pipe_b_sig <= _mulAddRecFNToRaw_postMul_io_rawOut_sig; + roundRawFNToRecFN_io_roundingMode_pipe_b <= roundingMode_stage0_pipe_pipe_pipe_b; + end + if (reset) begin + preMulToPostMul_pipe_v <= 1'h0; + mulToPostMul_pipe_v <= 1'h0; + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v <= 1'h0; + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_v <= 1'h0; + roundingMode_stage0_pipe_v <= 1'h0; + roundingMode_stage0_pipe_pipe_v <= 1'h0; + valid_stage0_pipe_v <= 1'h0; + valid_stage0_pipe_pipe_v <= 1'h0; + valid_stage0_pipe_pipe_pipe_v <= 1'h0; + io_validout_pipe_v <= 1'h0; + end + else begin + preMulToPostMul_pipe_v <= io_validin; + mulToPostMul_pipe_v <= preMulToPostMul_pipe_v; + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v <= io_validin; + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_v <= + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v; + roundingMode_stage0_pipe_v <= io_validin; + roundingMode_stage0_pipe_pipe_v <= roundingMode_stage0_pipe_v; + valid_stage0_pipe_v <= io_validin; + valid_stage0_pipe_pipe_v <= valid_stage0_pipe_v; + valid_stage0_pipe_pipe_pipe_v <= valid_stage0_pipe_pipe_v; + io_validout_pipe_v <= valid_stage0_pipe_pipe_pipe_v; + end + end // always @(posedge) + MulAddRecFNToRaw_preMul_e11_s53 mulAddRecFNToRaw_preMul ( + .io_op (io_op), + .io_a (io_a), + .io_b (io_b), + .io_c (io_c), + .io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA), + .io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB), + .io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC), + .io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), + .io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), + .io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), + .io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), + .io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB), + .io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB), + .io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), + .io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), + .io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), + .io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), + .io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), + .io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), + .io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), + .io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), + .io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), + .io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC) + ); + MulAddRecFNToRaw_postMul_e11_s53 mulAddRecFNToRaw_postMul ( + .io_fromPreMul_isSigNaNAny + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny), + .io_fromPreMul_isNaNAOrB + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB), + .io_fromPreMul_isInfA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA), + .io_fromPreMul_isZeroA + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA), + .io_fromPreMul_isInfB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB), + .io_fromPreMul_isZeroB + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB), + .io_fromPreMul_signProd + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd), + .io_fromPreMul_isNaNC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC), + .io_fromPreMul_isInfC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC), + .io_fromPreMul_isZeroC + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC), + .io_fromPreMul_sExpSum + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum), + .io_fromPreMul_doSubMags + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags), + .io_fromPreMul_CIsDominant + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant), + .io_fromPreMul_CDom_CAlignDist + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist), + .io_fromPreMul_highAlignedSigC + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC), + .io_fromPreMul_bit0AlignedSigC + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC), + .io_mulAddResult (mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b), + .io_roundingMode + (mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_pipe_b), + .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), + .io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), + .io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), + .io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), + .io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), + .io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), + .io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig) + ); + RoundRawFNToRecFN_e11_s53 roundRawFNToRecFN ( + .io_invalidExc (roundRawFNToRecFN_io_invalidExc_pipe_b), + .io_in_isNaN (roundRawFNToRecFN_io_in_pipe_b_isNaN), + .io_in_isInf (roundRawFNToRecFN_io_in_pipe_b_isInf), + .io_in_isZero (roundRawFNToRecFN_io_in_pipe_b_isZero), + .io_in_sign (roundRawFNToRecFN_io_in_pipe_b_sign), + .io_in_sExp (roundRawFNToRecFN_io_in_pipe_b_sExp), + .io_in_sig (roundRawFNToRecFN_io_in_pipe_b_sig), + .io_roundingMode (roundRawFNToRecFN_io_roundingMode_pipe_b), + .io_out (io_out), + .io_exceptionFlags (io_exceptionFlags) + ); + assign io_validout = io_validout_pipe_v; +endmodule + +module FPUFMAPipe_l6_f64( + input clock, + reset, + io_in_valid, + io_in_bits_ren3, + io_in_bits_swap23, + input [2:0] io_in_bits_rm, + input [1:0] io_in_bits_fmaCmd, + input [64:0] io_in_bits_in1, + io_in_bits_in2, + io_in_bits_in3, + output [64:0] io_out_bits_data, + output [4:0] io_out_bits_exc +); + + wire [64:0] _fma_io_out; + wire [4:0] _fma_io_exceptionFlags; + wire _fma_io_validout; + reg valid; + reg [2:0] in_rm; + reg [1:0] in_fmaCmd; + reg [64:0] in_in1; + reg [64:0] in_in2; + reg [64:0] in_in3; + reg [64:0] io_out_pipe_b_data; + reg [4:0] io_out_pipe_b_exc; + always @(posedge clock) begin + valid <= io_in_valid; + if (io_in_valid) begin + in_rm <= io_in_bits_rm; + in_fmaCmd <= io_in_bits_fmaCmd; + in_in1 <= io_in_bits_in1; + in_in2 <= io_in_bits_swap23 ? 65'h8000000000000000 : io_in_bits_in2; + in_in3 <= + io_in_bits_ren3 | io_in_bits_swap23 + ? io_in_bits_in3 + : (io_in_bits_in1 ^ io_in_bits_in2) & 65'h10000000000000000; + end + if (_fma_io_validout) begin + io_out_pipe_b_data <= + ({65{_fma_io_out[63:61] != 3'h7}} | 65'h1EFEFFFFFFFFFFFFF) & _fma_io_out; + io_out_pipe_b_exc <= _fma_io_exceptionFlags; + end + end // always @(posedge) + MulAddRecFNPipe_l4_e11_s53 fma ( + .clock (clock), + .reset (reset), + .io_validin (valid), + .io_op (in_fmaCmd), + .io_a (in_in1), + .io_b (in_in2), + .io_c (in_in3), + .io_roundingMode (in_rm), + .io_out (_fma_io_out), + .io_exceptionFlags (_fma_io_exceptionFlags), + .io_validout (_fma_io_validout) + ); + assign io_out_bits_data = io_out_pipe_b_data; + assign io_out_bits_exc = io_out_pipe_b_exc; +endmodule + +module RoundAnyRawFNToRecFN_ie11_is55_oe5_os11( + input io_invalidExc, + io_in_isNaN, + io_in_isInf, + io_in_isZero, + io_in_sign, + input [12:0] io_in_sExp, + input [55:0] io_in_sig, + input [2:0] io_roundingMode, + output [16:0] io_out, + output [4:0] io_exceptionFlags +); + + wire roundingMode_near_even = io_roundingMode == 3'h0; + wire roundingMode_odd = io_roundingMode == 3'h6; + wire roundMagUp = + io_roundingMode == 3'h2 & io_in_sign | io_roundingMode == 3'h3 & ~io_in_sign; + wire [13:0] sAdjustedExp = {io_in_sExp[12], io_in_sExp} - 14'h7E0; + wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> ~(sAdjustedExp[5:0])); + wire [1:0] _GEN = {roundMask_shift[10], roundMask_shift[11]}; + wire _common_underflow_T_4 = roundMask_shift[18] | io_in_sig[55]; + wire [12:0] _GEN_0 = + {1'h1, + ~(roundMask_shift[7]), + ~(roundMask_shift[8]), + ~(roundMask_shift[9]), + ~_GEN, + ~(roundMask_shift[12]), + ~(roundMask_shift[13]), + ~(roundMask_shift[14]), + ~(roundMask_shift[15]), + ~(roundMask_shift[16]), + ~(roundMask_shift[17]), + ~_common_underflow_T_4}; + wire [12:0] _GEN_1 = + {roundMask_shift[7], + roundMask_shift[8], + roundMask_shift[9], + roundMask_shift[10], + roundMask_shift[11], + roundMask_shift[12], + roundMask_shift[13], + roundMask_shift[14], + roundMask_shift[15], + roundMask_shift[16], + roundMask_shift[17], + _common_underflow_T_4, + 1'h1}; + wire [12:0] _roundPosBit_T = io_in_sig[55:43] & _GEN_0 & _GEN_1; + wire [12:0] _anyRoundExtra_T = {io_in_sig[54:43], |(io_in_sig[42:0])} & _GEN_1; + wire anyRound = (|_roundPosBit_T) | (|_anyRoundExtra_T); + wire _overflow_roundMagUp_T = roundingMode_near_even | io_roundingMode == 3'h4; + wire [12:0] roundedSig = + _overflow_roundMagUp_T & (|_roundPosBit_T) | roundMagUp & anyRound + ? {1'h0, + io_in_sig[55] | roundMask_shift[7], + io_in_sig[54] | roundMask_shift[8], + io_in_sig[53] | roundMask_shift[9], + io_in_sig[52:51] | _GEN, + io_in_sig[50] | roundMask_shift[12], + io_in_sig[49] | roundMask_shift[13], + io_in_sig[48] | roundMask_shift[14], + io_in_sig[47] | roundMask_shift[15], + io_in_sig[46] | roundMask_shift[16], + io_in_sig[45] | roundMask_shift[17], + io_in_sig[44] | _common_underflow_T_4} + 13'h1 + & ~(roundingMode_near_even & (|_roundPosBit_T) & ~(|_anyRoundExtra_T) + ? {roundMask_shift[7], + roundMask_shift[8], + roundMask_shift[9], + roundMask_shift[10], + roundMask_shift[11], + roundMask_shift[12], + roundMask_shift[13], + roundMask_shift[14], + roundMask_shift[15], + roundMask_shift[16], + roundMask_shift[17], + _common_underflow_T_4, + 1'h1} + : 13'h0) + : {1'h0, + io_in_sig[55:44] + & {~(roundMask_shift[7]), + ~(roundMask_shift[8]), + ~(roundMask_shift[9]), + ~_GEN, + ~(roundMask_shift[12]), + ~(roundMask_shift[13]), + ~(roundMask_shift[14]), + ~(roundMask_shift[15]), + ~(roundMask_shift[16]), + ~(roundMask_shift[17]), + ~_common_underflow_T_4}} + | (roundingMode_odd & anyRound ? _GEN_0 & _GEN_1 : 13'h0); + wire [14:0] sRoundedExp = {sAdjustedExp[13], sAdjustedExp} + {13'h0, roundedSig[12:11]}; + wire common_totalUnderflow = $signed(sRoundedExp) < 15'sh8; + wire isNaNOut = io_invalidExc | io_in_isNaN; + wire commonCase = ~isNaNOut & ~io_in_isInf & ~io_in_isZero; + wire overflow = commonCase & $signed(sRoundedExp[14:4]) > 11'sh2; + wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp; + wire pegMinNonzeroMagOut = + commonCase & common_totalUnderflow & (roundMagUp | roundingMode_odd); + wire pegMaxFiniteMagOut = overflow & ~overflow_roundMagUp; + wire notNaN_isInfOut = io_in_isInf | overflow & overflow_roundMagUp; + assign io_out = + {~isNaNOut & io_in_sign, + sRoundedExp[5:0] & ~(io_in_isZero | common_totalUnderflow ? 6'h38 : 6'h0) + & ~(pegMinNonzeroMagOut ? 6'h37 : 6'h0) & {1'h1, ~pegMaxFiniteMagOut, 4'hF} + & {2'h3, ~notNaN_isInfOut, 3'h7} | {2'h0, pegMinNonzeroMagOut, 3'h0} + | (pegMaxFiniteMagOut ? 6'h2F : 6'h0) | (notNaN_isInfOut ? 6'h30 : 6'h0) + | (isNaNOut ? 6'h38 : 6'h0), + (isNaNOut | io_in_isZero | common_totalUnderflow + ? {isNaNOut, 9'h0} + : io_in_sig[55] ? roundedSig[10:1] : roundedSig[9:0]) | {10{pegMaxFiniteMagOut}}}; + assign io_exceptionFlags = + {io_invalidExc, + 1'h0, + overflow, + commonCase + & (common_totalUnderflow | anyRound & $signed(sAdjustedExp[13:5]) < 9'sh1 + & (io_in_sig[55] ? roundMask_shift[17] : _common_underflow_T_4) + & ~(~(io_in_sig[55] ? roundMask_shift[16] : roundMask_shift[17]) + & (io_in_sig[55] ? roundedSig[12] : roundedSig[11]) & (|_roundPosBit_T) + & (_overflow_roundMagUp_T & (io_in_sig[55] ? io_in_sig[44] : io_in_sig[43]) + | roundMagUp + & (io_in_sig[55] & io_in_sig[44] + | (|{io_in_sig[43], |(io_in_sig[42:0])}))))), + overflow | commonCase & (common_totalUnderflow | anyRound)}; +endmodule + +module RoundAnyRawFNToRecFN_ie11_is55_oe8_os24( + input io_invalidExc, + io_in_isNaN, + io_in_isInf, + io_in_isZero, + io_in_sign, + input [12:0] io_in_sExp, + input [55:0] io_in_sig, + input [2:0] io_roundingMode, + output [32:0] io_out, + output [4:0] io_exceptionFlags +); + + wire roundingMode_near_even = io_roundingMode == 3'h0; + wire roundingMode_odd = io_roundingMode == 3'h6; + wire roundMagUp = + io_roundingMode == 3'h2 & io_in_sign | io_roundingMode == 3'h3 & ~io_in_sign; + wire [13:0] sAdjustedExp = {io_in_sExp[12], io_in_sExp} - 14'h700; + wire [8:0] _roundMask_T_1 = ~(sAdjustedExp[8:0]); + wire [64:0] _GEN = {59'h0, _roundMask_T_1[5:0]}; + wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> _GEN); + wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> _GEN); + wire [24:0] _roundMask_T_73 = + _roundMask_T_1[8] + ? (_roundMask_T_1[7] + ? {~(_roundMask_T_1[6] + ? 22'h0 + : ~{roundMask_shift[42], + roundMask_shift[43], + roundMask_shift[44], + roundMask_shift[45], + roundMask_shift[46], + {{roundMask_shift[47:46], roundMask_shift[49]} & 3'h5, 1'h0} + | {roundMask_shift[49:48], roundMask_shift[51:50]} & 4'h5, + roundMask_shift[51], + roundMask_shift[52], + roundMask_shift[53], + roundMask_shift[54], + roundMask_shift[55], + roundMask_shift[56], + roundMask_shift[57], + roundMask_shift[58], + roundMask_shift[59], + roundMask_shift[60], + roundMask_shift[61], + roundMask_shift[62], + roundMask_shift[63]}), + 3'h7} + : {22'h0, + _roundMask_T_1[6] + ? {roundMask_shift_1[0], roundMask_shift_1[1], roundMask_shift_1[2]} + : 3'h0}) + : 25'h0; + wire _common_underflow_T_4 = _roundMask_T_73[0] | io_in_sig[55]; + wire [25:0] _GEN_0 = {1'h1, ~(_roundMask_T_73[24:1]), ~_common_underflow_T_4}; + wire [25:0] _GEN_1 = {_roundMask_T_73[24:1], _common_underflow_T_4, 1'h1}; + wire [25:0] _roundPosBit_T = io_in_sig[55:30] & _GEN_0 & _GEN_1; + wire [25:0] _anyRoundExtra_T = {io_in_sig[54:30], |(io_in_sig[29:0])} & _GEN_1; + wire anyRound = (|_roundPosBit_T) | (|_anyRoundExtra_T); + wire _overflow_roundMagUp_T = roundingMode_near_even | io_roundingMode == 3'h4; + wire [25:0] roundedSig = + _overflow_roundMagUp_T & (|_roundPosBit_T) | roundMagUp & anyRound + ? {1'h0, + io_in_sig[55:32] | _roundMask_T_73[24:1], + io_in_sig[31] | _common_underflow_T_4} + 26'h1 + & ~(roundingMode_near_even & (|_roundPosBit_T) & ~(|_anyRoundExtra_T) + ? {_roundMask_T_73[24:1], _common_underflow_T_4, 1'h1} + : 26'h0) + : {1'h0, io_in_sig[55:31] & {~(_roundMask_T_73[24:1]), ~_common_underflow_T_4}} + | (roundingMode_odd & anyRound ? _GEN_0 & _GEN_1 : 26'h0); + wire [14:0] sRoundedExp = {sAdjustedExp[13], sAdjustedExp} + {13'h0, roundedSig[25:24]}; + wire common_totalUnderflow = $signed(sRoundedExp) < 15'sh6B; + wire isNaNOut = io_invalidExc | io_in_isNaN; + wire commonCase = ~isNaNOut & ~io_in_isInf & ~io_in_isZero; + wire overflow = commonCase & $signed(sRoundedExp[14:7]) > 8'sh2; + wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp; + wire pegMinNonzeroMagOut = + commonCase & common_totalUnderflow & (roundMagUp | roundingMode_odd); + wire pegMaxFiniteMagOut = overflow & ~overflow_roundMagUp; + wire notNaN_isInfOut = io_in_isInf | overflow & overflow_roundMagUp; + assign io_out = + {~isNaNOut & io_in_sign, + sRoundedExp[8:0] & ~(io_in_isZero | common_totalUnderflow ? 9'h1C0 : 9'h0) + & ~(pegMinNonzeroMagOut ? 9'h194 : 9'h0) & {1'h1, ~pegMaxFiniteMagOut, 7'h7F} + & {2'h3, ~notNaN_isInfOut, 6'h3F} | (pegMinNonzeroMagOut ? 9'h6B : 9'h0) + | (pegMaxFiniteMagOut ? 9'h17F : 9'h0) | (notNaN_isInfOut ? 9'h180 : 9'h0) + | (isNaNOut ? 9'h1C0 : 9'h0), + (isNaNOut | io_in_isZero | common_totalUnderflow + ? {isNaNOut, 22'h0} + : io_in_sig[55] ? roundedSig[23:1] : roundedSig[22:0]) + | {23{pegMaxFiniteMagOut}}}; + assign io_exceptionFlags = + {io_invalidExc, + 1'h0, + overflow, + commonCase + & (common_totalUnderflow | anyRound & $signed(sAdjustedExp[13:8]) < 6'sh1 + & (io_in_sig[55] ? _roundMask_T_73[1] : _common_underflow_T_4) + & ~(~(io_in_sig[55] ? _roundMask_T_73[2] : _roundMask_T_73[1]) + & (io_in_sig[55] ? roundedSig[25] : roundedSig[24]) & (|_roundPosBit_T) + & (_overflow_roundMagUp_T & (io_in_sig[55] ? io_in_sig[31] : io_in_sig[30]) + | roundMagUp + & (io_in_sig[55] & io_in_sig[31] + | (|{io_in_sig[30], |(io_in_sig[29:0])}))))), + overflow | commonCase & (common_totalUnderflow | anyRound)}; +endmodule + +module SharedMulAddRecFNPipe( + input clock, + reset, + io_validin, + input [1:0] io_op, + io_typeTag, + input [64:0] io_a, + io_b, + io_c, + input [2:0] io_roundingMode, + output [64:0] io_out_data, + output [4:0] io_out_exc, + output io_validout +); + + wire [64:0] _results_round_2_io_out; + wire [4:0] _results_round_2_io_exceptionFlags; + wire [32:0] _results_round_1_io_out; + wire [4:0] _results_round_1_io_exceptionFlags; + wire [16:0] _results_round_io_out; + wire [4:0] _results_round_io_exceptionFlags; + wire _post_io_invalidExc; + wire _post_io_rawOut_isNaN; + wire _post_io_rawOut_isInf; + wire _post_io_rawOut_isZero; + wire _post_io_rawOut_sign; + wire [12:0] _post_io_rawOut_sExp; + wire [55:0] _post_io_rawOut_sig; + wire [52:0] _pre_io_mulAddA; + wire [52:0] _pre_io_mulAddB; + wire [105:0] _pre_io_mulAddC; + wire _pre_io_toPostMul_isSigNaNAny; + wire _pre_io_toPostMul_isNaNAOrB; + wire _pre_io_toPostMul_isInfA; + wire _pre_io_toPostMul_isZeroA; + wire _pre_io_toPostMul_isInfB; + wire _pre_io_toPostMul_isZeroB; + wire _pre_io_toPostMul_signProd; + wire _pre_io_toPostMul_isNaNC; + wire _pre_io_toPostMul_isInfC; + wire _pre_io_toPostMul_isZeroC; + wire [12:0] _pre_io_toPostMul_sExpSum; + wire _pre_io_toPostMul_doSubMags; + wire _pre_io_toPostMul_CIsDominant; + wire [5:0] _pre_io_toPostMul_CDom_CAlignDist; + wire [54:0] _pre_io_toPostMul_highAlignedSigC; + wire _pre_io_toPostMul_bit0AlignedSigC; + reg [52:0] mulA_pipe_b; + reg [52:0] mulB_pipe_b; + reg [105:0] alignedC_pipe_b; + reg meta_pipe_v; + reg meta_pipe_b_isSigNaNAny; + reg meta_pipe_b_isNaNAOrB; + reg meta_pipe_b_isInfA; + reg meta_pipe_b_isZeroA; + reg meta_pipe_b_isInfB; + reg meta_pipe_b_isZeroB; + reg meta_pipe_b_signProd; + reg meta_pipe_b_isNaNC; + reg meta_pipe_b_isInfC; + reg meta_pipe_b_isZeroC; + reg [12:0] meta_pipe_b_sExpSum; + reg meta_pipe_b_doSubMags; + reg meta_pipe_b_CIsDominant; + reg [5:0] meta_pipe_b_CDom_CAlignDist; + reg [54:0] meta_pipe_b_highAlignedSigC; + reg meta_pipe_b_bit0AlignedSigC; + reg [105:0] product_pipe_b; + reg [105:0] delayedC_pipe_b; + reg delayedMeta_pipe_v; + reg delayedMeta_pipe_b_isSigNaNAny; + reg delayedMeta_pipe_b_isNaNAOrB; + reg delayedMeta_pipe_b_isInfA; + reg delayedMeta_pipe_b_isZeroA; + reg delayedMeta_pipe_b_isInfB; + reg delayedMeta_pipe_b_isZeroB; + reg delayedMeta_pipe_b_signProd; + reg delayedMeta_pipe_b_isNaNC; + reg delayedMeta_pipe_b_isInfC; + reg delayedMeta_pipe_b_isZeroC; + reg [12:0] delayedMeta_pipe_b_sExpSum; + reg delayedMeta_pipe_b_doSubMags; + reg delayedMeta_pipe_b_CIsDominant; + reg [5:0] delayedMeta_pipe_b_CDom_CAlignDist; + reg [54:0] delayedMeta_pipe_b_highAlignedSigC; + reg delayedMeta_pipe_b_bit0AlignedSigC; + reg post_io_fromPreMul_pipe_b_isSigNaNAny; + reg post_io_fromPreMul_pipe_b_isNaNAOrB; + reg post_io_fromPreMul_pipe_b_isInfA; + reg post_io_fromPreMul_pipe_b_isZeroA; + reg post_io_fromPreMul_pipe_b_isInfB; + reg post_io_fromPreMul_pipe_b_isZeroB; + reg post_io_fromPreMul_pipe_b_signProd; + reg post_io_fromPreMul_pipe_b_isNaNC; + reg post_io_fromPreMul_pipe_b_isInfC; + reg post_io_fromPreMul_pipe_b_isZeroC; + reg [12:0] post_io_fromPreMul_pipe_b_sExpSum; + reg post_io_fromPreMul_pipe_b_doSubMags; + reg post_io_fromPreMul_pipe_b_CIsDominant; + reg [5:0] post_io_fromPreMul_pipe_b_CDom_CAlignDist; + reg [54:0] post_io_fromPreMul_pipe_b_highAlignedSigC; + reg post_io_fromPreMul_pipe_b_bit0AlignedSigC; + reg [106:0] post_io_mulAddResult_pipe_b; + reg rmPost_pipe_v; + reg [2:0] rmPost_pipe_b; + reg rmPost_pipe_pipe_v; + reg [2:0] rmPost_pipe_pipe_b; + reg rmPost_pipe_pipe_pipe_v; + reg [2:0] rmPost_pipe_pipe_pipe_b; + reg raw_pipe_b_isNaN; + reg raw_pipe_b_isInf; + reg raw_pipe_b_isZero; + reg raw_pipe_b_sign; + reg [12:0] raw_pipe_b_sExp; + reg [55:0] raw_pipe_b_sig; + reg invalid_pipe_b; + reg rm_pipe_v; + reg [2:0] rm_pipe_b; + reg rm_pipe_pipe_v; + reg [2:0] rm_pipe_pipe_b; + reg rm_pipe_pipe_pipe_v; + reg [2:0] rm_pipe_pipe_pipe_b; + reg [2:0] rm_pipe_pipe_pipe_pipe_b; + reg tag_pipe_v; + reg [1:0] tag_pipe_b; + reg tag_pipe_pipe_v; + reg [1:0] tag_pipe_pipe_b; + reg tag_pipe_pipe_pipe_v; + reg [1:0] tag_pipe_pipe_pipe_b; + reg tag_pipe_pipe_pipe_pipe_v; + reg [1:0] tag_pipe_pipe_pipe_pipe_b; + wire [64:0] results_0_data = {48'h0, _results_round_io_out}; + wire [3:0][64:0] _GEN = + {{results_0_data}, + {({65{_results_round_2_io_out[63:61] != 3'h7}} | 65'h1EFEFFFFFFFFFFFFF) + & _results_round_2_io_out}, + {{32'h0, + ({33{_results_round_1_io_out[31:29] != 3'h7}} | 33'h1EF7FFFFF) + & _results_round_1_io_out}}, + {results_0_data}}; + wire [3:0][4:0] _GEN_0 = + {{_results_round_io_exceptionFlags}, + {_results_round_2_io_exceptionFlags}, + {_results_round_1_io_exceptionFlags}, + {_results_round_io_exceptionFlags}}; + always @(posedge clock) begin + if (io_validin) begin + mulA_pipe_b <= _pre_io_mulAddA; + mulB_pipe_b <= _pre_io_mulAddB; + alignedC_pipe_b <= _pre_io_mulAddC; + meta_pipe_b_isSigNaNAny <= _pre_io_toPostMul_isSigNaNAny; + meta_pipe_b_isNaNAOrB <= _pre_io_toPostMul_isNaNAOrB; + meta_pipe_b_isInfA <= _pre_io_toPostMul_isInfA; + meta_pipe_b_isZeroA <= _pre_io_toPostMul_isZeroA; + meta_pipe_b_isInfB <= _pre_io_toPostMul_isInfB; + meta_pipe_b_isZeroB <= _pre_io_toPostMul_isZeroB; + meta_pipe_b_signProd <= _pre_io_toPostMul_signProd; + meta_pipe_b_isNaNC <= _pre_io_toPostMul_isNaNC; + meta_pipe_b_isInfC <= _pre_io_toPostMul_isInfC; + meta_pipe_b_isZeroC <= _pre_io_toPostMul_isZeroC; + meta_pipe_b_sExpSum <= _pre_io_toPostMul_sExpSum; + meta_pipe_b_doSubMags <= _pre_io_toPostMul_doSubMags; + meta_pipe_b_CIsDominant <= _pre_io_toPostMul_CIsDominant; + meta_pipe_b_CDom_CAlignDist <= _pre_io_toPostMul_CDom_CAlignDist; + meta_pipe_b_highAlignedSigC <= _pre_io_toPostMul_highAlignedSigC; + meta_pipe_b_bit0AlignedSigC <= _pre_io_toPostMul_bit0AlignedSigC; + rmPost_pipe_b <= io_roundingMode; + rm_pipe_b <= io_roundingMode; + tag_pipe_b <= io_typeTag; + end + if (meta_pipe_v) begin + product_pipe_b <= {53'h0, mulA_pipe_b} * {53'h0, mulB_pipe_b}; + delayedC_pipe_b <= alignedC_pipe_b; + delayedMeta_pipe_b_isSigNaNAny <= meta_pipe_b_isSigNaNAny; + delayedMeta_pipe_b_isNaNAOrB <= meta_pipe_b_isNaNAOrB; + delayedMeta_pipe_b_isInfA <= meta_pipe_b_isInfA; + delayedMeta_pipe_b_isZeroA <= meta_pipe_b_isZeroA; + delayedMeta_pipe_b_isInfB <= meta_pipe_b_isInfB; + delayedMeta_pipe_b_isZeroB <= meta_pipe_b_isZeroB; + delayedMeta_pipe_b_signProd <= meta_pipe_b_signProd; + delayedMeta_pipe_b_isNaNC <= meta_pipe_b_isNaNC; + delayedMeta_pipe_b_isInfC <= meta_pipe_b_isInfC; + delayedMeta_pipe_b_isZeroC <= meta_pipe_b_isZeroC; + delayedMeta_pipe_b_sExpSum <= meta_pipe_b_sExpSum; + delayedMeta_pipe_b_doSubMags <= meta_pipe_b_doSubMags; + delayedMeta_pipe_b_CIsDominant <= meta_pipe_b_CIsDominant; + delayedMeta_pipe_b_CDom_CAlignDist <= meta_pipe_b_CDom_CAlignDist; + delayedMeta_pipe_b_highAlignedSigC <= meta_pipe_b_highAlignedSigC; + delayedMeta_pipe_b_bit0AlignedSigC <= meta_pipe_b_bit0AlignedSigC; + end + if (delayedMeta_pipe_v) begin + post_io_fromPreMul_pipe_b_isSigNaNAny <= delayedMeta_pipe_b_isSigNaNAny; + post_io_fromPreMul_pipe_b_isNaNAOrB <= delayedMeta_pipe_b_isNaNAOrB; + post_io_fromPreMul_pipe_b_isInfA <= delayedMeta_pipe_b_isInfA; + post_io_fromPreMul_pipe_b_isZeroA <= delayedMeta_pipe_b_isZeroA; + post_io_fromPreMul_pipe_b_isInfB <= delayedMeta_pipe_b_isInfB; + post_io_fromPreMul_pipe_b_isZeroB <= delayedMeta_pipe_b_isZeroB; + post_io_fromPreMul_pipe_b_signProd <= delayedMeta_pipe_b_signProd; + post_io_fromPreMul_pipe_b_isNaNC <= delayedMeta_pipe_b_isNaNC; + post_io_fromPreMul_pipe_b_isInfC <= delayedMeta_pipe_b_isInfC; + post_io_fromPreMul_pipe_b_isZeroC <= delayedMeta_pipe_b_isZeroC; + post_io_fromPreMul_pipe_b_sExpSum <= delayedMeta_pipe_b_sExpSum; + post_io_fromPreMul_pipe_b_doSubMags <= delayedMeta_pipe_b_doSubMags; + post_io_fromPreMul_pipe_b_CIsDominant <= delayedMeta_pipe_b_CIsDominant; + post_io_fromPreMul_pipe_b_CDom_CAlignDist <= delayedMeta_pipe_b_CDom_CAlignDist; + post_io_fromPreMul_pipe_b_highAlignedSigC <= delayedMeta_pipe_b_highAlignedSigC; + post_io_fromPreMul_pipe_b_bit0AlignedSigC <= delayedMeta_pipe_b_bit0AlignedSigC; + post_io_mulAddResult_pipe_b <= {1'h0, product_pipe_b} + {1'h0, delayedC_pipe_b}; + end + if (rmPost_pipe_v) + rmPost_pipe_pipe_b <= rmPost_pipe_b; + if (rmPost_pipe_pipe_v) + rmPost_pipe_pipe_pipe_b <= rmPost_pipe_pipe_b; + if (rmPost_pipe_pipe_pipe_v) begin + raw_pipe_b_isNaN <= _post_io_rawOut_isNaN; + raw_pipe_b_isInf <= _post_io_rawOut_isInf; + raw_pipe_b_isZero <= _post_io_rawOut_isZero; + raw_pipe_b_sign <= _post_io_rawOut_sign; + raw_pipe_b_sExp <= _post_io_rawOut_sExp; + raw_pipe_b_sig <= _post_io_rawOut_sig; + invalid_pipe_b <= _post_io_invalidExc; + end + if (rm_pipe_v) + rm_pipe_pipe_b <= rm_pipe_b; + if (rm_pipe_pipe_v) + rm_pipe_pipe_pipe_b <= rm_pipe_pipe_b; + if (rm_pipe_pipe_pipe_v) + rm_pipe_pipe_pipe_pipe_b <= rm_pipe_pipe_pipe_b; + if (tag_pipe_v) + tag_pipe_pipe_b <= tag_pipe_b; + if (tag_pipe_pipe_v) + tag_pipe_pipe_pipe_b <= tag_pipe_pipe_b; + if (tag_pipe_pipe_pipe_v) + tag_pipe_pipe_pipe_pipe_b <= tag_pipe_pipe_pipe_b; + if (reset) begin + meta_pipe_v <= 1'h0; + delayedMeta_pipe_v <= 1'h0; + rmPost_pipe_v <= 1'h0; + rmPost_pipe_pipe_v <= 1'h0; + rmPost_pipe_pipe_pipe_v <= 1'h0; + rm_pipe_v <= 1'h0; + rm_pipe_pipe_v <= 1'h0; + rm_pipe_pipe_pipe_v <= 1'h0; + tag_pipe_v <= 1'h0; + tag_pipe_pipe_v <= 1'h0; + tag_pipe_pipe_pipe_v <= 1'h0; + tag_pipe_pipe_pipe_pipe_v <= 1'h0; + end + else begin + meta_pipe_v <= io_validin; + delayedMeta_pipe_v <= meta_pipe_v; + rmPost_pipe_v <= io_validin; + rmPost_pipe_pipe_v <= rmPost_pipe_v; + rmPost_pipe_pipe_pipe_v <= rmPost_pipe_pipe_v; + rm_pipe_v <= io_validin; + rm_pipe_pipe_v <= rm_pipe_v; + rm_pipe_pipe_pipe_v <= rm_pipe_pipe_v; + tag_pipe_v <= io_validin; + tag_pipe_pipe_v <= tag_pipe_v; + tag_pipe_pipe_pipe_v <= tag_pipe_pipe_v; + tag_pipe_pipe_pipe_pipe_v <= tag_pipe_pipe_pipe_v; + end + end // always @(posedge) + MulAddRecFNToRaw_preMul_e11_s53 pre ( + .io_op (io_op), + .io_a (io_a), + .io_b (io_b), + .io_c (io_c), + .io_mulAddA (_pre_io_mulAddA), + .io_mulAddB (_pre_io_mulAddB), + .io_mulAddC (_pre_io_mulAddC), + .io_toPostMul_isSigNaNAny (_pre_io_toPostMul_isSigNaNAny), + .io_toPostMul_isNaNAOrB (_pre_io_toPostMul_isNaNAOrB), + .io_toPostMul_isInfA (_pre_io_toPostMul_isInfA), + .io_toPostMul_isZeroA (_pre_io_toPostMul_isZeroA), + .io_toPostMul_isInfB (_pre_io_toPostMul_isInfB), + .io_toPostMul_isZeroB (_pre_io_toPostMul_isZeroB), + .io_toPostMul_signProd (_pre_io_toPostMul_signProd), + .io_toPostMul_isNaNC (_pre_io_toPostMul_isNaNC), + .io_toPostMul_isInfC (_pre_io_toPostMul_isInfC), + .io_toPostMul_isZeroC (_pre_io_toPostMul_isZeroC), + .io_toPostMul_sExpSum (_pre_io_toPostMul_sExpSum), + .io_toPostMul_doSubMags (_pre_io_toPostMul_doSubMags), + .io_toPostMul_CIsDominant (_pre_io_toPostMul_CIsDominant), + .io_toPostMul_CDom_CAlignDist (_pre_io_toPostMul_CDom_CAlignDist), + .io_toPostMul_highAlignedSigC (_pre_io_toPostMul_highAlignedSigC), + .io_toPostMul_bit0AlignedSigC (_pre_io_toPostMul_bit0AlignedSigC) + ); + MulAddRecFNToRaw_postMul_e11_s53 post ( + .io_fromPreMul_isSigNaNAny (post_io_fromPreMul_pipe_b_isSigNaNAny), + .io_fromPreMul_isNaNAOrB (post_io_fromPreMul_pipe_b_isNaNAOrB), + .io_fromPreMul_isInfA (post_io_fromPreMul_pipe_b_isInfA), + .io_fromPreMul_isZeroA (post_io_fromPreMul_pipe_b_isZeroA), + .io_fromPreMul_isInfB (post_io_fromPreMul_pipe_b_isInfB), + .io_fromPreMul_isZeroB (post_io_fromPreMul_pipe_b_isZeroB), + .io_fromPreMul_signProd (post_io_fromPreMul_pipe_b_signProd), + .io_fromPreMul_isNaNC (post_io_fromPreMul_pipe_b_isNaNC), + .io_fromPreMul_isInfC (post_io_fromPreMul_pipe_b_isInfC), + .io_fromPreMul_isZeroC (post_io_fromPreMul_pipe_b_isZeroC), + .io_fromPreMul_sExpSum (post_io_fromPreMul_pipe_b_sExpSum), + .io_fromPreMul_doSubMags (post_io_fromPreMul_pipe_b_doSubMags), + .io_fromPreMul_CIsDominant (post_io_fromPreMul_pipe_b_CIsDominant), + .io_fromPreMul_CDom_CAlignDist (post_io_fromPreMul_pipe_b_CDom_CAlignDist), + .io_fromPreMul_highAlignedSigC (post_io_fromPreMul_pipe_b_highAlignedSigC), + .io_fromPreMul_bit0AlignedSigC (post_io_fromPreMul_pipe_b_bit0AlignedSigC), + .io_mulAddResult (post_io_mulAddResult_pipe_b), + .io_roundingMode (rmPost_pipe_pipe_pipe_b), + .io_invalidExc (_post_io_invalidExc), + .io_rawOut_isNaN (_post_io_rawOut_isNaN), + .io_rawOut_isInf (_post_io_rawOut_isInf), + .io_rawOut_isZero (_post_io_rawOut_isZero), + .io_rawOut_sign (_post_io_rawOut_sign), + .io_rawOut_sExp (_post_io_rawOut_sExp), + .io_rawOut_sig (_post_io_rawOut_sig) + ); + RoundAnyRawFNToRecFN_ie11_is55_oe5_os11 results_round ( + .io_invalidExc (invalid_pipe_b), + .io_in_isNaN (raw_pipe_b_isNaN), + .io_in_isInf (raw_pipe_b_isInf), + .io_in_isZero (raw_pipe_b_isZero), + .io_in_sign (raw_pipe_b_sign), + .io_in_sExp (raw_pipe_b_sExp), + .io_in_sig (raw_pipe_b_sig), + .io_roundingMode (rm_pipe_pipe_pipe_pipe_b), + .io_out (_results_round_io_out), + .io_exceptionFlags (_results_round_io_exceptionFlags) + ); + RoundAnyRawFNToRecFN_ie11_is55_oe8_os24 results_round_1 ( + .io_invalidExc (invalid_pipe_b), + .io_in_isNaN (raw_pipe_b_isNaN), + .io_in_isInf (raw_pipe_b_isInf), + .io_in_isZero (raw_pipe_b_isZero), + .io_in_sign (raw_pipe_b_sign), + .io_in_sExp (raw_pipe_b_sExp), + .io_in_sig (raw_pipe_b_sig), + .io_roundingMode (rm_pipe_pipe_pipe_pipe_b), + .io_out (_results_round_1_io_out), + .io_exceptionFlags (_results_round_1_io_exceptionFlags) + ); + RoundAnyRawFNToRecFN_ie11_is55_oe11_os53 results_round_2 ( + .io_invalidExc (invalid_pipe_b), + .io_in_isNaN (raw_pipe_b_isNaN), + .io_in_isInf (raw_pipe_b_isInf), + .io_in_isZero (raw_pipe_b_isZero), + .io_in_sign (raw_pipe_b_sign), + .io_in_sExp (raw_pipe_b_sExp), + .io_in_sig (raw_pipe_b_sig), + .io_roundingMode (rm_pipe_pipe_pipe_pipe_b), + .io_out (_results_round_2_io_out), + .io_exceptionFlags (_results_round_2_io_exceptionFlags) + ); + assign io_out_data = _GEN[tag_pipe_pipe_pipe_pipe_b]; + assign io_out_exc = _GEN_0[tag_pipe_pipe_pipe_pipe_b]; + assign io_validout = tag_pipe_pipe_pipe_pipe_v; +endmodule + +module FPUSharedFMAPipe( + input clock, + reset, + io_in_valid, + io_in_bits_ren3, + io_in_bits_swap23, + input [1:0] io_in_bits_typeTagOut, + input [2:0] io_in_bits_rm, + input [1:0] io_in_bits_fmaCmd, + input [64:0] io_in_bits_in1, + io_in_bits_in2, + io_in_bits_in3, + output io_out_valid, + output [64:0] io_out_bits_data, + output [4:0] io_out_bits_exc +); + + wire [64:0] _fma_io_out_data; + wire [4:0] _fma_io_out_exc; + wire _fma_io_validout; + reg valid; + reg [1:0] in_typeTagOut; + reg [2:0] in_rm; + reg [1:0] in_fmaCmd; + reg [64:0] in_in1; + reg [64:0] in_in2; + reg [64:0] in_in3; + reg io_out_pipe_v; + reg [64:0] io_out_pipe_b_data; + reg [4:0] io_out_pipe_b_exc; + always @(posedge clock) begin + if (reset) begin + valid <= 1'h0; + io_out_pipe_v <= 1'h0; + end + else begin + valid <= io_in_valid; + io_out_pipe_v <= _fma_io_validout; + end + if (io_in_valid) begin + automatic logic [11:0] _a_expOut_commonCase_T_2 = + {6'h0, io_in_bits_in1[15:10]} + 12'h7E0; + automatic logic [64:0] _a_T_1 = + {io_in_bits_in1[16], + io_in_bits_in1[15:13] == 3'h0 | io_in_bits_in1[15:13] > 3'h5 + ? {io_in_bits_in1[15:13], _a_expOut_commonCase_T_2[8:0]} + : _a_expOut_commonCase_T_2, + io_in_bits_in1[9:0], + 42'h0}; + automatic logic [11:0] _a_expOut_commonCase_T_5 = + {3'h0, io_in_bits_in1[31:23]} + 12'h700; + automatic logic [11:0] _b_expOut_commonCase_T_2 = + {6'h0, io_in_bits_in2[15:10]} + 12'h7E0; + automatic logic [64:0] _b_T_1 = + {io_in_bits_in2[16], + io_in_bits_in2[15:13] == 3'h0 | io_in_bits_in2[15:13] > 3'h5 + ? {io_in_bits_in2[15:13], _b_expOut_commonCase_T_2[8:0]} + : _b_expOut_commonCase_T_2, + io_in_bits_in2[9:0], + 42'h0}; + automatic logic [11:0] _b_expOut_commonCase_T_5 = + {3'h0, io_in_bits_in2[31:23]} + 12'h700; + automatic logic [11:0] _c_expOut_commonCase_T_2 = + {6'h0, io_in_bits_in3[15:10]} + 12'h7E0; + automatic logic [64:0] _c_T_1 = + {io_in_bits_in3[16], + io_in_bits_in3[15:13] == 3'h0 | io_in_bits_in3[15:13] > 3'h5 + ? {io_in_bits_in3[15:13], _c_expOut_commonCase_T_2[8:0]} + : _c_expOut_commonCase_T_2, + io_in_bits_in3[9:0], + 42'h0}; + automatic logic [11:0] _c_expOut_commonCase_T_5 = + {3'h0, io_in_bits_in3[31:23]} + 12'h700; + automatic logic [3:0][64:0] _GEN = + {{_a_T_1}, + {io_in_bits_in1}, + {{io_in_bits_in1[32], + io_in_bits_in1[31:29] == 3'h0 | io_in_bits_in1[31:29] > 3'h5 + ? {io_in_bits_in1[31:29], _a_expOut_commonCase_T_5[8:0]} + : _a_expOut_commonCase_T_5, + io_in_bits_in1[22:0], + 29'h0}}, + {_a_T_1}}; + automatic logic [3:0][64:0] _GEN_0 = + {{_b_T_1}, + {io_in_bits_in2}, + {{io_in_bits_in2[32], + io_in_bits_in2[31:29] == 3'h0 | io_in_bits_in2[31:29] > 3'h5 + ? {io_in_bits_in2[31:29], _b_expOut_commonCase_T_5[8:0]} + : _b_expOut_commonCase_T_5, + io_in_bits_in2[22:0], + 29'h0}}, + {_b_T_1}}; + automatic logic [3:0][64:0] _GEN_1 = + {{_c_T_1}, + {io_in_bits_in3}, + {{io_in_bits_in3[32], + io_in_bits_in3[31:29] == 3'h0 | io_in_bits_in3[31:29] > 3'h5 + ? {io_in_bits_in3[31:29], _c_expOut_commonCase_T_5[8:0]} + : _c_expOut_commonCase_T_5, + io_in_bits_in3[22:0], + 29'h0}}, + {_c_T_1}}; + in_typeTagOut <= io_in_bits_typeTagOut; + in_rm <= io_in_bits_rm; + in_fmaCmd <= io_in_bits_fmaCmd; + in_in1 <= _GEN[io_in_bits_typeTagOut]; + in_in2 <= io_in_bits_swap23 ? 65'h8000000000000000 : _GEN_0[io_in_bits_typeTagOut]; + in_in3 <= + io_in_bits_ren3 | io_in_bits_swap23 + ? _GEN_1[io_in_bits_typeTagOut] + : (_GEN[io_in_bits_typeTagOut] ^ _GEN_0[io_in_bits_typeTagOut]) + & 65'h10000000000000000; + end + if (_fma_io_validout) begin + io_out_pipe_b_data <= _fma_io_out_data; + io_out_pipe_b_exc <= _fma_io_out_exc; + end + end // always @(posedge) + SharedMulAddRecFNPipe fma ( + .clock (clock), + .reset (reset), + .io_validin (valid), + .io_op (in_fmaCmd), + .io_typeTag (in_typeTagOut), + .io_a (in_in1), + .io_b (in_in2), + .io_c (in_in3), + .io_roundingMode (in_rm), + .io_out_data (_fma_io_out_data), + .io_out_exc (_fma_io_out_exc), + .io_validout (_fma_io_validout) + ); + assign io_out_valid = io_out_pipe_v; + assign io_out_bits_data = io_out_pipe_b_data; + assign io_out_bits_exc = io_out_pipe_b_exc; +endmodule + +module FmaPrecisionCheck( + input clock, + reset, + valid, + input [1:0] tag, + kind, + op, + input [2:0] rm, + input [63:0] a, + b, + c, + output [63:0] expected, + actual, + output [4:0] expectedFlags, + actualFlags, + output outValid, + equal +); + + wire _shared_io_out_valid; + wire [64:0] _shared_io_out_bits_data; + wire [4:0] _shared_io_out_bits_exc; + wire [64:0] _refs_unit_2_io_out_bits_data; + wire [4:0] _refs_unit_2_io_out_bits_exc; + wire _refs_unit_1_io_out_valid; + wire [64:0] _refs_unit_1_io_out_bits_data; + wire [4:0] _refs_unit_1_io_out_bits_exc; + wire _refs_unit_io_out_valid; + wire [64:0] _refs_unit_io_out_bits_data; + wire [4:0] _refs_unit_io_out_bits_exc; + wire [3:0][1:0] _GEN = '{2'h0, 2'h2, 2'h1, 2'h0}; + wire inputs_2_ren3 = kind == 2'h0; + wire inputs_2_swap23 = kind == 2'h1; + wire inputs_in_in1_rawIn_isZeroExpIn = a[14:10] == 5'h0; + wire [3:0] inputs_in_in1_rawIn_normDist = + a[9] + ? 4'h0 + : a[8] + ? 4'h1 + : a[7] + ? 4'h2 + : a[6] + ? 4'h3 + : a[5] + ? 4'h4 + : a[4] ? 4'h5 : a[3] ? 4'h6 : a[2] ? 4'h7 : {3'h4, ~(a[1])}; + wire [24:0] _inputs_in_in1_rawIn_subnormFract_T = + {15'h0, a[9:0]} << inputs_in_in1_rawIn_normDist; + wire [5:0] _inputs_in_in1_rawIn_adjustedExp_T_4 = + (inputs_in_in1_rawIn_isZeroExpIn + ? {2'h3, ~inputs_in_in1_rawIn_normDist} + : {1'h0, a[14:10]}) + {4'h4, inputs_in_in1_rawIn_isZeroExpIn ? 2'h2 : 2'h1}; + wire [2:0] _inputs_in_in1_T_2 = + inputs_in_in1_rawIn_isZeroExpIn & ~(|(a[9:0])) + ? 3'h0 + : _inputs_in_in1_rawIn_adjustedExp_T_4[5:3]; + wire [64:0] inputs_0_in1 = + {48'h0, + a[15], + _inputs_in_in1_T_2[2:1], + _inputs_in_in1_T_2[0] | (&(_inputs_in_in1_rawIn_adjustedExp_T_4[5:4])) & (|(a[9:0])), + _inputs_in_in1_rawIn_adjustedExp_T_4[2:0], + inputs_in_in1_rawIn_isZeroExpIn + ? {_inputs_in_in1_rawIn_subnormFract_T[8:0], 1'h0} + : a[9:0]}; + wire inputs_in_in2_rawIn_isZeroExpIn = b[14:10] == 5'h0; + wire [3:0] inputs_in_in2_rawIn_normDist = + b[9] + ? 4'h0 + : b[8] + ? 4'h1 + : b[7] + ? 4'h2 + : b[6] + ? 4'h3 + : b[5] + ? 4'h4 + : b[4] ? 4'h5 : b[3] ? 4'h6 : b[2] ? 4'h7 : {3'h4, ~(b[1])}; + wire [24:0] _inputs_in_in2_rawIn_subnormFract_T = + {15'h0, b[9:0]} << inputs_in_in2_rawIn_normDist; + wire [5:0] _inputs_in_in2_rawIn_adjustedExp_T_4 = + (inputs_in_in2_rawIn_isZeroExpIn + ? {2'h3, ~inputs_in_in2_rawIn_normDist} + : {1'h0, b[14:10]}) + {4'h4, inputs_in_in2_rawIn_isZeroExpIn ? 2'h2 : 2'h1}; + wire [2:0] _inputs_in_in2_T_2 = + inputs_in_in2_rawIn_isZeroExpIn & ~(|(b[9:0])) + ? 3'h0 + : _inputs_in_in2_rawIn_adjustedExp_T_4[5:3]; + wire [64:0] inputs_0_in2 = + {48'h0, + b[15], + _inputs_in_in2_T_2[2:1], + _inputs_in_in2_T_2[0] | (&(_inputs_in_in2_rawIn_adjustedExp_T_4[5:4])) & (|(b[9:0])), + _inputs_in_in2_rawIn_adjustedExp_T_4[2:0], + inputs_in_in2_rawIn_isZeroExpIn + ? {_inputs_in_in2_rawIn_subnormFract_T[8:0], 1'h0} + : b[9:0]}; + wire inputs_in_in3_rawIn_isZeroExpIn = c[14:10] == 5'h0; + wire [3:0] inputs_in_in3_rawIn_normDist = + c[9] + ? 4'h0 + : c[8] + ? 4'h1 + : c[7] + ? 4'h2 + : c[6] + ? 4'h3 + : c[5] + ? 4'h4 + : c[4] ? 4'h5 : c[3] ? 4'h6 : c[2] ? 4'h7 : {3'h4, ~(c[1])}; + wire [24:0] _inputs_in_in3_rawIn_subnormFract_T = + {15'h0, c[9:0]} << inputs_in_in3_rawIn_normDist; + wire [5:0] _inputs_in_in3_rawIn_adjustedExp_T_4 = + (inputs_in_in3_rawIn_isZeroExpIn + ? {2'h3, ~inputs_in_in3_rawIn_normDist} + : {1'h0, c[14:10]}) + {4'h4, inputs_in_in3_rawIn_isZeroExpIn ? 2'h2 : 2'h1}; + wire [2:0] _inputs_in_in3_T_2 = + inputs_in_in3_rawIn_isZeroExpIn & ~(|(c[9:0])) + ? 3'h0 + : _inputs_in_in3_rawIn_adjustedExp_T_4[5:3]; + wire [64:0] inputs_0_in3 = + {48'h0, + c[15], + _inputs_in_in3_T_2[2:1], + _inputs_in_in3_T_2[0] | (&(_inputs_in_in3_rawIn_adjustedExp_T_4[5:4])) & (|(c[9:0])), + _inputs_in_in3_rawIn_adjustedExp_T_4[2:0], + inputs_in_in3_rawIn_isZeroExpIn + ? {_inputs_in_in3_rawIn_subnormFract_T[8:0], 1'h0} + : c[9:0]}; + wire inputs_in_in1_rawIn_isZeroExpIn_1 = a[30:23] == 8'h0; + wire [4:0] inputs_in_in1_rawIn_normDist_1 = + a[22] + ? 5'h0 + : a[21] + ? 5'h1 + : a[20] + ? 5'h2 + : a[19] + ? 5'h3 + : a[18] + ? 5'h4 + : a[17] + ? 5'h5 + : a[16] + ? 5'h6 + : a[15] + ? 5'h7 + : a[14] + ? 5'h8 + : a[13] + ? 5'h9 + : a[12] + ? 5'hA + : a[11] + ? 5'hB + : a[10] + ? 5'hC + : a[9] + ? 5'hD + : a[8] + ? 5'hE + : a[7] + ? 5'hF + : a[6] + ? 5'h10 + : a[5] + ? 5'h11 + : a[4] + ? 5'h12 + : a[3] + ? 5'h13 + : a[2] + ? 5'h14 + : a[1] + ? 5'h15 + : 5'h16; + wire [53:0] _inputs_in_in1_rawIn_subnormFract_T_2 = + {31'h0, a[22:0]} << inputs_in_in1_rawIn_normDist_1; + wire [8:0] _inputs_in_in1_rawIn_adjustedExp_T_9 = + (inputs_in_in1_rawIn_isZeroExpIn_1 + ? {4'hF, ~inputs_in_in1_rawIn_normDist_1} + : {1'h0, a[30:23]}) + {7'h20, inputs_in_in1_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1}; + wire [2:0] _inputs_in_in1_T_12 = + inputs_in_in1_rawIn_isZeroExpIn_1 & ~(|(a[22:0])) + ? 3'h0 + : _inputs_in_in1_rawIn_adjustedExp_T_9[8:6]; + wire [64:0] inputs_1_in1 = + {32'h0, + a[31], + _inputs_in_in1_T_12[2:1], + _inputs_in_in1_T_12[0] | (&(_inputs_in_in1_rawIn_adjustedExp_T_9[8:7])) + & (|(a[22:0])), + _inputs_in_in1_rawIn_adjustedExp_T_9[5:0], + inputs_in_in1_rawIn_isZeroExpIn_1 + ? {_inputs_in_in1_rawIn_subnormFract_T_2[21:0], 1'h0} + : a[22:0]}; + wire inputs_in_in2_rawIn_isZeroExpIn_1 = b[30:23] == 8'h0; + wire [4:0] inputs_in_in2_rawIn_normDist_1 = + b[22] + ? 5'h0 + : b[21] + ? 5'h1 + : b[20] + ? 5'h2 + : b[19] + ? 5'h3 + : b[18] + ? 5'h4 + : b[17] + ? 5'h5 + : b[16] + ? 5'h6 + : b[15] + ? 5'h7 + : b[14] + ? 5'h8 + : b[13] + ? 5'h9 + : b[12] + ? 5'hA + : b[11] + ? 5'hB + : b[10] + ? 5'hC + : b[9] + ? 5'hD + : b[8] + ? 5'hE + : b[7] + ? 5'hF + : b[6] + ? 5'h10 + : b[5] + ? 5'h11 + : b[4] + ? 5'h12 + : b[3] + ? 5'h13 + : b[2] + ? 5'h14 + : b[1] + ? 5'h15 + : 5'h16; + wire [53:0] _inputs_in_in2_rawIn_subnormFract_T_2 = + {31'h0, b[22:0]} << inputs_in_in2_rawIn_normDist_1; + wire [8:0] _inputs_in_in2_rawIn_adjustedExp_T_9 = + (inputs_in_in2_rawIn_isZeroExpIn_1 + ? {4'hF, ~inputs_in_in2_rawIn_normDist_1} + : {1'h0, b[30:23]}) + {7'h20, inputs_in_in2_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1}; + wire [2:0] _inputs_in_in2_T_12 = + inputs_in_in2_rawIn_isZeroExpIn_1 & ~(|(b[22:0])) + ? 3'h0 + : _inputs_in_in2_rawIn_adjustedExp_T_9[8:6]; + wire [64:0] inputs_1_in2 = + {32'h0, + b[31], + _inputs_in_in2_T_12[2:1], + _inputs_in_in2_T_12[0] | (&(_inputs_in_in2_rawIn_adjustedExp_T_9[8:7])) + & (|(b[22:0])), + _inputs_in_in2_rawIn_adjustedExp_T_9[5:0], + inputs_in_in2_rawIn_isZeroExpIn_1 + ? {_inputs_in_in2_rawIn_subnormFract_T_2[21:0], 1'h0} + : b[22:0]}; + wire inputs_in_in3_rawIn_isZeroExpIn_1 = c[30:23] == 8'h0; + wire [4:0] inputs_in_in3_rawIn_normDist_1 = + c[22] + ? 5'h0 + : c[21] + ? 5'h1 + : c[20] + ? 5'h2 + : c[19] + ? 5'h3 + : c[18] + ? 5'h4 + : c[17] + ? 5'h5 + : c[16] + ? 5'h6 + : c[15] + ? 5'h7 + : c[14] + ? 5'h8 + : c[13] + ? 5'h9 + : c[12] + ? 5'hA + : c[11] + ? 5'hB + : c[10] + ? 5'hC + : c[9] + ? 5'hD + : c[8] + ? 5'hE + : c[7] + ? 5'hF + : c[6] + ? 5'h10 + : c[5] + ? 5'h11 + : c[4] + ? 5'h12 + : c[3] + ? 5'h13 + : c[2] + ? 5'h14 + : c[1] + ? 5'h15 + : 5'h16; + wire [53:0] _inputs_in_in3_rawIn_subnormFract_T_2 = + {31'h0, c[22:0]} << inputs_in_in3_rawIn_normDist_1; + wire [8:0] _inputs_in_in3_rawIn_adjustedExp_T_9 = + (inputs_in_in3_rawIn_isZeroExpIn_1 + ? {4'hF, ~inputs_in_in3_rawIn_normDist_1} + : {1'h0, c[30:23]}) + {7'h20, inputs_in_in3_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1}; + wire [2:0] _inputs_in_in3_T_12 = + inputs_in_in3_rawIn_isZeroExpIn_1 & ~(|(c[22:0])) + ? 3'h0 + : _inputs_in_in3_rawIn_adjustedExp_T_9[8:6]; + wire [64:0] inputs_1_in3 = + {32'h0, + c[31], + _inputs_in_in3_T_12[2:1], + _inputs_in_in3_T_12[0] | (&(_inputs_in_in3_rawIn_adjustedExp_T_9[8:7])) + & (|(c[22:0])), + _inputs_in_in3_rawIn_adjustedExp_T_9[5:0], + inputs_in_in3_rawIn_isZeroExpIn_1 + ? {_inputs_in_in3_rawIn_subnormFract_T_2[21:0], 1'h0} + : c[22:0]}; + wire inputs_in_in1_rawIn_isZeroExpIn_2 = a[62:52] == 11'h0; + wire [5:0] inputs_in_in1_rawIn_normDist_2 = + a[51] + ? 6'h0 + : a[50] + ? 6'h1 + : a[49] + ? 6'h2 + : a[48] + ? 6'h3 + : a[47] + ? 6'h4 + : a[46] + ? 6'h5 + : a[45] + ? 6'h6 + : a[44] + ? 6'h7 + : a[43] + ? 6'h8 + : a[42] + ? 6'h9 + : a[41] + ? 6'hA + : a[40] + ? 6'hB + : a[39] + ? 6'hC + : a[38] + ? 6'hD + : a[37] + ? 6'hE + : a[36] + ? 6'hF + : a[35] + ? 6'h10 + : a[34] + ? 6'h11 + : a[33] + ? 6'h12 + : a[32] + ? 6'h13 + : a[31] + ? 6'h14 + : a[30] + ? 6'h15 + : a[29] + ? 6'h16 + : a[28] + ? 6'h17 + : a[27] + ? 6'h18 + : a[26] + ? 6'h19 + : a[25] + ? 6'h1A + : a[24] + ? 6'h1B + : a[23] + ? 6'h1C + : a[22] + ? 6'h1D + : a[21] + ? 6'h1E + : a[20] + ? 6'h1F + : a[19] + ? 6'h20 + : a[18] + ? 6'h21 + : a[17] + ? 6'h22 + : a[16] + ? 6'h23 + : a[15] + ? 6'h24 + : a[14] + ? 6'h25 + : a[13] + ? 6'h26 + : a[12] + ? 6'h27 + : a[11] + ? 6'h28 + : a[10] + ? 6'h29 + : a[9] + ? 6'h2A + : a[8] + ? 6'h2B + : a[7] + ? 6'h2C + : a[6] + ? 6'h2D + : a[5] + ? 6'h2E + : a[4] + ? 6'h2F + : a[3] + ? 6'h30 + : a[2] + ? 6'h31 + : {5'h19, + ~(a[1])}; + wire [114:0] _inputs_in_in1_rawIn_subnormFract_T_4 = + {63'h0, a[51:0]} << inputs_in_in1_rawIn_normDist_2; + wire [11:0] _inputs_in_in1_rawIn_adjustedExp_T_14 = + (inputs_in_in1_rawIn_isZeroExpIn_2 + ? {6'h3F, ~inputs_in_in1_rawIn_normDist_2} + : {1'h0, a[62:52]}) + {10'h100, inputs_in_in1_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1}; + wire [2:0] _inputs_in_in1_T_22 = + inputs_in_in1_rawIn_isZeroExpIn_2 & ~(|(a[51:0])) + ? 3'h0 + : _inputs_in_in1_rawIn_adjustedExp_T_14[11:9]; + wire [64:0] inputs_2_in1 = + {a[63], + _inputs_in_in1_T_22[2:1], + _inputs_in_in1_T_22[0] | (&(_inputs_in_in1_rawIn_adjustedExp_T_14[11:10])) + & (|(a[51:0])), + _inputs_in_in1_rawIn_adjustedExp_T_14[8:0], + inputs_in_in1_rawIn_isZeroExpIn_2 + ? {_inputs_in_in1_rawIn_subnormFract_T_4[50:0], 1'h0} + : a[51:0]}; + wire inputs_in_in2_rawIn_isZeroExpIn_2 = b[62:52] == 11'h0; + wire [5:0] inputs_in_in2_rawIn_normDist_2 = + b[51] + ? 6'h0 + : b[50] + ? 6'h1 + : b[49] + ? 6'h2 + : b[48] + ? 6'h3 + : b[47] + ? 6'h4 + : b[46] + ? 6'h5 + : b[45] + ? 6'h6 + : b[44] + ? 6'h7 + : b[43] + ? 6'h8 + : b[42] + ? 6'h9 + : b[41] + ? 6'hA + : b[40] + ? 6'hB + : b[39] + ? 6'hC + : b[38] + ? 6'hD + : b[37] + ? 6'hE + : b[36] + ? 6'hF + : b[35] + ? 6'h10 + : b[34] + ? 6'h11 + : b[33] + ? 6'h12 + : b[32] + ? 6'h13 + : b[31] + ? 6'h14 + : b[30] + ? 6'h15 + : b[29] + ? 6'h16 + : b[28] + ? 6'h17 + : b[27] + ? 6'h18 + : b[26] + ? 6'h19 + : b[25] + ? 6'h1A + : b[24] + ? 6'h1B + : b[23] + ? 6'h1C + : b[22] + ? 6'h1D + : b[21] + ? 6'h1E + : b[20] + ? 6'h1F + : b[19] + ? 6'h20 + : b[18] + ? 6'h21 + : b[17] + ? 6'h22 + : b[16] + ? 6'h23 + : b[15] + ? 6'h24 + : b[14] + ? 6'h25 + : b[13] + ? 6'h26 + : b[12] + ? 6'h27 + : b[11] + ? 6'h28 + : b[10] + ? 6'h29 + : b[9] + ? 6'h2A + : b[8] + ? 6'h2B + : b[7] + ? 6'h2C + : b[6] + ? 6'h2D + : b[5] + ? 6'h2E + : b[4] + ? 6'h2F + : b[3] + ? 6'h30 + : b[2] + ? 6'h31 + : {5'h19, + ~(b[1])}; + wire [114:0] _inputs_in_in2_rawIn_subnormFract_T_4 = + {63'h0, b[51:0]} << inputs_in_in2_rawIn_normDist_2; + wire [11:0] _inputs_in_in2_rawIn_adjustedExp_T_14 = + (inputs_in_in2_rawIn_isZeroExpIn_2 + ? {6'h3F, ~inputs_in_in2_rawIn_normDist_2} + : {1'h0, b[62:52]}) + {10'h100, inputs_in_in2_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1}; + wire [2:0] _inputs_in_in2_T_22 = + inputs_in_in2_rawIn_isZeroExpIn_2 & ~(|(b[51:0])) + ? 3'h0 + : _inputs_in_in2_rawIn_adjustedExp_T_14[11:9]; + wire [64:0] inputs_2_in2 = + {b[63], + _inputs_in_in2_T_22[2:1], + _inputs_in_in2_T_22[0] | (&(_inputs_in_in2_rawIn_adjustedExp_T_14[11:10])) + & (|(b[51:0])), + _inputs_in_in2_rawIn_adjustedExp_T_14[8:0], + inputs_in_in2_rawIn_isZeroExpIn_2 + ? {_inputs_in_in2_rawIn_subnormFract_T_4[50:0], 1'h0} + : b[51:0]}; + wire inputs_in_in3_rawIn_isZeroExpIn_2 = c[62:52] == 11'h0; + wire [5:0] inputs_in_in3_rawIn_normDist_2 = + c[51] + ? 6'h0 + : c[50] + ? 6'h1 + : c[49] + ? 6'h2 + : c[48] + ? 6'h3 + : c[47] + ? 6'h4 + : c[46] + ? 6'h5 + : c[45] + ? 6'h6 + : c[44] + ? 6'h7 + : c[43] + ? 6'h8 + : c[42] + ? 6'h9 + : c[41] + ? 6'hA + : c[40] + ? 6'hB + : c[39] + ? 6'hC + : c[38] + ? 6'hD + : c[37] + ? 6'hE + : c[36] + ? 6'hF + : c[35] + ? 6'h10 + : c[34] + ? 6'h11 + : c[33] + ? 6'h12 + : c[32] + ? 6'h13 + : c[31] + ? 6'h14 + : c[30] + ? 6'h15 + : c[29] + ? 6'h16 + : c[28] + ? 6'h17 + : c[27] + ? 6'h18 + : c[26] + ? 6'h19 + : c[25] + ? 6'h1A + : c[24] + ? 6'h1B + : c[23] + ? 6'h1C + : c[22] + ? 6'h1D + : c[21] + ? 6'h1E + : c[20] + ? 6'h1F + : c[19] + ? 6'h20 + : c[18] + ? 6'h21 + : c[17] + ? 6'h22 + : c[16] + ? 6'h23 + : c[15] + ? 6'h24 + : c[14] + ? 6'h25 + : c[13] + ? 6'h26 + : c[12] + ? 6'h27 + : c[11] + ? 6'h28 + : c[10] + ? 6'h29 + : c[9] + ? 6'h2A + : c[8] + ? 6'h2B + : c[7] + ? 6'h2C + : c[6] + ? 6'h2D + : c[5] + ? 6'h2E + : c[4] + ? 6'h2F + : c[3] + ? 6'h30 + : c[2] + ? 6'h31 + : {5'h19, + ~(c[1])}; + wire [114:0] _inputs_in_in3_rawIn_subnormFract_T_4 = + {63'h0, c[51:0]} << inputs_in_in3_rawIn_normDist_2; + wire [11:0] _inputs_in_in3_rawIn_adjustedExp_T_14 = + (inputs_in_in3_rawIn_isZeroExpIn_2 + ? {6'h3F, ~inputs_in_in3_rawIn_normDist_2} + : {1'h0, c[62:52]}) + {10'h100, inputs_in_in3_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1}; + wire [2:0] _inputs_in_in3_T_22 = + inputs_in_in3_rawIn_isZeroExpIn_2 & ~(|(c[51:0])) + ? 3'h0 + : _inputs_in_in3_rawIn_adjustedExp_T_14[11:9]; + wire [64:0] inputs_2_in3 = + {c[63], + _inputs_in_in3_T_22[2:1], + _inputs_in_in3_T_22[0] | (&(_inputs_in_in3_rawIn_adjustedExp_T_14[11:10])) + & (|(c[51:0])), + _inputs_in_in3_rawIn_adjustedExp_T_14[8:0], + inputs_in_in3_rawIn_isZeroExpIn_2 + ? {_inputs_in_in3_rawIn_subnormFract_T_4[50:0], 1'h0} + : c[51:0]}; + reg [64:0] refs_pipe_b_data; + reg [4:0] refs_pipe_b_exc; + reg [64:0] refs_pipe_b_1_data; + reg [4:0] refs_pipe_b_1_exc; + wire [3:0][64:0] _GEN_0 = + {{inputs_0_in1}, {inputs_2_in1}, {inputs_1_in1}, {inputs_0_in1}}; + wire [3:0][64:0] _GEN_1 = + {{inputs_0_in2}, {inputs_2_in2}, {inputs_1_in2}, {inputs_0_in2}}; + wire [3:0][64:0] _GEN_2 = + {{inputs_0_in3}, {inputs_2_in3}, {inputs_1_in3}, {inputs_0_in3}}; + reg outputTag_pipe_v; + reg [1:0] outputTag_pipe_b; + reg outputTag_pipe_pipe_v; + reg [1:0] outputTag_pipe_pipe_b; + reg outputTag_pipe_pipe_pipe_v; + reg [1:0] outputTag_pipe_pipe_pipe_b; + reg outputTag_pipe_pipe_pipe_pipe_v; + reg [1:0] outputTag_pipe_pipe_pipe_pipe_b; + reg outputTag_pipe_pipe_pipe_pipe_pipe_v; + reg [1:0] outputTag_pipe_pipe_pipe_pipe_pipe_b; + reg outputTag_pipe_pipe_pipe_pipe_pipe_pipe_v; + reg [1:0] outputTag_pipe_pipe_pipe_pipe_pipe_pipe_b; + wire originalData_rawIn_isInf = + (&(refs_pipe_b_data[15:14])) & ~(refs_pipe_b_data[13]); + wire originalData_isSubnormal = + $signed({1'h0, refs_pipe_b_data[15:10]}) < 7'sh12; + wire [10:0] _originalData_denormFract_T_1 = + {1'h0, |(refs_pipe_b_data[15:13]), refs_pipe_b_data[9:1]} >> 4'h1 + - refs_pipe_b_data[13:10]; + wire [63:0] originalData_0 = + {48'h0, + refs_pipe_b_data[16], + (originalData_isSubnormal ? 5'h0 : refs_pipe_b_data[14:10] + 5'hF) + | {5{(&(refs_pipe_b_data[15:14])) & refs_pipe_b_data[13] + | originalData_rawIn_isInf}}, + originalData_isSubnormal + ? _originalData_denormFract_T_1[9:0] + : originalData_rawIn_isInf ? 10'h0 : refs_pipe_b_data[9:0]}; + wire originalData_rawIn_1_isInf = + (&(refs_pipe_b_1_data[31:30])) & ~(refs_pipe_b_1_data[29]); + wire originalData_isSubnormal_1 = + $signed({1'h0, refs_pipe_b_1_data[31:23]}) < 10'sh82; + wire [23:0] _originalData_denormFract_T_3 = + {1'h0, |(refs_pipe_b_1_data[31:29]), refs_pipe_b_1_data[22:1]} >> 5'h1 + - refs_pipe_b_1_data[27:23]; + wire originalData_rawIn_2_isInf = + (&(_refs_unit_2_io_out_bits_data[63:62])) & ~(_refs_unit_2_io_out_bits_data[61]); + wire originalData_isSubnormal_2 = + $signed({1'h0, _refs_unit_2_io_out_bits_data[63:52]}) < 13'sh402; + wire [52:0] _originalData_denormFract_T_5 = + {1'h0, |(_refs_unit_2_io_out_bits_data[63:61]), _refs_unit_2_io_out_bits_data[51:1]} + >> 6'h1 - _refs_unit_2_io_out_bits_data[57:52]; + wire sharedData_rawIn_isInf = + (&(_shared_io_out_bits_data[15:14])) & ~(_shared_io_out_bits_data[13]); + wire sharedData_isSubnormal = + $signed({1'h0, _shared_io_out_bits_data[15:10]}) < 7'sh12; + wire [10:0] _sharedData_denormFract_T_1 = + {1'h0, |(_shared_io_out_bits_data[15:13]), _shared_io_out_bits_data[9:1]} >> 4'h1 + - _shared_io_out_bits_data[13:10]; + wire [63:0] sharedData_0 = + {48'h0, + _shared_io_out_bits_data[16], + (sharedData_isSubnormal ? 5'h0 : _shared_io_out_bits_data[14:10] + 5'hF) + | {5{(&(_shared_io_out_bits_data[15:14])) & _shared_io_out_bits_data[13] + | sharedData_rawIn_isInf}}, + sharedData_isSubnormal + ? _sharedData_denormFract_T_1[9:0] + : sharedData_rawIn_isInf ? 10'h0 : _shared_io_out_bits_data[9:0]}; + wire sharedData_rawIn_1_isInf = + (&(_shared_io_out_bits_data[31:30])) & ~(_shared_io_out_bits_data[29]); + wire sharedData_isSubnormal_1 = + $signed({1'h0, _shared_io_out_bits_data[31:23]}) < 10'sh82; + wire [23:0] _sharedData_denormFract_T_3 = + {1'h0, |(_shared_io_out_bits_data[31:29]), _shared_io_out_bits_data[22:1]} >> 5'h1 + - _shared_io_out_bits_data[27:23]; + wire sharedData_rawIn_2_isInf = + (&(_shared_io_out_bits_data[63:62])) & ~(_shared_io_out_bits_data[61]); + wire sharedData_isSubnormal_2 = + $signed({1'h0, _shared_io_out_bits_data[63:52]}) < 13'sh402; + wire [52:0] _sharedData_denormFract_T_5 = + {1'h0, |(_shared_io_out_bits_data[63:61]), _shared_io_out_bits_data[51:1]} >> 6'h1 + - _shared_io_out_bits_data[57:52]; + wire [3:0][63:0] _GEN_3 = + {{originalData_0}, + {{_refs_unit_2_io_out_bits_data[64], + (originalData_isSubnormal_2 + ? 11'h0 + : _refs_unit_2_io_out_bits_data[62:52] + 11'h3FF) + | {11{(&(_refs_unit_2_io_out_bits_data[63:62])) + & _refs_unit_2_io_out_bits_data[61] | originalData_rawIn_2_isInf}}, + originalData_isSubnormal_2 + ? _originalData_denormFract_T_5[51:0] + : originalData_rawIn_2_isInf ? 52'h0 : _refs_unit_2_io_out_bits_data[51:0]}}, + {{32'h0, + refs_pipe_b_1_data[32], + (originalData_isSubnormal_1 ? 8'h0 : refs_pipe_b_1_data[30:23] + 8'h7F) + | {8{(&(refs_pipe_b_1_data[31:30])) & refs_pipe_b_1_data[29] + | originalData_rawIn_1_isInf}}, + originalData_isSubnormal_1 + ? _originalData_denormFract_T_3[22:0] + : originalData_rawIn_1_isInf ? 23'h0 : refs_pipe_b_1_data[22:0]}}, + {originalData_0}}; + wire [63:0] _expected_output = _GEN_3[outputTag_pipe_pipe_pipe_pipe_pipe_pipe_b]; + wire [3:0][63:0] _GEN_4 = + {{sharedData_0}, + {{_shared_io_out_bits_data[64], + (sharedData_isSubnormal_2 ? 11'h0 : _shared_io_out_bits_data[62:52] + 11'h3FF) + | {11{(&(_shared_io_out_bits_data[63:62])) & _shared_io_out_bits_data[61] + | sharedData_rawIn_2_isInf}}, + sharedData_isSubnormal_2 + ? _sharedData_denormFract_T_5[51:0] + : sharedData_rawIn_2_isInf ? 52'h0 : _shared_io_out_bits_data[51:0]}}, + {{32'h0, + _shared_io_out_bits_data[32], + (sharedData_isSubnormal_1 ? 8'h0 : _shared_io_out_bits_data[30:23] + 8'h7F) + | {8{(&(_shared_io_out_bits_data[31:30])) & _shared_io_out_bits_data[29] + | sharedData_rawIn_1_isInf}}, + sharedData_isSubnormal_1 + ? _sharedData_denormFract_T_3[22:0] + : sharedData_rawIn_1_isInf ? 23'h0 : _shared_io_out_bits_data[22:0]}}, + {sharedData_0}}; + wire [63:0] _actual_output = _GEN_4[outputTag_pipe_pipe_pipe_pipe_pipe_pipe_b]; + wire [3:0][4:0] _GEN_5 = + {{refs_pipe_b_exc}, + {_refs_unit_2_io_out_bits_exc}, + {refs_pipe_b_1_exc}, + {refs_pipe_b_exc}}; + wire [4:0] _expectedFlags_output = + _GEN_5[outputTag_pipe_pipe_pipe_pipe_pipe_pipe_b]; + always @(posedge clock) begin + if (_refs_unit_io_out_valid) begin + refs_pipe_b_data <= _refs_unit_io_out_bits_data; + refs_pipe_b_exc <= _refs_unit_io_out_bits_exc; + end + if (_refs_unit_1_io_out_valid) begin + refs_pipe_b_1_data <= _refs_unit_1_io_out_bits_data; + refs_pipe_b_1_exc <= _refs_unit_1_io_out_bits_exc; + end + if (valid) + outputTag_pipe_b <= tag; + if (outputTag_pipe_v) + outputTag_pipe_pipe_b <= outputTag_pipe_b; + if (outputTag_pipe_pipe_v) + outputTag_pipe_pipe_pipe_b <= outputTag_pipe_pipe_b; + if (outputTag_pipe_pipe_pipe_v) + outputTag_pipe_pipe_pipe_pipe_b <= outputTag_pipe_pipe_pipe_b; + if (outputTag_pipe_pipe_pipe_pipe_v) + outputTag_pipe_pipe_pipe_pipe_pipe_b <= outputTag_pipe_pipe_pipe_pipe_b; + if (outputTag_pipe_pipe_pipe_pipe_pipe_v) + outputTag_pipe_pipe_pipe_pipe_pipe_pipe_b <= outputTag_pipe_pipe_pipe_pipe_pipe_b; + if (reset) begin + outputTag_pipe_v <= 1'h0; + outputTag_pipe_pipe_v <= 1'h0; + outputTag_pipe_pipe_pipe_v <= 1'h0; + outputTag_pipe_pipe_pipe_pipe_v <= 1'h0; + outputTag_pipe_pipe_pipe_pipe_pipe_v <= 1'h0; + outputTag_pipe_pipe_pipe_pipe_pipe_pipe_v <= 1'h0; + end + else begin + outputTag_pipe_v <= valid; + outputTag_pipe_pipe_v <= outputTag_pipe_v; + outputTag_pipe_pipe_pipe_v <= outputTag_pipe_pipe_v; + outputTag_pipe_pipe_pipe_pipe_v <= outputTag_pipe_pipe_pipe_v; + outputTag_pipe_pipe_pipe_pipe_pipe_v <= outputTag_pipe_pipe_pipe_pipe_v; + outputTag_pipe_pipe_pipe_pipe_pipe_pipe_v <= outputTag_pipe_pipe_pipe_pipe_pipe_v; + end + end // always @(posedge) + FPUFMAPipe_l5_f16 refs_unit ( + .clock (clock), + .reset (reset), + .io_in_valid (valid & tag == 2'h0), + .io_in_bits_ren3 (inputs_2_ren3), + .io_in_bits_swap23 (inputs_2_swap23), + .io_in_bits_rm (rm), + .io_in_bits_fmaCmd (op), + .io_in_bits_in1 (inputs_0_in1), + .io_in_bits_in2 (inputs_0_in2), + .io_in_bits_in3 (inputs_0_in3), + .io_out_valid (_refs_unit_io_out_valid), + .io_out_bits_data (_refs_unit_io_out_bits_data), + .io_out_bits_exc (_refs_unit_io_out_bits_exc) + ); + FPUFMAPipe_l5_f32 refs_unit_1 ( + .clock (clock), + .reset (reset), + .io_in_valid (valid & tag == 2'h1), + .io_in_bits_ren3 (inputs_2_ren3), + .io_in_bits_swap23 (inputs_2_swap23), + .io_in_bits_rm (rm), + .io_in_bits_fmaCmd (op), + .io_in_bits_in1 (inputs_1_in1), + .io_in_bits_in2 (inputs_1_in2), + .io_in_bits_in3 (inputs_1_in3), + .io_out_valid (_refs_unit_1_io_out_valid), + .io_out_bits_data (_refs_unit_1_io_out_bits_data), + .io_out_bits_exc (_refs_unit_1_io_out_bits_exc) + ); + FPUFMAPipe_l6_f64 refs_unit_2 ( + .clock (clock), + .reset (reset), + .io_in_valid (valid & tag == 2'h2), + .io_in_bits_ren3 (inputs_2_ren3), + .io_in_bits_swap23 (inputs_2_swap23), + .io_in_bits_rm (rm), + .io_in_bits_fmaCmd (op), + .io_in_bits_in1 (inputs_2_in1), + .io_in_bits_in2 (inputs_2_in2), + .io_in_bits_in3 (inputs_2_in3), + .io_out_bits_data (_refs_unit_2_io_out_bits_data), + .io_out_bits_exc (_refs_unit_2_io_out_bits_exc) + ); + FPUSharedFMAPipe shared ( + .clock (clock), + .reset (reset), + .io_in_valid (valid), + .io_in_bits_ren3 (inputs_2_ren3), + .io_in_bits_swap23 (inputs_2_swap23), + .io_in_bits_typeTagOut (_GEN[tag]), + .io_in_bits_rm (rm), + .io_in_bits_fmaCmd (op), + .io_in_bits_in1 (_GEN_0[tag]), + .io_in_bits_in2 (_GEN_1[tag]), + .io_in_bits_in3 (_GEN_2[tag]), + .io_out_valid (_shared_io_out_valid), + .io_out_bits_data (_shared_io_out_bits_data), + .io_out_bits_exc (_shared_io_out_bits_exc) + ); + assign expected = _expected_output; + assign actual = _actual_output; + assign expectedFlags = _expectedFlags_output; + assign actualFlags = _shared_io_out_bits_exc; + assign outValid = _shared_io_out_valid; + assign equal = + _shared_io_out_valid == outputTag_pipe_pipe_pipe_pipe_pipe_pipe_v + & (~outputTag_pipe_pipe_pipe_pipe_pipe_pipe_v | _expected_output == _actual_output + & _expectedFlags_output == _shared_io_out_bits_exc); +endmodule + diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/core-unit-regressions/GroupQueryCheck.sv b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/core-unit-regressions/GroupQueryCheck.sv new file mode 100644 index 0000000..fbf7300 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/core-unit-regressions/GroupQueryCheck.sv @@ -0,0 +1,374 @@ +// Generated by CIRCT firtool-1.62.1 +// Standard header to adapt well known macros for prints and assertions. + +// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. +`ifndef ASSERT_VERBOSE_COND_ + `ifdef ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) + `else // ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ 1 + `endif // ASSERT_VERBOSE_COND +`endif // not def ASSERT_VERBOSE_COND_ + +// Users can define 'STOP_COND' to add an extra gate to stop conditions. +`ifndef STOP_COND_ + `ifdef STOP_COND + `define STOP_COND_ (`STOP_COND) + `else // STOP_COND + `define STOP_COND_ 1 + `endif // STOP_COND +`endif // not def STOP_COND_ + +module RRArbiter( + input clock, + output io_in_0_ready, + input io_in_0_valid, + input [3:0] io_in_0_bits_bank, + input io_in_0_bits_shared, + output io_in_1_ready, + input io_in_1_valid, + input [3:0] io_in_1_bits_bank, + input io_in_1_bits_shared, + io_out_ready, + output io_out_valid, + output [3:0] io_out_bits_bank, + output io_out_bits_shared, + io_chosen +); + + wire io_chosen_choice; + wire io_out_valid_0 = io_chosen_choice ? io_in_1_valid : io_in_0_valid; + reg ctrl_validMask_grantMask_lastGrant; + wire ctrl_validMask_1 = io_in_1_valid & ~ctrl_validMask_grantMask_lastGrant; + assign io_chosen_choice = ctrl_validMask_1 | ~io_in_0_valid; + always @(posedge clock) begin + if (io_out_ready & io_out_valid_0) + ctrl_validMask_grantMask_lastGrant <= io_chosen_choice; + end // always @(posedge) + assign io_in_0_ready = ~ctrl_validMask_1 & io_out_ready; + assign io_in_1_ready = + (~ctrl_validMask_grantMask_lastGrant | ~(ctrl_validMask_1 | io_in_0_valid)) + & io_out_ready; + assign io_out_valid = io_out_valid_0; + assign io_out_bits_bank = io_chosen_choice ? io_in_1_bits_bank : io_in_0_bits_bank; + assign io_out_bits_shared = + io_chosen_choice ? io_in_1_bits_shared : io_in_0_bits_shared; + assign io_chosen = io_chosen_choice; +endmodule + +module MemGroupQueryArbiter( + input clock, + reset, + output io_request_0_ready, + input io_request_0_valid, + input [3:0] io_request_0_bits_bank, + input io_request_0_bits_shared, + output io_request_1_ready, + input io_request_1_valid, + input [3:0] io_request_1_bits_bank, + input io_request_1_bits_shared, + io_response_0_ready, + output io_response_0_valid, + output [3:0] io_response_0_bits, + input io_response_1_ready, + output io_response_1_valid, + output [3:0] io_response_1_bits, + io_backendBank, + output io_backendShared, + input [3:0] io_backendCount +); + + wire _arbiter_io_out_valid; + wire [3:0] _arbiter_io_out_bits_bank; + wire _arbiter_io_out_bits_shared; + wire _arbiter_io_chosen; + reg [1:0] state; + reg owner; + reg [3:0] address_bank; + reg address_shared; + reg [3:0] count; + wire _query_T = state == 2'h0; + wire io_response_0_valid_0 = (&state) & ~owner; + wire io_response_1_valid_0 = (&state) & owner; + always @(posedge clock) begin + if (reset) begin + state <= 2'h0; + owner <= 1'h0; + address_bank <= 4'h0; + address_shared <= 1'h0; + count <= 4'h0; + end + else begin + automatic logic _GEN; + automatic logic _GEN_0; + _GEN = _query_T & _arbiter_io_out_valid; + _GEN_0 = state == 2'h2; + if ((owner ? io_response_1_ready : io_response_0_ready) + & (owner ? io_response_1_valid_0 : io_response_0_valid_0)) + state <= 2'h0; + else if (_GEN_0) + state <= 2'h3; + else if (state == 2'h1) + state <= 2'h2; + else if (_GEN) + state <= 2'h1; + if (_GEN) begin + owner <= _arbiter_io_chosen; + address_bank <= _arbiter_io_out_bits_bank; + address_shared <= _arbiter_io_out_bits_shared; + end + if (_GEN_0) + count <= io_backendCount; + end + end // always @(posedge) + RRArbiter arbiter ( + .clock (clock), + .io_in_0_ready (io_request_0_ready), + .io_in_0_valid (io_request_0_valid), + .io_in_0_bits_bank (io_request_0_bits_bank), + .io_in_0_bits_shared (io_request_0_bits_shared), + .io_in_1_ready (io_request_1_ready), + .io_in_1_valid (io_request_1_valid), + .io_in_1_bits_bank (io_request_1_bits_bank), + .io_in_1_bits_shared (io_request_1_bits_shared), + .io_out_ready (_query_T), + .io_out_valid (_arbiter_io_out_valid), + .io_out_bits_bank (_arbiter_io_out_bits_bank), + .io_out_bits_shared (_arbiter_io_out_bits_shared), + .io_chosen (_arbiter_io_chosen) + ); + assign io_response_0_valid = io_response_0_valid_0; + assign io_response_0_bits = count; + assign io_response_1_valid = io_response_1_valid_0; + assign io_response_1_bits = count; + assign io_backendBank = _query_T ? _arbiter_io_out_bits_bank : address_bank; + assign io_backendShared = _query_T ? _arbiter_io_out_bits_shared : address_shared; +endmodule + +// VCS coverage exclude_file +module ram_4x4( + input [1:0] R0_addr, + input R0_en, + R0_clk, + output [3:0] R0_data, + input [1:0] W0_addr, + input W0_en, + W0_clk, + input [3:0] W0_data +); + + reg [3:0] Memory[0:3]; + always @(posedge W0_clk) begin + if (W0_en & 1'h1) + Memory[W0_addr] <= W0_data; + end // always @(posedge) + assign R0_data = R0_en ? Memory[R0_addr] : 4'bx; +endmodule + +module Queue4_UInt4( + input clock, + reset, + output io_enq_ready, + input io_enq_valid, + input [3:0] io_enq_bits, + input io_deq_ready, + output io_deq_valid, + output [3:0] io_deq_bits +); + + reg [1:0] enq_ptr_value; + reg [1:0] deq_ptr_value; + reg maybe_full; + wire ptr_match = enq_ptr_value == deq_ptr_value; + wire empty = ptr_match & ~maybe_full; + wire full = ptr_match & maybe_full; + wire do_enq = ~full & io_enq_valid; + always @(posedge clock) begin + if (reset) begin + enq_ptr_value <= 2'h0; + deq_ptr_value <= 2'h0; + maybe_full <= 1'h0; + end + else begin + automatic logic do_deq = io_deq_ready & ~empty; + if (do_enq) + enq_ptr_value <= enq_ptr_value + 2'h1; + if (do_deq) + deq_ptr_value <= deq_ptr_value + 2'h1; + if (~(do_enq == do_deq)) + maybe_full <= do_enq; + end + end // always @(posedge) + ram_4x4 ram_ext ( + .R0_addr (deq_ptr_value), + .R0_en (1'h1), + .R0_clk (clock), + .R0_data (io_deq_bits), + .W0_addr (enq_ptr_value), + .W0_en (do_enq), + .W0_clk (clock), + .W0_data (io_enq_bits) + ); + assign io_enq_ready = ~full; + assign io_deq_valid = ~empty; +endmodule + +module GroupQueryCheck( + input clock, + reset, + output passed +); + + wire _dut_io_request_1_bits_shared_T; + wire _sent_1_7; + wire _sent_0_7; + wire _expected_1_io_enq_ready; + wire _expected_1_io_deq_valid; + wire [3:0] _expected_1_io_deq_bits; + wire _expected_io_enq_ready; + wire _expected_io_deq_valid; + wire [3:0] _expected_io_deq_bits; + wire _dut_io_request_0_ready; + wire _dut_io_request_1_ready; + wire _dut_io_response_0_valid; + wire [3:0] _dut_io_response_0_bits; + wire _dut_io_response_1_valid; + wire [3:0] _dut_io_response_1_bits; + wire [3:0] _dut_io_backendBank; + wire _dut_io_backendShared; + reg [15:0] cycle; + reg [3:0] dut_io_backendCount_REG; + reg [3:0] dut_io_backendCount_REG_1; + reg [7:0] sent_0; + reg [7:0] sent_1; + reg [7:0] received_0; + reg [7:0] received_1; + assign _sent_0_7 = sent_0[7]; + wire _expected_io_enq_valid_T = _dut_io_request_0_ready & ~_sent_0_7; + wire _dut_io_response_0_ready_T_2 = cycle[1] & cycle[0]; + wire _expected_io_deq_ready_T = + _dut_io_response_0_ready_T_2 & _dut_io_response_0_valid; + assign _sent_1_7 = sent_1[7]; + assign _dut_io_request_1_bits_shared_T = sent_1[4]; + wire _expected_io_enq_valid_T_1 = _dut_io_request_1_ready & ~_sent_1_7; + wire _dut_io_response_1_ready_T_2 = cycle[2] & cycle[0]; + wire _expected_io_deq_ready_T_1 = + _dut_io_response_1_ready_T_2 & _dut_io_response_1_valid; + `ifndef SYNTHESIS + always @(posedge clock) begin + automatic logic _GEN = _dut_io_response_0_valid & ~reset; + automatic logic _GEN_0 = _dut_io_response_1_valid & ~reset; + if (~reset & cycle > 16'h270F) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: Group query arbitration timeout\n at EmitGroupQueryCheck.scala:13 assert(cycle < 10000.U, \"Group query arbitration timeout\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_expected_io_enq_valid_T & ~reset & ~_expected_io_enq_ready) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitGroupQueryCheck.scala:29 assert(expected.io.enq.ready)\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN & ~_expected_io_deq_valid) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: Query reply without an accepted request\n at EmitGroupQueryCheck.scala:33 assert(expected.io.deq.valid, \"Query reply without an accepted request\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN & _dut_io_response_0_bits != _expected_io_deq_bits) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: Reply belongs to another bank/client\n at EmitGroupQueryCheck.scala:34 assert(dut.io.response(i).bits === expected.io.deq.bits, \"Reply belongs to another bank/client\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_expected_io_enq_valid_T_1 & ~reset & ~_expected_1_io_enq_ready) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitGroupQueryCheck.scala:29 assert(expected.io.enq.ready)\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_0 & ~_expected_1_io_deq_valid) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: Query reply without an accepted request\n at EmitGroupQueryCheck.scala:33 assert(expected.io.deq.valid, \"Query reply without an accepted request\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_0 & _dut_io_response_1_bits != _expected_1_io_deq_bits) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: Reply belongs to another bank/client\n at EmitGroupQueryCheck.scala:34 assert(dut.io.response(i).bits === expected.io.deq.bits, \"Reply belongs to another bank/client\")\n"); + if (`STOP_COND_) + $fatal; + end + end // always @(posedge) + `endif // not def SYNTHESIS + always @(posedge clock) begin + if (reset) begin + cycle <= 16'h0; + dut_io_backendCount_REG <= 4'h0; + dut_io_backendCount_REG_1 <= 4'h0; + sent_0 <= 8'h0; + sent_1 <= 8'h0; + received_0 <= 8'h0; + received_1 <= 8'h0; + end + else begin + cycle <= cycle + 16'h1; + dut_io_backendCount_REG <= + {1'h0, _dut_io_backendBank[2:0] ^ {_dut_io_backendShared, 2'h0}} + 4'h1; + dut_io_backendCount_REG_1 <= dut_io_backendCount_REG; + if (_expected_io_enq_valid_T) + sent_0 <= sent_0 + 8'h1; + if (_expected_io_enq_valid_T_1) + sent_1 <= sent_1 + 8'h1; + if (_expected_io_deq_ready_T) + received_0 <= received_0 + 8'h1; + if (_expected_io_deq_ready_T_1) + received_1 <= received_1 + 8'h1; + end + end // always @(posedge) + MemGroupQueryArbiter dut ( + .clock (clock), + .reset (reset), + .io_request_0_ready (_dut_io_request_0_ready), + .io_request_0_valid (~_sent_0_7), + .io_request_0_bits_bank (sent_0[3:0]), + .io_request_0_bits_shared (sent_0[4]), + .io_request_1_ready (_dut_io_request_1_ready), + .io_request_1_valid (~_sent_1_7), + .io_request_1_bits_bank ({sent_1[3], ~(sent_1[2:0])}), + .io_request_1_bits_shared (~_dut_io_request_1_bits_shared_T), + .io_response_0_ready (_dut_io_response_0_ready_T_2), + .io_response_0_valid (_dut_io_response_0_valid), + .io_response_0_bits (_dut_io_response_0_bits), + .io_response_1_ready (_dut_io_response_1_ready_T_2), + .io_response_1_valid (_dut_io_response_1_valid), + .io_response_1_bits (_dut_io_response_1_bits), + .io_backendBank (_dut_io_backendBank), + .io_backendShared (_dut_io_backendShared), + .io_backendCount (dut_io_backendCount_REG_1) + ); + Queue4_UInt4 expected ( + .clock (clock), + .reset (reset), + .io_enq_ready (_expected_io_enq_ready), + .io_enq_valid (_expected_io_enq_valid_T), + .io_enq_bits ({1'h0, sent_0[2:0] ^ {sent_0[4], 2'h0}} + 4'h1), + .io_deq_ready (_expected_io_deq_ready_T), + .io_deq_valid (_expected_io_deq_valid), + .io_deq_bits (_expected_io_deq_bits) + ); + Queue4_UInt4 expected_1 ( + .clock (clock), + .reset (reset), + .io_enq_ready (_expected_1_io_enq_ready), + .io_enq_valid (_expected_io_enq_valid_T_1), + .io_enq_bits + ({1'h0, ~(sent_1[2:0]) ^ {~_dut_io_request_1_bits_shared_T, 2'h0}} + 4'h1), + .io_deq_ready (_expected_io_deq_ready_T_1), + .io_deq_valid (_expected_1_io_deq_valid), + .io_deq_bits (_expected_1_io_deq_bits) + ); + assign passed = received_0 == 8'h80 & received_1 == 8'h80; +endmodule + diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/core-unit-regressions/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/core-unit-regressions/RESULT.json new file mode 100644 index 0000000..d3e7170 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/core-unit-regressions/RESULT.json @@ -0,0 +1,18 @@ +{ + "result": "PASS_UNIT_REGRESSIONS", + "physical_hardware_tested": false, + "tests": { + "round": "PASS", + "group": "PASS", + "subrob": "PASS", + "fma": "PASS", + "rf": "PASS", + "pe": "PASS" + }, + "generated_rtl": { + "FmaPrecisionCheck.sv": "6d2af6cb54d8d190938afe0018f5ee72f964a178de2a158861c041aea04765a4", + "SubRobCheck.sv": "90c6e4cd01383fcd0a5a2956f0390998454f605c728d0830a371db288c02cc94", + "GroupQueryCheck.sv": "cc94ec9c0917f8ad6a6a6eece7fc7927b255ee1fb73052085e3ebb0319309294", + "RoundShiftChecks.sv": "d1da6458d0802ef201f7ecb90d62b8d0716cebdd3a29e6055174390ba7f7d3e2" + } +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/core-unit-regressions/RoundShiftChecks.sv b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/core-unit-regressions/RoundShiftChecks.sv new file mode 100644 index 0000000..c6cbbaf --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/core-unit-regressions/RoundShiftChecks.sv @@ -0,0 +1,93 @@ +// Generated by CIRCT firtool-1.62.1 +module RoundShiftChecks( + input [19:0] value20, + input [31:0] value32, + input [4:0] amount, + output [19:0] actual20, + output [31:0] actual32, + output [19:0] original20, + output [31:0] original32 +); + + wire [21:0] _actual20_T_1 = amount[0] ? {value20[19], value20, 1'h0} : {value20, 2'h0}; + wire [21:0] _actual20_T_3 = + amount[1] + ? {{2{_actual20_T_1[21]}}, + _actual20_T_1[21:3], + _actual20_T_1[2] | (|(_actual20_T_1[1:0]))} + : _actual20_T_1; + wire [21:0] _actual20_T_5 = + amount[2] + ? {{4{_actual20_T_3[21]}}, + _actual20_T_3[21:5], + _actual20_T_3[4] | (|(_actual20_T_3[3:0]))} + : _actual20_T_3; + wire [21:0] _actual20_T_7 = + amount[3] + ? {{8{_actual20_T_5[21]}}, + _actual20_T_5[21:9], + _actual20_T_5[8] | (|(_actual20_T_5[7:0]))} + : _actual20_T_5; + wire [21:0] _actual20_T_9 = + amount[4] + ? {{16{_actual20_T_7[21]}}, + _actual20_T_7[21:17], + _actual20_T_7[16] | (|(_actual20_T_7[15:0]))} + : _actual20_T_7; + wire [33:0] _actual32_T_1 = amount[0] ? {value32[31], value32, 1'h0} : {value32, 2'h0}; + wire [33:0] _actual32_T_3 = + amount[1] + ? {{2{_actual32_T_1[33]}}, + _actual32_T_1[33:3], + _actual32_T_1[2] | (|(_actual32_T_1[1:0]))} + : _actual32_T_1; + wire [33:0] _actual32_T_5 = + amount[2] + ? {{4{_actual32_T_3[33]}}, + _actual32_T_3[33:5], + _actual32_T_3[4] | (|(_actual32_T_3[3:0]))} + : _actual32_T_3; + wire [33:0] _actual32_T_7 = + amount[3] + ? {{8{_actual32_T_5[33]}}, + _actual32_T_5[33:9], + _actual32_T_5[8] | (|(_actual32_T_5[7:0]))} + : _actual32_T_5; + wire [33:0] _actual32_T_9 = + amount[4] + ? {{16{_actual32_T_7[33]}}, + _actual32_T_7[33:17], + _actual32_T_7[16] | (|(_actual32_T_7[15:0]))} + : _actual32_T_7; + wire [31:0] _GEN = {{12{value20[19]}}, value20}; + wire [31:0] _GEN_0 = {27'h0, amount - 5'h1}; + wire [31:0] _original20_point_five_T_3 = $signed($signed(_GEN) >>> _GEN_0); + wire _original32_zeros_T = amount < 5'h2; + wire [31:0] _GEN_1 = {27'h0, amount}; + wire [31:0] _original20_T_1 = $signed($signed(_GEN) >>> _GEN_1); + wire [31:0] _original20_T_3 = + _original20_T_1 + + {31'h0, + (|amount) & _original20_point_five_T_3[0] + & ((|(_original32_zeros_T ? 32'h0 : _GEN & (32'h1 << _GEN_0) - 32'h1)) + | _original20_T_1[0])}; + wire [31:0] _original32_point_five_T_3 = $signed($signed(value32) >>> _GEN_0); + wire [31:0] _original32_T = $signed($signed(value32) >>> _GEN_1); + assign actual20 = + _actual20_T_9[21:2] + + {19'h0, _actual20_T_9[1] & (_actual20_T_9[0] | _actual20_T_9[2])}; + assign actual32 = + _actual32_T_9[33:2] + + {31'h0, _actual32_T_9[1] & (_actual32_T_9[0] | _actual32_T_9[2])}; + assign original20 = + $signed(_original20_T_3) > 32'sh7FFFF + ? 20'h7FFFF + : $signed(_original20_T_3) < -32'sh80000 ? 20'h80000 : _original20_T_3[19:0]; + assign original32 = + _original32_T + + {31'h0, + (|amount) & _original32_point_five_T_3[0] + & ((|(_original32_zeros_T ? 32'h0 : value32 & (32'h1 << _GEN_0) - 32'h1)) + | _original32_T[0])}; +endmodule + diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/core-unit-regressions/SubRobCheck.sv b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/core-unit-regressions/SubRobCheck.sv new file mode 100644 index 0000000..a6f2a50 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/core-unit-regressions/SubRobCheck.sv @@ -0,0 +1,568 @@ +// Generated by CIRCT firtool-1.62.1 +// Standard header to adapt well known macros for prints and assertions. + +// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. +`ifndef ASSERT_VERBOSE_COND_ + `ifdef ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) + `else // ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ 1 + `endif // ASSERT_VERBOSE_COND +`endif // not def ASSERT_VERBOSE_COND_ + +// Users can define 'STOP_COND' to add an extra gate to stop conditions. +`ifndef STOP_COND_ + `ifdef STOP_COND + `define STOP_COND_ (`STOP_COND) + `else // STOP_COND + `define STOP_COND_ 1 + `endif // STOP_COND +`endif // not def STOP_COND_ + +// VCS coverage exclude_file +module sram_8x1269( + input [2:0] R0_addr, + input R0_en, + R0_clk, + output [1268:0] R0_data, + input [2:0] W0_addr, + input W0_en, + W0_clk, + input [1268:0] W0_data +); + + reg [1268:0] Memory[0:7]; + reg _R0_en_d0; + reg [2:0] _R0_addr_d0; + always @(posedge R0_clk) begin + _R0_en_d0 <= R0_en; + _R0_addr_d0 <= R0_addr; + end // always @(posedge) + always @(posedge W0_clk) begin + if (W0_en & 1'h1) + Memory[W0_addr] <= W0_data; + end // always @(posedge) + assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 1269'bx; +endmodule + +module SubROB( + input clock, + reset, + output io_write_ready, + input io_write_valid, + io_write_bits_slots_0_valid, + input [31:0] io_write_bits_slots_0_cmd_cmd_raw_inst, + input io_write_bits_slots_1_valid, + input [31:0] io_write_bits_slots_1_cmd_cmd_raw_inst, + io_write_bits_slots_2_cmd_cmd_raw_inst, + io_write_bits_slots_3_cmd_cmd_raw_inst, + input io_issue_ready, + output io_issue_valid, + output [31:0] io_issue_bits_cmd_raw_inst, + output [4:0] io_issueSubId, + input io_subComplete_valid, + input [4:0] io_subComplete_bits, + input io_masterComplete_ready, + output io_masterComplete_valid +); + + wire [1268:0] _sram_ext_R0_data; + reg [2:0] writePtr; + reg [2:0] readPtr; + reg [3:0] rowCount; + reg lockedBallId; + reg [3:0] masterRobId; + wire io_write_ready_0 = rowCount != 4'h8 & (~(|rowCount) | ~lockedBallId); + wire sram_MPORT_en = io_write_ready_0 & io_write_valid; + reg [2:0] state; + wire sramReadEn = state == 3'h1; + reg dataFresh; + reg sramData_slots_0_valid; + reg [31:0] sramData_slots_0_cmd_cmd_raw_inst; + reg sramData_slots_1_valid; + reg [31:0] sramData_slots_1_cmd_cmd_raw_inst; + reg sramData_slots_2_valid; + reg [31:0] sramData_slots_2_cmd_cmd_raw_inst; + reg sramData_slots_3_valid; + reg [31:0] sramData_slots_3_cmd_cmd_raw_inst; + reg [2:0] readPtrReg; + reg slotIssued_0; + reg slotIssued_1; + reg slotIssued_2; + reg slotIssued_3; + reg slotDone_0; + reg slotDone_1; + reg slotDone_2; + reg slotDone_3; + wire slotNeedsIssue_0 = sramData_slots_0_valid & ~slotIssued_0; + wire slotNeedsIssue_1 = sramData_slots_1_valid & ~slotIssued_1; + wire slotNeedsIssue_2 = sramData_slots_2_valid & ~slotIssued_2; + wire [1:0] firstSlotIdx = + slotNeedsIssue_0 ? 2'h0 : slotNeedsIssue_1 ? 2'h1 : {1'h1, ~slotNeedsIssue_2}; + wire _io_issue_valid_T = state == 3'h3; + wire io_issue_valid_0 = + _io_issue_valid_T + & (|{sramData_slots_3_valid & ~slotIssued_3, + slotNeedsIssue_2, + slotNeedsIssue_1, + slotNeedsIssue_0}); + wire [3:0][31:0] _GEN = + {{sramData_slots_3_cmd_cmd_raw_inst}, + {sramData_slots_2_cmd_cmd_raw_inst}, + {sramData_slots_1_cmd_cmd_raw_inst}, + {sramData_slots_0_cmd_cmd_raw_inst}}; + wire _GEN_0 = state == 3'h4; + wire _GEN_1 = state == 3'h5; + `ifndef SYNTHESIS + always @(posedge clock) begin + automatic logic _GEN_2 = io_subComplete_valid & ~reset; + if (sram_MPORT_en & (|rowCount) & ~reset & masterRobId != 4'h3) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: SubROB row master_rob_id mismatch\n at SubROB.scala:57 assert(io.write.bits.master_rob_id === masterRobId, \"SubROB row master_rob_id mismatch\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_2 & ~(_io_issue_valid_T | _GEN_0 | _GEN_1)) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: SubROB subComplete arrived in invalid state\n at SubROB.scala:115 assert(\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_2 & io_subComplete_bits / 5'h4 != {2'h0, readPtrReg}) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: SubROB subComplete points to non-active row\n at SubROB.scala:119 assert(subRow === readPtrReg, \"SubROB subComplete points to non-active row\")\n"); + if (`STOP_COND_) + $fatal; + end + end // always @(posedge) + `endif // not def SYNTHESIS + wire io_masterComplete_valid_0 = state == 3'h5; + always @(posedge clock) begin + if (reset) begin + writePtr <= 3'h0; + readPtr <= 3'h0; + rowCount <= 4'h0; + lockedBallId <= 1'h0; + masterRobId <= 4'h0; + state <= 3'h0; + dataFresh <= 1'h0; + slotIssued_0 <= 1'h0; + slotIssued_1 <= 1'h0; + slotIssued_2 <= 1'h0; + slotIssued_3 <= 1'h0; + slotDone_0 <= 1'h0; + slotDone_1 <= 1'h0; + slotDone_2 <= 1'h0; + slotDone_3 <= 1'h0; + end + else begin + automatic logic _GEN_3; + automatic logic [3:0] _allSlotsDone_T_8; + automatic logic _GEN_4; + automatic logic _GEN_5; + automatic logic _GEN_6; + automatic logic _GEN_7; + automatic logic _GEN_8 = state == 3'h0; + automatic logic _GEN_9 = state == 3'h1; + automatic logic _GEN_10 = state == 3'h2; + automatic logic _GEN_11; + automatic logic _allIssued_T_20; + automatic logic [3:0] _allIssued_T_24; + automatic logic [3:0] _allDoneNow_T_8; + automatic logic _GEN_12 = _GEN_8 | _GEN_9 | _GEN_10; + automatic logic _GEN_13; + automatic logic _GEN_14; + automatic logic [2:0] _GEN_15; + automatic logic [7:0][2:0] _GEN_16; + _GEN_3 = sram_MPORT_en & ~(|rowCount); + _allSlotsDone_T_8 = + {~sramData_slots_3_valid | slotDone_3, + ~sramData_slots_2_valid | slotDone_2, + ~sramData_slots_1_valid | slotDone_1, + ~sramData_slots_0_valid | slotDone_0}; + _GEN_4 = io_subComplete_valid & io_subComplete_bits[1:0] == 2'h0 | slotDone_0; + _GEN_5 = io_subComplete_valid & io_subComplete_bits[1:0] == 2'h1 | slotDone_1; + _GEN_6 = io_subComplete_valid & io_subComplete_bits[1:0] == 2'h2 | slotDone_2; + _GEN_7 = io_subComplete_valid & (&(io_subComplete_bits[1:0])) | slotDone_3; + _GEN_11 = state == 3'h3; + _allIssued_T_20 = io_issue_ready & io_issue_valid_0; + _allIssued_T_24 = + {~sramData_slots_3_valid | slotIssued_3 | _allIssued_T_20 & (&firstSlotIdx), + ~sramData_slots_2_valid | slotIssued_2 | _allIssued_T_20 & firstSlotIdx == 2'h2, + ~sramData_slots_1_valid | slotIssued_1 | _allIssued_T_20 & firstSlotIdx == 2'h1, + ~sramData_slots_0_valid | slotIssued_0 | _allIssued_T_20 & ~(|firstSlotIdx)}; + _allDoneNow_T_8 = + {~sramData_slots_3_valid | slotDone_3, + ~sramData_slots_2_valid | slotDone_2, + ~sramData_slots_1_valid | slotDone_1, + ~sramData_slots_0_valid | slotDone_0}; + _GEN_13 = _GEN_1 & io_masterComplete_ready & io_masterComplete_valid_0; + _GEN_14 = _GEN_8 | _GEN_9 | _GEN_10 | _GEN_11 | _GEN_0; + _GEN_15 = _GEN_13 ? 3'h0 : state; + if (sram_MPORT_en) begin + if (&writePtr) + writePtr <= 3'h0; + else + writePtr <= writePtr + 3'h1; + end + if (_GEN_12) begin + slotDone_0 <= _GEN_4; + slotDone_1 <= _GEN_5; + slotDone_2 <= _GEN_6; + slotDone_3 <= _GEN_7; + end + else if (_GEN_11) begin + automatic logic _GEN_17; + _GEN_17 = (&_allIssued_T_24) & (&_allDoneNow_T_8); + if (_GEN_17) begin + if (&readPtr) + readPtr <= 3'h0; + else + readPtr <= readPtr + 3'h1; + end + slotIssued_0 <= ~_GEN_17 & (_allIssued_T_20 & ~(|firstSlotIdx) | slotIssued_0); + slotIssued_1 <= + ~_GEN_17 & (_allIssued_T_20 & firstSlotIdx == 2'h1 | slotIssued_1); + slotIssued_2 <= + ~_GEN_17 & (_allIssued_T_20 & firstSlotIdx == 2'h2 | slotIssued_2); + slotIssued_3 <= ~_GEN_17 & (_allIssued_T_20 & (&firstSlotIdx) | slotIssued_3); + slotDone_0 <= ~_GEN_17 & _GEN_4; + slotDone_1 <= ~_GEN_17 & _GEN_5; + slotDone_2 <= ~_GEN_17 & _GEN_6; + slotDone_3 <= ~_GEN_17 & _GEN_7; + end + else begin + automatic logic _GEN_18; + _GEN_18 = _GEN_0 & (&_allSlotsDone_T_8); + if (_GEN_18) begin + if (&readPtr) + readPtr <= 3'h0; + else + readPtr <= readPtr + 3'h1; + end + slotIssued_0 <= ~_GEN_18 & slotIssued_0; + slotIssued_1 <= ~_GEN_18 & slotIssued_1; + slotIssued_2 <= ~_GEN_18 & slotIssued_2; + slotIssued_3 <= ~_GEN_18 & slotIssued_3; + slotDone_0 <= ~_GEN_18 & _GEN_4; + slotDone_1 <= ~_GEN_18 & _GEN_5; + slotDone_2 <= ~_GEN_18 & _GEN_6; + slotDone_3 <= ~_GEN_18 & _GEN_7; + end + if (~(sram_MPORT_en == (~_GEN_12 + & (_GEN_11 + ? (&_allIssued_T_24) & (&_allDoneNow_T_8) + : _GEN_0 & (&_allSlotsDone_T_8))))) begin + if (sram_MPORT_en) + rowCount <= rowCount + 4'h1; + else + rowCount <= rowCount - 4'h1; + end + if (_GEN_14) + lockedBallId <= ~_GEN_3 & lockedBallId; + else + lockedBallId <= ~(_GEN_13 | _GEN_3) & lockedBallId; + if (_GEN_14 | ~_GEN_13) begin + if (_GEN_3) + masterRobId <= 4'h3; + end + else + masterRobId <= 4'h0; + _GEN_16 = + {{_GEN_15}, + {_GEN_15}, + {_GEN_15}, + {(&_allSlotsDone_T_8) ? {rowCount == 4'h1 & ~sram_MPORT_en, 2'h1} : state}, + {(&_allIssued_T_24) + ? ((&_allDoneNow_T_8) ? {rowCount == 4'h1 & ~sram_MPORT_en, 2'h1} : 3'h4) + : state}, + {3'h3}, + {3'h2}, + {(|rowCount) ? 3'h1 : state}}; + state <= _GEN_16[state]; + dataFresh <= sramReadEn; + end + if (dataFresh) begin + sramData_slots_0_valid <= _sram_ext_R0_data[0]; + sramData_slots_0_cmd_cmd_raw_inst <= _sram_ext_R0_data[41:10]; + sramData_slots_1_valid <= _sram_ext_R0_data[316]; + sramData_slots_1_cmd_cmd_raw_inst <= _sram_ext_R0_data[357:326]; + sramData_slots_2_valid <= _sram_ext_R0_data[632]; + sramData_slots_2_cmd_cmd_raw_inst <= _sram_ext_R0_data[673:642]; + sramData_slots_3_valid <= _sram_ext_R0_data[948]; + sramData_slots_3_cmd_cmd_raw_inst <= _sram_ext_R0_data[989:958]; + end + if (sramReadEn) + readPtrReg <= readPtr; + end // always @(posedge) + sram_8x1269 sram_ext ( + .R0_addr (readPtr), + .R0_en (sramReadEn), + .R0_clk (clock), + .R0_data (_sram_ext_R0_data), + .W0_addr (writePtr), + .W0_en (sram_MPORT_en), + .W0_clk (clock), + .W0_data + ({279'h1800000000000000000000000000000000000000000000000000000000000000000000, + io_write_bits_slots_3_cmd_cmd_raw_inst, + 284'h0, + io_write_bits_slots_2_cmd_cmd_raw_inst, + 284'h0, + io_write_bits_slots_1_cmd_cmd_raw_inst, + 9'h0, + io_write_bits_slots_1_valid, + 274'h0, + io_write_bits_slots_0_cmd_cmd_raw_inst, + 9'h0, + io_write_bits_slots_0_valid}) + ); + assign io_write_ready = io_write_ready_0; + assign io_issue_valid = io_issue_valid_0; + assign io_issue_bits_cmd_raw_inst = _GEN[firstSlotIdx]; + assign io_issueSubId = {readPtrReg, 2'h0} + {3'h0, firstSlotIdx}; + assign io_masterComplete_valid = io_masterComplete_valid_0; +endmodule + +// VCS coverage exclude_file +module ram_8x5( + input [2:0] R0_addr, + input R0_en, + R0_clk, + output [4:0] R0_data, + input [2:0] W0_addr, + input W0_en, + W0_clk, + input [4:0] W0_data +); + + reg [4:0] Memory[0:7]; + always @(posedge W0_clk) begin + if (W0_en & 1'h1) + Memory[W0_addr] <= W0_data; + end // always @(posedge) + assign R0_data = R0_en ? Memory[R0_addr] : 5'bx; +endmodule + +module Queue8_UInt5( + input clock, + reset, + output io_enq_ready, + input io_enq_valid, + input [4:0] io_enq_bits, + input io_deq_ready, + output io_deq_valid, + output [4:0] io_deq_bits +); + + reg [2:0] enq_ptr_value; + reg [2:0] deq_ptr_value; + reg maybe_full; + wire ptr_match = enq_ptr_value == deq_ptr_value; + wire empty = ptr_match & ~maybe_full; + wire full = ptr_match & maybe_full; + wire do_enq = ~full & io_enq_valid; + always @(posedge clock) begin + if (reset) begin + enq_ptr_value <= 3'h0; + deq_ptr_value <= 3'h0; + maybe_full <= 1'h0; + end + else begin + automatic logic do_deq = io_deq_ready & ~empty; + if (do_enq) + enq_ptr_value <= enq_ptr_value + 3'h1; + if (do_deq) + deq_ptr_value <= deq_ptr_value + 3'h1; + if (~(do_enq == do_deq)) + maybe_full <= do_enq; + end + end // always @(posedge) + ram_8x5 ram_ext ( + .R0_addr (deq_ptr_value), + .R0_en (1'h1), + .R0_clk (clock), + .R0_data (io_deq_bits), + .W0_addr (enq_ptr_value), + .W0_en (do_enq), + .W0_clk (clock), + .W0_data (io_enq_bits) + ); + assign io_enq_ready = ~full; + assign io_deq_valid = ~empty; +endmodule + +module SubRobCheck( + input clock, + reset, + output passed +); + + wire _pending_io_enq_ready; + wire _pending_io_deq_valid; + wire [4:0] _pending_io_deq_bits; + wire _sub_io_write_ready; + wire _sub_io_issue_valid; + wire [31:0] _sub_io_issue_bits_cmd_raw_inst; + wire [4:0] _sub_io_issueSubId; + wire _sub_io_masterComplete_valid; + reg [15:0] cycle; + reg [5:0] sent; + reg [5:0] issued; + reg [5:0] completed; + reg [1:0] masters; + wire _sub_io_write_valid_T = sent < 6'h28; + wire [5:0] _sub_io_write_bits_slots_1_valid_T = sent % 6'h3; + wire [8:0] _GEN = {1'h0, sent, 2'h0}; + wire _sub_io_issue_ready_T_1 = _pending_io_enq_ready & cycle[0]; + wire _pending_io_enq_valid_T = _sub_io_issue_ready_T_1 & _sub_io_issue_valid; + wire _sub_io_subComplete_valid_T_1 = _pending_io_deq_valid & cycle[1]; + wire _GEN_0 = cycle[2] & _sub_io_masterComplete_valid; + `ifndef SYNTHESIS + always @(posedge clock) begin + automatic logic [63:0][31:0] _GEN_1 = + '{32'h4, + 32'h4, + 32'h4, + 32'h4, + 32'h4, + 32'h4, + 32'h4, + 32'h4, + 32'h4, + 32'h4, + 32'h4, + 32'h4, + 32'h4, + 32'h4, + 32'h4, + 32'h4, + 32'h4, + 32'h4, + 32'h4, + 32'h4, + 32'h4, + 32'h4, + 32'h4, + 32'h4, + 32'h4, + 32'h99, + 32'h98, + 32'h94, + 32'h8D, + 32'h8C, + 32'h88, + 32'h81, + 32'h80, + 32'h7C, + 32'h75, + 32'h74, + 32'h70, + 32'h69, + 32'h68, + 32'h64, + 32'h5D, + 32'h5C, + 32'h58, + 32'h51, + 32'h50, + 32'h4C, + 32'h45, + 32'h44, + 32'h40, + 32'h39, + 32'h38, + 32'h34, + 32'h2D, + 32'h2C, + 32'h28, + 32'h21, + 32'h20, + 32'h1C, + 32'h15, + 32'h14, + 32'h10, + 32'h9, + 32'h8, + 32'h4}; + automatic logic _GEN_2 = _pending_io_enq_valid_T & ~reset; + if (~reset & cycle > 16'h270F) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: SubROB streaming timeout\n at EmitSubRobCheck.scala:14 assert(cycle < 10000.U, \"SubROB streaming timeout\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_2 & issued > 6'h26) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitSubRobCheck.scala:41 assert(issued < expected.size.U)\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_2 & _sub_io_issue_bits_cmd_raw_inst != _GEN_1[issued]) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: SubROB dropped/reordered a row\n at EmitSubRobCheck.scala:42 assert(sub.io.issue.bits.cmd.raw_inst === commands(issued), \"SubROB dropped/reordered a row\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_0 & ~reset & ~(sent == 6'h28 & issued == 6'h27 & completed == 6'h27)) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: SubROB completed master before all accepted rows were executed\n at EmitSubRobCheck.scala:48 assert(sent === 40.U && issued === expected.size.U && completed === expected.size.U,\n"); + if (`STOP_COND_) + $fatal; + end + end // always @(posedge) + `endif // not def SYNTHESIS + always @(posedge clock) begin + if (reset) begin + cycle <= 16'h0; + sent <= 6'h0; + issued <= 6'h0; + completed <= 6'h0; + masters <= 2'h0; + end + else begin + cycle <= cycle + 16'h1; + if (_sub_io_write_ready & _sub_io_write_valid_T) + sent <= sent + 6'h1; + if (_pending_io_enq_valid_T) + issued <= issued + 6'h1; + if (_sub_io_subComplete_valid_T_1) + completed <= completed + 6'h1; + if (_GEN_0) + masters <= masters + 2'h1; + end + end // always @(posedge) + SubROB sub ( + .clock (clock), + .reset (reset), + .io_write_ready (_sub_io_write_ready), + .io_write_valid (_sub_io_write_valid_T), + .io_write_bits_slots_0_valid (|(_sub_io_write_bits_slots_1_valid_T[1:0])), + .io_write_bits_slots_0_cmd_cmd_raw_inst ({24'h0, sent, 2'h0}), + .io_write_bits_slots_1_valid + (_sub_io_write_bits_slots_1_valid_T[1:0] == 2'h2), + .io_write_bits_slots_1_cmd_cmd_raw_inst ({23'h0, _GEN + 9'h1}), + .io_write_bits_slots_2_cmd_cmd_raw_inst ({23'h0, _GEN + 9'h2}), + .io_write_bits_slots_3_cmd_cmd_raw_inst ({23'h0, _GEN + 9'h3}), + .io_issue_ready (_sub_io_issue_ready_T_1), + .io_issue_valid (_sub_io_issue_valid), + .io_issue_bits_cmd_raw_inst (_sub_io_issue_bits_cmd_raw_inst), + .io_issueSubId (_sub_io_issueSubId), + .io_subComplete_valid (_sub_io_subComplete_valid_T_1), + .io_subComplete_bits (_pending_io_deq_bits), + .io_masterComplete_ready (cycle[2]), + .io_masterComplete_valid (_sub_io_masterComplete_valid) + ); + Queue8_UInt5 pending ( + .clock (clock), + .reset (reset), + .io_enq_ready (_pending_io_enq_ready), + .io_enq_valid (_pending_io_enq_valid_T), + .io_enq_bits (_sub_io_issueSubId), + .io_deq_ready (cycle[1]), + .io_deq_valid (_pending_io_deq_valid), + .io_deq_bits (_pending_io_deq_bits) + ); + assign passed = masters == 2'h1; +endmodule + diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/core-unit-regressions/elaboration.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/core-unit-regressions/elaboration.log new file mode 100644 index 0000000..5898256 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/core-unit-regressions/elaboration.log @@ -0,0 +1,14 @@ +[info] welcome to sbt 1.12.11 (N/A Java 17.0.20) +[info] loading project definition from /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/project +[info] loading settings for project root from build.sbt... +[info] set current project to toy-arty-a7-linux (in build file:/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/) +[info] running fpga.arty.linux.EmitPeChecks +[success] Total time: 3 s, completed Oct 13, 2026, 12:57:36 AM +[info] running fpga.arty.linux.EmitFmaChecks +[success] Total time: 1 s, completed Oct 13, 2026, 12:57:38 AM +[info] running fpga.arty.linux.EmitRoundShiftChecks +[success] Total time: 1 s, completed Oct 13, 2026, 12:57:38 AM +[info] running fpga.arty.linux.EmitGroupQueryCheck +[success] Total time: 1 s, completed Oct 13, 2026, 12:57:39 AM +[info] running fpga.arty.linux.EmitSubRobCheck +[success] Total time: 1 s, completed Oct 13, 2026, 12:57:40 AM diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/core-unit-regressions/fma-compile.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/core-unit-regressions/fma-compile.log new file mode 100644 index 0000000..59eb83f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/core-unit-regressions/fma-compile.log @@ -0,0 +1,19 @@ +make: Entering directory '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/core-unit-regressions/fma-obj' +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Os -c -o fma_differential.o /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/fma_differential.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -c -o verilated.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -c -o verilated_threads.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_threads.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -x c++-header VFmaPrecisionCheck__pch.h -o VFmaPrecisionCheck__pch.h.fast.gch +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -x c++-header VFmaPrecisionCheck__pch.h -o VFmaPrecisionCheck__pch.h.slow.gch +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -include VFmaPrecisionCheck__pch.h.fast -c VFmaPrecisionCheck.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -include VFmaPrecisionCheck__pch.h.fast -c VFmaPrecisionCheck___024root__0.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -include VFmaPrecisionCheck__pch.h.fast -c VFmaPrecisionCheck___024root__1.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -include VFmaPrecisionCheck__pch.h.slow -c VFmaPrecisionCheck___024root__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -include VFmaPrecisionCheck__pch.h.slow -c VFmaPrecisionCheck___024root__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -include VFmaPrecisionCheck__pch.h.slow -c VFmaPrecisionCheck___024root__1__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -include VFmaPrecisionCheck__pch.h.slow -c VFmaPrecisionCheck__Syms__Slow.cpp +g++ fma_differential.o verilated.o verilated_threads.o VFmaPrecisionCheck__ALL.a -pthread -lpthread -latomic -o VFmaPrecisionCheck +rm VFmaPrecisionCheck__ALL.verilator_deplist.tmp +make: Leaving directory '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/core-unit-regressions/fma-obj' +- V e r i l a t i o n R e p o r t: Verilator 5.050 2026-07-01 rev v5.050 +- Verilator: Built from 0.251 MB sources in 24 modules, into 2.058 MB in 7 C++ files needing 0.006 MB +- Verilator: Walltime 3.830 s (elab=0.017, cvt=0.121, bld=3.653); cpu 0.204 s on 4 threads; allocated 367.379 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/core-unit-regressions/fma.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/core-unit-regressions/fma.log new file mode 100644 index 0000000..9528d57 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/core-unit-regressions/fma.log @@ -0,0 +1 @@ +PASS FMA_SHARED cycles=279118 comparisons=250819 H=83432 S=83970 D=83417 resets=7 reset_discarded=31 cpu_vectors=1536 diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/core-unit-regressions/group-compile.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/core-unit-regressions/group-compile.log new file mode 100644 index 0000000..f942900 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/core-unit-regressions/group-compile.log @@ -0,0 +1,12 @@ +make: Entering directory '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/core-unit-regressions/group-obj' +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_timing.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_timing.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_threads.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_threads.cpp +python3 /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vtb.cpp Vtb___024root__0.cpp Vtb__main.cpp Vtb___024root__Slow.cpp Vtb___024root__0__Slow.cpp Vtb__Syms__Slow.cpp > Vtb__ALL.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o Vtb__ALL.o Vtb__ALL.cpp +g++ verilated.o verilated_timing.o verilated_threads.o Vtb__ALL.a -pthread -lpthread -latomic -o Vtb +rm Vtb__ALL.verilator_deplist.tmp +make: Leaving directory '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/core-unit-regressions/group-obj' +- V e r i l a t i o n R e p o r t: Verilator 5.050 2026-07-01 rev v5.050 +- Verilator: Built from 0.080 MB sources in 7 modules, into 0.080 MB in 6 C++ files needing 0.000 MB +- Verilator: Walltime 3.490 s (elab=0.002, cvt=0.010, bld=3.469); cpu 0.026 s on 4 threads; allocated 223.438 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/core-unit-regressions/group.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/core-unit-regressions/group.log new file mode 100644 index 0000000..28af68f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/core-unit-regressions/group.log @@ -0,0 +1,5 @@ +PASS: 256 concurrent group queries, stalls, shared/private selection, reset and repeat +- /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/tb_group_query.sv:17: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 21ns; walltime 0.003 s; speed 7.968 us/s +- Verilator: cpu 0.003 s on 1 threads; allocated 6 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/core-unit-regressions/pe.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/core-unit-regressions/pe.log new file mode 100644 index 0000000..7896b50 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/core-unit-regressions/pe.log @@ -0,0 +1,7 @@ +PASS formal quantizer equivalence for all 2^25 input/shift pairs +PASS original/LUT/DSP PE: 91115 valid-cycle comparisons +- /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/tb_pe.sv:53: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 1ms; walltime 0.146 s; speed 7.247 ms/s +- Verilator: cpu 0.146 s on 1 threads; allocated 6 MB + diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/core-unit-regressions/rf-compile.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/core-unit-regressions/rf-compile.log new file mode 100644 index 0000000..e69de29 diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/core-unit-regressions/rf.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/core-unit-regressions/rf.log new file mode 100644 index 0000000..5df0ba4 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/core-unit-regressions/rf.log @@ -0,0 +1,2 @@ +PASS FPU_RF_LVT cycles=20032 comparisons=144129 dual_writes=15000 same_address_writes=2876 +/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/tb_fpu_rf.sv:95: $finish called at 200327000 (1ps) diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/core-unit-regressions/round-compile.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/core-unit-regressions/round-compile.log new file mode 100644 index 0000000..948c557 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/core-unit-regressions/round-compile.log @@ -0,0 +1,22 @@ +make: Entering directory '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/core-unit-regressions/round-obj' +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_timing.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_timing.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_threads.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_threads.cpp +python3 /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vtb.cpp Vtb___024root__0.cpp Vtb__main.cpp Vtb___024root__Slow.cpp Vtb___024root__0__Slow.cpp Vtb__Syms__Slow.cpp > Vtb__ALL.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o Vtb__ALL.o Vtb__ALL.cpp +g++ verilated.o verilated_timing.o verilated_threads.o Vtb__ALL.a -pthread -lpthread -latomic -o Vtb +rm Vtb__ALL.verilator_deplist.tmp +make: Leaving directory '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/core-unit-regressions/round-obj' +- V e r i l a t i o n R e p o r t: Verilator 5.050 2026-07-01 rev v5.050 +- Verilator: Built from 0.062 MB sources in 3 modules, into 0.156 MB in 6 C++ files needing 0.002 MB +- Verilator: Walltime 3.635 s (elab=0.002, cvt=0.013, bld=3.611); cpu 0.030 s on 4 threads; allocated 351.934 MB +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/tb_round_shift.sv:43:35: Operator NEGATE expects 64 bits on the LHS, but LHS's CONST '?32?sh80000000' generates 32 bits. + : ... note: In instance 'tb' + 43 | check(2147483647, s); check(-2147483648, s); + | ^ + ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=5.050 + ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/tb_round_shift.sv:49:59: Operator ADD expects 64 bits on the RHS, but RHS's VARREF 'delta' generates 32 bits. + : ... note: In instance 'tb' + 49 | check(q * (64'sd1 << s) + (64'sd1 << (s - 1)) + delta, s); + | ^ diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/core-unit-regressions/round.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/core-unit-regressions/round.log new file mode 100644 index 0000000..7dbcbb9 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/core-unit-regressions/round.log @@ -0,0 +1,5 @@ +PASS ROUND_SHIFT comparisons=402866 widths=20,32 shifts=0..31 +- /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/tb_round_shift.sv:57: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 201ns; walltime 0.041 s; speed 4.881 us/s +- Verilator: cpu 0.041 s on 1 threads; allocated 6 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/core-unit-regressions/subrob-compile.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/core-unit-regressions/subrob-compile.log new file mode 100644 index 0000000..0ab297f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/core-unit-regressions/subrob-compile.log @@ -0,0 +1,12 @@ +make: Entering directory '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/core-unit-regressions/subrob-obj' +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_timing.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_timing.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_threads.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_threads.cpp +python3 /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vtb.cpp Vtb___024root__0.cpp Vtb__main.cpp Vtb__ConstPool__0__Slow.cpp Vtb___024root__Slow.cpp Vtb___024root__0__Slow.cpp Vtb__Syms__Slow.cpp > Vtb__ALL.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o Vtb__ALL.o Vtb__ALL.cpp +g++ verilated.o verilated_timing.o verilated_threads.o Vtb__ALL.a -pthread -lpthread -latomic -o Vtb +rm Vtb__ALL.verilator_deplist.tmp +make: Leaving directory '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/core-unit-regressions/subrob-obj' +- V e r i l a t i o n R e p o r t: Verilator 5.050 2026-07-01 rev v5.050 +- Verilator: Built from 0.092 MB sources in 7 modules, into 0.128 MB in 7 C++ files needing 0.001 MB +- Verilator: Walltime 3.570 s (elab=0.002, cvt=0.012, bld=3.546); cpu 0.031 s on 4 threads; allocated 351.914 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/core-unit-regressions/subrob.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/core-unit-regressions/subrob.log new file mode 100644 index 0000000..d3b728b --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/core-unit-regressions/subrob.log @@ -0,0 +1,5 @@ +PASS SUBROB streaming rows=40 commands=39 cycles=269 +- /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/tb_subrob.sv:12: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 3ns; walltime 0.000 s; speed 13.852 us/s +- Verilator: cpu 0.000 s on 1 threads; allocated 6 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/cpu-smoke/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/cpu-smoke/RESULT.json new file mode 100644 index 0000000..78e8189 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/cpu-smoke/RESULT.json @@ -0,0 +1,10 @@ +{ + "result": "PASS", + "test_label": "whole Toy CPU smoke", + "core_rtl_sha256": "31e7e07f94d08208dbb564edf9546240df26ff834935bfb646b71b541d875fb9", + "test_binary_sha256": "3bbf33f7bf2b6bb0f3888ab4a649a11272de3f74458f6ea36b266f9670df75f5", + "cycles_including_boot": 639544, + "memory_read_bursts": 5970, + "memory_write_bursts": 2049, + "linux_boot_tested": false +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/cpu-smoke/simulation.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/cpu-smoke/simulation.log new file mode 100644 index 0000000..c342ea4 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/cpu-smoke/simulation.log @@ -0,0 +1,8 @@ +CPU status = 000000000000b007 +CPU status = 00000000600d600d +PASS whole Toy CPU smoke +- /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:88: Verilog $finish +MEASURE cycles=639544 memory_reads=5970 memory_writes=2049 +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 6ms; walltime 4.710 s; speed 1.358 ms/s +- Verilator: cpu 4.709 s on 1 threads; allocated 8 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/cpu-smoke/smoke.bin b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/cpu-smoke/smoke.bin new file mode 100644 index 0000000..f634740 Binary files /dev/null and b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/cpu-smoke/smoke.bin differ diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/cpu-smoke/smoke.disasm b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/cpu-smoke/smoke.disasm new file mode 100644 index 0000000..7389edf --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/cpu-smoke/smoke.disasm @@ -0,0 +1,477 @@ + +/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/smoke.elf: file format elf64-littleriscv + + +Disassembly of section .text: + +0000000080000000 <_start>: + 80000000: 00000297 auipc t0,0x0 + 80000004: 2fc28293 addi t0,t0,764 # 800002fc + 80000008: 30529073 csrw mtvec,t0 + 8000000c: 30201073 csrw medeleg,zero + 80000010: 30401073 csrw mie,zero + 80000014: 00000d13 li s10,0 + 80000018: 00000d93 li s11,0 + 8000001c: 00100193 li gp,1 + 80000020: 600002b7 lui t0,0x60000 + 80000024: 0000b337 lui t1,0xb + 80000028: 0073031b addiw t1,t1,7 # b007 <_start-0x7fff4ff9> + 8000002c: 0062b023 sd t1,0(t0) # 60000000 <_start-0x20000000> + 80000030: 00300d13 li s10,3 + 80000034: 00100073 ebreak + 80000038: 00100293 li t0,1 + 8000003c: 305d9063 bne s11,t0,8000033c + 80000040: 00200d13 li s10,2 + 80000044: 7b0022f3 csrr t0,dcsr + 80000048: 00200293 li t0,2 + 8000004c: 2e5d9863 bne s11,t0,8000033c + 80000050: 00500d13 li s10,5 + 80000054: 080002b7 lui t0,0x8000 + 80000058: 0002b303 ld t1,0(t0) # 8000000 <_start-0x78000000> + 8000005c: 00300293 li t0,3 + 80000060: 2c5d9e63 bne s11,t0,8000033c + 80000064: 00000d13 li s10,0 + 80000068: 00200193 li gp,2 + 8000006c: b0002473 csrr s0,mcycle + 80000070: b02024f3 csrr s1,minstret + 80000074: 10000293 li t0,256 + 80000078: fff28293 addi t0,t0,-1 + 8000007c: fe029ee3 bnez t0,80000078 <_start+0x78> + 80000080: b00022f3 csrr t0,mcycle + 80000084: 2a547c63 bgeu s0,t0,8000033c + 80000088: b02022f3 csrr t0,minstret + 8000008c: 2a54f863 bgeu s1,t0,8000033c + 80000090: 00300193 li gp,3 + 80000094: 0200c2b7 lui t0,0x200c + 80000098: ff82829b addiw t0,t0,-8 # 200bff8 <_start-0x7dff4008> + 8000009c: 0002b403 ld s0,0(t0) + 800000a0: 10000313 li t1,256 + 800000a4: fff30313 addi t1,t1,-1 + 800000a8: fe031ee3 bnez t1,800000a4 <_start+0xa4> + 800000ac: 0002b303 ld t1,0(t0) + 800000b0: 28647663 bgeu s0,t1,8000033c + 800000b4: 0c0002b7 lui t0,0xc000 + 800000b8: 0042829b addiw t0,t0,4 # c000004 <_start-0x73fffffc> + 800000bc: 00100313 li t1,1 + 800000c0: 0062a023 sw t1,0(t0) + 800000c4: 0002a383 lw t2,0(t0) + 800000c8: 26731a63 bne t1,t2,8000033c + 800000cc: 00400193 li gp,4 + 800000d0: 000062b7 lui t0,0x6 + 800000d4: 3002a073 csrs mstatus,t0 + 800000d8: 00300293 li t0,3 + 800000dc: d2028053 fcvt.d.w ft0,t0 + 800000e0: 020070d3 fadd.d ft1,ft0,ft0 + 800000e4: c2009353 fcvt.w.d t1,ft1,rtz + 800000e8: 00600393 li t2,6 + 800000ec: 24731863 bne t1,t2,8000033c + 800000f0: d002f053 fcvt.s.w ft0,t0 + 800000f4: 100070d3 fmul.s ft1,ft0,ft0 + 800000f8: c0009353 fcvt.w.s t1,ft1,rtz + 800000fc: 00900393 li t2,9 + 80000100: 22731e63 bne t1,t2,8000033c + 80000104: d402f053 fcvt.h.w ft0,t0 + 80000108: 040070d3 fadd.h ft1,ft0,ft0 + 8000010c: c4009353 fcvt.w.h t1,ft1,rtz + 80000110: 00600393 li t2,6 + 80000114: 22731463 bne t1,t2,8000033c + 80000118: 00009297 auipc t0,0x9 + 8000011c: ee828293 addi t0,t0,-280 # 80009000 + 80000120: 0012b427 fsd ft1,8(t0) + 80000124: 0082b107 fld ft2,8(t0) + 80000128: e2008353 fmv.x.d t1,ft1 + 8000012c: e20103d3 fmv.x.d t2,ft2 + 80000130: 20731663 bne t1,t2,8000033c + 80000134: 00500193 li gp,5 + 80000138: 00009297 auipc t0,0x9 + 8000013c: ec828293 addi t0,t0,-312 # 80009000 + 80000140: 02300313 li t1,35 + 80000144: 0062b023 sd t1,0(t0) + 80000148: 00700393 li t2,7 + 8000014c: 0072be2f amoadd.d t3,t2,(t0) + 80000150: 1fc31663 bne t1,t3,8000033c + 80000154: 0002be03 ld t3,0(t0) + 80000158: 02a00313 li t1,42 + 8000015c: 1fc31063 bne t1,t3,8000033c + 80000160: 02730e33 mul t3,t1,t2 + 80000164: 027e4e33 div t3,t3,t2 + 80000168: 1dc31a63 bne t1,t3,8000033c + 8000016c: 00900193 li gp,9 + 80000170: 00000913 li s2,0 + 80000174: 00300993 li s3,3 + +0000000080000178 : + 80000178: 00000417 auipc s0,0x0 + 8000017c: 28840413 addi s0,s0,648 # 80000400 + 80000180: 04000493 li s1,64 + +0000000080000184 : + 80000184: 000400e7 jalr s0 + 80000188: 20040413 addi s0,s0,512 + 8000018c: fff48493 addi s1,s1,-1 + 80000190: fe049ae3 bnez s1,80000184 + 80000194: fff98993 addi s3,s3,-1 + 80000198: fe0990e3 bnez s3,80000178 + 8000019c: 0c000293 li t0,192 + 800001a0: 18591e63 bne s2,t0,8000033c + 800001a4: 00a00193 li gp,10 + 800001a8: 00200993 li s3,2 + +00000000800001ac : + 800001ac: 0000b417 auipc s0,0xb + 800001b0: e5440413 addi s0,s0,-428 # 8000b000 + 800001b4: 000024b7 lui s1,0x2 + 800001b8: 00000913 li s2,0 + +00000000800001bc : + 800001bc: 013942b3 xor t0,s2,s3 + 800001c0: 00543023 sd t0,0(s0) + 800001c4: 00840413 addi s0,s0,8 + 800001c8: 00190913 addi s2,s2,1 + 800001cc: fff48493 addi s1,s1,-1 # 1fff <_start-0x7fffe001> + 800001d0: fe0496e3 bnez s1,800001bc + 800001d4: 0330000f fence rw,rw + 800001d8: 000024b7 lui s1,0x2 + +00000000800001dc : + 800001dc: ff840413 addi s0,s0,-8 + 800001e0: fff90913 addi s2,s2,-1 + 800001e4: 00043283 ld t0,0(s0) + 800001e8: 01394333 xor t1,s2,s3 + 800001ec: 14629863 bne t0,t1,8000033c + 800001f0: fff48493 addi s1,s1,-1 # 1fff <_start-0x7fffe001> + 800001f4: fe0494e3 bnez s1,800001dc + 800001f8: 000024b7 lui s1,0x2 + +00000000800001fc : + 800001fc: 00043283 ld t0,0(s0) + 80000200: 01394333 xor t1,s2,s3 + 80000204: 12629c63 bne t0,t1,8000033c + 80000208: 00840413 addi s0,s0,8 + 8000020c: 00190913 addi s2,s2,1 + 80000210: fff48493 addi s1,s1,-1 # 1fff <_start-0x7fffe001> + 80000214: fe0494e3 bnez s1,800001fc + 80000218: fff98993 addi s3,s3,-1 + 8000021c: f80998e3 bnez s3,800001ac + 80000220: 00600193 li gp,6 + 80000224: 0000a297 auipc t0,0xa + 80000228: ddc28293 addi t0,t0,-548 # 8000a000 + 8000022c: 0cf00313 li t1,207 + 80000230: 0062b023 sd t1,0(t0) + 80000234: 10000337 lui t1,0x10000 + 80000238: 0cf3031b addiw t1,t1,207 # 100000cf <_start-0x6fffff31> + 8000023c: 0062b423 sd t1,8(t0) + 80000240: 20000337 lui t1,0x20000 + 80000244: 0cf3031b addiw t1,t1,207 # 200000cf <_start-0x5fffff31> + 80000248: 0062b823 sd t1,16(t0) + 8000024c: 0062bc23 sd t1,24(t0) + 80000250: 0330000f fence rw,rw + 80000254: fff00313 li t1,-1 + 80000258: 3b031073 csrw pmpaddr0,t1 + 8000025c: 00f00313 li t1,15 + 80000260: 3a031073 csrw pmpcfg0,t1 + 80000264: 00700313 li t1,7 + 80000268: 30631073 csrw mcounteren,t1 + 8000026c: 00c2d293 srli t0,t0,0xc + 80000270: fff0031b addiw t1,zero,-1 + 80000274: 03f31313 slli t1,t1,0x3f + 80000278: 0062e2b3 or t0,t0,t1 + 8000027c: 18029073 csrw satp,t0 + 80000280: 12000073 sfence.vma + 80000284: 00000297 auipc t0,0x0 + 80000288: 02828293 addi t0,t0,40 # 800002ac + 8000028c: 34129073 csrw mepc,t0 + 80000290: 000022b7 lui t0,0x2 + 80000294: 8002829b addiw t0,t0,-2048 # 1800 <_start-0x7fffe800> + 80000298: 3002b073 csrc mstatus,t0 + 8000029c: 000012b7 lui t0,0x1 + 800002a0: 8002829b addiw t0,t0,-2048 # 800 <_start-0x7ffff800> + 800002a4: 3002a073 csrs mstatus,t0 + 800002a8: 30200073 mret + +00000000800002ac : + 800002ac: 00700193 li gp,7 + 800002b0: 00009297 auipc t0,0x9 + 800002b4: d5028293 addi t0,t0,-688 # 80009000 + 800002b8: 40000337 lui t1,0x40000 + 800002bc: 006282b3 add t0,t0,t1 + 800002c0: 0002b383 ld t2,0(t0) + 800002c4: 02a00e13 li t3,42 + 800002c8: 07c39a63 bne t2,t3,8000033c + 800002cc: 02b00393 li t2,43 + 800002d0: 0072b023 sd t2,0(t0) + 800002d4: 00009297 auipc t0,0x9 + 800002d8: d2c28293 addi t0,t0,-724 # 80009000 + 800002dc: 0002be03 ld t3,0(t0) + 800002e0: 05c39e63 bne t2,t3,8000033c + 800002e4: c00022f3 rdcycle t0 + 800002e8: 04028a63 beqz t0,8000033c + 800002ec: 00800193 li gp,8 + 800002f0: 00900d13 li s10,9 + 800002f4: 00000073 ecall + 800002f8: 0440006f j 8000033c + +00000000800002fc : + 800002fc: 342022f3 csrr t0,mcause + 80000300: 03a29e63 bne t0,s10,8000033c + 80000304: 001d8d93 addi s11,s11,1 + 80000308: 00900313 li t1,9 + 8000030c: 00628a63 beq t0,t1,80000320 + 80000310: 341022f3 csrr t0,mepc + 80000314: 00428293 addi t0,t0,4 + 80000318: 34129073 csrw mepc,t0 + 8000031c: 30200073 mret + +0000000080000320 : + 80000320: 00400293 li t0,4 + 80000324: 005d9c63 bne s11,t0,8000033c + 80000328: 600002b7 lui t0,0x60000 + 8000032c: 600d6337 lui t1,0x600d6 + 80000330: 00d3031b addiw t1,t1,13 # 600d600d <_start-0x1ff29ff3> + 80000334: 0062b023 sd t1,0(t0) # 60000000 <_start-0x20000000> + 80000338: 0000006f j 80000338 + +000000008000033c : + 8000033c: 600002b7 lui t0,0x60000 + 80000340: 00001337 lui t1,0x1 + 80000344: bad3031b addiw t1,t1,-1107 # bad <_start-0x7ffff453> + 80000348: 01431313 slli t1,t1,0x14 + 8000034c: 00336333 or t1,t1,gp + 80000350: 0062b023 sd t1,0(t0) # 60000000 <_start-0x20000000> + 80000354: 0000006f j 80000354 + 80000358: 00000013 nop + 8000035c: 00000013 nop + 80000360: 00000013 nop + 80000364: 00000013 nop + 80000368: 00000013 nop + 8000036c: 00000013 nop + 80000370: 00000013 nop + 80000374: 00000013 nop + 80000378: 00000013 nop + 8000037c: 00000013 nop + 80000380: 00000013 nop + 80000384: 00000013 nop + 80000388: 00000013 nop + 8000038c: 00000013 nop + 80000390: 00000013 nop + 80000394: 00000013 nop + 80000398: 00000013 nop + 8000039c: 00000013 nop + 800003a0: 00000013 nop + 800003a4: 00000013 nop + 800003a8: 00000013 nop + 800003ac: 00000013 nop + 800003b0: 00000013 nop + 800003b4: 00000013 nop + 800003b8: 00000013 nop + 800003bc: 00000013 nop + 800003c0: 00000013 nop + 800003c4: 00000013 nop + 800003c8: 00000013 nop + 800003cc: 00000013 nop + 800003d0: 00000013 nop + 800003d4: 00000013 nop + 800003d8: 00000013 nop + 800003dc: 00000013 nop + 800003e0: 00000013 nop + 800003e4: 00000013 nop + 800003e8: 00000013 nop + 800003ec: 00000013 nop + 800003f0: 00000013 nop + 800003f4: 00000013 nop + 800003f8: 00000013 nop + 800003fc: 00000013 nop + +0000000080000400 : + 80000400: 00190913 addi s2,s2,1 + 80000404: 00008067 ret + ... + 80000600: 00190913 addi s2,s2,1 + 80000604: 00008067 ret + ... + 80000800: 00190913 addi s2,s2,1 + 80000804: 00008067 ret + ... + 80000a00: 00190913 addi s2,s2,1 + 80000a04: 00008067 ret + ... + 80000c00: 00190913 addi s2,s2,1 + 80000c04: 00008067 ret + ... + 80000e00: 00190913 addi s2,s2,1 + 80000e04: 00008067 ret + ... + 80001000: 00190913 addi s2,s2,1 + 80001004: 00008067 ret + ... + 80001200: 00190913 addi s2,s2,1 + 80001204: 00008067 ret + ... + 80001400: 00190913 addi s2,s2,1 + 80001404: 00008067 ret + ... + 80001600: 00190913 addi s2,s2,1 + 80001604: 00008067 ret + ... + 80001800: 00190913 addi s2,s2,1 + 80001804: 00008067 ret + ... + 80001a00: 00190913 addi s2,s2,1 + 80001a04: 00008067 ret + ... + 80001c00: 00190913 addi s2,s2,1 + 80001c04: 00008067 ret + ... + 80001e00: 00190913 addi s2,s2,1 + 80001e04: 00008067 ret + ... + 80002000: 00190913 addi s2,s2,1 + 80002004: 00008067 ret + ... + 80002200: 00190913 addi s2,s2,1 + 80002204: 00008067 ret + ... + 80002400: 00190913 addi s2,s2,1 + 80002404: 00008067 ret + ... + 80002600: 00190913 addi s2,s2,1 + 80002604: 00008067 ret + ... + 80002800: 00190913 addi s2,s2,1 + 80002804: 00008067 ret + ... + 80002a00: 00190913 addi s2,s2,1 + 80002a04: 00008067 ret + ... + 80002c00: 00190913 addi s2,s2,1 + 80002c04: 00008067 ret + ... + 80002e00: 00190913 addi s2,s2,1 + 80002e04: 00008067 ret + ... + 80003000: 00190913 addi s2,s2,1 + 80003004: 00008067 ret + ... + 80003200: 00190913 addi s2,s2,1 + 80003204: 00008067 ret + ... + 80003400: 00190913 addi s2,s2,1 + 80003404: 00008067 ret + ... + 80003600: 00190913 addi s2,s2,1 + 80003604: 00008067 ret + ... + 80003800: 00190913 addi s2,s2,1 + 80003804: 00008067 ret + ... + 80003a00: 00190913 addi s2,s2,1 + 80003a04: 00008067 ret + ... + 80003c00: 00190913 addi s2,s2,1 + 80003c04: 00008067 ret + ... + 80003e00: 00190913 addi s2,s2,1 + 80003e04: 00008067 ret + ... + 80004000: 00190913 addi s2,s2,1 + 80004004: 00008067 ret + ... + 80004200: 00190913 addi s2,s2,1 + 80004204: 00008067 ret + ... + 80004400: 00190913 addi s2,s2,1 + 80004404: 00008067 ret + ... + 80004600: 00190913 addi s2,s2,1 + 80004604: 00008067 ret + ... + 80004800: 00190913 addi s2,s2,1 + 80004804: 00008067 ret + ... + 80004a00: 00190913 addi s2,s2,1 + 80004a04: 00008067 ret + ... + 80004c00: 00190913 addi s2,s2,1 + 80004c04: 00008067 ret + ... + 80004e00: 00190913 addi s2,s2,1 + 80004e04: 00008067 ret + ... + 80005000: 00190913 addi s2,s2,1 + 80005004: 00008067 ret + ... + 80005200: 00190913 addi s2,s2,1 + 80005204: 00008067 ret + ... + 80005400: 00190913 addi s2,s2,1 + 80005404: 00008067 ret + ... + 80005600: 00190913 addi s2,s2,1 + 80005604: 00008067 ret + ... + 80005800: 00190913 addi s2,s2,1 + 80005804: 00008067 ret + ... + 80005a00: 00190913 addi s2,s2,1 + 80005a04: 00008067 ret + ... + 80005c00: 00190913 addi s2,s2,1 + 80005c04: 00008067 ret + ... + 80005e00: 00190913 addi s2,s2,1 + 80005e04: 00008067 ret + ... + 80006000: 00190913 addi s2,s2,1 + 80006004: 00008067 ret + ... + 80006200: 00190913 addi s2,s2,1 + 80006204: 00008067 ret + ... + 80006400: 00190913 addi s2,s2,1 + 80006404: 00008067 ret + ... + 80006600: 00190913 addi s2,s2,1 + 80006604: 00008067 ret + ... + 80006800: 00190913 addi s2,s2,1 + 80006804: 00008067 ret + ... + 80006a00: 00190913 addi s2,s2,1 + 80006a04: 00008067 ret + ... + 80006c00: 00190913 addi s2,s2,1 + 80006c04: 00008067 ret + ... + 80006e00: 00190913 addi s2,s2,1 + 80006e04: 00008067 ret + ... + 80007000: 00190913 addi s2,s2,1 + 80007004: 00008067 ret + ... + 80007200: 00190913 addi s2,s2,1 + 80007204: 00008067 ret + ... + 80007400: 00190913 addi s2,s2,1 + 80007404: 00008067 ret + ... + 80007600: 00190913 addi s2,s2,1 + 80007604: 00008067 ret + ... + 80007800: 00190913 addi s2,s2,1 + 80007804: 00008067 ret + ... + 80007a00: 00190913 addi s2,s2,1 + 80007a04: 00008067 ret + ... + 80007c00: 00190913 addi s2,s2,1 + 80007c04: 00008067 ret + ... + 80007e00: 00190913 addi s2,s2,1 + 80007e04: 00008067 ret + ... + 80008000: 00190913 addi s2,s2,1 + 80008004: 00008067 ret + ... + 80008200: 00190913 addi s2,s2,1 + 80008204: 00008067 ret + ... diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/cpu-smoke/smoke.elf b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/cpu-smoke/smoke.elf new file mode 100644 index 0000000..a428cdf Binary files /dev/null and b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/cpu-smoke/smoke.elf differ diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/cpu-smoke/smoke.hex b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/cpu-smoke/smoke.hex new file mode 100644 index 0000000..b756dee --- /dev/null +++ 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memory_aw_bits_id; + wire [31:0] memory_aw_bits_addr; + wire [7:0] memory_aw_bits_len; + wire [2:0] memory_aw_bits_size; + wire [1:0] memory_aw_bits_burst; + wire memory_aw_bits_lock; + wire [3:0] memory_aw_bits_cache; + wire [2:0] memory_aw_bits_prot; + wire [3:0] memory_aw_bits_qos; + wire memory_w_ready; + wire memory_w_valid; + wire [127:0] memory_w_bits_data; + wire [15:0] memory_w_bits_strb; + wire memory_w_bits_last; + wire memory_b_ready; + wire memory_b_valid; + wire [3:0] memory_b_bits_id; + wire [1:0] memory_b_bits_resp; + wire memory_ar_ready; + wire memory_ar_valid; + wire [3:0] memory_ar_bits_id; + wire [31:0] memory_ar_bits_addr; + wire [7:0] memory_ar_bits_len; + wire [2:0] memory_ar_bits_size; + wire [1:0] memory_ar_bits_burst; + wire memory_ar_bits_lock; + wire [3:0] memory_ar_bits_cache; + wire [2:0] memory_ar_bits_prot; + wire [3:0] memory_ar_bits_qos; + wire memory_r_ready; + wire memory_r_valid; + wire [3:0] memory_r_bits_id; + wire [127:0] memory_r_bits_data; + wire [1:0] memory_r_bits_resp; + wire memory_r_bits_last; + wire peripherals_aw_ready; + wire peripherals_aw_valid; + wire [1:0] peripherals_aw_bits_id; + wire [30:0] peripherals_aw_bits_addr; + wire [7:0] peripherals_aw_bits_len; + wire [2:0] peripherals_aw_bits_size; + wire [1:0] peripherals_aw_bits_burst; + wire peripherals_aw_bits_lock; + wire [3:0] peripherals_aw_bits_cache; + wire [2:0] peripherals_aw_bits_prot; + wire [3:0] peripherals_aw_bits_qos; + wire peripherals_w_ready; + wire peripherals_w_valid; + wire [63:0] peripherals_w_bits_data; + wire [7:0] peripherals_w_bits_strb; + wire peripherals_w_bits_last; + wire peripherals_b_ready; + wire peripherals_b_valid; + wire [1:0] peripherals_b_bits_id; + wire [1:0] peripherals_b_bits_resp; + wire peripherals_ar_ready; + wire peripherals_ar_valid; + wire [1:0] peripherals_ar_bits_id; + wire [30:0] peripherals_ar_bits_addr; + wire [7:0] peripherals_ar_bits_len; + wire [2:0] peripherals_ar_bits_size; + wire [1:0] peripherals_ar_bits_burst; + wire peripherals_ar_bits_lock; + wire [3:0] peripherals_ar_bits_cache; + wire [2:0] peripherals_ar_bits_prot; + wire [3:0] peripherals_ar_bits_qos; + wire peripherals_r_ready; + wire peripherals_r_valid; + wire [1:0] peripherals_r_bits_id; + wire [63:0] peripherals_r_bits_data; + wire [1:0] peripherals_r_bits_resp; + wire peripherals_r_bits_last; + ToyLinuxChip dut(.*); + integer cycle_count=0; + always @(posedge clock) if (!reset) cycle_count<=cycle_count+1; + always #5 clock=~clock; + initial begin reset=1; repeat(20) @(negedge clock); reset=0; end + initial begin repeat(5000000) @(posedge clock); $fatal(1,"CPU timeout"); end + axi_smoke_memory #(.DATA_BITS(128), .ID_BITS(4), .ADDR_BITS(32), .BASE(32'h80000000), .CAPACITY(262144), .IMAGE("smoke.hex")) memory_model ( + .clock(clock), + .reset(reset), + .aw_ready(memory_aw_ready), + .aw_valid(memory_aw_valid), + .aw_bits_id(memory_aw_bits_id), + .aw_bits_addr(memory_aw_bits_addr), + .aw_bits_len(memory_aw_bits_len), + .aw_bits_size(memory_aw_bits_size), + .aw_bits_burst(memory_aw_bits_burst), + .w_ready(memory_w_ready), + .w_valid(memory_w_valid), + .w_bits_data(memory_w_bits_data), + .w_bits_strb(memory_w_bits_strb), + .w_bits_last(memory_w_bits_last), + .b_ready(memory_b_ready), + .b_valid(memory_b_valid), + .b_bits_id(memory_b_bits_id), + .b_bits_resp(memory_b_bits_resp), + .ar_ready(memory_ar_ready), + .ar_valid(memory_ar_valid), + .ar_bits_id(memory_ar_bits_id), + .ar_bits_addr(memory_ar_bits_addr), + .ar_bits_len(memory_ar_bits_len), + .ar_bits_size(memory_ar_bits_size), + .ar_bits_burst(memory_ar_bits_burst), + .r_ready(memory_r_ready), + .r_valid(memory_r_valid), + .r_bits_id(memory_r_bits_id), + .r_bits_data(memory_r_bits_data), + .r_bits_resp(memory_r_bits_resp), + .r_bits_last(memory_r_bits_last) + ); + axi_smoke_memory #(.DATA_BITS(64), .ID_BITS(2), .ADDR_BITS(31), .BASE(32'h60000000), .CAPACITY(4096), .MONITOR(1), .TEST_LABEL("whole Toy CPU smoke")) peripherals_model ( + .clock(clock), + .reset(reset), + .aw_ready(peripherals_aw_ready), + .aw_valid(peripherals_aw_valid), + .aw_bits_id(peripherals_aw_bits_id), + .aw_bits_addr(peripherals_aw_bits_addr), + .aw_bits_len(peripherals_aw_bits_len), + .aw_bits_size(peripherals_aw_bits_size), + .aw_bits_burst(peripherals_aw_bits_burst), + .w_ready(peripherals_w_ready), + .w_valid(peripherals_w_valid), + .w_bits_data(peripherals_w_bits_data), + .w_bits_strb(peripherals_w_bits_strb), + .w_bits_last(peripherals_w_bits_last), + .b_ready(peripherals_b_ready), + .b_valid(peripherals_b_valid), + .b_bits_id(peripherals_b_bits_id), + .b_bits_resp(peripherals_b_bits_resp), + .ar_ready(peripherals_ar_ready), + .ar_valid(peripherals_ar_valid), + .ar_bits_id(peripherals_ar_bits_id), + .ar_bits_addr(peripherals_ar_bits_addr), + .ar_bits_len(peripherals_ar_bits_len), + .ar_bits_size(peripherals_ar_bits_size), + .ar_bits_burst(peripherals_ar_bits_burst), + .r_ready(peripherals_r_ready), + .r_valid(peripherals_r_valid), + .r_bits_id(peripherals_r_bits_id), + .r_bits_data(peripherals_r_bits_data), + .r_bits_resp(peripherals_r_bits_resp), + .r_bits_last(peripherals_r_bits_last) + ); + final $display("MEASURE cycles=%0d memory_reads=%0d memory_writes=%0d", cycle_count, memory_model.read_bursts, memory_model.write_bursts); +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/cpu-smoke/verilator-build.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/cpu-smoke/verilator-build.log new file mode 100644 index 0000000..52bd492 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/cpu-smoke/verilator-build.log @@ -0,0 +1,2123 @@ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 31 | module NonSyncResetSynchronizerPrimitiveShiftReg_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ + ... For warning description see https://verilator.org/warn/TIMESCALEMOD?v=5.050 + ... Use "/* verilator lint_off TIMESCALEMOD */" and lint_on around source to disable this message. +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:48:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 48 | module SynchronizerShiftReg_w1_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:61:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 61 | module IntSyncAsyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:74:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 74 | module AsyncResetRegVec_w1_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 103 | module IntSyncCrossingSource_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:118:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 118 | module FixedClockBroadcast_3( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:139:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 139 | module TLMonitor( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:987:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 987 | module TLMonitor_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:2434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 2434 | module TLXbar_sbus_i2_o3_a32d128s3k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:3195:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3195 | module TLMonitor_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4151 | module Repeater_TLBundleA_a28d128s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4218 | module TLWidthWidget16( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4386 | module TLInterconnectCoupler_sbus_to_bus_named_cbus( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4478:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4478 | module ram_2x58( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4497:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4497 | module Queue2_AXI4BundleAW( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4581:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4581 | module ram_2x73( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4600:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4600 | module Queue2_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4657:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4657 | module ram_2x4( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4676:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4676 | module Queue2_AXI4BundleB( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4729:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4729 | module Queue2_AXI4BundleAR( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4813:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4813 | module ram_2x69( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4832:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4832 | module Queue2_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4891:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4891 | module AXI4Buffer( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5067:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5067 | module ram_2x8( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5086:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5086 | module Queue2_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5143:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5143 | module Queue1_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5178 | module AXI4UserYanker( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5540:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5540 | module ram_8x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5559:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5559 | module Queue8_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5631 | module AXI4Deinterleaver( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:6073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6073 | module AXI4IdIndexer( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:6219:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6219 | module TLMonitor_3( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7048:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7048 | module Queue1_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7082:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7082 | module Queue1_AXI4BundleARW( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7148:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7148 | module TLToAXI4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7529:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7529 | module TLMonitor_4( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8396:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8396 | module Repeater_TLBundleA_a31d128s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8463 | module TLWidthWidget16_2( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8623:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8623 | module TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:9400:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 9400 | module SystemBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10050 | module FixedClockBroadcast_4( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10073 | module TLMonitor_5( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10975:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10975 | module TLXbar_cbus_out_i1_o4_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:11288:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +11288 | module TLMonitor_6( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12202:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12202 | module ram_2x114( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12221 | module Queue2_TLBundleA_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12301 | module ram_2x79( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12320:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12320 | module Queue2_TLBundleD_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12399:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12399 | module TLBuffer_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12534:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12534 | module TLMonitor_7( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:13449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13449 | module TLAtomicAutomata_cbus( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:13973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13973 | module TLMonitor_8( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14799 | module Queue1_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14846:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14846 | module TLError( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14953 | module TLMonitor_9( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15857 | module ram_2x100( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15876:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15876 | module Queue2_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15955:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15955 | module Queue2_TLBundleD_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16028 | module TLBuffer_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16155 | module ErrorDeviceWrapper( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16258 | module TLMonitor_10( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17017:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17017 | module Repeater_TLBundleA_a26d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17081:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17081 | module TLFragmenter_CLINT( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17261:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17261 | module TLInterconnectCoupler_cbus_to_clint( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17336:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17336 | module TLMonitor_11( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18106:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18106 | module Repeater_TLBundleA_a28d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18170:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18170 | module TLFragmenter_PLIC( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18350 | module TLInterconnectCoupler_cbus_to_plic( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18425:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18425 | module TLMonitor_12( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19040 | module Repeater_TLBundleA_a17d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19104:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19104 | module TLFragmenter_bootrom( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19263:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19263 | module TLInterconnectCoupler_cbus_to_bootrom( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19330:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19330 | module PeripheryBus_cbus( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19882 | module TLMonitor_13( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20610:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20610 | module ProbePicker( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20688:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20688 | module ram_2x10( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20707:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20707 | module Queue2_BundleMap_6( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20764:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20764 | module AXI4UserYanker_1( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:21713:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21713 | module AXI4IdIndexer_1( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:21859:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21859 | module TLMonitor_14( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22587:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22587 | module Queue1_AXI4BundleW_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22621 | module Queue1_AXI4BundleARW_1( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22687:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22687 | module TLToAXI4_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:23555:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +23555 | module TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:24031:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24031 | module MemoryBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:24349:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24349 | module TLMonitor_15( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25732:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25732 | module BroadcastFilter( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25756:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25756 | module ram_4x144( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25775:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25775 | module Queue4_TLBroadcastData( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25828:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25828 | module TLBroadcastTracker( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25964:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25964 | module TLBroadcastTracker_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:26100:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26100 | module TLBroadcast( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:26686:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26686 | module TLMonitor_16( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27414 | module BankBinder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27491:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27491 | module CoherenceManagerWrapper( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27669:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27669 | module TLMonitor_17( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29229:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29229 | module TLMonitor_18( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29635:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29635 | module TLXbar_MasterXbar_BBTile_i2_o1_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29898 | module IntXbar_i4_o1( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29918:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29918 | module WritebackUnit( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30014:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30014 | module ProbeUnit( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30154:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30154 | module Arbiter1_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30168:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30168 | module Arbiter1_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30191 | module Arbiter1_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30214 | module Arbiter1_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30249:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30249 | module Arbiter1_Bool( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30258 | module ram_16x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30277:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30277 | module Queue16_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30360:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30360 | module Queue1_TLBundleE_a32d128s1k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30388:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30388 | module MSHR( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30835:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30835 | module Arbiter1_HellaCacheResp( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30879:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30879 | module IOMSHR( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31790:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31790 | module sdq_17x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31809 | module MSHRFile( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32350 | module OptimizationBarrier_TLBEntryData( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32406:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32406 | module PMPChecker_s3( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32691:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32691 | module PMAChecker( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32731:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32731 | module DTLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:35923:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35923 | module L1MetadataArray( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:35990:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35990 | module Arbiter5_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36023:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36023 | module Arbiter2_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36055 | module DataArray( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36151 | module Arbiter4_L1DataReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36180:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36180 | module Arbiter2_L1DataWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36206:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36206 | module AMOALU( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36248:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36248 | module MaxPeriodFibonacciLFSR( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36342:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36342 | module Arbiter2_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36377:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36377 | module NonBlockingDCache( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:37660:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37660 | module ICache( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:37914:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37914 | module ShiftQueue( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:38054:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38054 | module PMPChecker_s2( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:38215:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38215 | module ITLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:41129:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41129 | module Frontend( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:41494:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41494 | module TLMonitor_19( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:42301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +42301 | module TLMonitor_20( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43108:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43108 | module TLXbar_i2_o1_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43343 | module TLMonitor_21( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43851:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43851 | module ram_2x116( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43870:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43870 | module Queue2_TLBundleA_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43947:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43947 | module ram_2x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43966:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43966 | module Queue2_TLBundleD_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44045:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44045 | module TLBuffer_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44158:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44158 | module TLMonitor_22( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44783 | module TLBuffer_a32d64s1k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44892:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44892 | module TLMonitor_23( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:45699:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45699 | module Repeater_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:45766:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45766 | module TLWidthWidget8_4( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46074:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46074 | module TLMonitor_24( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46882 | module ram_2x117( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46901:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46901 | module Queue2_TLBundleA_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46981:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46981 | module ram_2x78( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47000:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47000 | module Queue2_TLBundleD_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47079:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47079 | module TLBuffer_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47214 | module HellaCacheArbiter( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47381 | module Arbiter3_Valid_PTWReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47419:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47419 | module OptimizationBarrier_UInt( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47427 | module OptimizationBarrier_PTE( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47459 | module PTW( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:48434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +48434 | module FPUDecoder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49794:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49794 | module CompareRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49824:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49824 | module RecFNToIN_e11_s53_i64( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49873:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49873 | module RecFNToIN_e11_s53_i32( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49912:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49912 | module FPToInt( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50375:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50375 | module RoundAnyRawFNToRecFN_ie7_is64_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50410:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50410 | module PipelinedINToRecFN( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50513:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50513 | module RoundAnyRawFNToRecFN_ie7_is64_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50539 | module PipelinedINToRecFN_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50614 | module RoundAnyRawFNToRecFN_ie7_is64_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50642:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50642 | module PipelinedINToRecFN_2( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50717 | module IntToFP( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51072:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51072 | module RoundAnyRawFNToRecFN_ie11_is53_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51199:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51199 | module RecFNToRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51221 | module RoundAnyRawFNToRecFN_ie11_is53_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51321:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51321 | module RecFNToRecFN_1( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51343 | module FPToFP( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51469:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51469 | module MulAddRecFNToRaw_preMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51569 | module MulAddRecFNToRaw_postMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51822:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51822 | module RoundAnyRawFNToRecFN_ie11_is55_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51953 | module RoundAnyRawFNToRecFN_ie11_is55_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52060:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52060 | module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52194:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52194 | module SharedMulAddRecFNPipe( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52551:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52551 | module FPUSharedFMAPipe( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52682:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52682 | module DivSqrtRawFN_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52852:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52852 | module DivSqrtRecFMToRaw_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52907:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52907 | module RoundAnyRawFNToRecFN_ie5_is13_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53039:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53039 | module RoundRawFNToRecFN_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53068:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53068 | module DivSqrtRecFM_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53128:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53128 | module DivSqrtRawFN_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53297:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53297 | module DivSqrtRecFMToRaw_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53352:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53352 | module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53456:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53456 | module RoundRawFNToRecFN_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53485:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53485 | module DivSqrtRecFM_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53545:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53545 | module DivSqrtRawFN_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53715:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53715 | module DivSqrtRecFMToRaw_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53770:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53770 | module RoundRawFNToRecFN_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53799 | module DivSqrtRecFM_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53860:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53860 | module regfile_32x65( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53905:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53905 | module FPU( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:54820:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +54820 | module RVCExpander( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:55183:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55183 | module IBuf( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:55307:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55307 | module CSRFile( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:57223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57223 | module RocketALU( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:57809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57809 | module MulDiv( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:58107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58107 | module Arbiter3_LLWB( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:58125:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58125 | module rf_31x64( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:58149:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58149 | module RocketBB( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62838:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62838 | module GlobalDecoder( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62928:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62928 | module BankAliasTable( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:64252:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64252 | module BankScoreboard( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:64627:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64627 | module GlobalROB( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68674:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68674 | module Arbiter3_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68717 | module ram_16x4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68736:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68736 | module Queue16_UInt4( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68782:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68782 | module SubROB( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:69357:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69357 | module Arbiter1_SubRobRow( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:69722:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69722 | module GlobalScheduler( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:70973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +70973 | module BootRom( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:71013:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71013 | module Frontend_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:71637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71637 | module PE( + | ^~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:71656:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71656 | module AlwaysOutTransposer( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72411:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72411 | module MacUnit( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72426:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72426 | module PE_64( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72524:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72524 | module Tile( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72571:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72571 | module Mesh( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76050 | module TagQueue( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76191 | module ram_6x7( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76210:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76210 | module Queue6_TagWithIdAndTotalRows( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76271:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76271 | module MeshWithDelays( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77318:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77318 | module ram_data_8x64( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77337 | module Queue8_SramReadResp( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77385:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77385 | module GemminiExCtrl( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79354:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79354 | module LoopMatmulUnroller( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79637 | module LoopConvAddrGen( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79690:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79690 | module LoopConvUnroller( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:80113:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80113 | module LoopCmdEncoder( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:80402:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80402 | module Arbiter2_LoopCmd( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:80598:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80598 | module GemminiBall( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:81783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81783 | module RRArbiter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:81857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81857 | module CmdRouter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:81985:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81985 | module BallCyclePMC( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:82095:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82095 | module BBus( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:82898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82898 | module BallDomainDecoder( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83028 | module ram_4x281( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83047:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83047 | module Queue4_BallReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83178 | module Arbiter1_BallRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83198:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83198 | module BallReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83328:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83328 | module BallDomain( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84141:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84141 | module MemDomainDecoder( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84300:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84300 | module ram_4x158( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84319:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84319 | module Queue4_MemReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84421:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84421 | module Arbiter3_MemRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84463 | module MemReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84631 | module MemLoader( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84869:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84869 | module MemStorer( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85122:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85122 | module MemCyclePMC( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85241:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85241 | module TLB( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85621 | module RRArbiter_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85649:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85649 | module BBTLBCluster( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85777 | module StreamReader( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86142:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86142 | module StreamWriter( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86223 | module ZeroLineGenerator( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86264:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86264 | module MemConfiger( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86433:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86433 | module RRArbiter_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86465:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86465 | module MemGroupQueryArbiter( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86543:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86543 | module MemFrontend( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87160 | module MemMidend( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87621 | module SramBank( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87672:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87672 | module AccPipe( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87781 | module PrivateMemBackend( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:90777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +90777 | module MemBackend( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:91055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91055 | module MemDomain( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:91973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91973 | module Queue1_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92008:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92008 | module GpDomain( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92040 | module ram_8x21( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92059 | module Queue8_BuckyballAccelerator_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92123:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92123 | module BuckyballAccelerator( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93569 | module Queue3_UInt2( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93614 | module SimpleHellaCacheIFReplayQueue( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93667:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93667 | module Arbiter2_HellaCacheReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93678:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93678 | module SimpleHellaCacheIF( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93768:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93768 | module BarrierUnit( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93785:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93785 | module BBTile( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:95579:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +95579 | module TLMonitor_25( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:96427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +96427 | module TLMonitor_26( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98184:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98184 | module ram_2x189( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98203:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98203 | module Queue2_TLBundleA_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98283:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98283 | module ram_2x142( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98302:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98302 | module Queue2_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98381 | module Queue2_TLBundleA_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98459 | module Queue2_TLBundleD_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98539 | module ram_2x60( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98558:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98558 | module Queue2_TLBundleB_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98622:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98622 | module ram_2x173( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98641:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98641 | module Queue2_TLBundleC_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98716:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98716 | module ram_sink_2x1( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98735:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98735 | module Queue2_TLBundleE_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98781 | module TLBuffer_a32d128s2k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99162:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99162 | module IntSyncSyncCrossingSink_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99173:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99173 | module IntSyncSyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99181:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99181 | module TilePRCIDomain( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99589:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99589 | module BundleBridgeNexus_UInt1_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99597:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99597 | module TLMonitor_27( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100216:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100216 | module CLINT( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100337 | module AsyncResetRegVec_w2_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100366:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100366 | module IntSyncCrossingSource_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100386 | module CLINTClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100449 | module TLMonitor_28( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101080:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101080 | module LevelGateway( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101099:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101099 | module PLICFanIn( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101111:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101111 | module Queue1_RegMapperInput_i23_m8( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101160 | module TLPLIC( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101389:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101389 | module PLICClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101452:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101452 | module TLMonitor_29( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101973 | module TLROM( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:102530:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102530 | module bootromClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:102569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102569 | module ToyLinuxSystem( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103817:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103817 | module ToyLinuxChip( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103984:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103984 | module tag_array( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104007:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104007 | module array_0_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104034:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104034 | module array_0_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104059 | module array_2_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104084:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104084 | module array_2_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104109:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104109 | module bbtile_icache_tag_array( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104132:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104132 | module bbtile_icache_data_arrays_0( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104155 | module bbtile_icache_data_arrays_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104176:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104176 | module bbtile_icache_data_arrays_2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104197:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104197 | module bbtile_icache_data_arrays_3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104218 | module robOperands( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104243:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104243 | module sram( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104268:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104268 | module mem( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104301 | module plusarg_reader #( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104326:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104326 | module ITraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104404:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104404 | module FpgaDspMac(input [7:0] a, b, input [19:0] c, output [19:0] y); + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104414 | module PMCTraceDPI( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104464:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104464 | module MemPMCTraceDPI( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104514:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104514 | module MTraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:1:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 1 | module tag_array_ext( input [4:0] RW0_addr, + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 19 | module array_0_0_ext( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:37:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 37 | module bbtile_icache_tag_array_ext( input [5:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:55:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 55 | module bbtile_icache_data_arrays_0_ext( input [7:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:73:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 73 | module robOperands_ext( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:90:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 90 | module sram_ext( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 107 | module mem_ext( input [9:0] RW0_addr, + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:3:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3 | module axi_smoke_memory #( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:52:20: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'addr' generates 31 bits. + : ... note: In instance 'tb.peripherals_model' + 52 | offset=(addr & ~(LANES-1))-BASE; + | ^ + ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=5.050 + ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:78:28: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'write_addr' generates 31 bits. + : ... note: In instance 'tb.peripherals_model' + 78 | offset=(write_addr & ~(LANES-1))-BASE; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:86:26: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'h600d600d' generates 64 bits. + : ... note: In instance 'tb.memory_model' + 86 | if (w_bits_data==64'h600d600d) begin + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:91:66: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff' generates 64 bits. + : ... note: In instance 'tb.memory_model' + 91 | $fatal(1,"CPU smoke failed at stage %0d",w_bits_data & 64'hffff); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:90:28: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff0000' generates 64 bits. + : ... note: In instance 'tb.memory_model' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:90:43: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'hbad00000' generates 64 bits. + : ... note: In instance 'tb.memory_model' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^~ +make: Entering directory '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/obj' +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_timing.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_timing.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_threads.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_threads.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb__pch.h -o Vtb__pch.h.fast.gch +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb__pch.h -o Vtb__pch.h.slow.gch +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb__ConstPool__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__1__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__2__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__3__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb__Syms__Slow.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__0.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__1.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__2.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__3.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__4.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__5.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__6.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__7.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__8.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__9.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb__main.cpp +g++ verilated.o verilated_timing.o verilated_threads.o Vtb__ALL.a -pthread -lpthread -latomic -o Vtb +rm Vtb__ALL.verilator_deplist.tmp +make: Leaving directory '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/cpu-smoke/obj' +- V e r i l a t i o n R e p o r t: Verilator 5.050 2026-07-01 rev v5.050 +- Verilator: Built from 15.468 MB sources in 346 modules, into 23.746 MB in 19 C++ files needing 0.019 MB +- Verilator: Walltime 14.009 s (elab=0.529, cvt=3.214, bld=9.707); cpu 4.552 s on 8 threads; allocated 561.750 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/dma-beat64/simulation/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/dma-beat64/simulation/RESULT.json new file mode 100644 index 0000000..9aee7b2 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/dma-beat64/simulation/RESULT.json @@ -0,0 +1,10 @@ +{ + "result": "PASS", + "test_label": "whole Toy unaligned DMA 64 bit beats", + "core_rtl_sha256": "31e7e07f94d08208dbb564edf9546240df26ff834935bfb646b71b541d875fb9", + "test_binary_sha256": "082965476d4dcc98cc556b8f79fa2fdf659cea501665e207d04349d40469e9d2", + "cycles_including_boot": 1879410, + "memory_read_bursts": 2249, + "memory_write_bursts": 1790, + "linux_boot_tested": false +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/dma-beat64/simulation/simulation.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/dma-beat64/simulation/simulation.log new file mode 100644 index 0000000..bb9022c --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/dma-beat64/simulation/simulation.log @@ -0,0 +1,7 @@ +CPU status = 00000000600d600d +PASS whole Toy unaligned DMA 64 bit beats +- /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:88: Verilog $finish +MEASURE cycles=1879410 memory_reads=2249 memory_writes=1790 +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 19ms; walltime 15.300 s; speed 1.228 ms/s +- Verilator: cpu 15.297 s on 1 threads; allocated 8 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/dma-beat64/simulation/smoke.bin b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/dma-beat64/simulation/smoke.bin new file mode 100644 index 0000000..c678df9 Binary files /dev/null and b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/dma-beat64/simulation/smoke.bin differ diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/dma-beat64/simulation/smoke.disasm b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/dma-beat64/simulation/smoke.disasm new file mode 100644 index 0000000..c07b598 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/dma-beat64/simulation/smoke.disasm @@ -0,0 +1,208 @@ + +/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/smoke.elf: file format elf64-littleriscv + + +Disassembly of section .text: + +0000000080000000 <_start>: + 80000000: 00002137 lui sp,0x2 + 80000004: 0011011b addiw sp,sp,1 # 2001 <_start-0x7fffdfff> + 80000008: 01211113 slli sp,sp,0x12 + 8000000c: ff010113 addi sp,sp,-16 + 80000010: 00000297 auipc t0,0x0 + 80000014: 04c28293 addi t0,t0,76 # 8000005c + 80000018: 30529073 csrw mtvec,t0 + 8000001c: 30401073 csrw mie,zero + 80000020: 30201073 csrw medeleg,zero + 80000024: 0001e2b7 lui t0,0x1e + 80000028: 3002a073 csrs mstatus,t0 + 8000002c: 00000097 auipc ra,0x0 + 80000030: 050080e7 jalr 80(ra) # 8000007c
+ 80000034: 600002b7 lui t0,0x60000 + 80000038: 600d6337 lui t1,0x600d6 + 8000003c: 00d3031b addiw t1,t1,13 # 600d600d <_start-0x1ff29ff3> + 80000040: 00050a63 beqz a0,80000054 + 80000044: 00001337 lui t1,0x1 + 80000048: bad3031b addiw t1,t1,-1107 # bad <_start-0x7ffff453> + 8000004c: 01431313 slli t1,t1,0x14 + 80000050: 00a36333 or t1,t1,a0 + +0000000080000054 : + 80000054: 0062b023 sd t1,0(t0) # 60000000 <_start-0x20000000> + 80000058: 0000006f j 80000058 + +000000008000005c : + 8000005c: 342023f3 csrr t2,mcause + 80000060: 600002b7 lui t0,0x60000 + 80000064: 000bb337 lui t1,0xbb + 80000068: d0f3031b addiw t1,t1,-753 # bad0f <_start-0x7ff452f1> + 8000006c: 00c31313 slli t1,t1,0xc + 80000070: 00736333 or t1,t1,t2 + 80000074: 0062b023 sd t1,0(t0) # 60000000 <_start-0x20000000> + 80000078: 0000006f j 80000078 + +000000008000007c
: + 8000007c: 7175 addi sp,sp,-144 + 8000007e: 479d li a5,7 + 80000080: e122 sd s0,128(sp) + 80000082: fca6 sd s1,120(sp) + 80000084: 0900 addi s0,sp,144 + 80000086: f8ca sd s2,112(sp) + 80000088: f4ce sd s3,104(sp) + 8000008a: ecd6 sd s5,88(sp) + 8000008c: e4de sd s7,72(sp) + 8000008e: fc66 sd s9,56(sp) + 80000090: f86a sd s10,48(sp) + 80000092: f46e sd s11,40(sp) + 80000094: e506 sd ra,136(sp) + 80000096: f0d2 sd s4,96(sp) + 80000098: e8da sd s6,80(sp) + 8000009a: e0e2 sd s8,64(sp) + 8000009c: 1782 slli a5,a5,0x20 + 8000009e: 078d addi a5,a5,3 + 800000a0: 4685 li a3,1 + 800000a2: f8f43023 sd a5,-128(s0) + 800000a6: 02069793 slli a5,a3,0x20 + 800000aa: f6f43c23 sd a5,-136(s0) + 800000ae: 6785 lui a5,0x1 + 800000b0: 17f5 addi a5,a5,-3 # ffd <_start-0x7ffff003> + 800000b2: 597d li s2,-1 + 800000b4: f8f42423 sw a5,-120(s0) + 800000b8: f7840d93 addi s11,s0,-136 + 800000bc: 01995913 srli s2,s2,0x19 + 800000c0: 4d01 li s10,0 + 800000c2: 498d li s3,3 + 800000c4: 4c81 li s9,0 + 800000c6: 00003b97 auipc s7,0x3 + 800000ca: f3ab8b93 addi s7,s7,-198 # 80003000 + 800000ce: 00005497 auipc s1,0x5 + 800000d2: f3248493 addi s1,s1,-206 # 80005000 + 800000d6: 00003a97 auipc s5,0x3 + 800000da: f2aa8a93 addi s5,s5,-214 # 80003000 + 800000de: 000dac03 lw s8,0(s11) + 800000e2: 001cfb13 andi s6,s9,1 + 800000e6: 00001a17 auipc s4,0x1 + 800000ea: f1aa0a13 addi s4,s4,-230 # 80001000 + 800000ee: 2b05 addiw s6,s6,1 + 800000f0: 86d2 mv a3,s4 + 800000f2: 00003797 auipc a5,0x3 + 800000f6: f0e78793 addi a5,a5,-242 # 80003000 + 800000fa: 876a mv a4,s10 + 800000fc: fa500613 li a2,-91 + 80000100: 00e78023 sb a4,0(a5) + 80000104: 00c68023 sb a2,0(a3) + 80000108: 0785 addi a5,a5,1 + 8000010a: 0257071b addiw a4,a4,37 + 8000010e: 0685 addi a3,a3,1 + 80000110: fef498e3 bne s1,a5,80000100 + 80000114: 4591 li a1,4 + 80000116: 4501 li a0,0 + 80000118: 00000097 auipc ra,0x0 + 8000011c: 104080e7 jalr 260(ra) # 8000021c + 80000120: 4601 li a2,0 + 80000122: 48100793 li a5,1153 + 80000126: 40f6307b .insn 4, 0x40f6307b + 8000012a: 0000100f fence.i + 8000012e: 018b87b3 add a5,s7,s8 + 80000132: 0127f7b3 and a5,a5,s2 + 80000136: 027b1693 slli a3,s6,0x27 + 8000013a: 4725 li a4,9 + 8000013c: 8fd5 or a5,a5,a3 + 8000013e: 077a slli a4,a4,0x1e + 80000140: 42f7307b .insn 4, 0x42f7307b + 80000144: 0000100f fence.i + 80000148: 00001817 auipc a6,0x1 + 8000014c: eb880813 addi a6,a6,-328 # 80001000 + 80000150: 013807b3 add a5,a6,s3 + 80000154: 0127f7b3 and a5,a5,s2 + 80000158: 8fd5 or a5,a5,a3 + 8000015a: 20f7307b .insn 4, 0x20f7307b + 8000015e: 4781 li a5,0 + 80000160: 00f7b07b .insn 4, 0x00f7b07b + 80000164: 0330000f fence rw,rw + 80000168: 0000100f fence.i + 8000016c: 4585 li a1,1 + 8000016e: 4501 li a0,0 + 80000170: 00000097 auipc ra,0x0 + 80000174: 0ac080e7 jalr 172(ra) # 8000021c + 80000178: 4601 li a2,0 + 8000017a: 40c6307b .insn 4, 0x40c6307b + 8000017e: 4130073b negw a4,s3 + 80000182: 005b161b slliw a2,s6,0x5 + 80000186: a019 j 8000018c + 80000188: 074a8463 beq s5,s4,800001f0 + 8000018c: 0a500793 li a5,165 + 80000190: 02074663 bltz a4,800001bc + 80000194: 02c747bb divw a5,a4,a2 + 80000198: 0097a593 slti a1,a5,9 + 8000019c: 02c766bb remw a3,a4,a2 + 800001a0: c5a9 beqz a1,800001ea + 800001a2: 0206a593 slti a1,a3,32 + 800001a6: c1b1 beqz a1,800001ea + 800001a8: 02fb07bb mulw a5,s6,a5 + 800001ac: 0057979b slliw a5,a5,0x5 + 800001b0: 018787bb addw a5,a5,s8 + 800001b4: 9fb5 addw a5,a5,a3 + 800001b6: 97de add a5,a5,s7 + 800001b8: 0007c783 lbu a5,0(a5) + 800001bc: 000a4683 lbu a3,0(s4) + 800001c0: 2705 addiw a4,a4,1 + 800001c2: 0a05 addi s4,s4,1 + 800001c4: fcf682e3 beq a3,a5,80000188 + 800001c8: 001c851b addiw a0,s9,1 + 800001cc: 60aa ld ra,136(sp) + 800001ce: 640a ld s0,128(sp) + 800001d0: 74e6 ld s1,120(sp) + 800001d2: 7946 ld s2,112(sp) + 800001d4: 79a6 ld s3,104(sp) + 800001d6: 7a06 ld s4,96(sp) + 800001d8: 6ae6 ld s5,88(sp) + 800001da: 6b46 ld s6,80(sp) + 800001dc: 6ba6 ld s7,72(sp) + 800001de: 6c06 ld s8,64(sp) + 800001e0: 7ce2 ld s9,56(sp) + 800001e2: 7d42 ld s10,48(sp) + 800001e4: 7da2 ld s11,40(sp) + 800001e6: 6149 addi sp,sp,144 + 800001e8: 8082 ret + 800001ea: 0a500793 li a5,165 + 800001ee: b7f9 j 800001bc + 800001f0: 001c871b addiw a4,s9,1 + 800001f4: 4695 li a3,5 + 800001f6: 02d70163 beq a4,a3,80000218 + 800001fa: 003c879b addiw a5,s9,3 + 800001fe: 02d7f7bb remuw a5,a5,a3 + 80000202: 8cba mv s9,a4 + 80000204: f7840713 addi a4,s0,-136 + 80000208: 0d91 addi s11,s11,4 + 8000020a: 2d4d addiw s10,s10,19 + 8000020c: 8b9d andi a5,a5,7 + 8000020e: 078a slli a5,a5,0x2 + 80000210: 97ba add a5,a5,a4 + 80000212: 0007a983 lw s3,0(a5) + 80000216: b5e1 j 800000de + 80000218: 4501 li a0,0 + 8000021a: bf4d j 800001cc + +000000008000021c : + 8000021c: 1141 addi sp,sp,-16 + 8000021e: e022 sd s0,0(sp) + 80000220: e406 sd ra,8(sp) + 80000222: 0800 addi s0,sp,16 + 80000224: 47bd li a5,15 + 80000226: 00a7fa63 bgeu a5,a0,8000023a + 8000022a: 00000717 auipc a4,0x0 + 8000022e: 02e73703 ld a4,46(a4) # 80000258 + 80000232: 600007b7 lui a5,0x60000 + 80000236: e398 sd a4,0(a5) + 80000238: a001 j 80000238 + 8000023a: 02051793 slli a5,a0,0x20 + 8000023e: 60a2 ld ra,8(sp) + 80000240: 6402 ld s0,0(sp) + 80000242: 01e7d513 srli a0,a5,0x1e + 80000246: 00005797 auipc a5,0x5 + 8000024a: dba78793 addi a5,a5,-582 # 80005000 + 8000024e: 97aa add a5,a5,a0 + 80000250: c38c sw a1,0(a5) + 80000252: 0141 addi sp,sp,16 + 80000254: 8082 ret diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/dma-beat64/simulation/smoke.elf b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/dma-beat64/simulation/smoke.elf new file mode 100644 index 0000000..54540c6 Binary files /dev/null and b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/dma-beat64/simulation/smoke.elf differ diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/dma-beat64/simulation/smoke.hex b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/dma-beat64/simulation/smoke.hex new file mode 100644 index 0000000..b137138 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/dma-beat64/simulation/smoke.hex @@ -0,0 +1,608 @@ +37 +21 +00 +00 +1b +01 +11 +00 +13 +11 +21 +01 +13 +01 +01 +ff +97 +02 +00 +00 +93 +82 +c2 +04 +73 +90 +52 +30 +73 +10 +40 +30 +73 +10 +20 +30 +b7 +e2 +01 +00 +73 +a0 +02 +30 +97 +00 +00 +00 +e7 +80 +00 +05 +b7 +02 +00 +60 +37 +63 +0d +60 +1b +03 +d3 +00 +63 +0a +05 +00 +37 +13 +00 +00 +1b +03 +d3 +ba +13 +13 +43 +01 +33 +63 +a3 +00 +23 +b0 +62 +00 +6f +00 +00 +00 +f3 +23 +20 +34 +b7 +02 +00 +60 +37 +b3 +0b +00 +1b +03 +f3 +d0 +13 +13 +c3 +00 +33 +63 +73 +00 +23 +b0 +62 +00 +6f +00 +00 +00 +75 +71 +9d +47 +22 +e1 +a6 +fc +00 +09 +ca +f8 +ce +f4 +d6 +ec +de +e4 +66 +fc +6a +f8 +6e +f4 +06 +e5 +d2 +f0 +da +e8 +e2 +e0 +82 +17 +8d +07 +85 +46 +23 +30 +f4 +f8 +93 +97 +06 +02 +23 +3c +f4 +f6 +85 +67 +f5 +17 +7d +59 +23 +24 +f4 +f8 +93 +0d +84 +f7 +13 +59 +99 +01 +01 +4d +8d +49 +81 +4c +97 +3b +00 +00 +93 +8b +ab +f3 +97 +54 +00 +00 +93 +84 +24 +f3 +97 +3a +00 +00 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reg clock=0; + reg reset=0; + reg interrupt=0; + wire memory_aw_ready; + wire memory_aw_valid; + wire [3:0] memory_aw_bits_id; + wire [31:0] memory_aw_bits_addr; + wire [7:0] memory_aw_bits_len; + wire [2:0] memory_aw_bits_size; + wire [1:0] memory_aw_bits_burst; + wire memory_aw_bits_lock; + wire [3:0] memory_aw_bits_cache; + wire [2:0] memory_aw_bits_prot; + wire [3:0] memory_aw_bits_qos; + wire memory_w_ready; + wire memory_w_valid; + wire [127:0] memory_w_bits_data; + wire [15:0] memory_w_bits_strb; + wire memory_w_bits_last; + wire memory_b_ready; + wire memory_b_valid; + wire [3:0] memory_b_bits_id; + wire [1:0] memory_b_bits_resp; + wire memory_ar_ready; + wire memory_ar_valid; + wire [3:0] memory_ar_bits_id; + wire [31:0] memory_ar_bits_addr; + wire [7:0] memory_ar_bits_len; + wire [2:0] memory_ar_bits_size; + wire [1:0] memory_ar_bits_burst; + wire memory_ar_bits_lock; + wire [3:0] memory_ar_bits_cache; + wire [2:0] memory_ar_bits_prot; + wire [3:0] memory_ar_bits_qos; + wire memory_r_ready; + wire memory_r_valid; + wire [3:0] memory_r_bits_id; + wire [127:0] memory_r_bits_data; + wire [1:0] memory_r_bits_resp; + wire memory_r_bits_last; + wire peripherals_aw_ready; + wire peripherals_aw_valid; + wire [1:0] peripherals_aw_bits_id; + wire [30:0] peripherals_aw_bits_addr; + wire [7:0] peripherals_aw_bits_len; + wire [2:0] peripherals_aw_bits_size; + wire [1:0] peripherals_aw_bits_burst; + wire peripherals_aw_bits_lock; + wire [3:0] peripherals_aw_bits_cache; + wire [2:0] peripherals_aw_bits_prot; + wire [3:0] peripherals_aw_bits_qos; + wire peripherals_w_ready; + wire peripherals_w_valid; + wire [63:0] peripherals_w_bits_data; + wire [7:0] peripherals_w_bits_strb; + wire peripherals_w_bits_last; + wire peripherals_b_ready; + wire peripherals_b_valid; + wire [1:0] peripherals_b_bits_id; + wire [1:0] peripherals_b_bits_resp; + wire peripherals_ar_ready; + wire peripherals_ar_valid; + wire [1:0] peripherals_ar_bits_id; + wire [30:0] peripherals_ar_bits_addr; + wire [7:0] peripherals_ar_bits_len; + wire [2:0] peripherals_ar_bits_size; + wire [1:0] peripherals_ar_bits_burst; + wire peripherals_ar_bits_lock; + wire [3:0] peripherals_ar_bits_cache; + wire [2:0] peripherals_ar_bits_prot; + wire [3:0] peripherals_ar_bits_qos; + wire peripherals_r_ready; + wire peripherals_r_valid; + wire [1:0] peripherals_r_bits_id; + wire [63:0] peripherals_r_bits_data; + wire [1:0] peripherals_r_bits_resp; + wire peripherals_r_bits_last; + ToyLinuxChip dut(.*); + integer cycle_count=0; + always @(posedge clock) if (!reset) cycle_count<=cycle_count+1; + always #5 clock=~clock; + initial begin reset=1; repeat(20) @(negedge clock); reset=0; end + initial begin repeat(5000000) @(posedge clock); $fatal(1,"CPU timeout"); end + axi_smoke_memory #(.DATA_BITS(128), .ID_BITS(4), .ADDR_BITS(32), .BASE(32'h80000000), .CAPACITY(262144), .IMAGE("smoke.hex")) memory_model ( + .clock(clock), + .reset(reset), + .aw_ready(memory_aw_ready), + .aw_valid(memory_aw_valid), + .aw_bits_id(memory_aw_bits_id), + .aw_bits_addr(memory_aw_bits_addr), + .aw_bits_len(memory_aw_bits_len), + .aw_bits_size(memory_aw_bits_size), + .aw_bits_burst(memory_aw_bits_burst), + .w_ready(memory_w_ready), + .w_valid(memory_w_valid), + .w_bits_data(memory_w_bits_data), + .w_bits_strb(memory_w_bits_strb), + .w_bits_last(memory_w_bits_last), + .b_ready(memory_b_ready), + .b_valid(memory_b_valid), + .b_bits_id(memory_b_bits_id), + .b_bits_resp(memory_b_bits_resp), + .ar_ready(memory_ar_ready), + .ar_valid(memory_ar_valid), + .ar_bits_id(memory_ar_bits_id), + .ar_bits_addr(memory_ar_bits_addr), + .ar_bits_len(memory_ar_bits_len), + .ar_bits_size(memory_ar_bits_size), + .ar_bits_burst(memory_ar_bits_burst), + .r_ready(memory_r_ready), + .r_valid(memory_r_valid), + .r_bits_id(memory_r_bits_id), + .r_bits_data(memory_r_bits_data), + .r_bits_resp(memory_r_bits_resp), + .r_bits_last(memory_r_bits_last) + ); + axi_smoke_memory #(.DATA_BITS(64), .ID_BITS(2), .ADDR_BITS(31), .BASE(32'h60000000), .CAPACITY(4096), .MONITOR(1), .TEST_LABEL("whole Toy unaligned DMA 64 bit beats")) peripherals_model ( + .clock(clock), + .reset(reset), + .aw_ready(peripherals_aw_ready), + .aw_valid(peripherals_aw_valid), + .aw_bits_id(peripherals_aw_bits_id), + .aw_bits_addr(peripherals_aw_bits_addr), + .aw_bits_len(peripherals_aw_bits_len), + .aw_bits_size(peripherals_aw_bits_size), + .aw_bits_burst(peripherals_aw_bits_burst), + .w_ready(peripherals_w_ready), + .w_valid(peripherals_w_valid), + .w_bits_data(peripherals_w_bits_data), + .w_bits_strb(peripherals_w_bits_strb), + .w_bits_last(peripherals_w_bits_last), + .b_ready(peripherals_b_ready), + .b_valid(peripherals_b_valid), + .b_bits_id(peripherals_b_bits_id), + .b_bits_resp(peripherals_b_bits_resp), + .ar_ready(peripherals_ar_ready), + .ar_valid(peripherals_ar_valid), + .ar_bits_id(peripherals_ar_bits_id), + .ar_bits_addr(peripherals_ar_bits_addr), + .ar_bits_len(peripherals_ar_bits_len), + .ar_bits_size(peripherals_ar_bits_size), + .ar_bits_burst(peripherals_ar_bits_burst), + .r_ready(peripherals_r_ready), + .r_valid(peripherals_r_valid), + .r_bits_id(peripherals_r_bits_id), + .r_bits_data(peripherals_r_bits_data), + .r_bits_resp(peripherals_r_bits_resp), + .r_bits_last(peripherals_r_bits_last) + ); + final $display("MEASURE cycles=%0d memory_reads=%0d memory_writes=%0d", cycle_count, memory_model.read_bursts, memory_model.write_bursts); +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/dma-beat64/simulation/verilator-build.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/dma-beat64/simulation/verilator-build.log new file mode 100644 index 0000000..874c731 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/dma-beat64/simulation/verilator-build.log @@ -0,0 +1,2123 @@ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 31 | module NonSyncResetSynchronizerPrimitiveShiftReg_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ + ... For warning description see https://verilator.org/warn/TIMESCALEMOD?v=5.050 + ... Use "/* verilator lint_off TIMESCALEMOD */" and lint_on around source to disable this message. +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:48:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 48 | module SynchronizerShiftReg_w1_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:61:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 61 | module IntSyncAsyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:74:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 74 | module AsyncResetRegVec_w1_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 103 | module IntSyncCrossingSource_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:118:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 118 | module FixedClockBroadcast_3( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:139:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 139 | module TLMonitor( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:987:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 987 | module TLMonitor_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:2434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 2434 | module TLXbar_sbus_i2_o3_a32d128s3k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:3195:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3195 | module TLMonitor_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4151 | module Repeater_TLBundleA_a28d128s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4218 | module TLWidthWidget16( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4386 | module TLInterconnectCoupler_sbus_to_bus_named_cbus( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4478:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4478 | module ram_2x58( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4497:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4497 | module Queue2_AXI4BundleAW( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4581:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4581 | module ram_2x73( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4600:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4600 | module Queue2_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4657:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4657 | module ram_2x4( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4676:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4676 | module Queue2_AXI4BundleB( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4729:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4729 | module Queue2_AXI4BundleAR( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4813:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4813 | module ram_2x69( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4832:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4832 | module Queue2_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4891:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4891 | module AXI4Buffer( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5067:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5067 | module ram_2x8( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5086:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5086 | module Queue2_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5143:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5143 | module Queue1_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5178 | module AXI4UserYanker( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5540:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5540 | module ram_8x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5559:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5559 | module Queue8_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5631 | module AXI4Deinterleaver( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:6073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6073 | module AXI4IdIndexer( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:6219:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6219 | module TLMonitor_3( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7048:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7048 | module Queue1_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7082:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7082 | module Queue1_AXI4BundleARW( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7148:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7148 | module TLToAXI4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7529:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7529 | module TLMonitor_4( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8396:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8396 | module Repeater_TLBundleA_a31d128s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8463 | module TLWidthWidget16_2( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8623:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8623 | module TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:9400:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 9400 | module SystemBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10050 | module FixedClockBroadcast_4( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10073 | module TLMonitor_5( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10975:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10975 | module TLXbar_cbus_out_i1_o4_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:11288:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +11288 | module TLMonitor_6( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12202:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12202 | module ram_2x114( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12221 | module Queue2_TLBundleA_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12301 | module ram_2x79( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12320:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12320 | module Queue2_TLBundleD_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12399:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12399 | module TLBuffer_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12534:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12534 | module TLMonitor_7( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:13449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13449 | module TLAtomicAutomata_cbus( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:13973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13973 | module TLMonitor_8( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14799 | module Queue1_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14846:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14846 | module TLError( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14953 | module TLMonitor_9( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15857 | module ram_2x100( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15876:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15876 | module Queue2_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15955:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15955 | module Queue2_TLBundleD_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16028 | module TLBuffer_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16155 | module ErrorDeviceWrapper( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16258 | module TLMonitor_10( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17017:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17017 | module Repeater_TLBundleA_a26d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17081:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17081 | module TLFragmenter_CLINT( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17261:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17261 | module TLInterconnectCoupler_cbus_to_clint( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17336:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17336 | module TLMonitor_11( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18106:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18106 | module Repeater_TLBundleA_a28d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18170:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18170 | module TLFragmenter_PLIC( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18350 | module TLInterconnectCoupler_cbus_to_plic( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18425:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18425 | module TLMonitor_12( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19040 | module Repeater_TLBundleA_a17d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19104:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19104 | module TLFragmenter_bootrom( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19263:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19263 | module TLInterconnectCoupler_cbus_to_bootrom( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19330:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19330 | module PeripheryBus_cbus( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19882 | module TLMonitor_13( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20610:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20610 | module ProbePicker( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20688:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20688 | module ram_2x10( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20707:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20707 | module Queue2_BundleMap_6( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20764:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20764 | module AXI4UserYanker_1( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:21713:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21713 | module AXI4IdIndexer_1( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:21859:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21859 | module TLMonitor_14( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22587:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22587 | module Queue1_AXI4BundleW_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22621 | module Queue1_AXI4BundleARW_1( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22687:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22687 | module TLToAXI4_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:23555:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +23555 | module TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:24031:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24031 | module MemoryBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:24349:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24349 | module TLMonitor_15( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25732:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25732 | module BroadcastFilter( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25756:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25756 | module ram_4x144( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25775:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25775 | module Queue4_TLBroadcastData( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25828:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25828 | module TLBroadcastTracker( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25964:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25964 | module TLBroadcastTracker_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:26100:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26100 | module TLBroadcast( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:26686:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26686 | module TLMonitor_16( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27414 | module BankBinder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27491:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27491 | module CoherenceManagerWrapper( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27669:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27669 | module TLMonitor_17( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29229:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29229 | module TLMonitor_18( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29635:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29635 | module TLXbar_MasterXbar_BBTile_i2_o1_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29898 | module IntXbar_i4_o1( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29918:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29918 | module WritebackUnit( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30014:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30014 | module ProbeUnit( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30154:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30154 | module Arbiter1_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30168:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30168 | module Arbiter1_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30191 | module Arbiter1_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30214 | module Arbiter1_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30249:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30249 | module Arbiter1_Bool( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30258 | module ram_16x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30277:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30277 | module Queue16_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30360:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30360 | module Queue1_TLBundleE_a32d128s1k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30388:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30388 | module MSHR( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30835:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30835 | module Arbiter1_HellaCacheResp( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30879:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30879 | module IOMSHR( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31790:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31790 | module sdq_17x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31809 | module MSHRFile( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32350 | module OptimizationBarrier_TLBEntryData( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32406:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32406 | module PMPChecker_s3( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32691:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32691 | module PMAChecker( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32731:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32731 | module DTLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:35923:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35923 | module L1MetadataArray( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:35990:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35990 | module Arbiter5_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36023:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36023 | module Arbiter2_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36055 | module DataArray( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36151 | module Arbiter4_L1DataReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36180:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36180 | module Arbiter2_L1DataWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36206:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36206 | module AMOALU( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36248:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36248 | module MaxPeriodFibonacciLFSR( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36342:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36342 | module Arbiter2_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36377:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36377 | module NonBlockingDCache( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:37660:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37660 | module ICache( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:37914:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37914 | module ShiftQueue( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:38054:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38054 | module PMPChecker_s2( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:38215:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38215 | module ITLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:41129:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41129 | module Frontend( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:41494:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41494 | module TLMonitor_19( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:42301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +42301 | module TLMonitor_20( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43108:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43108 | module TLXbar_i2_o1_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43343 | module TLMonitor_21( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43851:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43851 | module ram_2x116( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43870:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43870 | module Queue2_TLBundleA_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43947:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43947 | module ram_2x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43966:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43966 | module Queue2_TLBundleD_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44045:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44045 | module TLBuffer_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44158:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44158 | module TLMonitor_22( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44783 | module TLBuffer_a32d64s1k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44892:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44892 | module TLMonitor_23( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:45699:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45699 | module Repeater_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:45766:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45766 | module TLWidthWidget8_4( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46074:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46074 | module TLMonitor_24( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46882 | module ram_2x117( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46901:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46901 | module Queue2_TLBundleA_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46981:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46981 | module ram_2x78( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47000:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47000 | module Queue2_TLBundleD_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47079:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47079 | module TLBuffer_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47214 | module HellaCacheArbiter( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47381 | module Arbiter3_Valid_PTWReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47419:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47419 | module OptimizationBarrier_UInt( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47427 | module OptimizationBarrier_PTE( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47459 | module PTW( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:48434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +48434 | module FPUDecoder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49794:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49794 | module CompareRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49824:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49824 | module RecFNToIN_e11_s53_i64( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49873:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49873 | module RecFNToIN_e11_s53_i32( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49912:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49912 | module FPToInt( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50375:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50375 | module RoundAnyRawFNToRecFN_ie7_is64_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50410:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50410 | module PipelinedINToRecFN( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50513:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50513 | module RoundAnyRawFNToRecFN_ie7_is64_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50539 | module PipelinedINToRecFN_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50614 | module RoundAnyRawFNToRecFN_ie7_is64_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50642:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50642 | module PipelinedINToRecFN_2( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50717 | module IntToFP( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51072:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51072 | module RoundAnyRawFNToRecFN_ie11_is53_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51199:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51199 | module RecFNToRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51221 | module RoundAnyRawFNToRecFN_ie11_is53_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51321:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51321 | module RecFNToRecFN_1( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51343 | module FPToFP( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51469:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51469 | module MulAddRecFNToRaw_preMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51569 | module MulAddRecFNToRaw_postMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51822:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51822 | module RoundAnyRawFNToRecFN_ie11_is55_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51953 | module RoundAnyRawFNToRecFN_ie11_is55_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52060:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52060 | module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52194:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52194 | module SharedMulAddRecFNPipe( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52551:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52551 | module FPUSharedFMAPipe( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52682:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52682 | module DivSqrtRawFN_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52852:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52852 | module DivSqrtRecFMToRaw_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52907:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52907 | module RoundAnyRawFNToRecFN_ie5_is13_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53039:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53039 | module RoundRawFNToRecFN_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53068:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53068 | module DivSqrtRecFM_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53128:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53128 | module DivSqrtRawFN_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53297:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53297 | module DivSqrtRecFMToRaw_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53352:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53352 | module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53456:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53456 | module RoundRawFNToRecFN_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53485:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53485 | module DivSqrtRecFM_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53545:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53545 | module DivSqrtRawFN_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53715:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53715 | module DivSqrtRecFMToRaw_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53770:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53770 | module RoundRawFNToRecFN_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53799 | module DivSqrtRecFM_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53860:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53860 | module regfile_32x65( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53905:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53905 | module FPU( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:54820:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +54820 | module RVCExpander( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:55183:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55183 | module IBuf( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:55307:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55307 | module CSRFile( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:57223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57223 | module RocketALU( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:57809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57809 | module MulDiv( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:58107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58107 | module Arbiter3_LLWB( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:58125:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58125 | module rf_31x64( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:58149:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58149 | module RocketBB( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62838:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62838 | module GlobalDecoder( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62928:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62928 | module BankAliasTable( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:64252:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64252 | module BankScoreboard( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:64627:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64627 | module GlobalROB( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68674:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68674 | module Arbiter3_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68717 | module ram_16x4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68736:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68736 | module Queue16_UInt4( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68782:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68782 | module SubROB( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:69357:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69357 | module Arbiter1_SubRobRow( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:69722:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69722 | module GlobalScheduler( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:70973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +70973 | module BootRom( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:71013:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71013 | module Frontend_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:71637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71637 | module PE( + | ^~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:71656:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71656 | module AlwaysOutTransposer( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72411:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72411 | module MacUnit( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72426:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72426 | module PE_64( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72524:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72524 | module Tile( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72571:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72571 | module Mesh( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76050 | module TagQueue( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76191 | module ram_6x7( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76210:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76210 | module Queue6_TagWithIdAndTotalRows( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76271:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76271 | module MeshWithDelays( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77318:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77318 | module ram_data_8x64( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77337 | module Queue8_SramReadResp( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77385:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77385 | module GemminiExCtrl( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79354:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79354 | module LoopMatmulUnroller( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79637 | module LoopConvAddrGen( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79690:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79690 | module LoopConvUnroller( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:80113:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80113 | module LoopCmdEncoder( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:80402:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80402 | module Arbiter2_LoopCmd( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:80598:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80598 | module GemminiBall( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:81783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81783 | module RRArbiter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:81857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81857 | module CmdRouter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:81985:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81985 | module BallCyclePMC( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:82095:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82095 | module BBus( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:82898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82898 | module BallDomainDecoder( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83028 | module ram_4x281( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83047:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83047 | module Queue4_BallReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83178 | module Arbiter1_BallRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83198:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83198 | module BallReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83328:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83328 | module BallDomain( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84141:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84141 | module MemDomainDecoder( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84300:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84300 | module ram_4x158( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84319:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84319 | module Queue4_MemReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84421:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84421 | module Arbiter3_MemRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84463 | module MemReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84631 | module MemLoader( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84869:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84869 | module MemStorer( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85122:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85122 | module MemCyclePMC( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85241:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85241 | module TLB( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85621 | module RRArbiter_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85649:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85649 | module BBTLBCluster( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85777 | module StreamReader( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86142:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86142 | module StreamWriter( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86223 | module ZeroLineGenerator( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86264:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86264 | module MemConfiger( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86433:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86433 | module RRArbiter_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86465:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86465 | module MemGroupQueryArbiter( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86543:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86543 | module MemFrontend( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87160 | module MemMidend( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87621 | module SramBank( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87672:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87672 | module AccPipe( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87781 | module PrivateMemBackend( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:90777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +90777 | module MemBackend( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:91055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91055 | module MemDomain( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:91973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91973 | module Queue1_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92008:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92008 | module GpDomain( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92040 | module ram_8x21( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92059 | module Queue8_BuckyballAccelerator_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92123:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92123 | module BuckyballAccelerator( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93569 | module Queue3_UInt2( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93614 | module SimpleHellaCacheIFReplayQueue( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93667:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93667 | module Arbiter2_HellaCacheReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93678:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93678 | module SimpleHellaCacheIF( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93768:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93768 | module BarrierUnit( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93785:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93785 | module BBTile( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:95579:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +95579 | module TLMonitor_25( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:96427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +96427 | module TLMonitor_26( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98184:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98184 | module ram_2x189( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98203:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98203 | module Queue2_TLBundleA_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98283:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98283 | module ram_2x142( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98302:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98302 | module Queue2_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98381 | module Queue2_TLBundleA_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98459 | module Queue2_TLBundleD_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98539 | module ram_2x60( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98558:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98558 | module Queue2_TLBundleB_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98622:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98622 | module ram_2x173( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98641:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98641 | module Queue2_TLBundleC_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98716:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98716 | module ram_sink_2x1( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98735:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98735 | module Queue2_TLBundleE_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98781 | module TLBuffer_a32d128s2k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99162:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99162 | module IntSyncSyncCrossingSink_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99173:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99173 | module IntSyncSyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99181:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99181 | module TilePRCIDomain( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99589:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99589 | module BundleBridgeNexus_UInt1_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99597:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99597 | module TLMonitor_27( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100216:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100216 | module CLINT( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100337 | module AsyncResetRegVec_w2_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100366:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100366 | module IntSyncCrossingSource_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100386 | module CLINTClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100449 | module TLMonitor_28( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101080:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101080 | module LevelGateway( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101099:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101099 | module PLICFanIn( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101111:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101111 | module Queue1_RegMapperInput_i23_m8( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101160 | module TLPLIC( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101389:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101389 | module PLICClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101452:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101452 | module TLMonitor_29( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101973 | module TLROM( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:102530:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102530 | module bootromClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:102569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102569 | module ToyLinuxSystem( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103817:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103817 | module ToyLinuxChip( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103984:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103984 | module tag_array( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104007:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104007 | module array_0_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104034:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104034 | module array_0_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104059 | module array_2_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104084:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104084 | module array_2_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104109:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104109 | module bbtile_icache_tag_array( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104132:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104132 | module bbtile_icache_data_arrays_0( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104155 | module bbtile_icache_data_arrays_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104176:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104176 | module bbtile_icache_data_arrays_2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104197:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104197 | module bbtile_icache_data_arrays_3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104218 | module robOperands( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104243:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104243 | module sram( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104268:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104268 | module mem( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104301 | module plusarg_reader #( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104326:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104326 | module ITraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104404:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104404 | module FpgaDspMac(input [7:0] a, b, input [19:0] c, output [19:0] y); + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104414 | module PMCTraceDPI( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104464:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104464 | module MemPMCTraceDPI( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104514:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104514 | module MTraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:1:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 1 | module tag_array_ext( input [4:0] RW0_addr, + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 19 | module array_0_0_ext( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:37:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 37 | module bbtile_icache_tag_array_ext( input [5:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:55:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 55 | module bbtile_icache_data_arrays_0_ext( input [7:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:73:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 73 | module robOperands_ext( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:90:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 90 | module sram_ext( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 107 | module mem_ext( input [9:0] RW0_addr, + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:3:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3 | module axi_smoke_memory #( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:52:20: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'addr' generates 31 bits. + : ... note: In instance 'tb.peripherals_model' + 52 | offset=(addr & ~(LANES-1))-BASE; + | ^ + ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=5.050 + ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:78:28: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'write_addr' generates 31 bits. + : ... note: In instance 'tb.peripherals_model' + 78 | offset=(write_addr & ~(LANES-1))-BASE; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:86:26: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'h600d600d' generates 64 bits. + : ... note: In instance 'tb.memory_model' + 86 | if (w_bits_data==64'h600d600d) begin + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:91:66: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff' generates 64 bits. + : ... note: In instance 'tb.memory_model' + 91 | $fatal(1,"CPU smoke failed at stage %0d",w_bits_data & 64'hffff); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:90:28: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff0000' generates 64 bits. + : ... note: In instance 'tb.memory_model' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:90:43: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'hbad00000' generates 64 bits. + : ... note: In instance 'tb.memory_model' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^~ +make: Entering directory '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/obj' +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_timing.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_timing.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_threads.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_threads.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb__pch.h -o Vtb__pch.h.fast.gch +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb__pch.h -o Vtb__pch.h.slow.gch +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb__ConstPool__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__1__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__2__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__3__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb__Syms__Slow.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__0.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__1.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__2.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__3.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__4.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__5.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__6.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__7.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__8.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__9.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb__main.cpp +g++ verilated.o verilated_timing.o verilated_threads.o Vtb__ALL.a -pthread -lpthread -latomic -o Vtb +rm Vtb__ALL.verilator_deplist.tmp +make: Leaving directory '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/dma-beat64/simulation/obj' +- V e r i l a t i o n R e p o r t: Verilator 5.050 2026-07-01 rev v5.050 +- Verilator: Built from 15.468 MB sources in 346 modules, into 23.746 MB in 19 C++ files needing 0.019 MB +- Verilator: Walltime 13.988 s (elab=0.546, cvt=3.331, bld=9.474); cpu 4.822 s on 8 threads; allocated 561.750 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/flash-guard-check/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/flash-guard-check/RESULT.json new file mode 100644 index 0000000..f236658 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/flash-guard-check/RESULT.json @@ -0,0 +1,56 @@ +{ + "result": "PASS_FLASH_GUARDS_NORMAL_AND_OPTIMIZED", + "physical_hardware_tested": false, + "cases": [ + { + "optimized": false, + "field": "valid", + "result": "PASS" + }, + { + "optimized": false, + "field": "result", + "result": "PASS" + }, + { + "optimized": false, + "field": "bitstream_sha256", + "result": "PASS" + }, + { + "optimized": false, + "field": "packed_payload_sha256", + "result": "PASS" + }, + { + "optimized": false, + "field": "flash_image_sha256", + "result": "PASS" + }, + { + "optimized": true, + "field": "valid", + "result": "PASS" + }, + { + "optimized": true, + "field": "result", + "result": "PASS" + }, + { + "optimized": true, + "field": "bitstream_sha256", + "result": "PASS" + }, + { + "optimized": true, + "field": "packed_payload_sha256", + "result": "PASS" + }, + { + "optimized": true, + "field": "flash_image_sha256", + "result": "PASS" + } + ] +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/flash-guard-check/normal-bitstream_sha256.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/flash-guard-check/normal-bitstream_sha256.log new file mode 100644 index 0000000..743e348 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/flash-guard-check/normal-bitstream_sha256.log @@ -0,0 +1 @@ +PASS INVALID_IMAGE_BLOCKED Prepacked flash image bitstream hash mismatch diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/flash-guard-check/normal-flash_image_sha256.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/flash-guard-check/normal-flash_image_sha256.log new file mode 100644 index 0000000..ffaee7b --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/flash-guard-check/normal-flash_image_sha256.log @@ -0,0 +1 @@ +PASS INVALID_IMAGE_BLOCKED Prepacked flash image MCS hash mismatch diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/flash-guard-check/normal-packed_payload_sha256.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/flash-guard-check/normal-packed_payload_sha256.log new file mode 100644 index 0000000..7f5ad62 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/flash-guard-check/normal-packed_payload_sha256.log @@ -0,0 +1 @@ +PASS INVALID_IMAGE_BLOCKED Prepacked flash image payload hash mismatch diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/flash-guard-check/normal-result.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/flash-guard-check/normal-result.log new file mode 100644 index 0000000..c80dd16 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/flash-guard-check/normal-result.log @@ -0,0 +1 @@ +PASS INVALID_IMAGE_BLOCKED Prepacked flash image record did not pass packing diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/flash-guard-check/normal-valid.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/flash-guard-check/normal-valid.log new file mode 100644 index 0000000..d2a3276 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/flash-guard-check/normal-valid.log @@ -0,0 +1,32 @@ +USING_PREPACKED_FLASH_IMAGE bb7752b500cc85074635eb43d325bb3d1fdb575a8b76a6f8b77248923ce55774 +{ + "status": "FAILED", + "timeout_seconds": 3600, + "bitstream_sha256": "7bf8e955913c442ddd945fafdcc42d2a593f2e19477288bd98cc008062369335", + "packed_payload_sha256": "57312732d5af9cb3785067f8032a41a0c3d023b8ebe0a6a8cde1c1dff99714ff", + "part": "mt25ql128-spi-x1_x2_x4", + "port": "OFFLINE_NO_DEVICE", + "started_at": "2026-10-13T00:57:24.638217+08:00", + "commands": [ + null, + [ + "OFFLINE_NO_VIVADO", + "-mode", + "batch", + "-source", + "/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/program_flash.tcl", + "-log", + "/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/flash-guard-check/tmpy96p8d2c/run/program.log", + "-journal", + "/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/flash-guard-check/tmpy96p8d2c/run/program.jou", + "-tclargs", + "/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/flash-guard-check/tmpy96p8d2c/run/toy_flash.mcs", + "mt25ql128-spi-x1_x2_x4", + "/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/flash-guard-check/tmpy96p8d2c/run/flash-before.bin" + ] + ], + "error": "Guard accepted the valid image", + "elapsed_seconds": 0.0, + "finished_at": "2026-10-13T00:57:24.638335+08:00" +} +PASS VALID_IMAGE_REACHED_OFFLINE_BOUNDARY diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/flash-guard-check/optimized-bitstream_sha256.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/flash-guard-check/optimized-bitstream_sha256.log new file mode 100644 index 0000000..743e348 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/flash-guard-check/optimized-bitstream_sha256.log @@ -0,0 +1 @@ +PASS INVALID_IMAGE_BLOCKED Prepacked flash image bitstream hash mismatch diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/flash-guard-check/optimized-flash_image_sha256.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/flash-guard-check/optimized-flash_image_sha256.log new file mode 100644 index 0000000..ffaee7b --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/flash-guard-check/optimized-flash_image_sha256.log @@ -0,0 +1 @@ +PASS INVALID_IMAGE_BLOCKED Prepacked flash image MCS hash mismatch diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/flash-guard-check/optimized-packed_payload_sha256.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/flash-guard-check/optimized-packed_payload_sha256.log new file mode 100644 index 0000000..7f5ad62 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/flash-guard-check/optimized-packed_payload_sha256.log @@ -0,0 +1 @@ +PASS INVALID_IMAGE_BLOCKED Prepacked flash image payload hash mismatch diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/flash-guard-check/optimized-result.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/flash-guard-check/optimized-result.log new file mode 100644 index 0000000..c80dd16 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/flash-guard-check/optimized-result.log @@ -0,0 +1 @@ +PASS INVALID_IMAGE_BLOCKED Prepacked flash image record did not pass packing diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/flash-guard-check/optimized-valid.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/flash-guard-check/optimized-valid.log new file mode 100644 index 0000000..2fd4c29 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/flash-guard-check/optimized-valid.log @@ -0,0 +1,32 @@ +USING_PREPACKED_FLASH_IMAGE bb7752b500cc85074635eb43d325bb3d1fdb575a8b76a6f8b77248923ce55774 +{ + "status": "FAILED", + "timeout_seconds": 3600, + "bitstream_sha256": "7bf8e955913c442ddd945fafdcc42d2a593f2e19477288bd98cc008062369335", + "packed_payload_sha256": "57312732d5af9cb3785067f8032a41a0c3d023b8ebe0a6a8cde1c1dff99714ff", + "part": "mt25ql128-spi-x1_x2_x4", + "port": "OFFLINE_NO_DEVICE", + "started_at": "2026-10-13T00:57:25.017820+08:00", + "commands": [ + null, + [ + "OFFLINE_NO_VIVADO", + "-mode", + "batch", + "-source", + "/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/program_flash.tcl", + "-log", + "/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/flash-guard-check/tmp42g7vqyz/run/program.log", + "-journal", + "/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/flash-guard-check/tmp42g7vqyz/run/program.jou", + "-tclargs", + "/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/flash-guard-check/tmp42g7vqyz/run/toy_flash.mcs", + "mt25ql128-spi-x1_x2_x4", + "/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/flash-guard-check/tmp42g7vqyz/run/flash-before.bin" + ] + ], + "error": "Guard accepted the valid image", + "elapsed_seconds": 0.0, + "finished_at": "2026-10-13T00:57:25.017955+08:00" +} +PASS VALID_IMAGE_REACHED_OFFLINE_BOUNDARY diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fma-check/FmaPrecisionCheck.sv b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fma-check/FmaPrecisionCheck.sv new file mode 100644 index 0000000..cab0dd9 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fma-check/FmaPrecisionCheck.sv @@ -0,0 +1,4058 @@ +// Generated by CIRCT firtool-1.62.1 +module MulAddRecFNToRaw_preMul_e5_s11( + input [1:0] io_op, + input [16:0] io_a, + io_b, + io_c, + output [10:0] io_mulAddA, + io_mulAddB, + output [21:0] io_mulAddC, + output io_toPostMul_isSigNaNAny, + io_toPostMul_isNaNAOrB, + io_toPostMul_isInfA, + io_toPostMul_isZeroA, + io_toPostMul_isInfB, + io_toPostMul_isZeroB, + io_toPostMul_signProd, + io_toPostMul_isNaNC, + io_toPostMul_isInfC, + io_toPostMul_isZeroC, + output [6:0] io_toPostMul_sExpSum, + output io_toPostMul_doSubMags, + io_toPostMul_CIsDominant, + output [3:0] io_toPostMul_CDom_CAlignDist, + output [12:0] io_toPostMul_highAlignedSigC, + output io_toPostMul_bit0AlignedSigC +); + + wire rawA_isNaN = (&(io_a[15:14])) & io_a[13]; + wire rawB_isNaN = (&(io_b[15:14])) & io_b[13]; + wire rawC_isNaN = (&(io_c[15:14])) & io_c[13]; + wire signProd = io_a[16] ^ io_b[16] ^ io_op[1]; + wire [7:0] _sExpAlignedProd_T_1 = {2'h0, io_a[15:10]} + {2'h0, io_b[15:10]} - 8'h12; + wire doSubMags = signProd ^ io_c[16] ^ io_op[0]; + wire [7:0] _sNatCAlignDist_T = _sExpAlignedProd_T_1 - {2'h0, io_c[15:10]}; + wire isMinCAlign = + ~(|(io_a[15:13])) | ~(|(io_b[15:13])) | $signed(_sNatCAlignDist_T) < 8'sh0; + wire CIsDominant = + (|(io_c[15:13])) & (isMinCAlign | _sNatCAlignDist_T[6:0] < 7'hC); + wire [5:0] CAlignDist = + isMinCAlign ? 6'h0 : _sNatCAlignDist_T[6:0] < 7'h23 ? _sNatCAlignDist_T[5:0] : 6'h23; + wire [38:0] mainAlignedSigC = + $signed($signed({doSubMags + ? {1'h1, ~(|(io_c[15:13])), ~(io_c[9:0])} + : {1'h0, |(io_c[15:13]), io_c[9:0]}, + {27{doSubMags}}}) >>> CAlignDist); + wire [16:0] reduced4CExtra_shift = $signed(17'sh10000 >>> CAlignDist[5:2]); + wire [1:0] _GEN = + {|(io_c[7:4]), |(io_c[3:0])} & {reduced4CExtra_shift[8], reduced4CExtra_shift[9]}; + assign io_mulAddA = {|(io_a[15:13]), io_a[9:0]}; + assign io_mulAddB = {|(io_b[15:13]), io_b[9:0]}; + assign io_mulAddC = mainAlignedSigC[24:3]; + assign io_toPostMul_isSigNaNAny = + rawA_isNaN & ~(io_a[9]) | rawB_isNaN & ~(io_b[9]) | rawC_isNaN & ~(io_c[9]); + assign io_toPostMul_isNaNAOrB = rawA_isNaN | rawB_isNaN; + assign io_toPostMul_isInfA = (&(io_a[15:14])) & ~(io_a[13]); + assign io_toPostMul_isZeroA = ~(|(io_a[15:13])); + assign io_toPostMul_isInfB = (&(io_b[15:14])) & ~(io_b[13]); + assign io_toPostMul_isZeroB = ~(|(io_b[15:13])); + assign io_toPostMul_signProd = signProd; + assign io_toPostMul_isNaNC = rawC_isNaN; + assign io_toPostMul_isInfC = (&(io_c[15:14])) & ~(io_c[13]); + assign io_toPostMul_isZeroC = ~(|(io_c[15:13])); + assign io_toPostMul_sExpSum = + CIsDominant ? {1'h0, io_c[15:10]} : _sExpAlignedProd_T_1[6:0] - 7'hB; + assign io_toPostMul_doSubMags = doSubMags; + assign io_toPostMul_CIsDominant = CIsDominant; + assign io_toPostMul_CDom_CAlignDist = CAlignDist[3:0]; + assign io_toPostMul_highAlignedSigC = mainAlignedSigC[37:25]; + assign io_toPostMul_bit0AlignedSigC = + doSubMags + ? (&(mainAlignedSigC[2:0])) & ~(|_GEN) + : (|(mainAlignedSigC[2:0])) | (|_GEN); +endmodule + +module MulAddRecFNToRaw_postMul_e5_s11( + input io_fromPreMul_isSigNaNAny, + io_fromPreMul_isNaNAOrB, + io_fromPreMul_isInfA, + io_fromPreMul_isZeroA, + io_fromPreMul_isInfB, + io_fromPreMul_isZeroB, + io_fromPreMul_signProd, + io_fromPreMul_isNaNC, + io_fromPreMul_isInfC, + io_fromPreMul_isZeroC, + input [6:0] io_fromPreMul_sExpSum, + input io_fromPreMul_doSubMags, + io_fromPreMul_CIsDominant, + input [3:0] io_fromPreMul_CDom_CAlignDist, + input [12:0] io_fromPreMul_highAlignedSigC, + input io_fromPreMul_bit0AlignedSigC, + input [22:0] io_mulAddResult, + input [2:0] io_roundingMode, + output io_invalidExc, + io_rawOut_isNaN, + io_rawOut_isInf, + io_rawOut_isZero, + io_rawOut_sign, + output [6:0] io_rawOut_sExp, + output [13:0] io_rawOut_sig +); + + wire roundingMode_min = io_roundingMode == 3'h2; + wire opSignC = io_fromPreMul_signProd ^ io_fromPreMul_doSubMags; + wire [12:0] _sigSum_T_3 = + io_mulAddResult[22] + ? io_fromPreMul_highAlignedSigC + 13'h1 + : io_fromPreMul_highAlignedSigC; + wire [23:0] CDom_absSigSum = + io_fromPreMul_doSubMags + ? ~{_sigSum_T_3, io_mulAddResult[21:11]} + : {1'h0, + io_fromPreMul_highAlignedSigC[12:11], + _sigSum_T_3[10:0], + io_mulAddResult[21:12]}; + wire [38:0] _CDom_mainSig_T = {15'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist; + wire [4:0] CDom_reduced4SigExtra_shift = + $signed(5'sh10 >>> ~(io_fromPreMul_CDom_CAlignDist[3:2])); + wire [24:0] notCDom_absSigSum = + _sigSum_T_3[2] + ? ~{_sigSum_T_3[1:0], io_mulAddResult[21:0], io_fromPreMul_bit0AlignedSigC} + : {_sigSum_T_3[1:0], io_mulAddResult[21:0], io_fromPreMul_bit0AlignedSigC} + + {24'h0, io_fromPreMul_doSubMags}; + wire [3:0] notCDom_normDistReduced2 = + notCDom_absSigSum[24] + ? 4'h0 + : (|(notCDom_absSigSum[23:22])) + ? 4'h1 + : (|(notCDom_absSigSum[21:20])) + ? 4'h2 + : (|(notCDom_absSigSum[19:18])) + ? 4'h3 + : (|(notCDom_absSigSum[17:16])) + ? 4'h4 + : (|(notCDom_absSigSum[15:14])) + ? 4'h5 + : (|(notCDom_absSigSum[13:12])) + ? 4'h6 + : (|(notCDom_absSigSum[11:10])) + ? 4'h7 + : (|(notCDom_absSigSum[9:8])) + ? 4'h8 + : (|(notCDom_absSigSum[7:6])) + ? 4'h9 + : (|(notCDom_absSigSum[5:4])) + ? 4'hA + : (|(notCDom_absSigSum[3:2])) ? 4'hB : 4'hC; + wire [55:0] _notCDom_mainSig_T = + {31'h0, notCDom_absSigSum} << {51'h0, notCDom_normDistReduced2, 1'h0}; + wire [8:0] notCDom_reduced4SigExtra_shift = + $signed(9'sh100 >>> ~(notCDom_normDistReduced2[3:1])); + wire notCDom_completeCancellation = _notCDom_mainSig_T[25:24] == 2'h0; + wire notNaN_isInfProd = io_fromPreMul_isInfA | io_fromPreMul_isInfB; + wire notNaN_isInfOut = notNaN_isInfProd | io_fromPreMul_isInfC; + wire notNaN_addZeros = + (io_fromPreMul_isZeroA | io_fromPreMul_isZeroB) & io_fromPreMul_isZeroC; + assign io_invalidExc = + io_fromPreMul_isSigNaNAny | io_fromPreMul_isInfA & io_fromPreMul_isZeroB + | io_fromPreMul_isZeroA & io_fromPreMul_isInfB | ~io_fromPreMul_isNaNAOrB + & notNaN_isInfProd & io_fromPreMul_isInfC & io_fromPreMul_doSubMags; + assign io_rawOut_isNaN = io_fromPreMul_isNaNAOrB | io_fromPreMul_isNaNC; + assign io_rawOut_isInf = notNaN_isInfOut; + assign io_rawOut_isZero = + notNaN_addZeros | ~io_fromPreMul_CIsDominant & notCDom_completeCancellation; + assign io_rawOut_sign = + notNaN_isInfProd & io_fromPreMul_signProd | io_fromPreMul_isInfC & opSignC + | notNaN_addZeros & ~roundingMode_min & io_fromPreMul_signProd & opSignC + | notNaN_addZeros & roundingMode_min & (io_fromPreMul_signProd | opSignC) + | ~notNaN_isInfOut & ~notNaN_addZeros + & (io_fromPreMul_CIsDominant + ? opSignC + : notCDom_completeCancellation + ? roundingMode_min + : io_fromPreMul_signProd ^ _sigSum_T_3[2]); + assign io_rawOut_sExp = + io_fromPreMul_CIsDominant + ? io_fromPreMul_sExpSum - {6'h0, io_fromPreMul_doSubMags} + : io_fromPreMul_sExpSum - {2'h0, notCDom_normDistReduced2, 1'h0}; + assign io_rawOut_sig = + io_fromPreMul_CIsDominant + ? {_CDom_mainSig_T[23:11], + (|(_CDom_mainSig_T[10:8])) + | (|({|(CDom_absSigSum[7:4]), |(CDom_absSigSum[3:0])} + & {CDom_reduced4SigExtra_shift[1], CDom_reduced4SigExtra_shift[2]})) + | (io_fromPreMul_doSubMags + ? io_mulAddResult[10:0] != 11'h7FF + : (|(io_mulAddResult[11:0])))} + : {_notCDom_mainSig_T[25:13], + (|(_notCDom_mainSig_T[12:10])) + | (|({|{|(notCDom_absSigSum[9:8]), |(notCDom_absSigSum[7:6])}, + |{|(notCDom_absSigSum[5:4]), |(notCDom_absSigSum[3:2])}, + |(notCDom_absSigSum[1:0])} + & {notCDom_reduced4SigExtra_shift[1], + notCDom_reduced4SigExtra_shift[2], + notCDom_reduced4SigExtra_shift[3]}))}; +endmodule + +module RoundAnyRawFNToRecFN_ie5_is13_oe5_os11( + input io_invalidExc, + io_in_isNaN, + io_in_isInf, + io_in_isZero, + io_in_sign, + input [6:0] io_in_sExp, + input [13:0] io_in_sig, + input [2:0] io_roundingMode, + output [16:0] io_out, + output [4:0] io_exceptionFlags +); + + wire roundingMode_near_even = io_roundingMode == 3'h0; + wire roundingMode_odd = io_roundingMode == 3'h6; + wire roundMagUp = + io_roundingMode == 3'h2 & io_in_sign | io_roundingMode == 3'h3 & ~io_in_sign; + wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> ~(io_in_sExp[5:0])); + wire [1:0] _GEN = {roundMask_shift[10], roundMask_shift[11]}; + wire _common_underflow_T_4 = roundMask_shift[18] | io_in_sig[13]; + wire [12:0] _GEN_0 = + {1'h1, + ~(roundMask_shift[7]), + ~(roundMask_shift[8]), + ~(roundMask_shift[9]), + ~_GEN, + ~(roundMask_shift[12]), + ~(roundMask_shift[13]), + ~(roundMask_shift[14]), + ~(roundMask_shift[15]), + ~(roundMask_shift[16]), + ~(roundMask_shift[17]), + ~_common_underflow_T_4}; + wire [12:0] _GEN_1 = + {roundMask_shift[7], + roundMask_shift[8], + roundMask_shift[9], + roundMask_shift[10], + roundMask_shift[11], + roundMask_shift[12], + roundMask_shift[13], + roundMask_shift[14], + roundMask_shift[15], + roundMask_shift[16], + roundMask_shift[17], + _common_underflow_T_4, + 1'h1}; + wire [12:0] _roundPosBit_T = io_in_sig[13:1] & _GEN_0 & _GEN_1; + wire [12:0] _anyRoundExtra_T = io_in_sig[12:0] & _GEN_1; + wire anyRound = (|_roundPosBit_T) | (|_anyRoundExtra_T); + wire _overflow_roundMagUp_T = roundingMode_near_even | io_roundingMode == 3'h4; + wire [12:0] roundedSig = + _overflow_roundMagUp_T & (|_roundPosBit_T) | roundMagUp & anyRound + ? {1'h0, + io_in_sig[13:2] + | {roundMask_shift[7], + roundMask_shift[8], + roundMask_shift[9], + roundMask_shift[10], + roundMask_shift[11], + roundMask_shift[12], + roundMask_shift[13], + roundMask_shift[14], + roundMask_shift[15], + roundMask_shift[16], + roundMask_shift[17], + _common_underflow_T_4}} + 13'h1 + & ~(roundingMode_near_even & (|_roundPosBit_T) & ~(|_anyRoundExtra_T) + ? {roundMask_shift[7], + roundMask_shift[8], + roundMask_shift[9], + roundMask_shift[10], + roundMask_shift[11], + roundMask_shift[12], + roundMask_shift[13], + roundMask_shift[14], + roundMask_shift[15], + roundMask_shift[16], + roundMask_shift[17], + _common_underflow_T_4, + 1'h1} + : 13'h0) + : {1'h0, + io_in_sig[13:2] + & {~(roundMask_shift[7]), + ~(roundMask_shift[8]), + ~(roundMask_shift[9]), + ~_GEN, + ~(roundMask_shift[12]), + ~(roundMask_shift[13]), + ~(roundMask_shift[14]), + ~(roundMask_shift[15]), + ~(roundMask_shift[16]), + ~(roundMask_shift[17]), + ~_common_underflow_T_4}} + | (roundingMode_odd & anyRound ? _GEN_0 & _GEN_1 : 13'h0); + wire [7:0] sRoundedExp = {io_in_sExp[6], io_in_sExp} + {6'h0, roundedSig[12:11]}; + wire common_totalUnderflow = $signed(sRoundedExp) < 8'sh8; + wire isNaNOut = io_invalidExc | io_in_isNaN; + wire commonCase = ~isNaNOut & ~io_in_isInf & ~io_in_isZero; + wire overflow = commonCase & $signed(sRoundedExp[7:4]) > 4'sh2; + wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp; + wire pegMinNonzeroMagOut = + commonCase & common_totalUnderflow & (roundMagUp | roundingMode_odd); + wire pegMaxFiniteMagOut = overflow & ~overflow_roundMagUp; + wire notNaN_isInfOut = io_in_isInf | overflow & overflow_roundMagUp; + assign io_out = + {~isNaNOut & io_in_sign, + sRoundedExp[5:0] & ~(io_in_isZero | common_totalUnderflow ? 6'h38 : 6'h0) + & ~(pegMinNonzeroMagOut ? 6'h37 : 6'h0) & {1'h1, ~pegMaxFiniteMagOut, 4'hF} + & {2'h3, ~notNaN_isInfOut, 3'h7} | {2'h0, pegMinNonzeroMagOut, 3'h0} + | (pegMaxFiniteMagOut ? 6'h2F : 6'h0) | (notNaN_isInfOut ? 6'h30 : 6'h0) + | (isNaNOut ? 6'h38 : 6'h0), + (isNaNOut | io_in_isZero | common_totalUnderflow + ? {isNaNOut, 9'h0} + : io_in_sig[13] ? roundedSig[10:1] : roundedSig[9:0]) | {10{pegMaxFiniteMagOut}}}; + assign io_exceptionFlags = + {io_invalidExc, + 1'h0, + overflow, + commonCase + & (common_totalUnderflow | anyRound & io_in_sExp[6:5] != 2'h1 + & (io_in_sig[13] ? roundMask_shift[17] : _common_underflow_T_4) + & ~(~(io_in_sig[13] ? roundMask_shift[16] : roundMask_shift[17]) + & (io_in_sig[13] ? roundedSig[12] : roundedSig[11]) & (|_roundPosBit_T) + & (_overflow_roundMagUp_T & (io_in_sig[13] ? io_in_sig[2] : io_in_sig[1]) + | roundMagUp & (io_in_sig[13] & io_in_sig[2] | (|(io_in_sig[1:0])))))), + overflow | commonCase & (common_totalUnderflow | anyRound)}; +endmodule + +module RoundRawFNToRecFN_e5_s11( + input io_invalidExc, + io_in_isNaN, + io_in_isInf, + io_in_isZero, + io_in_sign, + input [6:0] io_in_sExp, + input [13:0] io_in_sig, + input [2:0] io_roundingMode, + output [16:0] io_out, + output [4:0] io_exceptionFlags +); + + RoundAnyRawFNToRecFN_ie5_is13_oe5_os11 roundAnyRawFNToRecFN ( + .io_invalidExc (io_invalidExc), + .io_in_isNaN (io_in_isNaN), + .io_in_isInf (io_in_isInf), + .io_in_isZero (io_in_isZero), + .io_in_sign (io_in_sign), + .io_in_sExp (io_in_sExp), + .io_in_sig (io_in_sig), + .io_roundingMode (io_roundingMode), + .io_out (io_out), + .io_exceptionFlags (io_exceptionFlags) + ); +endmodule + +module MulAddRecFNPipe_l4_e5_s11( + input clock, + reset, + io_validin, + input [1:0] io_op, + input [16:0] io_a, + io_b, + io_c, + input [2:0] io_roundingMode, + output [16:0] io_out, + output [4:0] io_exceptionFlags, + output io_validout +); + + wire _mulAddRecFNToRaw_postMul_io_invalidExc; + wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; + wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; + wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; + wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; + wire [6:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; + wire [13:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; + wire [10:0] _mulAddRecFNToRaw_preMul_io_mulAddA; + wire [10:0] _mulAddRecFNToRaw_preMul_io_mulAddB; + wire [21:0] _mulAddRecFNToRaw_preMul_io_mulAddC; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; + wire [6:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; + wire [3:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; + wire [12:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; + reg [10:0] preMulMulAddA_pipe_b; + reg [10:0] preMulMulAddB_pipe_b; + reg [21:0] preMulMulAddC_pipe_b; + reg preMulToPostMul_pipe_v; + reg preMulToPostMul_pipe_b_isSigNaNAny; + reg preMulToPostMul_pipe_b_isNaNAOrB; + reg preMulToPostMul_pipe_b_isInfA; + reg preMulToPostMul_pipe_b_isZeroA; + reg preMulToPostMul_pipe_b_isInfB; + reg preMulToPostMul_pipe_b_isZeroB; + reg preMulToPostMul_pipe_b_signProd; + reg preMulToPostMul_pipe_b_isNaNC; + reg preMulToPostMul_pipe_b_isInfC; + reg preMulToPostMul_pipe_b_isZeroC; + reg [6:0] preMulToPostMul_pipe_b_sExpSum; + reg preMulToPostMul_pipe_b_doSubMags; + reg preMulToPostMul_pipe_b_CIsDominant; + reg [3:0] preMulToPostMul_pipe_b_CDom_CAlignDist; + reg [12:0] preMulToPostMul_pipe_b_highAlignedSigC; + reg preMulToPostMul_pipe_b_bit0AlignedSigC; + reg [21:0] mulResultPipe_pipe_b; + reg [21:0] mulAddCPipe_pipe_b; + reg mulToPostMul_pipe_v; + reg mulToPostMul_pipe_b_isSigNaNAny; + reg mulToPostMul_pipe_b_isNaNAOrB; + reg mulToPostMul_pipe_b_isInfA; + reg mulToPostMul_pipe_b_isZeroA; + reg mulToPostMul_pipe_b_isInfB; + reg mulToPostMul_pipe_b_isZeroB; + reg mulToPostMul_pipe_b_signProd; + reg mulToPostMul_pipe_b_isNaNC; + reg mulToPostMul_pipe_b_isInfC; + reg mulToPostMul_pipe_b_isZeroC; + reg [6:0] mulToPostMul_pipe_b_sExpSum; + reg mulToPostMul_pipe_b_doSubMags; + reg mulToPostMul_pipe_b_CIsDominant; + reg [3:0] mulToPostMul_pipe_b_CDom_CAlignDist; + reg [12:0] mulToPostMul_pipe_b_highAlignedSigC; + reg mulToPostMul_pipe_b_bit0AlignedSigC; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC; + reg [6:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant; + reg [3:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist; + reg [12:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC; + reg [22:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b; + reg mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v; + reg [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b; + reg mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_v; + reg [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_b; + reg [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_pipe_b; + reg roundingMode_stage0_pipe_v; + reg [2:0] roundingMode_stage0_pipe_b; + reg roundingMode_stage0_pipe_pipe_v; + reg [2:0] roundingMode_stage0_pipe_pipe_b; + reg [2:0] roundingMode_stage0_pipe_pipe_pipe_b; + reg valid_stage0_pipe_v; + reg valid_stage0_pipe_pipe_v; + reg valid_stage0_pipe_pipe_pipe_v; + reg roundRawFNToRecFN_io_invalidExc_pipe_b; + reg roundRawFNToRecFN_io_in_pipe_b_isNaN; + reg roundRawFNToRecFN_io_in_pipe_b_isInf; + reg roundRawFNToRecFN_io_in_pipe_b_isZero; + reg roundRawFNToRecFN_io_in_pipe_b_sign; + reg [6:0] roundRawFNToRecFN_io_in_pipe_b_sExp; + reg [13:0] roundRawFNToRecFN_io_in_pipe_b_sig; + reg [2:0] roundRawFNToRecFN_io_roundingMode_pipe_b; + reg io_validout_pipe_v; + always @(posedge clock) begin + if (io_validin) begin + preMulMulAddA_pipe_b <= _mulAddRecFNToRaw_preMul_io_mulAddA; + preMulMulAddB_pipe_b <= _mulAddRecFNToRaw_preMul_io_mulAddB; + preMulMulAddC_pipe_b <= _mulAddRecFNToRaw_preMul_io_mulAddC; + preMulToPostMul_pipe_b_isSigNaNAny <= + _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; + preMulToPostMul_pipe_b_isNaNAOrB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; + preMulToPostMul_pipe_b_isInfA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; + preMulToPostMul_pipe_b_isZeroA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; + preMulToPostMul_pipe_b_isInfB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; + preMulToPostMul_pipe_b_isZeroB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; + preMulToPostMul_pipe_b_signProd <= _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; + preMulToPostMul_pipe_b_isNaNC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; + preMulToPostMul_pipe_b_isInfC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; + preMulToPostMul_pipe_b_isZeroC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; + preMulToPostMul_pipe_b_sExpSum <= _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; + preMulToPostMul_pipe_b_doSubMags <= _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; + preMulToPostMul_pipe_b_CIsDominant <= + _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; + preMulToPostMul_pipe_b_CDom_CAlignDist <= + _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; + preMulToPostMul_pipe_b_highAlignedSigC <= + _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; + preMulToPostMul_pipe_b_bit0AlignedSigC <= + _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b <= io_roundingMode; + roundingMode_stage0_pipe_b <= io_roundingMode; + end + if (preMulToPostMul_pipe_v) begin + mulResultPipe_pipe_b <= + {11'h0, preMulMulAddA_pipe_b} * {11'h0, preMulMulAddB_pipe_b}; + mulAddCPipe_pipe_b <= preMulMulAddC_pipe_b; + mulToPostMul_pipe_b_isSigNaNAny <= preMulToPostMul_pipe_b_isSigNaNAny; + mulToPostMul_pipe_b_isNaNAOrB <= preMulToPostMul_pipe_b_isNaNAOrB; + mulToPostMul_pipe_b_isInfA <= preMulToPostMul_pipe_b_isInfA; + mulToPostMul_pipe_b_isZeroA <= preMulToPostMul_pipe_b_isZeroA; + mulToPostMul_pipe_b_isInfB <= preMulToPostMul_pipe_b_isInfB; + mulToPostMul_pipe_b_isZeroB <= preMulToPostMul_pipe_b_isZeroB; + mulToPostMul_pipe_b_signProd <= preMulToPostMul_pipe_b_signProd; + mulToPostMul_pipe_b_isNaNC <= preMulToPostMul_pipe_b_isNaNC; + mulToPostMul_pipe_b_isInfC <= preMulToPostMul_pipe_b_isInfC; + mulToPostMul_pipe_b_isZeroC <= preMulToPostMul_pipe_b_isZeroC; + mulToPostMul_pipe_b_sExpSum <= preMulToPostMul_pipe_b_sExpSum; + mulToPostMul_pipe_b_doSubMags <= preMulToPostMul_pipe_b_doSubMags; + mulToPostMul_pipe_b_CIsDominant <= preMulToPostMul_pipe_b_CIsDominant; + mulToPostMul_pipe_b_CDom_CAlignDist <= preMulToPostMul_pipe_b_CDom_CAlignDist; + mulToPostMul_pipe_b_highAlignedSigC <= preMulToPostMul_pipe_b_highAlignedSigC; + mulToPostMul_pipe_b_bit0AlignedSigC <= preMulToPostMul_pipe_b_bit0AlignedSigC; + end + if (mulToPostMul_pipe_v) begin + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny <= + mulToPostMul_pipe_b_isSigNaNAny; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB <= + mulToPostMul_pipe_b_isNaNAOrB; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA <= mulToPostMul_pipe_b_isInfA; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA <= + mulToPostMul_pipe_b_isZeroA; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB <= mulToPostMul_pipe_b_isInfB; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB <= + mulToPostMul_pipe_b_isZeroB; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd <= + mulToPostMul_pipe_b_signProd; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC <= mulToPostMul_pipe_b_isNaNC; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC <= mulToPostMul_pipe_b_isInfC; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC <= + mulToPostMul_pipe_b_isZeroC; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum <= + mulToPostMul_pipe_b_sExpSum; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags <= + mulToPostMul_pipe_b_doSubMags; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant <= + mulToPostMul_pipe_b_CIsDominant; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist <= + mulToPostMul_pipe_b_CDom_CAlignDist; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC <= + mulToPostMul_pipe_b_highAlignedSigC; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC <= + mulToPostMul_pipe_b_bit0AlignedSigC; + mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b <= + {1'h0, mulResultPipe_pipe_b} + {1'h0, mulAddCPipe_pipe_b}; + end + if (mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v) + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_b <= + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b; + if (mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_v) + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_pipe_b <= + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_b; + if (roundingMode_stage0_pipe_v) + roundingMode_stage0_pipe_pipe_b <= roundingMode_stage0_pipe_b; + if (roundingMode_stage0_pipe_pipe_v) + roundingMode_stage0_pipe_pipe_pipe_b <= roundingMode_stage0_pipe_pipe_b; + if (valid_stage0_pipe_pipe_pipe_v) begin + roundRawFNToRecFN_io_invalidExc_pipe_b <= _mulAddRecFNToRaw_postMul_io_invalidExc; + roundRawFNToRecFN_io_in_pipe_b_isNaN <= _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; + roundRawFNToRecFN_io_in_pipe_b_isInf <= _mulAddRecFNToRaw_postMul_io_rawOut_isInf; + roundRawFNToRecFN_io_in_pipe_b_isZero <= _mulAddRecFNToRaw_postMul_io_rawOut_isZero; + roundRawFNToRecFN_io_in_pipe_b_sign <= _mulAddRecFNToRaw_postMul_io_rawOut_sign; + roundRawFNToRecFN_io_in_pipe_b_sExp <= _mulAddRecFNToRaw_postMul_io_rawOut_sExp; + roundRawFNToRecFN_io_in_pipe_b_sig <= _mulAddRecFNToRaw_postMul_io_rawOut_sig; + roundRawFNToRecFN_io_roundingMode_pipe_b <= roundingMode_stage0_pipe_pipe_pipe_b; + end + if (reset) begin + preMulToPostMul_pipe_v <= 1'h0; + mulToPostMul_pipe_v <= 1'h0; + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v <= 1'h0; + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_v <= 1'h0; + roundingMode_stage0_pipe_v <= 1'h0; + roundingMode_stage0_pipe_pipe_v <= 1'h0; + valid_stage0_pipe_v <= 1'h0; + valid_stage0_pipe_pipe_v <= 1'h0; + valid_stage0_pipe_pipe_pipe_v <= 1'h0; + io_validout_pipe_v <= 1'h0; + end + else begin + preMulToPostMul_pipe_v <= io_validin; + mulToPostMul_pipe_v <= preMulToPostMul_pipe_v; + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v <= io_validin; + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_v <= + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v; + roundingMode_stage0_pipe_v <= io_validin; + roundingMode_stage0_pipe_pipe_v <= roundingMode_stage0_pipe_v; + valid_stage0_pipe_v <= io_validin; + valid_stage0_pipe_pipe_v <= valid_stage0_pipe_v; + valid_stage0_pipe_pipe_pipe_v <= valid_stage0_pipe_pipe_v; + io_validout_pipe_v <= valid_stage0_pipe_pipe_pipe_v; + end + end // always @(posedge) + MulAddRecFNToRaw_preMul_e5_s11 mulAddRecFNToRaw_preMul ( + .io_op (io_op), + .io_a (io_a), + .io_b (io_b), + .io_c (io_c), + .io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA), + .io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB), + .io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC), + .io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), + .io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), + .io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), + .io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), + .io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB), + .io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB), + .io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), + .io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), + .io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), + .io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), + .io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), + .io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), + .io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), + .io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), + .io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), + .io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC) + ); + MulAddRecFNToRaw_postMul_e5_s11 mulAddRecFNToRaw_postMul ( + .io_fromPreMul_isSigNaNAny + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny), + .io_fromPreMul_isNaNAOrB + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB), + .io_fromPreMul_isInfA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA), + .io_fromPreMul_isZeroA + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA), + .io_fromPreMul_isInfB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB), + .io_fromPreMul_isZeroB + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB), + .io_fromPreMul_signProd + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd), + .io_fromPreMul_isNaNC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC), + .io_fromPreMul_isInfC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC), + .io_fromPreMul_isZeroC + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC), + .io_fromPreMul_sExpSum + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum), + .io_fromPreMul_doSubMags + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags), + .io_fromPreMul_CIsDominant + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant), + .io_fromPreMul_CDom_CAlignDist + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist), + .io_fromPreMul_highAlignedSigC + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC), + .io_fromPreMul_bit0AlignedSigC + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC), + .io_mulAddResult (mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b), + .io_roundingMode + (mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_pipe_b), + .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), + .io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), + .io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), + .io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), + .io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), + .io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), + .io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig) + ); + RoundRawFNToRecFN_e5_s11 roundRawFNToRecFN ( + .io_invalidExc (roundRawFNToRecFN_io_invalidExc_pipe_b), + .io_in_isNaN (roundRawFNToRecFN_io_in_pipe_b_isNaN), + .io_in_isInf (roundRawFNToRecFN_io_in_pipe_b_isInf), + .io_in_isZero (roundRawFNToRecFN_io_in_pipe_b_isZero), + .io_in_sign (roundRawFNToRecFN_io_in_pipe_b_sign), + .io_in_sExp (roundRawFNToRecFN_io_in_pipe_b_sExp), + .io_in_sig (roundRawFNToRecFN_io_in_pipe_b_sig), + .io_roundingMode (roundRawFNToRecFN_io_roundingMode_pipe_b), + .io_out (io_out), + .io_exceptionFlags (io_exceptionFlags) + ); + assign io_validout = io_validout_pipe_v; +endmodule + +module FPUFMAPipe_l5_f16( + input clock, + reset, + io_in_valid, + io_in_bits_ren3, + io_in_bits_swap23, + input [2:0] io_in_bits_rm, + input [1:0] io_in_bits_fmaCmd, + input [64:0] io_in_bits_in1, + io_in_bits_in2, + io_in_bits_in3, + output io_out_valid, + output [64:0] io_out_bits_data, + output [4:0] io_out_bits_exc +); + + wire [16:0] _fma_io_out; + reg valid; + reg [2:0] in_rm; + reg [1:0] in_fmaCmd; + reg [64:0] in_in1; + reg [64:0] in_in2; + reg [64:0] in_in3; + always @(posedge clock) begin + valid <= io_in_valid; + if (io_in_valid) begin + in_rm <= io_in_bits_rm; + in_fmaCmd <= io_in_bits_fmaCmd; + in_in1 <= io_in_bits_in1; + in_in2 <= io_in_bits_swap23 ? 65'h8000 : io_in_bits_in2; + in_in3 <= + io_in_bits_ren3 | io_in_bits_swap23 + ? io_in_bits_in3 + : {48'h0, (io_in_bits_in1[16:0] ^ io_in_bits_in2[16:0]) & 17'h10000}; + end + end // always @(posedge) + MulAddRecFNPipe_l4_e5_s11 fma ( + .clock (clock), + .reset (reset), + .io_validin (valid), + .io_op (in_fmaCmd), + .io_a (in_in1[16:0]), + .io_b (in_in2[16:0]), + .io_c (in_in3[16:0]), + .io_roundingMode (in_rm), + .io_out (_fma_io_out), + .io_exceptionFlags (io_out_bits_exc), + .io_validout (io_out_valid) + ); + assign io_out_bits_data = {48'h0, _fma_io_out}; +endmodule + +module MulAddRecFNToRaw_preMul_e8_s24( + input [1:0] io_op, + input [32:0] io_a, + io_b, + io_c, + output [23:0] io_mulAddA, + io_mulAddB, + output [47:0] io_mulAddC, + output io_toPostMul_isSigNaNAny, + io_toPostMul_isNaNAOrB, + io_toPostMul_isInfA, + io_toPostMul_isZeroA, + io_toPostMul_isInfB, + io_toPostMul_isZeroB, + io_toPostMul_signProd, + io_toPostMul_isNaNC, + io_toPostMul_isInfC, + io_toPostMul_isZeroC, + output [9:0] io_toPostMul_sExpSum, + output io_toPostMul_doSubMags, + io_toPostMul_CIsDominant, + output [4:0] io_toPostMul_CDom_CAlignDist, + output [25:0] io_toPostMul_highAlignedSigC, + output io_toPostMul_bit0AlignedSigC +); + + wire rawA_isNaN = (&(io_a[31:30])) & io_a[29]; + wire rawB_isNaN = (&(io_b[31:30])) & io_b[29]; + wire rawC_isNaN = (&(io_c[31:30])) & io_c[29]; + wire signProd = io_a[32] ^ io_b[32] ^ io_op[1]; + wire [10:0] _sExpAlignedProd_T_1 = {2'h0, io_a[31:23]} + {2'h0, io_b[31:23]} - 11'hE5; + wire doSubMags = signProd ^ io_c[32] ^ io_op[0]; + wire [10:0] _sNatCAlignDist_T = _sExpAlignedProd_T_1 - {2'h0, io_c[31:23]}; + wire isMinCAlign = + ~(|(io_a[31:29])) | ~(|(io_b[31:29])) | $signed(_sNatCAlignDist_T) < 11'sh0; + wire CIsDominant = + (|(io_c[31:29])) & (isMinCAlign | _sNatCAlignDist_T[9:0] < 10'h19); + wire [6:0] CAlignDist = + isMinCAlign ? 7'h0 : _sNatCAlignDist_T[9:0] < 10'h4A ? _sNatCAlignDist_T[6:0] : 7'h4A; + wire [77:0] mainAlignedSigC = + $signed($signed({doSubMags + ? {1'h1, ~(|(io_c[31:29])), ~(io_c[22:0])} + : {1'h0, |(io_c[31:29]), io_c[22:0]}, + {53{doSubMags}}}) >>> CAlignDist); + wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> CAlignDist[6:2]); + wire [5:0] _GEN = + {|(io_c[21:18]), + |(io_c[17:14]), + |(io_c[13:10]), + |(io_c[9:6]), + |(io_c[5:2]), + |(io_c[1:0])} + & {reduced4CExtra_shift[14], + reduced4CExtra_shift[15], + reduced4CExtra_shift[16], + reduced4CExtra_shift[17], + reduced4CExtra_shift[18], + reduced4CExtra_shift[19]}; + assign io_mulAddA = {|(io_a[31:29]), io_a[22:0]}; + assign io_mulAddB = {|(io_b[31:29]), io_b[22:0]}; + assign io_mulAddC = mainAlignedSigC[50:3]; + assign io_toPostMul_isSigNaNAny = + rawA_isNaN & ~(io_a[22]) | rawB_isNaN & ~(io_b[22]) | rawC_isNaN & ~(io_c[22]); + assign io_toPostMul_isNaNAOrB = rawA_isNaN | rawB_isNaN; + assign io_toPostMul_isInfA = (&(io_a[31:30])) & ~(io_a[29]); + assign io_toPostMul_isZeroA = ~(|(io_a[31:29])); + assign io_toPostMul_isInfB = (&(io_b[31:30])) & ~(io_b[29]); + assign io_toPostMul_isZeroB = ~(|(io_b[31:29])); + assign io_toPostMul_signProd = signProd; + assign io_toPostMul_isNaNC = rawC_isNaN; + assign io_toPostMul_isInfC = (&(io_c[31:30])) & ~(io_c[29]); + assign io_toPostMul_isZeroC = ~(|(io_c[31:29])); + assign io_toPostMul_sExpSum = + CIsDominant ? {1'h0, io_c[31:23]} : _sExpAlignedProd_T_1[9:0] - 10'h18; + assign io_toPostMul_doSubMags = doSubMags; + assign io_toPostMul_CIsDominant = CIsDominant; + assign io_toPostMul_CDom_CAlignDist = CAlignDist[4:0]; + assign io_toPostMul_highAlignedSigC = mainAlignedSigC[76:51]; + assign io_toPostMul_bit0AlignedSigC = + doSubMags + ? (&(mainAlignedSigC[2:0])) & ~(|_GEN) + : (|(mainAlignedSigC[2:0])) | (|_GEN); +endmodule + +module MulAddRecFNToRaw_postMul_e8_s24( + input io_fromPreMul_isSigNaNAny, + io_fromPreMul_isNaNAOrB, + io_fromPreMul_isInfA, + io_fromPreMul_isZeroA, + io_fromPreMul_isInfB, + io_fromPreMul_isZeroB, + io_fromPreMul_signProd, + io_fromPreMul_isNaNC, + io_fromPreMul_isInfC, + io_fromPreMul_isZeroC, + input [9:0] io_fromPreMul_sExpSum, + input io_fromPreMul_doSubMags, + io_fromPreMul_CIsDominant, + input [4:0] io_fromPreMul_CDom_CAlignDist, + input [25:0] io_fromPreMul_highAlignedSigC, + input io_fromPreMul_bit0AlignedSigC, + input [48:0] io_mulAddResult, + input [2:0] io_roundingMode, + output io_invalidExc, + io_rawOut_isNaN, + io_rawOut_isInf, + io_rawOut_isZero, + io_rawOut_sign, + output [9:0] io_rawOut_sExp, + output [26:0] io_rawOut_sig +); + + wire roundingMode_min = io_roundingMode == 3'h2; + wire opSignC = io_fromPreMul_signProd ^ io_fromPreMul_doSubMags; + wire [25:0] _sigSum_T_3 = + io_mulAddResult[48] + ? io_fromPreMul_highAlignedSigC + 26'h1 + : io_fromPreMul_highAlignedSigC; + wire [49:0] CDom_absSigSum = + io_fromPreMul_doSubMags + ? ~{_sigSum_T_3, io_mulAddResult[47:24]} + : {1'h0, + io_fromPreMul_highAlignedSigC[25:24], + _sigSum_T_3[23:0], + io_mulAddResult[47:25]}; + wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist; + wire [8:0] CDom_reduced4SigExtra_shift = + $signed(9'sh100 >>> ~(io_fromPreMul_CDom_CAlignDist[4:2])); + wire [50:0] notCDom_absSigSum = + _sigSum_T_3[2] + ? ~{_sigSum_T_3[1:0], io_mulAddResult[47:0], io_fromPreMul_bit0AlignedSigC} + : {_sigSum_T_3[1:0], io_mulAddResult[47:0], io_fromPreMul_bit0AlignedSigC} + + {50'h0, io_fromPreMul_doSubMags}; + wire [4:0] notCDom_normDistReduced2 = + notCDom_absSigSum[50] + ? 5'h0 + : (|(notCDom_absSigSum[49:48])) + ? 5'h1 + : (|(notCDom_absSigSum[47:46])) + ? 5'h2 + : (|(notCDom_absSigSum[45:44])) + ? 5'h3 + : (|(notCDom_absSigSum[43:42])) + ? 5'h4 + : (|(notCDom_absSigSum[41:40])) + ? 5'h5 + : (|(notCDom_absSigSum[39:38])) + ? 5'h6 + : (|(notCDom_absSigSum[37:36])) + ? 5'h7 + : (|(notCDom_absSigSum[35:34])) + ? 5'h8 + : (|(notCDom_absSigSum[33:32])) + ? 5'h9 + : (|(notCDom_absSigSum[31:30])) + ? 5'hA + : (|(notCDom_absSigSum[29:28])) + ? 5'hB + : (|(notCDom_absSigSum[27:26])) + ? 5'hC + : (|(notCDom_absSigSum[25:24])) + ? 5'hD + : (|(notCDom_absSigSum[23:22])) + ? 5'hE + : (|(notCDom_absSigSum[21:20])) + ? 5'hF + : (|(notCDom_absSigSum[19:18])) + ? 5'h10 + : (|(notCDom_absSigSum[17:16])) + ? 5'h11 + : (|(notCDom_absSigSum[15:14])) + ? 5'h12 + : (|(notCDom_absSigSum[13:12])) + ? 5'h13 + : (|(notCDom_absSigSum[11:10])) + ? 5'h14 + : (|(notCDom_absSigSum[9:8])) + ? 5'h15 + : (|(notCDom_absSigSum[7:6])) + ? 5'h16 + : (|(notCDom_absSigSum[5:4])) + ? 5'h17 + : {4'hC, + ~(|(notCDom_absSigSum[3:2]))}; + wire [113:0] _notCDom_mainSig_T = + {63'h0, notCDom_absSigSum} << {108'h0, notCDom_normDistReduced2, 1'h0}; + wire [16:0] notCDom_reduced4SigExtra_shift = + $signed(17'sh10000 >>> ~(notCDom_normDistReduced2[4:1])); + wire notCDom_completeCancellation = _notCDom_mainSig_T[51:50] == 2'h0; + wire notNaN_isInfProd = io_fromPreMul_isInfA | io_fromPreMul_isInfB; + wire notNaN_isInfOut = notNaN_isInfProd | io_fromPreMul_isInfC; + wire notNaN_addZeros = + (io_fromPreMul_isZeroA | io_fromPreMul_isZeroB) & io_fromPreMul_isZeroC; + assign io_invalidExc = + io_fromPreMul_isSigNaNAny | io_fromPreMul_isInfA & io_fromPreMul_isZeroB + | io_fromPreMul_isZeroA & io_fromPreMul_isInfB | ~io_fromPreMul_isNaNAOrB + & notNaN_isInfProd & io_fromPreMul_isInfC & io_fromPreMul_doSubMags; + assign io_rawOut_isNaN = io_fromPreMul_isNaNAOrB | io_fromPreMul_isNaNC; + assign io_rawOut_isInf = notNaN_isInfOut; + assign io_rawOut_isZero = + notNaN_addZeros | ~io_fromPreMul_CIsDominant & notCDom_completeCancellation; + assign io_rawOut_sign = + notNaN_isInfProd & io_fromPreMul_signProd | io_fromPreMul_isInfC & opSignC + | notNaN_addZeros & ~roundingMode_min & io_fromPreMul_signProd & opSignC + | notNaN_addZeros & roundingMode_min & (io_fromPreMul_signProd | opSignC) + | ~notNaN_isInfOut & ~notNaN_addZeros + & (io_fromPreMul_CIsDominant + ? opSignC + : notCDom_completeCancellation + ? roundingMode_min + : io_fromPreMul_signProd ^ _sigSum_T_3[2]); + assign io_rawOut_sExp = + io_fromPreMul_CIsDominant + ? io_fromPreMul_sExpSum - {9'h0, io_fromPreMul_doSubMags} + : io_fromPreMul_sExpSum - {4'h0, notCDom_normDistReduced2, 1'h0}; + assign io_rawOut_sig = + io_fromPreMul_CIsDominant + ? {_CDom_mainSig_T[49:24], + (|(_CDom_mainSig_T[23:21])) + | (|({|(CDom_absSigSum[20:17]), + |(CDom_absSigSum[16:13]), + |(CDom_absSigSum[12:9]), + |(CDom_absSigSum[8:5]), + |(CDom_absSigSum[4:1]), + CDom_absSigSum[0]} + & {CDom_reduced4SigExtra_shift[1], + CDom_reduced4SigExtra_shift[2], + CDom_reduced4SigExtra_shift[3], + CDom_reduced4SigExtra_shift[4], + CDom_reduced4SigExtra_shift[5], + CDom_reduced4SigExtra_shift[6]})) + | (io_fromPreMul_doSubMags + ? io_mulAddResult[23:0] != 24'hFFFFFF + : (|(io_mulAddResult[24:0])))} + : {_notCDom_mainSig_T[51:26], + (|(_notCDom_mainSig_T[25:23])) + | (|({|{|(notCDom_absSigSum[23:22]), |(notCDom_absSigSum[21:20])}, + |{|(notCDom_absSigSum[19:18]), |(notCDom_absSigSum[17:16])}, + |{|(notCDom_absSigSum[15:14]), |(notCDom_absSigSum[13:12])}, + |{|(notCDom_absSigSum[11:10]), |(notCDom_absSigSum[9:8])}, + |{|(notCDom_absSigSum[7:6]), |(notCDom_absSigSum[5:4])}, + |{|(notCDom_absSigSum[3:2]), |(notCDom_absSigSum[1:0])}} + & {notCDom_reduced4SigExtra_shift[1], + notCDom_reduced4SigExtra_shift[2], + notCDom_reduced4SigExtra_shift[3], + notCDom_reduced4SigExtra_shift[4], + notCDom_reduced4SigExtra_shift[5], + notCDom_reduced4SigExtra_shift[6]}))}; +endmodule + +module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24( + input io_invalidExc, + io_in_isNaN, + io_in_isInf, + io_in_isZero, + io_in_sign, + input [9:0] io_in_sExp, + input [26:0] io_in_sig, + input [2:0] io_roundingMode, + output [32:0] io_out, + output [4:0] io_exceptionFlags +); + + wire roundingMode_near_even = io_roundingMode == 3'h0; + wire roundingMode_odd = io_roundingMode == 3'h6; + wire roundMagUp = + io_roundingMode == 3'h2 & io_in_sign | io_roundingMode == 3'h3 & ~io_in_sign; + wire [8:0] _roundMask_T_1 = ~(io_in_sExp[8:0]); + wire [64:0] _GEN = {59'h0, _roundMask_T_1[5:0]}; + wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> _GEN); + wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> _GEN); + wire [24:0] _roundMask_T_73 = + _roundMask_T_1[8] + ? (_roundMask_T_1[7] + ? {~(_roundMask_T_1[6] + ? 22'h0 + : ~{roundMask_shift[42], + roundMask_shift[43], + roundMask_shift[44], + roundMask_shift[45], + roundMask_shift[46], + {{roundMask_shift[47:46], roundMask_shift[49]} & 3'h5, 1'h0} + | {roundMask_shift[49:48], roundMask_shift[51:50]} & 4'h5, + roundMask_shift[51], + roundMask_shift[52], + roundMask_shift[53], + roundMask_shift[54], + roundMask_shift[55], + roundMask_shift[56], + roundMask_shift[57], + roundMask_shift[58], + roundMask_shift[59], + roundMask_shift[60], + roundMask_shift[61], + roundMask_shift[62], + roundMask_shift[63]}), + 3'h7} + : {22'h0, + _roundMask_T_1[6] + ? {roundMask_shift_1[0], roundMask_shift_1[1], roundMask_shift_1[2]} + : 3'h0}) + : 25'h0; + wire _common_underflow_T_4 = _roundMask_T_73[0] | io_in_sig[26]; + wire [25:0] _GEN_0 = {1'h1, ~(_roundMask_T_73[24:1]), ~_common_underflow_T_4}; + wire [25:0] _GEN_1 = {_roundMask_T_73[24:1], _common_underflow_T_4, 1'h1}; + wire [25:0] _roundPosBit_T = io_in_sig[26:1] & _GEN_0 & _GEN_1; + wire [25:0] _anyRoundExtra_T = io_in_sig[25:0] & _GEN_1; + wire anyRound = (|_roundPosBit_T) | (|_anyRoundExtra_T); + wire _overflow_roundMagUp_T = roundingMode_near_even | io_roundingMode == 3'h4; + wire [25:0] roundedSig = + _overflow_roundMagUp_T & (|_roundPosBit_T) | roundMagUp & anyRound + ? {1'h0, io_in_sig[26:2] | {_roundMask_T_73[24:1], _common_underflow_T_4}} + 26'h1 + & ~(roundingMode_near_even & (|_roundPosBit_T) & ~(|_anyRoundExtra_T) + ? {_roundMask_T_73[24:1], _common_underflow_T_4, 1'h1} + : 26'h0) + : {1'h0, io_in_sig[26:2] & {~(_roundMask_T_73[24:1]), ~_common_underflow_T_4}} + | (roundingMode_odd & anyRound ? _GEN_0 & _GEN_1 : 26'h0); + wire [10:0] sRoundedExp = {io_in_sExp[9], io_in_sExp} + {9'h0, roundedSig[25:24]}; + wire common_totalUnderflow = $signed(sRoundedExp) < 11'sh6B; + wire isNaNOut = io_invalidExc | io_in_isNaN; + wire commonCase = ~isNaNOut & ~io_in_isInf & ~io_in_isZero; + wire overflow = commonCase & $signed(sRoundedExp[10:7]) > 4'sh2; + wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp; + wire pegMinNonzeroMagOut = + commonCase & common_totalUnderflow & (roundMagUp | roundingMode_odd); + wire pegMaxFiniteMagOut = overflow & ~overflow_roundMagUp; + wire notNaN_isInfOut = io_in_isInf | overflow & overflow_roundMagUp; + assign io_out = + {~isNaNOut & io_in_sign, + sRoundedExp[8:0] & ~(io_in_isZero | common_totalUnderflow ? 9'h1C0 : 9'h0) + & ~(pegMinNonzeroMagOut ? 9'h194 : 9'h0) & {1'h1, ~pegMaxFiniteMagOut, 7'h7F} + & {2'h3, ~notNaN_isInfOut, 6'h3F} | (pegMinNonzeroMagOut ? 9'h6B : 9'h0) + | (pegMaxFiniteMagOut ? 9'h17F : 9'h0) | (notNaN_isInfOut ? 9'h180 : 9'h0) + | (isNaNOut ? 9'h1C0 : 9'h0), + (isNaNOut | io_in_isZero | common_totalUnderflow + ? {isNaNOut, 22'h0} + : io_in_sig[26] ? roundedSig[23:1] : roundedSig[22:0]) + | {23{pegMaxFiniteMagOut}}}; + assign io_exceptionFlags = + {io_invalidExc, + 1'h0, + overflow, + commonCase + & (common_totalUnderflow | anyRound & io_in_sExp[9:8] != 2'h1 + & (io_in_sig[26] ? _roundMask_T_73[1] : _common_underflow_T_4) + & ~(~(io_in_sig[26] ? _roundMask_T_73[2] : _roundMask_T_73[1]) + & (io_in_sig[26] ? roundedSig[25] : roundedSig[24]) & (|_roundPosBit_T) + & (_overflow_roundMagUp_T & (io_in_sig[26] ? io_in_sig[2] : io_in_sig[1]) + | roundMagUp & (io_in_sig[26] & io_in_sig[2] | (|(io_in_sig[1:0])))))), + overflow | commonCase & (common_totalUnderflow | anyRound)}; +endmodule + +module RoundRawFNToRecFN_e8_s24( + input io_invalidExc, + io_in_isNaN, + io_in_isInf, + io_in_isZero, + io_in_sign, + input [9:0] io_in_sExp, + input [26:0] io_in_sig, + input [2:0] io_roundingMode, + output [32:0] io_out, + output [4:0] io_exceptionFlags +); + + RoundAnyRawFNToRecFN_ie8_is26_oe8_os24 roundAnyRawFNToRecFN ( + .io_invalidExc (io_invalidExc), + .io_in_isNaN (io_in_isNaN), + .io_in_isInf (io_in_isInf), + .io_in_isZero (io_in_isZero), + .io_in_sign (io_in_sign), + .io_in_sExp (io_in_sExp), + .io_in_sig (io_in_sig), + .io_roundingMode (io_roundingMode), + .io_out (io_out), + .io_exceptionFlags (io_exceptionFlags) + ); +endmodule + +module MulAddRecFNPipe_l4_e8_s24( + input clock, + reset, + io_validin, + input [1:0] io_op, + input [32:0] io_a, + io_b, + io_c, + input [2:0] io_roundingMode, + output [32:0] io_out, + output [4:0] io_exceptionFlags, + output io_validout +); + + wire _mulAddRecFNToRaw_postMul_io_invalidExc; + wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; + wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; + wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; + wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; + wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; + wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; + wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddA; + wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddB; + wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; + wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; + wire [4:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; + wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; + reg [23:0] preMulMulAddA_pipe_b; + reg [23:0] preMulMulAddB_pipe_b; + reg [47:0] preMulMulAddC_pipe_b; + reg preMulToPostMul_pipe_v; + reg preMulToPostMul_pipe_b_isSigNaNAny; + reg preMulToPostMul_pipe_b_isNaNAOrB; + reg preMulToPostMul_pipe_b_isInfA; + reg preMulToPostMul_pipe_b_isZeroA; + reg preMulToPostMul_pipe_b_isInfB; + reg preMulToPostMul_pipe_b_isZeroB; + reg preMulToPostMul_pipe_b_signProd; + reg preMulToPostMul_pipe_b_isNaNC; + reg preMulToPostMul_pipe_b_isInfC; + reg preMulToPostMul_pipe_b_isZeroC; + reg [9:0] preMulToPostMul_pipe_b_sExpSum; + reg preMulToPostMul_pipe_b_doSubMags; + reg preMulToPostMul_pipe_b_CIsDominant; + reg [4:0] preMulToPostMul_pipe_b_CDom_CAlignDist; + reg [25:0] preMulToPostMul_pipe_b_highAlignedSigC; + reg preMulToPostMul_pipe_b_bit0AlignedSigC; + reg [47:0] mulResultPipe_pipe_b; + reg [47:0] mulAddCPipe_pipe_b; + reg mulToPostMul_pipe_v; + reg mulToPostMul_pipe_b_isSigNaNAny; + reg mulToPostMul_pipe_b_isNaNAOrB; + reg mulToPostMul_pipe_b_isInfA; + reg mulToPostMul_pipe_b_isZeroA; + reg mulToPostMul_pipe_b_isInfB; + reg mulToPostMul_pipe_b_isZeroB; + reg mulToPostMul_pipe_b_signProd; + reg mulToPostMul_pipe_b_isNaNC; + reg mulToPostMul_pipe_b_isInfC; + reg mulToPostMul_pipe_b_isZeroC; + reg [9:0] mulToPostMul_pipe_b_sExpSum; + reg mulToPostMul_pipe_b_doSubMags; + reg mulToPostMul_pipe_b_CIsDominant; + reg [4:0] mulToPostMul_pipe_b_CDom_CAlignDist; + reg [25:0] mulToPostMul_pipe_b_highAlignedSigC; + reg mulToPostMul_pipe_b_bit0AlignedSigC; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC; + reg [9:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant; + reg [4:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist; + reg [25:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC; + reg [48:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b; + reg mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v; + reg [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b; + reg mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_v; + reg [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_b; + reg [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_pipe_b; + reg roundingMode_stage0_pipe_v; + reg [2:0] roundingMode_stage0_pipe_b; + reg roundingMode_stage0_pipe_pipe_v; + reg [2:0] roundingMode_stage0_pipe_pipe_b; + reg [2:0] roundingMode_stage0_pipe_pipe_pipe_b; + reg valid_stage0_pipe_v; + reg valid_stage0_pipe_pipe_v; + reg valid_stage0_pipe_pipe_pipe_v; + reg roundRawFNToRecFN_io_invalidExc_pipe_b; + reg roundRawFNToRecFN_io_in_pipe_b_isNaN; + reg roundRawFNToRecFN_io_in_pipe_b_isInf; + reg roundRawFNToRecFN_io_in_pipe_b_isZero; + reg roundRawFNToRecFN_io_in_pipe_b_sign; + reg [9:0] roundRawFNToRecFN_io_in_pipe_b_sExp; + reg [26:0] roundRawFNToRecFN_io_in_pipe_b_sig; + reg [2:0] roundRawFNToRecFN_io_roundingMode_pipe_b; + reg io_validout_pipe_v; + always @(posedge clock) begin + if (io_validin) begin + preMulMulAddA_pipe_b <= _mulAddRecFNToRaw_preMul_io_mulAddA; + preMulMulAddB_pipe_b <= _mulAddRecFNToRaw_preMul_io_mulAddB; + preMulMulAddC_pipe_b <= _mulAddRecFNToRaw_preMul_io_mulAddC; + preMulToPostMul_pipe_b_isSigNaNAny <= + _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; + preMulToPostMul_pipe_b_isNaNAOrB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; + preMulToPostMul_pipe_b_isInfA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; + preMulToPostMul_pipe_b_isZeroA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; + preMulToPostMul_pipe_b_isInfB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; + preMulToPostMul_pipe_b_isZeroB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; + preMulToPostMul_pipe_b_signProd <= _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; + preMulToPostMul_pipe_b_isNaNC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; + preMulToPostMul_pipe_b_isInfC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; + preMulToPostMul_pipe_b_isZeroC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; + preMulToPostMul_pipe_b_sExpSum <= _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; + preMulToPostMul_pipe_b_doSubMags <= _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; + preMulToPostMul_pipe_b_CIsDominant <= + _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; + preMulToPostMul_pipe_b_CDom_CAlignDist <= + _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; + preMulToPostMul_pipe_b_highAlignedSigC <= + _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; + preMulToPostMul_pipe_b_bit0AlignedSigC <= + _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b <= io_roundingMode; + roundingMode_stage0_pipe_b <= io_roundingMode; + end + if (preMulToPostMul_pipe_v) begin + mulResultPipe_pipe_b <= + {24'h0, preMulMulAddA_pipe_b} * {24'h0, preMulMulAddB_pipe_b}; + mulAddCPipe_pipe_b <= preMulMulAddC_pipe_b; + mulToPostMul_pipe_b_isSigNaNAny <= preMulToPostMul_pipe_b_isSigNaNAny; + mulToPostMul_pipe_b_isNaNAOrB <= preMulToPostMul_pipe_b_isNaNAOrB; + mulToPostMul_pipe_b_isInfA <= preMulToPostMul_pipe_b_isInfA; + mulToPostMul_pipe_b_isZeroA <= preMulToPostMul_pipe_b_isZeroA; + mulToPostMul_pipe_b_isInfB <= preMulToPostMul_pipe_b_isInfB; + mulToPostMul_pipe_b_isZeroB <= preMulToPostMul_pipe_b_isZeroB; + mulToPostMul_pipe_b_signProd <= preMulToPostMul_pipe_b_signProd; + mulToPostMul_pipe_b_isNaNC <= preMulToPostMul_pipe_b_isNaNC; + mulToPostMul_pipe_b_isInfC <= preMulToPostMul_pipe_b_isInfC; + mulToPostMul_pipe_b_isZeroC <= preMulToPostMul_pipe_b_isZeroC; + mulToPostMul_pipe_b_sExpSum <= preMulToPostMul_pipe_b_sExpSum; + mulToPostMul_pipe_b_doSubMags <= preMulToPostMul_pipe_b_doSubMags; + mulToPostMul_pipe_b_CIsDominant <= preMulToPostMul_pipe_b_CIsDominant; + mulToPostMul_pipe_b_CDom_CAlignDist <= preMulToPostMul_pipe_b_CDom_CAlignDist; + mulToPostMul_pipe_b_highAlignedSigC <= preMulToPostMul_pipe_b_highAlignedSigC; + mulToPostMul_pipe_b_bit0AlignedSigC <= preMulToPostMul_pipe_b_bit0AlignedSigC; + end + if (mulToPostMul_pipe_v) begin + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny <= + mulToPostMul_pipe_b_isSigNaNAny; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB <= + mulToPostMul_pipe_b_isNaNAOrB; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA <= mulToPostMul_pipe_b_isInfA; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA <= + mulToPostMul_pipe_b_isZeroA; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB <= mulToPostMul_pipe_b_isInfB; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB <= + mulToPostMul_pipe_b_isZeroB; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd <= + mulToPostMul_pipe_b_signProd; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC <= mulToPostMul_pipe_b_isNaNC; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC <= mulToPostMul_pipe_b_isInfC; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC <= + mulToPostMul_pipe_b_isZeroC; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum <= + mulToPostMul_pipe_b_sExpSum; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags <= + mulToPostMul_pipe_b_doSubMags; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant <= + mulToPostMul_pipe_b_CIsDominant; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist <= + mulToPostMul_pipe_b_CDom_CAlignDist; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC <= + mulToPostMul_pipe_b_highAlignedSigC; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC <= + mulToPostMul_pipe_b_bit0AlignedSigC; + mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b <= + {1'h0, mulResultPipe_pipe_b} + {1'h0, mulAddCPipe_pipe_b}; + end + if (mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v) + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_b <= + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b; + if (mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_v) + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_pipe_b <= + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_b; + if (roundingMode_stage0_pipe_v) + roundingMode_stage0_pipe_pipe_b <= roundingMode_stage0_pipe_b; + if (roundingMode_stage0_pipe_pipe_v) + roundingMode_stage0_pipe_pipe_pipe_b <= roundingMode_stage0_pipe_pipe_b; + if (valid_stage0_pipe_pipe_pipe_v) begin + roundRawFNToRecFN_io_invalidExc_pipe_b <= _mulAddRecFNToRaw_postMul_io_invalidExc; + roundRawFNToRecFN_io_in_pipe_b_isNaN <= _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; + roundRawFNToRecFN_io_in_pipe_b_isInf <= _mulAddRecFNToRaw_postMul_io_rawOut_isInf; + roundRawFNToRecFN_io_in_pipe_b_isZero <= _mulAddRecFNToRaw_postMul_io_rawOut_isZero; + roundRawFNToRecFN_io_in_pipe_b_sign <= _mulAddRecFNToRaw_postMul_io_rawOut_sign; + roundRawFNToRecFN_io_in_pipe_b_sExp <= _mulAddRecFNToRaw_postMul_io_rawOut_sExp; + roundRawFNToRecFN_io_in_pipe_b_sig <= _mulAddRecFNToRaw_postMul_io_rawOut_sig; + roundRawFNToRecFN_io_roundingMode_pipe_b <= roundingMode_stage0_pipe_pipe_pipe_b; + end + if (reset) begin + preMulToPostMul_pipe_v <= 1'h0; + mulToPostMul_pipe_v <= 1'h0; + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v <= 1'h0; + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_v <= 1'h0; + roundingMode_stage0_pipe_v <= 1'h0; + roundingMode_stage0_pipe_pipe_v <= 1'h0; + valid_stage0_pipe_v <= 1'h0; + valid_stage0_pipe_pipe_v <= 1'h0; + valid_stage0_pipe_pipe_pipe_v <= 1'h0; + io_validout_pipe_v <= 1'h0; + end + else begin + preMulToPostMul_pipe_v <= io_validin; + mulToPostMul_pipe_v <= preMulToPostMul_pipe_v; + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v <= io_validin; + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_v <= + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v; + roundingMode_stage0_pipe_v <= io_validin; + roundingMode_stage0_pipe_pipe_v <= roundingMode_stage0_pipe_v; + valid_stage0_pipe_v <= io_validin; + valid_stage0_pipe_pipe_v <= valid_stage0_pipe_v; + valid_stage0_pipe_pipe_pipe_v <= valid_stage0_pipe_pipe_v; + io_validout_pipe_v <= valid_stage0_pipe_pipe_pipe_v; + end + end // always @(posedge) + MulAddRecFNToRaw_preMul_e8_s24 mulAddRecFNToRaw_preMul ( + .io_op (io_op), + .io_a (io_a), + .io_b (io_b), + .io_c (io_c), + .io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA), + .io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB), + .io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC), + .io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), + .io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), + .io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), + .io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), + .io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB), + .io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB), + .io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), + .io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), + .io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), + .io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), + .io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), + .io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), + .io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), + .io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), + .io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), + .io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC) + ); + MulAddRecFNToRaw_postMul_e8_s24 mulAddRecFNToRaw_postMul ( + .io_fromPreMul_isSigNaNAny + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny), + .io_fromPreMul_isNaNAOrB + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB), + .io_fromPreMul_isInfA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA), + .io_fromPreMul_isZeroA + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA), + .io_fromPreMul_isInfB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB), + .io_fromPreMul_isZeroB + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB), + .io_fromPreMul_signProd + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd), + .io_fromPreMul_isNaNC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC), + .io_fromPreMul_isInfC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC), + .io_fromPreMul_isZeroC + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC), + .io_fromPreMul_sExpSum + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum), + .io_fromPreMul_doSubMags + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags), + .io_fromPreMul_CIsDominant + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant), + .io_fromPreMul_CDom_CAlignDist + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist), + .io_fromPreMul_highAlignedSigC + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC), + .io_fromPreMul_bit0AlignedSigC + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC), + .io_mulAddResult (mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b), + .io_roundingMode + (mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_pipe_b), + .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), + .io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), + .io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), + .io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), + .io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), + .io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), + .io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig) + ); + RoundRawFNToRecFN_e8_s24 roundRawFNToRecFN ( + .io_invalidExc (roundRawFNToRecFN_io_invalidExc_pipe_b), + .io_in_isNaN (roundRawFNToRecFN_io_in_pipe_b_isNaN), + .io_in_isInf (roundRawFNToRecFN_io_in_pipe_b_isInf), + .io_in_isZero (roundRawFNToRecFN_io_in_pipe_b_isZero), + .io_in_sign (roundRawFNToRecFN_io_in_pipe_b_sign), + .io_in_sExp (roundRawFNToRecFN_io_in_pipe_b_sExp), + .io_in_sig (roundRawFNToRecFN_io_in_pipe_b_sig), + .io_roundingMode (roundRawFNToRecFN_io_roundingMode_pipe_b), + .io_out (io_out), + .io_exceptionFlags (io_exceptionFlags) + ); + assign io_validout = io_validout_pipe_v; +endmodule + +module FPUFMAPipe_l5_f32( + input clock, + reset, + io_in_valid, + io_in_bits_ren3, + io_in_bits_swap23, + input [2:0] io_in_bits_rm, + input [1:0] io_in_bits_fmaCmd, + input [64:0] io_in_bits_in1, + io_in_bits_in2, + io_in_bits_in3, + output io_out_valid, + output [64:0] io_out_bits_data, + output [4:0] io_out_bits_exc +); + + wire [32:0] _fma_io_out; + reg valid; + reg [2:0] in_rm; + reg [1:0] in_fmaCmd; + reg [64:0] in_in1; + reg [64:0] in_in2; + reg [64:0] in_in3; + always @(posedge clock) begin + valid <= io_in_valid; + if (io_in_valid) begin + in_rm <= io_in_bits_rm; + in_fmaCmd <= io_in_bits_fmaCmd; + in_in1 <= io_in_bits_in1; + in_in2 <= io_in_bits_swap23 ? 65'h80000000 : io_in_bits_in2; + in_in3 <= + io_in_bits_ren3 | io_in_bits_swap23 + ? io_in_bits_in3 + : {32'h0, (io_in_bits_in1[32:0] ^ io_in_bits_in2[32:0]) & 33'h100000000}; + end + end // always @(posedge) + MulAddRecFNPipe_l4_e8_s24 fma ( + .clock (clock), + .reset (reset), + .io_validin (valid), + .io_op (in_fmaCmd), + .io_a (in_in1[32:0]), + .io_b (in_in2[32:0]), + .io_c (in_in3[32:0]), + .io_roundingMode (in_rm), + .io_out (_fma_io_out), + .io_exceptionFlags (io_out_bits_exc), + .io_validout (io_out_valid) + ); + assign io_out_bits_data = + {32'h0, ({33{_fma_io_out[31:29] != 3'h7}} | 33'h1EF7FFFFF) & _fma_io_out}; +endmodule + +module MulAddRecFNToRaw_preMul_e11_s53( + input [1:0] io_op, + input [64:0] io_a, + io_b, + io_c, + output [52:0] io_mulAddA, + io_mulAddB, + output [105:0] io_mulAddC, + output io_toPostMul_isSigNaNAny, + io_toPostMul_isNaNAOrB, + io_toPostMul_isInfA, + io_toPostMul_isZeroA, + io_toPostMul_isInfB, + io_toPostMul_isZeroB, + io_toPostMul_signProd, + io_toPostMul_isNaNC, + io_toPostMul_isInfC, + io_toPostMul_isZeroC, + output [12:0] io_toPostMul_sExpSum, + output io_toPostMul_doSubMags, + io_toPostMul_CIsDominant, + output [5:0] io_toPostMul_CDom_CAlignDist, + output [54:0] io_toPostMul_highAlignedSigC, + output io_toPostMul_bit0AlignedSigC +); + + wire rawA_isNaN = (&(io_a[63:62])) & io_a[61]; + wire rawB_isNaN = (&(io_b[63:62])) & io_b[61]; + wire rawC_isNaN = (&(io_c[63:62])) & io_c[61]; + wire signProd = io_a[64] ^ io_b[64] ^ io_op[1]; + wire [13:0] _sExpAlignedProd_T_1 = {2'h0, io_a[63:52]} + {2'h0, io_b[63:52]} - 14'h7C8; + wire doSubMags = signProd ^ io_c[64] ^ io_op[0]; + wire [13:0] _sNatCAlignDist_T = _sExpAlignedProd_T_1 - {2'h0, io_c[63:52]}; + wire isMinCAlign = + ~(|(io_a[63:61])) | ~(|(io_b[63:61])) | $signed(_sNatCAlignDist_T) < 14'sh0; + wire CIsDominant = + (|(io_c[63:61])) & (isMinCAlign | _sNatCAlignDist_T[12:0] < 13'h36); + wire [7:0] CAlignDist = + isMinCAlign + ? 8'h0 + : _sNatCAlignDist_T[12:0] < 13'hA1 ? _sNatCAlignDist_T[7:0] : 8'hA1; + wire [164:0] mainAlignedSigC = + $signed($signed({doSubMags + ? {1'h1, ~(|(io_c[63:61])), ~(io_c[51:0])} + : {1'h0, |(io_c[63:61]), io_c[51:0]}, + {111{doSubMags}}}) >>> CAlignDist); + wire [64:0] reduced4CExtra_shift = $signed(65'sh10000000000000000 >>> CAlignDist[7:2]); + wire [12:0] _GEN = + {|(io_c[51:48]), + |(io_c[47:44]), + |(io_c[43:40]), + |(io_c[39:36]), + |(io_c[35:32]), + |(io_c[31:28]), + |(io_c[27:24]), + |(io_c[23:20]), + |(io_c[19:16]), + |(io_c[15:12]), + |(io_c[11:8]), + |(io_c[7:4]), + |(io_c[3:0])} + & {reduced4CExtra_shift[24], + reduced4CExtra_shift[25], + reduced4CExtra_shift[26], + reduced4CExtra_shift[27], + reduced4CExtra_shift[28], + reduced4CExtra_shift[29], + reduced4CExtra_shift[30], + reduced4CExtra_shift[31], + reduced4CExtra_shift[32], + reduced4CExtra_shift[33], + reduced4CExtra_shift[34], + reduced4CExtra_shift[35], + reduced4CExtra_shift[36]}; + assign io_mulAddA = {|(io_a[63:61]), io_a[51:0]}; + assign io_mulAddB = {|(io_b[63:61]), io_b[51:0]}; + assign io_mulAddC = mainAlignedSigC[108:3]; + assign io_toPostMul_isSigNaNAny = + rawA_isNaN & ~(io_a[51]) | rawB_isNaN & ~(io_b[51]) | rawC_isNaN & ~(io_c[51]); + assign io_toPostMul_isNaNAOrB = rawA_isNaN | rawB_isNaN; + assign io_toPostMul_isInfA = (&(io_a[63:62])) & ~(io_a[61]); + assign io_toPostMul_isZeroA = ~(|(io_a[63:61])); + assign io_toPostMul_isInfB = (&(io_b[63:62])) & ~(io_b[61]); + assign io_toPostMul_isZeroB = ~(|(io_b[63:61])); + assign io_toPostMul_signProd = signProd; + assign io_toPostMul_isNaNC = rawC_isNaN; + assign io_toPostMul_isInfC = (&(io_c[63:62])) & ~(io_c[61]); + assign io_toPostMul_isZeroC = ~(|(io_c[63:61])); + assign io_toPostMul_sExpSum = + CIsDominant ? {1'h0, io_c[63:52]} : _sExpAlignedProd_T_1[12:0] - 13'h35; + assign io_toPostMul_doSubMags = doSubMags; + assign io_toPostMul_CIsDominant = CIsDominant; + assign io_toPostMul_CDom_CAlignDist = CAlignDist[5:0]; + assign io_toPostMul_highAlignedSigC = mainAlignedSigC[163:109]; + assign io_toPostMul_bit0AlignedSigC = + doSubMags + ? (&(mainAlignedSigC[2:0])) & ~(|_GEN) + : (|(mainAlignedSigC[2:0])) | (|_GEN); +endmodule + +module MulAddRecFNToRaw_postMul_e11_s53( + input io_fromPreMul_isSigNaNAny, + io_fromPreMul_isNaNAOrB, + io_fromPreMul_isInfA, + io_fromPreMul_isZeroA, + io_fromPreMul_isInfB, + io_fromPreMul_isZeroB, + io_fromPreMul_signProd, + io_fromPreMul_isNaNC, + io_fromPreMul_isInfC, + io_fromPreMul_isZeroC, + input [12:0] io_fromPreMul_sExpSum, + input io_fromPreMul_doSubMags, + io_fromPreMul_CIsDominant, + input [5:0] io_fromPreMul_CDom_CAlignDist, + input [54:0] io_fromPreMul_highAlignedSigC, + input io_fromPreMul_bit0AlignedSigC, + input [106:0] io_mulAddResult, + input [2:0] io_roundingMode, + output io_invalidExc, + io_rawOut_isNaN, + io_rawOut_isInf, + io_rawOut_isZero, + io_rawOut_sign, + output [12:0] io_rawOut_sExp, + output [55:0] io_rawOut_sig +); + + wire roundingMode_min = io_roundingMode == 3'h2; + wire opSignC = io_fromPreMul_signProd ^ io_fromPreMul_doSubMags; + wire [54:0] _sigSum_T_3 = + io_mulAddResult[106] + ? io_fromPreMul_highAlignedSigC + 55'h1 + : io_fromPreMul_highAlignedSigC; + wire [107:0] CDom_absSigSum = + io_fromPreMul_doSubMags + ? ~{_sigSum_T_3, io_mulAddResult[105:53]} + : {1'h0, + io_fromPreMul_highAlignedSigC[54:53], + _sigSum_T_3[52:0], + io_mulAddResult[105:54]}; + wire [170:0] _CDom_mainSig_T = {63'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist; + wire [16:0] CDom_reduced4SigExtra_shift = + $signed(17'sh10000 >>> ~(io_fromPreMul_CDom_CAlignDist[5:2])); + wire [108:0] notCDom_absSigSum = + _sigSum_T_3[2] + ? ~{_sigSum_T_3[1:0], io_mulAddResult[105:0], io_fromPreMul_bit0AlignedSigC} + : {_sigSum_T_3[1:0], io_mulAddResult[105:0], io_fromPreMul_bit0AlignedSigC} + + {108'h0, io_fromPreMul_doSubMags}; + wire [5:0] notCDom_normDistReduced2 = + notCDom_absSigSum[108] + ? 6'h0 + : (|(notCDom_absSigSum[107:106])) + ? 6'h1 + : (|(notCDom_absSigSum[105:104])) + ? 6'h2 + : (|(notCDom_absSigSum[103:102])) + ? 6'h3 + : (|(notCDom_absSigSum[101:100])) + ? 6'h4 + : (|(notCDom_absSigSum[99:98])) + ? 6'h5 + : (|(notCDom_absSigSum[97:96])) + ? 6'h6 + : (|(notCDom_absSigSum[95:94])) + ? 6'h7 + : (|(notCDom_absSigSum[93:92])) + ? 6'h8 + : (|(notCDom_absSigSum[91:90])) + ? 6'h9 + : (|(notCDom_absSigSum[89:88])) + ? 6'hA + : (|(notCDom_absSigSum[87:86])) + ? 6'hB + : (|(notCDom_absSigSum[85:84])) + ? 6'hC + : (|(notCDom_absSigSum[83:82])) + ? 6'hD + : (|(notCDom_absSigSum[81:80])) + ? 6'hE + : (|(notCDom_absSigSum[79:78])) + ? 6'hF + : (|(notCDom_absSigSum[77:76])) + ? 6'h10 + : (|(notCDom_absSigSum[75:74])) + ? 6'h11 + : (|(notCDom_absSigSum[73:72])) + ? 6'h12 + : (|(notCDom_absSigSum[71:70])) + ? 6'h13 + : (|(notCDom_absSigSum[69:68])) + ? 6'h14 + : (|(notCDom_absSigSum[67:66])) + ? 6'h15 + : (|(notCDom_absSigSum[65:64])) + ? 6'h16 + : (|(notCDom_absSigSum[63:62])) + ? 6'h17 + : (|(notCDom_absSigSum[61:60])) + ? 6'h18 + : (|(notCDom_absSigSum[59:58])) + ? 6'h19 + : (|(notCDom_absSigSum[57:56])) + ? 6'h1A + : (|(notCDom_absSigSum[55:54])) + ? 6'h1B + : (|(notCDom_absSigSum[53:52])) + ? 6'h1C + : (|(notCDom_absSigSum[51:50])) + ? 6'h1D + : (|(notCDom_absSigSum[49:48])) + ? 6'h1E + : (|(notCDom_absSigSum[47:46])) + ? 6'h1F + : (|(notCDom_absSigSum[45:44])) + ? 6'h20 + : (|(notCDom_absSigSum[43:42])) + ? 6'h21 + : (|(notCDom_absSigSum[41:40])) + ? 6'h22 + : (|(notCDom_absSigSum[39:38])) + ? 6'h23 + : (|(notCDom_absSigSum[37:36])) + ? 6'h24 + : (|(notCDom_absSigSum[35:34])) + ? 6'h25 + : (|(notCDom_absSigSum[33:32])) + ? 6'h26 + : (|(notCDom_absSigSum[31:30])) + ? 6'h27 + : (|(notCDom_absSigSum[29:28])) + ? 6'h28 + : (|(notCDom_absSigSum[27:26])) + ? 6'h29 + : (|(notCDom_absSigSum[25:24])) + ? 6'h2A + : (|(notCDom_absSigSum[23:22])) + ? 6'h2B + : (|(notCDom_absSigSum[21:20])) + ? 6'h2C + : (|(notCDom_absSigSum[19:18])) + ? 6'h2D + : (|(notCDom_absSigSum[17:16])) + ? 6'h2E + : (|(notCDom_absSigSum[15:14])) + ? 6'h2F + : (|(notCDom_absSigSum[13:12])) + ? 6'h30 + : (|(notCDom_absSigSum[11:10])) + ? 6'h31 + : (|(notCDom_absSigSum[9:8])) + ? 6'h32 + : (|(notCDom_absSigSum[7:6])) + ? 6'h33 + : (|(notCDom_absSigSum[5:4])) + ? 6'h34 + : (|(notCDom_absSigSum[3:2])) + ? 6'h35 + : 6'h36; + wire [235:0] _notCDom_mainSig_T = + {127'h0, notCDom_absSigSum} << {229'h0, notCDom_normDistReduced2, 1'h0}; + wire [32:0] notCDom_reduced4SigExtra_shift = + $signed(33'sh100000000 >>> ~(notCDom_normDistReduced2[5:1])); + wire notCDom_completeCancellation = _notCDom_mainSig_T[109:108] == 2'h0; + wire notNaN_isInfProd = io_fromPreMul_isInfA | io_fromPreMul_isInfB; + wire notNaN_isInfOut = notNaN_isInfProd | io_fromPreMul_isInfC; + wire notNaN_addZeros = + (io_fromPreMul_isZeroA | io_fromPreMul_isZeroB) & io_fromPreMul_isZeroC; + assign io_invalidExc = + io_fromPreMul_isSigNaNAny | io_fromPreMul_isInfA & io_fromPreMul_isZeroB + | io_fromPreMul_isZeroA & io_fromPreMul_isInfB | ~io_fromPreMul_isNaNAOrB + & notNaN_isInfProd & io_fromPreMul_isInfC & io_fromPreMul_doSubMags; + assign io_rawOut_isNaN = io_fromPreMul_isNaNAOrB | io_fromPreMul_isNaNC; + assign io_rawOut_isInf = notNaN_isInfOut; + assign io_rawOut_isZero = + notNaN_addZeros | ~io_fromPreMul_CIsDominant & notCDom_completeCancellation; + assign io_rawOut_sign = + notNaN_isInfProd & io_fromPreMul_signProd | io_fromPreMul_isInfC & opSignC + | notNaN_addZeros & ~roundingMode_min & io_fromPreMul_signProd & opSignC + | notNaN_addZeros & roundingMode_min & (io_fromPreMul_signProd | opSignC) + | ~notNaN_isInfOut & ~notNaN_addZeros + & (io_fromPreMul_CIsDominant + ? opSignC + : notCDom_completeCancellation + ? roundingMode_min + : io_fromPreMul_signProd ^ _sigSum_T_3[2]); + assign io_rawOut_sExp = + io_fromPreMul_CIsDominant + ? io_fromPreMul_sExpSum - {12'h0, io_fromPreMul_doSubMags} + : io_fromPreMul_sExpSum - {6'h0, notCDom_normDistReduced2, 1'h0}; + assign io_rawOut_sig = + io_fromPreMul_CIsDominant + ? {_CDom_mainSig_T[107:53], + (|(_CDom_mainSig_T[52:50])) + | (|({|(CDom_absSigSum[49:46]), + |(CDom_absSigSum[45:42]), + |(CDom_absSigSum[41:38]), + |(CDom_absSigSum[37:34]), + |(CDom_absSigSum[33:30]), + |(CDom_absSigSum[29:26]), + |(CDom_absSigSum[25:22]), + |(CDom_absSigSum[21:18]), + |(CDom_absSigSum[17:14]), + |(CDom_absSigSum[13:10]), + |(CDom_absSigSum[9:6]), + |(CDom_absSigSum[5:2]), + |(CDom_absSigSum[1:0])} + & {CDom_reduced4SigExtra_shift[1], + CDom_reduced4SigExtra_shift[2], + CDom_reduced4SigExtra_shift[3], + CDom_reduced4SigExtra_shift[4], + CDom_reduced4SigExtra_shift[5], + CDom_reduced4SigExtra_shift[6], + CDom_reduced4SigExtra_shift[7], + CDom_reduced4SigExtra_shift[8], + CDom_reduced4SigExtra_shift[9], + CDom_reduced4SigExtra_shift[10], + CDom_reduced4SigExtra_shift[11], + CDom_reduced4SigExtra_shift[12], + CDom_reduced4SigExtra_shift[13]})) + | (io_fromPreMul_doSubMags + ? io_mulAddResult[52:0] != 53'h1FFFFFFFFFFFFF + : (|(io_mulAddResult[53:0])))} + : {_notCDom_mainSig_T[109:55], + (|(_notCDom_mainSig_T[54:52])) + | (|({|{|(notCDom_absSigSum[51:50]), |(notCDom_absSigSum[49:48])}, + |{|(notCDom_absSigSum[47:46]), |(notCDom_absSigSum[45:44])}, + |{|(notCDom_absSigSum[43:42]), |(notCDom_absSigSum[41:40])}, + |{|(notCDom_absSigSum[39:38]), |(notCDom_absSigSum[37:36])}, + |{|(notCDom_absSigSum[35:34]), |(notCDom_absSigSum[33:32])}, + |{|(notCDom_absSigSum[31:30]), |(notCDom_absSigSum[29:28])}, + |{|(notCDom_absSigSum[27:26]), |(notCDom_absSigSum[25:24])}, + |{|(notCDom_absSigSum[23:22]), |(notCDom_absSigSum[21:20])}, + |{|(notCDom_absSigSum[19:18]), |(notCDom_absSigSum[17:16])}, + |{|(notCDom_absSigSum[15:14]), |(notCDom_absSigSum[13:12])}, + |{|(notCDom_absSigSum[11:10]), |(notCDom_absSigSum[9:8])}, + |{|(notCDom_absSigSum[7:6]), |(notCDom_absSigSum[5:4])}, + |{|(notCDom_absSigSum[3:2]), |(notCDom_absSigSum[1:0])}} + & {notCDom_reduced4SigExtra_shift[1], + notCDom_reduced4SigExtra_shift[2], + notCDom_reduced4SigExtra_shift[3], + notCDom_reduced4SigExtra_shift[4], + notCDom_reduced4SigExtra_shift[5], + notCDom_reduced4SigExtra_shift[6], + notCDom_reduced4SigExtra_shift[7], + notCDom_reduced4SigExtra_shift[8], + notCDom_reduced4SigExtra_shift[9], + notCDom_reduced4SigExtra_shift[10], + notCDom_reduced4SigExtra_shift[11], + notCDom_reduced4SigExtra_shift[12], + notCDom_reduced4SigExtra_shift[13]}))}; +endmodule + +module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53( + input io_invalidExc, + io_in_isNaN, + io_in_isInf, + io_in_isZero, + io_in_sign, + input [12:0] io_in_sExp, + input [55:0] io_in_sig, + input [2:0] io_roundingMode, + output [64:0] io_out, + output [4:0] io_exceptionFlags +); + + wire roundingMode_near_even = io_roundingMode == 3'h0; + wire roundingMode_odd = io_roundingMode == 3'h6; + wire roundMagUp = + io_roundingMode == 3'h2 & io_in_sign | io_roundingMode == 3'h3 & ~io_in_sign; + wire [11:0] _roundMask_T_1 = ~(io_in_sExp[11:0]); + wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> _roundMask_T_1[5:0]); + wire [7:0] _GEN = + {{roundMask_shift[24:21], roundMask_shift[28:27]} & 6'h33, 2'h0} + | {roundMask_shift[28:25], roundMask_shift[32:29]} & 8'h33; + wire [18:0] _GEN_0 = + {roundMask_shift[18:17], + roundMask_shift[20:19], + roundMask_shift[22:21], + _GEN, + roundMask_shift[32:31], + roundMask_shift[34:33], + roundMask_shift[36]} & 19'h55555; + wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> _roundMask_T_1[5:0]); + wire [53:0] _roundMask_T_128 = + _roundMask_T_1[11] + ? (_roundMask_T_1[10] + ? {~(_roundMask_T_1[9] | _roundMask_T_1[8] | _roundMask_T_1[7] + | _roundMask_T_1[6] + ? 51'h0 + : ~{roundMask_shift[13], + roundMask_shift[14], + roundMask_shift[15], + roundMask_shift[16], + roundMask_shift[17], + _GEN_0[18:15] | {roundMask_shift[20:19], roundMask_shift[22:21]} + & 4'h5, + _GEN_0[14:7] | _GEN & 8'h55, + _GEN[1], + _GEN_0[5] | roundMask_shift[31], + roundMask_shift[32], + roundMask_shift[33], + {_GEN_0[2:0], 1'h0} + | {roundMask_shift[36:35], roundMask_shift[38:37]} & 4'h5, + roundMask_shift[38], + roundMask_shift[39], + roundMask_shift[40], + roundMask_shift[41], + roundMask_shift[42], + roundMask_shift[43], + roundMask_shift[44], + roundMask_shift[45], + roundMask_shift[46], + roundMask_shift[47], + roundMask_shift[48], + roundMask_shift[49], + {{roundMask_shift[50:49], roundMask_shift[52]} & 3'h5, 1'h0} + | {roundMask_shift[52:51], roundMask_shift[54:53]} & 4'h5, + roundMask_shift[54], + roundMask_shift[55], + roundMask_shift[56], + roundMask_shift[57], + roundMask_shift[58], + roundMask_shift[59], + roundMask_shift[60], + roundMask_shift[61], + roundMask_shift[62], + roundMask_shift[63]}), + 3'h7} + : {51'h0, + _roundMask_T_1[9] & _roundMask_T_1[8] & _roundMask_T_1[7] + & _roundMask_T_1[6] + ? {roundMask_shift_1[0], roundMask_shift_1[1], roundMask_shift_1[2]} + : 3'h0}) + : 54'h0; + wire _common_underflow_T_4 = _roundMask_T_128[0] | io_in_sig[55]; + wire [54:0] _GEN_1 = {1'h1, ~(_roundMask_T_128[53:1]), ~_common_underflow_T_4}; + wire [54:0] _GEN_2 = {_roundMask_T_128[53:1], _common_underflow_T_4, 1'h1}; + wire [54:0] _roundPosBit_T = io_in_sig[55:1] & _GEN_1 & _GEN_2; + wire [54:0] _anyRoundExtra_T = io_in_sig[54:0] & _GEN_2; + wire anyRound = (|_roundPosBit_T) | (|_anyRoundExtra_T); + wire _overflow_roundMagUp_T = roundingMode_near_even | io_roundingMode == 3'h4; + wire [54:0] roundedSig = + _overflow_roundMagUp_T & (|_roundPosBit_T) | roundMagUp & anyRound + ? {1'h0, io_in_sig[55:2] | {_roundMask_T_128[53:1], _common_underflow_T_4}} + 55'h1 + & ~(roundingMode_near_even & (|_roundPosBit_T) & ~(|_anyRoundExtra_T) + ? {_roundMask_T_128[53:1], _common_underflow_T_4, 1'h1} + : 55'h0) + : {1'h0, io_in_sig[55:2] & {~(_roundMask_T_128[53:1]), ~_common_underflow_T_4}} + | (roundingMode_odd & anyRound ? _GEN_1 & _GEN_2 : 55'h0); + wire [13:0] sRoundedExp = {io_in_sExp[12], io_in_sExp} + {12'h0, roundedSig[54:53]}; + wire common_totalUnderflow = $signed(sRoundedExp) < 14'sh3CE; + wire isNaNOut = io_invalidExc | io_in_isNaN; + wire commonCase = ~isNaNOut & ~io_in_isInf & ~io_in_isZero; + wire overflow = commonCase & $signed(sRoundedExp[13:10]) > 4'sh2; + wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp; + wire pegMinNonzeroMagOut = + commonCase & common_totalUnderflow & (roundMagUp | roundingMode_odd); + wire pegMaxFiniteMagOut = overflow & ~overflow_roundMagUp; + wire notNaN_isInfOut = io_in_isInf | overflow & overflow_roundMagUp; + assign io_out = + {~isNaNOut & io_in_sign, + sRoundedExp[11:0] & ~(io_in_isZero | common_totalUnderflow ? 12'hE00 : 12'h0) + & ~(pegMinNonzeroMagOut ? 12'hC31 : 12'h0) & {1'h1, ~pegMaxFiniteMagOut, 10'h3FF} + & {2'h3, ~notNaN_isInfOut, 9'h1FF} | (pegMinNonzeroMagOut ? 12'h3CE : 12'h0) + | (pegMaxFiniteMagOut ? 12'hBFF : 12'h0) | (notNaN_isInfOut ? 12'hC00 : 12'h0) + | (isNaNOut ? 12'hE00 : 12'h0), + (isNaNOut | io_in_isZero | common_totalUnderflow + ? {isNaNOut, 51'h0} + : io_in_sig[55] ? roundedSig[52:1] : roundedSig[51:0]) + | {52{pegMaxFiniteMagOut}}}; + assign io_exceptionFlags = + {io_invalidExc, + 1'h0, + overflow, + commonCase + & (common_totalUnderflow | anyRound & io_in_sExp[12:11] != 2'h1 + & (io_in_sig[55] ? _roundMask_T_128[1] : _common_underflow_T_4) + & ~(~(io_in_sig[55] ? _roundMask_T_128[2] : _roundMask_T_128[1]) + & (io_in_sig[55] ? roundedSig[54] : roundedSig[53]) & (|_roundPosBit_T) + & (_overflow_roundMagUp_T & (io_in_sig[55] ? io_in_sig[2] : io_in_sig[1]) + | roundMagUp & (io_in_sig[55] & io_in_sig[2] | (|(io_in_sig[1:0])))))), + overflow | commonCase & (common_totalUnderflow | anyRound)}; +endmodule + +module RoundRawFNToRecFN_e11_s53( + input io_invalidExc, + io_in_isNaN, + io_in_isInf, + io_in_isZero, + io_in_sign, + input [12:0] io_in_sExp, + input [55:0] io_in_sig, + input [2:0] io_roundingMode, + output [64:0] io_out, + output [4:0] io_exceptionFlags +); + + RoundAnyRawFNToRecFN_ie11_is55_oe11_os53 roundAnyRawFNToRecFN ( + .io_invalidExc (io_invalidExc), + .io_in_isNaN (io_in_isNaN), + .io_in_isInf (io_in_isInf), + .io_in_isZero (io_in_isZero), + .io_in_sign (io_in_sign), + .io_in_sExp (io_in_sExp), + .io_in_sig (io_in_sig), + .io_roundingMode (io_roundingMode), + .io_out (io_out), + .io_exceptionFlags (io_exceptionFlags) + ); +endmodule + +module MulAddRecFNPipe_l4_e11_s53( + input clock, + reset, + io_validin, + input [1:0] io_op, + input [64:0] io_a, + io_b, + io_c, + input [2:0] io_roundingMode, + output [64:0] io_out, + output [4:0] io_exceptionFlags, + output io_validout +); + + wire _mulAddRecFNToRaw_postMul_io_invalidExc; + wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; + wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; + wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; + wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; + wire [12:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; + wire [55:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; + wire [52:0] _mulAddRecFNToRaw_preMul_io_mulAddA; + wire [52:0] _mulAddRecFNToRaw_preMul_io_mulAddB; + wire [105:0] _mulAddRecFNToRaw_preMul_io_mulAddC; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; + wire [12:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; + wire [5:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; + wire [54:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; + wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; + reg [52:0] preMulMulAddA_pipe_b; + reg [52:0] preMulMulAddB_pipe_b; + reg [105:0] preMulMulAddC_pipe_b; + reg preMulToPostMul_pipe_v; + reg preMulToPostMul_pipe_b_isSigNaNAny; + reg preMulToPostMul_pipe_b_isNaNAOrB; + reg preMulToPostMul_pipe_b_isInfA; + reg preMulToPostMul_pipe_b_isZeroA; + reg preMulToPostMul_pipe_b_isInfB; + reg preMulToPostMul_pipe_b_isZeroB; + reg preMulToPostMul_pipe_b_signProd; + reg preMulToPostMul_pipe_b_isNaNC; + reg preMulToPostMul_pipe_b_isInfC; + reg preMulToPostMul_pipe_b_isZeroC; + reg [12:0] preMulToPostMul_pipe_b_sExpSum; + reg preMulToPostMul_pipe_b_doSubMags; + reg preMulToPostMul_pipe_b_CIsDominant; + reg [5:0] preMulToPostMul_pipe_b_CDom_CAlignDist; + reg [54:0] preMulToPostMul_pipe_b_highAlignedSigC; + reg preMulToPostMul_pipe_b_bit0AlignedSigC; + reg [105:0] mulResultPipe_pipe_b; + reg [105:0] mulAddCPipe_pipe_b; + reg mulToPostMul_pipe_v; + reg mulToPostMul_pipe_b_isSigNaNAny; + reg mulToPostMul_pipe_b_isNaNAOrB; + reg mulToPostMul_pipe_b_isInfA; + reg mulToPostMul_pipe_b_isZeroA; + reg mulToPostMul_pipe_b_isInfB; + reg mulToPostMul_pipe_b_isZeroB; + reg mulToPostMul_pipe_b_signProd; + reg mulToPostMul_pipe_b_isNaNC; + reg mulToPostMul_pipe_b_isInfC; + reg mulToPostMul_pipe_b_isZeroC; + reg [12:0] mulToPostMul_pipe_b_sExpSum; + reg mulToPostMul_pipe_b_doSubMags; + reg mulToPostMul_pipe_b_CIsDominant; + reg [5:0] mulToPostMul_pipe_b_CDom_CAlignDist; + reg [54:0] mulToPostMul_pipe_b_highAlignedSigC; + reg mulToPostMul_pipe_b_bit0AlignedSigC; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC; + reg [12:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant; + reg [5:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist; + reg [54:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC; + reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC; + reg [106:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b; + reg mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v; + reg [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b; + reg mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_v; + reg [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_b; + reg [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_pipe_b; + reg roundingMode_stage0_pipe_v; + reg [2:0] roundingMode_stage0_pipe_b; + reg roundingMode_stage0_pipe_pipe_v; + reg [2:0] roundingMode_stage0_pipe_pipe_b; + reg [2:0] roundingMode_stage0_pipe_pipe_pipe_b; + reg valid_stage0_pipe_v; + reg valid_stage0_pipe_pipe_v; + reg valid_stage0_pipe_pipe_pipe_v; + reg roundRawFNToRecFN_io_invalidExc_pipe_b; + reg roundRawFNToRecFN_io_in_pipe_b_isNaN; + reg roundRawFNToRecFN_io_in_pipe_b_isInf; + reg roundRawFNToRecFN_io_in_pipe_b_isZero; + reg roundRawFNToRecFN_io_in_pipe_b_sign; + reg [12:0] roundRawFNToRecFN_io_in_pipe_b_sExp; + reg [55:0] roundRawFNToRecFN_io_in_pipe_b_sig; + reg [2:0] roundRawFNToRecFN_io_roundingMode_pipe_b; + reg io_validout_pipe_v; + always @(posedge clock) begin + if (io_validin) begin + preMulMulAddA_pipe_b <= _mulAddRecFNToRaw_preMul_io_mulAddA; + preMulMulAddB_pipe_b <= _mulAddRecFNToRaw_preMul_io_mulAddB; + preMulMulAddC_pipe_b <= _mulAddRecFNToRaw_preMul_io_mulAddC; + preMulToPostMul_pipe_b_isSigNaNAny <= + _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; + preMulToPostMul_pipe_b_isNaNAOrB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; + preMulToPostMul_pipe_b_isInfA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; + preMulToPostMul_pipe_b_isZeroA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; + preMulToPostMul_pipe_b_isInfB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; + preMulToPostMul_pipe_b_isZeroB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; + preMulToPostMul_pipe_b_signProd <= _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; + preMulToPostMul_pipe_b_isNaNC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; + preMulToPostMul_pipe_b_isInfC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; + preMulToPostMul_pipe_b_isZeroC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; + preMulToPostMul_pipe_b_sExpSum <= _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; + preMulToPostMul_pipe_b_doSubMags <= _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; + preMulToPostMul_pipe_b_CIsDominant <= + _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; + preMulToPostMul_pipe_b_CDom_CAlignDist <= + _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; + preMulToPostMul_pipe_b_highAlignedSigC <= + _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; + preMulToPostMul_pipe_b_bit0AlignedSigC <= + _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b <= io_roundingMode; + roundingMode_stage0_pipe_b <= io_roundingMode; + end + if (preMulToPostMul_pipe_v) begin + mulResultPipe_pipe_b <= + {53'h0, preMulMulAddA_pipe_b} * {53'h0, preMulMulAddB_pipe_b}; + mulAddCPipe_pipe_b <= preMulMulAddC_pipe_b; + mulToPostMul_pipe_b_isSigNaNAny <= preMulToPostMul_pipe_b_isSigNaNAny; + mulToPostMul_pipe_b_isNaNAOrB <= preMulToPostMul_pipe_b_isNaNAOrB; + mulToPostMul_pipe_b_isInfA <= preMulToPostMul_pipe_b_isInfA; + mulToPostMul_pipe_b_isZeroA <= preMulToPostMul_pipe_b_isZeroA; + mulToPostMul_pipe_b_isInfB <= preMulToPostMul_pipe_b_isInfB; + mulToPostMul_pipe_b_isZeroB <= preMulToPostMul_pipe_b_isZeroB; + mulToPostMul_pipe_b_signProd <= preMulToPostMul_pipe_b_signProd; + mulToPostMul_pipe_b_isNaNC <= preMulToPostMul_pipe_b_isNaNC; + mulToPostMul_pipe_b_isInfC <= preMulToPostMul_pipe_b_isInfC; + mulToPostMul_pipe_b_isZeroC <= preMulToPostMul_pipe_b_isZeroC; + mulToPostMul_pipe_b_sExpSum <= preMulToPostMul_pipe_b_sExpSum; + mulToPostMul_pipe_b_doSubMags <= preMulToPostMul_pipe_b_doSubMags; + mulToPostMul_pipe_b_CIsDominant <= preMulToPostMul_pipe_b_CIsDominant; + mulToPostMul_pipe_b_CDom_CAlignDist <= preMulToPostMul_pipe_b_CDom_CAlignDist; + mulToPostMul_pipe_b_highAlignedSigC <= preMulToPostMul_pipe_b_highAlignedSigC; + mulToPostMul_pipe_b_bit0AlignedSigC <= preMulToPostMul_pipe_b_bit0AlignedSigC; + end + if (mulToPostMul_pipe_v) begin + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny <= + mulToPostMul_pipe_b_isSigNaNAny; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB <= + mulToPostMul_pipe_b_isNaNAOrB; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA <= mulToPostMul_pipe_b_isInfA; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA <= + mulToPostMul_pipe_b_isZeroA; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB <= mulToPostMul_pipe_b_isInfB; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB <= + mulToPostMul_pipe_b_isZeroB; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd <= + mulToPostMul_pipe_b_signProd; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC <= mulToPostMul_pipe_b_isNaNC; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC <= mulToPostMul_pipe_b_isInfC; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC <= + mulToPostMul_pipe_b_isZeroC; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum <= + mulToPostMul_pipe_b_sExpSum; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags <= + mulToPostMul_pipe_b_doSubMags; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant <= + mulToPostMul_pipe_b_CIsDominant; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist <= + mulToPostMul_pipe_b_CDom_CAlignDist; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC <= + mulToPostMul_pipe_b_highAlignedSigC; + mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC <= + mulToPostMul_pipe_b_bit0AlignedSigC; + mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b <= + {1'h0, mulResultPipe_pipe_b} + {1'h0, mulAddCPipe_pipe_b}; + end + if (mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v) + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_b <= + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b; + if (mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_v) + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_pipe_b <= + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_b; + if (roundingMode_stage0_pipe_v) + roundingMode_stage0_pipe_pipe_b <= roundingMode_stage0_pipe_b; + if (roundingMode_stage0_pipe_pipe_v) + roundingMode_stage0_pipe_pipe_pipe_b <= roundingMode_stage0_pipe_pipe_b; + if (valid_stage0_pipe_pipe_pipe_v) begin + roundRawFNToRecFN_io_invalidExc_pipe_b <= _mulAddRecFNToRaw_postMul_io_invalidExc; + roundRawFNToRecFN_io_in_pipe_b_isNaN <= _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; + roundRawFNToRecFN_io_in_pipe_b_isInf <= _mulAddRecFNToRaw_postMul_io_rawOut_isInf; + roundRawFNToRecFN_io_in_pipe_b_isZero <= _mulAddRecFNToRaw_postMul_io_rawOut_isZero; + roundRawFNToRecFN_io_in_pipe_b_sign <= _mulAddRecFNToRaw_postMul_io_rawOut_sign; + roundRawFNToRecFN_io_in_pipe_b_sExp <= _mulAddRecFNToRaw_postMul_io_rawOut_sExp; + roundRawFNToRecFN_io_in_pipe_b_sig <= _mulAddRecFNToRaw_postMul_io_rawOut_sig; + roundRawFNToRecFN_io_roundingMode_pipe_b <= roundingMode_stage0_pipe_pipe_pipe_b; + end + if (reset) begin + preMulToPostMul_pipe_v <= 1'h0; + mulToPostMul_pipe_v <= 1'h0; + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v <= 1'h0; + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_v <= 1'h0; + roundingMode_stage0_pipe_v <= 1'h0; + roundingMode_stage0_pipe_pipe_v <= 1'h0; + valid_stage0_pipe_v <= 1'h0; + valid_stage0_pipe_pipe_v <= 1'h0; + valid_stage0_pipe_pipe_pipe_v <= 1'h0; + io_validout_pipe_v <= 1'h0; + end + else begin + preMulToPostMul_pipe_v <= io_validin; + mulToPostMul_pipe_v <= preMulToPostMul_pipe_v; + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v <= io_validin; + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_v <= + mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v; + roundingMode_stage0_pipe_v <= io_validin; + roundingMode_stage0_pipe_pipe_v <= roundingMode_stage0_pipe_v; + valid_stage0_pipe_v <= io_validin; + valid_stage0_pipe_pipe_v <= valid_stage0_pipe_v; + valid_stage0_pipe_pipe_pipe_v <= valid_stage0_pipe_pipe_v; + io_validout_pipe_v <= valid_stage0_pipe_pipe_pipe_v; + end + end // always @(posedge) + MulAddRecFNToRaw_preMul_e11_s53 mulAddRecFNToRaw_preMul ( + .io_op (io_op), + .io_a (io_a), + .io_b (io_b), + .io_c (io_c), + .io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA), + .io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB), + .io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC), + .io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), + .io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), + .io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), + .io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), + .io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB), + .io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB), + .io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), + .io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), + .io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), + .io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), + .io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), + .io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), + .io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), + .io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), + .io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), + .io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC) + ); + MulAddRecFNToRaw_postMul_e11_s53 mulAddRecFNToRaw_postMul ( + .io_fromPreMul_isSigNaNAny + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny), + .io_fromPreMul_isNaNAOrB + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB), + .io_fromPreMul_isInfA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA), + .io_fromPreMul_isZeroA + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA), + .io_fromPreMul_isInfB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB), + .io_fromPreMul_isZeroB + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB), + .io_fromPreMul_signProd + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd), + .io_fromPreMul_isNaNC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC), + .io_fromPreMul_isInfC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC), + .io_fromPreMul_isZeroC + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC), + .io_fromPreMul_sExpSum + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum), + .io_fromPreMul_doSubMags + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags), + .io_fromPreMul_CIsDominant + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant), + .io_fromPreMul_CDom_CAlignDist + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist), + .io_fromPreMul_highAlignedSigC + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC), + .io_fromPreMul_bit0AlignedSigC + (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC), + .io_mulAddResult (mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b), + .io_roundingMode + (mulAddRecFNToRaw_postMul_io_roundingMode_pipe_pipe_pipe_b), + .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), + .io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), + .io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), + .io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), + .io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), + .io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), + .io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig) + ); + RoundRawFNToRecFN_e11_s53 roundRawFNToRecFN ( + .io_invalidExc (roundRawFNToRecFN_io_invalidExc_pipe_b), + .io_in_isNaN (roundRawFNToRecFN_io_in_pipe_b_isNaN), + .io_in_isInf (roundRawFNToRecFN_io_in_pipe_b_isInf), + .io_in_isZero (roundRawFNToRecFN_io_in_pipe_b_isZero), + .io_in_sign (roundRawFNToRecFN_io_in_pipe_b_sign), + .io_in_sExp (roundRawFNToRecFN_io_in_pipe_b_sExp), + .io_in_sig (roundRawFNToRecFN_io_in_pipe_b_sig), + .io_roundingMode (roundRawFNToRecFN_io_roundingMode_pipe_b), + .io_out (io_out), + .io_exceptionFlags (io_exceptionFlags) + ); + assign io_validout = io_validout_pipe_v; +endmodule + +module FPUFMAPipe_l6_f64( + input clock, + reset, + io_in_valid, + io_in_bits_ren3, + io_in_bits_swap23, + input [2:0] io_in_bits_rm, + input [1:0] io_in_bits_fmaCmd, + input [64:0] io_in_bits_in1, + io_in_bits_in2, + io_in_bits_in3, + output [64:0] io_out_bits_data, + output [4:0] io_out_bits_exc +); + + wire [64:0] _fma_io_out; + wire [4:0] _fma_io_exceptionFlags; + wire _fma_io_validout; + reg valid; + reg [2:0] in_rm; + reg [1:0] in_fmaCmd; + reg [64:0] in_in1; + reg [64:0] in_in2; + reg [64:0] in_in3; + reg [64:0] io_out_pipe_b_data; + reg [4:0] io_out_pipe_b_exc; + always @(posedge clock) begin + valid <= io_in_valid; + if (io_in_valid) begin + in_rm <= io_in_bits_rm; + in_fmaCmd <= io_in_bits_fmaCmd; + in_in1 <= io_in_bits_in1; + in_in2 <= io_in_bits_swap23 ? 65'h8000000000000000 : io_in_bits_in2; + in_in3 <= + io_in_bits_ren3 | io_in_bits_swap23 + ? io_in_bits_in3 + : (io_in_bits_in1 ^ io_in_bits_in2) & 65'h10000000000000000; + end + if (_fma_io_validout) begin + io_out_pipe_b_data <= + ({65{_fma_io_out[63:61] != 3'h7}} | 65'h1EFEFFFFFFFFFFFFF) & _fma_io_out; + io_out_pipe_b_exc <= _fma_io_exceptionFlags; + end + end // always @(posedge) + MulAddRecFNPipe_l4_e11_s53 fma ( + .clock (clock), + .reset (reset), + .io_validin (valid), + .io_op (in_fmaCmd), + .io_a (in_in1), + .io_b (in_in2), + .io_c (in_in3), + .io_roundingMode (in_rm), + .io_out (_fma_io_out), + .io_exceptionFlags (_fma_io_exceptionFlags), + .io_validout (_fma_io_validout) + ); + assign io_out_bits_data = io_out_pipe_b_data; + assign io_out_bits_exc = io_out_pipe_b_exc; +endmodule + +module RoundAnyRawFNToRecFN_ie11_is55_oe5_os11( + input io_invalidExc, + io_in_isNaN, + io_in_isInf, + io_in_isZero, + io_in_sign, + input [12:0] io_in_sExp, + input [55:0] io_in_sig, + input [2:0] io_roundingMode, + output [16:0] io_out, + output [4:0] io_exceptionFlags +); + + wire roundingMode_near_even = io_roundingMode == 3'h0; + wire roundingMode_odd = io_roundingMode == 3'h6; + wire roundMagUp = + io_roundingMode == 3'h2 & io_in_sign | io_roundingMode == 3'h3 & ~io_in_sign; + wire [13:0] sAdjustedExp = {io_in_sExp[12], io_in_sExp} - 14'h7E0; + wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> ~(sAdjustedExp[5:0])); + wire [1:0] _GEN = {roundMask_shift[10], roundMask_shift[11]}; + wire _common_underflow_T_4 = roundMask_shift[18] | io_in_sig[55]; + wire [12:0] _GEN_0 = + {1'h1, + ~(roundMask_shift[7]), + ~(roundMask_shift[8]), + ~(roundMask_shift[9]), + ~_GEN, + ~(roundMask_shift[12]), + ~(roundMask_shift[13]), + ~(roundMask_shift[14]), + ~(roundMask_shift[15]), + ~(roundMask_shift[16]), + ~(roundMask_shift[17]), + ~_common_underflow_T_4}; + wire [12:0] _GEN_1 = + {roundMask_shift[7], + roundMask_shift[8], + roundMask_shift[9], + roundMask_shift[10], + roundMask_shift[11], + roundMask_shift[12], + roundMask_shift[13], + roundMask_shift[14], + roundMask_shift[15], + roundMask_shift[16], + roundMask_shift[17], + _common_underflow_T_4, + 1'h1}; + wire [12:0] _roundPosBit_T = io_in_sig[55:43] & _GEN_0 & _GEN_1; + wire [12:0] _anyRoundExtra_T = {io_in_sig[54:43], |(io_in_sig[42:0])} & _GEN_1; + wire anyRound = (|_roundPosBit_T) | (|_anyRoundExtra_T); + wire _overflow_roundMagUp_T = roundingMode_near_even | io_roundingMode == 3'h4; + wire [12:0] roundedSig = + _overflow_roundMagUp_T & (|_roundPosBit_T) | roundMagUp & anyRound + ? {1'h0, + io_in_sig[55] | roundMask_shift[7], + io_in_sig[54] | roundMask_shift[8], + io_in_sig[53] | roundMask_shift[9], + io_in_sig[52:51] | _GEN, + io_in_sig[50] | roundMask_shift[12], + io_in_sig[49] | roundMask_shift[13], + io_in_sig[48] | roundMask_shift[14], + io_in_sig[47] | roundMask_shift[15], + io_in_sig[46] | roundMask_shift[16], + io_in_sig[45] | roundMask_shift[17], + io_in_sig[44] | _common_underflow_T_4} + 13'h1 + & ~(roundingMode_near_even & (|_roundPosBit_T) & ~(|_anyRoundExtra_T) + ? {roundMask_shift[7], + roundMask_shift[8], + roundMask_shift[9], + roundMask_shift[10], + roundMask_shift[11], + roundMask_shift[12], + roundMask_shift[13], + roundMask_shift[14], + roundMask_shift[15], + roundMask_shift[16], + roundMask_shift[17], + _common_underflow_T_4, + 1'h1} + : 13'h0) + : {1'h0, + io_in_sig[55:44] + & {~(roundMask_shift[7]), + ~(roundMask_shift[8]), + ~(roundMask_shift[9]), + ~_GEN, + ~(roundMask_shift[12]), + ~(roundMask_shift[13]), + ~(roundMask_shift[14]), + ~(roundMask_shift[15]), + ~(roundMask_shift[16]), + ~(roundMask_shift[17]), + ~_common_underflow_T_4}} + | (roundingMode_odd & anyRound ? _GEN_0 & _GEN_1 : 13'h0); + wire [14:0] sRoundedExp = {sAdjustedExp[13], sAdjustedExp} + {13'h0, roundedSig[12:11]}; + wire common_totalUnderflow = $signed(sRoundedExp) < 15'sh8; + wire isNaNOut = io_invalidExc | io_in_isNaN; + wire commonCase = ~isNaNOut & ~io_in_isInf & ~io_in_isZero; + wire overflow = commonCase & $signed(sRoundedExp[14:4]) > 11'sh2; + wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp; + wire pegMinNonzeroMagOut = + commonCase & common_totalUnderflow & (roundMagUp | roundingMode_odd); + wire pegMaxFiniteMagOut = overflow & ~overflow_roundMagUp; + wire notNaN_isInfOut = io_in_isInf | overflow & overflow_roundMagUp; + assign io_out = + {~isNaNOut & io_in_sign, + sRoundedExp[5:0] & ~(io_in_isZero | common_totalUnderflow ? 6'h38 : 6'h0) + & ~(pegMinNonzeroMagOut ? 6'h37 : 6'h0) & {1'h1, ~pegMaxFiniteMagOut, 4'hF} + & {2'h3, ~notNaN_isInfOut, 3'h7} | {2'h0, pegMinNonzeroMagOut, 3'h0} + | (pegMaxFiniteMagOut ? 6'h2F : 6'h0) | (notNaN_isInfOut ? 6'h30 : 6'h0) + | (isNaNOut ? 6'h38 : 6'h0), + (isNaNOut | io_in_isZero | common_totalUnderflow + ? {isNaNOut, 9'h0} + : io_in_sig[55] ? roundedSig[10:1] : roundedSig[9:0]) | {10{pegMaxFiniteMagOut}}}; + assign io_exceptionFlags = + {io_invalidExc, + 1'h0, + overflow, + commonCase + & (common_totalUnderflow | anyRound & $signed(sAdjustedExp[13:5]) < 9'sh1 + & (io_in_sig[55] ? roundMask_shift[17] : _common_underflow_T_4) + & ~(~(io_in_sig[55] ? roundMask_shift[16] : roundMask_shift[17]) + & (io_in_sig[55] ? roundedSig[12] : roundedSig[11]) & (|_roundPosBit_T) + & (_overflow_roundMagUp_T & (io_in_sig[55] ? io_in_sig[44] : io_in_sig[43]) + | roundMagUp + & (io_in_sig[55] & io_in_sig[44] + | (|{io_in_sig[43], |(io_in_sig[42:0])}))))), + overflow | commonCase & (common_totalUnderflow | anyRound)}; +endmodule + +module RoundAnyRawFNToRecFN_ie11_is55_oe8_os24( + input io_invalidExc, + io_in_isNaN, + io_in_isInf, + io_in_isZero, + io_in_sign, + input [12:0] io_in_sExp, + input [55:0] io_in_sig, + input [2:0] io_roundingMode, + output [32:0] io_out, + output [4:0] io_exceptionFlags +); + + wire roundingMode_near_even = io_roundingMode == 3'h0; + wire roundingMode_odd = io_roundingMode == 3'h6; + wire roundMagUp = + io_roundingMode == 3'h2 & io_in_sign | io_roundingMode == 3'h3 & ~io_in_sign; + wire [13:0] sAdjustedExp = {io_in_sExp[12], io_in_sExp} - 14'h700; + wire [8:0] _roundMask_T_1 = ~(sAdjustedExp[8:0]); + wire [64:0] _GEN = {59'h0, _roundMask_T_1[5:0]}; + wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> _GEN); + wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> _GEN); + wire [24:0] _roundMask_T_73 = + _roundMask_T_1[8] + ? (_roundMask_T_1[7] + ? {~(_roundMask_T_1[6] + ? 22'h0 + : ~{roundMask_shift[42], + roundMask_shift[43], + roundMask_shift[44], + roundMask_shift[45], + roundMask_shift[46], + {{roundMask_shift[47:46], roundMask_shift[49]} & 3'h5, 1'h0} + | {roundMask_shift[49:48], roundMask_shift[51:50]} & 4'h5, + roundMask_shift[51], + roundMask_shift[52], + roundMask_shift[53], + roundMask_shift[54], + roundMask_shift[55], + roundMask_shift[56], + roundMask_shift[57], + roundMask_shift[58], + roundMask_shift[59], + roundMask_shift[60], + roundMask_shift[61], + roundMask_shift[62], + roundMask_shift[63]}), + 3'h7} + : {22'h0, + _roundMask_T_1[6] + ? {roundMask_shift_1[0], roundMask_shift_1[1], roundMask_shift_1[2]} + : 3'h0}) + : 25'h0; + wire _common_underflow_T_4 = _roundMask_T_73[0] | io_in_sig[55]; + wire [25:0] _GEN_0 = {1'h1, ~(_roundMask_T_73[24:1]), ~_common_underflow_T_4}; + wire [25:0] _GEN_1 = {_roundMask_T_73[24:1], _common_underflow_T_4, 1'h1}; + wire [25:0] _roundPosBit_T = io_in_sig[55:30] & _GEN_0 & _GEN_1; + wire [25:0] _anyRoundExtra_T = {io_in_sig[54:30], |(io_in_sig[29:0])} & _GEN_1; + wire anyRound = (|_roundPosBit_T) | (|_anyRoundExtra_T); + wire _overflow_roundMagUp_T = roundingMode_near_even | io_roundingMode == 3'h4; + wire [25:0] roundedSig = + _overflow_roundMagUp_T & (|_roundPosBit_T) | roundMagUp & anyRound + ? {1'h0, + io_in_sig[55:32] | _roundMask_T_73[24:1], + io_in_sig[31] | _common_underflow_T_4} + 26'h1 + & ~(roundingMode_near_even & (|_roundPosBit_T) & ~(|_anyRoundExtra_T) + ? {_roundMask_T_73[24:1], _common_underflow_T_4, 1'h1} + : 26'h0) + : {1'h0, io_in_sig[55:31] & {~(_roundMask_T_73[24:1]), ~_common_underflow_T_4}} + | (roundingMode_odd & anyRound ? _GEN_0 & _GEN_1 : 26'h0); + wire [14:0] sRoundedExp = {sAdjustedExp[13], sAdjustedExp} + {13'h0, roundedSig[25:24]}; + wire common_totalUnderflow = $signed(sRoundedExp) < 15'sh6B; + wire isNaNOut = io_invalidExc | io_in_isNaN; + wire commonCase = ~isNaNOut & ~io_in_isInf & ~io_in_isZero; + wire overflow = commonCase & $signed(sRoundedExp[14:7]) > 8'sh2; + wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp; + wire pegMinNonzeroMagOut = + commonCase & common_totalUnderflow & (roundMagUp | roundingMode_odd); + wire pegMaxFiniteMagOut = overflow & ~overflow_roundMagUp; + wire notNaN_isInfOut = io_in_isInf | overflow & overflow_roundMagUp; + assign io_out = + {~isNaNOut & io_in_sign, + sRoundedExp[8:0] & ~(io_in_isZero | common_totalUnderflow ? 9'h1C0 : 9'h0) + & ~(pegMinNonzeroMagOut ? 9'h194 : 9'h0) & {1'h1, ~pegMaxFiniteMagOut, 7'h7F} + & {2'h3, ~notNaN_isInfOut, 6'h3F} | (pegMinNonzeroMagOut ? 9'h6B : 9'h0) + | (pegMaxFiniteMagOut ? 9'h17F : 9'h0) | (notNaN_isInfOut ? 9'h180 : 9'h0) + | (isNaNOut ? 9'h1C0 : 9'h0), + (isNaNOut | io_in_isZero | common_totalUnderflow + ? {isNaNOut, 22'h0} + : io_in_sig[55] ? roundedSig[23:1] : roundedSig[22:0]) + | {23{pegMaxFiniteMagOut}}}; + assign io_exceptionFlags = + {io_invalidExc, + 1'h0, + overflow, + commonCase + & (common_totalUnderflow | anyRound & $signed(sAdjustedExp[13:8]) < 6'sh1 + & (io_in_sig[55] ? _roundMask_T_73[1] : _common_underflow_T_4) + & ~(~(io_in_sig[55] ? _roundMask_T_73[2] : _roundMask_T_73[1]) + & (io_in_sig[55] ? roundedSig[25] : roundedSig[24]) & (|_roundPosBit_T) + & (_overflow_roundMagUp_T & (io_in_sig[55] ? io_in_sig[31] : io_in_sig[30]) + | roundMagUp + & (io_in_sig[55] & io_in_sig[31] + | (|{io_in_sig[30], |(io_in_sig[29:0])}))))), + overflow | commonCase & (common_totalUnderflow | anyRound)}; +endmodule + +module SharedMulAddRecFNPipe( + input clock, + reset, + io_validin, + input [1:0] io_op, + io_typeTag, + input [64:0] io_a, + io_b, + io_c, + input [2:0] io_roundingMode, + output [64:0] io_out_data, + output [4:0] io_out_exc, + output io_validout +); + + wire [64:0] _results_round_2_io_out; + wire [4:0] _results_round_2_io_exceptionFlags; + wire [32:0] _results_round_1_io_out; + wire [4:0] _results_round_1_io_exceptionFlags; + wire [16:0] _results_round_io_out; + wire [4:0] _results_round_io_exceptionFlags; + wire _post_io_invalidExc; + wire _post_io_rawOut_isNaN; + wire _post_io_rawOut_isInf; + wire _post_io_rawOut_isZero; + wire _post_io_rawOut_sign; + wire [12:0] _post_io_rawOut_sExp; + wire [55:0] _post_io_rawOut_sig; + wire [52:0] _pre_io_mulAddA; + wire [52:0] _pre_io_mulAddB; + wire [105:0] _pre_io_mulAddC; + wire _pre_io_toPostMul_isSigNaNAny; + wire _pre_io_toPostMul_isNaNAOrB; + wire _pre_io_toPostMul_isInfA; + wire _pre_io_toPostMul_isZeroA; + wire _pre_io_toPostMul_isInfB; + wire _pre_io_toPostMul_isZeroB; + wire _pre_io_toPostMul_signProd; + wire _pre_io_toPostMul_isNaNC; + wire _pre_io_toPostMul_isInfC; + wire _pre_io_toPostMul_isZeroC; + wire [12:0] _pre_io_toPostMul_sExpSum; + wire _pre_io_toPostMul_doSubMags; + wire _pre_io_toPostMul_CIsDominant; + wire [5:0] _pre_io_toPostMul_CDom_CAlignDist; + wire [54:0] _pre_io_toPostMul_highAlignedSigC; + wire _pre_io_toPostMul_bit0AlignedSigC; + reg [52:0] mulA_pipe_b; + reg [52:0] mulB_pipe_b; + reg [105:0] alignedC_pipe_b; + reg meta_pipe_v; + reg meta_pipe_b_isSigNaNAny; + reg meta_pipe_b_isNaNAOrB; + reg meta_pipe_b_isInfA; + reg meta_pipe_b_isZeroA; + reg meta_pipe_b_isInfB; + reg meta_pipe_b_isZeroB; + reg meta_pipe_b_signProd; + reg meta_pipe_b_isNaNC; + reg meta_pipe_b_isInfC; + reg meta_pipe_b_isZeroC; + reg [12:0] meta_pipe_b_sExpSum; + reg meta_pipe_b_doSubMags; + reg meta_pipe_b_CIsDominant; + reg [5:0] meta_pipe_b_CDom_CAlignDist; + reg [54:0] meta_pipe_b_highAlignedSigC; + reg meta_pipe_b_bit0AlignedSigC; + reg [105:0] product_pipe_b; + reg [105:0] delayedC_pipe_b; + reg delayedMeta_pipe_v; + reg delayedMeta_pipe_b_isSigNaNAny; + reg delayedMeta_pipe_b_isNaNAOrB; + reg delayedMeta_pipe_b_isInfA; + reg delayedMeta_pipe_b_isZeroA; + reg delayedMeta_pipe_b_isInfB; + reg delayedMeta_pipe_b_isZeroB; + reg delayedMeta_pipe_b_signProd; + reg delayedMeta_pipe_b_isNaNC; + reg delayedMeta_pipe_b_isInfC; + reg delayedMeta_pipe_b_isZeroC; + reg [12:0] delayedMeta_pipe_b_sExpSum; + reg delayedMeta_pipe_b_doSubMags; + reg delayedMeta_pipe_b_CIsDominant; + reg [5:0] delayedMeta_pipe_b_CDom_CAlignDist; + reg [54:0] delayedMeta_pipe_b_highAlignedSigC; + reg delayedMeta_pipe_b_bit0AlignedSigC; + reg post_io_fromPreMul_pipe_b_isSigNaNAny; + reg post_io_fromPreMul_pipe_b_isNaNAOrB; + reg post_io_fromPreMul_pipe_b_isInfA; + reg post_io_fromPreMul_pipe_b_isZeroA; + reg post_io_fromPreMul_pipe_b_isInfB; + reg post_io_fromPreMul_pipe_b_isZeroB; + reg post_io_fromPreMul_pipe_b_signProd; + reg post_io_fromPreMul_pipe_b_isNaNC; + reg post_io_fromPreMul_pipe_b_isInfC; + reg post_io_fromPreMul_pipe_b_isZeroC; + reg [12:0] post_io_fromPreMul_pipe_b_sExpSum; + reg post_io_fromPreMul_pipe_b_doSubMags; + reg post_io_fromPreMul_pipe_b_CIsDominant; + reg [5:0] post_io_fromPreMul_pipe_b_CDom_CAlignDist; + reg [54:0] post_io_fromPreMul_pipe_b_highAlignedSigC; + reg post_io_fromPreMul_pipe_b_bit0AlignedSigC; + reg [106:0] post_io_mulAddResult_pipe_b; + reg rmPost_pipe_v; + reg [2:0] rmPost_pipe_b; + reg rmPost_pipe_pipe_v; + reg [2:0] rmPost_pipe_pipe_b; + reg rmPost_pipe_pipe_pipe_v; + reg [2:0] rmPost_pipe_pipe_pipe_b; + reg raw_pipe_b_isNaN; + reg raw_pipe_b_isInf; + reg raw_pipe_b_isZero; + reg raw_pipe_b_sign; + reg [12:0] raw_pipe_b_sExp; + reg [55:0] raw_pipe_b_sig; + reg invalid_pipe_b; + reg rm_pipe_v; + reg [2:0] rm_pipe_b; + reg rm_pipe_pipe_v; + reg [2:0] rm_pipe_pipe_b; + reg rm_pipe_pipe_pipe_v; + reg [2:0] rm_pipe_pipe_pipe_b; + reg [2:0] rm_pipe_pipe_pipe_pipe_b; + reg tag_pipe_v; + reg [1:0] tag_pipe_b; + reg tag_pipe_pipe_v; + reg [1:0] tag_pipe_pipe_b; + reg tag_pipe_pipe_pipe_v; + reg [1:0] tag_pipe_pipe_pipe_b; + reg tag_pipe_pipe_pipe_pipe_v; + reg [1:0] tag_pipe_pipe_pipe_pipe_b; + wire [64:0] results_0_data = {48'h0, _results_round_io_out}; + wire [3:0][64:0] _GEN = + {{results_0_data}, + {({65{_results_round_2_io_out[63:61] != 3'h7}} | 65'h1EFEFFFFFFFFFFFFF) + & _results_round_2_io_out}, + {{32'h0, + ({33{_results_round_1_io_out[31:29] != 3'h7}} | 33'h1EF7FFFFF) + & _results_round_1_io_out}}, + {results_0_data}}; + wire [3:0][4:0] _GEN_0 = + {{_results_round_io_exceptionFlags}, + {_results_round_2_io_exceptionFlags}, + {_results_round_1_io_exceptionFlags}, + {_results_round_io_exceptionFlags}}; + always @(posedge clock) begin + if (io_validin) begin + mulA_pipe_b <= _pre_io_mulAddA; + mulB_pipe_b <= _pre_io_mulAddB; + alignedC_pipe_b <= _pre_io_mulAddC; + meta_pipe_b_isSigNaNAny <= _pre_io_toPostMul_isSigNaNAny; + meta_pipe_b_isNaNAOrB <= _pre_io_toPostMul_isNaNAOrB; + meta_pipe_b_isInfA <= _pre_io_toPostMul_isInfA; + meta_pipe_b_isZeroA <= _pre_io_toPostMul_isZeroA; + meta_pipe_b_isInfB <= _pre_io_toPostMul_isInfB; + meta_pipe_b_isZeroB <= _pre_io_toPostMul_isZeroB; + meta_pipe_b_signProd <= _pre_io_toPostMul_signProd; + meta_pipe_b_isNaNC <= _pre_io_toPostMul_isNaNC; + meta_pipe_b_isInfC <= _pre_io_toPostMul_isInfC; + meta_pipe_b_isZeroC <= _pre_io_toPostMul_isZeroC; + meta_pipe_b_sExpSum <= _pre_io_toPostMul_sExpSum; + meta_pipe_b_doSubMags <= _pre_io_toPostMul_doSubMags; + meta_pipe_b_CIsDominant <= _pre_io_toPostMul_CIsDominant; + meta_pipe_b_CDom_CAlignDist <= _pre_io_toPostMul_CDom_CAlignDist; + meta_pipe_b_highAlignedSigC <= _pre_io_toPostMul_highAlignedSigC; + meta_pipe_b_bit0AlignedSigC <= _pre_io_toPostMul_bit0AlignedSigC; + rmPost_pipe_b <= io_roundingMode; + rm_pipe_b <= io_roundingMode; + tag_pipe_b <= io_typeTag; + end + if (meta_pipe_v) begin + product_pipe_b <= {53'h0, mulA_pipe_b} * {53'h0, mulB_pipe_b}; + delayedC_pipe_b <= alignedC_pipe_b; + delayedMeta_pipe_b_isSigNaNAny <= meta_pipe_b_isSigNaNAny; + delayedMeta_pipe_b_isNaNAOrB <= meta_pipe_b_isNaNAOrB; + delayedMeta_pipe_b_isInfA <= meta_pipe_b_isInfA; + delayedMeta_pipe_b_isZeroA <= meta_pipe_b_isZeroA; + delayedMeta_pipe_b_isInfB <= meta_pipe_b_isInfB; + delayedMeta_pipe_b_isZeroB <= meta_pipe_b_isZeroB; + delayedMeta_pipe_b_signProd <= meta_pipe_b_signProd; + delayedMeta_pipe_b_isNaNC <= meta_pipe_b_isNaNC; + delayedMeta_pipe_b_isInfC <= meta_pipe_b_isInfC; + delayedMeta_pipe_b_isZeroC <= meta_pipe_b_isZeroC; + delayedMeta_pipe_b_sExpSum <= meta_pipe_b_sExpSum; + delayedMeta_pipe_b_doSubMags <= meta_pipe_b_doSubMags; + delayedMeta_pipe_b_CIsDominant <= meta_pipe_b_CIsDominant; + delayedMeta_pipe_b_CDom_CAlignDist <= meta_pipe_b_CDom_CAlignDist; + delayedMeta_pipe_b_highAlignedSigC <= meta_pipe_b_highAlignedSigC; + delayedMeta_pipe_b_bit0AlignedSigC <= meta_pipe_b_bit0AlignedSigC; + end + if (delayedMeta_pipe_v) begin + post_io_fromPreMul_pipe_b_isSigNaNAny <= delayedMeta_pipe_b_isSigNaNAny; + post_io_fromPreMul_pipe_b_isNaNAOrB <= delayedMeta_pipe_b_isNaNAOrB; + post_io_fromPreMul_pipe_b_isInfA <= delayedMeta_pipe_b_isInfA; + post_io_fromPreMul_pipe_b_isZeroA <= delayedMeta_pipe_b_isZeroA; + post_io_fromPreMul_pipe_b_isInfB <= delayedMeta_pipe_b_isInfB; + post_io_fromPreMul_pipe_b_isZeroB <= delayedMeta_pipe_b_isZeroB; + post_io_fromPreMul_pipe_b_signProd <= delayedMeta_pipe_b_signProd; + post_io_fromPreMul_pipe_b_isNaNC <= delayedMeta_pipe_b_isNaNC; + post_io_fromPreMul_pipe_b_isInfC <= delayedMeta_pipe_b_isInfC; + post_io_fromPreMul_pipe_b_isZeroC <= delayedMeta_pipe_b_isZeroC; + post_io_fromPreMul_pipe_b_sExpSum <= delayedMeta_pipe_b_sExpSum; + post_io_fromPreMul_pipe_b_doSubMags <= delayedMeta_pipe_b_doSubMags; + post_io_fromPreMul_pipe_b_CIsDominant <= delayedMeta_pipe_b_CIsDominant; + post_io_fromPreMul_pipe_b_CDom_CAlignDist <= delayedMeta_pipe_b_CDom_CAlignDist; + post_io_fromPreMul_pipe_b_highAlignedSigC <= delayedMeta_pipe_b_highAlignedSigC; + post_io_fromPreMul_pipe_b_bit0AlignedSigC <= delayedMeta_pipe_b_bit0AlignedSigC; + post_io_mulAddResult_pipe_b <= {1'h0, product_pipe_b} + {1'h0, delayedC_pipe_b}; + end + if (rmPost_pipe_v) + rmPost_pipe_pipe_b <= rmPost_pipe_b; + if (rmPost_pipe_pipe_v) + rmPost_pipe_pipe_pipe_b <= rmPost_pipe_pipe_b; + if (rmPost_pipe_pipe_pipe_v) begin + raw_pipe_b_isNaN <= _post_io_rawOut_isNaN; + raw_pipe_b_isInf <= _post_io_rawOut_isInf; + raw_pipe_b_isZero <= _post_io_rawOut_isZero; + raw_pipe_b_sign <= _post_io_rawOut_sign; + raw_pipe_b_sExp <= _post_io_rawOut_sExp; + raw_pipe_b_sig <= _post_io_rawOut_sig; + invalid_pipe_b <= _post_io_invalidExc; + end + if (rm_pipe_v) + rm_pipe_pipe_b <= rm_pipe_b; + if (rm_pipe_pipe_v) + rm_pipe_pipe_pipe_b <= rm_pipe_pipe_b; + if (rm_pipe_pipe_pipe_v) + rm_pipe_pipe_pipe_pipe_b <= rm_pipe_pipe_pipe_b; + if (tag_pipe_v) + tag_pipe_pipe_b <= tag_pipe_b; + if (tag_pipe_pipe_v) + tag_pipe_pipe_pipe_b <= tag_pipe_pipe_b; + if (tag_pipe_pipe_pipe_v) + tag_pipe_pipe_pipe_pipe_b <= tag_pipe_pipe_pipe_b; + if (reset) begin + meta_pipe_v <= 1'h0; + delayedMeta_pipe_v <= 1'h0; + rmPost_pipe_v <= 1'h0; + rmPost_pipe_pipe_v <= 1'h0; + rmPost_pipe_pipe_pipe_v <= 1'h0; + rm_pipe_v <= 1'h0; + rm_pipe_pipe_v <= 1'h0; + rm_pipe_pipe_pipe_v <= 1'h0; + tag_pipe_v <= 1'h0; + tag_pipe_pipe_v <= 1'h0; + tag_pipe_pipe_pipe_v <= 1'h0; + tag_pipe_pipe_pipe_pipe_v <= 1'h0; + end + else begin + meta_pipe_v <= io_validin; + delayedMeta_pipe_v <= meta_pipe_v; + rmPost_pipe_v <= io_validin; + rmPost_pipe_pipe_v <= rmPost_pipe_v; + rmPost_pipe_pipe_pipe_v <= rmPost_pipe_pipe_v; + rm_pipe_v <= io_validin; + rm_pipe_pipe_v <= rm_pipe_v; + rm_pipe_pipe_pipe_v <= rm_pipe_pipe_v; + tag_pipe_v <= io_validin; + tag_pipe_pipe_v <= tag_pipe_v; + tag_pipe_pipe_pipe_v <= tag_pipe_pipe_v; + tag_pipe_pipe_pipe_pipe_v <= tag_pipe_pipe_pipe_v; + end + end // always @(posedge) + MulAddRecFNToRaw_preMul_e11_s53 pre ( + .io_op (io_op), + .io_a (io_a), + .io_b (io_b), + .io_c (io_c), + .io_mulAddA (_pre_io_mulAddA), + .io_mulAddB (_pre_io_mulAddB), + .io_mulAddC (_pre_io_mulAddC), + .io_toPostMul_isSigNaNAny (_pre_io_toPostMul_isSigNaNAny), + .io_toPostMul_isNaNAOrB (_pre_io_toPostMul_isNaNAOrB), + .io_toPostMul_isInfA (_pre_io_toPostMul_isInfA), + .io_toPostMul_isZeroA (_pre_io_toPostMul_isZeroA), + .io_toPostMul_isInfB (_pre_io_toPostMul_isInfB), + .io_toPostMul_isZeroB (_pre_io_toPostMul_isZeroB), + .io_toPostMul_signProd (_pre_io_toPostMul_signProd), + .io_toPostMul_isNaNC (_pre_io_toPostMul_isNaNC), + .io_toPostMul_isInfC (_pre_io_toPostMul_isInfC), + .io_toPostMul_isZeroC (_pre_io_toPostMul_isZeroC), + .io_toPostMul_sExpSum (_pre_io_toPostMul_sExpSum), + .io_toPostMul_doSubMags (_pre_io_toPostMul_doSubMags), + .io_toPostMul_CIsDominant (_pre_io_toPostMul_CIsDominant), + .io_toPostMul_CDom_CAlignDist (_pre_io_toPostMul_CDom_CAlignDist), + .io_toPostMul_highAlignedSigC (_pre_io_toPostMul_highAlignedSigC), + .io_toPostMul_bit0AlignedSigC (_pre_io_toPostMul_bit0AlignedSigC) + ); + MulAddRecFNToRaw_postMul_e11_s53 post ( + .io_fromPreMul_isSigNaNAny (post_io_fromPreMul_pipe_b_isSigNaNAny), + .io_fromPreMul_isNaNAOrB (post_io_fromPreMul_pipe_b_isNaNAOrB), + .io_fromPreMul_isInfA (post_io_fromPreMul_pipe_b_isInfA), + .io_fromPreMul_isZeroA (post_io_fromPreMul_pipe_b_isZeroA), + .io_fromPreMul_isInfB (post_io_fromPreMul_pipe_b_isInfB), + .io_fromPreMul_isZeroB (post_io_fromPreMul_pipe_b_isZeroB), + .io_fromPreMul_signProd (post_io_fromPreMul_pipe_b_signProd), + .io_fromPreMul_isNaNC (post_io_fromPreMul_pipe_b_isNaNC), + .io_fromPreMul_isInfC (post_io_fromPreMul_pipe_b_isInfC), + .io_fromPreMul_isZeroC (post_io_fromPreMul_pipe_b_isZeroC), + .io_fromPreMul_sExpSum (post_io_fromPreMul_pipe_b_sExpSum), + .io_fromPreMul_doSubMags (post_io_fromPreMul_pipe_b_doSubMags), + .io_fromPreMul_CIsDominant (post_io_fromPreMul_pipe_b_CIsDominant), + .io_fromPreMul_CDom_CAlignDist (post_io_fromPreMul_pipe_b_CDom_CAlignDist), + .io_fromPreMul_highAlignedSigC (post_io_fromPreMul_pipe_b_highAlignedSigC), + .io_fromPreMul_bit0AlignedSigC (post_io_fromPreMul_pipe_b_bit0AlignedSigC), + .io_mulAddResult (post_io_mulAddResult_pipe_b), + .io_roundingMode (rmPost_pipe_pipe_pipe_b), + .io_invalidExc (_post_io_invalidExc), + .io_rawOut_isNaN (_post_io_rawOut_isNaN), + .io_rawOut_isInf (_post_io_rawOut_isInf), + .io_rawOut_isZero (_post_io_rawOut_isZero), + .io_rawOut_sign (_post_io_rawOut_sign), + .io_rawOut_sExp (_post_io_rawOut_sExp), + .io_rawOut_sig (_post_io_rawOut_sig) + ); + RoundAnyRawFNToRecFN_ie11_is55_oe5_os11 results_round ( + .io_invalidExc (invalid_pipe_b), + .io_in_isNaN (raw_pipe_b_isNaN), + .io_in_isInf (raw_pipe_b_isInf), + .io_in_isZero (raw_pipe_b_isZero), + .io_in_sign (raw_pipe_b_sign), + .io_in_sExp (raw_pipe_b_sExp), + .io_in_sig (raw_pipe_b_sig), + .io_roundingMode (rm_pipe_pipe_pipe_pipe_b), + .io_out (_results_round_io_out), + .io_exceptionFlags (_results_round_io_exceptionFlags) + ); + RoundAnyRawFNToRecFN_ie11_is55_oe8_os24 results_round_1 ( + .io_invalidExc (invalid_pipe_b), + .io_in_isNaN (raw_pipe_b_isNaN), + .io_in_isInf (raw_pipe_b_isInf), + .io_in_isZero (raw_pipe_b_isZero), + .io_in_sign (raw_pipe_b_sign), + .io_in_sExp (raw_pipe_b_sExp), + .io_in_sig (raw_pipe_b_sig), + .io_roundingMode (rm_pipe_pipe_pipe_pipe_b), + .io_out (_results_round_1_io_out), + .io_exceptionFlags (_results_round_1_io_exceptionFlags) + ); + RoundAnyRawFNToRecFN_ie11_is55_oe11_os53 results_round_2 ( + .io_invalidExc (invalid_pipe_b), + .io_in_isNaN (raw_pipe_b_isNaN), + .io_in_isInf (raw_pipe_b_isInf), + .io_in_isZero (raw_pipe_b_isZero), + .io_in_sign (raw_pipe_b_sign), + .io_in_sExp (raw_pipe_b_sExp), + .io_in_sig (raw_pipe_b_sig), + .io_roundingMode (rm_pipe_pipe_pipe_pipe_b), + .io_out (_results_round_2_io_out), + .io_exceptionFlags (_results_round_2_io_exceptionFlags) + ); + assign io_out_data = _GEN[tag_pipe_pipe_pipe_pipe_b]; + assign io_out_exc = _GEN_0[tag_pipe_pipe_pipe_pipe_b]; + assign io_validout = tag_pipe_pipe_pipe_pipe_v; +endmodule + +module FPUSharedFMAPipe( + input clock, + reset, + io_in_valid, + io_in_bits_ren3, + io_in_bits_swap23, + input [1:0] io_in_bits_typeTagOut, + input [2:0] io_in_bits_rm, + input [1:0] io_in_bits_fmaCmd, + input [64:0] io_in_bits_in1, + io_in_bits_in2, + io_in_bits_in3, + output io_out_valid, + output [64:0] io_out_bits_data, + output [4:0] io_out_bits_exc +); + + wire [64:0] _fma_io_out_data; + wire [4:0] _fma_io_out_exc; + wire _fma_io_validout; + reg valid; + reg [1:0] in_typeTagOut; + reg [2:0] in_rm; + reg [1:0] in_fmaCmd; + reg [64:0] in_in1; + reg [64:0] in_in2; + reg [64:0] in_in3; + reg io_out_pipe_v; + reg [64:0] io_out_pipe_b_data; + reg [4:0] io_out_pipe_b_exc; + always @(posedge clock) begin + if (reset) begin + valid <= 1'h0; + io_out_pipe_v <= 1'h0; + end + else begin + valid <= io_in_valid; + io_out_pipe_v <= _fma_io_validout; + end + if (io_in_valid) begin + automatic logic [11:0] _a_expOut_commonCase_T_2 = + {6'h0, io_in_bits_in1[15:10]} + 12'h7E0; + automatic logic [64:0] _a_T_1 = + {io_in_bits_in1[16], + io_in_bits_in1[15:13] == 3'h0 | io_in_bits_in1[15:13] > 3'h5 + ? {io_in_bits_in1[15:13], _a_expOut_commonCase_T_2[8:0]} + : _a_expOut_commonCase_T_2, + io_in_bits_in1[9:0], + 42'h0}; + automatic logic [11:0] _a_expOut_commonCase_T_5 = + {3'h0, io_in_bits_in1[31:23]} + 12'h700; + automatic logic [11:0] _b_expOut_commonCase_T_2 = + {6'h0, io_in_bits_in2[15:10]} + 12'h7E0; + automatic logic [64:0] _b_T_1 = + {io_in_bits_in2[16], + io_in_bits_in2[15:13] == 3'h0 | io_in_bits_in2[15:13] > 3'h5 + ? {io_in_bits_in2[15:13], _b_expOut_commonCase_T_2[8:0]} + : _b_expOut_commonCase_T_2, + io_in_bits_in2[9:0], + 42'h0}; + automatic logic [11:0] _b_expOut_commonCase_T_5 = + {3'h0, io_in_bits_in2[31:23]} + 12'h700; + automatic logic [11:0] _c_expOut_commonCase_T_2 = + {6'h0, io_in_bits_in3[15:10]} + 12'h7E0; + automatic logic [64:0] _c_T_1 = + {io_in_bits_in3[16], + io_in_bits_in3[15:13] == 3'h0 | io_in_bits_in3[15:13] > 3'h5 + ? {io_in_bits_in3[15:13], _c_expOut_commonCase_T_2[8:0]} + : _c_expOut_commonCase_T_2, + io_in_bits_in3[9:0], + 42'h0}; + automatic logic [11:0] _c_expOut_commonCase_T_5 = + {3'h0, io_in_bits_in3[31:23]} + 12'h700; + automatic logic [3:0][64:0] _GEN = + {{_a_T_1}, + {io_in_bits_in1}, + {{io_in_bits_in1[32], + io_in_bits_in1[31:29] == 3'h0 | io_in_bits_in1[31:29] > 3'h5 + ? {io_in_bits_in1[31:29], _a_expOut_commonCase_T_5[8:0]} + : _a_expOut_commonCase_T_5, + io_in_bits_in1[22:0], + 29'h0}}, + {_a_T_1}}; + automatic logic [3:0][64:0] _GEN_0 = + {{_b_T_1}, + {io_in_bits_in2}, + {{io_in_bits_in2[32], + io_in_bits_in2[31:29] == 3'h0 | io_in_bits_in2[31:29] > 3'h5 + ? {io_in_bits_in2[31:29], _b_expOut_commonCase_T_5[8:0]} + : _b_expOut_commonCase_T_5, + io_in_bits_in2[22:0], + 29'h0}}, + {_b_T_1}}; + automatic logic [3:0][64:0] _GEN_1 = + {{_c_T_1}, + {io_in_bits_in3}, + {{io_in_bits_in3[32], + io_in_bits_in3[31:29] == 3'h0 | io_in_bits_in3[31:29] > 3'h5 + ? {io_in_bits_in3[31:29], _c_expOut_commonCase_T_5[8:0]} + : _c_expOut_commonCase_T_5, + io_in_bits_in3[22:0], + 29'h0}}, + {_c_T_1}}; + in_typeTagOut <= io_in_bits_typeTagOut; + in_rm <= io_in_bits_rm; + in_fmaCmd <= io_in_bits_fmaCmd; + in_in1 <= _GEN[io_in_bits_typeTagOut]; + in_in2 <= io_in_bits_swap23 ? 65'h8000000000000000 : _GEN_0[io_in_bits_typeTagOut]; + in_in3 <= + io_in_bits_ren3 | io_in_bits_swap23 + ? _GEN_1[io_in_bits_typeTagOut] + : (_GEN[io_in_bits_typeTagOut] ^ _GEN_0[io_in_bits_typeTagOut]) + & 65'h10000000000000000; + end + if (_fma_io_validout) begin + io_out_pipe_b_data <= _fma_io_out_data; + io_out_pipe_b_exc <= _fma_io_out_exc; + end + end // always @(posedge) + SharedMulAddRecFNPipe fma ( + .clock (clock), + .reset (reset), + .io_validin (valid), + .io_op (in_fmaCmd), + .io_typeTag (in_typeTagOut), + .io_a (in_in1), + .io_b (in_in2), + .io_c (in_in3), + .io_roundingMode (in_rm), + .io_out_data (_fma_io_out_data), + .io_out_exc (_fma_io_out_exc), + .io_validout (_fma_io_validout) + ); + assign io_out_valid = io_out_pipe_v; + assign io_out_bits_data = io_out_pipe_b_data; + assign io_out_bits_exc = io_out_pipe_b_exc; +endmodule + +module FmaPrecisionCheck( + input clock, + reset, + valid, + input [1:0] tag, + kind, + op, + input [2:0] rm, + input [63:0] a, + b, + c, + output [63:0] expected, + actual, + output [4:0] expectedFlags, + actualFlags, + output outValid, + equal +); + + wire _shared_io_out_valid; + wire [64:0] _shared_io_out_bits_data; + wire [4:0] _shared_io_out_bits_exc; + wire [64:0] _refs_unit_2_io_out_bits_data; + wire [4:0] _refs_unit_2_io_out_bits_exc; + wire _refs_unit_1_io_out_valid; + wire [64:0] _refs_unit_1_io_out_bits_data; + wire [4:0] _refs_unit_1_io_out_bits_exc; + wire _refs_unit_io_out_valid; + wire [64:0] _refs_unit_io_out_bits_data; + wire [4:0] _refs_unit_io_out_bits_exc; + wire [3:0][1:0] _GEN = '{2'h0, 2'h2, 2'h1, 2'h0}; + wire inputs_2_ren3 = kind == 2'h0; + wire inputs_2_swap23 = kind == 2'h1; + wire inputs_in_in1_rawIn_isZeroExpIn = a[14:10] == 5'h0; + wire [3:0] inputs_in_in1_rawIn_normDist = + a[9] + ? 4'h0 + : a[8] + ? 4'h1 + : a[7] + ? 4'h2 + : a[6] + ? 4'h3 + : a[5] + ? 4'h4 + : a[4] ? 4'h5 : a[3] ? 4'h6 : a[2] ? 4'h7 : {3'h4, ~(a[1])}; + wire [24:0] _inputs_in_in1_rawIn_subnormFract_T = + {15'h0, a[9:0]} << inputs_in_in1_rawIn_normDist; + wire [5:0] _inputs_in_in1_rawIn_adjustedExp_T_4 = + (inputs_in_in1_rawIn_isZeroExpIn + ? {2'h3, ~inputs_in_in1_rawIn_normDist} + : {1'h0, a[14:10]}) + {4'h4, inputs_in_in1_rawIn_isZeroExpIn ? 2'h2 : 2'h1}; + wire [2:0] _inputs_in_in1_T_2 = + inputs_in_in1_rawIn_isZeroExpIn & ~(|(a[9:0])) + ? 3'h0 + : _inputs_in_in1_rawIn_adjustedExp_T_4[5:3]; + wire [64:0] inputs_0_in1 = + {48'h0, + a[15], + _inputs_in_in1_T_2[2:1], + _inputs_in_in1_T_2[0] | (&(_inputs_in_in1_rawIn_adjustedExp_T_4[5:4])) & (|(a[9:0])), + _inputs_in_in1_rawIn_adjustedExp_T_4[2:0], + inputs_in_in1_rawIn_isZeroExpIn + ? {_inputs_in_in1_rawIn_subnormFract_T[8:0], 1'h0} + : a[9:0]}; + wire inputs_in_in2_rawIn_isZeroExpIn = b[14:10] == 5'h0; + wire [3:0] inputs_in_in2_rawIn_normDist = + b[9] + ? 4'h0 + : b[8] + ? 4'h1 + : b[7] + ? 4'h2 + : b[6] + ? 4'h3 + : b[5] + ? 4'h4 + : b[4] ? 4'h5 : b[3] ? 4'h6 : b[2] ? 4'h7 : {3'h4, ~(b[1])}; + wire [24:0] _inputs_in_in2_rawIn_subnormFract_T = + {15'h0, b[9:0]} << inputs_in_in2_rawIn_normDist; + wire [5:0] _inputs_in_in2_rawIn_adjustedExp_T_4 = + (inputs_in_in2_rawIn_isZeroExpIn + ? {2'h3, ~inputs_in_in2_rawIn_normDist} + : {1'h0, b[14:10]}) + {4'h4, inputs_in_in2_rawIn_isZeroExpIn ? 2'h2 : 2'h1}; + wire [2:0] _inputs_in_in2_T_2 = + inputs_in_in2_rawIn_isZeroExpIn & ~(|(b[9:0])) + ? 3'h0 + : _inputs_in_in2_rawIn_adjustedExp_T_4[5:3]; + wire [64:0] inputs_0_in2 = + {48'h0, + b[15], + _inputs_in_in2_T_2[2:1], + _inputs_in_in2_T_2[0] | (&(_inputs_in_in2_rawIn_adjustedExp_T_4[5:4])) & (|(b[9:0])), + _inputs_in_in2_rawIn_adjustedExp_T_4[2:0], + inputs_in_in2_rawIn_isZeroExpIn + ? {_inputs_in_in2_rawIn_subnormFract_T[8:0], 1'h0} + : b[9:0]}; + wire inputs_in_in3_rawIn_isZeroExpIn = c[14:10] == 5'h0; + wire [3:0] inputs_in_in3_rawIn_normDist = + c[9] + ? 4'h0 + : c[8] + ? 4'h1 + : c[7] + ? 4'h2 + : c[6] + ? 4'h3 + : c[5] + ? 4'h4 + : c[4] ? 4'h5 : c[3] ? 4'h6 : c[2] ? 4'h7 : {3'h4, ~(c[1])}; + wire [24:0] _inputs_in_in3_rawIn_subnormFract_T = + {15'h0, c[9:0]} << inputs_in_in3_rawIn_normDist; + wire [5:0] _inputs_in_in3_rawIn_adjustedExp_T_4 = + (inputs_in_in3_rawIn_isZeroExpIn + ? {2'h3, ~inputs_in_in3_rawIn_normDist} + : {1'h0, c[14:10]}) + {4'h4, inputs_in_in3_rawIn_isZeroExpIn ? 2'h2 : 2'h1}; + wire [2:0] _inputs_in_in3_T_2 = + inputs_in_in3_rawIn_isZeroExpIn & ~(|(c[9:0])) + ? 3'h0 + : _inputs_in_in3_rawIn_adjustedExp_T_4[5:3]; + wire [64:0] inputs_0_in3 = + {48'h0, + c[15], + _inputs_in_in3_T_2[2:1], + _inputs_in_in3_T_2[0] | (&(_inputs_in_in3_rawIn_adjustedExp_T_4[5:4])) & (|(c[9:0])), + _inputs_in_in3_rawIn_adjustedExp_T_4[2:0], + inputs_in_in3_rawIn_isZeroExpIn + ? {_inputs_in_in3_rawIn_subnormFract_T[8:0], 1'h0} + : c[9:0]}; + wire inputs_in_in1_rawIn_isZeroExpIn_1 = a[30:23] == 8'h0; + wire [4:0] inputs_in_in1_rawIn_normDist_1 = + a[22] + ? 5'h0 + : a[21] + ? 5'h1 + : a[20] + ? 5'h2 + : a[19] + ? 5'h3 + : a[18] + ? 5'h4 + : a[17] + ? 5'h5 + : a[16] + ? 5'h6 + : a[15] + ? 5'h7 + : a[14] + ? 5'h8 + : a[13] + ? 5'h9 + : a[12] + ? 5'hA + : a[11] + ? 5'hB + : a[10] + ? 5'hC + : a[9] + ? 5'hD + : a[8] + ? 5'hE + : a[7] + ? 5'hF + : a[6] + ? 5'h10 + : a[5] + ? 5'h11 + : a[4] + ? 5'h12 + : a[3] + ? 5'h13 + : a[2] + ? 5'h14 + : a[1] + ? 5'h15 + : 5'h16; + wire [53:0] _inputs_in_in1_rawIn_subnormFract_T_2 = + {31'h0, a[22:0]} << inputs_in_in1_rawIn_normDist_1; + wire [8:0] _inputs_in_in1_rawIn_adjustedExp_T_9 = + (inputs_in_in1_rawIn_isZeroExpIn_1 + ? {4'hF, ~inputs_in_in1_rawIn_normDist_1} + : {1'h0, a[30:23]}) + {7'h20, inputs_in_in1_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1}; + wire [2:0] _inputs_in_in1_T_12 = + inputs_in_in1_rawIn_isZeroExpIn_1 & ~(|(a[22:0])) + ? 3'h0 + : _inputs_in_in1_rawIn_adjustedExp_T_9[8:6]; + wire [64:0] inputs_1_in1 = + {32'h0, + a[31], + _inputs_in_in1_T_12[2:1], + _inputs_in_in1_T_12[0] | (&(_inputs_in_in1_rawIn_adjustedExp_T_9[8:7])) + & (|(a[22:0])), + _inputs_in_in1_rawIn_adjustedExp_T_9[5:0], + inputs_in_in1_rawIn_isZeroExpIn_1 + ? {_inputs_in_in1_rawIn_subnormFract_T_2[21:0], 1'h0} + : a[22:0]}; + wire inputs_in_in2_rawIn_isZeroExpIn_1 = b[30:23] == 8'h0; + wire [4:0] inputs_in_in2_rawIn_normDist_1 = + b[22] + ? 5'h0 + : b[21] + ? 5'h1 + : b[20] + ? 5'h2 + : b[19] + ? 5'h3 + : b[18] + ? 5'h4 + : b[17] + ? 5'h5 + : b[16] + ? 5'h6 + : b[15] + ? 5'h7 + : b[14] + ? 5'h8 + : b[13] + ? 5'h9 + : b[12] + ? 5'hA + : b[11] + ? 5'hB + : b[10] + ? 5'hC + : b[9] + ? 5'hD + : b[8] + ? 5'hE + : b[7] + ? 5'hF + : b[6] + ? 5'h10 + : b[5] + ? 5'h11 + : b[4] + ? 5'h12 + : b[3] + ? 5'h13 + : b[2] + ? 5'h14 + : b[1] + ? 5'h15 + : 5'h16; + wire [53:0] _inputs_in_in2_rawIn_subnormFract_T_2 = + {31'h0, b[22:0]} << inputs_in_in2_rawIn_normDist_1; + wire [8:0] _inputs_in_in2_rawIn_adjustedExp_T_9 = + (inputs_in_in2_rawIn_isZeroExpIn_1 + ? {4'hF, ~inputs_in_in2_rawIn_normDist_1} + : {1'h0, b[30:23]}) + {7'h20, inputs_in_in2_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1}; + wire [2:0] _inputs_in_in2_T_12 = + inputs_in_in2_rawIn_isZeroExpIn_1 & ~(|(b[22:0])) + ? 3'h0 + : _inputs_in_in2_rawIn_adjustedExp_T_9[8:6]; + wire [64:0] inputs_1_in2 = + {32'h0, + b[31], + _inputs_in_in2_T_12[2:1], + _inputs_in_in2_T_12[0] | (&(_inputs_in_in2_rawIn_adjustedExp_T_9[8:7])) + & (|(b[22:0])), + _inputs_in_in2_rawIn_adjustedExp_T_9[5:0], + inputs_in_in2_rawIn_isZeroExpIn_1 + ? {_inputs_in_in2_rawIn_subnormFract_T_2[21:0], 1'h0} + : b[22:0]}; + wire inputs_in_in3_rawIn_isZeroExpIn_1 = c[30:23] == 8'h0; + wire [4:0] inputs_in_in3_rawIn_normDist_1 = + c[22] + ? 5'h0 + : c[21] + ? 5'h1 + : c[20] + ? 5'h2 + : c[19] + ? 5'h3 + : c[18] + ? 5'h4 + : c[17] + ? 5'h5 + : c[16] + ? 5'h6 + : c[15] + ? 5'h7 + : c[14] + ? 5'h8 + : c[13] + ? 5'h9 + : c[12] + ? 5'hA + : c[11] + ? 5'hB + : c[10] + ? 5'hC + : c[9] + ? 5'hD + : c[8] + ? 5'hE + : c[7] + ? 5'hF + : c[6] + ? 5'h10 + : c[5] + ? 5'h11 + : c[4] + ? 5'h12 + : c[3] + ? 5'h13 + : c[2] + ? 5'h14 + : c[1] + ? 5'h15 + : 5'h16; + wire [53:0] _inputs_in_in3_rawIn_subnormFract_T_2 = + {31'h0, c[22:0]} << inputs_in_in3_rawIn_normDist_1; + wire [8:0] _inputs_in_in3_rawIn_adjustedExp_T_9 = + (inputs_in_in3_rawIn_isZeroExpIn_1 + ? {4'hF, ~inputs_in_in3_rawIn_normDist_1} + : {1'h0, c[30:23]}) + {7'h20, inputs_in_in3_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1}; + wire [2:0] _inputs_in_in3_T_12 = + inputs_in_in3_rawIn_isZeroExpIn_1 & ~(|(c[22:0])) + ? 3'h0 + : _inputs_in_in3_rawIn_adjustedExp_T_9[8:6]; + wire [64:0] inputs_1_in3 = + {32'h0, + c[31], + _inputs_in_in3_T_12[2:1], + _inputs_in_in3_T_12[0] | (&(_inputs_in_in3_rawIn_adjustedExp_T_9[8:7])) + & (|(c[22:0])), + _inputs_in_in3_rawIn_adjustedExp_T_9[5:0], + inputs_in_in3_rawIn_isZeroExpIn_1 + ? {_inputs_in_in3_rawIn_subnormFract_T_2[21:0], 1'h0} + : c[22:0]}; + wire inputs_in_in1_rawIn_isZeroExpIn_2 = a[62:52] == 11'h0; + wire [5:0] inputs_in_in1_rawIn_normDist_2 = + a[51] + ? 6'h0 + : a[50] + ? 6'h1 + : a[49] + ? 6'h2 + : a[48] + ? 6'h3 + : a[47] + ? 6'h4 + : a[46] + ? 6'h5 + : a[45] + ? 6'h6 + : a[44] + ? 6'h7 + : a[43] + ? 6'h8 + : a[42] + ? 6'h9 + : a[41] + ? 6'hA + : a[40] + ? 6'hB + : a[39] + ? 6'hC + : a[38] + ? 6'hD + : a[37] + ? 6'hE + : a[36] + ? 6'hF + : a[35] + ? 6'h10 + : a[34] + ? 6'h11 + : a[33] + ? 6'h12 + : a[32] + ? 6'h13 + : a[31] + ? 6'h14 + : a[30] + ? 6'h15 + : a[29] + ? 6'h16 + : a[28] + ? 6'h17 + : a[27] + ? 6'h18 + : a[26] + ? 6'h19 + : a[25] + ? 6'h1A + : a[24] + ? 6'h1B + : a[23] + ? 6'h1C + : a[22] + ? 6'h1D + : a[21] + ? 6'h1E + : a[20] + ? 6'h1F + : a[19] + ? 6'h20 + : a[18] + ? 6'h21 + : a[17] + ? 6'h22 + : a[16] + ? 6'h23 + : a[15] + ? 6'h24 + : a[14] + ? 6'h25 + : a[13] + ? 6'h26 + : a[12] + ? 6'h27 + : a[11] + ? 6'h28 + : a[10] + ? 6'h29 + : a[9] + ? 6'h2A + : a[8] + ? 6'h2B + : a[7] + ? 6'h2C + : a[6] + ? 6'h2D + : a[5] + ? 6'h2E + : a[4] + ? 6'h2F + : a[3] + ? 6'h30 + : a[2] + ? 6'h31 + : {5'h19, + ~(a[1])}; + wire [114:0] _inputs_in_in1_rawIn_subnormFract_T_4 = + {63'h0, a[51:0]} << inputs_in_in1_rawIn_normDist_2; + wire [11:0] _inputs_in_in1_rawIn_adjustedExp_T_14 = + (inputs_in_in1_rawIn_isZeroExpIn_2 + ? {6'h3F, ~inputs_in_in1_rawIn_normDist_2} + : {1'h0, a[62:52]}) + {10'h100, inputs_in_in1_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1}; + wire [2:0] _inputs_in_in1_T_22 = + inputs_in_in1_rawIn_isZeroExpIn_2 & ~(|(a[51:0])) + ? 3'h0 + : _inputs_in_in1_rawIn_adjustedExp_T_14[11:9]; + wire [64:0] inputs_2_in1 = + {a[63], + _inputs_in_in1_T_22[2:1], + _inputs_in_in1_T_22[0] | (&(_inputs_in_in1_rawIn_adjustedExp_T_14[11:10])) + & (|(a[51:0])), + _inputs_in_in1_rawIn_adjustedExp_T_14[8:0], + inputs_in_in1_rawIn_isZeroExpIn_2 + ? {_inputs_in_in1_rawIn_subnormFract_T_4[50:0], 1'h0} + : a[51:0]}; + wire inputs_in_in2_rawIn_isZeroExpIn_2 = b[62:52] == 11'h0; + wire [5:0] inputs_in_in2_rawIn_normDist_2 = + b[51] + ? 6'h0 + : b[50] + ? 6'h1 + : b[49] + ? 6'h2 + : b[48] + ? 6'h3 + : b[47] + ? 6'h4 + : b[46] + ? 6'h5 + : b[45] + ? 6'h6 + : b[44] + ? 6'h7 + : b[43] + ? 6'h8 + : b[42] + ? 6'h9 + : b[41] + ? 6'hA + : b[40] + ? 6'hB + : b[39] + ? 6'hC + : b[38] + ? 6'hD + : b[37] + ? 6'hE + : b[36] + ? 6'hF + : b[35] + ? 6'h10 + : b[34] + ? 6'h11 + : b[33] + ? 6'h12 + : b[32] + ? 6'h13 + : b[31] + ? 6'h14 + : b[30] + ? 6'h15 + : b[29] + ? 6'h16 + : b[28] + ? 6'h17 + : b[27] + ? 6'h18 + : b[26] + ? 6'h19 + : b[25] + ? 6'h1A + : b[24] + ? 6'h1B + : b[23] + ? 6'h1C + : b[22] + ? 6'h1D + : b[21] + ? 6'h1E + : b[20] + ? 6'h1F + : b[19] + ? 6'h20 + : b[18] + ? 6'h21 + : b[17] + ? 6'h22 + : b[16] + ? 6'h23 + : b[15] + ? 6'h24 + : b[14] + ? 6'h25 + : b[13] + ? 6'h26 + : b[12] + ? 6'h27 + : b[11] + ? 6'h28 + : b[10] + ? 6'h29 + : b[9] + ? 6'h2A + : b[8] + ? 6'h2B + : b[7] + ? 6'h2C + : b[6] + ? 6'h2D + : b[5] + ? 6'h2E + : b[4] + ? 6'h2F + : b[3] + ? 6'h30 + : b[2] + ? 6'h31 + : {5'h19, + ~(b[1])}; + wire [114:0] _inputs_in_in2_rawIn_subnormFract_T_4 = + {63'h0, b[51:0]} << inputs_in_in2_rawIn_normDist_2; + wire [11:0] _inputs_in_in2_rawIn_adjustedExp_T_14 = + (inputs_in_in2_rawIn_isZeroExpIn_2 + ? {6'h3F, ~inputs_in_in2_rawIn_normDist_2} + : {1'h0, b[62:52]}) + {10'h100, inputs_in_in2_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1}; + wire [2:0] _inputs_in_in2_T_22 = + inputs_in_in2_rawIn_isZeroExpIn_2 & ~(|(b[51:0])) + ? 3'h0 + : _inputs_in_in2_rawIn_adjustedExp_T_14[11:9]; + wire [64:0] inputs_2_in2 = + {b[63], + _inputs_in_in2_T_22[2:1], + _inputs_in_in2_T_22[0] | (&(_inputs_in_in2_rawIn_adjustedExp_T_14[11:10])) + & (|(b[51:0])), + _inputs_in_in2_rawIn_adjustedExp_T_14[8:0], + inputs_in_in2_rawIn_isZeroExpIn_2 + ? {_inputs_in_in2_rawIn_subnormFract_T_4[50:0], 1'h0} + : b[51:0]}; + wire inputs_in_in3_rawIn_isZeroExpIn_2 = c[62:52] == 11'h0; + wire [5:0] inputs_in_in3_rawIn_normDist_2 = + c[51] + ? 6'h0 + : c[50] + ? 6'h1 + : c[49] + ? 6'h2 + : c[48] + ? 6'h3 + : c[47] + ? 6'h4 + : c[46] + ? 6'h5 + : c[45] + ? 6'h6 + : c[44] + ? 6'h7 + : c[43] + ? 6'h8 + : c[42] + ? 6'h9 + : c[41] + ? 6'hA + : c[40] + ? 6'hB + : c[39] + ? 6'hC + : c[38] + ? 6'hD + : c[37] + ? 6'hE + : c[36] + ? 6'hF + : c[35] + ? 6'h10 + : c[34] + ? 6'h11 + : c[33] + ? 6'h12 + : c[32] + ? 6'h13 + : c[31] + ? 6'h14 + : c[30] + ? 6'h15 + : c[29] + ? 6'h16 + : c[28] + ? 6'h17 + : c[27] + ? 6'h18 + : c[26] + ? 6'h19 + : c[25] + ? 6'h1A + : c[24] + ? 6'h1B + : c[23] + ? 6'h1C + : c[22] + ? 6'h1D + : c[21] + ? 6'h1E + : c[20] + ? 6'h1F + : c[19] + ? 6'h20 + : c[18] + ? 6'h21 + : c[17] + ? 6'h22 + : c[16] + ? 6'h23 + : c[15] + ? 6'h24 + : c[14] + ? 6'h25 + : c[13] + ? 6'h26 + : c[12] + ? 6'h27 + : c[11] + ? 6'h28 + : c[10] + ? 6'h29 + : c[9] + ? 6'h2A + : c[8] + ? 6'h2B + : c[7] + ? 6'h2C + : c[6] + ? 6'h2D + : c[5] + ? 6'h2E + : c[4] + ? 6'h2F + : c[3] + ? 6'h30 + : c[2] + ? 6'h31 + : {5'h19, + ~(c[1])}; + wire [114:0] _inputs_in_in3_rawIn_subnormFract_T_4 = + {63'h0, c[51:0]} << inputs_in_in3_rawIn_normDist_2; + wire [11:0] _inputs_in_in3_rawIn_adjustedExp_T_14 = + (inputs_in_in3_rawIn_isZeroExpIn_2 + ? {6'h3F, ~inputs_in_in3_rawIn_normDist_2} + : {1'h0, c[62:52]}) + {10'h100, inputs_in_in3_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1}; + wire [2:0] _inputs_in_in3_T_22 = + inputs_in_in3_rawIn_isZeroExpIn_2 & ~(|(c[51:0])) + ? 3'h0 + : _inputs_in_in3_rawIn_adjustedExp_T_14[11:9]; + wire [64:0] inputs_2_in3 = + {c[63], + _inputs_in_in3_T_22[2:1], + _inputs_in_in3_T_22[0] | (&(_inputs_in_in3_rawIn_adjustedExp_T_14[11:10])) + & (|(c[51:0])), + _inputs_in_in3_rawIn_adjustedExp_T_14[8:0], + inputs_in_in3_rawIn_isZeroExpIn_2 + ? {_inputs_in_in3_rawIn_subnormFract_T_4[50:0], 1'h0} + : c[51:0]}; + reg [64:0] refs_pipe_b_data; + reg [4:0] refs_pipe_b_exc; + reg [64:0] refs_pipe_b_1_data; + reg [4:0] refs_pipe_b_1_exc; + wire [3:0][64:0] _GEN_0 = + {{inputs_0_in1}, {inputs_2_in1}, {inputs_1_in1}, {inputs_0_in1}}; + wire [3:0][64:0] _GEN_1 = + {{inputs_0_in2}, {inputs_2_in2}, {inputs_1_in2}, {inputs_0_in2}}; + wire [3:0][64:0] _GEN_2 = + {{inputs_0_in3}, {inputs_2_in3}, {inputs_1_in3}, {inputs_0_in3}}; + reg outputTag_pipe_v; + reg [1:0] outputTag_pipe_b; + reg outputTag_pipe_pipe_v; + reg [1:0] outputTag_pipe_pipe_b; + reg outputTag_pipe_pipe_pipe_v; + reg [1:0] outputTag_pipe_pipe_pipe_b; + reg outputTag_pipe_pipe_pipe_pipe_v; + reg [1:0] outputTag_pipe_pipe_pipe_pipe_b; + reg outputTag_pipe_pipe_pipe_pipe_pipe_v; + reg [1:0] outputTag_pipe_pipe_pipe_pipe_pipe_b; + reg outputTag_pipe_pipe_pipe_pipe_pipe_pipe_v; + reg [1:0] outputTag_pipe_pipe_pipe_pipe_pipe_pipe_b; + wire originalData_rawIn_isInf = + (&(refs_pipe_b_data[15:14])) & ~(refs_pipe_b_data[13]); + wire originalData_isSubnormal = + $signed({1'h0, refs_pipe_b_data[15:10]}) < 7'sh12; + wire [10:0] _originalData_denormFract_T_1 = + {1'h0, |(refs_pipe_b_data[15:13]), refs_pipe_b_data[9:1]} >> 4'h1 + - refs_pipe_b_data[13:10]; + wire [63:0] originalData_0 = + {48'h0, + refs_pipe_b_data[16], + (originalData_isSubnormal ? 5'h0 : refs_pipe_b_data[14:10] + 5'hF) + | {5{(&(refs_pipe_b_data[15:14])) & refs_pipe_b_data[13] + | originalData_rawIn_isInf}}, + originalData_isSubnormal + ? _originalData_denormFract_T_1[9:0] + : originalData_rawIn_isInf ? 10'h0 : refs_pipe_b_data[9:0]}; + wire originalData_rawIn_1_isInf = + (&(refs_pipe_b_1_data[31:30])) & ~(refs_pipe_b_1_data[29]); + wire originalData_isSubnormal_1 = + $signed({1'h0, refs_pipe_b_1_data[31:23]}) < 10'sh82; + wire [23:0] _originalData_denormFract_T_3 = + {1'h0, |(refs_pipe_b_1_data[31:29]), refs_pipe_b_1_data[22:1]} >> 5'h1 + - refs_pipe_b_1_data[27:23]; + wire originalData_rawIn_2_isInf = + (&(_refs_unit_2_io_out_bits_data[63:62])) & ~(_refs_unit_2_io_out_bits_data[61]); + wire originalData_isSubnormal_2 = + $signed({1'h0, _refs_unit_2_io_out_bits_data[63:52]}) < 13'sh402; + wire [52:0] _originalData_denormFract_T_5 = + {1'h0, |(_refs_unit_2_io_out_bits_data[63:61]), _refs_unit_2_io_out_bits_data[51:1]} + >> 6'h1 - _refs_unit_2_io_out_bits_data[57:52]; + wire sharedData_rawIn_isInf = + (&(_shared_io_out_bits_data[15:14])) & ~(_shared_io_out_bits_data[13]); + wire sharedData_isSubnormal = + $signed({1'h0, _shared_io_out_bits_data[15:10]}) < 7'sh12; + wire [10:0] _sharedData_denormFract_T_1 = + {1'h0, |(_shared_io_out_bits_data[15:13]), _shared_io_out_bits_data[9:1]} >> 4'h1 + - _shared_io_out_bits_data[13:10]; + wire [63:0] sharedData_0 = + {48'h0, + _shared_io_out_bits_data[16], + (sharedData_isSubnormal ? 5'h0 : _shared_io_out_bits_data[14:10] + 5'hF) + | {5{(&(_shared_io_out_bits_data[15:14])) & _shared_io_out_bits_data[13] + | sharedData_rawIn_isInf}}, + sharedData_isSubnormal + ? _sharedData_denormFract_T_1[9:0] + : sharedData_rawIn_isInf ? 10'h0 : _shared_io_out_bits_data[9:0]}; + wire sharedData_rawIn_1_isInf = + (&(_shared_io_out_bits_data[31:30])) & ~(_shared_io_out_bits_data[29]); + wire sharedData_isSubnormal_1 = + $signed({1'h0, _shared_io_out_bits_data[31:23]}) < 10'sh82; + wire [23:0] _sharedData_denormFract_T_3 = + {1'h0, |(_shared_io_out_bits_data[31:29]), _shared_io_out_bits_data[22:1]} >> 5'h1 + - _shared_io_out_bits_data[27:23]; + wire sharedData_rawIn_2_isInf = + (&(_shared_io_out_bits_data[63:62])) & ~(_shared_io_out_bits_data[61]); + wire sharedData_isSubnormal_2 = + $signed({1'h0, _shared_io_out_bits_data[63:52]}) < 13'sh402; + wire [52:0] _sharedData_denormFract_T_5 = + {1'h0, |(_shared_io_out_bits_data[63:61]), _shared_io_out_bits_data[51:1]} >> 6'h1 + - _shared_io_out_bits_data[57:52]; + wire [3:0][63:0] _GEN_3 = + {{originalData_0}, + {{_refs_unit_2_io_out_bits_data[64], + (originalData_isSubnormal_2 + ? 11'h0 + : _refs_unit_2_io_out_bits_data[62:52] + 11'h3FF) + | {11{(&(_refs_unit_2_io_out_bits_data[63:62])) + & _refs_unit_2_io_out_bits_data[61] | originalData_rawIn_2_isInf}}, + originalData_isSubnormal_2 + ? _originalData_denormFract_T_5[51:0] + : originalData_rawIn_2_isInf ? 52'h0 : _refs_unit_2_io_out_bits_data[51:0]}}, + {{32'h0, + refs_pipe_b_1_data[32], + (originalData_isSubnormal_1 ? 8'h0 : refs_pipe_b_1_data[30:23] + 8'h7F) + | {8{(&(refs_pipe_b_1_data[31:30])) & refs_pipe_b_1_data[29] + | originalData_rawIn_1_isInf}}, + originalData_isSubnormal_1 + ? _originalData_denormFract_T_3[22:0] + : originalData_rawIn_1_isInf ? 23'h0 : refs_pipe_b_1_data[22:0]}}, + {originalData_0}}; + wire [63:0] _expected_output = _GEN_3[outputTag_pipe_pipe_pipe_pipe_pipe_pipe_b]; + wire [3:0][63:0] _GEN_4 = + {{sharedData_0}, + {{_shared_io_out_bits_data[64], + (sharedData_isSubnormal_2 ? 11'h0 : _shared_io_out_bits_data[62:52] + 11'h3FF) + | {11{(&(_shared_io_out_bits_data[63:62])) & _shared_io_out_bits_data[61] + | sharedData_rawIn_2_isInf}}, + sharedData_isSubnormal_2 + ? _sharedData_denormFract_T_5[51:0] + : sharedData_rawIn_2_isInf ? 52'h0 : _shared_io_out_bits_data[51:0]}}, + {{32'h0, + _shared_io_out_bits_data[32], + (sharedData_isSubnormal_1 ? 8'h0 : _shared_io_out_bits_data[30:23] + 8'h7F) + | {8{(&(_shared_io_out_bits_data[31:30])) & _shared_io_out_bits_data[29] + | sharedData_rawIn_1_isInf}}, + sharedData_isSubnormal_1 + ? _sharedData_denormFract_T_3[22:0] + : sharedData_rawIn_1_isInf ? 23'h0 : _shared_io_out_bits_data[22:0]}}, + {sharedData_0}}; + wire [63:0] _actual_output = _GEN_4[outputTag_pipe_pipe_pipe_pipe_pipe_pipe_b]; + wire [3:0][4:0] _GEN_5 = + {{refs_pipe_b_exc}, + {_refs_unit_2_io_out_bits_exc}, + {refs_pipe_b_1_exc}, + {refs_pipe_b_exc}}; + wire [4:0] _expectedFlags_output = + _GEN_5[outputTag_pipe_pipe_pipe_pipe_pipe_pipe_b]; + always @(posedge clock) begin + if (_refs_unit_io_out_valid) begin + refs_pipe_b_data <= _refs_unit_io_out_bits_data; + refs_pipe_b_exc <= _refs_unit_io_out_bits_exc; + end + if (_refs_unit_1_io_out_valid) begin + refs_pipe_b_1_data <= _refs_unit_1_io_out_bits_data; + refs_pipe_b_1_exc <= _refs_unit_1_io_out_bits_exc; + end + if (valid) + outputTag_pipe_b <= tag; + if (outputTag_pipe_v) + outputTag_pipe_pipe_b <= outputTag_pipe_b; + if (outputTag_pipe_pipe_v) + outputTag_pipe_pipe_pipe_b <= outputTag_pipe_pipe_b; + if (outputTag_pipe_pipe_pipe_v) + outputTag_pipe_pipe_pipe_pipe_b <= outputTag_pipe_pipe_pipe_b; + if (outputTag_pipe_pipe_pipe_pipe_v) + outputTag_pipe_pipe_pipe_pipe_pipe_b <= outputTag_pipe_pipe_pipe_pipe_b; + if (outputTag_pipe_pipe_pipe_pipe_pipe_v) + outputTag_pipe_pipe_pipe_pipe_pipe_pipe_b <= outputTag_pipe_pipe_pipe_pipe_pipe_b; + if (reset) begin + outputTag_pipe_v <= 1'h0; + outputTag_pipe_pipe_v <= 1'h0; + outputTag_pipe_pipe_pipe_v <= 1'h0; + outputTag_pipe_pipe_pipe_pipe_v <= 1'h0; + outputTag_pipe_pipe_pipe_pipe_pipe_v <= 1'h0; + outputTag_pipe_pipe_pipe_pipe_pipe_pipe_v <= 1'h0; + end + else begin + outputTag_pipe_v <= valid; + outputTag_pipe_pipe_v <= outputTag_pipe_v; + outputTag_pipe_pipe_pipe_v <= outputTag_pipe_pipe_v; + outputTag_pipe_pipe_pipe_pipe_v <= outputTag_pipe_pipe_pipe_v; + outputTag_pipe_pipe_pipe_pipe_pipe_v <= outputTag_pipe_pipe_pipe_pipe_v; + outputTag_pipe_pipe_pipe_pipe_pipe_pipe_v <= outputTag_pipe_pipe_pipe_pipe_pipe_v; + end + end // always @(posedge) + FPUFMAPipe_l5_f16 refs_unit ( + .clock (clock), + .reset (reset), + .io_in_valid (valid & tag == 2'h0), + .io_in_bits_ren3 (inputs_2_ren3), + .io_in_bits_swap23 (inputs_2_swap23), + .io_in_bits_rm (rm), + .io_in_bits_fmaCmd (op), + .io_in_bits_in1 (inputs_0_in1), + .io_in_bits_in2 (inputs_0_in2), + .io_in_bits_in3 (inputs_0_in3), + .io_out_valid (_refs_unit_io_out_valid), + .io_out_bits_data (_refs_unit_io_out_bits_data), + .io_out_bits_exc (_refs_unit_io_out_bits_exc) + ); + FPUFMAPipe_l5_f32 refs_unit_1 ( + .clock (clock), + .reset (reset), + .io_in_valid (valid & tag == 2'h1), + .io_in_bits_ren3 (inputs_2_ren3), + .io_in_bits_swap23 (inputs_2_swap23), + .io_in_bits_rm (rm), + .io_in_bits_fmaCmd (op), + .io_in_bits_in1 (inputs_1_in1), + .io_in_bits_in2 (inputs_1_in2), + .io_in_bits_in3 (inputs_1_in3), + .io_out_valid (_refs_unit_1_io_out_valid), + .io_out_bits_data (_refs_unit_1_io_out_bits_data), + .io_out_bits_exc (_refs_unit_1_io_out_bits_exc) + ); + FPUFMAPipe_l6_f64 refs_unit_2 ( + .clock (clock), + .reset (reset), + .io_in_valid (valid & tag == 2'h2), + .io_in_bits_ren3 (inputs_2_ren3), + .io_in_bits_swap23 (inputs_2_swap23), + .io_in_bits_rm (rm), + .io_in_bits_fmaCmd (op), + .io_in_bits_in1 (inputs_2_in1), + .io_in_bits_in2 (inputs_2_in2), + .io_in_bits_in3 (inputs_2_in3), + .io_out_bits_data (_refs_unit_2_io_out_bits_data), + .io_out_bits_exc (_refs_unit_2_io_out_bits_exc) + ); + FPUSharedFMAPipe shared ( + .clock (clock), + .reset (reset), + .io_in_valid (valid), + .io_in_bits_ren3 (inputs_2_ren3), + .io_in_bits_swap23 (inputs_2_swap23), + .io_in_bits_typeTagOut (_GEN[tag]), + .io_in_bits_rm (rm), + .io_in_bits_fmaCmd (op), + .io_in_bits_in1 (_GEN_0[tag]), + .io_in_bits_in2 (_GEN_1[tag]), + .io_in_bits_in3 (_GEN_2[tag]), + .io_out_valid (_shared_io_out_valid), + .io_out_bits_data (_shared_io_out_bits_data), + .io_out_bits_exc (_shared_io_out_bits_exc) + ); + assign expected = _expected_output; + assign actual = _actual_output; + assign expectedFlags = _expectedFlags_output; + assign actualFlags = _shared_io_out_bits_exc; + assign outValid = _shared_io_out_valid; + assign equal = + _shared_io_out_valid == outputTag_pipe_pipe_pipe_pipe_pipe_pipe_v + & (~outputTag_pipe_pipe_pipe_pipe_pipe_pipe_v | _expected_output == _actual_output + & _expectedFlags_output == _shared_io_out_bits_exc); +endmodule + diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fma-check/vectors.csv b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fma-check/vectors.csv new file mode 100644 index 0000000..57cb221 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fma-check/vectors.csv @@ -0,0 +1,1536 @@ +0,0,0,0,1,7c00,fe00,7e00,0 +0,0,0,0,83ff,3bff,3ff,0,3 +0,0,0,0,3c00,400,3c01,3c01,1 +0,0,0,0,3bff,8000,7c00,7c00,0 +0,0,0,0,3800,7e00,7c01,7e00,10 +0,0,0,0,7c00,3800,8001,7c00,0 +0,0,0,0,7c01,3c00,bc00,7e00,10 +0,0,1,0,0,8001,fbff,7bff,0 +0,0,1,0,1,fe00,7e00,7e00,0 +0,0,1,0,83ff,fbff,1,43fd,1 +0,0,1,0,3c00,3c01,3c00,1400,0 +0,0,1,0,3bff,83ff,7bff,fbff,1 +0,0,1,0,7bff,0,fe00,7e00,0 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"c3f667a561aeb6dccee4ed24866eb084a17c35eb5aa9accf56255b4f3a555f56", + "oracle": "unchanged original H/S/D FPUFMAPipe data and exception flags", + "regression": { + "result": "PASS", + "test_label": "whole Toy shared FPU 1536 oracle vectors", + "core_rtl_sha256": "31e7e07f94d08208dbb564edf9546240df26ff834935bfb646b71b541d875fb9", + "test_binary_sha256": "6b484b5850f3f8f84fdc1bb1d43a15cfc6669d938d4829b69f1ca675df0b16ba", + "cycles_including_boot": 168403, + "memory_read_bursts": 1387, + "memory_write_bursts": 11, + "linux_boot_tested": false + }, + "baseline_regression": { + "result": "PASS", + "test_label": "whole Toy baseline FPU 1536 oracle vectors", + "core_rtl_sha256": "81fb5cbe38d2feb3a9498b0a25f695f2d32468f7ee3fd3368426b079358eb35f", + "test_binary_sha256": "6b484b5850f3f8f84fdc1bb1d43a15cfc6669d938d4829b69f1ca675df0b16ba", + "cycles_including_boot": 165339, + "memory_read_bursts": 1387, + "memory_write_bursts": 11, + "linux_boot_tested": false + }, + "dependency_benchmark": { + "operation": "1024 dependent FADD; groups of 32, including loop overhead and final store", + "baseline_cycles_HSD": { + "0": 7242, + "1": 7271, + "2": 8211 + }, + "candidate_cycles_HSD": { + "0": 8264, + "1": 8291, + "2": 8213 + }, + "delta_cycles_HSD": { + "0": 1022, + "1": 1020, + "2": 2 + } + } +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/baseline-simulation/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/baseline-simulation/RESULT.json new file mode 100644 index 0000000..dbc8ae0 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/baseline-simulation/RESULT.json @@ -0,0 +1,10 @@ +{ + "result": "PASS", + "test_label": "whole Toy baseline FPU 1536 oracle vectors", + "core_rtl_sha256": "81fb5cbe38d2feb3a9498b0a25f695f2d32468f7ee3fd3368426b079358eb35f", + "test_binary_sha256": "6b484b5850f3f8f84fdc1bb1d43a15cfc6669d938d4829b69f1ca675df0b16ba", + "cycles_including_boot": 165339, + "memory_read_bursts": 1387, + "memory_write_bursts": 11, + "linux_boot_tested": false +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/baseline-simulation/simulation.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/baseline-simulation/simulation.log new file mode 100644 index 0000000..e90d62a --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/baseline-simulation/simulation.log @@ -0,0 +1,10 @@ +CPU status = 7300000000001c4a +CPU status = 7300000100001c67 +CPU status = 7300000200002013 +CPU status = 00000000600d600d +PASS whole Toy baseline FPU 1536 oracle vectors +- /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:88: Verilog $finish +MEASURE cycles=165339 memory_reads=1387 memory_writes=11 +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 2ms; walltime 1.258 s; speed 1.314 ms/s +- Verilator: cpu 1.258 s on 1 threads; allocated 8 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/baseline-simulation/smoke.bin b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/baseline-simulation/smoke.bin new file mode 100644 index 0000000..fce167b Binary files /dev/null and b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/baseline-simulation/smoke.bin differ diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/baseline-simulation/smoke.disasm b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/baseline-simulation/smoke.disasm new file mode 100644 index 0000000..ec095ed --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/baseline-simulation/smoke.disasm @@ -0,0 +1,538 @@ + +/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/smoke.elf: file format elf64-littleriscv + + +Disassembly of section .text: + +0000000080000000 <_start>: + 80000000: 00002137 lui sp,0x2 + 80000004: 0011011b addiw sp,sp,1 # 2001 <_start-0x7fffdfff> + 80000008: 01211113 slli sp,sp,0x12 + 8000000c: ff010113 addi sp,sp,-16 + 80000010: 00000297 auipc t0,0x0 + 80000014: 04c28293 addi t0,t0,76 # 8000005c + 80000018: 30529073 csrw mtvec,t0 + 8000001c: 30401073 csrw mie,zero + 80000020: 30201073 csrw medeleg,zero + 80000024: 0001e2b7 lui t0,0x1e + 80000028: 3002a073 csrs mstatus,t0 + 8000002c: 00000097 auipc ra,0x0 + 80000030: 050080e7 jalr 80(ra) # 8000007c
+ 80000034: 600002b7 lui t0,0x60000 + 80000038: 600d6337 lui t1,0x600d6 + 8000003c: 00d3031b addiw t1,t1,13 # 600d600d <_start-0x1ff29ff3> + 80000040: 00050a63 beqz a0,80000054 + 80000044: 00001337 lui t1,0x1 + 80000048: bad3031b addiw t1,t1,-1107 # bad <_start-0x7ffff453> + 8000004c: 01431313 slli t1,t1,0x14 + 80000050: 00a36333 or t1,t1,a0 + +0000000080000054 : + 80000054: 0062b023 sd t1,0(t0) # 60000000 <_start-0x20000000> + 80000058: 0000006f j 80000058 + +000000008000005c : + 8000005c: 342023f3 csrr t2,mcause + 80000060: 600002b7 lui t0,0x60000 + 80000064: 000bb337 lui t1,0xbb + 80000068: d0f3031b addiw t1,t1,-753 # bad0f <_start-0x7ff452f1> + 8000006c: 00c31313 slli t1,t1,0xc + 80000070: 00736333 or t1,t1,t2 + 80000074: 0062b023 sd t1,0(t0) # 60000000 <_start-0x20000000> + 80000078: 0000006f j 80000078 + +000000008000007c
: + 8000007c: 1101 addi sp,sp,-32 + 8000007e: e822 sd s0,16(sp) + 80000080: 00000f17 auipc t5,0x0 + 80000084: 6c0f0f13 addi t5,t5,1728 # 80000740 + 80000088: 1000 addi s0,sp,32 + 8000008a: ec06 sd ra,24(sp) + 8000008c: 87fa mv a5,t5 + 8000008e: 4681 li a3,0 + 80000090: 4805 li a6,1 + 80000092: 4889 li a7,2 + 80000094: 4e8d li t4,3 + 80000096: fe840e13 addi t3,s0,-24 + 8000009a: 60000313 li t1,1536 + 8000009e: 02c7e603 lwu a2,44(a5) + 800000a2: fe043423 sd zero,-24(s0) + 800000a6: 00261073 fsrm a2 + 800000aa: 5390 lw a2,32(a5) + 800000ac: 3e061b63 bnez a2,800004a2 + 800000b0: 53d0 lw a2,36(a5) + 800000b2: 34061763 bnez a2,80000400 + 800000b6: 578c lw a1,40(a5) + 800000b8: e19d bnez a1,800000de + 800000ba: 00101073 fsflags zero + 800000be: 00079007 flh ft0,0(a5) + 800000c2: 00879087 flh ft1,8(a5) + 800000c6: 01079107 flh ft2,16(a5) + 800000ca: 141071c3 fmadd.h ft3,ft0,ft1,ft2 + 800000ce: 003e1027 fsh ft3,0(t3) + 800000d2: 00102773 frflags a4 + 800000d6: 53d0 lw a2,36(a5) + 800000d8: 32061463 bnez a2,80000400 + 800000dc: 578c lw a1,40(a5) + 800000de: 37058d63 beq a1,a6,80000458 + 800000e2: 39158e63 beq a1,a7,8000047e + 800000e6: 4601 li a2,0 + 800000e8: 2fd58d63 beq a1,t4,800003e2 + 800000ec: 29160863 beq a2,a7,8000037c + 800000f0: fe843583 ld a1,-24(s0) + 800000f4: 6f88 ld a0,24(a5) + 800000f6: 0307e603 lwu a2,48(a5) + 800000fa: 2ab51963 bne a0,a1,800003ac + 800000fe: 2ac71763 bne a4,a2,800003ac + 80000102: 0685 addi a3,a3,1 + 80000104: 03878793 addi a5,a5,56 + 80000108: f8669be3 bne a3,t1,8000009e + 8000010c: 6791 lui a5,0x4 + 8000010e: c0078793 addi a5,a5,-1024 # 3c00 <_start-0x7fffc400> + 80000112: fef43023 sd a5,-32(s0) + 80000116: fe043423 sd zero,-24(s0) + 8000011a: fe040793 addi a5,s0,-32 + 8000011e: fe840693 addi a3,s0,-24 + 80000122: 00079007 flh ft0,0(a5) + 80000126: 00079087 flh ft1,0(a5) + 8000012a: 02000293 li t0,32 + 8000012e: c00025f3 rdcycle a1 + 80000132: 04100053 fadd.h ft0,ft0,ft1,rne + 80000136: 04100053 fadd.h ft0,ft0,ft1,rne + 8000013a: 04100053 fadd.h ft0,ft0,ft1,rne + 8000013e: 04100053 fadd.h ft0,ft0,ft1,rne + 80000142: 04100053 fadd.h ft0,ft0,ft1,rne + 80000146: 04100053 fadd.h ft0,ft0,ft1,rne + 8000014a: 04100053 fadd.h ft0,ft0,ft1,rne + 8000014e: 04100053 fadd.h ft0,ft0,ft1,rne + 80000152: 04100053 fadd.h ft0,ft0,ft1,rne + 80000156: 04100053 fadd.h ft0,ft0,ft1,rne + 8000015a: 04100053 fadd.h ft0,ft0,ft1,rne + 8000015e: 04100053 fadd.h ft0,ft0,ft1,rne + 80000162: 04100053 fadd.h ft0,ft0,ft1,rne + 80000166: 04100053 fadd.h ft0,ft0,ft1,rne + 8000016a: 04100053 fadd.h ft0,ft0,ft1,rne + 8000016e: 04100053 fadd.h ft0,ft0,ft1,rne + 80000172: 04100053 fadd.h ft0,ft0,ft1,rne + 80000176: 04100053 fadd.h ft0,ft0,ft1,rne + 8000017a: 04100053 fadd.h ft0,ft0,ft1,rne + 8000017e: 04100053 fadd.h ft0,ft0,ft1,rne + 80000182: 04100053 fadd.h ft0,ft0,ft1,rne + 80000186: 04100053 fadd.h ft0,ft0,ft1,rne + 8000018a: 04100053 fadd.h ft0,ft0,ft1,rne + 8000018e: 04100053 fadd.h ft0,ft0,ft1,rne + 80000192: 04100053 fadd.h ft0,ft0,ft1,rne + 80000196: 04100053 fadd.h ft0,ft0,ft1,rne + 8000019a: 04100053 fadd.h ft0,ft0,ft1,rne + 8000019e: 04100053 fadd.h ft0,ft0,ft1,rne + 800001a2: 04100053 fadd.h ft0,ft0,ft1,rne + 800001a6: 04100053 fadd.h ft0,ft0,ft1,rne + 800001aa: 04100053 fadd.h ft0,ft0,ft1,rne + 800001ae: 04100053 fadd.h ft0,ft0,ft1,rne + 800001b2: 12fd addi t0,t0,-1 + 800001b4: f6029fe3 bnez t0,80000132 + 800001b8: 00069027 fsh ft0,0(a3) + 800001bc: c0002773 rdcycle a4 + 800001c0: fe843603 ld a2,-24(s0) + 800001c4: 6699 lui a3,0x6 + 800001c6: 40168693 addi a3,a3,1025 # 6401 <_start-0x7fff9bff> + 800001ca: 56d61663 bne a2,a3,80000736 + 800001ce: 07300693 li a3,115 + 800001d2: 8f0d sub a4,a4,a1 + 800001d4: 16e2 slli a3,a3,0x38 + 800001d6: 8f55 or a4,a4,a3 + 800001d8: 60000637 lui a2,0x60000 + 800001dc: e218 sd a4,0(a2) + 800001de: 3f800737 lui a4,0x3f800 + 800001e2: fee43023 sd a4,-32(s0) + 800001e6: fe043423 sd zero,-24(s0) + 800001ea: fe840693 addi a3,s0,-24 + 800001ee: 0007a007 flw ft0,0(a5) + 800001f2: 0007a087 flw ft1,0(a5) + 800001f6: 02000293 li t0,32 + 800001fa: c0002573 rdcycle a0 + 800001fe: 00100053 fadd.s ft0,ft0,ft1,rne + 80000202: 00100053 fadd.s ft0,ft0,ft1,rne + 80000206: 00100053 fadd.s ft0,ft0,ft1,rne + 8000020a: 00100053 fadd.s ft0,ft0,ft1,rne + 8000020e: 00100053 fadd.s ft0,ft0,ft1,rne + 80000212: 00100053 fadd.s ft0,ft0,ft1,rne + 80000216: 00100053 fadd.s ft0,ft0,ft1,rne + 8000021a: 00100053 fadd.s ft0,ft0,ft1,rne + 8000021e: 00100053 fadd.s ft0,ft0,ft1,rne + 80000222: 00100053 fadd.s ft0,ft0,ft1,rne + 80000226: 00100053 fadd.s ft0,ft0,ft1,rne + 8000022a: 00100053 fadd.s ft0,ft0,ft1,rne + 8000022e: 00100053 fadd.s ft0,ft0,ft1,rne + 80000232: 00100053 fadd.s ft0,ft0,ft1,rne + 80000236: 00100053 fadd.s ft0,ft0,ft1,rne + 8000023a: 00100053 fadd.s ft0,ft0,ft1,rne + 8000023e: 00100053 fadd.s ft0,ft0,ft1,rne + 80000242: 00100053 fadd.s ft0,ft0,ft1,rne + 80000246: 00100053 fadd.s ft0,ft0,ft1,rne + 8000024a: 00100053 fadd.s ft0,ft0,ft1,rne + 8000024e: 00100053 fadd.s ft0,ft0,ft1,rne + 80000252: 00100053 fadd.s ft0,ft0,ft1,rne + 80000256: 00100053 fadd.s ft0,ft0,ft1,rne + 8000025a: 00100053 fadd.s ft0,ft0,ft1,rne + 8000025e: 00100053 fadd.s ft0,ft0,ft1,rne + 80000262: 00100053 fadd.s ft0,ft0,ft1,rne + 80000266: 00100053 fadd.s ft0,ft0,ft1,rne + 8000026a: 00100053 fadd.s ft0,ft0,ft1,rne + 8000026e: 00100053 fadd.s ft0,ft0,ft1,rne + 80000272: 00100053 fadd.s ft0,ft0,ft1,rne + 80000276: 00100053 fadd.s ft0,ft0,ft1,rne + 8000027a: 00100053 fadd.s ft0,ft0,ft1,rne + 8000027e: 12fd addi t0,t0,-1 + 80000280: f6029fe3 bnez t0,800001fe + 80000284: 0006a027 fsw ft0,0(a3) + 80000288: c0002773 rdcycle a4 + 8000028c: fe843583 ld a1,-24(s0) + 80000290: 448026b7 lui a3,0x44802 + 80000294: 4ad59163 bne a1,a3,80000736 + 80000298: 730006b7 lui a3,0x73000 + 8000029c: 0685 addi a3,a3,1 # 73000001 <_start-0xcffffff> + 8000029e: 8f09 sub a4,a4,a0 + 800002a0: 1682 slli a3,a3,0x20 + 800002a2: 8f55 or a4,a4,a3 + 800002a4: e218 sd a4,0(a2) + 800002a6: 3ff00713 li a4,1023 + 800002aa: 1752 slli a4,a4,0x34 + 800002ac: fee43023 sd a4,-32(s0) + 800002b0: fe043423 sd zero,-24(s0) + 800002b4: fe840693 addi a3,s0,-24 + 800002b8: 0007b007 fld ft0,0(a5) + 800002bc: 0007b087 fld ft1,0(a5) + 800002c0: 02000293 li t0,32 + 800002c4: c00025f3 rdcycle a1 + 800002c8: 02100053 fadd.d ft0,ft0,ft1,rne + 800002cc: 02100053 fadd.d ft0,ft0,ft1,rne + 800002d0: 02100053 fadd.d ft0,ft0,ft1,rne + 800002d4: 02100053 fadd.d ft0,ft0,ft1,rne + 800002d8: 02100053 fadd.d ft0,ft0,ft1,rne + 800002dc: 02100053 fadd.d ft0,ft0,ft1,rne + 800002e0: 02100053 fadd.d ft0,ft0,ft1,rne + 800002e4: 02100053 fadd.d ft0,ft0,ft1,rne + 800002e8: 02100053 fadd.d ft0,ft0,ft1,rne + 800002ec: 02100053 fadd.d ft0,ft0,ft1,rne + 800002f0: 02100053 fadd.d ft0,ft0,ft1,rne + 800002f4: 02100053 fadd.d ft0,ft0,ft1,rne + 800002f8: 02100053 fadd.d ft0,ft0,ft1,rne + 800002fc: 02100053 fadd.d ft0,ft0,ft1,rne + 80000300: 02100053 fadd.d ft0,ft0,ft1,rne + 80000304: 02100053 fadd.d ft0,ft0,ft1,rne + 80000308: 02100053 fadd.d ft0,ft0,ft1,rne + 8000030c: 02100053 fadd.d ft0,ft0,ft1,rne + 80000310: 02100053 fadd.d ft0,ft0,ft1,rne + 80000314: 02100053 fadd.d ft0,ft0,ft1,rne + 80000318: 02100053 fadd.d ft0,ft0,ft1,rne + 8000031c: 02100053 fadd.d ft0,ft0,ft1,rne + 80000320: 02100053 fadd.d ft0,ft0,ft1,rne + 80000324: 02100053 fadd.d ft0,ft0,ft1,rne + 80000328: 02100053 fadd.d ft0,ft0,ft1,rne + 8000032c: 02100053 fadd.d ft0,ft0,ft1,rne + 80000330: 02100053 fadd.d ft0,ft0,ft1,rne + 80000334: 02100053 fadd.d ft0,ft0,ft1,rne + 80000338: 02100053 fadd.d ft0,ft0,ft1,rne + 8000033c: 02100053 fadd.d ft0,ft0,ft1,rne + 80000340: 02100053 fadd.d ft0,ft0,ft1,rne + 80000344: 02100053 fadd.d ft0,ft0,ft1,rne + 80000348: 12fd addi t0,t0,-1 + 8000034a: f6029fe3 bnez t0,800002c8 + 8000034e: 0006b027 fsd ft0,0(a3) + 80000352: c0002773 rdcycle a4 + 80000356: 001027b7 lui a5,0x102 + 8000035a: fe843683 ld a3,-24(s0) + 8000035e: 40178793 addi a5,a5,1025 # 102401 <_start-0x7fefdbff> + 80000362: 17aa slli a5,a5,0x2a + 80000364: 3cf69963 bne a3,a5,80000736 + 80000368: 40b707b3 sub a5,a4,a1 + 8000036c: 39800737 lui a4,0x39800 + 80000370: 0705 addi a4,a4,1 # 39800001 <_start-0x467fffff> + 80000372: 1706 slli a4,a4,0x21 + 80000374: 8fd9 or a5,a5,a4 + 80000376: e21c sd a5,0(a2) + 80000378: 4501 li a0,0 + 8000037a: a085 j 800003da + 8000037c: 5790 lw a2,40(a5) + 8000037e: d60619e3 bnez a2,800000f0 + 80000382: 00101073 fsflags zero + 80000386: 00079007 flh ft0,0(a5) + 8000038a: 00879087 flh ft1,8(a5) + 8000038e: 01079107 flh ft2,16(a5) + 80000392: 141071d3 fmul.h ft3,ft0,ft1 + 80000396: 003e1027 fsh ft3,0(t3) + 8000039a: 00102773 frflags a4 + 8000039e: fe843583 ld a1,-24(s0) + 800003a2: 6f88 ld a0,24(a5) + 800003a4: 0307e603 lwu a2,48(a5) + 800003a8: d4b50be3 beq a0,a1,800000fe + 800003ac: 02069813 slli a6,a3,0x20 + 800003b0: 02085813 srli a6,a6,0x20 + 800003b4: 00381793 slli a5,a6,0x3 + 800003b8: 410787b3 sub a5,a5,a6 + 800003bc: 078e slli a5,a5,0x3 + 800003be: 9f3e add t5,t5,a5 + 800003c0: 60000537 lui a0,0x60000 + 800003c4: 018f3803 ld a6,24(t5) + 800003c8: e914 sd a3,16(a0) + 800003ca: ed0c sd a1,24(a0) + 800003cc: 03053023 sd a6,32(a0) # 60000020 <_start-0x1fffffe0> + 800003d0: f518 sd a4,40(a0) + 800003d2: 01850693 addi a3,a0,24 + 800003d6: f910 sd a2,48(a0) + 800003d8: 457d li a0,31 + 800003da: 60e2 ld ra,24(sp) + 800003dc: 6442 ld s0,16(sp) + 800003de: 6105 addi sp,sp,32 + 800003e0: 8082 ret + 800003e2: 00101073 fsflags zero + 800003e6: 00079007 flh ft0,0(a5) + 800003ea: 00879087 flh ft1,8(a5) + 800003ee: 01079107 flh ft2,16(a5) + 800003f2: 141071cf fnmadd.h ft3,ft0,ft1,ft2 + 800003f6: 003e1027 fsh ft3,0(t3) + 800003fa: 00102773 frflags a4 + 800003fe: 53d0 lw a2,36(a5) + 80000400: cf0616e3 bne a2,a6,800000ec + 80000404: 5790 lw a2,40(a5) + 80000406: e21d bnez a2,8000042c + 80000408: 00101073 fsflags zero + 8000040c: 00079007 flh ft0,0(a5) + 80000410: 00879087 flh ft1,8(a5) + 80000414: 01079107 flh ft2,16(a5) + 80000418: 042071d3 fadd.h ft3,ft0,ft2 + 8000041c: 003e1027 fsh ft3,0(t3) + 80000420: 00102773 frflags a4 + 80000424: 53d0 lw a2,36(a5) + 80000426: cd0613e3 bne a2,a6,800000ec + 8000042a: 5790 lw a2,40(a5) + 8000042c: cd0612e3 bne a2,a6,800000f0 + 80000430: fe840713 addi a4,s0,-24 + 80000434: 00101073 fsflags zero + 80000438: 00079007 flh ft0,0(a5) + 8000043c: 00879087 flh ft1,8(a5) + 80000440: 01079107 flh ft2,16(a5) + 80000444: 0c2071d3 fsub.h ft3,ft0,ft2 + 80000448: 00371027 fsh ft3,0(a4) + 8000044c: 00102773 frflags a4 + 80000450: 53d0 lw a2,36(a5) + 80000452: c9161fe3 bne a2,a7,800000f0 + 80000456: b71d j 8000037c + 80000458: 00101073 fsflags zero + 8000045c: 00079007 flh ft0,0(a5) + 80000460: 00879087 flh ft1,8(a5) + 80000464: 01079107 flh ft2,16(a5) + 80000468: 141071c7 fmsub.h ft3,ft0,ft1,ft2 + 8000046c: 003e1027 fsh ft3,0(t3) + 80000470: 00102773 frflags a4 + 80000474: 53d0 lw a2,36(a5) + 80000476: f649 bnez a2,80000400 + 80000478: 578c lw a1,40(a5) + 8000047a: c71596e3 bne a1,a7,800000e6 + 8000047e: 00101073 fsflags zero + 80000482: 00079007 flh ft0,0(a5) + 80000486: 00879087 flh ft1,8(a5) + 8000048a: 01079107 flh ft2,16(a5) + 8000048e: 141071cb fnmsub.h ft3,ft0,ft1,ft2 + 80000492: 003e1027 fsh ft3,0(t3) + 80000496: 00102773 frflags a4 + 8000049a: 53d0 lw a2,36(a5) + 8000049c: f235 bnez a2,80000400 + 8000049e: 578c lw a1,40(a5) + 800004a0: b199 j 800000e6 + 800004a2: 07060f63 beq a2,a6,80000520 + 800004a6: 4581 li a1,0 + 800004a8: c51616e3 bne a2,a7,800000f4 + 800004ac: 53cc lw a1,36(a5) + 800004ae: 852e mv a0,a1 + 800004b0: 16059e63 bnez a1,8000062c + 800004b4: 5790 lw a2,40(a5) + 800004b6: e615 bnez a2,800004e2 + 800004b8: fe840713 addi a4,s0,-24 + 800004bc: 00101073 fsflags zero + 800004c0: 0007b007 fld ft0,0(a5) + 800004c4: 0087b087 fld ft1,8(a5) + 800004c8: 0107b107 fld ft2,16(a5) + 800004cc: 121071c3 fmadd.d ft3,ft0,ft1,ft2 + 800004d0: 00373027 fsd ft3,0(a4) + 800004d4: 00102773 frflags a4 + 800004d8: 53cc lw a1,36(a5) + 800004da: 852e mv a0,a1 + 800004dc: 14059863 bnez a1,8000062c + 800004e0: 5790 lw a2,40(a5) + 800004e2: 4505 li a0,1 + 800004e4: 22a60363 beq a2,a0,8000070a + 800004e8: 4509 li a0,2 + 800004ea: 1ea60b63 beq a2,a0,800006e0 + 800004ee: 450d li a0,3 + 800004f0: 10a60c63 beq a2,a0,80000608 + 800004f4: bf159ee3 bne a1,a7,800000f0 + 800004f8: 5790 lw a2,40(a5) + 800004fa: be061be3 bnez a2,800000f0 + 800004fe: fe840713 addi a4,s0,-24 + 80000502: 00101073 fsflags zero + 80000506: 0007b007 fld ft0,0(a5) + 8000050a: 0087b087 fld ft1,8(a5) + 8000050e: 0107b107 fld ft2,16(a5) + 80000512: 121071d3 fmul.d ft3,ft0,ft1 + 80000516: 00373027 fsd ft3,0(a4) + 8000051a: 00102773 frflags a4 + 8000051e: bec9 j 800000f0 + 80000520: 53cc lw a1,36(a5) + 80000522: e5d1 bnez a1,800005ae + 80000524: 5790 lw a2,40(a5) + 80000526: e605 bnez a2,8000054e + 80000528: fe840713 addi a4,s0,-24 + 8000052c: 00101073 fsflags zero + 80000530: 0007a007 flw ft0,0(a5) + 80000534: 0087a087 flw ft1,8(a5) + 80000538: 0107a107 flw ft2,16(a5) + 8000053c: 101071c3 fmadd.s ft3,ft0,ft1,ft2 + 80000540: 00372027 fsw ft3,0(a4) + 80000544: 00102773 frflags a4 + 80000548: 53cc lw a1,36(a5) + 8000054a: e1b5 bnez a1,800005ae + 8000054c: 5790 lw a2,40(a5) + 8000054e: 13060f63 beq a2,a6,8000068c + 80000552: 17160263 beq a2,a7,800006b6 + 80000556: 4581 li a1,0 + 80000558: 03d60a63 beq a2,t4,8000058c + 8000055c: b9159ae3 bne a1,a7,800000f0 + 80000560: 5790 lw a2,40(a5) + 80000562: b80617e3 bnez a2,800000f0 + 80000566: fe840713 addi a4,s0,-24 + 8000056a: 00101073 fsflags zero + 8000056e: 0007a007 flw ft0,0(a5) + 80000572: 0087a087 flw ft1,8(a5) + 80000576: 0107a107 flw ft2,16(a5) + 8000057a: 101071d3 fmul.s ft3,ft0,ft1 + 8000057e: 00372027 fsw ft3,0(a4) + 80000582: 00102773 frflags a4 + 80000586: fe843583 ld a1,-24(s0) + 8000058a: b6ad j 800000f4 + 8000058c: fe840713 addi a4,s0,-24 + 80000590: 00101073 fsflags zero + 80000594: 0007a007 flw ft0,0(a5) + 80000598: 0087a087 flw ft1,8(a5) + 8000059c: 0107a107 flw ft2,16(a5) + 800005a0: 101071cf fnmadd.s ft3,ft0,ft1,ft2 + 800005a4: 00372027 fsw ft3,0(a4) + 800005a8: 00102773 frflags a4 + 800005ac: 53cc lw a1,36(a5) + 800005ae: fb0597e3 bne a1,a6,8000055c + 800005b2: 5790 lw a2,40(a5) + 800005b4: e60d bnez a2,800005de + 800005b6: fe840713 addi a4,s0,-24 + 800005ba: 00101073 fsflags zero + 800005be: 0007a007 flw ft0,0(a5) + 800005c2: 0087a087 flw ft1,8(a5) + 800005c6: 0107a107 flw ft2,16(a5) + 800005ca: 002071d3 fadd.s ft3,ft0,ft2 + 800005ce: 00372027 fsw ft3,0(a4) + 800005d2: 00102773 frflags a4 + 800005d6: 53cc lw a1,36(a5) + 800005d8: f90592e3 bne a1,a6,8000055c + 800005dc: 5790 lw a2,40(a5) + 800005de: 4585 li a1,1 + 800005e0: b0b618e3 bne a2,a1,800000f0 + 800005e4: fe840713 addi a4,s0,-24 + 800005e8: 00101073 fsflags zero + 800005ec: 0007a007 flw ft0,0(a5) + 800005f0: 0087a087 flw ft1,8(a5) + 800005f4: 0107a107 flw ft2,16(a5) + 800005f8: 082071d3 fsub.s ft3,ft0,ft2 + 800005fc: 00372027 fsw ft3,0(a4) + 80000600: 00102773 frflags a4 + 80000604: 53cc lw a1,36(a5) + 80000606: bf99 j 8000055c + 80000608: fe840713 addi a4,s0,-24 + 8000060c: 00101073 fsflags zero + 80000610: 0007b007 fld ft0,0(a5) + 80000614: 0087b087 fld ft1,8(a5) + 80000618: 0107b107 fld ft2,16(a5) + 8000061c: 121071cf fnmadd.d ft3,ft0,ft1,ft2 + 80000620: 00373027 fsd ft3,0(a4) + 80000624: 00102773 frflags a4 + 80000628: 53cc lw a1,36(a5) + 8000062a: 852e mv a0,a1 + 8000062c: 4605 li a2,1 + 8000062e: ecc593e3 bne a1,a2,800004f4 + 80000632: 5790 lw a2,40(a5) + 80000634: e60d bnez a2,8000065e + 80000636: fe840713 addi a4,s0,-24 + 8000063a: 00101073 fsflags zero + 8000063e: 0007b007 fld ft0,0(a5) + 80000642: 0087b087 fld ft1,8(a5) + 80000646: 0107b107 fld ft2,16(a5) + 8000064a: 022071d3 fadd.d ft3,ft0,ft2 + 8000064e: 00373027 fsd ft3,0(a4) + 80000652: 00102773 frflags a4 + 80000656: 53cc lw a1,36(a5) + 80000658: e8a59ee3 bne a1,a0,800004f4 + 8000065c: 5790 lw a2,40(a5) + 8000065e: 4585 li a1,1 + 80000660: a8b618e3 bne a2,a1,800000f0 + 80000664: fe840713 addi a4,s0,-24 + 80000668: 00101073 fsflags zero + 8000066c: 0007b007 fld ft0,0(a5) + 80000670: 0087b087 fld ft1,8(a5) + 80000674: 0107b107 fld ft2,16(a5) + 80000678: 0a2071d3 fsub.d ft3,ft0,ft2 + 8000067c: 00373027 fsd ft3,0(a4) + 80000680: 00102773 frflags a4 + 80000684: 53cc lw a1,36(a5) + 80000686: a71595e3 bne a1,a7,800000f0 + 8000068a: b5bd j 800004f8 + 8000068c: fe840713 addi a4,s0,-24 + 80000690: 00101073 fsflags zero + 80000694: 0007a007 flw ft0,0(a5) + 80000698: 0087a087 flw ft1,8(a5) + 8000069c: 0107a107 flw ft2,16(a5) + 800006a0: 101071c7 fmsub.s ft3,ft0,ft1,ft2 + 800006a4: 00372027 fsw ft3,0(a4) + 800006a8: 00102773 frflags a4 + 800006ac: 53cc lw a1,36(a5) + 800006ae: f181 bnez a1,800005ae + 800006b0: 5790 lw a2,40(a5) + 800006b2: eb1612e3 bne a2,a7,80000556 + 800006b6: fe840713 addi a4,s0,-24 + 800006ba: 00101073 fsflags zero + 800006be: 0007a007 flw ft0,0(a5) + 800006c2: 0087a087 flw ft1,8(a5) + 800006c6: 0107a107 flw ft2,16(a5) + 800006ca: 101071cb fnmsub.s ft3,ft0,ft1,ft2 + 800006ce: 00372027 fsw ft3,0(a4) + 800006d2: 00102773 frflags a4 + 800006d6: 53cc lw a1,36(a5) + 800006d8: ec059be3 bnez a1,800005ae + 800006dc: 5790 lw a2,40(a5) + 800006de: bda5 j 80000556 + 800006e0: fe840713 addi a4,s0,-24 + 800006e4: 00101073 fsflags zero + 800006e8: 0007b007 fld ft0,0(a5) + 800006ec: 0087b087 fld ft1,8(a5) + 800006f0: 0107b107 fld ft2,16(a5) + 800006f4: 121071cb fnmsub.d ft3,ft0,ft1,ft2 + 800006f8: 00373027 fsd ft3,0(a4) + 800006fc: 00102773 frflags a4 + 80000700: 53cc lw a1,36(a5) + 80000702: 852e mv a0,a1 + 80000704: f585 bnez a1,8000062c + 80000706: 5790 lw a2,40(a5) + 80000708: b3dd j 800004ee + 8000070a: fe840713 addi a4,s0,-24 + 8000070e: 00101073 fsflags zero + 80000712: 0007b007 fld ft0,0(a5) + 80000716: 0087b087 fld ft1,8(a5) + 8000071a: 0107b107 fld ft2,16(a5) + 8000071e: 121071c7 fmsub.d ft3,ft0,ft1,ft2 + 80000722: 00373027 fsd ft3,0(a4) + 80000726: 00102773 frflags a4 + 8000072a: 53cc lw a1,36(a5) + 8000072c: 852e mv a0,a1 + 8000072e: ee059fe3 bnez a1,8000062c + 80000732: 5790 lw a2,40(a5) + 80000734: bb55 j 800004e8 + 80000736: 02000513 li a0,32 + 8000073a: b145 j 800003da diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/baseline-simulation/smoke.elf b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/baseline-simulation/smoke.elf new file mode 100644 index 0000000..060d443 Binary files /dev/null and b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/baseline-simulation/smoke.elf differ diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/baseline-simulation/smoke.hex b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/baseline-simulation/smoke.hex new file mode 100644 index 0000000..b6b2e9e --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/baseline-simulation/smoke.hex @@ -0,0 +1,87872 @@ +37 +21 +00 +00 +1b +01 +11 +00 +13 +11 +21 +01 +13 +01 +01 +ff +97 +02 +00 +00 +93 +82 +c2 +04 +73 +90 +52 +30 +73 +10 +40 +30 +73 +10 +20 +30 +b7 +e2 +01 +00 +73 +a0 +02 +30 +97 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memory_aw_bits_size; + wire [1:0] memory_aw_bits_burst; + wire memory_aw_bits_lock; + wire [3:0] memory_aw_bits_cache; + wire [2:0] memory_aw_bits_prot; + wire [3:0] memory_aw_bits_qos; + wire memory_w_ready; + wire memory_w_valid; + wire [127:0] memory_w_bits_data; + wire [15:0] memory_w_bits_strb; + wire memory_w_bits_last; + wire memory_b_ready; + wire memory_b_valid; + wire [3:0] memory_b_bits_id; + wire [1:0] memory_b_bits_resp; + wire memory_ar_ready; + wire memory_ar_valid; + wire [3:0] memory_ar_bits_id; + wire [31:0] memory_ar_bits_addr; + wire [7:0] memory_ar_bits_len; + wire [2:0] memory_ar_bits_size; + wire [1:0] memory_ar_bits_burst; + wire memory_ar_bits_lock; + wire [3:0] memory_ar_bits_cache; + wire [2:0] memory_ar_bits_prot; + wire [3:0] memory_ar_bits_qos; + wire memory_r_ready; + wire memory_r_valid; + wire [3:0] memory_r_bits_id; + wire [127:0] memory_r_bits_data; + wire [1:0] memory_r_bits_resp; + wire memory_r_bits_last; + wire peripherals_aw_ready; + wire peripherals_aw_valid; + wire [1:0] peripherals_aw_bits_id; + wire [30:0] peripherals_aw_bits_addr; + wire [7:0] peripherals_aw_bits_len; + wire [2:0] peripherals_aw_bits_size; + wire [1:0] peripherals_aw_bits_burst; + wire peripherals_aw_bits_lock; + wire [3:0] peripherals_aw_bits_cache; + wire [2:0] peripherals_aw_bits_prot; + wire [3:0] peripherals_aw_bits_qos; + wire peripherals_w_ready; + wire peripherals_w_valid; + wire [63:0] peripherals_w_bits_data; + wire [7:0] peripherals_w_bits_strb; + wire peripherals_w_bits_last; + wire peripherals_b_ready; + wire peripherals_b_valid; + wire [1:0] peripherals_b_bits_id; + wire [1:0] peripherals_b_bits_resp; + wire peripherals_ar_ready; + wire peripherals_ar_valid; + wire [1:0] peripherals_ar_bits_id; + wire [30:0] peripherals_ar_bits_addr; + wire [7:0] peripherals_ar_bits_len; + wire [2:0] peripherals_ar_bits_size; + wire [1:0] peripherals_ar_bits_burst; + wire peripherals_ar_bits_lock; + wire [3:0] peripherals_ar_bits_cache; + wire [2:0] peripherals_ar_bits_prot; + wire [3:0] peripherals_ar_bits_qos; + wire peripherals_r_ready; + wire peripherals_r_valid; + wire [1:0] peripherals_r_bits_id; + wire [63:0] peripherals_r_bits_data; + wire [1:0] peripherals_r_bits_resp; + wire peripherals_r_bits_last; + ToyLinuxChip dut(.*); + integer cycle_count=0; + always @(posedge clock) if (!reset) cycle_count<=cycle_count+1; + always #5 clock=~clock; + initial begin reset=1; repeat(20) @(negedge clock); reset=0; end + initial begin repeat(5000000) @(posedge clock); $fatal(1,"CPU timeout"); end + axi_smoke_memory #(.DATA_BITS(128), .ID_BITS(4), .ADDR_BITS(32), .BASE(32'h80000000), .CAPACITY(262144), .IMAGE("smoke.hex")) memory_model ( + .clock(clock), + .reset(reset), + .aw_ready(memory_aw_ready), + .aw_valid(memory_aw_valid), + .aw_bits_id(memory_aw_bits_id), + .aw_bits_addr(memory_aw_bits_addr), + .aw_bits_len(memory_aw_bits_len), + .aw_bits_size(memory_aw_bits_size), + .aw_bits_burst(memory_aw_bits_burst), + .w_ready(memory_w_ready), + .w_valid(memory_w_valid), + .w_bits_data(memory_w_bits_data), + .w_bits_strb(memory_w_bits_strb), + .w_bits_last(memory_w_bits_last), + .b_ready(memory_b_ready), + .b_valid(memory_b_valid), + .b_bits_id(memory_b_bits_id), + .b_bits_resp(memory_b_bits_resp), + .ar_ready(memory_ar_ready), + .ar_valid(memory_ar_valid), + .ar_bits_id(memory_ar_bits_id), + .ar_bits_addr(memory_ar_bits_addr), + .ar_bits_len(memory_ar_bits_len), + .ar_bits_size(memory_ar_bits_size), + .ar_bits_burst(memory_ar_bits_burst), + .r_ready(memory_r_ready), + .r_valid(memory_r_valid), + .r_bits_id(memory_r_bits_id), + .r_bits_data(memory_r_bits_data), + .r_bits_resp(memory_r_bits_resp), + .r_bits_last(memory_r_bits_last) + ); + axi_smoke_memory #(.DATA_BITS(64), .ID_BITS(2), .ADDR_BITS(31), .BASE(32'h60000000), .CAPACITY(4096), .MONITOR(1), .TEST_LABEL("whole Toy baseline FPU 1536 oracle vectors")) peripherals_model ( + .clock(clock), + .reset(reset), + .aw_ready(peripherals_aw_ready), + .aw_valid(peripherals_aw_valid), + .aw_bits_id(peripherals_aw_bits_id), + .aw_bits_addr(peripherals_aw_bits_addr), + .aw_bits_len(peripherals_aw_bits_len), + .aw_bits_size(peripherals_aw_bits_size), + .aw_bits_burst(peripherals_aw_bits_burst), + .w_ready(peripherals_w_ready), + .w_valid(peripherals_w_valid), + .w_bits_data(peripherals_w_bits_data), + .w_bits_strb(peripherals_w_bits_strb), + .w_bits_last(peripherals_w_bits_last), + .b_ready(peripherals_b_ready), + .b_valid(peripherals_b_valid), + .b_bits_id(peripherals_b_bits_id), + .b_bits_resp(peripherals_b_bits_resp), + .ar_ready(peripherals_ar_ready), + .ar_valid(peripherals_ar_valid), + .ar_bits_id(peripherals_ar_bits_id), + .ar_bits_addr(peripherals_ar_bits_addr), + .ar_bits_len(peripherals_ar_bits_len), + .ar_bits_size(peripherals_ar_bits_size), + .ar_bits_burst(peripherals_ar_bits_burst), + .r_ready(peripherals_r_ready), + .r_valid(peripherals_r_valid), + .r_bits_id(peripherals_r_bits_id), + .r_bits_data(peripherals_r_bits_data), + .r_bits_resp(peripherals_r_bits_resp), + .r_bits_last(peripherals_r_bits_last) + ); + final $display("MEASURE cycles=%0d memory_reads=%0d memory_writes=%0d", cycle_count, memory_model.read_bursts, memory_model.write_bursts); +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/baseline-simulation/verilator-build.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/baseline-simulation/verilator-build.log new file mode 100644 index 0000000..25e3801 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/baseline-simulation/verilator-build.log @@ -0,0 +1,2135 @@ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:31:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 31 | module NonSyncResetSynchronizerPrimitiveShiftReg_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ + ... For warning description see https://verilator.org/warn/TIMESCALEMOD?v=5.050 + ... Use "/* verilator lint_off TIMESCALEMOD */" and lint_on around source to disable this message. +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:48:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 48 | module SynchronizerShiftReg_w1_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:61:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 61 | module IntSyncAsyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:74:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 74 | module AsyncResetRegVec_w1_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:103:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 103 | module IntSyncCrossingSource_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:118:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 118 | module FixedClockBroadcast_3( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:139:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 139 | module TLMonitor( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:987:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 987 | module TLMonitor_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:2434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 2434 | module TLXbar_sbus_i2_o3_a32d128s3k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:3195:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3195 | module TLMonitor_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:4151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4151 | module Repeater_TLBundleA_a28d128s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:4218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4218 | module TLWidthWidget16( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:4386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4386 | module TLInterconnectCoupler_sbus_to_bus_named_cbus( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:4478:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4478 | module ram_2x58( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:4497:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4497 | module Queue2_AXI4BundleAW( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:4581:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4581 | module ram_2x73( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:4600:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4600 | module Queue2_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:4657:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4657 | module ram_2x4( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:4676:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4676 | module Queue2_AXI4BundleB( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:4729:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4729 | module Queue2_AXI4BundleAR( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:4813:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4813 | module ram_2x69( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:4832:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4832 | module Queue2_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:4891:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4891 | module AXI4Buffer( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:5067:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5067 | module ram_2x8( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:5086:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5086 | module Queue2_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:5143:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5143 | module Queue1_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:5178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5178 | module AXI4UserYanker( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:5540:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5540 | module ram_8x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:5559:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5559 | module Queue8_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:5631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5631 | module AXI4Deinterleaver( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:6073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6073 | module AXI4IdIndexer( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:6219:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6219 | module TLMonitor_3( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:7048:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7048 | module Queue1_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:7082:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7082 | module Queue1_AXI4BundleARW( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:7148:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7148 | module TLToAXI4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:7529:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7529 | module TLMonitor_4( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:8396:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8396 | module Repeater_TLBundleA_a31d128s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:8463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8463 | module TLWidthWidget16_2( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:8623:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8623 | module TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:9400:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 9400 | module SystemBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:10050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10050 | module FixedClockBroadcast_4( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:10073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10073 | module TLMonitor_5( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:10975:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10975 | module TLXbar_cbus_out_i1_o4_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:11288:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +11288 | module TLMonitor_6( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:12202:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12202 | module ram_2x114( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:12221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12221 | module Queue2_TLBundleA_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:12301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12301 | module ram_2x79( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:12320:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12320 | module Queue2_TLBundleD_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:12399:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12399 | module TLBuffer_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:12534:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12534 | module TLMonitor_7( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:13449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13449 | module TLAtomicAutomata_cbus( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:13973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13973 | module TLMonitor_8( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:14799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14799 | module Queue1_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:14846:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14846 | module TLError( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:14953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14953 | module TLMonitor_9( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:15857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15857 | module ram_2x100( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:15876:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15876 | module Queue2_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:15955:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15955 | module Queue2_TLBundleD_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:16028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16028 | module TLBuffer_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:16155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16155 | module ErrorDeviceWrapper( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:16258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16258 | module TLMonitor_10( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:17017:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17017 | module Repeater_TLBundleA_a26d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:17081:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17081 | module TLFragmenter_CLINT( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:17261:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17261 | module TLInterconnectCoupler_cbus_to_clint( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:17336:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17336 | module TLMonitor_11( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:18106:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18106 | module Repeater_TLBundleA_a28d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:18170:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18170 | module TLFragmenter_PLIC( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:18350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18350 | module TLInterconnectCoupler_cbus_to_plic( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:18425:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18425 | module TLMonitor_12( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:19040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19040 | module Repeater_TLBundleA_a17d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:19104:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19104 | module TLFragmenter_bootrom( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:19263:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19263 | module TLInterconnectCoupler_cbus_to_bootrom( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:19330:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19330 | module PeripheryBus_cbus( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:19882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19882 | module TLMonitor_13( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:20610:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20610 | module ProbePicker( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:20688:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20688 | module ram_2x10( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:20707:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20707 | module Queue2_BundleMap_6( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:20764:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20764 | module AXI4UserYanker_1( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:21713:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21713 | module AXI4IdIndexer_1( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:21859:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21859 | module TLMonitor_14( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:22587:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22587 | module Queue1_AXI4BundleW_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:22621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22621 | module Queue1_AXI4BundleARW_1( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:22687:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22687 | module TLToAXI4_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:23555:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +23555 | module TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:24031:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24031 | module MemoryBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:24349:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24349 | module TLMonitor_15( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:25732:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25732 | module BroadcastFilter( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:25756:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25756 | module ram_4x144( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:25775:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25775 | module Queue4_TLBroadcastData( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:25828:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25828 | module TLBroadcastTracker( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:25964:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25964 | module TLBroadcastTracker_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:26100:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26100 | module TLBroadcast( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:26686:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26686 | module TLMonitor_16( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:27414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27414 | module BankBinder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:27491:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27491 | module CoherenceManagerWrapper( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:27669:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27669 | module TLMonitor_17( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:29229:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29229 | module TLMonitor_18( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:29635:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29635 | module TLXbar_MasterXbar_BBTile_i2_o1_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:29898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29898 | module IntXbar_i4_o1( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:29918:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29918 | module WritebackUnit( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:30014:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30014 | module ProbeUnit( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:30154:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30154 | module Arbiter1_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:30168:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30168 | module Arbiter1_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:30191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30191 | module Arbiter1_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:30214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30214 | module Arbiter1_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:30249:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30249 | module Arbiter1_Bool( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:30258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30258 | module ram_16x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:30277:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30277 | module Queue16_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:30360:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30360 | module Queue1_TLBundleE_a32d128s1k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:30388:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30388 | module MSHR( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:30835:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30835 | module Arbiter1_HellaCacheResp( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:30879:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30879 | module IOMSHR( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:31790:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31790 | module sdq_17x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:31809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31809 | module MSHRFile( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:32350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32350 | module OptimizationBarrier_TLBEntryData( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:32406:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32406 | module PMPChecker_s3( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:32691:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32691 | module PMAChecker( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:32731:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32731 | module DTLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:35923:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35923 | module L1MetadataArray( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:35990:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35990 | module Arbiter5_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:36023:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36023 | module Arbiter2_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:36055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36055 | module DataArray( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:36151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36151 | module Arbiter4_L1DataReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:36180:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36180 | module Arbiter2_L1DataWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:36206:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36206 | module AMOALU( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:36248:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36248 | module MaxPeriodFibonacciLFSR( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:36342:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36342 | module Arbiter2_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:36377:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36377 | module NonBlockingDCache( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:37660:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37660 | module ICache( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:37914:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37914 | module ShiftQueue( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:38054:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38054 | module PMPChecker_s2( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:38215:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38215 | module ITLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:41129:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41129 | module Frontend( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:41494:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41494 | module TLMonitor_19( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:42301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +42301 | module TLMonitor_20( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:43108:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43108 | module TLXbar_i2_o1_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:43343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43343 | module TLMonitor_21( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:43851:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43851 | module ram_2x116( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:43870:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43870 | module Queue2_TLBundleA_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:43947:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43947 | module ram_2x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:43966:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43966 | module Queue2_TLBundleD_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:44045:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44045 | module TLBuffer_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:44158:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44158 | module TLMonitor_22( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:44783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44783 | module TLBuffer_a32d64s1k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:44892:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44892 | module TLMonitor_23( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:45699:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45699 | module Repeater_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:45766:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45766 | module TLWidthWidget8_4( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:46074:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46074 | module TLMonitor_24( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:46882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46882 | module ram_2x117( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:46901:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46901 | module Queue2_TLBundleA_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:46981:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46981 | module ram_2x78( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:47000:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47000 | module Queue2_TLBundleD_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:47079:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47079 | module TLBuffer_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:47214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47214 | module HellaCacheArbiter( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:47381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47381 | module Arbiter3_Valid_PTWReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:47419:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47419 | module OptimizationBarrier_UInt( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:47427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47427 | module OptimizationBarrier_PTE( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:47459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47459 | module PTW( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:48434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +48434 | module FPUDecoder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:49794:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49794 | module MulAddRecFNToRaw_preMul_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:49878:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49878 | module MulAddRecFNToRaw_postMul_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:50044:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50044 | module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:50148:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50148 | module RoundRawFNToRecFN_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:50177:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50177 | module MulAddRecFNPipe_l4_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:50499:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50499 | module FPUFMAPipe_l5_f32( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:50550:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50550 | module CompareRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:50580:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50580 | module RecFNToIN_e11_s53_i64( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:50629:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50629 | module RecFNToIN_e11_s53_i32( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:50668:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50668 | module FPToInt( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:51131:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51131 | module RoundAnyRawFNToRecFN_ie7_is64_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:51166:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51166 | module PipelinedINToRecFN( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:51269:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51269 | module RoundAnyRawFNToRecFN_ie7_is64_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:51295:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51295 | module PipelinedINToRecFN_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:51370:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51370 | module RoundAnyRawFNToRecFN_ie7_is64_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:51398:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51398 | module PipelinedINToRecFN_2( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:51473:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51473 | module IntToFP( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:51828:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51828 | module RoundAnyRawFNToRecFN_ie11_is53_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:51955:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51955 | module RecFNToRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:51977:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51977 | module RoundAnyRawFNToRecFN_ie11_is53_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:52077:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52077 | module RecFNToRecFN_1( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:52099:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52099 | module FPToFP( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:52225:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52225 | module MulAddRecFNToRaw_preMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:52325:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52325 | module MulAddRecFNToRaw_postMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:52578:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52578 | module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:52712:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52712 | module RoundRawFNToRecFN_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:52741:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52741 | module MulAddRecFNPipe_l4_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:53068:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53068 | module FPUFMAPipe_l6_f64( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:53129:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53129 | module MulAddRecFNToRaw_preMul_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:53202:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53202 | module MulAddRecFNToRaw_postMul_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:53325:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53325 | module RoundAnyRawFNToRecFN_ie5_is13_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:53457:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53457 | module RoundRawFNToRecFN_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:53486:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53486 | module MulAddRecFNPipe_l4_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:53808:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53808 | module FPUFMAPipe_l5_f16( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:53858:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53858 | module DivSqrtRawFN_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:54028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +54028 | module DivSqrtRecFMToRaw_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:54083:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +54083 | module DivSqrtRecFM_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:54143:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +54143 | module DivSqrtRawFN_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:54312:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +54312 | module DivSqrtRecFMToRaw_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:54367:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +54367 | module DivSqrtRecFM_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:54427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +54427 | module DivSqrtRawFN_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:54597:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +54597 | module DivSqrtRecFMToRaw_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:54652:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +54652 | module DivSqrtRecFM_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:54713:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +54713 | module regfile_32x65( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:54758:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +54758 | module FPU( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:55729:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55729 | module RVCExpander( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:56092:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +56092 | module IBuf( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:56216:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +56216 | module CSRFile( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:58132:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58132 | module RocketALU( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:58718:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58718 | module MulDiv( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:59016:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +59016 | module Arbiter3_LLWB( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:59034:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +59034 | module rf_31x64( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:59058:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +59058 | module RocketBB( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:63747:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +63747 | module GlobalDecoder( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:63837:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +63837 | module BankAliasTable( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:65161:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +65161 | module BankScoreboard( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:65536:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +65536 | module GlobalROB( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:69560:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69560 | module Arbiter3_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:69603:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69603 | module ram_16x4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:69622:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69622 | module Queue16_UInt4( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:69668:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69668 | module SubROB( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:70243:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +70243 | module Arbiter1_SubRobRow( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:70608:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +70608 | module GlobalScheduler( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:71859:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71859 | module BootRom( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:71899:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71899 | module Frontend_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:72523:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72523 | module PE( + | ^~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:72542:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72542 | module AlwaysOutTransposer( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:73297:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +73297 | module MacUnit( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:73312:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +73312 | module PE_64( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:73410:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +73410 | module Tile( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:73457:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +73457 | module Mesh( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:76936:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76936 | module TagQueue( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:77077:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77077 | module ram_6x7( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:77096:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77096 | module Queue6_TagWithIdAndTotalRows( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:77157:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77157 | module MeshWithDelays( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:78204:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +78204 | module ram_data_8x64( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:78223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +78223 | module Queue8_SramReadResp( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:78271:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +78271 | module GemminiExCtrl( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:80027:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80027 | module LoopMatmulUnroller( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:80297:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80297 | module LoopConvAddrGen( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:80350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80350 | module LoopConvUnroller( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:80773:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80773 | module LoopCmdEncoder( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:81062:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81062 | module Arbiter2_LoopCmd( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:81255:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81255 | module GemminiBall( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:82430:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82430 | module RRArbiter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:82504:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82504 | module CmdRouter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:82632:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82632 | module BallCyclePMC( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:82742:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82742 | module BBus( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:83545:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83545 | module BallDomainDecoder( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:83675:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83675 | module ram_4x281( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:83694:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83694 | module Queue4_BallReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:83825:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83825 | module Arbiter1_BallRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:83845:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83845 | module BallReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:83975:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83975 | module BallDomain( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:84788:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84788 | module MemDomainDecoder( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:84947:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84947 | module ram_4x158( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:84966:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84966 | module Queue4_MemReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:85068:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85068 | module Arbiter3_MemRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:85110:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85110 | module MemReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:85284:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85284 | module MemLoader( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:85528:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85528 | module MemStorer( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:85787:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85787 | module MemCyclePMC( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:85906:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85906 | module TLB( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:86286:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86286 | module RRArbiter_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:86314:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86314 | module BBTLBCluster( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:86442:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86442 | module StreamReader( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:86807:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86807 | module StreamWriter( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:86888:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86888 | module ZeroLineGenerator( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:86929:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86929 | module MemConfiger( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:87098:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87098 | module MemFrontend( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:87709:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87709 | module MemMidend( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:88170:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +88170 | module SramBank( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:88221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +88221 | module AccPipe( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:88330:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +88330 | module PrivateMemBackend( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:91326:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91326 | module MemBackend( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:91604:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91604 | module MemDomain( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:92522:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92522 | module Queue1_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:92557:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92557 | module GpDomain( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:92589:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92589 | module ram_8x21( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:92608:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92608 | module Queue8_BuckyballAccelerator_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:92672:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92672 | module BuckyballAccelerator( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:94118:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +94118 | module Queue3_UInt2( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:94163:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +94163 | module SimpleHellaCacheIFReplayQueue( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:94216:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +94216 | module Arbiter2_HellaCacheReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:94227:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +94227 | module SimpleHellaCacheIF( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:94317:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +94317 | module BarrierUnit( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:94334:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +94334 | module BBTile( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:96128:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +96128 | module TLMonitor_25( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:96976:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +96976 | module TLMonitor_26( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:98733:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98733 | module ram_2x189( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:98752:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98752 | module Queue2_TLBundleA_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:98832:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98832 | module ram_2x142( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:98851:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98851 | module Queue2_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:98930:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98930 | module Queue2_TLBundleA_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:99008:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99008 | module Queue2_TLBundleD_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:99088:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99088 | module ram_2x60( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:99107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99107 | module Queue2_TLBundleB_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:99171:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99171 | module ram_2x173( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:99190:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99190 | module Queue2_TLBundleC_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:99265:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99265 | module ram_sink_2x1( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:99284:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99284 | module Queue2_TLBundleE_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:99330:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99330 | module TLBuffer_a32d128s2k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:99711:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99711 | module IntSyncSyncCrossingSink_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:99722:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99722 | module IntSyncSyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:99730:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99730 | module TilePRCIDomain( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:100138:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100138 | module BundleBridgeNexus_UInt1_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:100146:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100146 | module TLMonitor_27( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:100765:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100765 | module CLINT( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:100886:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100886 | module AsyncResetRegVec_w2_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:100915:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100915 | module IntSyncCrossingSource_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:100935:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100935 | module CLINTClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:100998:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100998 | module TLMonitor_28( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:101629:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101629 | module LevelGateway( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:101648:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101648 | module PLICFanIn( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:101660:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101660 | module Queue1_RegMapperInput_i23_m8( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:101709:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101709 | module TLPLIC( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:101938:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101938 | module PLICClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:102001:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102001 | module TLMonitor_29( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:102522:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102522 | module TLROM( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:103079:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103079 | module bootromClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:103118:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103118 | module ToyLinuxSystem( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:104366:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104366 | module ToyLinuxChip( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:104533:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104533 | module tag_array( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:104556:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104556 | module array_0_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:104583:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104583 | module array_0_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:104608:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104608 | module array_2_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:104633:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104633 | module array_2_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:104658:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104658 | module bbtile_icache_tag_array( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:104681:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104681 | module bbtile_icache_data_arrays_0( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:104704:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104704 | module bbtile_icache_data_arrays_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:104725:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104725 | module bbtile_icache_data_arrays_2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:104746:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104746 | module bbtile_icache_data_arrays_3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:104767:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104767 | module sram( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:104792:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104792 | module mem( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:104825:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104825 | module plusarg_reader #( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:104850:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104850 | module ITraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:104928:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104928 | module FpgaDspMac(input [7:0] a, b, input [19:0] c, output [19:0] y); + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:104938:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104938 | module PMCTraceDPI( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:104988:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104988 | module MemPMCTraceDPI( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/ToyLinuxChip.sv:105038:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +105038 | module MTraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/FpgaMemories.sv:1:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 1 | module tag_array_ext( input [4:0] RW0_addr, + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/FpgaMemories.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 19 | module array_0_0_ext( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/FpgaMemories.sv:37:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 37 | module bbtile_icache_tag_array_ext( input [5:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/FpgaMemories.sv:55:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 55 | module bbtile_icache_data_arrays_0_ext( input [7:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/FpgaMemories.sv:73:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 73 | module sram_ext( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/reference-fpu/FpgaMemories.sv:90:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 90 | module mem_ext( input [9:0] RW0_addr, + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:3:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3 | module axi_smoke_memory #( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:52:20: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'addr' generates 31 bits. + : ... note: In instance 'tb.peripherals_model' + 52 | offset=(addr & ~(LANES-1))-BASE; + | ^ + ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=5.050 + ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:78:28: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'write_addr' generates 31 bits. + : ... note: In instance 'tb.peripherals_model' + 78 | offset=(write_addr & ~(LANES-1))-BASE; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:86:26: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'h600d600d' generates 64 bits. + : ... note: In instance 'tb.memory_model' + 86 | if (w_bits_data==64'h600d600d) begin + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:91:66: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff' generates 64 bits. + : ... note: In instance 'tb.memory_model' + 91 | $fatal(1,"CPU smoke failed at stage %0d",w_bits_data & 64'hffff); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:90:28: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff0000' generates 64 bits. + : ... note: In instance 'tb.memory_model' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:90:43: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'hbad00000' generates 64 bits. + : ... note: In instance 'tb.memory_model' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^~ +make: Entering directory '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/obj' +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_timing.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_timing.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_threads.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_threads.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb__pch.h -o Vtb__pch.h.fast.gch +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb__pch.h -o Vtb__pch.h.slow.gch +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__0.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__1.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__2.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__3.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__4.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__5.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__6.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__7.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__8.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__9.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb__main.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb__ConstPool__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__1__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__2__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__3__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb__Syms__Slow.cpp +g++ verilated.o verilated_timing.o verilated_threads.o Vtb__ALL.a -pthread -lpthread -latomic -o Vtb +rm Vtb__ALL.verilator_deplist.tmp +make: Leaving directory '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/baseline-simulation/obj' +- V e r i l a t i o n R e p o r t: Verilator 5.050 2026-07-01 rev v5.050 +- Verilator: Built from 15.576 MB sources in 348 modules, into 23.888 MB in 19 C++ files needing 0.018 MB +- Verilator: Walltime 14.614 s (elab=0.678, cvt=4.041, bld=9.178); cpu 5.725 s on 8 threads; allocated 434.969 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/fpu_vectors.c b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/fpu_vectors.c new file mode 100644 index 0000000..47ab9ab --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/fpu_vectors.c @@ -0,0 +1,1743 @@ +#include +struct Vector { uint64_t a,b,c,expected; unsigned tag,kind,op,rm,flags; }; +static const struct Vector vectors[] = { + {0x1ULL,0x7c00ULL,0xfe00ULL,0x7e00ULL,0,0,0,0,0}, + {0x83ffULL,0x3bffULL,0x3ffULL,0x0ULL,0,0,0,0,3}, + {0x3c00ULL,0x400ULL,0x3c01ULL,0x3c01ULL,0,0,0,0,1}, + {0x3bffULL,0x8000ULL,0x7c00ULL,0x7c00ULL,0,0,0,0,0}, + {0x3800ULL,0x7e00ULL,0x7c01ULL,0x7e00ULL,0,0,0,0,16}, + {0x7c00ULL,0x3800ULL,0x8001ULL,0x7c00ULL,0,0,0,0,0}, + {0x7c01ULL,0x3c00ULL,0xbc00ULL,0x7e00ULL,0,0,0,0,16}, + {0x0ULL,0x8001ULL,0xfbffULL,0x7bffULL,0,0,1,0,0}, + {0x1ULL,0xfe00ULL,0x7e00ULL,0x7e00ULL,0,0,1,0,0}, + {0x83ffULL,0xfbffULL,0x1ULL,0x43fdULL,0,0,1,0,1}, + {0x3c00ULL,0x3c01ULL,0x3c00ULL,0x1400ULL,0,0,1,0,0}, + {0x3bffULL,0x83ffULL,0x7bffULL,0xfbffULL,0,0,1,0,1}, + {0x7bffULL,0x0ULL,0xfe00ULL,0x7e00ULL,0,0,1,0,0}, + {0x7c00ULL,0xfc00ULL,0x8000ULL,0xfc00ULL,0,0,1,0,0}, + {0x7c01ULL,0x4000ULL,0x8400ULL,0x7e00ULL,0,0,1,0,16}, + {0x0ULL,0x8400ULL,0x3800ULL,0x3800ULL,0,0,2,0,0}, + {0x8001ULL,0x1ULL,0x7c01ULL,0x7e00ULL,0,0,2,0,16}, + {0x83ffULL,0x7c01ULL,0x0ULL,0x7e00ULL,0,0,2,0,16}, + {0x3c00ULL,0x7bffULL,0x400ULL,0xfbffULL,0,0,2,0,1}, + {0x3bffULL,0xbc00ULL,0x4000ULL,0x4200ULL,0,0,2,0,1}, + {0x7bffULL,0x3ffULL,0x7e00ULL,0x7e00ULL,0,0,2,0,0}, + {0x7c00ULL,0xfc01ULL,0xfc01ULL,0x7e00ULL,0,0,2,0,16}, + {0x7c01ULL,0x7c00ULL,0x83ffULL,0x7e00ULL,0,0,2,0,16}, + {0x0ULL,0x3bffULL,0x3bffULL,0xbbffULL,0,0,3,0,0}, + {0x8001ULL,0x400ULL,0xfc00ULL,0x7c00ULL,0,0,3,0,0}, + {0x400ULL,0x8000ULL,0x8000ULL,0x0ULL,0,0,3,0,0}, + {0x3c00ULL,0x7e00ULL,0x3ffULL,0x7e00ULL,0,0,3,0,0}, + {0x3bffULL,0x3800ULL,0x3c01ULL,0xbe01ULL,0,0,3,0,1}, + {0x7bffULL,0x3c00ULL,0x7c00ULL,0xfc00ULL,0,0,3,0,0}, + {0xfc00ULL,0x8001ULL,0x0ULL,0xfc00ULL,0,0,3,0,0}, + {0x7c01ULL,0xfe00ULL,0x8001ULL,0x7e00ULL,0,0,3,0,16}, + {0x0ULL,0xfbffULL,0xbc00ULL,0xbc00ULL,0,1,0,0,0}, + {0x8001ULL,0x3c01ULL,0xfbffULL,0xfbffULL,0,1,0,0,1}, + {0x400ULL,0x83ffULL,0xfc01ULL,0x7e00ULL,0,1,0,0,16}, + {0xbc00ULL,0x0ULL,0x83ffULL,0xbc00ULL,0,1,0,0,1}, + {0x3bffULL,0xfc00ULL,0x3c00ULL,0x4000ULL,0,1,0,0,1}, + {0x7bffULL,0x4000ULL,0x7bffULL,0x7c00ULL,0,1,0,0,5}, + {0xfc00ULL,0x8400ULL,0xfe00ULL,0x7e00ULL,0,1,0,0,0}, + {0xfe00ULL,0x1ULL,0x3ffULL,0x7e00ULL,0,1,0,0,0}, + {0x0ULL,0x7c01ULL,0x8400ULL,0x400ULL,0,1,1,0,0}, + {0x8001ULL,0x7bffULL,0x3800ULL,0xb800ULL,0,1,1,0,1}, + {0x400ULL,0xbc00ULL,0x7c01ULL,0x7e00ULL,0,1,1,0,16}, + {0xbc00ULL,0x3ffULL,0x8001ULL,0xbc00ULL,0,1,1,0,1}, + {0x3bffULL,0xfc01ULL,0x400ULL,0x3bffULL,0,1,1,0,1}, + {0x7bffULL,0x7c00ULL,0x4000ULL,0x7bffULL,0,1,1,0,1}, + {0xfc00ULL,0x3bffULL,0x7e00ULL,0x7e00ULL,0,1,1,0,0}, + {0xfe00ULL,0x400ULL,0x1ULL,0x7e00ULL,0,1,1,0,0}, + {0x8000ULL,0x8000ULL,0x3c00ULL,0x0ULL,0,2,0,0,0}, + {0x8001ULL,0x7e00ULL,0x3bffULL,0x7e00ULL,0,2,0,0,0}, + {0x400ULL,0x3800ULL,0xfc00ULL,0x200ULL,0,2,0,0,0}, + {0xbc00ULL,0x3c00ULL,0x8000ULL,0xbc00ULL,0,2,0,0,0}, + {0x4000ULL,0x8001ULL,0x8400ULL,0x8002ULL,0,2,0,0,0}, + {0x7bffULL,0xfe00ULL,0x3c01ULL,0x7e00ULL,0,2,0,0,0}, + {0xfc00ULL,0xfbffULL,0x7c00ULL,0x7c00ULL,0,2,0,0,0}, + {0xfe00ULL,0x3c01ULL,0x0ULL,0x7e00ULL,0,2,0,0,0}, + {0x8000ULL,0x83ffULL,0x400ULL,0x400ULL,0,0,0,1,0}, + {0x3ffULL,0x0ULL,0x4000ULL,0x4000ULL,0,0,0,1,0}, + {0x400ULL,0xfc00ULL,0xfbffULL,0xfc00ULL,0,0,0,1,0}, + {0xbc00ULL,0x4000ULL,0xfc01ULL,0x7e00ULL,0,0,0,1,16}, + {0x4000ULL,0x8400ULL,0x83ffULL,0x89ffULL,0,0,0,1,1}, + {0xfbffULL,0x1ULL,0x3bffULL,0x3bf7ULL,0,0,0,1,1}, + {0xfc00ULL,0x7c01ULL,0x7bffULL,0x7e00ULL,0,0,0,1,16}, + {0xfe00ULL,0x7bffULL,0xfe00ULL,0x7e00ULL,0,0,0,1,0}, + {0x8000ULL,0xbc00ULL,0x3ffULL,0x83ffULL,0,0,1,1,0}, + {0x3ffULL,0x3ffULL,0x3c01ULL,0xbc00ULL,0,0,1,1,1}, + {0x400ULL,0xfc01ULL,0x3800ULL,0x7e00ULL,0,0,1,1,16}, + {0xbc00ULL,0x7c00ULL,0x7c01ULL,0x7e00ULL,0,0,1,1,16}, + {0x4000ULL,0x3bffULL,0x8001ULL,0x3fffULL,0,0,1,1,1}, + {0xfbffULL,0x400ULL,0xbc00ULL,0xc1ffULL,0,0,1,1,0}, + {0x7e00ULL,0x8000ULL,0xfbffULL,0x7e00ULL,0,0,1,1,0}, + {0xfe00ULL,0x7e00ULL,0x7e00ULL,0x7e00ULL,0,0,1,1,0}, + {0x8000ULL,0x3800ULL,0x1ULL,0x1ULL,0,0,2,1,0}, + {0x3ffULL,0x3c00ULL,0x3c00ULL,0x3bffULL,0,0,2,1,1}, + {0x8400ULL,0x8001ULL,0x7bffULL,0x7bfeULL,0,0,2,1,1}, + {0xbc00ULL,0xfe00ULL,0xfc00ULL,0x7e00ULL,0,0,2,1,0}, + {0x4000ULL,0xfbffULL,0x8000ULL,0x7bffULL,0,0,2,1,5}, + {0xfbffULL,0x3c01ULL,0x8400ULL,0x7bffULL,0,0,2,1,5}, + {0x7e00ULL,0x83ffULL,0x3800ULL,0x7e00ULL,0,0,2,1,0}, + {0xfc01ULL,0x0ULL,0x7c01ULL,0x7e00ULL,0,0,2,1,16}, + {0x8000ULL,0xfc00ULL,0x0ULL,0x7e00ULL,0,0,3,1,16}, + {0x3ffULL,0x4000ULL,0x400ULL,0x89ffULL,0,0,3,1,0}, + {0x8400ULL,0x8400ULL,0x4000ULL,0xc000ULL,0,0,3,1,1}, + {0x3c01ULL,0x1ULL,0x7e00ULL,0x7e00ULL,0,0,3,1,0}, + {0x4000ULL,0x7c01ULL,0xfc01ULL,0x7e00ULL,0,0,3,1,16}, + {0xfbffULL,0x7bffULL,0x83ffULL,0x7bffULL,0,0,3,1,5}, + {0x7e00ULL,0xbc00ULL,0x3bffULL,0x7e00ULL,0,0,3,1,0}, + {0xfc01ULL,0x3ffULL,0xfc00ULL,0x7e00ULL,0,0,3,1,16}, + {0x8000ULL,0xfc01ULL,0xfe00ULL,0x7e00ULL,0,1,0,1,0}, + {0x3ffULL,0x7c00ULL,0x3ffULL,0x7feULL,0,1,0,1,0}, + {0x8400ULL,0x3bffULL,0x3c01ULL,0x3c00ULL,0,1,0,1,1}, + {0x3c01ULL,0x400ULL,0x7c00ULL,0x7c00ULL,0,1,0,1,0}, + {0x3800ULL,0x8000ULL,0x0ULL,0x3800ULL,0,1,0,1,0}, + {0xfbffULL,0x7e00ULL,0x8001ULL,0xfbffULL,0,1,0,1,1}, + {0x7e00ULL,0x3800ULL,0xbc00ULL,0x7e00ULL,0,1,0,1,0}, + {0xfc01ULL,0x3c00ULL,0xfbffULL,0x7e00ULL,0,1,0,1,16}, + {0x1ULL,0x8001ULL,0xfc01ULL,0x7e00ULL,0,1,1,1,16}, + {0x3ffULL,0xfe00ULL,0x1ULL,0x3feULL,0,1,1,1,0}, + {0x8400ULL,0xfbffULL,0x3c00ULL,0xbc00ULL,0,1,1,1,1}, + {0x3c01ULL,0x3c01ULL,0x7bffULL,0xfbfeULL,0,1,1,1,1}, + {0x3800ULL,0x83ffULL,0xfe00ULL,0x7e00ULL,0,1,1,1,0}, + {0x7c00ULL,0x0ULL,0x3ffULL,0x7c00ULL,0,1,1,1,0}, + {0x7e00ULL,0xfc00ULL,0x8400ULL,0x7e00ULL,0,1,1,1,0}, + {0xfc01ULL,0x4000ULL,0x3800ULL,0x7e00ULL,0,1,1,1,16}, + {0x1ULL,0x8400ULL,0x7c01ULL,0x8000ULL,0,2,0,1,3}, + {0x83ffULL,0x1ULL,0x8001ULL,0x8000ULL,0,2,0,1,3}, + {0x8400ULL,0x7c01ULL,0x400ULL,0x7e00ULL,0,2,0,1,16}, + {0x3c01ULL,0x7bffULL,0x4000ULL,0x7bffULL,0,2,0,1,5}, + {0x3800ULL,0xbc00ULL,0x7e00ULL,0xb800ULL,0,2,0,1,0}, + {0x7c00ULL,0x3ffULL,0x1ULL,0x7c00ULL,0,2,0,1,0}, + {0x7e00ULL,0xfc01ULL,0x83ffULL,0x7e00ULL,0,2,0,1,16}, + {0xfc01ULL,0x7c00ULL,0x3bffULL,0x7e00ULL,0,2,0,1,16}, + {0x1ULL,0x3bffULL,0xfc00ULL,0xfc00ULL,0,0,0,2,0}, + {0x83ffULL,0x400ULL,0x8000ULL,0x8001ULL,0,0,0,2,3}, + {0x3c00ULL,0x8000ULL,0x8400ULL,0x8400ULL,0,0,0,2,0}, + {0x3c01ULL,0x7e00ULL,0x3c01ULL,0x7e00ULL,0,0,0,2,0}, + {0x3800ULL,0x3800ULL,0x7c00ULL,0x7c00ULL,0,0,0,2,0}, + {0x7c00ULL,0x3c00ULL,0x0ULL,0x7c00ULL,0,0,0,2,0}, + {0x7c01ULL,0x8001ULL,0x400ULL,0x7e00ULL,0,0,0,2,16}, + {0xfc01ULL,0xfe00ULL,0xbc00ULL,0x7e00ULL,0,0,0,2,16}, + {0x1ULL,0xfbffULL,0xfbffULL,0x7bfeULL,0,0,1,2,1}, + {0x83ffULL,0x3c01ULL,0xfc01ULL,0x7e00ULL,0,0,1,2,16}, + {0x3c00ULL,0x83ffULL,0x83ffULL,0x8000ULL,0,0,1,2,0}, + {0x3bffULL,0x0ULL,0x3bffULL,0xbbffULL,0,0,1,2,0}, + {0x3800ULL,0xfc00ULL,0x7bffULL,0xfc00ULL,0,0,1,2,0}, + {0x7c00ULL,0x4000ULL,0xfe00ULL,0x7e00ULL,0,0,1,2,0}, + {0x7c01ULL,0x8400ULL,0x3ffULL,0x7e00ULL,0,0,1,2,16}, + {0x0ULL,0x1ULL,0x3c01ULL,0x3c01ULL,0,0,2,2,0}, + {0x1ULL,0x7c01ULL,0x3800ULL,0x7e00ULL,0,0,2,2,16}, + {0x83ffULL,0x7bffULL,0x7c01ULL,0x7e00ULL,0,0,2,2,16}, + {0x3c00ULL,0xbc00ULL,0x8001ULL,0x3bffULL,0,0,2,2,1}, + {0x3bffULL,0x3ffULL,0xbc00ULL,0xbc01ULL,0,0,2,2,1}, + {0x3800ULL,0xfc01ULL,0x4000ULL,0x7e00ULL,0,0,2,2,16}, + {0x7c00ULL,0x7c00ULL,0x7e00ULL,0x7e00ULL,0,0,2,2,0}, + {0x7c01ULL,0x3bffULL,0x1ULL,0x7e00ULL,0,0,2,2,16}, + {0x0ULL,0x400ULL,0x3c00ULL,0xbc00ULL,0,0,3,2,0}, + {0x8001ULL,0x8000ULL,0x7bffULL,0xfbffULL,0,0,3,2,0}, + {0x83ffULL,0x7e00ULL,0xfc00ULL,0x7e00ULL,0,0,3,2,0}, + {0x3c00ULL,0x3800ULL,0x8000ULL,0xb800ULL,0,0,3,2,0}, + {0x3bffULL,0x3c00ULL,0x8400ULL,0xbbffULL,0,0,3,2,1}, + {0x7bffULL,0x8001ULL,0x3800ULL,0xb7f1ULL,0,0,3,2,1}, + {0x7c00ULL,0xfe00ULL,0x7c00ULL,0x7e00ULL,0,0,3,2,0}, + {0x7c01ULL,0xfbffULL,0x0ULL,0x7e00ULL,0,0,3,2,16}, + {0x0ULL,0x3c01ULL,0x400ULL,0x400ULL,0,1,0,2,0}, + {0x8001ULL,0x83ffULL,0x4000ULL,0x3fffULL,0,1,0,2,1}, + {0x400ULL,0x0ULL,0x7e00ULL,0x7e00ULL,0,1,0,2,0}, + {0x3c00ULL,0xfc00ULL,0xfc01ULL,0x7e00ULL,0,1,0,2,16}, + {0x3bffULL,0x4000ULL,0x83ffULL,0x3bfeULL,0,1,0,2,1}, + {0x7bffULL,0x8400ULL,0x3bffULL,0x7bffULL,0,1,0,2,1}, + {0xfc00ULL,0x1ULL,0xfc00ULL,0xfc00ULL,0,1,0,2,0}, + {0x7c01ULL,0x7c01ULL,0xfe00ULL,0x7e00ULL,0,1,0,2,16}, + {0x0ULL,0x7bffULL,0x3ffULL,0x83ffULL,0,1,1,2,0}, + {0x8001ULL,0xbc00ULL,0x3c01ULL,0xbc02ULL,0,1,1,2,1}, + {0x400ULL,0x3ffULL,0x7c00ULL,0xfc00ULL,0,1,1,2,0}, + {0x3c00ULL,0xfc01ULL,0x7c01ULL,0x7e00ULL,0,1,1,2,16}, + {0x3bffULL,0x7c00ULL,0x8001ULL,0x3bffULL,0,1,1,2,1}, + {0x7bffULL,0x3bffULL,0xbc00ULL,0x7bffULL,0,1,1,2,1}, + {0xfc00ULL,0x400ULL,0xfbffULL,0xfc00ULL,0,1,1,2,0}, + {0xfe00ULL,0x8000ULL,0xfc01ULL,0x7e00ULL,0,1,1,2,16}, + {0x0ULL,0x7e00ULL,0x1ULL,0x7e00ULL,0,2,0,2,0}, + {0x8001ULL,0x3800ULL,0x3c00ULL,0x8001ULL,0,2,0,2,3}, + {0x400ULL,0x3c00ULL,0x7bffULL,0x400ULL,0,2,0,2,0}, + {0xbc00ULL,0x8001ULL,0xfe00ULL,0x1ULL,0,2,0,2,0}, + {0x3bffULL,0xfe00ULL,0x8000ULL,0x7e00ULL,0,2,0,2,0}, + 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{0x4d61ed7ff0a4da10ULL,0x3dd11abc17df0be5ULL,0x41e7acb35377eea5ULL,0xeea5ULL,0,0,2,0,1}, + {0x63fcb72a8e0d1b91ULL,0x81012ba8c6546bd1ULL,0xb7214fa98666a3e0ULL,0x63fcb72a8e0d1b91ULL,2,1,0,4,1}, + {0x6f2187ce4d9504b3ULL,0x71ede10cbcdc0f80ULL,0x4403789ce459c2edULL,0x0ULL,0,2,0,1,3}, + {0x910fde3f201ac822ULL,0xc890b11f88f9f1a2ULL,0xa1dbfaa898a36409ULL,0x98a36408ULL,1,0,2,3,1}, + {0xa3429f5bf9e56303ULL,0x8a4f302da67c5095ULL,0xb38068ff53973f56ULL,0xb38068ff53973f57ULL,2,1,0,2,1}, + {0x3aab2d20c2c1bd7fULL,0x188bafb8c1a58385ULL,0x6a077b6d05cde430ULL,0x44fa8557ULL,1,2,0,4,1}, + {0x5b76eb6983a979b2ULL,0x2175771f84e52b0bULL,0x214f1ee225e0aa93ULL,0x79b2ULL,0,1,1,4,1}, + {0x9b368d8d409779f0ULL,0xd35e0b11d54ded87ULL,0x7dc529d84ee64d1cULL,0x7dc529d84ee64d1cULL,2,0,2,3,1}, + {0x6d2f94c22472e3b6ULL,0xe619c043dccef410ULL,0xe0ed0329eadf73a3ULL,0xc1c45acdULL,1,2,0,4,1}, + {0xa77d4f413c9303a5ULL,0x9f13721a584a598cULL,0x35ae8985616f811fULL,0x210cULL,0,0,0,0,1}, + {0x4c9adda02c32fe38ULL,0x90b659b8b47ad1dbULL,0x9787d11e22fe822eULL,0x4c9adda02c32fe38ULL,2,1,0,0,1}, + {0x34007430195ad969ULL,0x5cd04a25c3846cfULL,0x94ed7274f7dcf011ULL,0x361d88ccULL,1,2,0,4,1}, + {0xc8f0776209b21440ULL,0xf8fe6e8896f6bf75ULL,0x68664e3a02743f7dULL,0xbf7cULL,0,1,1,4,1}, + {0xdead708dab3be55aULL,0x1a56880166d756b5ULL,0x7993505e9d1fd783ULL,0xb914ba8109f23925ULL,2,2,0,0,1}, + {0x22b7448a7c48c34aULL,0x708e31ffe336f3f6ULL,0xfa77172b22f08a13ULL,0xff800000ULL,1,0,0,2,5}, + {0xa4f54a372f8c58b2ULL,0x17a0a57a5ec00fc1ULL,0x21c6005e954c70c1ULL,0xf0aeULL,0,1,1,0,1}, + {0x352d2c8a8b21898bULL,0xee6cea0f54ed7b77ULL,0xe91335249a308fbULL,0x49a308faULL,1,1,0,2,1}, + {0x6b56d643e9dbfee2ULL,0x653e155ef8f8178cULL,0xf039793e54a3c306ULL,0x7e00ULL,0,2,0,0,0}, + {0x24b66848fa588c2bULL,0x36adb063a71ef100ULL,0x33e9abe596f95b83ULL,0xb3e9abe596f95b83ULL,2,1,1,0,1}, + {0x3796df19100aad51ULL,0x1218d2546ddf4ee5ULL,0x82ba490bc72928c6ULL,0xc72928c6ULL,1,1,0,0,1}, + {0x666c5fe9fac6074bULL,0xb15cc1c6eb19aba9ULL,0x4bd7160ba2face6fULL,0xd7d97fbf988ca1d5ULL,2,0,0,3,1}, + {0xe20cc1da96dea2adULL,0x1e92e54ae088d942ULL,0x46d780bb3e75e2ddULL,0x4063ULL,0,2,0,4,1}, + {0x6a3aeef89c116a22ULL,0xd1c27a618c0031eeULL,0x5ceddc064d9ae8cfULL,0x4d9ae8cfULL,1,1,0,4,1}, + {0x497ee4e974b143eaULL,0x5d8f9b2a7fdbb42dULL,0x59a67188f63ffe75ULL,0x671e838ffbbbf8adULL,2,0,0,3,1}, + {0x7b80bf4a61d0c4a5ULL,0xa0c969d35869cc46ULL,0xbb034fa9839e2c39ULL,0xd4f5ULL,0,0,2,3,1}, + {0x302a0b5d9d565a63ULL,0x84a1f63431ed453bULL,0x32461ddbc533bb77ULL,0x4533bb76ULL,1,1,1,1,1}, + {0xa8e8a815b6d84fb7ULL,0x244cc355faec2459ULL,0x8e382e05f20cc786ULL,0x8d462995842046dbULL,2,2,0,2,1}, + {0x66fb6f436a8418b9ULL,0x9dbc940c7074ba16ULL,0x46f78bd708967394ULL,0xf394ULL,0,1,1,4,1}, + {0xcde685235e749a30ULL,0x4f8b46fc0a5e2f94ULL,0xa7c58ff762dd07a6ULL,0xcde685235e749a2fULL,2,1,1,3,1}, + {0x950bba8914369e18ULL,0xeaab4b705871644dULL,0xcc72b8db16d93d97ULL,0xc68dULL,0,2,0,0,1}, + {0x875641c3f64b1c47ULL,0xf6bf3b5398ba7e0cULL,0xcda15d541bd2cc25ULL,0x4da15d541bd2cc24ULL,2,1,1,2,1}, + {0x10026d7cb0f0c713ULL,0xc820c698146073b0ULL,0xcb37732e47095c22ULL,0xfc00ULL,0,2,0,4,5}, + {0xa8def5c820847fdaULL,0xda5862fe9e7c1b2cULL,0x4081fcd56770e08cULL,0x4347981d25811578ULL,2,0,1,2,1}, + {0x54e78995ebe17ce3ULL,0x94e150e83f3e74fbULL,0x27c2ee2d1f010c08ULL,0x7e00ULL,0,1,0,0,16}, + {0x1894c394ac13b1aaULL,0xcab115b2d640aa3bULL,0x213a28efbd6dcbf8ULL,0xa3562bf6bfd20678ULL,2,0,0,2,1}, + {0xddc556161aa65638ULL,0x819e4fee920ccd69ULL,0xb814e05dc4eabc2dULL,0xe835ULL,0,2,0,2,1}, + {0x2c4dd70579c39d5ULL,0x9948d32242d865e4ULL,0x2f359828ecb6c0f4ULL,0x644bULL,0,2,0,4,1}, + {0xab304c7f663fee53ULL,0x4e589234e34ecf41ULL,0x99ddbe4b28abafbdULL,0x399907af041090b2ULL,2,0,3,2,1}, + {0xb891c3377b69cc93ULL,0xe5db266256f3ffb4ULL,0xb32bdf03f77d28bdULL,0x5e7e240a7043a358ULL,2,2,0,3,1}, +}; +static uint64_t execute(const struct Vector *v, uint64_t *flags) { + uint64_t result = 0, f; + asm volatile("csrw frm, %0" :: "r"((uint64_t)v->rm)); + if (v->tag == 0) { + if (v->kind == 0 && v->op == 0) { + asm volatile("csrw fflags, zero\n" + "flh ft0, 0(%2)\nflh ft1, 8(%2)\nflh ft2, 16(%2)\n" + "fmadd.h ft3, ft0, ft1, ft2, dyn\nfsh ft3, 0(%1)\nfrflags %0\n" + : "=r"(f) : "r"(&result), "r"(v) + : "memory", "ft0", "ft1", "ft2", "ft3"); + } + if (v->kind == 0 && v->op == 1) { + asm volatile("csrw fflags, zero\n" + "flh ft0, 0(%2)\nflh ft1, 8(%2)\nflh ft2, 16(%2)\n" + "fmsub.h ft3, ft0, ft1, ft2, dyn\nfsh ft3, 0(%1)\nfrflags %0\n" + : "=r"(f) : "r"(&result), "r"(v) + : "memory", "ft0", "ft1", "ft2", "ft3"); + } + if (v->kind == 0 && v->op == 2) { + asm volatile("csrw fflags, zero\n" + "flh ft0, 0(%2)\nflh ft1, 8(%2)\nflh ft2, 16(%2)\n" + "fnmsub.h ft3, ft0, ft1, ft2, dyn\nfsh ft3, 0(%1)\nfrflags %0\n" + : "=r"(f) : "r"(&result), "r"(v) + : "memory", "ft0", "ft1", "ft2", "ft3"); + } + if (v->kind == 0 && v->op == 3) { + asm volatile("csrw fflags, zero\n" + "flh ft0, 0(%2)\nflh ft1, 8(%2)\nflh ft2, 16(%2)\n" + "fnmadd.h ft3, ft0, ft1, ft2, dyn\nfsh ft3, 0(%1)\nfrflags %0\n" + : "=r"(f) : "r"(&result), "r"(v) + : "memory", "ft0", "ft1", "ft2", "ft3"); + } + if (v->kind == 1 && v->op == 0) { + asm volatile("csrw fflags, zero\n" + "flh ft0, 0(%2)\nflh ft1, 8(%2)\nflh ft2, 16(%2)\n" + "fadd.h ft3, ft0, ft2, dyn\nfsh ft3, 0(%1)\nfrflags %0\n" + : "=r"(f) : "r"(&result), "r"(v) + : "memory", "ft0", "ft1", "ft2", "ft3"); + } + if (v->kind == 1 && v->op == 1) { + asm volatile("csrw fflags, zero\n" + "flh ft0, 0(%2)\nflh ft1, 8(%2)\nflh ft2, 16(%2)\n" + "fsub.h ft3, ft0, ft2, dyn\nfsh ft3, 0(%1)\nfrflags %0\n" + : "=r"(f) : "r"(&result), "r"(v) + : "memory", "ft0", "ft1", "ft2", "ft3"); + } + if (v->kind == 2 && v->op == 0) { + asm volatile("csrw fflags, zero\n" + "flh ft0, 0(%2)\nflh ft1, 8(%2)\nflh ft2, 16(%2)\n" + "fmul.h ft3, ft0, ft1, dyn\nfsh ft3, 0(%1)\nfrflags %0\n" + : "=r"(f) : "r"(&result), "r"(v) + : "memory", "ft0", "ft1", "ft2", "ft3"); + } + } + else if (v->tag == 1) { + if (v->kind == 0 && v->op == 0) { + asm volatile("csrw fflags, zero\n" + "flw ft0, 0(%2)\nflw ft1, 8(%2)\nflw ft2, 16(%2)\n" + "fmadd.s ft3, ft0, ft1, ft2, dyn\nfsw ft3, 0(%1)\nfrflags %0\n" + : "=r"(f) : "r"(&result), "r"(v) + : "memory", "ft0", "ft1", "ft2", "ft3"); + } + if (v->kind == 0 && v->op == 1) { + asm volatile("csrw fflags, zero\n" + "flw ft0, 0(%2)\nflw ft1, 8(%2)\nflw ft2, 16(%2)\n" + "fmsub.s ft3, ft0, ft1, ft2, dyn\nfsw ft3, 0(%1)\nfrflags %0\n" + : "=r"(f) : "r"(&result), "r"(v) + : "memory", "ft0", "ft1", "ft2", "ft3"); + } + if (v->kind == 0 && v->op == 2) { + asm volatile("csrw fflags, zero\n" + "flw ft0, 0(%2)\nflw ft1, 8(%2)\nflw ft2, 16(%2)\n" + "fnmsub.s ft3, ft0, ft1, ft2, dyn\nfsw ft3, 0(%1)\nfrflags %0\n" + : "=r"(f) : "r"(&result), "r"(v) + : "memory", "ft0", "ft1", "ft2", "ft3"); + } + if (v->kind == 0 && v->op == 3) { + asm volatile("csrw fflags, zero\n" + "flw ft0, 0(%2)\nflw ft1, 8(%2)\nflw ft2, 16(%2)\n" + "fnmadd.s ft3, ft0, ft1, ft2, dyn\nfsw ft3, 0(%1)\nfrflags %0\n" + : "=r"(f) : "r"(&result), "r"(v) + : "memory", "ft0", "ft1", "ft2", "ft3"); + } + if (v->kind == 1 && v->op == 0) { + asm volatile("csrw fflags, zero\n" + "flw ft0, 0(%2)\nflw ft1, 8(%2)\nflw ft2, 16(%2)\n" + "fadd.s ft3, ft0, ft2, dyn\nfsw ft3, 0(%1)\nfrflags %0\n" + : "=r"(f) : "r"(&result), "r"(v) + : "memory", "ft0", "ft1", "ft2", "ft3"); + } + if (v->kind == 1 && v->op == 1) { + asm volatile("csrw fflags, zero\n" + "flw ft0, 0(%2)\nflw ft1, 8(%2)\nflw ft2, 16(%2)\n" + "fsub.s ft3, ft0, ft2, dyn\nfsw ft3, 0(%1)\nfrflags %0\n" + : "=r"(f) : "r"(&result), "r"(v) + : "memory", "ft0", "ft1", "ft2", "ft3"); + } + if (v->kind == 2 && v->op == 0) { + asm volatile("csrw fflags, zero\n" + "flw ft0, 0(%2)\nflw ft1, 8(%2)\nflw ft2, 16(%2)\n" + "fmul.s ft3, ft0, ft1, dyn\nfsw ft3, 0(%1)\nfrflags %0\n" + : "=r"(f) : "r"(&result), "r"(v) + : "memory", "ft0", "ft1", "ft2", "ft3"); + } + } + else if (v->tag == 2) { + if (v->kind == 0 && v->op == 0) { + asm volatile("csrw fflags, zero\n" + "fld ft0, 0(%2)\nfld ft1, 8(%2)\nfld ft2, 16(%2)\n" + "fmadd.d ft3, ft0, ft1, ft2, dyn\nfsd ft3, 0(%1)\nfrflags %0\n" + : "=r"(f) : "r"(&result), "r"(v) + : "memory", "ft0", "ft1", "ft2", "ft3"); + } + if (v->kind == 0 && v->op == 1) { + asm volatile("csrw fflags, zero\n" + "fld ft0, 0(%2)\nfld ft1, 8(%2)\nfld ft2, 16(%2)\n" + "fmsub.d ft3, ft0, ft1, ft2, dyn\nfsd ft3, 0(%1)\nfrflags %0\n" + : "=r"(f) : "r"(&result), "r"(v) + : "memory", "ft0", "ft1", "ft2", "ft3"); + } + if (v->kind == 0 && v->op == 2) { + asm volatile("csrw fflags, zero\n" + "fld ft0, 0(%2)\nfld ft1, 8(%2)\nfld ft2, 16(%2)\n" + "fnmsub.d ft3, ft0, ft1, ft2, dyn\nfsd ft3, 0(%1)\nfrflags %0\n" + : "=r"(f) : "r"(&result), "r"(v) + : "memory", "ft0", "ft1", "ft2", "ft3"); + } + if (v->kind == 0 && v->op == 3) { + asm volatile("csrw fflags, zero\n" + "fld ft0, 0(%2)\nfld ft1, 8(%2)\nfld ft2, 16(%2)\n" + "fnmadd.d ft3, ft0, ft1, ft2, dyn\nfsd ft3, 0(%1)\nfrflags %0\n" + : "=r"(f) : "r"(&result), "r"(v) + : "memory", "ft0", "ft1", "ft2", "ft3"); + } + if (v->kind == 1 && v->op == 0) { + asm volatile("csrw fflags, zero\n" + "fld ft0, 0(%2)\nfld ft1, 8(%2)\nfld ft2, 16(%2)\n" + "fadd.d ft3, ft0, ft2, dyn\nfsd ft3, 0(%1)\nfrflags %0\n" + : "=r"(f) : "r"(&result), "r"(v) + : "memory", "ft0", "ft1", "ft2", "ft3"); + } + if (v->kind == 1 && v->op == 1) { + asm volatile("csrw fflags, zero\n" + "fld ft0, 0(%2)\nfld ft1, 8(%2)\nfld ft2, 16(%2)\n" + "fsub.d ft3, ft0, ft2, dyn\nfsd ft3, 0(%1)\nfrflags %0\n" + : "=r"(f) : "r"(&result), "r"(v) + : "memory", "ft0", "ft1", "ft2", "ft3"); + } + if (v->kind == 2 && v->op == 0) { + asm volatile("csrw fflags, zero\n" + "fld ft0, 0(%2)\nfld ft1, 8(%2)\nfld ft2, 16(%2)\n" + "fmul.d ft3, ft0, ft1, dyn\nfsd ft3, 0(%1)\nfrflags %0\n" + : "=r"(f) : "r"(&result), "r"(v) + : "memory", "ft0", "ft1", "ft2", "ft3"); + } + } + *flags = f; return result; +} +static int dependency_benchmark(void) { + volatile uint64_t *status = (volatile uint64_t *)0x60000000ULL; + { + uint64_t one=0x3c00ULL, result=0, begin, end; + asm volatile("flh ft0, 0(%2)\nflh ft1, 0(%2)\nli t0, 32\ncsrr %0, cycle\n" + "1: .rept 32\nfadd.h ft0, ft0, ft1, rne\n.endr\n" + "addi t0, t0, -1\nbnez t0, 1b\nfsh ft0, 0(%3)\ncsrr %1, cycle\n" + : "=&r"(begin), "=&r"(end) : "r"(&one), "r"(&result) + : "memory", "t0", "ft0", "ft1"); + if (result != 0x6401ULL) return 32; + status[0] = 0x7300000000000000ULL | (end-begin); + } + { + uint64_t one=0x3f800000ULL, result=0, begin, end; + asm volatile("flw ft0, 0(%2)\nflw ft1, 0(%2)\nli t0, 32\ncsrr %0, cycle\n" + "1: .rept 32\nfadd.s ft0, ft0, ft1, rne\n.endr\n" + "addi t0, t0, -1\nbnez t0, 1b\nfsw ft0, 0(%3)\ncsrr %1, cycle\n" + : "=&r"(begin), "=&r"(end) : "r"(&one), "r"(&result) + : "memory", "t0", "ft0", "ft1"); + if (result != 0x44802000ULL) return 32; + status[0] = 0x7300000100000000ULL | (end-begin); + } + { + uint64_t one=0x3ff0000000000000ULL, result=0, begin, end; + asm volatile("fld ft0, 0(%2)\nfld ft1, 0(%2)\nli t0, 32\ncsrr %0, cycle\n" + "1: .rept 32\nfadd.d ft0, ft0, ft1, rne\n.endr\n" + "addi t0, t0, -1\nbnez t0, 1b\nfsd ft0, 0(%3)\ncsrr %1, cycle\n" + : "=&r"(begin), "=&r"(end) : "r"(&one), "r"(&result) + : "memory", "t0", "ft0", "ft1"); + if (result != 0x4090040000000000ULL) return 32; + status[0] = 0x7300000200000000ULL | (end-begin); + } + return 0; +} +int main(void) { + volatile uint64_t *status = (volatile uint64_t *)0x60000000ULL; + for (unsigned i = 0; i < sizeof(vectors)/sizeof(vectors[0]); ++i) { + uint64_t flags; uint64_t actual = execute(&vectors[i], &flags); + if (actual != vectors[i].expected || flags != vectors[i].flags) { + status[2] = i; status[3] = actual; status[4] = vectors[i].expected; + status[5] = flags; status[6] = vectors[i].flags; return 31; + } + } + return dependency_benchmark(); +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/fpu_vectors.elf b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/fpu_vectors.elf new file mode 100644 index 0000000..060d443 Binary files /dev/null and b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/fpu_vectors.elf differ diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/simulation/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/simulation/RESULT.json new file mode 100644 index 0000000..71df845 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/simulation/RESULT.json @@ -0,0 +1,10 @@ +{ + "result": "PASS", + "test_label": "whole Toy shared FPU 1536 oracle vectors", + "core_rtl_sha256": "31e7e07f94d08208dbb564edf9546240df26ff834935bfb646b71b541d875fb9", + "test_binary_sha256": "6b484b5850f3f8f84fdc1bb1d43a15cfc6669d938d4829b69f1ca675df0b16ba", + "cycles_including_boot": 168403, + "memory_read_bursts": 1387, + "memory_write_bursts": 11, + "linux_boot_tested": false +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/simulation/simulation.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/simulation/simulation.log new file mode 100644 index 0000000..6d88c6e --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/simulation/simulation.log @@ -0,0 +1,10 @@ +CPU status = 7300000000002048 +CPU status = 7300000100002063 +CPU status = 7300000200002015 +CPU status = 00000000600d600d +PASS whole Toy shared FPU 1536 oracle vectors +- /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:88: Verilog $finish +MEASURE cycles=168403 memory_reads=1387 memory_writes=11 +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 2ms; walltime 1.552 s; speed 1.085 ms/s +- Verilator: cpu 1.552 s on 1 threads; allocated 8 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/simulation/smoke.bin b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/simulation/smoke.bin new file mode 100644 index 0000000..fce167b Binary files /dev/null and b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/simulation/smoke.bin differ diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/simulation/smoke.disasm b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/simulation/smoke.disasm new file mode 100644 index 0000000..7d04ad8 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/simulation/smoke.disasm @@ -0,0 +1,538 @@ + +/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/smoke.elf: file format elf64-littleriscv + + +Disassembly of section .text: + +0000000080000000 <_start>: + 80000000: 00002137 lui sp,0x2 + 80000004: 0011011b addiw sp,sp,1 # 2001 <_start-0x7fffdfff> + 80000008: 01211113 slli sp,sp,0x12 + 8000000c: ff010113 addi sp,sp,-16 + 80000010: 00000297 auipc t0,0x0 + 80000014: 04c28293 addi t0,t0,76 # 8000005c + 80000018: 30529073 csrw mtvec,t0 + 8000001c: 30401073 csrw mie,zero + 80000020: 30201073 csrw medeleg,zero + 80000024: 0001e2b7 lui t0,0x1e + 80000028: 3002a073 csrs mstatus,t0 + 8000002c: 00000097 auipc ra,0x0 + 80000030: 050080e7 jalr 80(ra) # 8000007c
+ 80000034: 600002b7 lui t0,0x60000 + 80000038: 600d6337 lui t1,0x600d6 + 8000003c: 00d3031b addiw t1,t1,13 # 600d600d <_start-0x1ff29ff3> + 80000040: 00050a63 beqz a0,80000054 + 80000044: 00001337 lui t1,0x1 + 80000048: bad3031b addiw t1,t1,-1107 # bad <_start-0x7ffff453> + 8000004c: 01431313 slli t1,t1,0x14 + 80000050: 00a36333 or t1,t1,a0 + +0000000080000054 : + 80000054: 0062b023 sd t1,0(t0) # 60000000 <_start-0x20000000> + 80000058: 0000006f j 80000058 + +000000008000005c : + 8000005c: 342023f3 csrr t2,mcause + 80000060: 600002b7 lui t0,0x60000 + 80000064: 000bb337 lui t1,0xbb + 80000068: d0f3031b addiw t1,t1,-753 # bad0f <_start-0x7ff452f1> + 8000006c: 00c31313 slli t1,t1,0xc + 80000070: 00736333 or t1,t1,t2 + 80000074: 0062b023 sd t1,0(t0) # 60000000 <_start-0x20000000> + 80000078: 0000006f j 80000078 + +000000008000007c
: + 8000007c: 1101 addi sp,sp,-32 + 8000007e: e822 sd s0,16(sp) + 80000080: 00000f17 auipc t5,0x0 + 80000084: 6c0f0f13 addi t5,t5,1728 # 80000740 + 80000088: 1000 addi s0,sp,32 + 8000008a: ec06 sd ra,24(sp) + 8000008c: 87fa mv a5,t5 + 8000008e: 4681 li a3,0 + 80000090: 4805 li a6,1 + 80000092: 4889 li a7,2 + 80000094: 4e8d li t4,3 + 80000096: fe840e13 addi t3,s0,-24 + 8000009a: 60000313 li t1,1536 + 8000009e: 02c7e603 lwu a2,44(a5) + 800000a2: fe043423 sd zero,-24(s0) + 800000a6: 00261073 fsrm a2 + 800000aa: 5390 lw a2,32(a5) + 800000ac: 3e061b63 bnez a2,800004a2 + 800000b0: 53d0 lw a2,36(a5) + 800000b2: 34061763 bnez a2,80000400 + 800000b6: 578c lw a1,40(a5) + 800000b8: e19d bnez a1,800000de + 800000ba: 00101073 fsflags zero + 800000be: 00079007 flh ft0,0(a5) + 800000c2: 00879087 flh ft1,8(a5) + 800000c6: 01079107 flh ft2,16(a5) + 800000ca: 141071c3 fmadd.h ft3,ft0,ft1,ft2 + 800000ce: 003e1027 fsh ft3,0(t3) + 800000d2: 00102773 frflags a4 + 800000d6: 53d0 lw a2,36(a5) + 800000d8: 32061463 bnez a2,80000400 + 800000dc: 578c lw a1,40(a5) + 800000de: 37058d63 beq a1,a6,80000458 + 800000e2: 39158e63 beq a1,a7,8000047e + 800000e6: 4601 li a2,0 + 800000e8: 2fd58d63 beq a1,t4,800003e2 + 800000ec: 29160863 beq a2,a7,8000037c + 800000f0: fe843583 ld a1,-24(s0) + 800000f4: 6f88 ld a0,24(a5) + 800000f6: 0307e603 lwu a2,48(a5) + 800000fa: 2ab51963 bne a0,a1,800003ac + 800000fe: 2ac71763 bne a4,a2,800003ac + 80000102: 0685 addi a3,a3,1 + 80000104: 03878793 addi a5,a5,56 + 80000108: f8669be3 bne a3,t1,8000009e + 8000010c: 6791 lui a5,0x4 + 8000010e: c0078793 addi a5,a5,-1024 # 3c00 <_start-0x7fffc400> + 80000112: fef43023 sd a5,-32(s0) + 80000116: fe043423 sd zero,-24(s0) + 8000011a: fe040793 addi a5,s0,-32 + 8000011e: fe840693 addi a3,s0,-24 + 80000122: 00079007 flh ft0,0(a5) + 80000126: 00079087 flh ft1,0(a5) + 8000012a: 02000293 li t0,32 + 8000012e: c00025f3 rdcycle a1 + 80000132: 04100053 fadd.h ft0,ft0,ft1,rne + 80000136: 04100053 fadd.h ft0,ft0,ft1,rne + 8000013a: 04100053 fadd.h ft0,ft0,ft1,rne + 8000013e: 04100053 fadd.h ft0,ft0,ft1,rne + 80000142: 04100053 fadd.h ft0,ft0,ft1,rne + 80000146: 04100053 fadd.h ft0,ft0,ft1,rne + 8000014a: 04100053 fadd.h ft0,ft0,ft1,rne + 8000014e: 04100053 fadd.h ft0,ft0,ft1,rne + 80000152: 04100053 fadd.h ft0,ft0,ft1,rne + 80000156: 04100053 fadd.h ft0,ft0,ft1,rne + 8000015a: 04100053 fadd.h ft0,ft0,ft1,rne + 8000015e: 04100053 fadd.h ft0,ft0,ft1,rne + 80000162: 04100053 fadd.h ft0,ft0,ft1,rne + 80000166: 04100053 fadd.h ft0,ft0,ft1,rne + 8000016a: 04100053 fadd.h ft0,ft0,ft1,rne + 8000016e: 04100053 fadd.h ft0,ft0,ft1,rne + 80000172: 04100053 fadd.h ft0,ft0,ft1,rne + 80000176: 04100053 fadd.h ft0,ft0,ft1,rne + 8000017a: 04100053 fadd.h ft0,ft0,ft1,rne + 8000017e: 04100053 fadd.h ft0,ft0,ft1,rne + 80000182: 04100053 fadd.h ft0,ft0,ft1,rne + 80000186: 04100053 fadd.h ft0,ft0,ft1,rne + 8000018a: 04100053 fadd.h ft0,ft0,ft1,rne + 8000018e: 04100053 fadd.h ft0,ft0,ft1,rne + 80000192: 04100053 fadd.h ft0,ft0,ft1,rne + 80000196: 04100053 fadd.h ft0,ft0,ft1,rne + 8000019a: 04100053 fadd.h ft0,ft0,ft1,rne + 8000019e: 04100053 fadd.h ft0,ft0,ft1,rne + 800001a2: 04100053 fadd.h ft0,ft0,ft1,rne + 800001a6: 04100053 fadd.h ft0,ft0,ft1,rne + 800001aa: 04100053 fadd.h ft0,ft0,ft1,rne + 800001ae: 04100053 fadd.h ft0,ft0,ft1,rne + 800001b2: 12fd addi t0,t0,-1 + 800001b4: f6029fe3 bnez t0,80000132 + 800001b8: 00069027 fsh ft0,0(a3) + 800001bc: c0002773 rdcycle a4 + 800001c0: fe843603 ld a2,-24(s0) + 800001c4: 6699 lui a3,0x6 + 800001c6: 40168693 addi a3,a3,1025 # 6401 <_start-0x7fff9bff> + 800001ca: 56d61663 bne a2,a3,80000736 + 800001ce: 07300693 li a3,115 + 800001d2: 8f0d sub a4,a4,a1 + 800001d4: 16e2 slli a3,a3,0x38 + 800001d6: 8f55 or a4,a4,a3 + 800001d8: 60000637 lui a2,0x60000 + 800001dc: e218 sd a4,0(a2) + 800001de: 3f800737 lui a4,0x3f800 + 800001e2: fee43023 sd a4,-32(s0) + 800001e6: fe043423 sd zero,-24(s0) + 800001ea: fe840693 addi a3,s0,-24 + 800001ee: 0007a007 flw ft0,0(a5) + 800001f2: 0007a087 flw ft1,0(a5) + 800001f6: 02000293 li t0,32 + 800001fa: c0002573 rdcycle a0 + 800001fe: 00100053 fadd.s ft0,ft0,ft1,rne + 80000202: 00100053 fadd.s ft0,ft0,ft1,rne + 80000206: 00100053 fadd.s ft0,ft0,ft1,rne + 8000020a: 00100053 fadd.s ft0,ft0,ft1,rne + 8000020e: 00100053 fadd.s ft0,ft0,ft1,rne + 80000212: 00100053 fadd.s ft0,ft0,ft1,rne + 80000216: 00100053 fadd.s ft0,ft0,ft1,rne + 8000021a: 00100053 fadd.s ft0,ft0,ft1,rne + 8000021e: 00100053 fadd.s ft0,ft0,ft1,rne + 80000222: 00100053 fadd.s ft0,ft0,ft1,rne + 80000226: 00100053 fadd.s ft0,ft0,ft1,rne + 8000022a: 00100053 fadd.s ft0,ft0,ft1,rne + 8000022e: 00100053 fadd.s ft0,ft0,ft1,rne + 80000232: 00100053 fadd.s ft0,ft0,ft1,rne + 80000236: 00100053 fadd.s ft0,ft0,ft1,rne + 8000023a: 00100053 fadd.s ft0,ft0,ft1,rne + 8000023e: 00100053 fadd.s ft0,ft0,ft1,rne + 80000242: 00100053 fadd.s ft0,ft0,ft1,rne + 80000246: 00100053 fadd.s ft0,ft0,ft1,rne + 8000024a: 00100053 fadd.s ft0,ft0,ft1,rne + 8000024e: 00100053 fadd.s ft0,ft0,ft1,rne + 80000252: 00100053 fadd.s ft0,ft0,ft1,rne + 80000256: 00100053 fadd.s ft0,ft0,ft1,rne + 8000025a: 00100053 fadd.s ft0,ft0,ft1,rne + 8000025e: 00100053 fadd.s ft0,ft0,ft1,rne + 80000262: 00100053 fadd.s ft0,ft0,ft1,rne + 80000266: 00100053 fadd.s ft0,ft0,ft1,rne + 8000026a: 00100053 fadd.s ft0,ft0,ft1,rne + 8000026e: 00100053 fadd.s ft0,ft0,ft1,rne + 80000272: 00100053 fadd.s ft0,ft0,ft1,rne + 80000276: 00100053 fadd.s ft0,ft0,ft1,rne + 8000027a: 00100053 fadd.s ft0,ft0,ft1,rne + 8000027e: 12fd addi t0,t0,-1 + 80000280: f6029fe3 bnez t0,800001fe + 80000284: 0006a027 fsw ft0,0(a3) + 80000288: c0002773 rdcycle a4 + 8000028c: fe843583 ld a1,-24(s0) + 80000290: 448026b7 lui a3,0x44802 + 80000294: 4ad59163 bne a1,a3,80000736 + 80000298: 730006b7 lui a3,0x73000 + 8000029c: 0685 addi a3,a3,1 # 73000001 <_start-0xcffffff> + 8000029e: 8f09 sub a4,a4,a0 + 800002a0: 1682 slli a3,a3,0x20 + 800002a2: 8f55 or a4,a4,a3 + 800002a4: e218 sd a4,0(a2) + 800002a6: 3ff00713 li a4,1023 + 800002aa: 1752 slli a4,a4,0x34 + 800002ac: fee43023 sd a4,-32(s0) + 800002b0: fe043423 sd zero,-24(s0) + 800002b4: fe840693 addi a3,s0,-24 + 800002b8: 0007b007 fld ft0,0(a5) + 800002bc: 0007b087 fld ft1,0(a5) + 800002c0: 02000293 li t0,32 + 800002c4: c00025f3 rdcycle a1 + 800002c8: 02100053 fadd.d ft0,ft0,ft1,rne + 800002cc: 02100053 fadd.d ft0,ft0,ft1,rne + 800002d0: 02100053 fadd.d ft0,ft0,ft1,rne + 800002d4: 02100053 fadd.d ft0,ft0,ft1,rne + 800002d8: 02100053 fadd.d ft0,ft0,ft1,rne + 800002dc: 02100053 fadd.d ft0,ft0,ft1,rne + 800002e0: 02100053 fadd.d ft0,ft0,ft1,rne + 800002e4: 02100053 fadd.d ft0,ft0,ft1,rne + 800002e8: 02100053 fadd.d ft0,ft0,ft1,rne + 800002ec: 02100053 fadd.d ft0,ft0,ft1,rne + 800002f0: 02100053 fadd.d ft0,ft0,ft1,rne + 800002f4: 02100053 fadd.d ft0,ft0,ft1,rne + 800002f8: 02100053 fadd.d ft0,ft0,ft1,rne + 800002fc: 02100053 fadd.d ft0,ft0,ft1,rne + 80000300: 02100053 fadd.d ft0,ft0,ft1,rne + 80000304: 02100053 fadd.d ft0,ft0,ft1,rne + 80000308: 02100053 fadd.d ft0,ft0,ft1,rne + 8000030c: 02100053 fadd.d ft0,ft0,ft1,rne + 80000310: 02100053 fadd.d ft0,ft0,ft1,rne + 80000314: 02100053 fadd.d ft0,ft0,ft1,rne + 80000318: 02100053 fadd.d ft0,ft0,ft1,rne + 8000031c: 02100053 fadd.d ft0,ft0,ft1,rne + 80000320: 02100053 fadd.d ft0,ft0,ft1,rne + 80000324: 02100053 fadd.d ft0,ft0,ft1,rne + 80000328: 02100053 fadd.d ft0,ft0,ft1,rne + 8000032c: 02100053 fadd.d ft0,ft0,ft1,rne + 80000330: 02100053 fadd.d ft0,ft0,ft1,rne + 80000334: 02100053 fadd.d ft0,ft0,ft1,rne + 80000338: 02100053 fadd.d ft0,ft0,ft1,rne + 8000033c: 02100053 fadd.d ft0,ft0,ft1,rne + 80000340: 02100053 fadd.d ft0,ft0,ft1,rne + 80000344: 02100053 fadd.d ft0,ft0,ft1,rne + 80000348: 12fd addi t0,t0,-1 + 8000034a: f6029fe3 bnez t0,800002c8 + 8000034e: 0006b027 fsd ft0,0(a3) + 80000352: c0002773 rdcycle a4 + 80000356: 001027b7 lui a5,0x102 + 8000035a: fe843683 ld a3,-24(s0) + 8000035e: 40178793 addi a5,a5,1025 # 102401 <_start-0x7fefdbff> + 80000362: 17aa slli a5,a5,0x2a + 80000364: 3cf69963 bne a3,a5,80000736 + 80000368: 40b707b3 sub a5,a4,a1 + 8000036c: 39800737 lui a4,0x39800 + 80000370: 0705 addi a4,a4,1 # 39800001 <_start-0x467fffff> + 80000372: 1706 slli a4,a4,0x21 + 80000374: 8fd9 or a5,a5,a4 + 80000376: e21c sd a5,0(a2) + 80000378: 4501 li a0,0 + 8000037a: a085 j 800003da + 8000037c: 5790 lw a2,40(a5) + 8000037e: d60619e3 bnez a2,800000f0 + 80000382: 00101073 fsflags zero + 80000386: 00079007 flh ft0,0(a5) + 8000038a: 00879087 flh ft1,8(a5) + 8000038e: 01079107 flh ft2,16(a5) + 80000392: 141071d3 fmul.h ft3,ft0,ft1 + 80000396: 003e1027 fsh ft3,0(t3) + 8000039a: 00102773 frflags a4 + 8000039e: fe843583 ld a1,-24(s0) + 800003a2: 6f88 ld a0,24(a5) + 800003a4: 0307e603 lwu a2,48(a5) + 800003a8: d4b50be3 beq a0,a1,800000fe + 800003ac: 02069813 slli a6,a3,0x20 + 800003b0: 02085813 srli a6,a6,0x20 + 800003b4: 00381793 slli a5,a6,0x3 + 800003b8: 410787b3 sub a5,a5,a6 + 800003bc: 078e slli a5,a5,0x3 + 800003be: 9f3e add t5,t5,a5 + 800003c0: 60000537 lui a0,0x60000 + 800003c4: 018f3803 ld a6,24(t5) + 800003c8: e914 sd a3,16(a0) + 800003ca: ed0c sd a1,24(a0) + 800003cc: 03053023 sd a6,32(a0) # 60000020 <_start-0x1fffffe0> + 800003d0: f518 sd a4,40(a0) + 800003d2: 01850693 addi a3,a0,24 + 800003d6: f910 sd a2,48(a0) + 800003d8: 457d li a0,31 + 800003da: 60e2 ld ra,24(sp) + 800003dc: 6442 ld s0,16(sp) + 800003de: 6105 addi sp,sp,32 + 800003e0: 8082 ret + 800003e2: 00101073 fsflags zero + 800003e6: 00079007 flh ft0,0(a5) + 800003ea: 00879087 flh ft1,8(a5) + 800003ee: 01079107 flh ft2,16(a5) + 800003f2: 141071cf fnmadd.h ft3,ft0,ft1,ft2 + 800003f6: 003e1027 fsh ft3,0(t3) + 800003fa: 00102773 frflags a4 + 800003fe: 53d0 lw a2,36(a5) + 80000400: cf0616e3 bne a2,a6,800000ec + 80000404: 5790 lw a2,40(a5) + 80000406: e21d bnez a2,8000042c + 80000408: 00101073 fsflags zero + 8000040c: 00079007 flh ft0,0(a5) + 80000410: 00879087 flh ft1,8(a5) + 80000414: 01079107 flh ft2,16(a5) + 80000418: 042071d3 fadd.h ft3,ft0,ft2 + 8000041c: 003e1027 fsh ft3,0(t3) + 80000420: 00102773 frflags a4 + 80000424: 53d0 lw a2,36(a5) + 80000426: cd0613e3 bne a2,a6,800000ec + 8000042a: 5790 lw a2,40(a5) + 8000042c: cd0612e3 bne a2,a6,800000f0 + 80000430: fe840713 addi a4,s0,-24 + 80000434: 00101073 fsflags zero + 80000438: 00079007 flh ft0,0(a5) + 8000043c: 00879087 flh ft1,8(a5) + 80000440: 01079107 flh ft2,16(a5) + 80000444: 0c2071d3 fsub.h ft3,ft0,ft2 + 80000448: 00371027 fsh ft3,0(a4) + 8000044c: 00102773 frflags a4 + 80000450: 53d0 lw a2,36(a5) + 80000452: c9161fe3 bne a2,a7,800000f0 + 80000456: b71d j 8000037c + 80000458: 00101073 fsflags zero + 8000045c: 00079007 flh ft0,0(a5) + 80000460: 00879087 flh ft1,8(a5) + 80000464: 01079107 flh ft2,16(a5) + 80000468: 141071c7 fmsub.h ft3,ft0,ft1,ft2 + 8000046c: 003e1027 fsh ft3,0(t3) + 80000470: 00102773 frflags a4 + 80000474: 53d0 lw a2,36(a5) + 80000476: f649 bnez a2,80000400 + 80000478: 578c lw a1,40(a5) + 8000047a: c71596e3 bne a1,a7,800000e6 + 8000047e: 00101073 fsflags zero + 80000482: 00079007 flh ft0,0(a5) + 80000486: 00879087 flh ft1,8(a5) + 8000048a: 01079107 flh ft2,16(a5) + 8000048e: 141071cb fnmsub.h ft3,ft0,ft1,ft2 + 80000492: 003e1027 fsh ft3,0(t3) + 80000496: 00102773 frflags a4 + 8000049a: 53d0 lw a2,36(a5) + 8000049c: f235 bnez a2,80000400 + 8000049e: 578c lw a1,40(a5) + 800004a0: b199 j 800000e6 + 800004a2: 07060f63 beq a2,a6,80000520 + 800004a6: 4581 li a1,0 + 800004a8: c51616e3 bne a2,a7,800000f4 + 800004ac: 53cc lw a1,36(a5) + 800004ae: 852e mv a0,a1 + 800004b0: 16059e63 bnez a1,8000062c + 800004b4: 5790 lw a2,40(a5) + 800004b6: e615 bnez a2,800004e2 + 800004b8: fe840713 addi a4,s0,-24 + 800004bc: 00101073 fsflags zero + 800004c0: 0007b007 fld ft0,0(a5) + 800004c4: 0087b087 fld ft1,8(a5) + 800004c8: 0107b107 fld ft2,16(a5) + 800004cc: 121071c3 fmadd.d ft3,ft0,ft1,ft2 + 800004d0: 00373027 fsd ft3,0(a4) + 800004d4: 00102773 frflags a4 + 800004d8: 53cc lw a1,36(a5) + 800004da: 852e mv a0,a1 + 800004dc: 14059863 bnez a1,8000062c + 800004e0: 5790 lw a2,40(a5) + 800004e2: 4505 li a0,1 + 800004e4: 22a60363 beq a2,a0,8000070a + 800004e8: 4509 li a0,2 + 800004ea: 1ea60b63 beq a2,a0,800006e0 + 800004ee: 450d li a0,3 + 800004f0: 10a60c63 beq a2,a0,80000608 + 800004f4: bf159ee3 bne a1,a7,800000f0 + 800004f8: 5790 lw a2,40(a5) + 800004fa: be061be3 bnez a2,800000f0 + 800004fe: fe840713 addi a4,s0,-24 + 80000502: 00101073 fsflags zero + 80000506: 0007b007 fld ft0,0(a5) + 8000050a: 0087b087 fld ft1,8(a5) + 8000050e: 0107b107 fld ft2,16(a5) + 80000512: 121071d3 fmul.d ft3,ft0,ft1 + 80000516: 00373027 fsd ft3,0(a4) + 8000051a: 00102773 frflags a4 + 8000051e: bec9 j 800000f0 + 80000520: 53cc lw a1,36(a5) + 80000522: e5d1 bnez a1,800005ae + 80000524: 5790 lw a2,40(a5) + 80000526: e605 bnez a2,8000054e + 80000528: fe840713 addi a4,s0,-24 + 8000052c: 00101073 fsflags zero + 80000530: 0007a007 flw ft0,0(a5) + 80000534: 0087a087 flw ft1,8(a5) + 80000538: 0107a107 flw ft2,16(a5) + 8000053c: 101071c3 fmadd.s ft3,ft0,ft1,ft2 + 80000540: 00372027 fsw ft3,0(a4) + 80000544: 00102773 frflags a4 + 80000548: 53cc lw a1,36(a5) + 8000054a: e1b5 bnez a1,800005ae + 8000054c: 5790 lw a2,40(a5) + 8000054e: 13060f63 beq a2,a6,8000068c + 80000552: 17160263 beq a2,a7,800006b6 + 80000556: 4581 li a1,0 + 80000558: 03d60a63 beq a2,t4,8000058c + 8000055c: b9159ae3 bne a1,a7,800000f0 + 80000560: 5790 lw a2,40(a5) + 80000562: b80617e3 bnez a2,800000f0 + 80000566: fe840713 addi a4,s0,-24 + 8000056a: 00101073 fsflags zero + 8000056e: 0007a007 flw ft0,0(a5) + 80000572: 0087a087 flw ft1,8(a5) + 80000576: 0107a107 flw ft2,16(a5) + 8000057a: 101071d3 fmul.s ft3,ft0,ft1 + 8000057e: 00372027 fsw ft3,0(a4) + 80000582: 00102773 frflags a4 + 80000586: fe843583 ld a1,-24(s0) + 8000058a: b6ad j 800000f4 + 8000058c: fe840713 addi a4,s0,-24 + 80000590: 00101073 fsflags zero + 80000594: 0007a007 flw ft0,0(a5) + 80000598: 0087a087 flw ft1,8(a5) + 8000059c: 0107a107 flw ft2,16(a5) + 800005a0: 101071cf fnmadd.s ft3,ft0,ft1,ft2 + 800005a4: 00372027 fsw ft3,0(a4) + 800005a8: 00102773 frflags a4 + 800005ac: 53cc lw a1,36(a5) + 800005ae: fb0597e3 bne a1,a6,8000055c + 800005b2: 5790 lw a2,40(a5) + 800005b4: e60d bnez a2,800005de + 800005b6: fe840713 addi a4,s0,-24 + 800005ba: 00101073 fsflags zero + 800005be: 0007a007 flw ft0,0(a5) + 800005c2: 0087a087 flw ft1,8(a5) + 800005c6: 0107a107 flw ft2,16(a5) + 800005ca: 002071d3 fadd.s ft3,ft0,ft2 + 800005ce: 00372027 fsw ft3,0(a4) + 800005d2: 00102773 frflags a4 + 800005d6: 53cc lw a1,36(a5) + 800005d8: f90592e3 bne a1,a6,8000055c + 800005dc: 5790 lw a2,40(a5) + 800005de: 4585 li a1,1 + 800005e0: b0b618e3 bne a2,a1,800000f0 + 800005e4: fe840713 addi a4,s0,-24 + 800005e8: 00101073 fsflags zero + 800005ec: 0007a007 flw ft0,0(a5) + 800005f0: 0087a087 flw ft1,8(a5) + 800005f4: 0107a107 flw ft2,16(a5) + 800005f8: 082071d3 fsub.s ft3,ft0,ft2 + 800005fc: 00372027 fsw ft3,0(a4) + 80000600: 00102773 frflags a4 + 80000604: 53cc lw a1,36(a5) + 80000606: bf99 j 8000055c + 80000608: fe840713 addi a4,s0,-24 + 8000060c: 00101073 fsflags zero + 80000610: 0007b007 fld ft0,0(a5) + 80000614: 0087b087 fld ft1,8(a5) + 80000618: 0107b107 fld ft2,16(a5) + 8000061c: 121071cf fnmadd.d ft3,ft0,ft1,ft2 + 80000620: 00373027 fsd ft3,0(a4) + 80000624: 00102773 frflags a4 + 80000628: 53cc lw a1,36(a5) + 8000062a: 852e mv a0,a1 + 8000062c: 4605 li a2,1 + 8000062e: ecc593e3 bne a1,a2,800004f4 + 80000632: 5790 lw a2,40(a5) + 80000634: e60d bnez a2,8000065e + 80000636: fe840713 addi a4,s0,-24 + 8000063a: 00101073 fsflags zero + 8000063e: 0007b007 fld ft0,0(a5) + 80000642: 0087b087 fld ft1,8(a5) + 80000646: 0107b107 fld ft2,16(a5) + 8000064a: 022071d3 fadd.d ft3,ft0,ft2 + 8000064e: 00373027 fsd ft3,0(a4) + 80000652: 00102773 frflags a4 + 80000656: 53cc lw a1,36(a5) + 80000658: e8a59ee3 bne a1,a0,800004f4 + 8000065c: 5790 lw a2,40(a5) + 8000065e: 4585 li a1,1 + 80000660: a8b618e3 bne a2,a1,800000f0 + 80000664: fe840713 addi a4,s0,-24 + 80000668: 00101073 fsflags zero + 8000066c: 0007b007 fld ft0,0(a5) + 80000670: 0087b087 fld ft1,8(a5) + 80000674: 0107b107 fld ft2,16(a5) + 80000678: 0a2071d3 fsub.d ft3,ft0,ft2 + 8000067c: 00373027 fsd ft3,0(a4) + 80000680: 00102773 frflags a4 + 80000684: 53cc lw a1,36(a5) + 80000686: a71595e3 bne a1,a7,800000f0 + 8000068a: b5bd j 800004f8 + 8000068c: fe840713 addi a4,s0,-24 + 80000690: 00101073 fsflags zero + 80000694: 0007a007 flw ft0,0(a5) + 80000698: 0087a087 flw ft1,8(a5) + 8000069c: 0107a107 flw ft2,16(a5) + 800006a0: 101071c7 fmsub.s ft3,ft0,ft1,ft2 + 800006a4: 00372027 fsw ft3,0(a4) + 800006a8: 00102773 frflags a4 + 800006ac: 53cc lw a1,36(a5) + 800006ae: f181 bnez a1,800005ae + 800006b0: 5790 lw a2,40(a5) + 800006b2: eb1612e3 bne a2,a7,80000556 + 800006b6: fe840713 addi a4,s0,-24 + 800006ba: 00101073 fsflags zero + 800006be: 0007a007 flw ft0,0(a5) + 800006c2: 0087a087 flw ft1,8(a5) + 800006c6: 0107a107 flw ft2,16(a5) + 800006ca: 101071cb fnmsub.s ft3,ft0,ft1,ft2 + 800006ce: 00372027 fsw ft3,0(a4) + 800006d2: 00102773 frflags a4 + 800006d6: 53cc lw a1,36(a5) + 800006d8: ec059be3 bnez a1,800005ae + 800006dc: 5790 lw a2,40(a5) + 800006de: bda5 j 80000556 + 800006e0: fe840713 addi a4,s0,-24 + 800006e4: 00101073 fsflags zero + 800006e8: 0007b007 fld ft0,0(a5) + 800006ec: 0087b087 fld ft1,8(a5) + 800006f0: 0107b107 fld ft2,16(a5) + 800006f4: 121071cb fnmsub.d ft3,ft0,ft1,ft2 + 800006f8: 00373027 fsd ft3,0(a4) + 800006fc: 00102773 frflags a4 + 80000700: 53cc lw a1,36(a5) + 80000702: 852e mv a0,a1 + 80000704: f585 bnez a1,8000062c + 80000706: 5790 lw a2,40(a5) + 80000708: b3dd j 800004ee + 8000070a: fe840713 addi a4,s0,-24 + 8000070e: 00101073 fsflags zero + 80000712: 0007b007 fld ft0,0(a5) + 80000716: 0087b087 fld ft1,8(a5) + 8000071a: 0107b107 fld ft2,16(a5) + 8000071e: 121071c7 fmsub.d ft3,ft0,ft1,ft2 + 80000722: 00373027 fsd ft3,0(a4) + 80000726: 00102773 frflags a4 + 8000072a: 53cc lw a1,36(a5) + 8000072c: 852e mv a0,a1 + 8000072e: ee059fe3 bnez a1,8000062c + 80000732: 5790 lw a2,40(a5) + 80000734: bb55 j 800004e8 + 80000736: 02000513 li a0,32 + 8000073a: b145 j 800003da diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/simulation/smoke.elf b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/simulation/smoke.elf new file mode 100644 index 0000000..060d443 Binary files /dev/null and b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/simulation/smoke.elf differ diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/simulation/smoke.hex b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/simulation/smoke.hex new file mode 100644 index 0000000..b6b2e9e --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/simulation/smoke.hex @@ -0,0 +1,87872 @@ +37 +21 +00 +00 +1b +01 +11 +00 +13 +11 +21 +01 +13 +01 +01 +ff +97 +02 +00 +00 +93 +82 +c2 +04 +73 +90 +52 +30 +73 +10 +40 +30 +73 +10 +20 +30 +b7 +e2 +01 +00 +73 +a0 +02 +30 +97 +00 +00 +00 +e7 +80 +00 +05 +b7 +02 +00 +60 +37 +63 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[3:0] memory_aw_bits_cache; + wire [2:0] memory_aw_bits_prot; + wire [3:0] memory_aw_bits_qos; + wire memory_w_ready; + wire memory_w_valid; + wire [127:0] memory_w_bits_data; + wire [15:0] memory_w_bits_strb; + wire memory_w_bits_last; + wire memory_b_ready; + wire memory_b_valid; + wire [3:0] memory_b_bits_id; + wire [1:0] memory_b_bits_resp; + wire memory_ar_ready; + wire memory_ar_valid; + wire [3:0] memory_ar_bits_id; + wire [31:0] memory_ar_bits_addr; + wire [7:0] memory_ar_bits_len; + wire [2:0] memory_ar_bits_size; + wire [1:0] memory_ar_bits_burst; + wire memory_ar_bits_lock; + wire [3:0] memory_ar_bits_cache; + wire [2:0] memory_ar_bits_prot; + wire [3:0] memory_ar_bits_qos; + wire memory_r_ready; + wire memory_r_valid; + wire [3:0] memory_r_bits_id; + wire [127:0] memory_r_bits_data; + wire [1:0] memory_r_bits_resp; + wire memory_r_bits_last; + wire peripherals_aw_ready; + wire peripherals_aw_valid; + wire [1:0] peripherals_aw_bits_id; + wire [30:0] peripherals_aw_bits_addr; + wire [7:0] peripherals_aw_bits_len; + wire [2:0] peripherals_aw_bits_size; + wire [1:0] peripherals_aw_bits_burst; + wire peripherals_aw_bits_lock; + wire [3:0] peripherals_aw_bits_cache; + wire [2:0] peripherals_aw_bits_prot; + wire [3:0] peripherals_aw_bits_qos; + wire peripherals_w_ready; + wire peripherals_w_valid; + wire [63:0] peripherals_w_bits_data; + wire [7:0] peripherals_w_bits_strb; + wire peripherals_w_bits_last; + wire peripherals_b_ready; + wire peripherals_b_valid; + wire [1:0] peripherals_b_bits_id; + wire [1:0] peripherals_b_bits_resp; + wire peripherals_ar_ready; + wire peripherals_ar_valid; + wire [1:0] peripherals_ar_bits_id; + wire [30:0] peripherals_ar_bits_addr; + wire [7:0] peripherals_ar_bits_len; + wire [2:0] peripherals_ar_bits_size; + wire [1:0] peripherals_ar_bits_burst; + wire peripherals_ar_bits_lock; + wire [3:0] peripherals_ar_bits_cache; + wire [2:0] peripherals_ar_bits_prot; + wire [3:0] peripherals_ar_bits_qos; + wire peripherals_r_ready; + wire peripherals_r_valid; + wire [1:0] peripherals_r_bits_id; + wire [63:0] peripherals_r_bits_data; + wire [1:0] peripherals_r_bits_resp; + wire peripherals_r_bits_last; + ToyLinuxChip dut(.*); + integer cycle_count=0; + always @(posedge clock) if (!reset) cycle_count<=cycle_count+1; + always #5 clock=~clock; + initial begin reset=1; repeat(20) @(negedge clock); reset=0; end + initial begin repeat(5000000) @(posedge clock); $fatal(1,"CPU timeout"); end + axi_smoke_memory #(.DATA_BITS(128), .ID_BITS(4), .ADDR_BITS(32), .BASE(32'h80000000), .CAPACITY(262144), .IMAGE("smoke.hex")) memory_model ( + .clock(clock), + .reset(reset), + .aw_ready(memory_aw_ready), + .aw_valid(memory_aw_valid), + .aw_bits_id(memory_aw_bits_id), + .aw_bits_addr(memory_aw_bits_addr), + .aw_bits_len(memory_aw_bits_len), + .aw_bits_size(memory_aw_bits_size), + .aw_bits_burst(memory_aw_bits_burst), + .w_ready(memory_w_ready), + .w_valid(memory_w_valid), + .w_bits_data(memory_w_bits_data), + .w_bits_strb(memory_w_bits_strb), + .w_bits_last(memory_w_bits_last), + .b_ready(memory_b_ready), + .b_valid(memory_b_valid), + .b_bits_id(memory_b_bits_id), + .b_bits_resp(memory_b_bits_resp), + .ar_ready(memory_ar_ready), + .ar_valid(memory_ar_valid), + .ar_bits_id(memory_ar_bits_id), + .ar_bits_addr(memory_ar_bits_addr), + .ar_bits_len(memory_ar_bits_len), + .ar_bits_size(memory_ar_bits_size), + .ar_bits_burst(memory_ar_bits_burst), + .r_ready(memory_r_ready), + .r_valid(memory_r_valid), + .r_bits_id(memory_r_bits_id), + .r_bits_data(memory_r_bits_data), + .r_bits_resp(memory_r_bits_resp), + .r_bits_last(memory_r_bits_last) + ); + axi_smoke_memory #(.DATA_BITS(64), .ID_BITS(2), .ADDR_BITS(31), .BASE(32'h60000000), .CAPACITY(4096), .MONITOR(1), .TEST_LABEL("whole Toy shared FPU 1536 oracle vectors")) peripherals_model ( + .clock(clock), + .reset(reset), + .aw_ready(peripherals_aw_ready), + .aw_valid(peripherals_aw_valid), + .aw_bits_id(peripherals_aw_bits_id), + .aw_bits_addr(peripherals_aw_bits_addr), + .aw_bits_len(peripherals_aw_bits_len), + .aw_bits_size(peripherals_aw_bits_size), + .aw_bits_burst(peripherals_aw_bits_burst), + .w_ready(peripherals_w_ready), + .w_valid(peripherals_w_valid), + .w_bits_data(peripherals_w_bits_data), + .w_bits_strb(peripherals_w_bits_strb), + .w_bits_last(peripherals_w_bits_last), + .b_ready(peripherals_b_ready), + .b_valid(peripherals_b_valid), + .b_bits_id(peripherals_b_bits_id), + .b_bits_resp(peripherals_b_bits_resp), + .ar_ready(peripherals_ar_ready), + .ar_valid(peripherals_ar_valid), + .ar_bits_id(peripherals_ar_bits_id), + .ar_bits_addr(peripherals_ar_bits_addr), + .ar_bits_len(peripherals_ar_bits_len), + .ar_bits_size(peripherals_ar_bits_size), + .ar_bits_burst(peripherals_ar_bits_burst), + .r_ready(peripherals_r_ready), + .r_valid(peripherals_r_valid), + .r_bits_id(peripherals_r_bits_id), + .r_bits_data(peripherals_r_bits_data), + .r_bits_resp(peripherals_r_bits_resp), + .r_bits_last(peripherals_r_bits_last) + ); + final $display("MEASURE cycles=%0d memory_reads=%0d memory_writes=%0d", cycle_count, memory_model.read_bursts, memory_model.write_bursts); +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/simulation/verilator-build.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/simulation/verilator-build.log new file mode 100644 index 0000000..7c19681 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/fpu-shared/simulation/verilator-build.log @@ -0,0 +1,2123 @@ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 31 | module NonSyncResetSynchronizerPrimitiveShiftReg_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ + ... For warning description see https://verilator.org/warn/TIMESCALEMOD?v=5.050 + ... Use "/* verilator lint_off TIMESCALEMOD */" and lint_on around source to disable this message. +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:48:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 48 | module SynchronizerShiftReg_w1_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:61:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 61 | module IntSyncAsyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:74:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 74 | module AsyncResetRegVec_w1_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 103 | module IntSyncCrossingSource_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:118:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 118 | module FixedClockBroadcast_3( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:139:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 139 | module TLMonitor( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:987:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 987 | module TLMonitor_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:2434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 2434 | module TLXbar_sbus_i2_o3_a32d128s3k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:3195:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3195 | module TLMonitor_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4151 | module Repeater_TLBundleA_a28d128s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4218 | module TLWidthWidget16( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4386 | module TLInterconnectCoupler_sbus_to_bus_named_cbus( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4478:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4478 | module ram_2x58( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4497:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4497 | module Queue2_AXI4BundleAW( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4581:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4581 | module ram_2x73( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4600:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4600 | module Queue2_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4657:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4657 | module ram_2x4( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4676:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4676 | module Queue2_AXI4BundleB( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4729:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4729 | module Queue2_AXI4BundleAR( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4813:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4813 | module ram_2x69( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4832:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4832 | module Queue2_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4891:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4891 | module AXI4Buffer( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5067:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5067 | module ram_2x8( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5086:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5086 | module Queue2_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5143:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5143 | module Queue1_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5178 | module AXI4UserYanker( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5540:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5540 | module ram_8x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5559:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5559 | module Queue8_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5631 | module AXI4Deinterleaver( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:6073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6073 | module AXI4IdIndexer( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:6219:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6219 | module TLMonitor_3( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7048:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7048 | module Queue1_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7082:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7082 | module Queue1_AXI4BundleARW( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7148:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7148 | module TLToAXI4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7529:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7529 | module TLMonitor_4( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8396:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8396 | module Repeater_TLBundleA_a31d128s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8463 | module TLWidthWidget16_2( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8623:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8623 | module TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:9400:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 9400 | module SystemBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10050 | module FixedClockBroadcast_4( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10073 | module TLMonitor_5( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10975:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10975 | module TLXbar_cbus_out_i1_o4_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:11288:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +11288 | module TLMonitor_6( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12202:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12202 | module ram_2x114( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12221 | module Queue2_TLBundleA_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12301 | module ram_2x79( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12320:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12320 | module Queue2_TLBundleD_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12399:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12399 | module TLBuffer_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12534:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12534 | module TLMonitor_7( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:13449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13449 | module TLAtomicAutomata_cbus( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:13973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13973 | module TLMonitor_8( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14799 | module Queue1_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14846:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14846 | module TLError( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14953 | module TLMonitor_9( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15857 | module ram_2x100( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15876:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15876 | module Queue2_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15955:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15955 | module Queue2_TLBundleD_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16028 | module TLBuffer_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16155 | module ErrorDeviceWrapper( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16258 | module TLMonitor_10( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17017:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17017 | module Repeater_TLBundleA_a26d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17081:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17081 | module TLFragmenter_CLINT( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17261:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17261 | module TLInterconnectCoupler_cbus_to_clint( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17336:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17336 | module TLMonitor_11( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18106:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18106 | module Repeater_TLBundleA_a28d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18170:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18170 | module TLFragmenter_PLIC( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18350 | module TLInterconnectCoupler_cbus_to_plic( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18425:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18425 | module TLMonitor_12( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19040 | module Repeater_TLBundleA_a17d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19104:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19104 | module TLFragmenter_bootrom( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19263:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19263 | module TLInterconnectCoupler_cbus_to_bootrom( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19330:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19330 | module PeripheryBus_cbus( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19882 | module TLMonitor_13( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20610:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20610 | module ProbePicker( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20688:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20688 | module ram_2x10( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20707:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20707 | module Queue2_BundleMap_6( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20764:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20764 | module AXI4UserYanker_1( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:21713:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21713 | module AXI4IdIndexer_1( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:21859:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21859 | module TLMonitor_14( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22587:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22587 | module Queue1_AXI4BundleW_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22621 | module Queue1_AXI4BundleARW_1( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22687:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22687 | module TLToAXI4_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:23555:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +23555 | module TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:24031:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24031 | module MemoryBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:24349:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24349 | module TLMonitor_15( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25732:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25732 | module BroadcastFilter( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25756:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25756 | module ram_4x144( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25775:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25775 | module Queue4_TLBroadcastData( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25828:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25828 | module TLBroadcastTracker( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25964:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25964 | module TLBroadcastTracker_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:26100:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26100 | module TLBroadcast( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:26686:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26686 | module TLMonitor_16( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27414 | module BankBinder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27491:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27491 | module CoherenceManagerWrapper( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27669:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27669 | module TLMonitor_17( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29229:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29229 | module TLMonitor_18( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29635:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29635 | module TLXbar_MasterXbar_BBTile_i2_o1_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29898 | module IntXbar_i4_o1( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29918:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29918 | module WritebackUnit( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30014:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30014 | module ProbeUnit( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30154:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30154 | module Arbiter1_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30168:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30168 | module Arbiter1_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30191 | module Arbiter1_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30214 | module Arbiter1_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30249:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30249 | module Arbiter1_Bool( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30258 | module ram_16x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30277:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30277 | module Queue16_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30360:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30360 | module Queue1_TLBundleE_a32d128s1k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30388:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30388 | module MSHR( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30835:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30835 | module Arbiter1_HellaCacheResp( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30879:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30879 | module IOMSHR( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31790:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31790 | module sdq_17x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31809 | module MSHRFile( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32350 | module OptimizationBarrier_TLBEntryData( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32406:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32406 | module PMPChecker_s3( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32691:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32691 | module PMAChecker( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32731:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32731 | module DTLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:35923:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35923 | module L1MetadataArray( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:35990:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35990 | module Arbiter5_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36023:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36023 | module Arbiter2_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36055 | module DataArray( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36151 | module Arbiter4_L1DataReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36180:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36180 | module Arbiter2_L1DataWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36206:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36206 | module AMOALU( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36248:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36248 | module MaxPeriodFibonacciLFSR( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36342:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36342 | module Arbiter2_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36377:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36377 | module NonBlockingDCache( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:37660:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37660 | module ICache( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:37914:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37914 | module ShiftQueue( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:38054:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38054 | module PMPChecker_s2( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:38215:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38215 | module ITLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:41129:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41129 | module Frontend( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:41494:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41494 | module TLMonitor_19( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:42301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +42301 | module TLMonitor_20( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43108:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43108 | module TLXbar_i2_o1_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43343 | module TLMonitor_21( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43851:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43851 | module ram_2x116( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43870:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43870 | module Queue2_TLBundleA_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43947:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43947 | module ram_2x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43966:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43966 | module Queue2_TLBundleD_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44045:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44045 | module TLBuffer_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44158:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44158 | module TLMonitor_22( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44783 | module TLBuffer_a32d64s1k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44892:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44892 | module TLMonitor_23( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:45699:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45699 | module Repeater_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:45766:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45766 | module TLWidthWidget8_4( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46074:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46074 | module TLMonitor_24( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46882 | module ram_2x117( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46901:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46901 | module Queue2_TLBundleA_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46981:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46981 | module ram_2x78( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47000:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47000 | module Queue2_TLBundleD_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47079:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47079 | module TLBuffer_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47214 | module HellaCacheArbiter( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47381 | module Arbiter3_Valid_PTWReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47419:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47419 | module OptimizationBarrier_UInt( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47427 | module OptimizationBarrier_PTE( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47459 | module PTW( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:48434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +48434 | module FPUDecoder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49794:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49794 | module CompareRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49824:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49824 | module RecFNToIN_e11_s53_i64( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49873:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49873 | module RecFNToIN_e11_s53_i32( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49912:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49912 | module FPToInt( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50375:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50375 | module RoundAnyRawFNToRecFN_ie7_is64_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50410:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50410 | module PipelinedINToRecFN( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50513:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50513 | module RoundAnyRawFNToRecFN_ie7_is64_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50539 | module PipelinedINToRecFN_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50614 | module RoundAnyRawFNToRecFN_ie7_is64_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50642:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50642 | module PipelinedINToRecFN_2( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50717 | module IntToFP( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51072:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51072 | module RoundAnyRawFNToRecFN_ie11_is53_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51199:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51199 | module RecFNToRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51221 | module RoundAnyRawFNToRecFN_ie11_is53_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51321:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51321 | module RecFNToRecFN_1( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51343 | module FPToFP( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51469:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51469 | module MulAddRecFNToRaw_preMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51569 | module MulAddRecFNToRaw_postMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51822:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51822 | module RoundAnyRawFNToRecFN_ie11_is55_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51953 | module RoundAnyRawFNToRecFN_ie11_is55_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52060:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52060 | module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52194:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52194 | module SharedMulAddRecFNPipe( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52551:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52551 | module FPUSharedFMAPipe( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52682:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52682 | module DivSqrtRawFN_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52852:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52852 | module DivSqrtRecFMToRaw_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52907:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52907 | module RoundAnyRawFNToRecFN_ie5_is13_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53039:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53039 | module RoundRawFNToRecFN_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53068:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53068 | module DivSqrtRecFM_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53128:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53128 | module DivSqrtRawFN_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53297:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53297 | module DivSqrtRecFMToRaw_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53352:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53352 | module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53456:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53456 | module RoundRawFNToRecFN_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53485:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53485 | module DivSqrtRecFM_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53545:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53545 | module DivSqrtRawFN_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53715:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53715 | module DivSqrtRecFMToRaw_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53770:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53770 | module RoundRawFNToRecFN_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53799 | module DivSqrtRecFM_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53860:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53860 | module regfile_32x65( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53905:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53905 | module FPU( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:54820:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +54820 | module RVCExpander( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:55183:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55183 | module IBuf( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:55307:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55307 | module CSRFile( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:57223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57223 | module RocketALU( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:57809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57809 | module MulDiv( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:58107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58107 | module Arbiter3_LLWB( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:58125:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58125 | module rf_31x64( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:58149:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58149 | module RocketBB( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62838:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62838 | module GlobalDecoder( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62928:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62928 | module BankAliasTable( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:64252:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64252 | module BankScoreboard( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:64627:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64627 | module GlobalROB( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68674:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68674 | module Arbiter3_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68717 | module ram_16x4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68736:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68736 | module Queue16_UInt4( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68782:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68782 | module SubROB( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:69357:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69357 | module Arbiter1_SubRobRow( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:69722:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69722 | module GlobalScheduler( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:70973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +70973 | module BootRom( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:71013:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71013 | module Frontend_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:71637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71637 | module PE( + | ^~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:71656:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71656 | module AlwaysOutTransposer( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72411:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72411 | module MacUnit( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72426:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72426 | module PE_64( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72524:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72524 | module Tile( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72571:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72571 | module Mesh( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76050 | module TagQueue( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76191 | module ram_6x7( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76210:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76210 | module Queue6_TagWithIdAndTotalRows( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76271:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76271 | module MeshWithDelays( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77318:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77318 | module ram_data_8x64( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77337 | module Queue8_SramReadResp( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77385:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77385 | module GemminiExCtrl( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79354:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79354 | module LoopMatmulUnroller( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79637 | module LoopConvAddrGen( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79690:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79690 | module LoopConvUnroller( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:80113:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80113 | module LoopCmdEncoder( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:80402:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80402 | module Arbiter2_LoopCmd( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:80598:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80598 | module GemminiBall( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:81783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81783 | module RRArbiter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:81857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81857 | module CmdRouter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:81985:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81985 | module BallCyclePMC( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:82095:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82095 | module BBus( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:82898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82898 | module BallDomainDecoder( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83028 | module ram_4x281( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83047:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83047 | module Queue4_BallReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83178 | module Arbiter1_BallRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83198:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83198 | module BallReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83328:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83328 | module BallDomain( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84141:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84141 | module MemDomainDecoder( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84300:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84300 | module ram_4x158( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84319:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84319 | module Queue4_MemReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84421:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84421 | module Arbiter3_MemRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84463 | module MemReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84631 | module MemLoader( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84869:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84869 | module MemStorer( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85122:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85122 | module MemCyclePMC( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85241:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85241 | module TLB( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85621 | module RRArbiter_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85649:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85649 | module BBTLBCluster( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85777 | module StreamReader( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86142:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86142 | module StreamWriter( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86223 | module ZeroLineGenerator( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86264:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86264 | module MemConfiger( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86433:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86433 | module RRArbiter_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86465:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86465 | module MemGroupQueryArbiter( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86543:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86543 | module MemFrontend( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87160 | module MemMidend( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87621 | module SramBank( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87672:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87672 | module AccPipe( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87781 | module PrivateMemBackend( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:90777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +90777 | module MemBackend( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:91055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91055 | module MemDomain( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:91973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91973 | module Queue1_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92008:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92008 | module GpDomain( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92040 | module ram_8x21( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92059 | module Queue8_BuckyballAccelerator_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92123:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92123 | module BuckyballAccelerator( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93569 | module Queue3_UInt2( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93614 | module SimpleHellaCacheIFReplayQueue( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93667:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93667 | module Arbiter2_HellaCacheReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93678:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93678 | module SimpleHellaCacheIF( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93768:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93768 | module BarrierUnit( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93785:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93785 | module BBTile( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:95579:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +95579 | module TLMonitor_25( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:96427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +96427 | module TLMonitor_26( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98184:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98184 | module ram_2x189( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98203:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98203 | module Queue2_TLBundleA_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98283:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98283 | module ram_2x142( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98302:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98302 | module Queue2_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98381 | module Queue2_TLBundleA_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98459 | module Queue2_TLBundleD_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98539 | module ram_2x60( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98558:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98558 | module Queue2_TLBundleB_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98622:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98622 | module ram_2x173( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98641:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98641 | module Queue2_TLBundleC_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98716:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98716 | module ram_sink_2x1( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98735:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98735 | module Queue2_TLBundleE_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98781 | module TLBuffer_a32d128s2k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99162:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99162 | module IntSyncSyncCrossingSink_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99173:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99173 | module IntSyncSyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99181:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99181 | module TilePRCIDomain( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99589:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99589 | module BundleBridgeNexus_UInt1_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99597:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99597 | module TLMonitor_27( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100216:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100216 | module CLINT( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100337 | module AsyncResetRegVec_w2_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100366:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100366 | module IntSyncCrossingSource_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100386 | module CLINTClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100449 | module TLMonitor_28( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101080:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101080 | module LevelGateway( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101099:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101099 | module PLICFanIn( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101111:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101111 | module Queue1_RegMapperInput_i23_m8( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101160 | module TLPLIC( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101389:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101389 | module PLICClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101452:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101452 | module TLMonitor_29( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101973 | module TLROM( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:102530:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102530 | module bootromClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:102569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102569 | module ToyLinuxSystem( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103817:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103817 | module ToyLinuxChip( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103984:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103984 | module tag_array( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104007:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104007 | module array_0_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104034:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104034 | module array_0_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104059 | module array_2_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104084:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104084 | module array_2_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104109:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104109 | module bbtile_icache_tag_array( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104132:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104132 | module bbtile_icache_data_arrays_0( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104155 | module bbtile_icache_data_arrays_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104176:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104176 | module bbtile_icache_data_arrays_2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104197:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104197 | module bbtile_icache_data_arrays_3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104218 | module robOperands( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104243:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104243 | module sram( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104268:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104268 | module mem( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104301 | module plusarg_reader #( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104326:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104326 | module ITraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104404:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104404 | module FpgaDspMac(input [7:0] a, b, input [19:0] c, output [19:0] y); + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104414 | module PMCTraceDPI( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104464:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104464 | module MemPMCTraceDPI( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104514:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104514 | module MTraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:1:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 1 | module tag_array_ext( input [4:0] RW0_addr, + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 19 | module array_0_0_ext( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:37:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 37 | module bbtile_icache_tag_array_ext( input [5:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:55:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 55 | module bbtile_icache_data_arrays_0_ext( input [7:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:73:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 73 | module robOperands_ext( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:90:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 90 | module sram_ext( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 107 | module mem_ext( input [9:0] RW0_addr, + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:3:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3 | module axi_smoke_memory #( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:52:20: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'addr' generates 31 bits. + : ... note: In instance 'tb.peripherals_model' + 52 | offset=(addr & ~(LANES-1))-BASE; + | ^ + ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=5.050 + ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:78:28: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'write_addr' generates 31 bits. + : ... note: In instance 'tb.peripherals_model' + 78 | offset=(write_addr & ~(LANES-1))-BASE; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:86:26: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'h600d600d' generates 64 bits. + : ... note: In instance 'tb.memory_model' + 86 | if (w_bits_data==64'h600d600d) begin + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:91:66: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff' generates 64 bits. + : ... note: In instance 'tb.memory_model' + 91 | $fatal(1,"CPU smoke failed at stage %0d",w_bits_data & 64'hffff); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:90:28: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff0000' generates 64 bits. + : ... note: In instance 'tb.memory_model' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:90:43: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'hbad00000' generates 64 bits. + : ... note: In instance 'tb.memory_model' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^~ +make: Entering directory '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/obj' +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_timing.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_timing.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_threads.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_threads.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb__pch.h -o Vtb__pch.h.fast.gch +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb__pch.h -o Vtb__pch.h.slow.gch +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__0.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__1.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__2.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__3.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__4.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__5.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__6.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__7.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__8.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__9.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb__main.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb__ConstPool__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__1__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__2__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__3__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb__Syms__Slow.cpp +g++ verilated.o verilated_timing.o verilated_threads.o Vtb__ALL.a -pthread -lpthread -latomic -o Vtb +rm Vtb__ALL.verilator_deplist.tmp +make: Leaving directory '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/fpu-shared/simulation/obj' +- V e r i l a t i o n R e p o r t: Verilator 5.050 2026-07-01 rev v5.050 +- Verilator: Built from 15.468 MB sources in 346 modules, into 23.746 MB in 19 C++ files needing 0.019 MB +- Verilator: Walltime 14.593 s (elab=0.600, cvt=3.664, bld=9.657); cpu 5.229 s on 8 threads; allocated 433.781 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/gemmini-tests/simulation/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/gemmini-tests/simulation/RESULT.json new file mode 100644 index 0000000..58b8021 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/gemmini-tests/simulation/RESULT.json @@ -0,0 +1,10 @@ +{ + "result": "PASS", + "test_label": "whole Toy Gemmini regression", + "core_rtl_sha256": "31e7e07f94d08208dbb564edf9546240df26ff834935bfb646b71b541d875fb9", + "test_binary_sha256": "d6307d194aadb9f23e14edf695ce98ab1ea361881237576b15c251573af2826e", + "cycles_including_boot": 245517, + "memory_read_bursts": 674, + "memory_write_bursts": 444, + "linux_boot_tested": false +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/gemmini-tests/simulation/simulation.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/gemmini-tests/simulation/simulation.log new file mode 100644 index 0000000..2938e44 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/gemmini-tests/simulation/simulation.log @@ -0,0 +1,33 @@ +CPU status = 0000000071000001 +CPU status = 0000000072000001 +CPU status = 0000000071000002 +CPU status = 0000000072000002 +CPU status = 0000000071000003 +CPU status = 0000000072000003 +CPU status = 0000000071000004 +CPU status = 0000000072000004 +CPU status = 0000000071000005 +CPU status = 0000000072000005 +CPU status = 0000000071000006 +CPU status = 0000000072000006 +CPU status = 0000000071000007 +CPU status = 0000000072000007 +CPU status = 0000000071000008 +CPU status = 0000000072000008 +CPU status = 0000000071000009 +CPU status = 0000000072000009 +CPU status = 000000007100000a +CPU status = 000000007200000a +CPU status = 000000007100000b +CPU status = 000000007200000b +CPU status = 000000007100000c +CPU status = 000000007200000c +CPU status = 000000007100000d +CPU status = 000000007200000d +CPU status = 00000000600d600d +PASS whole Toy Gemmini regression +- /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:88: Verilog $finish +MEASURE cycles=245517 memory_reads=674 memory_writes=444 +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 2ms; walltime 2.089 s; speed 1.175 ms/s +- Verilator: cpu 2.089 s on 1 threads; allocated 8 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/gemmini-tests/simulation/smoke.bin b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/gemmini-tests/simulation/smoke.bin new file mode 100644 index 0000000..cf62a30 Binary files /dev/null and b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/gemmini-tests/simulation/smoke.bin differ diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/gemmini-tests/simulation/smoke.disasm b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/gemmini-tests/simulation/smoke.disasm new file mode 100644 index 0000000..502da9a --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/gemmini-tests/simulation/smoke.disasm @@ -0,0 +1,2735 @@ + +/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/smoke.elf: file format elf64-littleriscv + + +Disassembly of section .text: + +0000000080000000 <_start>: + 80000000: 00002137 lui sp,0x2 + 80000004: 0011011b addiw sp,sp,1 # 2001 <_start-0x7fffdfff> + 80000008: 01211113 slli sp,sp,0x12 + 8000000c: ff010113 addi sp,sp,-16 + 80000010: 00000297 auipc t0,0x0 + 80000014: 04c28293 addi t0,t0,76 # 8000005c + 80000018: 30529073 csrw mtvec,t0 + 8000001c: 30401073 csrw mie,zero + 80000020: 30201073 csrw medeleg,zero + 80000024: 0001e2b7 lui t0,0x1e + 80000028: 3002a073 csrs mstatus,t0 + 8000002c: 00000097 auipc ra,0x0 + 80000030: 050080e7 jalr 80(ra) # 8000007c
+ 80000034: 600002b7 lui t0,0x60000 + 80000038: 600d6337 lui t1,0x600d6 + 8000003c: 00d3031b addiw t1,t1,13 # 600d600d <_start-0x1ff29ff3> + 80000040: 00050a63 beqz a0,80000054 + 80000044: 00001337 lui t1,0x1 + 80000048: bad3031b addiw t1,t1,-1107 # bad <_start-0x7ffff453> + 8000004c: 01431313 slli t1,t1,0x14 + 80000050: 00a36333 or t1,t1,a0 + +0000000080000054 : + 80000054: 0062b023 sd t1,0(t0) # 60000000 <_start-0x20000000> + 80000058: 0000006f j 80000058 + +000000008000005c : + 8000005c: 342023f3 csrr t2,mcause + 80000060: 600002b7 lui t0,0x60000 + 80000064: 000bb337 lui t1,0xbb + 80000068: d0f3031b addiw t1,t1,-753 # bad0f <_start-0x7ff452f1> + 8000006c: 00c31313 slli t1,t1,0xc + 80000070: 00736333 or t1,t1,t2 + 80000074: 0062b023 sd t1,0(t0) # 60000000 <_start-0x20000000> + 80000078: 0000006f j 80000078 + +000000008000007c
: + 8000007c: 1101 addi sp,sp,-32 + 8000007e: e822 sd s0,16(sp) + 80000080: e426 sd s1,8(sp) + 80000082: ec06 sd ra,24(sp) + 80000084: 1000 addi s0,sp,32 + 80000086: 710007b7 lui a5,0x71000 + 8000008a: 0785 addi a5,a5,1 # 71000001 <_start-0xeffffff> + 8000008c: 600004b7 lui s1,0x60000 + 80000090: e09c sd a5,0(s1) + 80000092: 00000097 auipc ra,0x0 + 80000096: 3ec080e7 jalr 1004(ra) # 8000047e + 8000009a: 87aa mv a5,a0 + 8000009c: 4505 li a0,1 + 8000009e: c791 beqz a5,800000aa + 800000a0: 60e2 ld ra,24(sp) + 800000a2: 6442 ld s0,16(sp) + 800000a4: 64a2 ld s1,8(sp) + 800000a6: 6105 addi sp,sp,32 + 800000a8: 8082 ret + 800000aa: 72000737 lui a4,0x72000 + 800000ae: 972a add a4,a4,a0 + 800000b0: 710007b7 lui a5,0x71000 + 800000b4: e098 sd a4,0(s1) + 800000b6: 0789 addi a5,a5,2 # 71000002 <_start-0xefffffe> + 800000b8: e09c sd a5,0(s1) + 800000ba: 00000097 auipc ra,0x0 + 800000be: 582080e7 jalr 1410(ra) # 8000063c + 800000c2: 12051963 bnez a0,800001f4 + 800000c6: 72000737 lui a4,0x72000 + 800000ca: 0709 addi a4,a4,2 # 72000002 <_start-0xdfffffe> + 800000cc: 710007b7 lui a5,0x71000 + 800000d0: e098 sd a4,0(s1) + 800000d2: 078d addi a5,a5,3 # 71000003 <_start-0xefffffd> + 800000d4: e09c sd a5,0(s1) + 800000d6: 00000097 auipc ra,0x0 + 800000da: 704080e7 jalr 1796(ra) # 800007da + 800000de: 10051d63 bnez a0,800001f8 + 800000e2: 72000737 lui a4,0x72000 + 800000e6: 070d addi a4,a4,3 # 72000003 <_start-0xdfffffd> + 800000e8: 710007b7 lui a5,0x71000 + 800000ec: e098 sd a4,0(s1) + 800000ee: 0791 addi a5,a5,4 # 71000004 <_start-0xefffffc> + 800000f0: e09c sd a5,0(s1) + 800000f2: 00001097 auipc ra,0x1 + 800000f6: 8a6080e7 jalr -1882(ra) # 80000998 + 800000fa: e97d bnez a0,800001f0 + 800000fc: 72000737 lui a4,0x72000 + 80000100: 0711 addi a4,a4,4 # 72000004 <_start-0xdfffffc> + 80000102: 710007b7 lui a5,0x71000 + 80000106: e098 sd a4,0(s1) + 80000108: 0795 addi a5,a5,5 # 71000005 <_start-0xefffffb> + 8000010a: e09c sd a5,0(s1) + 8000010c: 00001097 auipc ra,0x1 + 80000110: a64080e7 jalr -1436(ra) # 80000b70 + 80000114: e575 bnez a0,80000200 + 80000116: 72000737 lui a4,0x72000 + 8000011a: 0715 addi a4,a4,5 # 72000005 <_start-0xdfffffb> + 8000011c: 710007b7 lui a5,0x71000 + 80000120: e098 sd a4,0(s1) + 80000122: 0799 addi a5,a5,6 # 71000006 <_start-0xefffffa> + 80000124: e09c sd a5,0(s1) + 80000126: 00001097 auipc ra,0x1 + 8000012a: ca2080e7 jalr -862(ra) # 80000dc8 + 8000012e: e979 bnez a0,80000204 + 80000130: 72000737 lui a4,0x72000 + 80000134: 0719 addi a4,a4,6 # 72000006 <_start-0xdfffffa> + 80000136: 710007b7 lui a5,0x71000 + 8000013a: e098 sd a4,0(s1) + 8000013c: 079d addi a5,a5,7 # 71000007 <_start-0xefffff9> + 8000013e: e09c sd a5,0(s1) + 80000140: 00001097 auipc ra,0x1 + 80000144: ec4080e7 jalr -316(ra) # 80001004 + 80000148: e955 bnez a0,800001fc + 8000014a: 72000737 lui a4,0x72000 + 8000014e: 071d addi a4,a4,7 # 72000007 <_start-0xdfffff9> + 80000150: 710007b7 lui a5,0x71000 + 80000154: e098 sd a4,0(s1) + 80000156: 07a1 addi a5,a5,8 # 71000008 <_start-0xefffff8> + 80000158: e09c sd a5,0(s1) + 8000015a: 00001097 auipc ra,0x1 + 8000015e: 18e080e7 jalr 398(ra) # 800012e8 + 80000162: e15d bnez a0,80000208 + 80000164: 72000737 lui a4,0x72000 + 80000168: 0721 addi a4,a4,8 # 72000008 <_start-0xdfffff8> + 8000016a: 710007b7 lui a5,0x71000 + 8000016e: e098 sd a4,0(s1) + 80000170: 07a5 addi a5,a5,9 # 71000009 <_start-0xefffff7> + 80000172: e09c sd a5,0(s1) + 80000174: 00001097 auipc ra,0x1 + 80000178: 3b0080e7 jalr 944(ra) # 80001524 + 8000017c: e941 bnez a0,8000020c + 8000017e: 72000737 lui a4,0x72000 + 80000182: 0725 addi a4,a4,9 # 72000009 <_start-0xdfffff7> + 80000184: 710007b7 lui a5,0x71000 + 80000188: e098 sd a4,0(s1) + 8000018a: 07a9 addi a5,a5,10 # 7100000a <_start-0xefffff6> + 8000018c: e09c sd a5,0(s1) + 8000018e: 00001097 auipc ra,0x1 + 80000192: 5e0080e7 jalr 1504(ra) # 8000176e + 80000196: ed2d bnez a0,80000210 + 80000198: 72000737 lui a4,0x72000 + 8000019c: 0729 addi a4,a4,10 # 7200000a <_start-0xdfffff6> + 8000019e: 710007b7 lui a5,0x71000 + 800001a2: e098 sd a4,0(s1) + 800001a4: 07ad addi a5,a5,11 # 7100000b <_start-0xefffff5> + 800001a6: e09c sd a5,0(s1) + 800001a8: 00001097 auipc ra,0x1 + 800001ac: 764080e7 jalr 1892(ra) # 8000190c + 800001b0: e135 bnez a0,80000214 + 800001b2: 72000737 lui a4,0x72000 + 800001b6: 072d addi a4,a4,11 # 7200000b <_start-0xdfffff5> + 800001b8: 710007b7 lui a5,0x71000 + 800001bc: e098 sd a4,0(s1) + 800001be: 07b1 addi a5,a5,12 # 7100000c <_start-0xefffff4> + 800001c0: e09c sd a5,0(s1) + 800001c2: 00002097 auipc ra,0x2 + 800001c6: 9b0080e7 jalr -1616(ra) # 80001b72 + 800001ca: e539 bnez a0,80000218 + 800001cc: 72000737 lui a4,0x72000 + 800001d0: 0731 addi a4,a4,12 # 7200000c <_start-0xdfffff4> + 800001d2: 710007b7 lui a5,0x71000 + 800001d6: e098 sd a4,0(s1) + 800001d8: 07b5 addi a5,a5,13 # 7100000d <_start-0xefffff3> + 800001da: e09c sd a5,0(s1) + 800001dc: 00002097 auipc ra,0x2 + 800001e0: c2a080e7 jalr -982(ra) # 80001e06 + 800001e4: ed05 bnez a0,8000021c + 800001e6: 720007b7 lui a5,0x72000 + 800001ea: 07b5 addi a5,a5,13 # 7200000d <_start-0xdfffff3> + 800001ec: e09c sd a5,0(s1) + 800001ee: bd4d j 800000a0 + 800001f0: 4511 li a0,4 + 800001f2: b57d j 800000a0 + 800001f4: 4509 li a0,2 + 800001f6: b56d j 800000a0 + 800001f8: 450d li a0,3 + 800001fa: b55d j 800000a0 + 800001fc: 451d li a0,7 + 800001fe: b54d j 800000a0 + 80000200: 4515 li a0,5 + 80000202: bd79 j 800000a0 + 80000204: 4519 li a0,6 + 80000206: bd69 j 800000a0 + 80000208: 4521 li a0,8 + 8000020a: bd59 j 800000a0 + 8000020c: 4525 li a0,9 + 8000020e: bd49 j 800000a0 + 80000210: 4529 li a0,10 + 80000212: b579 j 800000a0 + 80000214: 452d li a0,11 + 80000216: b569 j 800000a0 + 80000218: 4531 li a0,12 + 8000021a: b559 j 800000a0 + 8000021c: 4535 li a0,13 + 8000021e: b549 j 800000a0 + +0000000080000220 : + 80000220: 1141 addi sp,sp,-16 + 80000222: e022 sd s0,0(sp) + 80000224: e406 sd ra,8(sp) + 80000226: 0800 addi s0,sp,16 + 80000228: 47bd li a5,15 + 8000022a: 00a7fa63 bgeu a5,a0,8000023e + 8000022e: 00002717 auipc a4,0x2 + 80000232: e7a73703 ld a4,-390(a4) # 800020a8 + 80000236: 600007b7 lui a5,0x60000 + 8000023a: e398 sd a4,0(a5) + 8000023c: a001 j 8000023c + 8000023e: 02051793 slli a5,a0,0x20 + 80000242: 60a2 ld ra,8(sp) + 80000244: 6402 ld s0,0(sp) + 80000246: 01e7d513 srli a0,a5,0x1e + 8000024a: 00002797 auipc a5,0x2 + 8000024e: 57678793 addi a5,a5,1398 # 800027c0 + 80000252: 97aa add a5,a5,a0 + 80000254: c38c sw a1,0(a5) + 80000256: 0141 addi sp,sp,16 + 80000258: 8082 ret + +000000008000025a : + 8000025a: 715d addi sp,sp,-80 + 8000025c: e022 sd s0,0(sp) + 8000025e: e406 sd ra,8(sp) + 80000260: 0800 addi s0,sp,16 + 80000262: e40c sd a1,8(s0) + 80000264: 60a2 ld ra,8(sp) + 80000266: e810 sd a2,16(s0) + 80000268: ec14 sd a3,24(s0) + 8000026a: f018 sd a4,32(s0) + 8000026c: f41c sd a5,40(s0) + 8000026e: 03043823 sd a6,48(s0) + 80000272: 03143c23 sd a7,56(s0) + 80000276: 6402 ld s0,0(sp) + 80000278: 4501 li a0,0 + 8000027a: 6161 addi sp,sp,80 + 8000027c: 8082 ret + +000000008000027e : + 8000027e: 1141 addi sp,sp,-16 + 80000280: e022 sd s0,0(sp) + 80000282: e406 sd ra,8(sp) + 80000284: 0800 addi s0,sp,16 + 80000286: 00c50733 add a4,a0,a2 + 8000028a: c619 beqz a2,80000298 + 8000028c: 87aa mv a5,a0 + 8000028e: 00b78023 sb a1,0(a5) + 80000292: 0785 addi a5,a5,1 + 80000294: fee79de3 bne a5,a4,8000028e + 80000298: 60a2 ld ra,8(sp) + 8000029a: 6402 ld s0,0(sp) + 8000029c: 0141 addi sp,sp,16 + 8000029e: 8082 ret + +00000000800002a0 : + 800002a0: 02d6073b mulw a4,a2,a3 + 800002a4: 02e05f63 blez a4,800002e2 + 800002a8: 87ae mv a5,a1 + 800002aa: 4581 li a1,0 + 800002ac: a021 j 800002b4 + 800002ae: 2585 addiw a1,a1,1 + 800002b0: 02e58963 beq a1,a4,800002e2 + 800002b4: 4114 lw a3,0(a0) + 800002b6: 4390 lw a2,0(a5) + 800002b8: 0511 addi a0,a0,4 + 800002ba: 0791 addi a5,a5,4 + 800002bc: fec689e3 beq a3,a2,800002ae + 800002c0: 1141 addi sp,sp,-16 + 800002c2: e022 sd s0,0(sp) + 800002c4: e406 sd ra,8(sp) + 800002c6: 0800 addi s0,sp,16 + 800002c8: 00002517 auipc a0,0x2 + 800002cc: de850513 addi a0,a0,-536 # 800020b0 + 800002d0: 00000097 auipc ra,0x0 + 800002d4: f8a080e7 jalr -118(ra) # 8000025a + 800002d8: 60a2 ld ra,8(sp) + 800002da: 6402 ld s0,0(sp) + 800002dc: 4501 li a0,0 + 800002de: 0141 addi sp,sp,16 + 800002e0: 8082 ret + 800002e2: 4505 li a0,1 + 800002e4: 8082 ret + +00000000800002e6 : + 800002e6: 02c5863b mulw a2,a1,a2 + 800002ea: 1141 addi sp,sp,-16 + 800002ec: e022 sd s0,0(sp) + 800002ee: e406 sd ra,8(sp) + 800002f0: 0800 addi s0,sp,16 + 800002f2: 6402 ld s0,0(sp) + 800002f4: 60a2 ld ra,8(sp) + 800002f6: 4581 li a1,0 + 800002f8: 0141 addi sp,sp,16 + 800002fa: 00000317 auipc t1,0x0 + 800002fe: f8430067 jr -124(t1) # 8000027e + +0000000080000302 : + 80000302: 1141 addi sp,sp,-16 + 80000304: e022 sd s0,0(sp) + 80000306: e406 sd ra,8(sp) + 80000308: 0800 addi s0,sp,16 + 8000030a: 00c05b63 blez a2,80000320 + 8000030e: 4e01 li t3,0 + 80000310: 4301 li t1,0 + 80000312: 00d04b63 bgtz a3,80000328 + 80000316: 0305 addi t1,t1,1 + 80000318: 00de0e3b addw t3,t3,a3 + 8000031c: fec31be3 bne t1,a2,80000312 + 80000320: 60a2 ld ra,8(sp) + 80000322: 6402 ld s0,0(sp) + 80000324: 0141 addi sp,sp,16 + 80000326: 8082 ret + 80000328: 00d50eb3 add t4,a0,a3 + 8000032c: 01c507b3 add a5,a0,t3 + 80000330: 00658733 add a4,a1,t1 + 80000334: 01ce88b3 add a7,t4,t3 + 80000338: 00078803 lb a6,0(a5) + 8000033c: 0785 addi a5,a5,1 + 8000033e: 01070023 sb a6,0(a4) + 80000342: 9732 add a4,a4,a2 + 80000344: ff179ae3 bne a5,a7,80000338 + 80000348: 0305 addi t1,t1,1 + 8000034a: 00de0e3b addw t3,t3,a3 + 8000034e: fcc31fe3 bne t1,a2,8000032c + 80000352: 60a2 ld ra,8(sp) + 80000354: 6402 ld s0,0(sp) + 80000356: 0141 addi sp,sp,16 + 80000358: 8082 ret + +000000008000035a : + 8000035a: 1141 addi sp,sp,-16 + 8000035c: e022 sd s0,0(sp) + 8000035e: e406 sd ra,8(sp) + 80000360: 0800 addi s0,sp,16 + 80000362: 87aa mv a5,a0 + 80000364: 02b05e63 blez a1,800003a0 + 80000368: 477d li a4,31 + 8000036a: 4781 li a5,0 + 8000036c: 02b74a63 blt a4,a1,800003a0 + 80000370: fff5879b addiw a5,a1,-1 + 80000374: 4605 li a2,1 + 80000376: 00f556bb srlw a3,a0,a5 + 8000037a: 4701 li a4,0 + 8000037c: 00c58a63 beq a1,a2,80000390 + 80000380: 577d li a4,-1 + 80000382: 00f7173b sllw a4,a4,a5 + 80000386: fff74713 not a4,a4 + 8000038a: 8f69 and a4,a4,a0 + 8000038c: 00e03733 snez a4,a4 + 80000390: 00b557bb srlw a5,a0,a1 + 80000394: 8b85 andi a5,a5,1 + 80000396: 8fd9 or a5,a5,a4 + 80000398: 8ff5 and a5,a5,a3 + 8000039a: 40b5553b sraw a0,a0,a1 + 8000039e: 9fa9 addw a5,a5,a0 + 800003a0: 60a2 ld ra,8(sp) + 800003a2: 6402 ld s0,0(sp) + 800003a4: 853e mv a0,a5 + 800003a6: 0141 addi sp,sp,16 + 800003a8: 8082 ret + +00000000800003aa : + 800003aa: 02e6883b mulw a6,a3,a4 + 800003ae: 715d addi sp,sp,-80 + 800003b0: e0a2 sd s0,64(sp) + 800003b2: fc26 sd s1,56(sp) + 800003b4: 0880 addi s0,sp,80 + 800003b6: f84a sd s2,48(sp) + 800003b8: f44e sd s3,40(sp) + 800003ba: e486 sd ra,72(sp) + 800003bc: 84b2 mv s1,a2 + 800003be: 89aa mv s3,a0 + 800003c0: 892e mv s2,a1 + 800003c2: 8532 mv a0,a2 + 800003c4: 4581 li a1,0 + 800003c6: 00281613 slli a2,a6,0x2 + 800003ca: fcd43023 sd a3,-64(s0) + 800003ce: fae43c23 sd a4,-72(s0) + 800003d2: fcf43423 sd a5,-56(s0) + 800003d6: 00000097 auipc ra,0x0 + 800003da: ea8080e7 jalr -344(ra) # 8000027e + 800003de: fc043683 ld a3,-64(s0) + 800003e2: 02d05c63 blez a3,8000041a + 800003e6: fc843783 ld a5,-56(s0) + 800003ea: fb843703 ld a4,-72(s0) + 800003ee: f052 sd s4,32(sp) + 800003f0: 4f01 li t5,0 + 800003f2: 4281 li t0,0 + 800003f4: 4381 li t2,0 + 800003f6: 00f98a33 add s4,s3,a5 + 800003fa: 02e05763 blez a4,80000428 + 800003fe: 4e81 li t4,0 + 80000400: 02f04e63 bgtz a5,8000043c + 80000404: 0e85 addi t4,t4,1 + 80000406: feee9de3 bne t4,a4,80000400 + 8000040a: 2385 addiw t2,t2,1 + 8000040c: 00f282bb addw t0,t0,a5 + 80000410: 00ef0f3b addw t5,t5,a4 + 80000414: fe7695e3 bne a3,t2,800003fe + 80000418: 7a02 ld s4,32(sp) + 8000041a: 60a6 ld ra,72(sp) + 8000041c: 6406 ld s0,64(sp) + 8000041e: 74e2 ld s1,56(sp) + 80000420: 7942 ld s2,48(sp) + 80000422: 79a2 ld s3,40(sp) + 80000424: 6161 addi sp,sp,80 + 80000426: 8082 ret + 80000428: 2385 addiw t2,t2,1 + 8000042a: 00f282bb addw t0,t0,a5 + 8000042e: 00ef0f3b addw t5,t5,a4 + 80000432: fe7683e3 beq a3,t2,80000418 + 80000436: fce044e3 bgtz a4,800003fe + 8000043a: b7fd j 80000428 + 8000043c: 8376 mv t1,t4 + 8000043e: 00598fb3 add t6,s3,t0 + 80000442: 005a0e33 add t3,s4,t0 + 80000446: 01e3033b addw t1,t1,t5 + 8000044a: 030a slli t1,t1,0x2 + 8000044c: 9326 add t1,t1,s1 + 8000044e: 00032803 lw a6,0(t1) + 80000452: 867e mv a2,t6 + 80000454: 01d90533 add a0,s2,t4 + 80000458: 00060583 lb a1,0(a2) + 8000045c: 00050883 lb a7,0(a0) + 80000460: 0605 addi a2,a2,1 + 80000462: 953a add a0,a0,a4 + 80000464: 031585bb mulw a1,a1,a7 + 80000468: 0105883b addw a6,a1,a6 + 8000046c: 01032023 sw a6,0(t1) + 80000470: fece14e3 bne t3,a2,80000458 + 80000474: 0e85 addi t4,t4,1 + 80000476: fbd709e3 beq a4,t4,80000428 + 8000047a: 8376 mv t1,t4 + 8000047c: b7e9 j 80000446 + +000000008000047e : + 8000047e: 1101 addi sp,sp,-32 + 80000480: e822 sd s0,16(sp) + 80000482: e426 sd s1,8(sp) + 80000484: e04a sd s2,0(sp) + 80000486: ec06 sd ra,24(sp) + 80000488: 1000 addi s0,sp,32 + 8000048a: 00002517 auipc a0,0x2 + 8000048e: c5650513 addi a0,a0,-938 # 800020e0 + 80000492: 00000097 auipc ra,0x0 + 80000496: dc8080e7 jalr -568(ra) # 8000025a + 8000049a: 00002917 auipc s2,0x2 + 8000049e: 5e690913 addi s2,s2,1510 # 80002a80 + 800004a2: 00002497 auipc s1,0x2 + 800004a6: 55e48493 addi s1,s1,1374 # 80002a00 + 800004aa: 2e8ba337 lui t1,0x2e8ba + 800004ae: 4ec4f8b7 lui a7,0x4ec4f + 800004b2: 8f4a mv t5,s2 + 800004b4: 8ea6 mv t4,s1 + 800004b6: 2e930313 addi t1,t1,745 # 2e8ba2e9 <_start-0x51745d17> + 800004ba: c4f88893 addi a7,a7,-945 # 4ec4ec4f <_start-0x313b13b1> + 800004be: 02800813 li a6,40 + 800004c2: 4e01 li t3,0 + 800004c4: 04000f93 li t6,64 + 800004c8: fd88069b addiw a3,a6,-40 + 800004cc: 8576 mv a0,t4 + 800004ce: 8672 mv a2,t3 + 800004d0: 85fa mv a1,t5 + 800004d2: 026682b3 mul t0,a3,t1 + 800004d6: 02061713 slli a4,a2,0x20 + 800004da: 9301 srli a4,a4,0x20 + 800004dc: 41f6d79b sraiw a5,a3,0x1f + 800004e0: 0505 addi a0,a0,1 + 800004e2: 0585 addi a1,a1,1 + 800004e4: 03170733 mul a4,a4,a7 + 800004e8: 4212d293 srai t0,t0,0x21 + 800004ec: 40f282bb subw t0,t0,a5 + 800004f0: 0012979b slliw a5,t0,0x1 + 800004f4: 005787bb addw a5,a5,t0 + 800004f8: 0027979b slliw a5,a5,0x2 + 800004fc: 405787bb subw a5,a5,t0 + 80000500: 40f687bb subw a5,a3,a5 + 80000504: 37ed addiw a5,a5,-5 + 80000506: fef58fa3 sb a5,-1(a1) + 8000050a: 9309 srli a4,a4,0x22 + 8000050c: 0017179b slliw a5,a4,0x1 + 80000510: 9fb9 addw a5,a5,a4 + 80000512: 0027979b slliw a5,a5,0x2 + 80000516: 9fb9 addw a5,a5,a4 + 80000518: 40f607bb subw a5,a2,a5 + 8000051c: 37e9 addiw a5,a5,-6 + 8000051e: fef50fa3 sb a5,-1(a0) + 80000522: 2695 addiw a3,a3,5 + 80000524: 2609 addiw a2,a2,2 + 80000526: fb0696e3 bne a3,a6,800004d2 + 8000052a: 0036881b addiw a6,a3,3 + 8000052e: 0f21 addi t5,t5,8 + 80000530: 2e1d addiw t3,t3,7 + 80000532: 0ea1 addi t4,t4,8 + 80000534: f9f81ae3 bne a6,t6,800004c8 + 80000538: 46a1 li a3,8 + 8000053a: 8636 mv a2,a3 + 8000053c: 00002597 auipc a1,0x2 + 80000540: 50458593 addi a1,a1,1284 # 80002a40 + 80000544: 00002517 auipc a0,0x2 + 80000548: 53c50513 addi a0,a0,1340 # 80002a80 + 8000054c: 00000097 auipc ra,0x0 + 80000550: db6080e7 jalr -586(ra) # 80000302 + 80000554: 47a1 li a5,8 + 80000556: 873e mv a4,a5 + 80000558: 86be mv a3,a5 + 8000055a: 00002617 auipc a2,0x2 + 8000055e: 2a660613 addi a2,a2,678 # 80002800 + 80000562: 00002597 auipc a1,0x2 + 80000566: 49e58593 addi a1,a1,1182 # 80002a00 + 8000056a: 00002517 auipc a0,0x2 + 8000056e: 4d650513 addi a0,a0,1238 # 80002a40 + 80000572: 00000097 auipc ra,0x0 + 80000576: e38080e7 jalr -456(ra) # 800003aa + 8000057a: 4781 li a5,0 + 8000057c: 08000713 li a4,128 + 80000580: 04e7b07b .insn 4, 0x04e7b07b + 80000584: 10001737 lui a4,0x10001 + 80000588: 0712 slli a4,a4,0x4 + 8000058a: 0705 addi a4,a4,1 # 10001001 <_start-0x6fffefff> + 8000058c: a0e7b07b .insn 4, 0xa0e7b07b + 80000590: 577d li a4,-1 + 80000592: 8365 srli a4,a4,0x19 + 80000594: 00e97933 and s2,s2,a4 + 80000598: a327b07b .insn 4, 0xa327b07b + 8000059c: 8cf9 and s1,s1,a4 + 8000059e: a497b07b .insn 4, 0xa497b07b + 800005a2: 4681 li a3,0 + 800005a4: a6d7b07b .insn 4, 0xa6d7b07b + 800005a8: 00002697 auipc a3,0x2 + 800005ac: 35868693 addi a3,a3,856 # 80002900 + 800005b0: 8f75 and a4,a4,a3 + 800005b2: a8e7b07b .insn 4, 0xa8e7b07b + 800005b6: 46a1 li a3,8 + 800005b8: 02069713 slli a4,a3,0x20 + 800005bc: 9736 add a4,a4,a3 + 800005be: aae7b07b .insn 4, 0xaae7b07b + 800005c2: 4485 li s1,1 + 800005c4: 02549713 slli a4,s1,0x25 + 800005c8: ace7b07b .insn 4, 0xace7b07b + 800005cc: 40200737 lui a4,0x40200 + 800005d0: 40070713 addi a4,a4,1024 # 40200400 <_start-0x3fdffc00> + 800005d4: aee7b07b .insn 4, 0xaee7b07b + 800005d8: 00f7b07b .insn 4, 0x00f7b07b + 800005dc: 0330000f fence rw,rw + 800005e0: 0000100f fence.i + 800005e4: 00002517 auipc a0,0x2 + 800005e8: 31c50513 addi a0,a0,796 # 80002900 + 800005ec: 8636 mv a2,a3 + 800005ee: 00002597 auipc a1,0x2 + 800005f2: 21258593 addi a1,a1,530 # 80002800 + 800005f6: 00000097 auipc ra,0x0 + 800005fa: caa080e7 jalr -854(ra) # 800002a0 + 800005fe: e105 bnez a0,8000061e + 80000600: 00002517 auipc a0,0x2 + 80000604: b4050513 addi a0,a0,-1216 # 80002140 + 80000608: 00000097 auipc ra,0x0 + 8000060c: c52080e7 jalr -942(ra) # 8000025a + 80000610: 60e2 ld ra,24(sp) + 80000612: 6442 ld s0,16(sp) + 80000614: 6902 ld s2,0(sp) + 80000616: 8526 mv a0,s1 + 80000618: 64a2 ld s1,8(sp) + 8000061a: 6105 addi sp,sp,32 + 8000061c: 8082 ret + 8000061e: 00002517 auipc a0,0x2 + 80000622: af250513 addi a0,a0,-1294 # 80002110 + 80000626: 00000097 auipc ra,0x0 + 8000062a: c34080e7 jalr -972(ra) # 8000025a + 8000062e: 60e2 ld ra,24(sp) + 80000630: 6442 ld s0,16(sp) + 80000632: 64a2 ld s1,8(sp) + 80000634: 6902 ld s2,0(sp) + 80000636: 4501 li a0,0 + 80000638: 6105 addi sp,sp,32 + 8000063a: 8082 ret + +000000008000063c : + 8000063c: 1101 addi sp,sp,-32 + 8000063e: e822 sd s0,16(sp) + 80000640: e426 sd s1,8(sp) + 80000642: e04a sd s2,0(sp) + 80000644: ec06 sd ra,24(sp) + 80000646: 1000 addi s0,sp,32 + 80000648: 00002517 auipc a0,0x2 + 8000064c: b2850513 addi a0,a0,-1240 # 80002170 + 80000650: 00000097 auipc ra,0x0 + 80000654: c0a080e7 jalr -1014(ra) # 8000025a + 80000658: 00002917 auipc s2,0x2 + 8000065c: 6a890913 addi s2,s2,1704 # 80002d00 + 80000660: 00002497 auipc s1,0x2 + 80000664: 66048493 addi s1,s1,1632 # 80002cc0 + 80000668: 2e8ba337 lui t1,0x2e8ba + 8000066c: 4ec4f8b7 lui a7,0x4ec4f + 80000670: 8f4a mv t5,s2 + 80000672: 8ea6 mv t4,s1 + 80000674: 2e930313 addi t1,t1,745 # 2e8ba2e9 <_start-0x51745d17> + 80000678: c4f88893 addi a7,a7,-945 # 4ec4ec4f <_start-0x313b13b1> + 8000067c: 02800813 li a6,40 + 80000680: 4e01 li t3,0 + 80000682: 04000f93 li t6,64 + 80000686: fd88069b addiw a3,a6,-40 + 8000068a: 8576 mv a0,t4 + 8000068c: 8672 mv a2,t3 + 8000068e: 85fa mv a1,t5 + 80000690: 026682b3 mul t0,a3,t1 + 80000694: 02061713 slli a4,a2,0x20 + 80000698: 9301 srli a4,a4,0x20 + 8000069a: 41f6d79b sraiw a5,a3,0x1f + 8000069e: 0505 addi a0,a0,1 + 800006a0: 0585 addi a1,a1,1 + 800006a2: 03170733 mul a4,a4,a7 + 800006a6: 4212d293 srai t0,t0,0x21 + 800006aa: 40f282bb subw t0,t0,a5 + 800006ae: 0012979b slliw a5,t0,0x1 + 800006b2: 005787bb addw a5,a5,t0 + 800006b6: 0027979b slliw a5,a5,0x2 + 800006ba: 405787bb subw a5,a5,t0 + 800006be: 40f687bb subw a5,a3,a5 + 800006c2: 37ed addiw a5,a5,-5 + 800006c4: fef58fa3 sb a5,-1(a1) + 800006c8: 9309 srli a4,a4,0x22 + 800006ca: 0017179b slliw a5,a4,0x1 + 800006ce: 9fb9 addw a5,a5,a4 + 800006d0: 0027979b slliw a5,a5,0x2 + 800006d4: 9fb9 addw a5,a5,a4 + 800006d6: 40f607bb subw a5,a2,a5 + 800006da: 37e9 addiw a5,a5,-6 + 800006dc: fef50fa3 sb a5,-1(a0) + 800006e0: 2695 addiw a3,a3,5 + 800006e2: 2609 addiw a2,a2,2 + 800006e4: fb0696e3 bne a3,a6,80000690 + 800006e8: 0036881b addiw a6,a3,3 + 800006ec: 0f21 addi t5,t5,8 + 800006ee: 2e1d addiw t3,t3,7 + 800006f0: 0ea1 addi t4,t4,8 + 800006f2: f9f81ae3 bne a6,t6,80000686 + 800006f6: 47a1 li a5,8 + 800006f8: 873e mv a4,a5 + 800006fa: 86be mv a3,a5 + 800006fc: 00002617 auipc a2,0x2 + 80000700: 3c460613 addi a2,a2,964 # 80002ac0 + 80000704: 00002597 auipc a1,0x2 + 80000708: 5bc58593 addi a1,a1,1468 # 80002cc0 + 8000070c: 00002517 auipc a0,0x2 + 80000710: 5f450513 addi a0,a0,1524 # 80002d00 + 80000714: 00000097 auipc ra,0x0 + 80000718: c96080e7 jalr -874(ra) # 800003aa + 8000071c: 4781 li a5,0 + 8000071e: 4681 li a3,0 + 80000720: 04d7b07b .insn 4, 0x04d7b07b + 80000724: 10001737 lui a4,0x10001 + 80000728: 0712 slli a4,a4,0x4 + 8000072a: 0705 addi a4,a4,1 # 10001001 <_start-0x6fffefff> + 8000072c: a0e7b07b .insn 4, 0xa0e7b07b + 80000730: 577d li a4,-1 + 80000732: 8365 srli a4,a4,0x19 + 80000734: 00e97933 and s2,s2,a4 + 80000738: a327b07b .insn 4, 0xa327b07b + 8000073c: 8cf9 and s1,s1,a4 + 8000073e: a497b07b .insn 4, 0xa497b07b + 80000742: a6d7b07b .insn 4, 0xa6d7b07b + 80000746: 00002697 auipc a3,0x2 + 8000074a: 47a68693 addi a3,a3,1146 # 80002bc0 + 8000074e: 8f75 and a4,a4,a3 + 80000750: a8e7b07b .insn 4, 0xa8e7b07b + 80000754: 46a1 li a3,8 + 80000756: 02069713 slli a4,a3,0x20 + 8000075a: 9736 add a4,a4,a3 + 8000075c: aae7b07b .insn 4, 0xaae7b07b + 80000760: 4485 li s1,1 + 80000762: 02549713 slli a4,s1,0x25 + 80000766: ace7b07b .insn 4, 0xace7b07b + 8000076a: 40200737 lui a4,0x40200 + 8000076e: 40070713 addi a4,a4,1024 # 40200400 <_start-0x3fdffc00> + 80000772: aee7b07b .insn 4, 0xaee7b07b + 80000776: 00f7b07b .insn 4, 0x00f7b07b + 8000077a: 0330000f fence rw,rw + 8000077e: 0000100f fence.i + 80000782: 00002517 auipc a0,0x2 + 80000786: 43e50513 addi a0,a0,1086 # 80002bc0 + 8000078a: 8636 mv a2,a3 + 8000078c: 00002597 auipc a1,0x2 + 80000790: 33458593 addi a1,a1,820 # 80002ac0 + 80000794: 00000097 auipc ra,0x0 + 80000798: b0c080e7 jalr -1268(ra) # 800002a0 + 8000079c: e105 bnez a0,800007bc + 8000079e: 00002517 auipc a0,0x2 + 800007a2: a2250513 addi a0,a0,-1502 # 800021c0 + 800007a6: 00000097 auipc ra,0x0 + 800007aa: ab4080e7 jalr -1356(ra) # 8000025a + 800007ae: 60e2 ld ra,24(sp) + 800007b0: 6442 ld s0,16(sp) + 800007b2: 6902 ld s2,0(sp) + 800007b4: 8526 mv a0,s1 + 800007b6: 64a2 ld s1,8(sp) + 800007b8: 6105 addi sp,sp,32 + 800007ba: 8082 ret + 800007bc: 00002517 auipc a0,0x2 + 800007c0: 9dc50513 addi a0,a0,-1572 # 80002198 + 800007c4: 00000097 auipc ra,0x0 + 800007c8: a96080e7 jalr -1386(ra) # 8000025a + 800007cc: 60e2 ld ra,24(sp) + 800007ce: 6442 ld s0,16(sp) + 800007d0: 64a2 ld s1,8(sp) + 800007d2: 6902 ld s2,0(sp) + 800007d4: 4501 li a0,0 + 800007d6: 6105 addi sp,sp,32 + 800007d8: 8082 ret + +00000000800007da : + 800007da: 1101 addi sp,sp,-32 + 800007dc: e822 sd s0,16(sp) + 800007de: e426 sd s1,8(sp) + 800007e0: e04a sd s2,0(sp) + 800007e2: ec06 sd ra,24(sp) + 800007e4: 1000 addi s0,sp,32 + 800007e6: 00002517 auipc a0,0x2 + 800007ea: a0250513 addi a0,a0,-1534 # 800021e8 + 800007ee: 00000097 auipc ra,0x0 + 800007f2: a6c080e7 jalr -1428(ra) # 8000025a + 800007f6: 00002917 auipc s2,0x2 + 800007fa: 7ca90913 addi s2,s2,1994 # 80002fc0 + 800007fe: 00002497 auipc s1,0x2 + 80000802: 78248493 addi s1,s1,1922 # 80002f80 + 80000806: 2e8ba337 lui t1,0x2e8ba + 8000080a: 4ec4f8b7 lui a7,0x4ec4f + 8000080e: 8f4a mv t5,s2 + 80000810: 8ea6 mv t4,s1 + 80000812: 2e930313 addi t1,t1,745 # 2e8ba2e9 <_start-0x51745d17> + 80000816: c4f88893 addi a7,a7,-945 # 4ec4ec4f <_start-0x313b13b1> + 8000081a: 02800813 li a6,40 + 8000081e: 4e01 li t3,0 + 80000820: 04000f93 li t6,64 + 80000824: fd88069b addiw a3,a6,-40 + 80000828: 8576 mv a0,t4 + 8000082a: 8672 mv a2,t3 + 8000082c: 85fa mv a1,t5 + 8000082e: 026682b3 mul t0,a3,t1 + 80000832: 02061713 slli a4,a2,0x20 + 80000836: 9301 srli a4,a4,0x20 + 80000838: 41f6d79b sraiw a5,a3,0x1f + 8000083c: 0505 addi a0,a0,1 + 8000083e: 0585 addi a1,a1,1 + 80000840: 03170733 mul a4,a4,a7 + 80000844: 4212d293 srai t0,t0,0x21 + 80000848: 40f282bb subw t0,t0,a5 + 8000084c: 0012979b slliw a5,t0,0x1 + 80000850: 005787bb addw a5,a5,t0 + 80000854: 0027979b slliw a5,a5,0x2 + 80000858: 405787bb subw a5,a5,t0 + 8000085c: 40f687bb subw a5,a3,a5 + 80000860: 37ed addiw a5,a5,-5 + 80000862: fef58fa3 sb a5,-1(a1) + 80000866: 9309 srli a4,a4,0x22 + 80000868: 0017179b slliw a5,a4,0x1 + 8000086c: 9fb9 addw a5,a5,a4 + 8000086e: 0027979b slliw a5,a5,0x2 + 80000872: 9fb9 addw a5,a5,a4 + 80000874: 40f607bb subw a5,a2,a5 + 80000878: 37e9 addiw a5,a5,-6 + 8000087a: fef50fa3 sb a5,-1(a0) + 8000087e: 2695 addiw a3,a3,5 + 80000880: 2609 addiw a2,a2,2 + 80000882: fb0696e3 bne a3,a6,8000082e + 80000886: 0036881b addiw a6,a3,3 + 8000088a: 0f21 addi t5,t5,8 + 8000088c: 2e1d addiw t3,t3,7 + 8000088e: 0ea1 addi t4,t4,8 + 80000890: f9f81ae3 bne a6,t6,80000824 + 80000894: 46a1 li a3,8 + 80000896: 8636 mv a2,a3 + 80000898: 00002597 auipc a1,0x2 + 8000089c: 6a858593 addi a1,a1,1704 # 80002f40 + 800008a0: 00002517 auipc a0,0x2 + 800008a4: 6e050513 addi a0,a0,1760 # 80002f80 + 800008a8: 00000097 auipc ra,0x0 + 800008ac: a5a080e7 jalr -1446(ra) # 80000302 + 800008b0: 47a1 li a5,8 + 800008b2: 873e mv a4,a5 + 800008b4: 86be mv a3,a5 + 800008b6: 00002617 auipc a2,0x2 + 800008ba: 48a60613 addi a2,a2,1162 # 80002d40 + 800008be: 00002597 auipc a1,0x2 + 800008c2: 68258593 addi a1,a1,1666 # 80002f40 + 800008c6: 00002517 auipc a0,0x2 + 800008ca: 6fa50513 addi a0,a0,1786 # 80002fc0 + 800008ce: 00000097 auipc ra,0x0 + 800008d2: adc080e7 jalr -1316(ra) # 800003aa + 800008d6: 4781 li a5,0 + 800008d8: 10000713 li a4,256 + 800008dc: 04e7b07b .insn 4, 0x04e7b07b + 800008e0: 10001737 lui a4,0x10001 + 800008e4: 0712 slli a4,a4,0x4 + 800008e6: 0705 addi a4,a4,1 # 10001001 <_start-0x6fffefff> + 800008e8: a0e7b07b .insn 4, 0xa0e7b07b + 800008ec: 577d li a4,-1 + 800008ee: 8365 srli a4,a4,0x19 + 800008f0: 00e97933 and s2,s2,a4 + 800008f4: a327b07b .insn 4, 0xa327b07b + 800008f8: 8cf9 and s1,s1,a4 + 800008fa: a497b07b .insn 4, 0xa497b07b + 800008fe: 4681 li a3,0 + 80000900: a6d7b07b .insn 4, 0xa6d7b07b + 80000904: 00002697 auipc a3,0x2 + 80000908: 53c68693 addi a3,a3,1340 # 80002e40 + 8000090c: 8f75 and a4,a4,a3 + 8000090e: a8e7b07b .insn 4, 0xa8e7b07b + 80000912: 46a1 li a3,8 + 80000914: 02069713 slli a4,a3,0x20 + 80000918: 9736 add a4,a4,a3 + 8000091a: aae7b07b .insn 4, 0xaae7b07b + 8000091e: 4485 li s1,1 + 80000920: 02549713 slli a4,s1,0x25 + 80000924: ace7b07b .insn 4, 0xace7b07b + 80000928: 40200737 lui a4,0x40200 + 8000092c: 40070713 addi a4,a4,1024 # 40200400 <_start-0x3fdffc00> + 80000930: aee7b07b .insn 4, 0xaee7b07b + 80000934: 00f7b07b .insn 4, 0x00f7b07b + 80000938: 0330000f fence rw,rw + 8000093c: 0000100f fence.i + 80000940: 00002517 auipc a0,0x2 + 80000944: 50050513 addi a0,a0,1280 # 80002e40 + 80000948: 8636 mv a2,a3 + 8000094a: 00002597 auipc a1,0x2 + 8000094e: 3f658593 addi a1,a1,1014 # 80002d40 + 80000952: 00000097 auipc ra,0x0 + 80000956: 94e080e7 jalr -1714(ra) # 800002a0 + 8000095a: e105 bnez a0,8000097a + 8000095c: 00002517 auipc a0,0x2 + 80000960: 8ec50513 addi a0,a0,-1812 # 80002248 + 80000964: 00000097 auipc ra,0x0 + 80000968: 8f6080e7 jalr -1802(ra) # 8000025a + 8000096c: 60e2 ld ra,24(sp) + 8000096e: 6442 ld s0,16(sp) + 80000970: 6902 ld s2,0(sp) + 80000972: 8526 mv a0,s1 + 80000974: 64a2 ld s1,8(sp) + 80000976: 6105 addi sp,sp,32 + 80000978: 8082 ret + 8000097a: 00002517 auipc a0,0x2 + 8000097e: 89e50513 addi a0,a0,-1890 # 80002218 + 80000982: 00000097 auipc ra,0x0 + 80000986: 8d8080e7 jalr -1832(ra) # 8000025a + 8000098a: 60e2 ld ra,24(sp) + 8000098c: 6442 ld s0,16(sp) + 8000098e: 64a2 ld s1,8(sp) + 80000990: 6902 ld s2,0(sp) + 80000992: 4501 li a0,0 + 80000994: 6105 addi sp,sp,32 + 80000996: 8082 ret + +0000000080000998 : + 80000998: 7179 addi sp,sp,-48 + 8000099a: f022 sd s0,32(sp) + 8000099c: ec26 sd s1,24(sp) + 8000099e: e84a sd s2,16(sp) + 800009a0: f406 sd ra,40(sp) + 800009a2: e44e sd s3,8(sp) + 800009a4: e052 sd s4,0(sp) + 800009a6: 1800 addi s0,sp,48 + 800009a8: 00002517 auipc a0,0x2 + 800009ac: 8d050513 addi a0,a0,-1840 # 80002278 + 800009b0: 00000097 auipc ra,0x0 + 800009b4: 8aa080e7 jalr -1878(ra) # 8000025a + 800009b8: 00003917 auipc s2,0x3 + 800009bc: 88890913 addi s2,s2,-1912 # 80003240 + 800009c0: 00003497 auipc s1,0x3 + 800009c4: 84048493 addi s1,s1,-1984 # 80003200 + 800009c8: 2e8ba337 lui t1,0x2e8ba + 800009cc: 4ec4f8b7 lui a7,0x4ec4f + 800009d0: 8f4a mv t5,s2 + 800009d2: 8ea6 mv t4,s1 + 800009d4: 2e930313 addi t1,t1,745 # 2e8ba2e9 <_start-0x51745d17> + 800009d8: c4f88893 addi a7,a7,-945 # 4ec4ec4f <_start-0x313b13b1> + 800009dc: 02800813 li a6,40 + 800009e0: 4e01 li t3,0 + 800009e2: 04000f93 li t6,64 + 800009e6: fd88069b addiw a3,a6,-40 + 800009ea: 8576 mv a0,t4 + 800009ec: 8672 mv a2,t3 + 800009ee: 85fa mv a1,t5 + 800009f0: 026682b3 mul t0,a3,t1 + 800009f4: 02061713 slli a4,a2,0x20 + 800009f8: 9301 srli a4,a4,0x20 + 800009fa: 41f6d79b sraiw a5,a3,0x1f + 800009fe: 0505 addi a0,a0,1 + 80000a00: 0585 addi a1,a1,1 + 80000a02: 03170733 mul a4,a4,a7 + 80000a06: 4212d293 srai t0,t0,0x21 + 80000a0a: 40f282bb subw t0,t0,a5 + 80000a0e: 0012979b slliw a5,t0,0x1 + 80000a12: 005787bb addw a5,a5,t0 + 80000a16: 0027979b slliw a5,a5,0x2 + 80000a1a: 405787bb subw a5,a5,t0 + 80000a1e: 40f687bb subw a5,a3,a5 + 80000a22: 37ed addiw a5,a5,-5 + 80000a24: fef58fa3 sb a5,-1(a1) + 80000a28: 9309 srli a4,a4,0x22 + 80000a2a: 0017179b slliw a5,a4,0x1 + 80000a2e: 9fb9 addw a5,a5,a4 + 80000a30: 0027979b slliw a5,a5,0x2 + 80000a34: 9fb9 addw a5,a5,a4 + 80000a36: 40f607bb subw a5,a2,a5 + 80000a3a: 37e9 addiw a5,a5,-6 + 80000a3c: fef50fa3 sb a5,-1(a0) + 80000a40: 2695 addiw a3,a3,5 + 80000a42: 2609 addiw a2,a2,2 + 80000a44: fb0696e3 bne a3,a6,800009f0 + 80000a48: 0036881b addiw a6,a3,3 + 80000a4c: 0f21 addi t5,t5,8 + 80000a4e: 2e1d addiw t3,t3,7 + 80000a50: 0ea1 addi t4,t4,8 + 80000a52: f9f81ae3 bne a6,t6,800009e6 + 80000a56: 47a1 li a5,8 + 80000a58: 873e mv a4,a5 + 80000a5a: 86be mv a3,a5 + 80000a5c: 00002617 auipc a2,0x2 + 80000a60: 5a460613 addi a2,a2,1444 # 80003000 + 80000a64: 00002597 auipc a1,0x2 + 80000a68: 79c58593 addi a1,a1,1948 # 80003200 + 80000a6c: 00002517 auipc a0,0x2 + 80000a70: 7d450513 addi a0,a0,2004 # 80003240 + 80000a74: 00000097 auipc ra,0x0 + 80000a78: 936080e7 jalr -1738(ra) # 800003aa + 80000a7c: 00002997 auipc s3,0x2 + 80000a80: 58498993 addi s3,s3,1412 # 80003000 + 80000a84: 00002a17 auipc s4,0x2 + 80000a88: 67ca0a13 addi s4,s4,1660 # 80003100 + 80000a8c: 0009a503 lw a0,0(s3) + 80000a90: 4591 li a1,4 + 80000a92: 0991 addi s3,s3,4 + 80000a94: 00000097 auipc ra,0x0 + 80000a98: 8c6080e7 jalr -1850(ra) # 8000035a + 80000a9c: fea9ae23 sw a0,-4(s3) + 80000aa0: ff3a16e3 bne s4,s3,80000a8c + 80000aa4: 6705 lui a4,0x1 + 80000aa6: 80070713 addi a4,a4,-2048 # 800 <_start-0x7ffff800> + 80000aaa: 4781 li a5,0 + 80000aac: 04e7b07b .insn 4, 0x04e7b07b + 80000ab0: 10001737 lui a4,0x10001 + 80000ab4: 0712 slli a4,a4,0x4 + 80000ab6: 0705 addi a4,a4,1 # 10001001 <_start-0x6fffefff> + 80000ab8: a0e7b07b .insn 4, 0xa0e7b07b + 80000abc: 577d li a4,-1 + 80000abe: 8365 srli a4,a4,0x19 + 80000ac0: 00e97933 and s2,s2,a4 + 80000ac4: a327b07b .insn 4, 0xa327b07b + 80000ac8: 8cf9 and s1,s1,a4 + 80000aca: a497b07b .insn 4, 0xa497b07b + 80000ace: 4681 li a3,0 + 80000ad0: a6d7b07b .insn 4, 0xa6d7b07b + 80000ad4: 00002697 auipc a3,0x2 + 80000ad8: 62c68693 addi a3,a3,1580 # 80003100 + 80000adc: 8f75 and a4,a4,a3 + 80000ade: a8e7b07b .insn 4, 0xa8e7b07b + 80000ae2: 46a1 li a3,8 + 80000ae4: 02069713 slli a4,a3,0x20 + 80000ae8: 9736 add a4,a4,a3 + 80000aea: aae7b07b .insn 4, 0xaae7b07b + 80000aee: 4485 li s1,1 + 80000af0: 02549713 slli a4,s1,0x25 + 80000af4: ace7b07b .insn 4, 0xace7b07b + 80000af8: 40200737 lui a4,0x40200 + 80000afc: 40070713 addi a4,a4,1024 # 40200400 <_start-0x3fdffc00> + 80000b00: aee7b07b .insn 4, 0xaee7b07b + 80000b04: 00f7b07b .insn 4, 0x00f7b07b + 80000b08: 0330000f fence rw,rw + 80000b0c: 0000100f fence.i + 80000b10: 00002517 auipc a0,0x2 + 80000b14: 5f050513 addi a0,a0,1520 # 80003100 + 80000b18: 8636 mv a2,a3 + 80000b1a: 00002597 auipc a1,0x2 + 80000b1e: 4e658593 addi a1,a1,1254 # 80003000 + 80000b22: fffff097 auipc ra,0xfffff + 80000b26: 77e080e7 jalr 1918(ra) # 800002a0 + 80000b2a: e115 bnez a0,80000b4e + 80000b2c: 00001517 auipc a0,0x1 + 80000b30: 79c50513 addi a0,a0,1948 # 800022c8 + 80000b34: fffff097 auipc ra,0xfffff + 80000b38: 726080e7 jalr 1830(ra) # 8000025a + 80000b3c: 70a2 ld ra,40(sp) + 80000b3e: 7402 ld s0,32(sp) + 80000b40: 6942 ld s2,16(sp) + 80000b42: 69a2 ld s3,8(sp) + 80000b44: 6a02 ld s4,0(sp) + 80000b46: 8526 mv a0,s1 + 80000b48: 64e2 ld s1,24(sp) + 80000b4a: 6145 addi sp,sp,48 + 80000b4c: 8082 ret + 80000b4e: 00001517 auipc a0,0x1 + 80000b52: 75250513 addi a0,a0,1874 # 800022a0 + 80000b56: fffff097 auipc ra,0xfffff + 80000b5a: 704080e7 jalr 1796(ra) # 8000025a + 80000b5e: 70a2 ld ra,40(sp) + 80000b60: 7402 ld s0,32(sp) + 80000b62: 64e2 ld s1,24(sp) + 80000b64: 6942 ld s2,16(sp) + 80000b66: 69a2 ld s3,8(sp) + 80000b68: 6a02 ld s4,0(sp) + 80000b6a: 4501 li a0,0 + 80000b6c: 6145 addi sp,sp,48 + 80000b6e: 8082 ret + +0000000080000b70 : + 80000b70: 7139 addi sp,sp,-64 + 80000b72: f822 sd s0,48(sp) + 80000b74: f426 sd s1,40(sp) + 80000b76: f04a sd s2,32(sp) + 80000b78: fc06 sd ra,56(sp) + 80000b7a: ec4e sd s3,24(sp) + 80000b7c: e852 sd s4,16(sp) + 80000b7e: e456 sd s5,8(sp) + 80000b80: 0080 addi s0,sp,64 + 80000b82: 00001517 auipc a0,0x1 + 80000b86: 76e50513 addi a0,a0,1902 # 800022f0 + 80000b8a: fffff097 auipc ra,0xfffff + 80000b8e: 6d0080e7 jalr 1744(ra) # 8000025a + 80000b92: 00003917 auipc s2,0x3 + 80000b96: 9ae90913 addi s2,s2,-1618 # 80003540 + 80000b9a: 00003497 auipc s1,0x3 + 80000b9e: 96648493 addi s1,s1,-1690 # 80003500 + 80000ba2: 2e8ba337 lui t1,0x2e8ba + 80000ba6: 4ec4f8b7 lui a7,0x4ec4f + 80000baa: 8f4a mv t5,s2 + 80000bac: 8ea6 mv t4,s1 + 80000bae: 2e930313 addi t1,t1,745 # 2e8ba2e9 <_start-0x51745d17> + 80000bb2: c4f88893 addi a7,a7,-945 # 4ec4ec4f <_start-0x313b13b1> + 80000bb6: 02800813 li a6,40 + 80000bba: 4e01 li t3,0 + 80000bbc: 04000f93 li t6,64 + 80000bc0: fd88069b addiw a3,a6,-40 + 80000bc4: 8576 mv a0,t4 + 80000bc6: 8672 mv a2,t3 + 80000bc8: 85fa mv a1,t5 + 80000bca: 026682b3 mul t0,a3,t1 + 80000bce: 02061713 slli a4,a2,0x20 + 80000bd2: 9301 srli a4,a4,0x20 + 80000bd4: 41f6d79b sraiw a5,a3,0x1f + 80000bd8: 0505 addi a0,a0,1 + 80000bda: 0585 addi a1,a1,1 + 80000bdc: 03170733 mul a4,a4,a7 + 80000be0: 4212d293 srai t0,t0,0x21 + 80000be4: 40f282bb subw t0,t0,a5 + 80000be8: 0012979b slliw a5,t0,0x1 + 80000bec: 005787bb addw a5,a5,t0 + 80000bf0: 0027979b slliw a5,a5,0x2 + 80000bf4: 405787bb subw a5,a5,t0 + 80000bf8: 40f687bb subw a5,a3,a5 + 80000bfc: 37ed addiw a5,a5,-5 + 80000bfe: fef58fa3 sb a5,-1(a1) + 80000c02: 9309 srli a4,a4,0x22 + 80000c04: 0017179b slliw a5,a4,0x1 + 80000c08: 9fb9 addw a5,a5,a4 + 80000c0a: 0027979b slliw a5,a5,0x2 + 80000c0e: 9fb9 addw a5,a5,a4 + 80000c10: 40f607bb subw a5,a2,a5 + 80000c14: 37e9 addiw a5,a5,-6 + 80000c16: fef50fa3 sb a5,-1(a0) + 80000c1a: 2695 addiw a3,a3,5 + 80000c1c: 2609 addiw a2,a2,2 + 80000c1e: fb0696e3 bne a3,a6,80000bca + 80000c22: 0036881b addiw a6,a3,3 + 80000c26: 0f21 addi t5,t5,8 + 80000c28: 2e1d addiw t3,t3,7 + 80000c2a: 0ea1 addi t4,t4,8 + 80000c2c: f9f81ae3 bne a6,t6,80000bc0 + 80000c30: 46a1 li a3,8 + 80000c32: 8636 mv a2,a3 + 80000c34: 00003597 auipc a1,0x3 + 80000c38: 88c58593 addi a1,a1,-1908 # 800034c0 + 80000c3c: 00003517 auipc a0,0x3 + 80000c40: 90450513 addi a0,a0,-1788 # 80003540 + 80000c44: fffff097 auipc ra,0xfffff + 80000c48: 6be080e7 jalr 1726(ra) # 80000302 + 80000c4c: 46a1 li a3,8 + 80000c4e: 8636 mv a2,a3 + 80000c50: 00003597 auipc a1,0x3 + 80000c54: 83058593 addi a1,a1,-2000 # 80003480 + 80000c58: 00003517 auipc a0,0x3 + 80000c5c: 8a850513 addi a0,a0,-1880 # 80003500 + 80000c60: fffff097 auipc ra,0xfffff + 80000c64: 6a2080e7 jalr 1698(ra) # 80000302 + 80000c68: 47a1 li a5,8 + 80000c6a: 873e mv a4,a5 + 80000c6c: 86be mv a3,a5 + 80000c6e: 00002617 auipc a2,0x2 + 80000c72: 61260613 addi a2,a2,1554 # 80003280 + 80000c76: 00003597 auipc a1,0x3 + 80000c7a: 80a58593 addi a1,a1,-2038 # 80003480 + 80000c7e: 00003517 auipc a0,0x3 + 80000c82: 84250513 addi a0,a0,-1982 # 800034c0 + 80000c86: fffff097 auipc ra,0xfffff + 80000c8a: 724080e7 jalr 1828(ra) # 800003aa + 80000c8e: 4585 li a1,1 + 80000c90: 4501 li a0,0 + 80000c92: fffff097 auipc ra,0xfffff + 80000c96: 58e080e7 jalr 1422(ra) # 80000220 + 80000c9a: 4a01 li s4,0 + 80000c9c: 42100a93 li s5,1057 + 80000ca0: 415a307b .insn 4, 0x415a307b + 80000ca4: 4585 li a1,1 + 80000ca6: 852e mv a0,a1 + 80000ca8: fffff097 auipc ra,0xfffff + 80000cac: 578080e7 jalr 1400(ra) # 80000220 + 80000cb0: 4985 li s3,1 + 80000cb2: 4159b07b .insn 4, 0x4159b07b + 80000cb6: 4591 li a1,4 + 80000cb8: 4509 li a0,2 + 80000cba: fffff097 auipc ra,0xfffff + 80000cbe: 566080e7 jalr 1382(ra) # 80000220 + 80000cc2: 4a89 li s5,2 + 80000cc4: 48100793 li a5,1153 + 80000cc8: 40fab07b .insn 4, 0x40fab07b + 80000ccc: 0000100f fence.i + 80000cd0: 57fd li a5,-1 + 80000cd2: 83e5 srli a5,a5,0x19 + 80000cd4: 00f97733 and a4,s2,a5 + 80000cd8: 02799613 slli a2,s3,0x27 + 80000cdc: 8f51 or a4,a4,a2 + 80000cde: 02199693 slli a3,s3,0x21 + 80000ce2: 42e6b07b .insn 4, 0x42e6b07b + 80000ce6: 0000100f fence.i + 80000cea: 020016b7 lui a3,0x2001 + 80000cee: 00f4f733 and a4,s1,a5 + 80000cf2: 8f51 or a4,a4,a2 + 80000cf4: 06a2 slli a3,a3,0x8 + 80000cf6: 42e6b07b .insn 4, 0x42e6b07b + 80000cfa: 4681 li a3,0 + 80000cfc: 18000713 li a4,384 + 80000d00: 04e6b07b .insn 4, 0x04e6b07b + 80000d04: 01001737 lui a4,0x1001 + 80000d08: 0726 slli a4,a4,0x9 + 80000d0a: 6b37307b .insn 4, 0x6b37307b + 80000d0e: 01001737 lui a4,0x1001 + 80000d12: 0726 slli a4,a4,0x9 + 80000d14: 40070713 addi a4,a4,1024 # 1001400 <_start-0x7effec00> + 80000d18: 8557307b .insn 4, 0x8557307b + 80000d1c: 0000100f fence.i + 80000d20: 00002717 auipc a4,0x2 + 80000d24: 66070713 addi a4,a4,1632 # 80003380 + 80000d28: 8ff9 and a5,a5,a4 + 80000d2a: 020a9713 slli a4,s5,0x20 + 80000d2e: 8fd1 or a5,a5,a2 + 80000d30: 9756 add a4,a4,s5 + 80000d32: 20f7307b .insn 4, 0x20f7307b + 80000d36: 00d6b07b .insn 4, 0x00d6b07b + 80000d3a: 0330000f fence rw,rw + 80000d3e: 0000100f fence.i + 80000d42: 4501 li a0,0 + 80000d44: 85ce mv a1,s3 + 80000d46: fffff097 auipc ra,0xfffff + 80000d4a: 4da080e7 jalr 1242(ra) # 80000220 + 80000d4e: 414a307b .insn 4, 0x414a307b + 80000d52: 85ce mv a1,s3 + 80000d54: 854e mv a0,s3 + 80000d56: fffff097 auipc ra,0xfffff + 80000d5a: 4ca080e7 jalr 1226(ra) # 80000220 + 80000d5e: 4149b07b .insn 4, 0x4149b07b + 80000d62: 85ce mv a1,s3 + 80000d64: 8556 mv a0,s5 + 80000d66: fffff097 auipc ra,0xfffff + 80000d6a: 4ba080e7 jalr 1210(ra) # 80000220 + 80000d6e: 414ab07b .insn 4, 0x414ab07b + 80000d72: 46a1 li a3,8 + 80000d74: 00002517 auipc a0,0x2 + 80000d78: 60c50513 addi a0,a0,1548 # 80003380 + 80000d7c: 8636 mv a2,a3 + 80000d7e: 00002597 auipc a1,0x2 + 80000d82: 50258593 addi a1,a1,1282 # 80003280 + 80000d86: fffff097 auipc ra,0xfffff + 80000d8a: 51a080e7 jalr 1306(ra) # 800002a0 + 80000d8e: e11d bnez a0,80000db4 + 80000d90: 00001517 auipc a0,0x1 + 80000d94: 5c050513 addi a0,a0,1472 # 80002350 + 80000d98: fffff097 auipc ra,0xfffff + 80000d9c: 4c2080e7 jalr 1218(ra) # 8000025a + 80000da0: 854e mv a0,s3 + 80000da2: 70e2 ld ra,56(sp) + 80000da4: 7442 ld s0,48(sp) + 80000da6: 74a2 ld s1,40(sp) + 80000da8: 7902 ld s2,32(sp) + 80000daa: 69e2 ld s3,24(sp) + 80000dac: 6a42 ld s4,16(sp) + 80000dae: 6aa2 ld s5,8(sp) + 80000db0: 6121 addi sp,sp,64 + 80000db2: 8082 ret + 80000db4: 00001517 auipc a0,0x1 + 80000db8: 56c50513 addi a0,a0,1388 # 80002320 + 80000dbc: fffff097 auipc ra,0xfffff + 80000dc0: 49e080e7 jalr 1182(ra) # 8000025a + 80000dc4: 4501 li a0,0 + 80000dc6: bff1 j 80000da2 + +0000000080000dc8 : + 80000dc8: 7139 addi sp,sp,-64 + 80000dca: f822 sd s0,48(sp) + 80000dcc: f426 sd s1,40(sp) + 80000dce: f04a sd s2,32(sp) + 80000dd0: fc06 sd ra,56(sp) + 80000dd2: ec4e sd s3,24(sp) + 80000dd4: e852 sd s4,16(sp) + 80000dd6: e456 sd s5,8(sp) + 80000dd8: 0080 addi s0,sp,64 + 80000dda: 00001517 auipc a0,0x1 + 80000dde: 5a650513 addi a0,a0,1446 # 80002380 + 80000de2: fffff097 auipc ra,0xfffff + 80000de6: 478080e7 jalr 1144(ra) # 8000025a + 80000dea: 00003917 auipc s2,0x3 + 80000dee: a1690913 addi s2,s2,-1514 # 80003800 + 80000df2: 00003497 auipc s1,0x3 + 80000df6: 9ce48493 addi s1,s1,-1586 # 800037c0 + 80000dfa: 2e8ba337 lui t1,0x2e8ba + 80000dfe: 4ec4f8b7 lui a7,0x4ec4f + 80000e02: 8f4a mv t5,s2 + 80000e04: 8ea6 mv t4,s1 + 80000e06: 2e930313 addi t1,t1,745 # 2e8ba2e9 <_start-0x51745d17> + 80000e0a: c4f88893 addi a7,a7,-945 # 4ec4ec4f <_start-0x313b13b1> + 80000e0e: 02800813 li a6,40 + 80000e12: 4e01 li t3,0 + 80000e14: 04000f93 li t6,64 + 80000e18: fd88069b addiw a3,a6,-40 + 80000e1c: 8576 mv a0,t4 + 80000e1e: 8672 mv a2,t3 + 80000e20: 85fa mv a1,t5 + 80000e22: 026682b3 mul t0,a3,t1 + 80000e26: 02061713 slli a4,a2,0x20 + 80000e2a: 9301 srli a4,a4,0x20 + 80000e2c: 41f6d79b sraiw a5,a3,0x1f + 80000e30: 0505 addi a0,a0,1 + 80000e32: 0585 addi a1,a1,1 + 80000e34: 03170733 mul a4,a4,a7 + 80000e38: 4212d293 srai t0,t0,0x21 + 80000e3c: 40f282bb subw t0,t0,a5 + 80000e40: 0012979b slliw a5,t0,0x1 + 80000e44: 005787bb addw a5,a5,t0 + 80000e48: 0027979b slliw a5,a5,0x2 + 80000e4c: 405787bb subw a5,a5,t0 + 80000e50: 40f687bb subw a5,a3,a5 + 80000e54: 37ed addiw a5,a5,-5 + 80000e56: fef58fa3 sb a5,-1(a1) + 80000e5a: 9309 srli a4,a4,0x22 + 80000e5c: 0017179b slliw a5,a4,0x1 + 80000e60: 9fb9 addw a5,a5,a4 + 80000e62: 0027979b slliw a5,a5,0x2 + 80000e66: 9fb9 addw a5,a5,a4 + 80000e68: 40f607bb subw a5,a2,a5 + 80000e6c: 37e9 addiw a5,a5,-6 + 80000e6e: fef50fa3 sb a5,-1(a0) + 80000e72: 2695 addiw a3,a3,5 # 2001005 <_start-0x7dffeffb> + 80000e74: 2609 addiw a2,a2,2 + 80000e76: fb0696e3 bne a3,a6,80000e22 + 80000e7a: 0036881b addiw a6,a3,3 + 80000e7e: 0f21 addi t5,t5,8 + 80000e80: 2e1d addiw t3,t3,7 + 80000e82: 0ea1 addi t4,t4,8 + 80000e84: f9f81ae3 bne a6,t6,80000e18 + 80000e88: 46a1 li a3,8 + 80000e8a: 8636 mv a2,a3 + 80000e8c: 00003597 auipc a1,0x3 + 80000e90: 8f458593 addi a1,a1,-1804 # 80003780 + 80000e94: 00003517 auipc a0,0x3 + 80000e98: 96c50513 addi a0,a0,-1684 # 80003800 + 80000e9c: fffff097 auipc ra,0xfffff + 80000ea0: 466080e7 jalr 1126(ra) # 80000302 + 80000ea4: 47a1 li a5,8 + 80000ea6: 873e mv a4,a5 + 80000ea8: 86be mv a3,a5 + 80000eaa: 00002617 auipc a2,0x2 + 80000eae: 6d660613 addi a2,a2,1750 # 80003580 + 80000eb2: 00003597 auipc a1,0x3 + 80000eb6: 90e58593 addi a1,a1,-1778 # 800037c0 + 80000eba: 00003517 auipc a0,0x3 + 80000ebe: 8c650513 addi a0,a0,-1850 # 80003780 + 80000ec2: fffff097 auipc ra,0xfffff + 80000ec6: 4e8080e7 jalr 1256(ra) # 800003aa + 80000eca: 4585 li a1,1 + 80000ecc: 4501 li a0,0 + 80000ece: fffff097 auipc ra,0xfffff + 80000ed2: 352080e7 jalr 850(ra) # 80000220 + 80000ed6: 4a01 li s4,0 + 80000ed8: 42100a93 li s5,1057 + 80000edc: 415a307b .insn 4, 0x415a307b + 80000ee0: 4585 li a1,1 + 80000ee2: 852e mv a0,a1 + 80000ee4: fffff097 auipc ra,0xfffff + 80000ee8: 33c080e7 jalr 828(ra) # 80000220 + 80000eec: 4985 li s3,1 + 80000eee: 4159b07b .insn 4, 0x4159b07b + 80000ef2: 4591 li a1,4 + 80000ef4: 4509 li a0,2 + 80000ef6: fffff097 auipc ra,0xfffff + 80000efa: 32a080e7 jalr 810(ra) # 80000220 + 80000efe: 4a89 li s5,2 + 80000f00: 48100793 li a5,1153 + 80000f04: 40fab07b .insn 4, 0x40fab07b + 80000f08: 0000100f fence.i + 80000f0c: 57fd li a5,-1 + 80000f0e: 83e5 srli a5,a5,0x19 + 80000f10: 00f97733 and a4,s2,a5 + 80000f14: 02799613 slli a2,s3,0x27 + 80000f18: 8f51 or a4,a4,a2 + 80000f1a: 02199693 slli a3,s3,0x21 + 80000f1e: 42e6b07b .insn 4, 0x42e6b07b + 80000f22: 0000100f fence.i + 80000f26: 020016b7 lui a3,0x2001 + 80000f2a: 00f4f733 and a4,s1,a5 + 80000f2e: 8f51 or a4,a4,a2 + 80000f30: 06a2 slli a3,a3,0x8 + 80000f32: 42e6b07b .insn 4, 0x42e6b07b + 80000f36: 4681 li a3,0 + 80000f38: 08000713 li a4,128 + 80000f3c: 04e6b07b .insn 4, 0x04e6b07b + 80000f40: 01001737 lui a4,0x1001 + 80000f44: 0726 slli a4,a4,0x9 + 80000f46: 6b37307b .insn 4, 0x6b37307b + 80000f4a: 01001737 lui a4,0x1001 + 80000f4e: 0726 slli a4,a4,0x9 + 80000f50: 40070713 addi a4,a4,1024 # 1001400 <_start-0x7effec00> + 80000f54: 8557307b .insn 4, 0x8557307b + 80000f58: 0000100f fence.i + 80000f5c: 00002717 auipc a4,0x2 + 80000f60: 72470713 addi a4,a4,1828 # 80003680 + 80000f64: 8ff9 and a5,a5,a4 + 80000f66: 020a9713 slli a4,s5,0x20 + 80000f6a: 8fd1 or a5,a5,a2 + 80000f6c: 9756 add a4,a4,s5 + 80000f6e: 20f7307b .insn 4, 0x20f7307b + 80000f72: 00d6b07b .insn 4, 0x00d6b07b + 80000f76: 0330000f fence rw,rw + 80000f7a: 0000100f fence.i + 80000f7e: 4501 li a0,0 + 80000f80: 85ce mv a1,s3 + 80000f82: fffff097 auipc ra,0xfffff + 80000f86: 29e080e7 jalr 670(ra) # 80000220 + 80000f8a: 414a307b .insn 4, 0x414a307b + 80000f8e: 85ce mv a1,s3 + 80000f90: 854e mv a0,s3 + 80000f92: fffff097 auipc ra,0xfffff + 80000f96: 28e080e7 jalr 654(ra) # 80000220 + 80000f9a: 4149b07b .insn 4, 0x4149b07b + 80000f9e: 85ce mv a1,s3 + 80000fa0: 8556 mv a0,s5 + 80000fa2: fffff097 auipc ra,0xfffff + 80000fa6: 27e080e7 jalr 638(ra) # 80000220 + 80000faa: 414ab07b .insn 4, 0x414ab07b + 80000fae: 46a1 li a3,8 + 80000fb0: 00002517 auipc a0,0x2 + 80000fb4: 6d050513 addi a0,a0,1744 # 80003680 + 80000fb8: 8636 mv a2,a3 + 80000fba: 00002597 auipc a1,0x2 + 80000fbe: 5c658593 addi a1,a1,1478 # 80003580 + 80000fc2: fffff097 auipc ra,0xfffff + 80000fc6: 2de080e7 jalr 734(ra) # 800002a0 + 80000fca: e11d bnez a0,80000ff0 + 80000fcc: 00001517 auipc a0,0x1 + 80000fd0: 41450513 addi a0,a0,1044 # 800023e0 + 80000fd4: fffff097 auipc ra,0xfffff + 80000fd8: 286080e7 jalr 646(ra) # 8000025a + 80000fdc: 854e mv a0,s3 + 80000fde: 70e2 ld ra,56(sp) + 80000fe0: 7442 ld s0,48(sp) + 80000fe2: 74a2 ld s1,40(sp) + 80000fe4: 7902 ld s2,32(sp) + 80000fe6: 69e2 ld s3,24(sp) + 80000fe8: 6a42 ld s4,16(sp) + 80000fea: 6aa2 ld s5,8(sp) + 80000fec: 6121 addi sp,sp,64 + 80000fee: 8082 ret + 80000ff0: 00001517 auipc a0,0x1 + 80000ff4: 3c050513 addi a0,a0,960 # 800023b0 + 80000ff8: fffff097 auipc ra,0xfffff + 80000ffc: 262080e7 jalr 610(ra) # 8000025a + 80001000: 4501 li a0,0 + 80001002: bff1 j 80000fde + +0000000080001004 : + 80001004: 715d addi sp,sp,-80 + 80001006: e0a2 sd s0,64(sp) + 80001008: fc26 sd s1,56(sp) + 8000100a: f84a sd s2,48(sp) + 8000100c: e486 sd ra,72(sp) + 8000100e: f44e sd s3,40(sp) + 80001010: f052 sd s4,32(sp) + 80001012: ec56 sd s5,24(sp) + 80001014: e85a sd s6,16(sp) + 80001016: e45e sd s7,8(sp) + 80001018: 0880 addi s0,sp,80 + 8000101a: 00001517 auipc a0,0x1 + 8000101e: 3f650513 addi a0,a0,1014 # 80002410 + 80001022: fffff097 auipc ra,0xfffff + 80001026: 238080e7 jalr 568(ra) # 8000025a + 8000102a: 00003917 auipc s2,0x3 + 8000102e: a9690913 addi s2,s2,-1386 # 80003ac0 + 80001032: 00003497 auipc s1,0x3 + 80001036: a4e48493 addi s1,s1,-1458 # 80003a80 + 8000103a: 2e8ba337 lui t1,0x2e8ba + 8000103e: 4ec4f8b7 lui a7,0x4ec4f + 80001042: 8f4a mv t5,s2 + 80001044: 8ea6 mv t4,s1 + 80001046: 2e930313 addi t1,t1,745 # 2e8ba2e9 <_start-0x51745d17> + 8000104a: c4f88893 addi a7,a7,-945 # 4ec4ec4f <_start-0x313b13b1> + 8000104e: 02800813 li a6,40 + 80001052: 4e01 li t3,0 + 80001054: 04000f93 li t6,64 + 80001058: fd88069b addiw a3,a6,-40 + 8000105c: 8576 mv a0,t4 + 8000105e: 8672 mv a2,t3 + 80001060: 85fa mv a1,t5 + 80001062: 026682b3 mul t0,a3,t1 + 80001066: 02061713 slli a4,a2,0x20 + 8000106a: 9301 srli a4,a4,0x20 + 8000106c: 41f6d79b sraiw a5,a3,0x1f + 80001070: 0505 addi a0,a0,1 + 80001072: 0585 addi a1,a1,1 + 80001074: 03170733 mul a4,a4,a7 + 80001078: 4212d293 srai t0,t0,0x21 + 8000107c: 40f282bb subw t0,t0,a5 + 80001080: 0012979b slliw a5,t0,0x1 + 80001084: 005787bb addw a5,a5,t0 + 80001088: 0027979b slliw a5,a5,0x2 + 8000108c: 405787bb subw a5,a5,t0 + 80001090: 40f687bb subw a5,a3,a5 + 80001094: 37ed addiw a5,a5,-5 + 80001096: fef58fa3 sb a5,-1(a1) + 8000109a: 9309 srli a4,a4,0x22 + 8000109c: 0017179b slliw a5,a4,0x1 + 800010a0: 9fb9 addw a5,a5,a4 + 800010a2: 0027979b slliw a5,a5,0x2 + 800010a6: 9fb9 addw a5,a5,a4 + 800010a8: 40f607bb subw a5,a2,a5 + 800010ac: 37e9 addiw a5,a5,-6 + 800010ae: fef50fa3 sb a5,-1(a0) + 800010b2: 2695 addiw a3,a3,5 # 2001005 <_start-0x7dffeffb> + 800010b4: 2609 addiw a2,a2,2 + 800010b6: fb0696e3 bne a3,a6,80001062 + 800010ba: 0036881b addiw a6,a3,3 + 800010be: 0f21 addi t5,t5,8 + 800010c0: 2e1d addiw t3,t3,7 + 800010c2: 0ea1 addi t4,t4,8 + 800010c4: f9f81ae3 bne a6,t6,80001058 + 800010c8: 47a1 li a5,8 + 800010ca: 873e mv a4,a5 + 800010cc: 86be mv a3,a5 + 800010ce: 00002617 auipc a2,0x2 + 800010d2: 77260613 addi a2,a2,1906 # 80003840 + 800010d6: 00003597 auipc a1,0x3 + 800010da: 9aa58593 addi a1,a1,-1622 # 80003a80 + 800010de: 00003517 auipc a0,0x3 + 800010e2: 9e250513 addi a0,a0,-1566 # 80003ac0 + 800010e6: fffff097 auipc ra,0xfffff + 800010ea: 2c4080e7 jalr 708(ra) # 800003aa + 800010ee: 4585 li a1,1 + 800010f0: 4501 li a0,0 + 800010f2: fffff097 auipc ra,0xfffff + 800010f6: 12e080e7 jalr 302(ra) # 80000220 + 800010fa: 4a01 li s4,0 + 800010fc: 42100b93 li s7,1057 + 80001100: 417a307b .insn 4, 0x417a307b + 80001104: 4585 li a1,1 + 80001106: 852e mv a0,a1 + 80001108: fffff097 auipc ra,0xfffff + 8000110c: 118080e7 jalr 280(ra) # 80000220 + 80001110: 4985 li s3,1 + 80001112: 4179b07b .insn 4, 0x4179b07b + 80001116: 4591 li a1,4 + 80001118: 4509 li a0,2 + 8000111a: fffff097 auipc ra,0xfffff + 8000111e: 106080e7 jalr 262(ra) # 80000220 + 80001122: 4a89 li s5,2 + 80001124: 48100793 li a5,1153 + 80001128: 40fab07b .insn 4, 0x40fab07b + 8000112c: 450d li a0,3 + 8000112e: 85ce mv a1,s3 + 80001130: fffff097 auipc ra,0xfffff + 80001134: 0f0080e7 jalr 240(ra) # 80000220 + 80001138: 4b0d li s6,3 + 8000113a: 417b307b .insn 4, 0x417b307b + 8000113e: 0000100f fence.i + 80001142: 57fd li a5,-1 + 80001144: 83e5 srli a5,a5,0x19 + 80001146: 00f97733 and a4,s2,a5 + 8000114a: 02799693 slli a3,s3,0x27 + 8000114e: 8f55 or a4,a4,a3 + 80001150: 02199613 slli a2,s3,0x21 + 80001154: 42e6307b .insn 4, 0x42e6307b + 80001158: 0000100f fence.i + 8000115c: 02001637 lui a2,0x2001 + 80001160: 00f4f733 and a4,s1,a5 + 80001164: 8f55 or a4,a4,a3 + 80001166: 0622 slli a2,a2,0x8 + 80001168: 42e6307b .insn 4, 0x42e6307b + 8000116c: 0000100f fence.i + 80001170: 00003717 auipc a4,0x3 + 80001174: 8d070713 addi a4,a4,-1840 # 80003a40 + 80001178: 8f7d and a4,a4,a5 + 8000117a: 02003637 lui a2,0x2003 + 8000117e: 8f55 or a4,a4,a3 + 80001180: 0622 slli a2,a2,0x8 + 80001182: 42e6307b .insn 4, 0x42e6307b + 80001186: 4601 li a2,0 + 80001188: 0546307b .insn 4, 0x0546307b + 8000118c: 01001737 lui a4,0x1001 + 80001190: 0726 slli a4,a4,0x9 + 80001192: 975a add a4,a4,s6 + 80001194: 6b37307b .insn 4, 0x6b37307b + 80001198: 01001737 lui a4,0x1001 + 8000119c: 0726 slli a4,a4,0x9 + 8000119e: 40070713 addi a4,a4,1024 # 1001400 <_start-0x7effec00> + 800011a2: 8557307b .insn 4, 0x8557307b + 800011a6: 00002497 auipc s1,0x2 + 800011aa: 79a48493 addi s1,s1,1946 # 80003940 + 800011ae: 0000100f fence.i + 800011b2: 8fe5 and a5,a5,s1 + 800011b4: 020a9713 slli a4,s5,0x20 + 800011b8: 8fd5 or a5,a5,a3 + 800011ba: 9756 add a4,a4,s5 + 800011bc: 20f7307b .insn 4, 0x20f7307b + 800011c0: 00c6307b .insn 4, 0x00c6307b + 800011c4: 0330000f fence rw,rw + 800011c8: 0000100f fence.i + 800011cc: 4501 li a0,0 + 800011ce: 85ce mv a1,s3 + 800011d0: fffff097 auipc ra,0xfffff + 800011d4: 050080e7 jalr 80(ra) # 80000220 + 800011d8: 414a307b .insn 4, 0x414a307b + 800011dc: 85ce mv a1,s3 + 800011de: 854e mv a0,s3 + 800011e0: fffff097 auipc ra,0xfffff + 800011e4: 040080e7 jalr 64(ra) # 80000220 + 800011e8: 4149b07b .insn 4, 0x4149b07b + 800011ec: 85ce mv a1,s3 + 800011ee: 8556 mv a0,s5 + 800011f0: fffff097 auipc ra,0xfffff + 800011f4: 030080e7 jalr 48(ra) # 80000220 + 800011f8: 414ab07b .insn 4, 0x414ab07b + 800011fc: 85ce mv a1,s3 + 800011fe: 855a mv a0,s6 + 80001200: fffff097 auipc ra,0xfffff + 80001204: 020080e7 jalr 32(ra) # 80000220 + 80001208: 414b307b .insn 4, 0x414b307b + 8000120c: 46a1 li a3,8 + 8000120e: 8526 mv a0,s1 + 80001210: 8636 mv a2,a3 + 80001212: 00002597 auipc a1,0x2 + 80001216: 62e58593 addi a1,a1,1582 # 80003840 + 8000121a: fffff097 auipc ra,0xfffff + 8000121e: 086080e7 jalr 134(ra) # 800002a0 + 80001222: e94d bnez a0,800012d4 + 80001224: 00001517 auipc a0,0x1 + 80001228: 23c50513 addi a0,a0,572 # 80002460 + 8000122c: fffff097 auipc ra,0xfffff + 80001230: 02e080e7 jalr 46(ra) # 8000025a + 80001234: 00002917 auipc s2,0x2 + 80001238: 72c90913 addi s2,s2,1836 # 80003960 + 8000123c: 408c lw a1,0(s1) + 8000123e: 00001517 auipc a0,0x1 + 80001242: 23250513 addi a0,a0,562 # 80002470 + 80001246: 0491 addi s1,s1,4 + 80001248: fffff097 auipc ra,0xfffff + 8000124c: 012080e7 jalr 18(ra) # 8000025a + 80001250: ff2496e3 bne s1,s2,8000123c + 80001254: 00001517 auipc a0,0x1 + 80001258: 22450513 addi a0,a0,548 # 80002478 + 8000125c: fffff097 auipc ra,0xfffff + 80001260: ffe080e7 jalr -2(ra) # 8000025a + 80001264: 00001517 auipc a0,0x1 + 80001268: 21c50513 addi a0,a0,540 # 80002480 + 8000126c: fffff097 auipc ra,0xfffff + 80001270: fee080e7 jalr -18(ra) # 8000025a + 80001274: 00002497 auipc s1,0x2 + 80001278: 5cc48493 addi s1,s1,1484 # 80003840 + 8000127c: 00002917 auipc s2,0x2 + 80001280: 5e490913 addi s2,s2,1508 # 80003860 + 80001284: 408c lw a1,0(s1) + 80001286: 00001517 auipc a0,0x1 + 8000128a: 1ea50513 addi a0,a0,490 # 80002470 + 8000128e: 0491 addi s1,s1,4 + 80001290: fffff097 auipc ra,0xfffff + 80001294: fca080e7 jalr -54(ra) # 8000025a + 80001298: fe9916e3 bne s2,s1,80001284 + 8000129c: 00001517 auipc a0,0x1 + 800012a0: 1dc50513 addi a0,a0,476 # 80002478 + 800012a4: fffff097 auipc ra,0xfffff + 800012a8: fb6080e7 jalr -74(ra) # 8000025a + 800012ac: 00001517 auipc a0,0x1 + 800012b0: 1e450513 addi a0,a0,484 # 80002490 + 800012b4: fffff097 auipc ra,0xfffff + 800012b8: fa6080e7 jalr -90(ra) # 8000025a + 800012bc: 4505 li a0,1 + 800012be: 60a6 ld ra,72(sp) + 800012c0: 6406 ld s0,64(sp) + 800012c2: 74e2 ld s1,56(sp) + 800012c4: 7942 ld s2,48(sp) + 800012c6: 79a2 ld s3,40(sp) + 800012c8: 7a02 ld s4,32(sp) + 800012ca: 6ae2 ld s5,24(sp) + 800012cc: 6b42 ld s6,16(sp) + 800012ce: 6ba2 ld s7,8(sp) + 800012d0: 6161 addi sp,sp,80 + 800012d2: 8082 ret + 800012d4: 00001517 auipc a0,0x1 + 800012d8: 16450513 addi a0,a0,356 # 80002438 + 800012dc: fffff097 auipc ra,0xfffff + 800012e0: f7e080e7 jalr -130(ra) # 8000025a + 800012e4: 4501 li a0,0 + 800012e6: bfe1 j 800012be + +00000000800012e8 : + 800012e8: 7139 addi sp,sp,-64 + 800012ea: f822 sd s0,48(sp) + 800012ec: f426 sd s1,40(sp) + 800012ee: f04a sd s2,32(sp) + 800012f0: fc06 sd ra,56(sp) + 800012f2: ec4e sd s3,24(sp) + 800012f4: e852 sd s4,16(sp) + 800012f6: e456 sd s5,8(sp) + 800012f8: 0080 addi s0,sp,64 + 800012fa: 00001517 auipc a0,0x1 + 800012fe: 1be50513 addi a0,a0,446 # 800024b8 + 80001302: fffff097 auipc ra,0xfffff + 80001306: f58080e7 jalr -168(ra) # 8000025a + 8000130a: 00003917 auipc s2,0x3 + 8000130e: a7690913 addi s2,s2,-1418 # 80003d80 + 80001312: 00003497 auipc s1,0x3 + 80001316: a2e48493 addi s1,s1,-1490 # 80003d40 + 8000131a: 2e8ba337 lui t1,0x2e8ba + 8000131e: 4ec4f8b7 lui a7,0x4ec4f + 80001322: 8f4a mv t5,s2 + 80001324: 8ea6 mv t4,s1 + 80001326: 2e930313 addi t1,t1,745 # 2e8ba2e9 <_start-0x51745d17> + 8000132a: c4f88893 addi a7,a7,-945 # 4ec4ec4f <_start-0x313b13b1> + 8000132e: 02800813 li a6,40 + 80001332: 4e01 li t3,0 + 80001334: 04000f93 li t6,64 + 80001338: fd88069b addiw a3,a6,-40 + 8000133c: 8576 mv a0,t4 + 8000133e: 8672 mv a2,t3 + 80001340: 85fa mv a1,t5 + 80001342: 026682b3 mul t0,a3,t1 + 80001346: 02061713 slli a4,a2,0x20 + 8000134a: 9301 srli a4,a4,0x20 + 8000134c: 41f6d79b sraiw a5,a3,0x1f + 80001350: 0505 addi a0,a0,1 + 80001352: 0585 addi a1,a1,1 + 80001354: 03170733 mul a4,a4,a7 + 80001358: 4212d293 srai t0,t0,0x21 + 8000135c: 40f282bb subw t0,t0,a5 + 80001360: 0012979b slliw a5,t0,0x1 + 80001364: 005787bb addw a5,a5,t0 + 80001368: 0027979b slliw a5,a5,0x2 + 8000136c: 405787bb subw a5,a5,t0 + 80001370: 40f687bb subw a5,a3,a5 + 80001374: 37ed addiw a5,a5,-5 + 80001376: fef58fa3 sb a5,-1(a1) + 8000137a: 9309 srli a4,a4,0x22 + 8000137c: 0017179b slliw a5,a4,0x1 + 80001380: 9fb9 addw a5,a5,a4 + 80001382: 0027979b slliw a5,a5,0x2 + 80001386: 9fb9 addw a5,a5,a4 + 80001388: 40f607bb subw a5,a2,a5 + 8000138c: 37e9 addiw a5,a5,-6 + 8000138e: fef50fa3 sb a5,-1(a0) + 80001392: 2695 addiw a3,a3,5 + 80001394: 2609 addiw a2,a2,2 # 2003002 <_start-0x7dffcffe> + 80001396: fb0696e3 bne a3,a6,80001342 + 8000139a: 0036881b addiw a6,a3,3 + 8000139e: 0f21 addi t5,t5,8 + 800013a0: 2e1d addiw t3,t3,7 + 800013a2: 0ea1 addi t4,t4,8 + 800013a4: f9f81ae3 bne a6,t6,80001338 + 800013a8: 46a1 li a3,8 + 800013aa: 8636 mv a2,a3 + 800013ac: 00003597 auipc a1,0x3 + 800013b0: 95458593 addi a1,a1,-1708 # 80003d00 + 800013b4: 00003517 auipc a0,0x3 + 800013b8: 98c50513 addi a0,a0,-1652 # 80003d40 + 800013bc: fffff097 auipc ra,0xfffff + 800013c0: f46080e7 jalr -186(ra) # 80000302 + 800013c4: 47a1 li a5,8 + 800013c6: 873e mv a4,a5 + 800013c8: 86be mv a3,a5 + 800013ca: 00002617 auipc a2,0x2 + 800013ce: 73660613 addi a2,a2,1846 # 80003b00 + 800013d2: 00003597 auipc a1,0x3 + 800013d6: 92e58593 addi a1,a1,-1746 # 80003d00 + 800013da: 00003517 auipc a0,0x3 + 800013de: 9a650513 addi a0,a0,-1626 # 80003d80 + 800013e2: fffff097 auipc ra,0xfffff + 800013e6: fc8080e7 jalr -56(ra) # 800003aa + 800013ea: 4585 li a1,1 + 800013ec: 4501 li a0,0 + 800013ee: fffff097 auipc ra,0xfffff + 800013f2: e32080e7 jalr -462(ra) # 80000220 + 800013f6: 4a01 li s4,0 + 800013f8: 42100a93 li s5,1057 + 800013fc: 415a307b .insn 4, 0x415a307b + 80001400: 4585 li a1,1 + 80001402: 852e mv a0,a1 + 80001404: fffff097 auipc ra,0xfffff + 80001408: e1c080e7 jalr -484(ra) # 80000220 + 8000140c: 4985 li s3,1 + 8000140e: 4159b07b .insn 4, 0x4159b07b + 80001412: 4591 li a1,4 + 80001414: 4509 li a0,2 + 80001416: fffff097 auipc ra,0xfffff + 8000141a: e0a080e7 jalr -502(ra) # 80000220 + 8000141e: 4a89 li s5,2 + 80001420: 48100793 li a5,1153 + 80001424: 40fab07b .insn 4, 0x40fab07b + 80001428: 0000100f fence.i + 8000142c: 57fd li a5,-1 + 8000142e: 83e5 srli a5,a5,0x19 + 80001430: 00f97733 and a4,s2,a5 + 80001434: 02799613 slli a2,s3,0x27 + 80001438: 8f51 or a4,a4,a2 + 8000143a: 02199693 slli a3,s3,0x21 + 8000143e: 42e6b07b .insn 4, 0x42e6b07b + 80001442: 0000100f fence.i + 80001446: 020016b7 lui a3,0x2001 + 8000144a: 00f4f733 and a4,s1,a5 + 8000144e: 8f51 or a4,a4,a2 + 80001450: 06a2 slli a3,a3,0x8 + 80001452: 42e6b07b .insn 4, 0x42e6b07b + 80001456: 4681 li a3,0 + 80001458: 10000713 li a4,256 + 8000145c: 04e6b07b .insn 4, 0x04e6b07b + 80001460: 01001737 lui a4,0x1001 + 80001464: 0726 slli a4,a4,0x9 + 80001466: 6b37307b .insn 4, 0x6b37307b + 8000146a: 01001737 lui a4,0x1001 + 8000146e: 0726 slli a4,a4,0x9 + 80001470: 40070713 addi a4,a4,1024 # 1001400 <_start-0x7effec00> + 80001474: 8557307b .insn 4, 0x8557307b + 80001478: 0000100f fence.i + 8000147c: 00002717 auipc a4,0x2 + 80001480: 78470713 addi a4,a4,1924 # 80003c00 + 80001484: 8ff9 and a5,a5,a4 + 80001486: 020a9713 slli a4,s5,0x20 + 8000148a: 8fd1 or a5,a5,a2 + 8000148c: 9756 add a4,a4,s5 + 8000148e: 20f7307b .insn 4, 0x20f7307b + 80001492: 00d6b07b .insn 4, 0x00d6b07b + 80001496: 0330000f fence rw,rw + 8000149a: 0000100f fence.i + 8000149e: 4501 li a0,0 + 800014a0: 85ce mv a1,s3 + 800014a2: fffff097 auipc ra,0xfffff + 800014a6: d7e080e7 jalr -642(ra) # 80000220 + 800014aa: 414a307b .insn 4, 0x414a307b + 800014ae: 85ce mv a1,s3 + 800014b0: 854e mv a0,s3 + 800014b2: fffff097 auipc ra,0xfffff + 800014b6: d6e080e7 jalr -658(ra) # 80000220 + 800014ba: 4149b07b .insn 4, 0x4149b07b + 800014be: 85ce mv a1,s3 + 800014c0: 8556 mv a0,s5 + 800014c2: fffff097 auipc ra,0xfffff + 800014c6: d5e080e7 jalr -674(ra) # 80000220 + 800014ca: 414ab07b .insn 4, 0x414ab07b + 800014ce: 46a1 li a3,8 + 800014d0: 00002517 auipc a0,0x2 + 800014d4: 73050513 addi a0,a0,1840 # 80003c00 + 800014d8: 8636 mv a2,a3 + 800014da: 00002597 auipc a1,0x2 + 800014de: 62658593 addi a1,a1,1574 # 80003b00 + 800014e2: fffff097 auipc ra,0xfffff + 800014e6: dbe080e7 jalr -578(ra) # 800002a0 + 800014ea: e11d bnez a0,80001510 + 800014ec: 00001517 auipc a0,0x1 + 800014f0: 02c50513 addi a0,a0,44 # 80002518 + 800014f4: fffff097 auipc ra,0xfffff + 800014f8: d66080e7 jalr -666(ra) # 8000025a + 800014fc: 854e mv a0,s3 + 800014fe: 70e2 ld ra,56(sp) + 80001500: 7442 ld s0,48(sp) + 80001502: 74a2 ld s1,40(sp) + 80001504: 7902 ld s2,32(sp) + 80001506: 69e2 ld s3,24(sp) + 80001508: 6a42 ld s4,16(sp) + 8000150a: 6aa2 ld s5,8(sp) + 8000150c: 6121 addi sp,sp,64 + 8000150e: 8082 ret + 80001510: 00001517 auipc a0,0x1 + 80001514: fd850513 addi a0,a0,-40 # 800024e8 + 80001518: fffff097 auipc ra,0xfffff + 8000151c: d42080e7 jalr -702(ra) # 8000025a + 80001520: 4501 li a0,0 + 80001522: bff1 j 800014fe + +0000000080001524 : + 80001524: 7139 addi sp,sp,-64 + 80001526: f822 sd s0,48(sp) + 80001528: f426 sd s1,40(sp) + 8000152a: f04a sd s2,32(sp) + 8000152c: fc06 sd ra,56(sp) + 8000152e: ec4e sd s3,24(sp) + 80001530: e852 sd s4,16(sp) + 80001532: e456 sd s5,8(sp) + 80001534: 0080 addi s0,sp,64 + 80001536: 00001517 auipc a0,0x1 + 8000153a: 01250513 addi a0,a0,18 # 80002548 + 8000153e: fffff097 auipc ra,0xfffff + 80001542: d1c080e7 jalr -740(ra) # 8000025a + 80001546: 00003917 auipc s2,0x3 + 8000154a: aba90913 addi s2,s2,-1350 # 80004000 + 8000154e: 00003497 auipc s1,0x3 + 80001552: a7248493 addi s1,s1,-1422 # 80003fc0 + 80001556: 2e8ba337 lui t1,0x2e8ba + 8000155a: 4ec4f8b7 lui a7,0x4ec4f + 8000155e: 8f4a mv t5,s2 + 80001560: 8ea6 mv t4,s1 + 80001562: 2e930313 addi t1,t1,745 # 2e8ba2e9 <_start-0x51745d17> + 80001566: c4f88893 addi a7,a7,-945 # 4ec4ec4f <_start-0x313b13b1> + 8000156a: 02800813 li a6,40 + 8000156e: 4e01 li t3,0 + 80001570: 04000f93 li t6,64 + 80001574: fd88069b addiw a3,a6,-40 + 80001578: 8576 mv a0,t4 + 8000157a: 8672 mv a2,t3 + 8000157c: 85fa mv a1,t5 + 8000157e: 026682b3 mul t0,a3,t1 + 80001582: 02061713 slli a4,a2,0x20 + 80001586: 9301 srli a4,a4,0x20 + 80001588: 41f6d79b sraiw a5,a3,0x1f + 8000158c: 0505 addi a0,a0,1 + 8000158e: 0585 addi a1,a1,1 + 80001590: 03170733 mul a4,a4,a7 + 80001594: 4212d293 srai t0,t0,0x21 + 80001598: 40f282bb subw t0,t0,a5 + 8000159c: 0012979b slliw a5,t0,0x1 + 800015a0: 005787bb addw a5,a5,t0 + 800015a4: 0027979b slliw a5,a5,0x2 + 800015a8: 405787bb subw a5,a5,t0 + 800015ac: 40f687bb subw a5,a3,a5 + 800015b0: 37ed addiw a5,a5,-5 + 800015b2: fef58fa3 sb a5,-1(a1) + 800015b6: 9309 srli a4,a4,0x22 + 800015b8: 0017179b slliw a5,a4,0x1 + 800015bc: 9fb9 addw a5,a5,a4 + 800015be: 0027979b slliw a5,a5,0x2 + 800015c2: 9fb9 addw a5,a5,a4 + 800015c4: 40f607bb subw a5,a2,a5 + 800015c8: 37e9 addiw a5,a5,-6 + 800015ca: fef50fa3 sb a5,-1(a0) + 800015ce: 2695 addiw a3,a3,5 # 2001005 <_start-0x7dffeffb> + 800015d0: 2609 addiw a2,a2,2 + 800015d2: fb0696e3 bne a3,a6,8000157e + 800015d6: 0036881b addiw a6,a3,3 + 800015da: 0f21 addi t5,t5,8 + 800015dc: 2e1d addiw t3,t3,7 + 800015de: 0ea1 addi t4,t4,8 + 800015e0: f9f81ae3 bne a6,t6,80001574 + 800015e4: 47a1 li a5,8 + 800015e6: 873e mv a4,a5 + 800015e8: 86be mv a3,a5 + 800015ea: 00002617 auipc a2,0x2 + 800015ee: 7d660613 addi a2,a2,2006 # 80003dc0 + 800015f2: 00003597 auipc a1,0x3 + 800015f6: 9ce58593 addi a1,a1,-1586 # 80003fc0 + 800015fa: 00003517 auipc a0,0x3 + 800015fe: a0650513 addi a0,a0,-1530 # 80004000 + 80001602: fffff097 auipc ra,0xfffff + 80001606: da8080e7 jalr -600(ra) # 800003aa + 8000160a: 00002997 auipc s3,0x2 + 8000160e: 7b698993 addi s3,s3,1974 # 80003dc0 + 80001612: 00003a17 auipc s4,0x3 + 80001616: 8aea0a13 addi s4,s4,-1874 # 80003ec0 + 8000161a: 0009a503 lw a0,0(s3) + 8000161e: 4591 li a1,4 + 80001620: 0991 addi s3,s3,4 + 80001622: fffff097 auipc ra,0xfffff + 80001626: d38080e7 jalr -712(ra) # 8000035a + 8000162a: fea9ae23 sw a0,-4(s3) + 8000162e: ff3a16e3 bne s4,s3,8000161a + 80001632: 4585 li a1,1 + 80001634: 4501 li a0,0 + 80001636: fffff097 auipc ra,0xfffff + 8000163a: bea080e7 jalr -1046(ra) # 80000220 + 8000163e: 4a01 li s4,0 + 80001640: 42100a93 li s5,1057 + 80001644: 415a307b .insn 4, 0x415a307b + 80001648: 4585 li a1,1 + 8000164a: 852e mv a0,a1 + 8000164c: fffff097 auipc ra,0xfffff + 80001650: bd4080e7 jalr -1068(ra) # 80000220 + 80001654: 4985 li s3,1 + 80001656: 4159b07b .insn 4, 0x4159b07b + 8000165a: 4591 li a1,4 + 8000165c: 4509 li a0,2 + 8000165e: fffff097 auipc ra,0xfffff + 80001662: bc2080e7 jalr -1086(ra) # 80000220 + 80001666: 4a89 li s5,2 + 80001668: 48100793 li a5,1153 + 8000166c: 40fab07b .insn 4, 0x40fab07b + 80001670: 0000100f fence.i + 80001674: 57fd li a5,-1 + 80001676: 83e5 srli a5,a5,0x19 + 80001678: 00f97733 and a4,s2,a5 + 8000167c: 02799613 slli a2,s3,0x27 + 80001680: 8f51 or a4,a4,a2 + 80001682: 02199693 slli a3,s3,0x21 + 80001686: 42e6b07b .insn 4, 0x42e6b07b + 8000168a: 0000100f fence.i + 8000168e: 020016b7 lui a3,0x2001 + 80001692: 00f4f733 and a4,s1,a5 + 80001696: 8f51 or a4,a4,a2 + 80001698: 06a2 slli a3,a3,0x8 + 8000169a: 42e6b07b .insn 4, 0x42e6b07b + 8000169e: 6705 lui a4,0x1 + 800016a0: 80070713 addi a4,a4,-2048 # 800 <_start-0x7ffff800> + 800016a4: 4681 li a3,0 + 800016a6: 04e6b07b .insn 4, 0x04e6b07b + 800016aa: 01001737 lui a4,0x1001 + 800016ae: 0726 slli a4,a4,0x9 + 800016b0: 6b37307b .insn 4, 0x6b37307b + 800016b4: 01001737 lui a4,0x1001 + 800016b8: 0726 slli a4,a4,0x9 + 800016ba: 40070713 addi a4,a4,1024 # 1001400 <_start-0x7effec00> + 800016be: 8557307b .insn 4, 0x8557307b + 800016c2: 0000100f fence.i + 800016c6: 00002717 auipc a4,0x2 + 800016ca: 7fa70713 addi a4,a4,2042 # 80003ec0 + 800016ce: 8ff9 and a5,a5,a4 + 800016d0: 020a9713 slli a4,s5,0x20 + 800016d4: 8fd1 or a5,a5,a2 + 800016d6: 9756 add a4,a4,s5 + 800016d8: 20f7307b .insn 4, 0x20f7307b + 800016dc: 00d6b07b .insn 4, 0x00d6b07b + 800016e0: 0330000f fence rw,rw + 800016e4: 0000100f fence.i + 800016e8: 4501 li a0,0 + 800016ea: 85ce mv a1,s3 + 800016ec: fffff097 auipc ra,0xfffff + 800016f0: b34080e7 jalr -1228(ra) # 80000220 + 800016f4: 414a307b .insn 4, 0x414a307b + 800016f8: 85ce mv a1,s3 + 800016fa: 854e mv a0,s3 + 800016fc: fffff097 auipc ra,0xfffff + 80001700: b24080e7 jalr -1244(ra) # 80000220 + 80001704: 4149b07b .insn 4, 0x4149b07b + 80001708: 85ce mv a1,s3 + 8000170a: 8556 mv a0,s5 + 8000170c: fffff097 auipc ra,0xfffff + 80001710: b14080e7 jalr -1260(ra) # 80000220 + 80001714: 414ab07b .insn 4, 0x414ab07b + 80001718: 46a1 li a3,8 + 8000171a: 00002517 auipc a0,0x2 + 8000171e: 7a650513 addi a0,a0,1958 # 80003ec0 + 80001722: 8636 mv a2,a3 + 80001724: 00002597 auipc a1,0x2 + 80001728: 69c58593 addi a1,a1,1692 # 80003dc0 + 8000172c: fffff097 auipc ra,0xfffff + 80001730: b74080e7 jalr -1164(ra) # 800002a0 + 80001734: e11d bnez a0,8000175a + 80001736: 00001517 auipc a0,0x1 + 8000173a: e6250513 addi a0,a0,-414 # 80002598 + 8000173e: fffff097 auipc ra,0xfffff + 80001742: b1c080e7 jalr -1252(ra) # 8000025a + 80001746: 854e mv a0,s3 + 80001748: 70e2 ld ra,56(sp) + 8000174a: 7442 ld s0,48(sp) + 8000174c: 74a2 ld s1,40(sp) + 8000174e: 7902 ld s2,32(sp) + 80001750: 69e2 ld s3,24(sp) + 80001752: 6a42 ld s4,16(sp) + 80001754: 6aa2 ld s5,8(sp) + 80001756: 6121 addi sp,sp,64 + 80001758: 8082 ret + 8000175a: 00001517 auipc a0,0x1 + 8000175e: e1650513 addi a0,a0,-490 # 80002570 + 80001762: fffff097 auipc ra,0xfffff + 80001766: af8080e7 jalr -1288(ra) # 8000025a + 8000176a: 4501 li a0,0 + 8000176c: bff1 j 80001748 + +000000008000176e : + 8000176e: 7179 addi sp,sp,-48 + 80001770: f022 sd s0,32(sp) + 80001772: ec26 sd s1,24(sp) + 80001774: e84a sd s2,16(sp) + 80001776: f406 sd ra,40(sp) + 80001778: 1800 addi s0,sp,48 + 8000177a: 00001517 auipc a0,0x1 + 8000177e: e4650513 addi a0,a0,-442 # 800025c0 + 80001782: fffff097 auipc ra,0xfffff + 80001786: ad8080e7 jalr -1320(ra) # 8000025a + 8000178a: 00003917 auipc s2,0x3 + 8000178e: 97690913 addi s2,s2,-1674 # 80004100 + 80001792: 00003497 auipc s1,0x3 + 80001796: 92e48493 addi s1,s1,-1746 # 800040c0 + 8000179a: 92492e37 lui t3,0x92492 + 8000179e: 66666737 lui a4,0x66666 + 800017a2: 834a mv t1,s2 + 800017a4: 88a6 mv a7,s1 + 800017a6: 493e0e13 addi t3,t3,1171 # ffffffff92492493 + 800017aa: 66770713 addi a4,a4,1639 # 66666667 <_start-0x19999999> + 800017ae: 4861 li a6,24 + 800017b0: 4781 li a5,0 + 800017b2: 4ea1 li t4,8 + 800017b4: 03c786b3 mul a3,a5,t3 + 800017b8: 41f7d61b sraiw a2,a5,0x1f + 800017bc: 0017959b slliw a1,a5,0x1 + 800017c0: 8546 mv a0,a7 + 800017c2: 9281 srli a3,a3,0x20 + 800017c4: 9ebd addw a3,a3,a5 + 800017c6: 4026d69b sraiw a3,a3,0x2 + 800017ca: 9e91 subw a3,a3,a2 + 800017cc: 0036961b slliw a2,a3,0x3 + 800017d0: 40d606bb subw a3,a2,a3 + 800017d4: 40d786bb subw a3,a5,a3 + 800017d8: 36f5 addiw a3,a3,-3 # 2000ffd <_start-0x7dfff003> + 800017da: 00d30023 sb a3,0(t1) + 800017de: 02e58633 mul a2,a1,a4 + 800017e2: 41f5d69b sraiw a3,a1,0x1f + 800017e6: 0505 addi a0,a0,1 + 800017e8: 9605 srai a2,a2,0x21 + 800017ea: 9e15 subw a2,a2,a3 + 800017ec: 0026169b slliw a3,a2,0x2 + 800017f0: 9eb1 addw a3,a3,a2 + 800017f2: 40d586bb subw a3,a1,a3 + 800017f6: 36f9 addiw a3,a3,-2 + 800017f8: fed50fa3 sb a3,-1(a0) + 800017fc: 258d addiw a1,a1,3 + 800017fe: ff0590e3 bne a1,a6,800017de + 80001802: 2785 addiw a5,a5,1 + 80001804: 0305 addi t1,t1,1 + 80001806: 08a1 addi a7,a7,8 + 80001808: 0025881b addiw a6,a1,2 + 8000180c: fbd794e3 bne a5,t4,800017b4 + 80001810: 873e mv a4,a5 + 80001812: 4685 li a3,1 + 80001814: 00003617 auipc a2,0x3 + 80001818: 82c60613 addi a2,a2,-2004 # 80004040 + 8000181c: 00003597 auipc a1,0x3 + 80001820: 8a458593 addi a1,a1,-1884 # 800040c0 + 80001824: 00003517 auipc a0,0x3 + 80001828: 8dc50513 addi a0,a0,-1828 # 80004100 + 8000182c: fcf43c23 sd a5,-40(s0) + 80001830: fffff097 auipc ra,0xfffff + 80001834: b7a080e7 jalr -1158(ra) # 800003aa + 80001838: 4701 li a4,0 + 8000183a: 46c1 li a3,16 + 8000183c: 04d7307b .insn 4, 0x04d7307b + 80001840: 000806b7 lui a3,0x80 + 80001844: 0685 addi a3,a3,1 # 80001 <_start-0x7ff7ffff> + 80001846: 06c2 slli a3,a3,0x10 + 80001848: 0685 addi a3,a3,1 + 8000184a: c0d7307b .insn 4, 0xc0d7307b + 8000184e: 100016b7 lui a3,0x10001 + 80001852: 0692 slli a3,a3,0x4 + 80001854: 06a1 addi a3,a3,8 # 10001008 <_start-0x6fffeff8> + 80001856: c2d7307b .insn 4, 0xc2d7307b + 8000185a: 4785 li a5,1 + 8000185c: c4f7307b .insn 4, 0xc4f7307b + 80001860: 4681 li a3,0 + 80001862: c6d7307b .insn 4, 0xc6d7307b + 80001866: 56fd li a3,-1 + 80001868: 82e5 srli a3,a3,0x19 + 8000186a: 00d97933 and s2,s2,a3 + 8000186e: c927307b .insn 4, 0xc927307b + 80001872: 8cf5 and s1,s1,a3 + 80001874: ca97307b .insn 4, 0xca97307b + 80001878: 00003797 auipc a5,0x3 + 8000187c: 80878793 addi a5,a5,-2040 # 80004080 + 80001880: 8efd and a3,a3,a5 + 80001882: ccd7307b .insn 4, 0xccd7307b + 80001886: 4685 li a3,1 + 80001888: 169a slli a3,a3,0x26 + 8000188a: 06a1 addi a3,a3,8 + 8000188c: ced7307b .insn 4, 0xced7307b + 80001890: 02000693 li a3,32 + 80001894: d0d7307b .insn 4, 0xd0d7307b + 80001898: 402006b7 lui a3,0x40200 + 8000189c: 40068693 addi a3,a3,1024 # 40200400 <_start-0x3fdffc00> + 800018a0: d2d7307b .insn 4, 0xd2d7307b + 800018a4: 00e7307b .insn 4, 0x00e7307b + 800018a8: 0330000f fence rw,rw + 800018ac: 0000100f fence.i + 800018b0: fd843683 ld a3,-40(s0) + 800018b4: 00002597 auipc a1,0x2 + 800018b8: 78c58593 addi a1,a1,1932 # 80004040 + 800018bc: 00002517 auipc a0,0x2 + 800018c0: 7c450513 addi a0,a0,1988 # 80004080 + 800018c4: 4605 li a2,1 + 800018c6: fffff097 auipc ra,0xfffff + 800018ca: 9da080e7 jalr -1574(ra) # 800002a0 + 800018ce: e105 bnez a0,800018ee + 800018d0: 00001517 auipc a0,0x1 + 800018d4: d4050513 addi a0,a0,-704 # 80002610 + 800018d8: fffff097 auipc ra,0xfffff + 800018dc: 982080e7 jalr -1662(ra) # 8000025a + 800018e0: 70a2 ld ra,40(sp) + 800018e2: 7402 ld s0,32(sp) + 800018e4: 64e2 ld s1,24(sp) + 800018e6: 6942 ld s2,16(sp) + 800018e8: 4505 li a0,1 + 800018ea: 6145 addi sp,sp,48 + 800018ec: 8082 ret + 800018ee: 00001517 auipc a0,0x1 + 800018f2: cfa50513 addi a0,a0,-774 # 800025e8 + 800018f6: fffff097 auipc ra,0xfffff + 800018fa: 964080e7 jalr -1692(ra) # 8000025a + 800018fe: 70a2 ld ra,40(sp) + 80001900: 7402 ld s0,32(sp) + 80001902: 64e2 ld s1,24(sp) + 80001904: 6942 ld s2,16(sp) + 80001906: 4501 li a0,0 + 80001908: 6145 addi sp,sp,48 + 8000190a: 8082 ret + +000000008000190c : + 8000190c: 7139 addi sp,sp,-64 + 8000190e: f822 sd s0,48(sp) + 80001910: f426 sd s1,40(sp) + 80001912: f04a sd s2,32(sp) + 80001914: fc06 sd ra,56(sp) + 80001916: ec4e sd s3,24(sp) + 80001918: e852 sd s4,16(sp) + 8000191a: e456 sd s5,8(sp) + 8000191c: e05a sd s6,0(sp) + 8000191e: 0080 addi s0,sp,64 + 80001920: 00001517 auipc a0,0x1 + 80001924: d1850513 addi a0,a0,-744 # 80002638 + 80001928: fffff097 auipc ra,0xfffff + 8000192c: 932080e7 jalr -1742(ra) # 8000025a + 80001930: 00003497 auipc s1,0x3 + 80001934: a9048493 addi s1,s1,-1392 # 800043c0 + 80001938: 00003917 auipc s2,0x3 + 8000193c: a4890913 addi s2,s2,-1464 # 80004380 + 80001940: 2e8ba337 lui t1,0x2e8ba + 80001944: 4ec4f8b7 lui a7,0x4ec4f + 80001948: 8f26 mv t5,s1 + 8000194a: 8eca mv t4,s2 + 8000194c: 2e930313 addi t1,t1,745 # 2e8ba2e9 <_start-0x51745d17> + 80001950: c4f88893 addi a7,a7,-945 # 4ec4ec4f <_start-0x313b13b1> + 80001954: 02800813 li a6,40 + 80001958: 4e01 li t3,0 + 8000195a: 04000f93 li t6,64 + 8000195e: fd88069b addiw a3,a6,-40 + 80001962: 8576 mv a0,t4 + 80001964: 8672 mv a2,t3 + 80001966: 85fa mv a1,t5 + 80001968: 026682b3 mul t0,a3,t1 + 8000196c: 02061713 slli a4,a2,0x20 + 80001970: 9301 srli a4,a4,0x20 + 80001972: 41f6d79b sraiw a5,a3,0x1f + 80001976: 0505 addi a0,a0,1 + 80001978: 0585 addi a1,a1,1 + 8000197a: 03170733 mul a4,a4,a7 + 8000197e: 4212d293 srai t0,t0,0x21 + 80001982: 40f282bb subw t0,t0,a5 + 80001986: 0012979b slliw a5,t0,0x1 + 8000198a: 005787bb addw a5,a5,t0 + 8000198e: 0027979b slliw a5,a5,0x2 + 80001992: 405787bb subw a5,a5,t0 + 80001996: 40f687bb subw a5,a3,a5 + 8000199a: 37ed addiw a5,a5,-5 + 8000199c: fef58fa3 sb a5,-1(a1) + 800019a0: 9309 srli a4,a4,0x22 + 800019a2: 0017179b slliw a5,a4,0x1 + 800019a6: 9fb9 addw a5,a5,a4 + 800019a8: 0027979b slliw a5,a5,0x2 + 800019ac: 9fb9 addw a5,a5,a4 + 800019ae: 40f607bb subw a5,a2,a5 + 800019b2: 37e9 addiw a5,a5,-6 + 800019b4: fef50fa3 sb a5,-1(a0) + 800019b8: 2695 addiw a3,a3,5 + 800019ba: 2609 addiw a2,a2,2 + 800019bc: fb0696e3 bne a3,a6,80001968 + 800019c0: 0036881b addiw a6,a3,3 + 800019c4: 0f21 addi t5,t5,8 + 800019c6: 2e1d addiw t3,t3,7 + 800019c8: 0ea1 addi t4,t4,8 + 800019ca: f9f81ae3 bne a6,t6,8000195e + 800019ce: 4621 li a2,8 + 800019d0: 85b2 mv a1,a2 + 800019d2: 00003517 auipc a0,0x3 + 800019d6: 96e50513 addi a0,a0,-1682 # 80004340 + 800019da: fffff097 auipc ra,0xfffff + 800019de: 90c080e7 jalr -1780(ra) # 800002e6 + 800019e2: 47a1 li a5,8 + 800019e4: 873e mv a4,a5 + 800019e6: 86be mv a3,a5 + 800019e8: 00002617 auipc a2,0x2 + 800019ec: 75860613 addi a2,a2,1880 # 80004140 + 800019f0: 00003597 auipc a1,0x3 + 800019f4: 99058593 addi a1,a1,-1648 # 80004380 + 800019f8: 00003517 auipc a0,0x3 + 800019fc: 9c850513 addi a0,a0,-1592 # 800043c0 + 80001a00: fffff097 auipc ra,0xfffff + 80001a04: 9aa080e7 jalr -1622(ra) # 800003aa + 80001a08: 4585 li a1,1 + 80001a0a: 4501 li a0,0 + 80001a0c: fffff097 auipc ra,0xfffff + 80001a10: 814080e7 jalr -2028(ra) # 80000220 + 80001a14: 4a01 li s4,0 + 80001a16: 42100b13 li s6,1057 + 80001a1a: 416a307b .insn 4, 0x416a307b + 80001a1e: 4585 li a1,1 + 80001a20: 852e mv a0,a1 + 80001a22: ffffe097 auipc ra,0xffffe + 80001a26: 7fe080e7 jalr 2046(ra) # 80000220 + 80001a2a: 4985 li s3,1 + 80001a2c: 4169b07b .insn 4, 0x4169b07b + 80001a30: 4509 li a0,2 + 80001a32: 85ce mv a1,s3 + 80001a34: ffffe097 auipc ra,0xffffe + 80001a38: 7ec080e7 jalr 2028(ra) # 80000220 + 80001a3c: 4a89 li s5,2 + 80001a3e: 416ab07b .insn 4, 0x416ab07b + 80001a42: 4591 li a1,4 + 80001a44: 450d li a0,3 + 80001a46: ffffe097 auipc ra,0xffffe + 80001a4a: 7da080e7 jalr 2010(ra) # 80000220 + 80001a4e: 4b0d li s6,3 + 80001a50: 48100793 li a5,1153 + 80001a54: 40fb307b .insn 4, 0x40fb307b + 80001a58: 0000100f fence.i + 80001a5c: 57fd li a5,-1 + 80001a5e: 83e5 srli a5,a5,0x19 + 80001a60: 00f97733 and a4,s2,a5 + 80001a64: 02799693 slli a3,s3,0x27 + 80001a68: 8f55 or a4,a4,a3 + 80001a6a: 02199613 slli a2,s3,0x21 + 80001a6e: 42e6307b .insn 4, 0x42e6307b + 80001a72: 0000100f fence.i + 80001a76: 02001637 lui a2,0x2001 + 80001a7a: 00f4f733 and a4,s1,a5 + 80001a7e: 8f55 or a4,a4,a3 + 80001a80: 0622 slli a2,a2,0x8 + 80001a82: 42e6307b .insn 4, 0x42e6307b + 80001a86: 0000100f fence.i + 80001a8a: 00003717 auipc a4,0x3 + 80001a8e: 8b670713 addi a4,a4,-1866 # 80004340 + 80001a92: 8f7d and a4,a4,a5 + 80001a94: 01001637 lui a2,0x1001 + 80001a98: 8f55 or a4,a4,a3 + 80001a9a: 0626 slli a2,a2,0x9 + 80001a9c: 42e6307b .insn 4, 0x42e6307b + 80001aa0: 4601 li a2,0 + 80001aa2: 4741 li a4,16 + 80001aa4: 04e6307b .insn 4, 0x04e6307b + 80001aa8: 02003737 lui a4,0x2003 + 80001aac: 0722 slli a4,a4,0x8 + 80001aae: 6b37307b .insn 4, 0x6b37307b + 80001ab2: 00200737 lui a4,0x200 + 80001ab6: 30170713 addi a4,a4,769 # 200301 <_start-0x7fdffcff> + 80001aba: 0732 slli a4,a4,0xc + 80001abc: 80170713 addi a4,a4,-2047 + 80001ac0: 8557307b .insn 4, 0x8557307b + 80001ac4: 0000100f fence.i + 80001ac8: 00002597 auipc a1,0x2 + 80001acc: 77858593 addi a1,a1,1912 # 80004240 + 80001ad0: 8fed and a5,a5,a1 + 80001ad2: 02199713 slli a4,s3,0x21 + 80001ad6: 8fd5 or a5,a5,a3 + 80001ad8: 975a add a4,a4,s6 + 80001ada: 20f7307b .insn 4, 0x20f7307b + 80001ade: 00c6307b .insn 4, 0x00c6307b + 80001ae2: 0330000f fence rw,rw + 80001ae6: 0000100f fence.i + 80001aea: 4501 li a0,0 + 80001aec: 85ce mv a1,s3 + 80001aee: ffffe097 auipc ra,0xffffe + 80001af2: 732080e7 jalr 1842(ra) # 80000220 + 80001af6: 414a307b .insn 4, 0x414a307b + 80001afa: 85ce mv a1,s3 + 80001afc: 854e mv a0,s3 + 80001afe: ffffe097 auipc ra,0xffffe + 80001b02: 722080e7 jalr 1826(ra) # 80000220 + 80001b06: 4149b07b .insn 4, 0x4149b07b + 80001b0a: 85ce mv a1,s3 + 80001b0c: 8556 mv a0,s5 + 80001b0e: ffffe097 auipc ra,0xffffe + 80001b12: 712080e7 jalr 1810(ra) # 80000220 + 80001b16: 414ab07b .insn 4, 0x414ab07b + 80001b1a: 85ce mv a1,s3 + 80001b1c: 855a mv a0,s6 + 80001b1e: ffffe097 auipc ra,0xffffe + 80001b22: 702080e7 jalr 1794(ra) # 80000220 + 80001b26: 414b307b .insn 4, 0x414b307b + 80001b2a: 46a1 li a3,8 + 80001b2c: 00002517 auipc a0,0x2 + 80001b30: 71450513 addi a0,a0,1812 # 80004240 + 80001b34: 8636 mv a2,a3 + 80001b36: 00002597 auipc a1,0x2 + 80001b3a: 60a58593 addi a1,a1,1546 # 80004140 + 80001b3e: ffffe097 auipc ra,0xffffe + 80001b42: 762080e7 jalr 1890(ra) # 800002a0 + 80001b46: ed01 bnez a0,80001b5e + 80001b48: 70e2 ld ra,56(sp) + 80001b4a: 7442 ld s0,48(sp) + 80001b4c: 74a2 ld s1,40(sp) + 80001b4e: 7902 ld s2,32(sp) + 80001b50: 6a42 ld s4,16(sp) + 80001b52: 6aa2 ld s5,8(sp) + 80001b54: 6b02 ld s6,0(sp) + 80001b56: 854e mv a0,s3 + 80001b58: 69e2 ld s3,24(sp) + 80001b5a: 6121 addi sp,sp,64 + 80001b5c: 8082 ret + 80001b5e: 00001517 auipc a0,0x1 + 80001b62: b0250513 addi a0,a0,-1278 # 80002660 + 80001b66: ffffe097 auipc ra,0xffffe + 80001b6a: 6f4080e7 jalr 1780(ra) # 8000025a + 80001b6e: 4981 li s3,0 + 80001b70: bfe1 j 80001b48 + +0000000080001b72 : + 80001b72: 7139 addi sp,sp,-64 + 80001b74: f822 sd s0,48(sp) + 80001b76: f426 sd s1,40(sp) + 80001b78: f04a sd s2,32(sp) + 80001b7a: fc06 sd ra,56(sp) + 80001b7c: ec4e sd s3,24(sp) + 80001b7e: e852 sd s4,16(sp) + 80001b80: e456 sd s5,8(sp) + 80001b82: e05a sd s6,0(sp) + 80001b84: 0080 addi s0,sp,64 + 80001b86: 00001517 auipc a0,0x1 + 80001b8a: b0250513 addi a0,a0,-1278 # 80002688 + 80001b8e: ffffe097 auipc ra,0xffffe + 80001b92: 6cc080e7 jalr 1740(ra) # 8000025a + 80001b96: 00003497 auipc s1,0x3 + 80001b9a: b2a48493 addi s1,s1,-1238 # 800046c0 + 80001b9e: 00003917 auipc s2,0x3 + 80001ba2: ae290913 addi s2,s2,-1310 # 80004680 + 80001ba6: 2e8ba337 lui t1,0x2e8ba + 80001baa: 4ec4f8b7 lui a7,0x4ec4f + 80001bae: 8f26 mv t5,s1 + 80001bb0: 8eca mv t4,s2 + 80001bb2: 2e930313 addi t1,t1,745 # 2e8ba2e9 <_start-0x51745d17> + 80001bb6: c4f88893 addi a7,a7,-945 # 4ec4ec4f <_start-0x313b13b1> + 80001bba: 02800813 li a6,40 + 80001bbe: 4e01 li t3,0 + 80001bc0: 04000f93 li t6,64 + 80001bc4: fd88069b addiw a3,a6,-40 + 80001bc8: 8576 mv a0,t4 + 80001bca: 8672 mv a2,t3 + 80001bcc: 85fa mv a1,t5 + 80001bce: 026682b3 mul t0,a3,t1 + 80001bd2: 02061713 slli a4,a2,0x20 + 80001bd6: 9301 srli a4,a4,0x20 + 80001bd8: 41f6d79b sraiw a5,a3,0x1f + 80001bdc: 0505 addi a0,a0,1 + 80001bde: 0585 addi a1,a1,1 + 80001be0: 03170733 mul a4,a4,a7 + 80001be4: 4212d293 srai t0,t0,0x21 + 80001be8: 40f282bb subw t0,t0,a5 + 80001bec: 0012979b slliw a5,t0,0x1 + 80001bf0: 005787bb addw a5,a5,t0 + 80001bf4: 0027979b slliw a5,a5,0x2 + 80001bf8: 405787bb subw a5,a5,t0 + 80001bfc: 40f687bb subw a5,a3,a5 + 80001c00: 37ed addiw a5,a5,-5 + 80001c02: fef58fa3 sb a5,-1(a1) + 80001c06: 9309 srli a4,a4,0x22 + 80001c08: 0017179b slliw a5,a4,0x1 + 80001c0c: 9fb9 addw a5,a5,a4 + 80001c0e: 0027979b slliw a5,a5,0x2 + 80001c12: 9fb9 addw a5,a5,a4 + 80001c14: 40f607bb subw a5,a2,a5 + 80001c18: 37e9 addiw a5,a5,-6 + 80001c1a: fef50fa3 sb a5,-1(a0) + 80001c1e: 2695 addiw a3,a3,5 + 80001c20: 2609 addiw a2,a2,2 # 1001002 <_start-0x7effeffe> + 80001c22: fb0696e3 bne a3,a6,80001bce + 80001c26: 0036881b addiw a6,a3,3 + 80001c2a: 0f21 addi t5,t5,8 + 80001c2c: 2e1d addiw t3,t3,7 + 80001c2e: 0ea1 addi t4,t4,8 + 80001c30: f9f81ae3 bne a6,t6,80001bc4 + 80001c34: 46a1 li a3,8 + 80001c36: 8636 mv a2,a3 + 80001c38: 00003597 auipc a1,0x3 + 80001c3c: a0858593 addi a1,a1,-1528 # 80004640 + 80001c40: 00003517 auipc a0,0x3 + 80001c44: a4050513 addi a0,a0,-1472 # 80004680 + 80001c48: ffffe097 auipc ra,0xffffe + 80001c4c: 6ba080e7 jalr 1722(ra) # 80000302 + 80001c50: 4621 li a2,8 + 80001c52: 85b2 mv a1,a2 + 80001c54: 00003517 auipc a0,0x3 + 80001c58: 9ac50513 addi a0,a0,-1620 # 80004600 + 80001c5c: ffffe097 auipc ra,0xffffe + 80001c60: 68a080e7 jalr 1674(ra) # 800002e6 + 80001c64: 47a1 li a5,8 + 80001c66: 873e mv a4,a5 + 80001c68: 86be mv a3,a5 + 80001c6a: 00002617 auipc a2,0x2 + 80001c6e: 79660613 addi a2,a2,1942 # 80004400 + 80001c72: 00003597 auipc a1,0x3 + 80001c76: 9ce58593 addi a1,a1,-1586 # 80004640 + 80001c7a: 00003517 auipc a0,0x3 + 80001c7e: a4650513 addi a0,a0,-1466 # 800046c0 + 80001c82: ffffe097 auipc ra,0xffffe + 80001c86: 728080e7 jalr 1832(ra) # 800003aa + 80001c8a: 4585 li a1,1 + 80001c8c: 4501 li a0,0 + 80001c8e: ffffe097 auipc ra,0xffffe + 80001c92: 592080e7 jalr 1426(ra) # 80000220 + 80001c96: 4a01 li s4,0 + 80001c98: 42100b13 li s6,1057 + 80001c9c: 416a307b .insn 4, 0x416a307b + 80001ca0: 4585 li a1,1 + 80001ca2: 852e mv a0,a1 + 80001ca4: ffffe097 auipc ra,0xffffe + 80001ca8: 57c080e7 jalr 1404(ra) # 80000220 + 80001cac: 4985 li s3,1 + 80001cae: 4169b07b .insn 4, 0x4169b07b + 80001cb2: 4509 li a0,2 + 80001cb4: 85ce mv a1,s3 + 80001cb6: ffffe097 auipc ra,0xffffe + 80001cba: 56a080e7 jalr 1386(ra) # 80000220 + 80001cbe: 4a89 li s5,2 + 80001cc0: 416ab07b .insn 4, 0x416ab07b + 80001cc4: 4591 li a1,4 + 80001cc6: 450d li a0,3 + 80001cc8: ffffe097 auipc ra,0xffffe + 80001ccc: 558080e7 jalr 1368(ra) # 80000220 + 80001cd0: 4b0d li s6,3 + 80001cd2: 48100793 li a5,1153 + 80001cd6: 40fb307b .insn 4, 0x40fb307b + 80001cda: 0000100f fence.i + 80001cde: 57fd li a5,-1 + 80001ce0: 83e5 srli a5,a5,0x19 + 80001ce2: 00f97733 and a4,s2,a5 + 80001ce6: 02799693 slli a3,s3,0x27 + 80001cea: 8f55 or a4,a4,a3 + 80001cec: 02199613 slli a2,s3,0x21 + 80001cf0: 42e6307b .insn 4, 0x42e6307b + 80001cf4: 0000100f fence.i + 80001cf8: 02001637 lui a2,0x2001 + 80001cfc: 00f4f733 and a4,s1,a5 + 80001d00: 8f55 or a4,a4,a3 + 80001d02: 0622 slli a2,a2,0x8 + 80001d04: 42e6307b .insn 4, 0x42e6307b + 80001d08: 0000100f fence.i + 80001d0c: 00003717 auipc a4,0x3 + 80001d10: 8f470713 addi a4,a4,-1804 # 80004600 + 80001d14: 8f7d and a4,a4,a5 + 80001d16: 01001637 lui a2,0x1001 + 80001d1a: 8f55 or a4,a4,a3 + 80001d1c: 0626 slli a2,a2,0x9 + 80001d1e: 42e6307b .insn 4, 0x42e6307b + 80001d22: 4601 li a2,0 + 80001d24: 11000713 li a4,272 + 80001d28: 04e6307b .insn 4, 0x04e6307b + 80001d2c: 02003737 lui a4,0x2003 + 80001d30: 0722 slli a4,a4,0x8 + 80001d32: 6b37307b .insn 4, 0x6b37307b + 80001d36: 00200737 lui a4,0x200 + 80001d3a: 30170713 addi a4,a4,769 # 200301 <_start-0x7fdffcff> + 80001d3e: 0732 slli a4,a4,0xc + 80001d40: 80170713 addi a4,a4,-2047 + 80001d44: 8557307b .insn 4, 0x8557307b + 80001d48: 0000100f fence.i + 80001d4c: 00002597 auipc a1,0x2 + 80001d50: 7b458593 addi a1,a1,1972 # 80004500 + 80001d54: 8fed and a5,a5,a1 + 80001d56: 02199713 slli a4,s3,0x21 + 80001d5a: 8fd5 or a5,a5,a3 + 80001d5c: 975a add a4,a4,s6 + 80001d5e: 20f7307b .insn 4, 0x20f7307b + 80001d62: 00c6307b .insn 4, 0x00c6307b + 80001d66: 0330000f fence rw,rw + 80001d6a: 0000100f fence.i + 80001d6e: 4501 li a0,0 + 80001d70: 85ce mv a1,s3 + 80001d72: ffffe097 auipc ra,0xffffe + 80001d76: 4ae080e7 jalr 1198(ra) # 80000220 + 80001d7a: 414a307b .insn 4, 0x414a307b + 80001d7e: 85ce mv a1,s3 + 80001d80: 854e mv a0,s3 + 80001d82: ffffe097 auipc ra,0xffffe + 80001d86: 49e080e7 jalr 1182(ra) # 80000220 + 80001d8a: 4149b07b .insn 4, 0x4149b07b + 80001d8e: 85ce mv a1,s3 + 80001d90: 8556 mv a0,s5 + 80001d92: ffffe097 auipc ra,0xffffe + 80001d96: 48e080e7 jalr 1166(ra) # 80000220 + 80001d9a: 414ab07b .insn 4, 0x414ab07b + 80001d9e: 85ce mv a1,s3 + 80001da0: 855a mv a0,s6 + 80001da2: ffffe097 auipc ra,0xffffe + 80001da6: 47e080e7 jalr 1150(ra) # 80000220 + 80001daa: 414b307b .insn 4, 0x414b307b + 80001dae: 46a1 li a3,8 + 80001db0: 00002517 auipc a0,0x2 + 80001db4: 75050513 addi a0,a0,1872 # 80004500 + 80001db8: 8636 mv a2,a3 + 80001dba: 00002597 auipc a1,0x2 + 80001dbe: 64658593 addi a1,a1,1606 # 80004400 + 80001dc2: ffffe097 auipc ra,0xffffe + 80001dc6: 4de080e7 jalr 1246(ra) # 800002a0 + 80001dca: e505 bnez a0,80001df2 + 80001dcc: 00001517 auipc a0,0x1 + 80001dd0: 91c50513 addi a0,a0,-1764 # 800026e8 + 80001dd4: ffffe097 auipc ra,0xffffe + 80001dd8: 486080e7 jalr 1158(ra) # 8000025a + 80001ddc: 854e mv a0,s3 + 80001dde: 70e2 ld ra,56(sp) + 80001de0: 7442 ld s0,48(sp) + 80001de2: 74a2 ld s1,40(sp) + 80001de4: 7902 ld s2,32(sp) + 80001de6: 69e2 ld s3,24(sp) + 80001de8: 6a42 ld s4,16(sp) + 80001dea: 6aa2 ld s5,8(sp) + 80001dec: 6b02 ld s6,0(sp) + 80001dee: 6121 addi sp,sp,64 + 80001df0: 8082 ret + 80001df2: 00001517 auipc a0,0x1 + 80001df6: 8c650513 addi a0,a0,-1850 # 800026b8 + 80001dfa: ffffe097 auipc ra,0xffffe + 80001dfe: 460080e7 jalr 1120(ra) # 8000025a + 80001e02: 4501 li a0,0 + 80001e04: bfe9 j 80001dde + +0000000080001e06 : + 80001e06: 7139 addi sp,sp,-64 + 80001e08: f822 sd s0,48(sp) + 80001e0a: f426 sd s1,40(sp) + 80001e0c: f04a sd s2,32(sp) + 80001e0e: fc06 sd ra,56(sp) + 80001e10: ec4e sd s3,24(sp) + 80001e12: e852 sd s4,16(sp) + 80001e14: e456 sd s5,8(sp) + 80001e16: e05a sd s6,0(sp) + 80001e18: 0080 addi s0,sp,64 + 80001e1a: 00001517 auipc a0,0x1 + 80001e1e: 8fe50513 addi a0,a0,-1794 # 80002718 + 80001e22: ffffe097 auipc ra,0xffffe + 80001e26: 438080e7 jalr 1080(ra) # 8000025a + 80001e2a: 00003497 auipc s1,0x3 + 80001e2e: b5648493 addi s1,s1,-1194 # 80004980 + 80001e32: 00003917 auipc s2,0x3 + 80001e36: b0e90913 addi s2,s2,-1266 # 80004940 + 80001e3a: 2e8ba337 lui t1,0x2e8ba + 80001e3e: 4ec4f8b7 lui a7,0x4ec4f + 80001e42: 8f26 mv t5,s1 + 80001e44: 8eca mv t4,s2 + 80001e46: 2e930313 addi t1,t1,745 # 2e8ba2e9 <_start-0x51745d17> + 80001e4a: c4f88893 addi a7,a7,-945 # 4ec4ec4f <_start-0x313b13b1> + 80001e4e: 02800813 li a6,40 + 80001e52: 4e01 li t3,0 + 80001e54: 04000f93 li t6,64 + 80001e58: fd88069b addiw a3,a6,-40 + 80001e5c: 8576 mv a0,t4 + 80001e5e: 8672 mv a2,t3 + 80001e60: 85fa mv a1,t5 + 80001e62: 026682b3 mul t0,a3,t1 + 80001e66: 02061713 slli a4,a2,0x20 + 80001e6a: 9301 srli a4,a4,0x20 + 80001e6c: 41f6d79b sraiw a5,a3,0x1f + 80001e70: 0505 addi a0,a0,1 + 80001e72: 0585 addi a1,a1,1 + 80001e74: 03170733 mul a4,a4,a7 + 80001e78: 4212d293 srai t0,t0,0x21 + 80001e7c: 40f282bb subw t0,t0,a5 + 80001e80: 0012979b slliw a5,t0,0x1 + 80001e84: 005787bb addw a5,a5,t0 + 80001e88: 0027979b slliw a5,a5,0x2 + 80001e8c: 405787bb subw a5,a5,t0 + 80001e90: 40f687bb subw a5,a3,a5 + 80001e94: 37ed addiw a5,a5,-5 + 80001e96: fef58fa3 sb a5,-1(a1) + 80001e9a: 9309 srli a4,a4,0x22 + 80001e9c: 0017179b slliw a5,a4,0x1 + 80001ea0: 9fb9 addw a5,a5,a4 + 80001ea2: 0027979b slliw a5,a5,0x2 + 80001ea6: 9fb9 addw a5,a5,a4 + 80001ea8: 40f607bb subw a5,a2,a5 + 80001eac: 37e9 addiw a5,a5,-6 + 80001eae: fef50fa3 sb a5,-1(a0) + 80001eb2: 2695 addiw a3,a3,5 + 80001eb4: 2609 addiw a2,a2,2 # 1001002 <_start-0x7effeffe> + 80001eb6: fb0696e3 bne a3,a6,80001e62 + 80001eba: 0036881b addiw a6,a3,3 + 80001ebe: 0f21 addi t5,t5,8 + 80001ec0: 2e1d addiw t3,t3,7 + 80001ec2: 0ea1 addi t4,t4,8 + 80001ec4: f9f81ae3 bne a6,t6,80001e58 + 80001ec8: 4621 li a2,8 + 80001eca: 85b2 mv a1,a2 + 80001ecc: 00003517 auipc a0,0x3 + 80001ed0: a3450513 addi a0,a0,-1484 # 80004900 + 80001ed4: ffffe097 auipc ra,0xffffe + 80001ed8: 412080e7 jalr 1042(ra) # 800002e6 + 80001edc: 47a1 li a5,8 + 80001ede: 873e mv a4,a5 + 80001ee0: 86be mv a3,a5 + 80001ee2: 00003617 auipc a2,0x3 + 80001ee6: 81e60613 addi a2,a2,-2018 # 80004700 + 80001eea: 00003597 auipc a1,0x3 + 80001eee: a5658593 addi a1,a1,-1450 # 80004940 + 80001ef2: 00003517 auipc a0,0x3 + 80001ef6: a8e50513 addi a0,a0,-1394 # 80004980 + 80001efa: ffffe097 auipc ra,0xffffe + 80001efe: 4b0080e7 jalr 1200(ra) # 800003aa + 80001f02: 00002997 auipc s3,0x2 + 80001f06: 7fe98993 addi s3,s3,2046 # 80004700 + 80001f0a: 00003a17 auipc s4,0x3 + 80001f0e: 8f6a0a13 addi s4,s4,-1802 # 80004800 + 80001f12: 0009a503 lw a0,0(s3) + 80001f16: 4591 li a1,4 + 80001f18: 0991 addi s3,s3,4 + 80001f1a: ffffe097 auipc ra,0xffffe + 80001f1e: 440080e7 jalr 1088(ra) # 8000035a + 80001f22: fea9ae23 sw a0,-4(s3) + 80001f26: ff3a16e3 bne s4,s3,80001f12 + 80001f2a: 4585 li a1,1 + 80001f2c: 4501 li a0,0 + 80001f2e: ffffe097 auipc ra,0xffffe + 80001f32: 2f2080e7 jalr 754(ra) # 80000220 + 80001f36: 4a01 li s4,0 + 80001f38: 42100b13 li s6,1057 + 80001f3c: 416a307b .insn 4, 0x416a307b + 80001f40: 4585 li a1,1 + 80001f42: 852e mv a0,a1 + 80001f44: ffffe097 auipc ra,0xffffe + 80001f48: 2dc080e7 jalr 732(ra) # 80000220 + 80001f4c: 4985 li s3,1 + 80001f4e: 4169b07b .insn 4, 0x4169b07b + 80001f52: 4509 li a0,2 + 80001f54: 85ce mv a1,s3 + 80001f56: ffffe097 auipc ra,0xffffe + 80001f5a: 2ca080e7 jalr 714(ra) # 80000220 + 80001f5e: 4a89 li s5,2 + 80001f60: 416ab07b .insn 4, 0x416ab07b + 80001f64: 4591 li a1,4 + 80001f66: 450d li a0,3 + 80001f68: ffffe097 auipc ra,0xffffe + 80001f6c: 2b8080e7 jalr 696(ra) # 80000220 + 80001f70: 4b0d li s6,3 + 80001f72: 48100793 li a5,1153 + 80001f76: 40fb307b .insn 4, 0x40fb307b + 80001f7a: 0000100f fence.i + 80001f7e: 57fd li a5,-1 + 80001f80: 83e5 srli a5,a5,0x19 + 80001f82: 00f97733 and a4,s2,a5 + 80001f86: 02799693 slli a3,s3,0x27 + 80001f8a: 8f55 or a4,a4,a3 + 80001f8c: 02199613 slli a2,s3,0x21 + 80001f90: 42e6307b .insn 4, 0x42e6307b + 80001f94: 0000100f fence.i + 80001f98: 02001637 lui a2,0x2001 + 80001f9c: 00f4f733 and a4,s1,a5 + 80001fa0: 8f55 or a4,a4,a3 + 80001fa2: 0622 slli a2,a2,0x8 + 80001fa4: 42e6307b .insn 4, 0x42e6307b + 80001fa8: 0000100f fence.i + 80001fac: 00003717 auipc a4,0x3 + 80001fb0: 95470713 addi a4,a4,-1708 # 80004900 + 80001fb4: 8f7d and a4,a4,a5 + 80001fb6: 01001637 lui a2,0x1001 + 80001fba: 8f55 or a4,a4,a3 + 80001fbc: 0626 slli a2,a2,0x9 + 80001fbe: 42e6307b .insn 4, 0x42e6307b + 80001fc2: 6705 lui a4,0x1 + 80001fc4: 81070713 addi a4,a4,-2032 # 810 <_start-0x7ffff7f0> + 80001fc8: 4601 li a2,0 + 80001fca: 04e6307b .insn 4, 0x04e6307b + 80001fce: 02003737 lui a4,0x2003 + 80001fd2: 0722 slli a4,a4,0x8 + 80001fd4: 6b37307b .insn 4, 0x6b37307b + 80001fd8: 00200737 lui a4,0x200 + 80001fdc: 30170713 addi a4,a4,769 # 200301 <_start-0x7fdffcff> + 80001fe0: 0732 slli a4,a4,0xc + 80001fe2: 80170713 addi a4,a4,-2047 + 80001fe6: 8557307b .insn 4, 0x8557307b + 80001fea: 0000100f fence.i + 80001fee: 00003597 auipc a1,0x3 + 80001ff2: 81258593 addi a1,a1,-2030 # 80004800 + 80001ff6: 8fed and a5,a5,a1 + 80001ff8: 02199713 slli a4,s3,0x21 + 80001ffc: 8fd5 or a5,a5,a3 + 80001ffe: 975a add a4,a4,s6 + 80002000: 20f7307b .insn 4, 0x20f7307b + 80002004: 00c6307b .insn 4, 0x00c6307b + 80002008: 0330000f fence rw,rw + 8000200c: 0000100f fence.i + 80002010: 4501 li a0,0 + 80002012: 85ce mv a1,s3 + 80002014: ffffe097 auipc ra,0xffffe + 80002018: 20c080e7 jalr 524(ra) # 80000220 + 8000201c: 414a307b .insn 4, 0x414a307b + 80002020: 85ce mv a1,s3 + 80002022: 854e mv a0,s3 + 80002024: ffffe097 auipc ra,0xffffe + 80002028: 1fc080e7 jalr 508(ra) # 80000220 + 8000202c: 4149b07b .insn 4, 0x4149b07b + 80002030: 85ce mv a1,s3 + 80002032: 8556 mv a0,s5 + 80002034: ffffe097 auipc ra,0xffffe + 80002038: 1ec080e7 jalr 492(ra) # 80000220 + 8000203c: 414ab07b .insn 4, 0x414ab07b + 80002040: 85ce mv a1,s3 + 80002042: 855a mv a0,s6 + 80002044: ffffe097 auipc ra,0xffffe + 80002048: 1dc080e7 jalr 476(ra) # 80000220 + 8000204c: 414b307b .insn 4, 0x414b307b + 80002050: 46a1 li a3,8 + 80002052: 00002517 auipc a0,0x2 + 80002056: 7ae50513 addi a0,a0,1966 # 80004800 + 8000205a: 8636 mv a2,a3 + 8000205c: 00002597 auipc a1,0x2 + 80002060: 6a458593 addi a1,a1,1700 # 80004700 + 80002064: ffffe097 auipc ra,0xffffe + 80002068: 23c080e7 jalr 572(ra) # 800002a0 + 8000206c: e505 bnez a0,80002094 + 8000206e: 00000517 auipc a0,0x0 + 80002072: 6fa50513 addi a0,a0,1786 # 80002768 + 80002076: ffffe097 auipc ra,0xffffe + 8000207a: 1e4080e7 jalr 484(ra) # 8000025a + 8000207e: 854e mv a0,s3 + 80002080: 70e2 ld ra,56(sp) + 80002082: 7442 ld s0,48(sp) + 80002084: 74a2 ld s1,40(sp) + 80002086: 7902 ld s2,32(sp) + 80002088: 69e2 ld s3,24(sp) + 8000208a: 6a42 ld s4,16(sp) + 8000208c: 6aa2 ld s5,8(sp) + 8000208e: 6b02 ld s6,0(sp) + 80002090: 6121 addi sp,sp,64 + 80002092: 8082 ret + 80002094: 00000517 auipc a0,0x0 + 80002098: 6ac50513 addi a0,a0,1708 # 80002740 + 8000209c: ffffe097 auipc ra,0xffffe + 800020a0: 1be080e7 jalr 446(ra) # 8000025a + 800020a4: 4501 li a0,0 + 800020a6: bfe9 j 80002080 diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/gemmini-tests/simulation/smoke.elf b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/gemmini-tests/simulation/smoke.elf new file mode 100644 index 0000000..9e0dd11 Binary files /dev/null and b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/gemmini-tests/simulation/smoke.elf differ diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/gemmini-tests/simulation/smoke.hex b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/gemmini-tests/simulation/smoke.hex new file mode 100644 index 0000000..3554207 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/gemmini-tests/simulation/smoke.hex @@ -0,0 +1,10126 @@ +37 +21 +00 +00 +1b +01 +11 +00 +13 +11 +21 +01 +13 +01 +01 +ff +97 +02 +00 +00 +93 +82 +c2 +04 +73 +90 +52 +30 +73 +10 +40 +30 +73 +10 +20 +30 +b7 +e2 +01 +00 +73 +a0 +02 +30 +97 +00 +00 +00 +e7 +80 +00 +05 +b7 +02 +00 +60 +37 +63 +0d +60 +1b +03 +d3 +00 +63 +0a +05 +00 +37 +13 +00 +00 +1b +03 +d3 +ba +13 +13 +43 +01 +33 +63 +a3 +00 +23 +b0 +62 +00 +6f +00 +00 +00 +f3 +23 +20 +34 +b7 +02 +00 +60 +37 +b3 +0b +00 +1b +03 +f3 +d0 +13 +13 +c3 +00 +33 +63 +73 +00 +23 +b0 +62 +00 +6f +00 +00 +00 +01 +11 +22 +e8 +26 +e4 +06 +ec +00 +10 +b7 +07 +00 +71 +85 +07 +b7 +04 +00 +60 +9c +e0 +97 +00 +00 +00 +e7 +80 +c0 +3e +aa +87 +05 +45 +91 +c7 +e2 +60 +42 +64 +a2 +64 +05 +61 +82 +80 +37 +07 +00 +72 +2a +97 +b7 +07 +00 +71 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b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/gemmini-tests/simulation/tb_cpu.sv new file mode 100644 index 0000000..35875f7 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/gemmini-tests/simulation/tb_cpu.sv @@ -0,0 +1,153 @@ +`timescale 1ns/1ps +module tb; + reg clock=0; + reg reset=0; + reg interrupt=0; + wire memory_aw_ready; + wire memory_aw_valid; + wire [3:0] memory_aw_bits_id; + wire [31:0] memory_aw_bits_addr; + wire [7:0] memory_aw_bits_len; + wire [2:0] memory_aw_bits_size; + wire [1:0] memory_aw_bits_burst; + wire memory_aw_bits_lock; + wire [3:0] memory_aw_bits_cache; + wire [2:0] memory_aw_bits_prot; + wire [3:0] memory_aw_bits_qos; + wire memory_w_ready; + wire memory_w_valid; + wire [127:0] memory_w_bits_data; + wire [15:0] memory_w_bits_strb; + wire memory_w_bits_last; + wire memory_b_ready; + wire memory_b_valid; + wire [3:0] memory_b_bits_id; + wire [1:0] memory_b_bits_resp; + wire memory_ar_ready; + wire memory_ar_valid; + wire [3:0] memory_ar_bits_id; + wire [31:0] memory_ar_bits_addr; + wire [7:0] memory_ar_bits_len; + wire [2:0] memory_ar_bits_size; + wire [1:0] memory_ar_bits_burst; + wire memory_ar_bits_lock; + wire [3:0] memory_ar_bits_cache; + wire [2:0] memory_ar_bits_prot; + wire [3:0] memory_ar_bits_qos; + wire memory_r_ready; + wire memory_r_valid; + wire [3:0] memory_r_bits_id; + wire [127:0] memory_r_bits_data; + wire [1:0] memory_r_bits_resp; + wire memory_r_bits_last; + wire peripherals_aw_ready; + wire peripherals_aw_valid; + wire [1:0] peripherals_aw_bits_id; + wire [30:0] peripherals_aw_bits_addr; + wire [7:0] peripherals_aw_bits_len; + wire [2:0] peripherals_aw_bits_size; + wire [1:0] peripherals_aw_bits_burst; + wire peripherals_aw_bits_lock; + wire [3:0] peripherals_aw_bits_cache; + wire [2:0] peripherals_aw_bits_prot; + wire [3:0] peripherals_aw_bits_qos; + wire peripherals_w_ready; + wire peripherals_w_valid; + wire [63:0] peripherals_w_bits_data; + wire [7:0] peripherals_w_bits_strb; + wire peripherals_w_bits_last; + wire peripherals_b_ready; + wire peripherals_b_valid; + wire [1:0] peripherals_b_bits_id; + wire [1:0] peripherals_b_bits_resp; + wire peripherals_ar_ready; + wire peripherals_ar_valid; + wire [1:0] peripherals_ar_bits_id; + wire [30:0] peripherals_ar_bits_addr; + wire [7:0] peripherals_ar_bits_len; + wire [2:0] peripherals_ar_bits_size; + wire [1:0] peripherals_ar_bits_burst; + wire peripherals_ar_bits_lock; + wire [3:0] peripherals_ar_bits_cache; + wire [2:0] peripherals_ar_bits_prot; + wire [3:0] peripherals_ar_bits_qos; + wire peripherals_r_ready; + wire peripherals_r_valid; + wire [1:0] peripherals_r_bits_id; + wire [63:0] peripherals_r_bits_data; + wire [1:0] peripherals_r_bits_resp; + wire peripherals_r_bits_last; + ToyLinuxChip dut(.*); + integer cycle_count=0; + always @(posedge clock) if (!reset) cycle_count<=cycle_count+1; + always #5 clock=~clock; + initial begin reset=1; repeat(20) @(negedge clock); reset=0; end + initial begin repeat(5000000) @(posedge clock); $fatal(1,"CPU timeout"); end + axi_smoke_memory #(.DATA_BITS(128), .ID_BITS(4), .ADDR_BITS(32), .BASE(32'h80000000), .CAPACITY(262144), .IMAGE("smoke.hex")) memory_model ( + .clock(clock), + .reset(reset), + .aw_ready(memory_aw_ready), + .aw_valid(memory_aw_valid), + .aw_bits_id(memory_aw_bits_id), + .aw_bits_addr(memory_aw_bits_addr), + .aw_bits_len(memory_aw_bits_len), + .aw_bits_size(memory_aw_bits_size), + .aw_bits_burst(memory_aw_bits_burst), + .w_ready(memory_w_ready), + .w_valid(memory_w_valid), + .w_bits_data(memory_w_bits_data), + .w_bits_strb(memory_w_bits_strb), + .w_bits_last(memory_w_bits_last), + .b_ready(memory_b_ready), + .b_valid(memory_b_valid), + .b_bits_id(memory_b_bits_id), + .b_bits_resp(memory_b_bits_resp), + .ar_ready(memory_ar_ready), + .ar_valid(memory_ar_valid), + .ar_bits_id(memory_ar_bits_id), + .ar_bits_addr(memory_ar_bits_addr), + .ar_bits_len(memory_ar_bits_len), + .ar_bits_size(memory_ar_bits_size), + .ar_bits_burst(memory_ar_bits_burst), + .r_ready(memory_r_ready), + .r_valid(memory_r_valid), + .r_bits_id(memory_r_bits_id), + .r_bits_data(memory_r_bits_data), + .r_bits_resp(memory_r_bits_resp), + .r_bits_last(memory_r_bits_last) + ); + axi_smoke_memory #(.DATA_BITS(64), .ID_BITS(2), .ADDR_BITS(31), .BASE(32'h60000000), .CAPACITY(4096), .MONITOR(1), .TEST_LABEL("whole Toy Gemmini regression")) peripherals_model ( + .clock(clock), + .reset(reset), + .aw_ready(peripherals_aw_ready), + .aw_valid(peripherals_aw_valid), + .aw_bits_id(peripherals_aw_bits_id), + .aw_bits_addr(peripherals_aw_bits_addr), + .aw_bits_len(peripherals_aw_bits_len), + .aw_bits_size(peripherals_aw_bits_size), + .aw_bits_burst(peripherals_aw_bits_burst), + .w_ready(peripherals_w_ready), + .w_valid(peripherals_w_valid), + .w_bits_data(peripherals_w_bits_data), + .w_bits_strb(peripherals_w_bits_strb), + .w_bits_last(peripherals_w_bits_last), + .b_ready(peripherals_b_ready), + .b_valid(peripherals_b_valid), + .b_bits_id(peripherals_b_bits_id), + .b_bits_resp(peripherals_b_bits_resp), + .ar_ready(peripherals_ar_ready), + .ar_valid(peripherals_ar_valid), + .ar_bits_id(peripherals_ar_bits_id), + .ar_bits_addr(peripherals_ar_bits_addr), + .ar_bits_len(peripherals_ar_bits_len), + .ar_bits_size(peripherals_ar_bits_size), + .ar_bits_burst(peripherals_ar_bits_burst), + .r_ready(peripherals_r_ready), + .r_valid(peripherals_r_valid), + .r_bits_id(peripherals_r_bits_id), + .r_bits_data(peripherals_r_bits_data), + .r_bits_resp(peripherals_r_bits_resp), + .r_bits_last(peripherals_r_bits_last) + ); + final $display("MEASURE cycles=%0d memory_reads=%0d memory_writes=%0d", cycle_count, memory_model.read_bursts, memory_model.write_bursts); +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/gemmini-tests/simulation/verilator-build.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/gemmini-tests/simulation/verilator-build.log new file mode 100644 index 0000000..e4634fb --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/gemmini-tests/simulation/verilator-build.log @@ -0,0 +1,2123 @@ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 31 | module NonSyncResetSynchronizerPrimitiveShiftReg_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ + ... For warning description see https://verilator.org/warn/TIMESCALEMOD?v=5.050 + ... Use "/* verilator lint_off TIMESCALEMOD */" and lint_on around source to disable this message. +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:48:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 48 | module SynchronizerShiftReg_w1_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:61:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 61 | module IntSyncAsyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:74:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 74 | module AsyncResetRegVec_w1_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 103 | module IntSyncCrossingSource_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:118:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 118 | module FixedClockBroadcast_3( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:139:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 139 | module TLMonitor( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:987:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 987 | module TLMonitor_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:2434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 2434 | module TLXbar_sbus_i2_o3_a32d128s3k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:3195:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3195 | module TLMonitor_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4151 | module Repeater_TLBundleA_a28d128s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4218 | module TLWidthWidget16( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4386 | module TLInterconnectCoupler_sbus_to_bus_named_cbus( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4478:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4478 | module ram_2x58( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4497:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4497 | module Queue2_AXI4BundleAW( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4581:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4581 | module ram_2x73( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4600:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4600 | module Queue2_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4657:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4657 | module ram_2x4( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4676:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4676 | module Queue2_AXI4BundleB( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4729:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4729 | module Queue2_AXI4BundleAR( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4813:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4813 | module ram_2x69( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4832:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4832 | module Queue2_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4891:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4891 | module AXI4Buffer( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5067:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5067 | module ram_2x8( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5086:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5086 | module Queue2_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5143:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5143 | module Queue1_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5178 | module AXI4UserYanker( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5540:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5540 | module ram_8x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5559:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5559 | module Queue8_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5631 | module AXI4Deinterleaver( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:6073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6073 | module AXI4IdIndexer( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:6219:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6219 | module TLMonitor_3( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7048:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7048 | module Queue1_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7082:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7082 | module Queue1_AXI4BundleARW( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7148:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7148 | module TLToAXI4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7529:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7529 | module TLMonitor_4( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8396:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8396 | module Repeater_TLBundleA_a31d128s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8463 | module TLWidthWidget16_2( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8623:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8623 | module TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:9400:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 9400 | module SystemBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10050 | module FixedClockBroadcast_4( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10073 | module TLMonitor_5( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10975:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10975 | module TLXbar_cbus_out_i1_o4_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:11288:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +11288 | module TLMonitor_6( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12202:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12202 | module ram_2x114( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12221 | module Queue2_TLBundleA_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12301 | module ram_2x79( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12320:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12320 | module Queue2_TLBundleD_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12399:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12399 | module TLBuffer_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12534:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12534 | module TLMonitor_7( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:13449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13449 | module TLAtomicAutomata_cbus( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:13973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13973 | module TLMonitor_8( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14799 | module Queue1_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14846:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14846 | module TLError( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14953 | module TLMonitor_9( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15857 | module ram_2x100( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15876:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15876 | module Queue2_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15955:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15955 | module Queue2_TLBundleD_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16028 | module TLBuffer_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16155 | module ErrorDeviceWrapper( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16258 | module TLMonitor_10( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17017:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17017 | module Repeater_TLBundleA_a26d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17081:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17081 | module TLFragmenter_CLINT( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17261:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17261 | module TLInterconnectCoupler_cbus_to_clint( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17336:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17336 | module TLMonitor_11( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18106:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18106 | module Repeater_TLBundleA_a28d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18170:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18170 | module TLFragmenter_PLIC( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18350 | module TLInterconnectCoupler_cbus_to_plic( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18425:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18425 | module TLMonitor_12( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19040 | module Repeater_TLBundleA_a17d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19104:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19104 | module TLFragmenter_bootrom( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19263:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19263 | module TLInterconnectCoupler_cbus_to_bootrom( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19330:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19330 | module PeripheryBus_cbus( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19882 | module TLMonitor_13( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20610:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20610 | module ProbePicker( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20688:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20688 | module ram_2x10( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20707:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20707 | module Queue2_BundleMap_6( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20764:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20764 | module AXI4UserYanker_1( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:21713:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21713 | module AXI4IdIndexer_1( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:21859:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21859 | module TLMonitor_14( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22587:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22587 | module Queue1_AXI4BundleW_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22621 | module Queue1_AXI4BundleARW_1( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22687:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22687 | module TLToAXI4_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:23555:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +23555 | module TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:24031:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24031 | module MemoryBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:24349:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24349 | module TLMonitor_15( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25732:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25732 | module BroadcastFilter( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25756:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25756 | module ram_4x144( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25775:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25775 | module Queue4_TLBroadcastData( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25828:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25828 | module TLBroadcastTracker( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25964:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25964 | module TLBroadcastTracker_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:26100:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26100 | module TLBroadcast( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:26686:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26686 | module TLMonitor_16( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27414 | module BankBinder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27491:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27491 | module CoherenceManagerWrapper( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27669:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27669 | module TLMonitor_17( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29229:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29229 | module TLMonitor_18( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29635:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29635 | module TLXbar_MasterXbar_BBTile_i2_o1_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29898 | module IntXbar_i4_o1( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29918:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29918 | module WritebackUnit( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30014:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30014 | module ProbeUnit( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30154:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30154 | module Arbiter1_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30168:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30168 | module Arbiter1_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30191 | module Arbiter1_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30214 | module Arbiter1_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30249:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30249 | module Arbiter1_Bool( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30258 | module ram_16x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30277:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30277 | module Queue16_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30360:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30360 | module Queue1_TLBundleE_a32d128s1k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30388:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30388 | module MSHR( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30835:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30835 | module Arbiter1_HellaCacheResp( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30879:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30879 | module IOMSHR( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31790:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31790 | module sdq_17x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31809 | module MSHRFile( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32350 | module OptimizationBarrier_TLBEntryData( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32406:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32406 | module PMPChecker_s3( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32691:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32691 | module PMAChecker( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32731:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32731 | module DTLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:35923:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35923 | module L1MetadataArray( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:35990:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35990 | module Arbiter5_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36023:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36023 | module Arbiter2_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36055 | module DataArray( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36151 | module Arbiter4_L1DataReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36180:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36180 | module Arbiter2_L1DataWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36206:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36206 | module AMOALU( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36248:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36248 | module MaxPeriodFibonacciLFSR( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36342:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36342 | module Arbiter2_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36377:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36377 | module NonBlockingDCache( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:37660:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37660 | module ICache( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:37914:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37914 | module ShiftQueue( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:38054:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38054 | module PMPChecker_s2( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:38215:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38215 | module ITLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:41129:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41129 | module Frontend( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:41494:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41494 | module TLMonitor_19( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:42301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +42301 | module TLMonitor_20( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43108:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43108 | module TLXbar_i2_o1_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43343 | module TLMonitor_21( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43851:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43851 | module ram_2x116( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43870:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43870 | module Queue2_TLBundleA_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43947:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43947 | module ram_2x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43966:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43966 | module Queue2_TLBundleD_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44045:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44045 | module TLBuffer_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44158:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44158 | module TLMonitor_22( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44783 | module TLBuffer_a32d64s1k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44892:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44892 | module TLMonitor_23( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:45699:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45699 | module Repeater_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:45766:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45766 | module TLWidthWidget8_4( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46074:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46074 | module TLMonitor_24( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46882 | module ram_2x117( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46901:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46901 | module Queue2_TLBundleA_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46981:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46981 | module ram_2x78( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47000:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47000 | module Queue2_TLBundleD_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47079:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47079 | module TLBuffer_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47214 | module HellaCacheArbiter( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47381 | module Arbiter3_Valid_PTWReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47419:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47419 | module OptimizationBarrier_UInt( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47427 | module OptimizationBarrier_PTE( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47459 | module PTW( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:48434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +48434 | module FPUDecoder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49794:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49794 | module CompareRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49824:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49824 | module RecFNToIN_e11_s53_i64( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49873:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49873 | module RecFNToIN_e11_s53_i32( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49912:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49912 | module FPToInt( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50375:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50375 | module RoundAnyRawFNToRecFN_ie7_is64_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50410:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50410 | module PipelinedINToRecFN( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50513:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50513 | module RoundAnyRawFNToRecFN_ie7_is64_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50539 | module PipelinedINToRecFN_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50614 | module RoundAnyRawFNToRecFN_ie7_is64_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50642:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50642 | module PipelinedINToRecFN_2( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50717 | module IntToFP( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51072:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51072 | module RoundAnyRawFNToRecFN_ie11_is53_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51199:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51199 | module RecFNToRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51221 | module RoundAnyRawFNToRecFN_ie11_is53_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51321:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51321 | module RecFNToRecFN_1( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51343 | module FPToFP( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51469:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51469 | module MulAddRecFNToRaw_preMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51569 | module MulAddRecFNToRaw_postMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51822:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51822 | module RoundAnyRawFNToRecFN_ie11_is55_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51953 | module RoundAnyRawFNToRecFN_ie11_is55_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52060:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52060 | module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52194:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52194 | module SharedMulAddRecFNPipe( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52551:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52551 | module FPUSharedFMAPipe( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52682:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52682 | module DivSqrtRawFN_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52852:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52852 | module DivSqrtRecFMToRaw_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52907:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52907 | module RoundAnyRawFNToRecFN_ie5_is13_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53039:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53039 | module RoundRawFNToRecFN_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53068:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53068 | module DivSqrtRecFM_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53128:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53128 | module DivSqrtRawFN_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53297:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53297 | module DivSqrtRecFMToRaw_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53352:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53352 | module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53456:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53456 | module RoundRawFNToRecFN_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53485:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53485 | module DivSqrtRecFM_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53545:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53545 | module DivSqrtRawFN_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53715:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53715 | module DivSqrtRecFMToRaw_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53770:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53770 | module RoundRawFNToRecFN_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53799 | module DivSqrtRecFM_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53860:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53860 | module regfile_32x65( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53905:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53905 | module FPU( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:54820:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +54820 | module RVCExpander( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:55183:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55183 | module IBuf( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:55307:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55307 | module CSRFile( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:57223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57223 | module RocketALU( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:57809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57809 | module MulDiv( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:58107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58107 | module Arbiter3_LLWB( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:58125:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58125 | module rf_31x64( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:58149:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58149 | module RocketBB( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62838:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62838 | module GlobalDecoder( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62928:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62928 | module BankAliasTable( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:64252:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64252 | module BankScoreboard( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:64627:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64627 | module GlobalROB( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68674:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68674 | module Arbiter3_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68717 | module ram_16x4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68736:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68736 | module Queue16_UInt4( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68782:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68782 | module SubROB( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:69357:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69357 | module Arbiter1_SubRobRow( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:69722:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69722 | module GlobalScheduler( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:70973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +70973 | module BootRom( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:71013:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71013 | module Frontend_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:71637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71637 | module PE( + | ^~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:71656:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71656 | module AlwaysOutTransposer( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72411:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72411 | module MacUnit( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72426:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72426 | module PE_64( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72524:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72524 | module Tile( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72571:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72571 | module Mesh( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76050 | module TagQueue( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76191 | module ram_6x7( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76210:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76210 | module Queue6_TagWithIdAndTotalRows( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76271:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76271 | module MeshWithDelays( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77318:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77318 | module ram_data_8x64( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77337 | module Queue8_SramReadResp( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77385:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77385 | module GemminiExCtrl( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79354:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79354 | module LoopMatmulUnroller( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79637 | module LoopConvAddrGen( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79690:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79690 | module LoopConvUnroller( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:80113:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80113 | module LoopCmdEncoder( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:80402:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80402 | module Arbiter2_LoopCmd( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:80598:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80598 | module GemminiBall( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:81783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81783 | module RRArbiter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:81857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81857 | module CmdRouter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:81985:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81985 | module BallCyclePMC( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:82095:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82095 | module BBus( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:82898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82898 | module BallDomainDecoder( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83028 | module ram_4x281( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83047:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83047 | module Queue4_BallReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83178 | module Arbiter1_BallRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83198:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83198 | module BallReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83328:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83328 | module BallDomain( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84141:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84141 | module MemDomainDecoder( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84300:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84300 | module ram_4x158( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84319:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84319 | module Queue4_MemReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84421:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84421 | module Arbiter3_MemRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84463 | module MemReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84631 | module MemLoader( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84869:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84869 | module MemStorer( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85122:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85122 | module MemCyclePMC( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85241:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85241 | module TLB( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85621 | module RRArbiter_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85649:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85649 | module BBTLBCluster( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85777 | module StreamReader( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86142:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86142 | module StreamWriter( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86223 | module ZeroLineGenerator( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86264:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86264 | module MemConfiger( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86433:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86433 | module RRArbiter_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86465:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86465 | module MemGroupQueryArbiter( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86543:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86543 | module MemFrontend( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87160 | module MemMidend( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87621 | module SramBank( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87672:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87672 | module AccPipe( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87781 | module PrivateMemBackend( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:90777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +90777 | module MemBackend( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:91055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91055 | module MemDomain( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:91973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91973 | module Queue1_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92008:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92008 | module GpDomain( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92040 | module ram_8x21( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92059 | module Queue8_BuckyballAccelerator_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92123:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92123 | module BuckyballAccelerator( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93569 | module Queue3_UInt2( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93614 | module SimpleHellaCacheIFReplayQueue( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93667:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93667 | module Arbiter2_HellaCacheReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93678:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93678 | module SimpleHellaCacheIF( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93768:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93768 | module BarrierUnit( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93785:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93785 | module BBTile( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:95579:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +95579 | module TLMonitor_25( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:96427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +96427 | module TLMonitor_26( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98184:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98184 | module ram_2x189( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98203:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98203 | module Queue2_TLBundleA_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98283:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98283 | module ram_2x142( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98302:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98302 | module Queue2_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98381 | module Queue2_TLBundleA_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98459 | module Queue2_TLBundleD_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98539 | module ram_2x60( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98558:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98558 | module Queue2_TLBundleB_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98622:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98622 | module ram_2x173( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98641:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98641 | module Queue2_TLBundleC_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98716:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98716 | module ram_sink_2x1( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98735:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98735 | module Queue2_TLBundleE_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98781 | module TLBuffer_a32d128s2k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99162:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99162 | module IntSyncSyncCrossingSink_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99173:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99173 | module IntSyncSyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99181:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99181 | module TilePRCIDomain( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99589:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99589 | module BundleBridgeNexus_UInt1_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99597:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99597 | module TLMonitor_27( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100216:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100216 | module CLINT( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100337 | module AsyncResetRegVec_w2_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100366:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100366 | module IntSyncCrossingSource_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100386 | module CLINTClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100449 | module TLMonitor_28( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101080:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101080 | module LevelGateway( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101099:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101099 | module PLICFanIn( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101111:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101111 | module Queue1_RegMapperInput_i23_m8( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101160 | module TLPLIC( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101389:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101389 | module PLICClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101452:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101452 | module TLMonitor_29( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101973 | module TLROM( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:102530:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102530 | module bootromClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:102569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102569 | module ToyLinuxSystem( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103817:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103817 | module ToyLinuxChip( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103984:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103984 | module tag_array( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104007:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104007 | module array_0_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104034:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104034 | module array_0_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104059 | module array_2_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104084:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104084 | module array_2_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104109:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104109 | module bbtile_icache_tag_array( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104132:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104132 | module bbtile_icache_data_arrays_0( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104155 | module bbtile_icache_data_arrays_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104176:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104176 | module bbtile_icache_data_arrays_2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104197:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104197 | module bbtile_icache_data_arrays_3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104218 | module robOperands( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104243:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104243 | module sram( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104268:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104268 | module mem( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104301 | module plusarg_reader #( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104326:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104326 | module ITraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104404:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104404 | module FpgaDspMac(input [7:0] a, b, input [19:0] c, output [19:0] y); + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104414 | module PMCTraceDPI( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104464:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104464 | module MemPMCTraceDPI( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104514:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104514 | module MTraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:1:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 1 | module tag_array_ext( input [4:0] RW0_addr, + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 19 | module array_0_0_ext( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:37:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 37 | module bbtile_icache_tag_array_ext( input [5:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:55:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 55 | module bbtile_icache_data_arrays_0_ext( input [7:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:73:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 73 | module robOperands_ext( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:90:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 90 | module sram_ext( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 107 | module mem_ext( input [9:0] RW0_addr, + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:3:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3 | module axi_smoke_memory #( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:52:20: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'addr' generates 31 bits. + : ... note: In instance 'tb.peripherals_model' + 52 | offset=(addr & ~(LANES-1))-BASE; + | ^ + ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=5.050 + ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:78:28: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'write_addr' generates 31 bits. + : ... note: In instance 'tb.peripherals_model' + 78 | offset=(write_addr & ~(LANES-1))-BASE; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:86:26: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'h600d600d' generates 64 bits. + : ... note: In instance 'tb.memory_model' + 86 | if (w_bits_data==64'h600d600d) begin + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:91:66: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff' generates 64 bits. + : ... note: In instance 'tb.memory_model' + 91 | $fatal(1,"CPU smoke failed at stage %0d",w_bits_data & 64'hffff); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:90:28: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff0000' generates 64 bits. + : ... note: In instance 'tb.memory_model' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:90:43: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'hbad00000' generates 64 bits. + : ... note: In instance 'tb.memory_model' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^~ +make: Entering directory '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/obj' +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_timing.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_timing.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_threads.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_threads.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb__pch.h -o Vtb__pch.h.fast.gch +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb__pch.h -o Vtb__pch.h.slow.gch +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb__ConstPool__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__1__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__2__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__3__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb__Syms__Slow.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__0.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__1.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__2.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__3.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__4.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__5.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__6.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__7.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__8.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__9.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb__main.cpp +g++ verilated.o verilated_timing.o verilated_threads.o Vtb__ALL.a -pthread -lpthread -latomic -o Vtb +rm Vtb__ALL.verilator_deplist.tmp +make: Leaving directory '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/gemmini-tests/simulation/obj' +- V e r i l a t i o n R e p o r t: Verilator 5.050 2026-07-01 rev v5.050 +- Verilator: Built from 15.468 MB sources in 346 modules, into 23.746 MB in 19 C++ files needing 0.019 MB +- Verilator: Walltime 14.397 s (elab=0.569, cvt=3.434, bld=9.793); cpu 4.880 s on 8 threads; allocated 433.770 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/globalrob-check/GlobalRobCheck.sim.sv b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/globalrob-check/GlobalRobCheck.sim.sv new file mode 100644 index 0000000..ad7c124 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/globalrob-check/GlobalRobCheck.sim.sv @@ -0,0 +1,13682 @@ +// Generated by CIRCT firtool-1.62.1 +// Standard header to adapt well known macros for prints and assertions. + +// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. +`ifndef ASSERT_VERBOSE_COND_ + `ifdef ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) + `else // ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ 1 + `endif // ASSERT_VERBOSE_COND +`endif // not def ASSERT_VERBOSE_COND_ + +// Users can define 'STOP_COND' to add an extra gate to stop conditions. +`ifndef STOP_COND_ + `ifdef STOP_COND + `define STOP_COND_ (`STOP_COND) + `else // STOP_COND + `define STOP_COND_ 1 + `endif // STOP_COND +`endif // not def STOP_COND_ + +module BankAliasTable( + input clock, + reset, + io_alloc_valid, + input [3:0] io_alloc_rob_id, + input io_alloc_raw_rd_bank_0_valid, + input [9:0] io_alloc_raw_rd_bank_0_id, + input io_alloc_raw_rd_bank_1_valid, + input [9:0] io_alloc_raw_rd_bank_1_id, + input io_alloc_raw_wr_bank_valid, + input [9:0] io_alloc_raw_wr_bank_id, + output io_alloc_renamed_rd_bank_0_valid, + output [9:0] io_alloc_renamed_rd_bank_0_id, + output io_alloc_renamed_rd_bank_1_valid, + output [9:0] io_alloc_renamed_rd_bank_1_id, + output io_alloc_renamed_wr_bank_valid, + output [9:0] io_alloc_renamed_wr_bank_id, + input io_free_valid, + io_free_mask_0, + io_free_mask_1, + io_free_mask_2, + io_free_mask_3, + io_free_mask_4, + io_free_mask_5, + io_free_mask_6, + io_free_mask_7, + io_free_mask_8, + io_free_mask_9, + io_free_mask_10, + io_free_mask_11, + io_free_mask_12, + io_free_mask_13, + io_free_mask_14, + io_free_mask_15 +); + + reg [9:0] v2a_0; + reg [9:0] v2a_1; + reg [9:0] v2a_2; + reg [9:0] v2a_3; + reg [9:0] v2a_4; + reg [9:0] v2a_5; + reg [9:0] v2a_6; + reg [9:0] v2a_7; + reg [9:0] v2a_8; + reg [9:0] v2a_9; + reg [9:0] v2a_10; + reg [9:0] v2a_11; + reg [9:0] v2a_12; + reg [9:0] v2a_13; + reg [9:0] v2a_14; + reg [9:0] v2a_15; + reg aliasInUse_0; + reg aliasInUse_1; + reg aliasInUse_2; + reg aliasInUse_3; + reg aliasInUse_4; + reg aliasInUse_5; + reg aliasInUse_6; + reg aliasInUse_7; + reg aliasInUse_8; + reg aliasInUse_9; + reg aliasInUse_10; + reg aliasInUse_11; + reg aliasInUse_12; + reg aliasInUse_13; + reg aliasInUse_14; + reg aliasInUse_15; + reg entHasWrite_0; + reg entHasWrite_1; + reg entHasWrite_2; + reg entHasWrite_3; + reg entHasWrite_4; + reg entHasWrite_5; + reg entHasWrite_6; + reg entHasWrite_7; + reg entHasWrite_8; + reg entHasWrite_9; + reg entHasWrite_10; + reg entHasWrite_11; + reg entHasWrite_12; + reg entHasWrite_13; + reg entHasWrite_14; + reg entHasWrite_15; + reg [9:0] entNewAlias_0; + reg [9:0] entNewAlias_1; + reg [9:0] entNewAlias_2; + reg [9:0] entNewAlias_3; + reg [9:0] entNewAlias_4; + reg [9:0] entNewAlias_5; + reg [9:0] entNewAlias_6; + reg [9:0] entNewAlias_7; + reg [9:0] entNewAlias_8; + reg [9:0] entNewAlias_9; + reg [9:0] entNewAlias_10; + reg [9:0] entNewAlias_11; + reg [9:0] entNewAlias_12; + reg [9:0] entNewAlias_13; + reg [9:0] entNewAlias_14; + reg [9:0] entNewAlias_15; + reg [3:0] entWrVbank_0; + reg [3:0] entWrVbank_1; + reg [3:0] entWrVbank_2; + reg [3:0] entWrVbank_3; + reg [3:0] entWrVbank_4; + reg [3:0] entWrVbank_5; + reg [3:0] entWrVbank_6; + reg [3:0] entWrVbank_7; + reg [3:0] entWrVbank_8; + reg [3:0] entWrVbank_9; + reg [3:0] entWrVbank_10; + reg [3:0] entWrVbank_11; + reg [3:0] entWrVbank_12; + reg [3:0] entWrVbank_13; + reg [3:0] entWrVbank_14; + reg [3:0] entWrVbank_15; + wire [15:0][9:0] _GEN = + {{v2a_15}, + {v2a_14}, + {v2a_13}, + {v2a_12}, + {v2a_11}, + {v2a_10}, + {v2a_9}, + {v2a_8}, + {v2a_7}, + {v2a_6}, + {v2a_5}, + {v2a_4}, + {v2a_3}, + {v2a_2}, + {v2a_1}, + {v2a_0}}; + wire [9:0] _v2a_T = {6'h0, io_alloc_rob_id} + 10'h10; + wire _GEN_0 = io_free_valid & io_free_mask_0; + wire _GEN_1 = io_free_valid & io_free_mask_1; + wire _GEN_2 = io_free_valid & io_free_mask_2; + wire _GEN_3 = io_free_valid & io_free_mask_3; + wire _GEN_4 = io_free_valid & io_free_mask_4; + wire _GEN_5 = io_free_valid & io_free_mask_5; + wire _GEN_6 = io_free_valid & io_free_mask_6; + wire _GEN_7 = io_free_valid & io_free_mask_7; + wire _GEN_8 = io_free_valid & io_free_mask_8; + wire _GEN_9 = io_free_valid & io_free_mask_9; + wire _GEN_10 = io_free_valid & io_free_mask_10; + wire _GEN_11 = io_free_valid & io_free_mask_11; + wire _GEN_12 = io_free_valid & io_free_mask_12; + wire _GEN_13 = io_free_valid & io_free_mask_13; + wire _GEN_14 = io_free_valid & io_free_mask_14; + wire _GEN_15 = io_free_valid & io_free_mask_15; + `ifndef SYNTHESIS + always @(posedge clock) begin + automatic logic [15:0] _GEN_16 = + {{aliasInUse_15}, + {aliasInUse_14}, + {aliasInUse_13}, + {aliasInUse_12}, + {aliasInUse_11}, + {aliasInUse_10}, + {aliasInUse_9}, + {aliasInUse_8}, + {aliasInUse_7}, + {aliasInUse_6}, + {aliasInUse_5}, + {aliasInUse_4}, + {aliasInUse_3}, + {aliasInUse_2}, + {aliasInUse_1}, + {aliasInUse_0}}; + if (io_alloc_valid & io_alloc_raw_wr_bank_valid & ~reset + & _GEN_16[io_alloc_rob_id]) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: BAT alias reused before free\n at BankAliasTable.scala:101 assert(!aliasInUse(rid), \"BAT alias reused before free\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_0 & entHasWrite_0 & ~reset & ~aliasInUse_0) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: BAT free on non-allocated alias\n at BankAliasTable.scala:111 assert(aliasInUse(i), \"BAT free on non-allocated alias\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_1 & entHasWrite_1 & ~reset & ~aliasInUse_1) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: BAT free on non-allocated alias\n at BankAliasTable.scala:111 assert(aliasInUse(i), \"BAT free on non-allocated alias\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_2 & entHasWrite_2 & ~reset & ~aliasInUse_2) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: BAT free on non-allocated alias\n at BankAliasTable.scala:111 assert(aliasInUse(i), \"BAT free on non-allocated alias\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_3 & entHasWrite_3 & ~reset & ~aliasInUse_3) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: BAT free on non-allocated alias\n at BankAliasTable.scala:111 assert(aliasInUse(i), \"BAT free on non-allocated alias\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_4 & entHasWrite_4 & ~reset & ~aliasInUse_4) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: BAT free on non-allocated alias\n at BankAliasTable.scala:111 assert(aliasInUse(i), \"BAT free on non-allocated alias\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_5 & entHasWrite_5 & ~reset & ~aliasInUse_5) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: BAT free on non-allocated alias\n at BankAliasTable.scala:111 assert(aliasInUse(i), \"BAT free on non-allocated alias\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_6 & entHasWrite_6 & ~reset & ~aliasInUse_6) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: BAT free on non-allocated alias\n at BankAliasTable.scala:111 assert(aliasInUse(i), \"BAT free on non-allocated alias\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_7 & entHasWrite_7 & ~reset & ~aliasInUse_7) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: BAT free on non-allocated alias\n at BankAliasTable.scala:111 assert(aliasInUse(i), \"BAT free on non-allocated alias\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_8 & entHasWrite_8 & ~reset & ~aliasInUse_8) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: BAT free on non-allocated alias\n at BankAliasTable.scala:111 assert(aliasInUse(i), \"BAT free on non-allocated alias\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_9 & entHasWrite_9 & ~reset & ~aliasInUse_9) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: BAT free on non-allocated alias\n at BankAliasTable.scala:111 assert(aliasInUse(i), \"BAT free on non-allocated alias\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_10 & entHasWrite_10 & ~reset & ~aliasInUse_10) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: BAT free on non-allocated alias\n at BankAliasTable.scala:111 assert(aliasInUse(i), \"BAT free on non-allocated alias\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_11 & entHasWrite_11 & ~reset & ~aliasInUse_11) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: BAT free on non-allocated alias\n at BankAliasTable.scala:111 assert(aliasInUse(i), \"BAT free on non-allocated alias\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_12 & entHasWrite_12 & ~reset & ~aliasInUse_12) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: BAT free on non-allocated alias\n at BankAliasTable.scala:111 assert(aliasInUse(i), \"BAT free on non-allocated alias\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_13 & entHasWrite_13 & ~reset & ~aliasInUse_13) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: BAT free on non-allocated alias\n at BankAliasTable.scala:111 assert(aliasInUse(i), \"BAT free on non-allocated alias\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_14 & entHasWrite_14 & ~reset & ~aliasInUse_14) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: BAT free on non-allocated alias\n at BankAliasTable.scala:111 assert(aliasInUse(i), \"BAT free on non-allocated alias\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_15 & entHasWrite_15 & ~reset & ~aliasInUse_15) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: BAT free on non-allocated alias\n at BankAliasTable.scala:111 assert(aliasInUse(i), \"BAT free on non-allocated alias\")\n"); + if (`STOP_COND_) + $fatal; + end + end // always @(posedge) + `endif // not def SYNTHESIS + always @(posedge clock) begin + if (reset) begin + v2a_0 <= 10'h0; + v2a_1 <= 10'h1; + v2a_2 <= 10'h2; + v2a_3 <= 10'h3; + v2a_4 <= 10'h4; + v2a_5 <= 10'h5; + v2a_6 <= 10'h6; + v2a_7 <= 10'h7; + v2a_8 <= 10'h8; + v2a_9 <= 10'h9; + v2a_10 <= 10'hA; + v2a_11 <= 10'hB; + v2a_12 <= 10'hC; + v2a_13 <= 10'hD; + v2a_14 <= 10'hE; + v2a_15 <= 10'hF; + aliasInUse_0 <= 1'h0; + aliasInUse_1 <= 1'h0; + aliasInUse_2 <= 1'h0; + aliasInUse_3 <= 1'h0; + aliasInUse_4 <= 1'h0; + aliasInUse_5 <= 1'h0; + aliasInUse_6 <= 1'h0; + aliasInUse_7 <= 1'h0; + aliasInUse_8 <= 1'h0; + aliasInUse_9 <= 1'h0; + aliasInUse_10 <= 1'h0; + aliasInUse_11 <= 1'h0; + aliasInUse_12 <= 1'h0; + aliasInUse_13 <= 1'h0; + aliasInUse_14 <= 1'h0; + aliasInUse_15 <= 1'h0; + entHasWrite_0 <= 1'h0; + entHasWrite_1 <= 1'h0; + entHasWrite_2 <= 1'h0; + entHasWrite_3 <= 1'h0; + entHasWrite_4 <= 1'h0; + entHasWrite_5 <= 1'h0; + entHasWrite_6 <= 1'h0; + entHasWrite_7 <= 1'h0; + entHasWrite_8 <= 1'h0; + entHasWrite_9 <= 1'h0; + entHasWrite_10 <= 1'h0; + entHasWrite_11 <= 1'h0; + entHasWrite_12 <= 1'h0; + entHasWrite_13 <= 1'h0; + entHasWrite_14 <= 1'h0; + entHasWrite_15 <= 1'h0; + entNewAlias_0 <= 10'h0; + entNewAlias_1 <= 10'h0; + entNewAlias_2 <= 10'h0; + entNewAlias_3 <= 10'h0; + entNewAlias_4 <= 10'h0; + entNewAlias_5 <= 10'h0; + entNewAlias_6 <= 10'h0; + entNewAlias_7 <= 10'h0; + entNewAlias_8 <= 10'h0; + entNewAlias_9 <= 10'h0; + entNewAlias_10 <= 10'h0; + entNewAlias_11 <= 10'h0; + entNewAlias_12 <= 10'h0; + entNewAlias_13 <= 10'h0; + entNewAlias_14 <= 10'h0; + entNewAlias_15 <= 10'h0; + entWrVbank_0 <= 4'h0; + entWrVbank_1 <= 4'h0; + entWrVbank_2 <= 4'h0; + entWrVbank_3 <= 4'h0; + entWrVbank_4 <= 4'h0; + entWrVbank_5 <= 4'h0; + entWrVbank_6 <= 4'h0; + entWrVbank_7 <= 4'h0; + entWrVbank_8 <= 4'h0; + entWrVbank_9 <= 4'h0; + entWrVbank_10 <= 4'h0; + entWrVbank_11 <= 4'h0; + entWrVbank_12 <= 4'h0; + entWrVbank_13 <= 4'h0; + entWrVbank_14 <= 4'h0; + entWrVbank_15 <= 4'h0; + end + else begin + automatic logic _GEN_17 = io_alloc_rob_id == 4'h0; + automatic logic _GEN_18; + automatic logic _GEN_19 = io_alloc_rob_id == 4'h1; + automatic logic _GEN_20; + automatic logic _GEN_21 = io_alloc_rob_id == 4'h2; + automatic logic _GEN_22; + automatic logic _GEN_23 = io_alloc_rob_id == 4'h3; + automatic logic _GEN_24; + automatic logic _GEN_25 = io_alloc_rob_id == 4'h4; + automatic logic _GEN_26; + automatic logic _GEN_27 = io_alloc_rob_id == 4'h5; + automatic logic _GEN_28; + automatic logic _GEN_29 = io_alloc_rob_id == 4'h6; + automatic logic _GEN_30; + automatic logic _GEN_31 = io_alloc_rob_id == 4'h7; + automatic logic _GEN_32; + automatic logic _GEN_33 = io_alloc_rob_id == 4'h8; + automatic logic _GEN_34; + automatic logic _GEN_35 = io_alloc_rob_id == 4'h9; + automatic logic _GEN_36; + automatic logic _GEN_37 = io_alloc_rob_id == 4'hA; + automatic logic _GEN_38; + automatic logic _GEN_39 = io_alloc_rob_id == 4'hB; + automatic logic _GEN_40; + automatic logic _GEN_41 = io_alloc_rob_id == 4'hC; + automatic logic _GEN_42; + automatic logic _GEN_43 = io_alloc_rob_id == 4'hD; + automatic logic _GEN_44; + automatic logic _GEN_45 = io_alloc_rob_id == 4'hE; + automatic logic _GEN_46; + automatic logic _GEN_47; + automatic logic [9:0] _entNewAlias_T_2; + automatic logic _GEN_48; + automatic logic _GEN_49; + automatic logic _GEN_50; + automatic logic _GEN_51; + automatic logic _GEN_52; + automatic logic _GEN_53; + automatic logic _GEN_54; + automatic logic _GEN_55; + automatic logic _GEN_56; + automatic logic _GEN_57; + automatic logic _GEN_58; + automatic logic _GEN_59; + automatic logic _GEN_60; + automatic logic _GEN_61; + automatic logic _GEN_62; + automatic logic _GEN_63; + _GEN_18 = io_alloc_valid & _GEN_17; + _GEN_20 = io_alloc_valid & _GEN_19; + _GEN_22 = io_alloc_valid & _GEN_21; + _GEN_24 = io_alloc_valid & _GEN_23; + _GEN_26 = io_alloc_valid & _GEN_25; + _GEN_28 = io_alloc_valid & _GEN_27; + _GEN_30 = io_alloc_valid & _GEN_29; + _GEN_32 = io_alloc_valid & _GEN_31; + _GEN_34 = io_alloc_valid & _GEN_33; + _GEN_36 = io_alloc_valid & _GEN_35; + _GEN_38 = io_alloc_valid & _GEN_37; + _GEN_40 = io_alloc_valid & _GEN_39; + _GEN_42 = io_alloc_valid & _GEN_41; + _GEN_44 = io_alloc_valid & _GEN_43; + _GEN_46 = io_alloc_valid & _GEN_45; + _GEN_47 = io_alloc_valid & (&io_alloc_rob_id); + _entNewAlias_T_2 = io_alloc_raw_wr_bank_valid ? _v2a_T : 10'h0; + _GEN_48 = + io_alloc_valid & io_alloc_raw_wr_bank_valid + & io_alloc_raw_wr_bank_id[3:0] == 4'h0; + _GEN_49 = + io_alloc_valid & io_alloc_raw_wr_bank_valid + & io_alloc_raw_wr_bank_id[3:0] == 4'h1; + _GEN_50 = + io_alloc_valid & io_alloc_raw_wr_bank_valid + & io_alloc_raw_wr_bank_id[3:0] == 4'h2; + _GEN_51 = + io_alloc_valid & io_alloc_raw_wr_bank_valid + & io_alloc_raw_wr_bank_id[3:0] == 4'h3; + _GEN_52 = + io_alloc_valid & io_alloc_raw_wr_bank_valid + & io_alloc_raw_wr_bank_id[3:0] == 4'h4; + _GEN_53 = + io_alloc_valid & io_alloc_raw_wr_bank_valid + & io_alloc_raw_wr_bank_id[3:0] == 4'h5; + _GEN_54 = + io_alloc_valid & io_alloc_raw_wr_bank_valid + & io_alloc_raw_wr_bank_id[3:0] == 4'h6; + _GEN_55 = + io_alloc_valid & io_alloc_raw_wr_bank_valid + & io_alloc_raw_wr_bank_id[3:0] == 4'h7; + _GEN_56 = + io_alloc_valid & io_alloc_raw_wr_bank_valid + & io_alloc_raw_wr_bank_id[3:0] == 4'h8; + _GEN_57 = + io_alloc_valid & io_alloc_raw_wr_bank_valid + & io_alloc_raw_wr_bank_id[3:0] == 4'h9; + _GEN_58 = + io_alloc_valid & io_alloc_raw_wr_bank_valid + & io_alloc_raw_wr_bank_id[3:0] == 4'hA; + _GEN_59 = + io_alloc_valid & io_alloc_raw_wr_bank_valid + & io_alloc_raw_wr_bank_id[3:0] == 4'hB; + _GEN_60 = + io_alloc_valid & io_alloc_raw_wr_bank_valid + & io_alloc_raw_wr_bank_id[3:0] == 4'hC; + _GEN_61 = + io_alloc_valid & io_alloc_raw_wr_bank_valid + & io_alloc_raw_wr_bank_id[3:0] == 4'hD; + _GEN_62 = + io_alloc_valid & io_alloc_raw_wr_bank_valid + & io_alloc_raw_wr_bank_id[3:0] == 4'hE; + _GEN_63 = + io_alloc_valid & io_alloc_raw_wr_bank_valid & (&(io_alloc_raw_wr_bank_id[3:0])); + if (io_free_valid) begin + automatic logic _GEN_64; + automatic logic [9:0] _GEN_65; + automatic logic _GEN_66; + automatic logic [9:0] _GEN_67; + automatic logic _GEN_68; + automatic logic [9:0] _GEN_69; + automatic logic _GEN_70; + automatic logic [9:0] _GEN_71; + automatic logic _GEN_72; + automatic logic [9:0] _GEN_73; + automatic logic _GEN_74; + automatic logic [9:0] _GEN_75; + automatic logic _GEN_76; + automatic logic [9:0] _GEN_77; + automatic logic _GEN_78; + automatic logic [9:0] _GEN_79; + automatic logic _GEN_80; + automatic logic [9:0] _GEN_81; + automatic logic _GEN_82; + automatic logic [9:0] _GEN_83; + automatic logic _GEN_84; + automatic logic [9:0] _GEN_85; + automatic logic _GEN_86; + automatic logic [9:0] _GEN_87; + automatic logic _GEN_88; + automatic logic [9:0] _GEN_89; + automatic logic _GEN_90; + automatic logic [9:0] _GEN_91; + automatic logic _GEN_92; + automatic logic [9:0] _GEN_93; + automatic logic _GEN_94 = _GEN[entWrVbank_15] == entNewAlias_15; + automatic logic [9:0] _GEN_95; + _GEN_64 = _GEN[entWrVbank_0] == entNewAlias_0; + _GEN_65 = {6'h0, entWrVbank_0}; + _GEN_66 = _GEN[entWrVbank_1] == entNewAlias_1; + _GEN_67 = {6'h0, entWrVbank_1}; + _GEN_68 = _GEN[entWrVbank_2] == entNewAlias_2; + _GEN_69 = {6'h0, entWrVbank_2}; + _GEN_70 = _GEN[entWrVbank_3] == entNewAlias_3; + _GEN_71 = {6'h0, entWrVbank_3}; + _GEN_72 = _GEN[entWrVbank_4] == entNewAlias_4; + _GEN_73 = {6'h0, entWrVbank_4}; + _GEN_74 = _GEN[entWrVbank_5] == entNewAlias_5; + _GEN_75 = {6'h0, entWrVbank_5}; + _GEN_76 = _GEN[entWrVbank_6] == entNewAlias_6; + _GEN_77 = {6'h0, entWrVbank_6}; + _GEN_78 = _GEN[entWrVbank_7] == entNewAlias_7; + _GEN_79 = {6'h0, entWrVbank_7}; + _GEN_80 = _GEN[entWrVbank_8] == entNewAlias_8; + _GEN_81 = {6'h0, entWrVbank_8}; + _GEN_82 = _GEN[entWrVbank_9] == entNewAlias_9; + _GEN_83 = {6'h0, entWrVbank_9}; + _GEN_84 = _GEN[entWrVbank_10] == entNewAlias_10; + _GEN_85 = {6'h0, entWrVbank_10}; + _GEN_86 = _GEN[entWrVbank_11] == entNewAlias_11; + _GEN_87 = {6'h0, entWrVbank_11}; + _GEN_88 = _GEN[entWrVbank_12] == entNewAlias_12; + _GEN_89 = {6'h0, entWrVbank_12}; + _GEN_90 = _GEN[entWrVbank_13] == entNewAlias_13; + _GEN_91 = {6'h0, entWrVbank_13}; + _GEN_92 = _GEN[entWrVbank_14] == entNewAlias_14; + _GEN_93 = {6'h0, entWrVbank_14}; + _GEN_95 = {6'h0, entWrVbank_15}; + if (io_free_mask_15 & entHasWrite_15 & _GEN_94 & entWrVbank_15 == 4'h0) + v2a_0 <= _GEN_95; + else if (io_free_mask_14 & entHasWrite_14 & _GEN_92 & entWrVbank_14 == 4'h0) + v2a_0 <= _GEN_93; + else if (io_free_mask_13 & entHasWrite_13 & _GEN_90 & entWrVbank_13 == 4'h0) + v2a_0 <= _GEN_91; + else if (io_free_mask_12 & entHasWrite_12 & _GEN_88 & entWrVbank_12 == 4'h0) + v2a_0 <= _GEN_89; + else if (io_free_mask_11 & entHasWrite_11 & _GEN_86 & entWrVbank_11 == 4'h0) + v2a_0 <= _GEN_87; + else if (io_free_mask_10 & entHasWrite_10 & _GEN_84 & entWrVbank_10 == 4'h0) + v2a_0 <= _GEN_85; + else if (io_free_mask_9 & entHasWrite_9 & _GEN_82 & entWrVbank_9 == 4'h0) + v2a_0 <= _GEN_83; + else if (io_free_mask_8 & entHasWrite_8 & _GEN_80 & entWrVbank_8 == 4'h0) + v2a_0 <= _GEN_81; + else if (io_free_mask_7 & entHasWrite_7 & _GEN_78 & entWrVbank_7 == 4'h0) + v2a_0 <= _GEN_79; + else if (io_free_mask_6 & entHasWrite_6 & _GEN_76 & entWrVbank_6 == 4'h0) + v2a_0 <= _GEN_77; + else if (io_free_mask_5 & entHasWrite_5 & _GEN_74 & entWrVbank_5 == 4'h0) + v2a_0 <= _GEN_75; + else if (io_free_mask_4 & entHasWrite_4 & _GEN_72 & entWrVbank_4 == 4'h0) + v2a_0 <= _GEN_73; + else if (io_free_mask_3 & entHasWrite_3 & _GEN_70 & entWrVbank_3 == 4'h0) + v2a_0 <= _GEN_71; + else if (io_free_mask_2 & entHasWrite_2 & _GEN_68 & entWrVbank_2 == 4'h0) + v2a_0 <= _GEN_69; + else if (io_free_mask_1 & entHasWrite_1 & _GEN_66 & entWrVbank_1 == 4'h0) + v2a_0 <= _GEN_67; + else if (io_free_mask_0 & entHasWrite_0 & _GEN_64 & entWrVbank_0 == 4'h0) + v2a_0 <= _GEN_65; + else if (_GEN_48) + v2a_0 <= _v2a_T; + if (io_free_mask_15 & entHasWrite_15 & _GEN_94 & entWrVbank_15 == 4'h1) + v2a_1 <= _GEN_95; + else if (io_free_mask_14 & entHasWrite_14 & _GEN_92 & entWrVbank_14 == 4'h1) + v2a_1 <= _GEN_93; + else if (io_free_mask_13 & entHasWrite_13 & _GEN_90 & entWrVbank_13 == 4'h1) + v2a_1 <= _GEN_91; + else if (io_free_mask_12 & entHasWrite_12 & _GEN_88 & entWrVbank_12 == 4'h1) + v2a_1 <= _GEN_89; + else if (io_free_mask_11 & entHasWrite_11 & _GEN_86 & entWrVbank_11 == 4'h1) + v2a_1 <= _GEN_87; + else if (io_free_mask_10 & entHasWrite_10 & _GEN_84 & entWrVbank_10 == 4'h1) + v2a_1 <= _GEN_85; + else if (io_free_mask_9 & entHasWrite_9 & _GEN_82 & entWrVbank_9 == 4'h1) + v2a_1 <= _GEN_83; + else if (io_free_mask_8 & entHasWrite_8 & _GEN_80 & entWrVbank_8 == 4'h1) + v2a_1 <= _GEN_81; + else if (io_free_mask_7 & entHasWrite_7 & _GEN_78 & entWrVbank_7 == 4'h1) + v2a_1 <= _GEN_79; + else if (io_free_mask_6 & entHasWrite_6 & _GEN_76 & entWrVbank_6 == 4'h1) + v2a_1 <= _GEN_77; + else if (io_free_mask_5 & entHasWrite_5 & _GEN_74 & entWrVbank_5 == 4'h1) + v2a_1 <= _GEN_75; + else if (io_free_mask_4 & entHasWrite_4 & _GEN_72 & entWrVbank_4 == 4'h1) + v2a_1 <= _GEN_73; + else if (io_free_mask_3 & entHasWrite_3 & _GEN_70 & entWrVbank_3 == 4'h1) + v2a_1 <= _GEN_71; + else if (io_free_mask_2 & entHasWrite_2 & _GEN_68 & entWrVbank_2 == 4'h1) + v2a_1 <= _GEN_69; + else if (io_free_mask_1 & entHasWrite_1 & _GEN_66 & entWrVbank_1 == 4'h1) + v2a_1 <= _GEN_67; + else if (io_free_mask_0 & entHasWrite_0 & _GEN_64 & entWrVbank_0 == 4'h1) + v2a_1 <= _GEN_65; + else if (_GEN_49) + v2a_1 <= _v2a_T; + if (io_free_mask_15 & entHasWrite_15 & _GEN_94 & entWrVbank_15 == 4'h2) + v2a_2 <= _GEN_95; + else if (io_free_mask_14 & entHasWrite_14 & _GEN_92 & entWrVbank_14 == 4'h2) + v2a_2 <= _GEN_93; + else if (io_free_mask_13 & entHasWrite_13 & _GEN_90 & entWrVbank_13 == 4'h2) + v2a_2 <= _GEN_91; + else if (io_free_mask_12 & entHasWrite_12 & _GEN_88 & entWrVbank_12 == 4'h2) + v2a_2 <= _GEN_89; + else if (io_free_mask_11 & entHasWrite_11 & _GEN_86 & entWrVbank_11 == 4'h2) + v2a_2 <= _GEN_87; + else if (io_free_mask_10 & entHasWrite_10 & _GEN_84 & entWrVbank_10 == 4'h2) + v2a_2 <= _GEN_85; + else if (io_free_mask_9 & entHasWrite_9 & _GEN_82 & entWrVbank_9 == 4'h2) + v2a_2 <= _GEN_83; + else if (io_free_mask_8 & entHasWrite_8 & _GEN_80 & entWrVbank_8 == 4'h2) + v2a_2 <= _GEN_81; + else if (io_free_mask_7 & entHasWrite_7 & _GEN_78 & entWrVbank_7 == 4'h2) + v2a_2 <= _GEN_79; + else if (io_free_mask_6 & entHasWrite_6 & _GEN_76 & entWrVbank_6 == 4'h2) + v2a_2 <= _GEN_77; + else if (io_free_mask_5 & entHasWrite_5 & _GEN_74 & entWrVbank_5 == 4'h2) + v2a_2 <= _GEN_75; + else if (io_free_mask_4 & entHasWrite_4 & _GEN_72 & entWrVbank_4 == 4'h2) + v2a_2 <= _GEN_73; + else if (io_free_mask_3 & entHasWrite_3 & _GEN_70 & entWrVbank_3 == 4'h2) + v2a_2 <= _GEN_71; + else if (io_free_mask_2 & entHasWrite_2 & _GEN_68 & entWrVbank_2 == 4'h2) + v2a_2 <= _GEN_69; + else if (io_free_mask_1 & entHasWrite_1 & _GEN_66 & entWrVbank_1 == 4'h2) + v2a_2 <= _GEN_67; + else if (io_free_mask_0 & entHasWrite_0 & _GEN_64 & entWrVbank_0 == 4'h2) + v2a_2 <= _GEN_65; + else if (_GEN_50) + v2a_2 <= _v2a_T; + if (io_free_mask_15 & entHasWrite_15 & _GEN_94 & entWrVbank_15 == 4'h3) + v2a_3 <= _GEN_95; + else if (io_free_mask_14 & entHasWrite_14 & _GEN_92 & entWrVbank_14 == 4'h3) + v2a_3 <= _GEN_93; + else if (io_free_mask_13 & entHasWrite_13 & _GEN_90 & entWrVbank_13 == 4'h3) + v2a_3 <= _GEN_91; + else if (io_free_mask_12 & entHasWrite_12 & _GEN_88 & entWrVbank_12 == 4'h3) + v2a_3 <= _GEN_89; + else if (io_free_mask_11 & entHasWrite_11 & _GEN_86 & entWrVbank_11 == 4'h3) + v2a_3 <= _GEN_87; + else if (io_free_mask_10 & entHasWrite_10 & _GEN_84 & entWrVbank_10 == 4'h3) + v2a_3 <= _GEN_85; + else if (io_free_mask_9 & entHasWrite_9 & _GEN_82 & entWrVbank_9 == 4'h3) + v2a_3 <= _GEN_83; + else if (io_free_mask_8 & entHasWrite_8 & _GEN_80 & entWrVbank_8 == 4'h3) + v2a_3 <= _GEN_81; + else if (io_free_mask_7 & entHasWrite_7 & _GEN_78 & entWrVbank_7 == 4'h3) + v2a_3 <= _GEN_79; + else if (io_free_mask_6 & entHasWrite_6 & _GEN_76 & entWrVbank_6 == 4'h3) + v2a_3 <= _GEN_77; + else if (io_free_mask_5 & entHasWrite_5 & _GEN_74 & entWrVbank_5 == 4'h3) + v2a_3 <= _GEN_75; + else if (io_free_mask_4 & entHasWrite_4 & _GEN_72 & entWrVbank_4 == 4'h3) + v2a_3 <= _GEN_73; + else if (io_free_mask_3 & entHasWrite_3 & _GEN_70 & entWrVbank_3 == 4'h3) + v2a_3 <= _GEN_71; + else if (io_free_mask_2 & entHasWrite_2 & _GEN_68 & entWrVbank_2 == 4'h3) + v2a_3 <= _GEN_69; + else if (io_free_mask_1 & entHasWrite_1 & _GEN_66 & entWrVbank_1 == 4'h3) + v2a_3 <= _GEN_67; + else if (io_free_mask_0 & entHasWrite_0 & _GEN_64 & entWrVbank_0 == 4'h3) + v2a_3 <= _GEN_65; + else if (_GEN_51) + v2a_3 <= _v2a_T; + if (io_free_mask_15 & entHasWrite_15 & _GEN_94 & entWrVbank_15 == 4'h4) + v2a_4 <= _GEN_95; + else if (io_free_mask_14 & entHasWrite_14 & _GEN_92 & entWrVbank_14 == 4'h4) + v2a_4 <= _GEN_93; + else if (io_free_mask_13 & entHasWrite_13 & _GEN_90 & entWrVbank_13 == 4'h4) + v2a_4 <= _GEN_91; + else if (io_free_mask_12 & entHasWrite_12 & _GEN_88 & entWrVbank_12 == 4'h4) + v2a_4 <= _GEN_89; + else if (io_free_mask_11 & entHasWrite_11 & _GEN_86 & entWrVbank_11 == 4'h4) + v2a_4 <= _GEN_87; + else if (io_free_mask_10 & entHasWrite_10 & _GEN_84 & entWrVbank_10 == 4'h4) + v2a_4 <= _GEN_85; + else if (io_free_mask_9 & entHasWrite_9 & _GEN_82 & entWrVbank_9 == 4'h4) + v2a_4 <= _GEN_83; + else if (io_free_mask_8 & entHasWrite_8 & _GEN_80 & entWrVbank_8 == 4'h4) + v2a_4 <= _GEN_81; + else if (io_free_mask_7 & entHasWrite_7 & _GEN_78 & entWrVbank_7 == 4'h4) + v2a_4 <= _GEN_79; + else if (io_free_mask_6 & entHasWrite_6 & _GEN_76 & entWrVbank_6 == 4'h4) + v2a_4 <= _GEN_77; + else if (io_free_mask_5 & entHasWrite_5 & _GEN_74 & entWrVbank_5 == 4'h4) + v2a_4 <= _GEN_75; + else if (io_free_mask_4 & entHasWrite_4 & _GEN_72 & entWrVbank_4 == 4'h4) + v2a_4 <= _GEN_73; + else if (io_free_mask_3 & entHasWrite_3 & _GEN_70 & entWrVbank_3 == 4'h4) + v2a_4 <= _GEN_71; + else if (io_free_mask_2 & entHasWrite_2 & _GEN_68 & entWrVbank_2 == 4'h4) + v2a_4 <= _GEN_69; + else if (io_free_mask_1 & entHasWrite_1 & _GEN_66 & entWrVbank_1 == 4'h4) + v2a_4 <= _GEN_67; + else if (io_free_mask_0 & entHasWrite_0 & _GEN_64 & entWrVbank_0 == 4'h4) + v2a_4 <= _GEN_65; + else if (_GEN_52) + v2a_4 <= _v2a_T; + if (io_free_mask_15 & entHasWrite_15 & _GEN_94 & entWrVbank_15 == 4'h5) + v2a_5 <= _GEN_95; + else if (io_free_mask_14 & entHasWrite_14 & _GEN_92 & entWrVbank_14 == 4'h5) + v2a_5 <= _GEN_93; + else if (io_free_mask_13 & entHasWrite_13 & _GEN_90 & entWrVbank_13 == 4'h5) + v2a_5 <= _GEN_91; + else if (io_free_mask_12 & entHasWrite_12 & _GEN_88 & entWrVbank_12 == 4'h5) + v2a_5 <= _GEN_89; + else if (io_free_mask_11 & entHasWrite_11 & _GEN_86 & entWrVbank_11 == 4'h5) + v2a_5 <= _GEN_87; + else if (io_free_mask_10 & entHasWrite_10 & _GEN_84 & entWrVbank_10 == 4'h5) + v2a_5 <= _GEN_85; + else if (io_free_mask_9 & entHasWrite_9 & _GEN_82 & entWrVbank_9 == 4'h5) + v2a_5 <= _GEN_83; + else if (io_free_mask_8 & entHasWrite_8 & _GEN_80 & entWrVbank_8 == 4'h5) + v2a_5 <= _GEN_81; + else if (io_free_mask_7 & entHasWrite_7 & _GEN_78 & entWrVbank_7 == 4'h5) + v2a_5 <= _GEN_79; + else if (io_free_mask_6 & entHasWrite_6 & _GEN_76 & entWrVbank_6 == 4'h5) + v2a_5 <= _GEN_77; + else if (io_free_mask_5 & entHasWrite_5 & _GEN_74 & entWrVbank_5 == 4'h5) + v2a_5 <= _GEN_75; + else if (io_free_mask_4 & entHasWrite_4 & _GEN_72 & entWrVbank_4 == 4'h5) + v2a_5 <= _GEN_73; + else if (io_free_mask_3 & entHasWrite_3 & _GEN_70 & entWrVbank_3 == 4'h5) + v2a_5 <= _GEN_71; + else if (io_free_mask_2 & entHasWrite_2 & _GEN_68 & entWrVbank_2 == 4'h5) + v2a_5 <= _GEN_69; + else if (io_free_mask_1 & entHasWrite_1 & _GEN_66 & entWrVbank_1 == 4'h5) + v2a_5 <= _GEN_67; + else if (io_free_mask_0 & entHasWrite_0 & _GEN_64 & entWrVbank_0 == 4'h5) + v2a_5 <= _GEN_65; + else if (_GEN_53) + v2a_5 <= _v2a_T; + if (io_free_mask_15 & entHasWrite_15 & _GEN_94 & entWrVbank_15 == 4'h6) + v2a_6 <= _GEN_95; + else if (io_free_mask_14 & entHasWrite_14 & _GEN_92 & entWrVbank_14 == 4'h6) + v2a_6 <= _GEN_93; + else if (io_free_mask_13 & entHasWrite_13 & _GEN_90 & entWrVbank_13 == 4'h6) + v2a_6 <= _GEN_91; + else if (io_free_mask_12 & entHasWrite_12 & _GEN_88 & entWrVbank_12 == 4'h6) + v2a_6 <= _GEN_89; + else if (io_free_mask_11 & entHasWrite_11 & _GEN_86 & entWrVbank_11 == 4'h6) + v2a_6 <= _GEN_87; + else if (io_free_mask_10 & entHasWrite_10 & _GEN_84 & entWrVbank_10 == 4'h6) + v2a_6 <= _GEN_85; + else if (io_free_mask_9 & entHasWrite_9 & _GEN_82 & entWrVbank_9 == 4'h6) + v2a_6 <= _GEN_83; + else if (io_free_mask_8 & entHasWrite_8 & _GEN_80 & entWrVbank_8 == 4'h6) + v2a_6 <= _GEN_81; + else if (io_free_mask_7 & entHasWrite_7 & _GEN_78 & entWrVbank_7 == 4'h6) + v2a_6 <= _GEN_79; + else if (io_free_mask_6 & entHasWrite_6 & _GEN_76 & entWrVbank_6 == 4'h6) + v2a_6 <= _GEN_77; + else if (io_free_mask_5 & entHasWrite_5 & _GEN_74 & entWrVbank_5 == 4'h6) + v2a_6 <= _GEN_75; + else if (io_free_mask_4 & entHasWrite_4 & _GEN_72 & entWrVbank_4 == 4'h6) + v2a_6 <= _GEN_73; + else if (io_free_mask_3 & entHasWrite_3 & _GEN_70 & entWrVbank_3 == 4'h6) + v2a_6 <= _GEN_71; + else if (io_free_mask_2 & entHasWrite_2 & _GEN_68 & entWrVbank_2 == 4'h6) + v2a_6 <= _GEN_69; + else if (io_free_mask_1 & entHasWrite_1 & _GEN_66 & entWrVbank_1 == 4'h6) + v2a_6 <= _GEN_67; + else if (io_free_mask_0 & entHasWrite_0 & _GEN_64 & entWrVbank_0 == 4'h6) + v2a_6 <= _GEN_65; + else if (_GEN_54) + v2a_6 <= _v2a_T; + if (io_free_mask_15 & entHasWrite_15 & _GEN_94 & entWrVbank_15 == 4'h7) + v2a_7 <= _GEN_95; + else if (io_free_mask_14 & entHasWrite_14 & _GEN_92 & entWrVbank_14 == 4'h7) + v2a_7 <= _GEN_93; + else if (io_free_mask_13 & entHasWrite_13 & _GEN_90 & entWrVbank_13 == 4'h7) + v2a_7 <= _GEN_91; + else if (io_free_mask_12 & entHasWrite_12 & _GEN_88 & entWrVbank_12 == 4'h7) + v2a_7 <= _GEN_89; + else if (io_free_mask_11 & entHasWrite_11 & _GEN_86 & entWrVbank_11 == 4'h7) + v2a_7 <= _GEN_87; + else if (io_free_mask_10 & entHasWrite_10 & _GEN_84 & entWrVbank_10 == 4'h7) + v2a_7 <= _GEN_85; + else if (io_free_mask_9 & entHasWrite_9 & _GEN_82 & entWrVbank_9 == 4'h7) + v2a_7 <= _GEN_83; + else if (io_free_mask_8 & entHasWrite_8 & _GEN_80 & entWrVbank_8 == 4'h7) + v2a_7 <= _GEN_81; + else if (io_free_mask_7 & entHasWrite_7 & _GEN_78 & entWrVbank_7 == 4'h7) + v2a_7 <= _GEN_79; + else if (io_free_mask_6 & entHasWrite_6 & _GEN_76 & entWrVbank_6 == 4'h7) + v2a_7 <= _GEN_77; + else if (io_free_mask_5 & entHasWrite_5 & _GEN_74 & entWrVbank_5 == 4'h7) + v2a_7 <= _GEN_75; + else if (io_free_mask_4 & entHasWrite_4 & _GEN_72 & entWrVbank_4 == 4'h7) + v2a_7 <= _GEN_73; + else if (io_free_mask_3 & entHasWrite_3 & _GEN_70 & entWrVbank_3 == 4'h7) + v2a_7 <= _GEN_71; + else if (io_free_mask_2 & entHasWrite_2 & _GEN_68 & entWrVbank_2 == 4'h7) + v2a_7 <= _GEN_69; + else if (io_free_mask_1 & entHasWrite_1 & _GEN_66 & entWrVbank_1 == 4'h7) + v2a_7 <= _GEN_67; + else if (io_free_mask_0 & entHasWrite_0 & _GEN_64 & entWrVbank_0 == 4'h7) + v2a_7 <= _GEN_65; + else if (_GEN_55) + v2a_7 <= _v2a_T; + if (io_free_mask_15 & entHasWrite_15 & _GEN_94 & entWrVbank_15 == 4'h8) + v2a_8 <= _GEN_95; + else if (io_free_mask_14 & entHasWrite_14 & _GEN_92 & entWrVbank_14 == 4'h8) + v2a_8 <= _GEN_93; + else if (io_free_mask_13 & entHasWrite_13 & _GEN_90 & entWrVbank_13 == 4'h8) + v2a_8 <= _GEN_91; + else if (io_free_mask_12 & entHasWrite_12 & _GEN_88 & entWrVbank_12 == 4'h8) + v2a_8 <= _GEN_89; + else if (io_free_mask_11 & entHasWrite_11 & _GEN_86 & entWrVbank_11 == 4'h8) + v2a_8 <= _GEN_87; + else if (io_free_mask_10 & entHasWrite_10 & _GEN_84 & entWrVbank_10 == 4'h8) + v2a_8 <= _GEN_85; + else if (io_free_mask_9 & entHasWrite_9 & _GEN_82 & entWrVbank_9 == 4'h8) + v2a_8 <= _GEN_83; + else if (io_free_mask_8 & entHasWrite_8 & _GEN_80 & entWrVbank_8 == 4'h8) + v2a_8 <= _GEN_81; + else if (io_free_mask_7 & entHasWrite_7 & _GEN_78 & entWrVbank_7 == 4'h8) + v2a_8 <= _GEN_79; + else if (io_free_mask_6 & entHasWrite_6 & _GEN_76 & entWrVbank_6 == 4'h8) + v2a_8 <= _GEN_77; + else if (io_free_mask_5 & entHasWrite_5 & _GEN_74 & entWrVbank_5 == 4'h8) + v2a_8 <= _GEN_75; + else if (io_free_mask_4 & entHasWrite_4 & _GEN_72 & entWrVbank_4 == 4'h8) + v2a_8 <= _GEN_73; + else if (io_free_mask_3 & entHasWrite_3 & _GEN_70 & entWrVbank_3 == 4'h8) + v2a_8 <= _GEN_71; + else if (io_free_mask_2 & entHasWrite_2 & _GEN_68 & entWrVbank_2 == 4'h8) + v2a_8 <= _GEN_69; + else if (io_free_mask_1 & entHasWrite_1 & _GEN_66 & entWrVbank_1 == 4'h8) + v2a_8 <= _GEN_67; + else if (io_free_mask_0 & entHasWrite_0 & _GEN_64 & entWrVbank_0 == 4'h8) + v2a_8 <= _GEN_65; + else if (_GEN_56) + v2a_8 <= _v2a_T; + if (io_free_mask_15 & entHasWrite_15 & _GEN_94 & entWrVbank_15 == 4'h9) + v2a_9 <= _GEN_95; + else if (io_free_mask_14 & entHasWrite_14 & _GEN_92 & entWrVbank_14 == 4'h9) + v2a_9 <= _GEN_93; + else if (io_free_mask_13 & entHasWrite_13 & _GEN_90 & entWrVbank_13 == 4'h9) + v2a_9 <= _GEN_91; + else if (io_free_mask_12 & entHasWrite_12 & _GEN_88 & entWrVbank_12 == 4'h9) + v2a_9 <= _GEN_89; + else if (io_free_mask_11 & entHasWrite_11 & _GEN_86 & entWrVbank_11 == 4'h9) + v2a_9 <= _GEN_87; + else if (io_free_mask_10 & entHasWrite_10 & _GEN_84 & entWrVbank_10 == 4'h9) + v2a_9 <= _GEN_85; + else if (io_free_mask_9 & entHasWrite_9 & _GEN_82 & entWrVbank_9 == 4'h9) + v2a_9 <= _GEN_83; + else if (io_free_mask_8 & entHasWrite_8 & _GEN_80 & entWrVbank_8 == 4'h9) + v2a_9 <= _GEN_81; + else if (io_free_mask_7 & entHasWrite_7 & _GEN_78 & entWrVbank_7 == 4'h9) + v2a_9 <= _GEN_79; + else if (io_free_mask_6 & entHasWrite_6 & _GEN_76 & entWrVbank_6 == 4'h9) + v2a_9 <= _GEN_77; + else if (io_free_mask_5 & entHasWrite_5 & _GEN_74 & entWrVbank_5 == 4'h9) + v2a_9 <= _GEN_75; + else if (io_free_mask_4 & entHasWrite_4 & _GEN_72 & entWrVbank_4 == 4'h9) + v2a_9 <= _GEN_73; + else if (io_free_mask_3 & entHasWrite_3 & _GEN_70 & entWrVbank_3 == 4'h9) + v2a_9 <= _GEN_71; + else if (io_free_mask_2 & entHasWrite_2 & _GEN_68 & entWrVbank_2 == 4'h9) + v2a_9 <= _GEN_69; + else if (io_free_mask_1 & entHasWrite_1 & _GEN_66 & entWrVbank_1 == 4'h9) + v2a_9 <= _GEN_67; + else if (io_free_mask_0 & entHasWrite_0 & _GEN_64 & entWrVbank_0 == 4'h9) + v2a_9 <= _GEN_65; + else if (_GEN_57) + v2a_9 <= _v2a_T; + if (io_free_mask_15 & entHasWrite_15 & _GEN_94 & entWrVbank_15 == 4'hA) + v2a_10 <= _GEN_95; + else if (io_free_mask_14 & entHasWrite_14 & _GEN_92 & entWrVbank_14 == 4'hA) + v2a_10 <= _GEN_93; + else if (io_free_mask_13 & entHasWrite_13 & _GEN_90 & entWrVbank_13 == 4'hA) + v2a_10 <= _GEN_91; + else if (io_free_mask_12 & entHasWrite_12 & _GEN_88 & entWrVbank_12 == 4'hA) + v2a_10 <= _GEN_89; + else if (io_free_mask_11 & entHasWrite_11 & _GEN_86 & entWrVbank_11 == 4'hA) + v2a_10 <= _GEN_87; + else if (io_free_mask_10 & entHasWrite_10 & _GEN_84 & entWrVbank_10 == 4'hA) + v2a_10 <= _GEN_85; + else if (io_free_mask_9 & entHasWrite_9 & _GEN_82 & entWrVbank_9 == 4'hA) + v2a_10 <= _GEN_83; + else if (io_free_mask_8 & entHasWrite_8 & _GEN_80 & entWrVbank_8 == 4'hA) + v2a_10 <= _GEN_81; + else if (io_free_mask_7 & entHasWrite_7 & _GEN_78 & entWrVbank_7 == 4'hA) + v2a_10 <= _GEN_79; + else if (io_free_mask_6 & entHasWrite_6 & _GEN_76 & entWrVbank_6 == 4'hA) + v2a_10 <= _GEN_77; + else if (io_free_mask_5 & entHasWrite_5 & _GEN_74 & entWrVbank_5 == 4'hA) + v2a_10 <= _GEN_75; + else if (io_free_mask_4 & entHasWrite_4 & _GEN_72 & entWrVbank_4 == 4'hA) + v2a_10 <= _GEN_73; + else if (io_free_mask_3 & entHasWrite_3 & _GEN_70 & entWrVbank_3 == 4'hA) + v2a_10 <= _GEN_71; + else if (io_free_mask_2 & entHasWrite_2 & _GEN_68 & entWrVbank_2 == 4'hA) + v2a_10 <= _GEN_69; + else if (io_free_mask_1 & entHasWrite_1 & _GEN_66 & entWrVbank_1 == 4'hA) + v2a_10 <= _GEN_67; + else if (io_free_mask_0 & entHasWrite_0 & _GEN_64 & entWrVbank_0 == 4'hA) + v2a_10 <= _GEN_65; + else if (_GEN_58) + v2a_10 <= _v2a_T; + if (io_free_mask_15 & entHasWrite_15 & _GEN_94 & entWrVbank_15 == 4'hB) + v2a_11 <= _GEN_95; + else if (io_free_mask_14 & entHasWrite_14 & _GEN_92 & entWrVbank_14 == 4'hB) + v2a_11 <= _GEN_93; + else if (io_free_mask_13 & entHasWrite_13 & _GEN_90 & entWrVbank_13 == 4'hB) + v2a_11 <= _GEN_91; + else if (io_free_mask_12 & entHasWrite_12 & _GEN_88 & entWrVbank_12 == 4'hB) + v2a_11 <= _GEN_89; + else if (io_free_mask_11 & entHasWrite_11 & _GEN_86 & entWrVbank_11 == 4'hB) + v2a_11 <= _GEN_87; + else if (io_free_mask_10 & entHasWrite_10 & _GEN_84 & entWrVbank_10 == 4'hB) + v2a_11 <= _GEN_85; + else if (io_free_mask_9 & entHasWrite_9 & _GEN_82 & entWrVbank_9 == 4'hB) + v2a_11 <= _GEN_83; + else if (io_free_mask_8 & entHasWrite_8 & _GEN_80 & entWrVbank_8 == 4'hB) + v2a_11 <= _GEN_81; + else if (io_free_mask_7 & entHasWrite_7 & _GEN_78 & entWrVbank_7 == 4'hB) + v2a_11 <= _GEN_79; + else if (io_free_mask_6 & entHasWrite_6 & _GEN_76 & entWrVbank_6 == 4'hB) + v2a_11 <= _GEN_77; + else if (io_free_mask_5 & entHasWrite_5 & _GEN_74 & entWrVbank_5 == 4'hB) + v2a_11 <= _GEN_75; + else if (io_free_mask_4 & entHasWrite_4 & _GEN_72 & entWrVbank_4 == 4'hB) + v2a_11 <= _GEN_73; + else if (io_free_mask_3 & entHasWrite_3 & _GEN_70 & entWrVbank_3 == 4'hB) + v2a_11 <= _GEN_71; + else if (io_free_mask_2 & entHasWrite_2 & _GEN_68 & entWrVbank_2 == 4'hB) + v2a_11 <= _GEN_69; + else if (io_free_mask_1 & entHasWrite_1 & _GEN_66 & entWrVbank_1 == 4'hB) + v2a_11 <= _GEN_67; + else if (io_free_mask_0 & entHasWrite_0 & _GEN_64 & entWrVbank_0 == 4'hB) + v2a_11 <= _GEN_65; + else if (_GEN_59) + v2a_11 <= _v2a_T; + if (io_free_mask_15 & entHasWrite_15 & _GEN_94 & entWrVbank_15 == 4'hC) + v2a_12 <= _GEN_95; + else if (io_free_mask_14 & entHasWrite_14 & _GEN_92 & entWrVbank_14 == 4'hC) + v2a_12 <= _GEN_93; + else if (io_free_mask_13 & entHasWrite_13 & _GEN_90 & entWrVbank_13 == 4'hC) + v2a_12 <= _GEN_91; + else if (io_free_mask_12 & entHasWrite_12 & _GEN_88 & entWrVbank_12 == 4'hC) + v2a_12 <= _GEN_89; + else if (io_free_mask_11 & entHasWrite_11 & _GEN_86 & entWrVbank_11 == 4'hC) + v2a_12 <= _GEN_87; + else if (io_free_mask_10 & entHasWrite_10 & _GEN_84 & entWrVbank_10 == 4'hC) + v2a_12 <= _GEN_85; + else if (io_free_mask_9 & entHasWrite_9 & _GEN_82 & entWrVbank_9 == 4'hC) + v2a_12 <= _GEN_83; + else if (io_free_mask_8 & entHasWrite_8 & _GEN_80 & entWrVbank_8 == 4'hC) + v2a_12 <= _GEN_81; + else if (io_free_mask_7 & entHasWrite_7 & _GEN_78 & entWrVbank_7 == 4'hC) + v2a_12 <= _GEN_79; + else if (io_free_mask_6 & entHasWrite_6 & _GEN_76 & entWrVbank_6 == 4'hC) + v2a_12 <= _GEN_77; + else if (io_free_mask_5 & entHasWrite_5 & _GEN_74 & entWrVbank_5 == 4'hC) + v2a_12 <= _GEN_75; + else if (io_free_mask_4 & entHasWrite_4 & _GEN_72 & entWrVbank_4 == 4'hC) + v2a_12 <= _GEN_73; + else if (io_free_mask_3 & entHasWrite_3 & _GEN_70 & entWrVbank_3 == 4'hC) + v2a_12 <= _GEN_71; + else if (io_free_mask_2 & entHasWrite_2 & _GEN_68 & entWrVbank_2 == 4'hC) + v2a_12 <= _GEN_69; + else if (io_free_mask_1 & entHasWrite_1 & _GEN_66 & entWrVbank_1 == 4'hC) + v2a_12 <= _GEN_67; + else if (io_free_mask_0 & entHasWrite_0 & _GEN_64 & entWrVbank_0 == 4'hC) + v2a_12 <= _GEN_65; + else if (_GEN_60) + v2a_12 <= _v2a_T; + if (io_free_mask_15 & entHasWrite_15 & _GEN_94 & entWrVbank_15 == 4'hD) + v2a_13 <= _GEN_95; + else if (io_free_mask_14 & entHasWrite_14 & _GEN_92 & entWrVbank_14 == 4'hD) + v2a_13 <= _GEN_93; + else if (io_free_mask_13 & entHasWrite_13 & _GEN_90 & entWrVbank_13 == 4'hD) + v2a_13 <= _GEN_91; + else if (io_free_mask_12 & entHasWrite_12 & _GEN_88 & entWrVbank_12 == 4'hD) + v2a_13 <= _GEN_89; + else if (io_free_mask_11 & entHasWrite_11 & _GEN_86 & entWrVbank_11 == 4'hD) + v2a_13 <= _GEN_87; + else if (io_free_mask_10 & entHasWrite_10 & _GEN_84 & entWrVbank_10 == 4'hD) + v2a_13 <= _GEN_85; + else if (io_free_mask_9 & entHasWrite_9 & _GEN_82 & entWrVbank_9 == 4'hD) + v2a_13 <= _GEN_83; + else if (io_free_mask_8 & entHasWrite_8 & _GEN_80 & entWrVbank_8 == 4'hD) + v2a_13 <= _GEN_81; + else if (io_free_mask_7 & entHasWrite_7 & _GEN_78 & entWrVbank_7 == 4'hD) + v2a_13 <= _GEN_79; + else if (io_free_mask_6 & entHasWrite_6 & _GEN_76 & entWrVbank_6 == 4'hD) + v2a_13 <= _GEN_77; + else if (io_free_mask_5 & entHasWrite_5 & _GEN_74 & entWrVbank_5 == 4'hD) + v2a_13 <= _GEN_75; + else if (io_free_mask_4 & entHasWrite_4 & _GEN_72 & entWrVbank_4 == 4'hD) + v2a_13 <= _GEN_73; + else if (io_free_mask_3 & entHasWrite_3 & _GEN_70 & entWrVbank_3 == 4'hD) + v2a_13 <= _GEN_71; + else if (io_free_mask_2 & entHasWrite_2 & _GEN_68 & entWrVbank_2 == 4'hD) + v2a_13 <= _GEN_69; + else if (io_free_mask_1 & entHasWrite_1 & _GEN_66 & entWrVbank_1 == 4'hD) + v2a_13 <= _GEN_67; + else if (io_free_mask_0 & entHasWrite_0 & _GEN_64 & entWrVbank_0 == 4'hD) + v2a_13 <= _GEN_65; + else if (_GEN_61) + v2a_13 <= _v2a_T; + if (io_free_mask_15 & entHasWrite_15 & _GEN_94 & entWrVbank_15 == 4'hE) + v2a_14 <= _GEN_95; + else if (io_free_mask_14 & entHasWrite_14 & _GEN_92 & entWrVbank_14 == 4'hE) + v2a_14 <= _GEN_93; + else if (io_free_mask_13 & entHasWrite_13 & _GEN_90 & entWrVbank_13 == 4'hE) + v2a_14 <= _GEN_91; + else if (io_free_mask_12 & entHasWrite_12 & _GEN_88 & entWrVbank_12 == 4'hE) + v2a_14 <= _GEN_89; + else if (io_free_mask_11 & entHasWrite_11 & _GEN_86 & entWrVbank_11 == 4'hE) + v2a_14 <= _GEN_87; + else if (io_free_mask_10 & entHasWrite_10 & _GEN_84 & entWrVbank_10 == 4'hE) + v2a_14 <= _GEN_85; + else if (io_free_mask_9 & entHasWrite_9 & _GEN_82 & entWrVbank_9 == 4'hE) + v2a_14 <= _GEN_83; + else if (io_free_mask_8 & entHasWrite_8 & _GEN_80 & entWrVbank_8 == 4'hE) + v2a_14 <= _GEN_81; + else if (io_free_mask_7 & entHasWrite_7 & _GEN_78 & entWrVbank_7 == 4'hE) + v2a_14 <= _GEN_79; + else if (io_free_mask_6 & entHasWrite_6 & _GEN_76 & entWrVbank_6 == 4'hE) + v2a_14 <= _GEN_77; + else if (io_free_mask_5 & entHasWrite_5 & _GEN_74 & entWrVbank_5 == 4'hE) + v2a_14 <= _GEN_75; + else if (io_free_mask_4 & entHasWrite_4 & _GEN_72 & entWrVbank_4 == 4'hE) + v2a_14 <= _GEN_73; + else if (io_free_mask_3 & entHasWrite_3 & _GEN_70 & entWrVbank_3 == 4'hE) + v2a_14 <= _GEN_71; + else if (io_free_mask_2 & entHasWrite_2 & _GEN_68 & entWrVbank_2 == 4'hE) + v2a_14 <= _GEN_69; + else if (io_free_mask_1 & entHasWrite_1 & _GEN_66 & entWrVbank_1 == 4'hE) + v2a_14 <= _GEN_67; + else if (io_free_mask_0 & entHasWrite_0 & _GEN_64 & entWrVbank_0 == 4'hE) + v2a_14 <= _GEN_65; + else if (_GEN_62) + v2a_14 <= _v2a_T; + if (io_free_mask_15 & entHasWrite_15 & _GEN_94 & (&entWrVbank_15)) + v2a_15 <= _GEN_95; + else if (io_free_mask_14 & entHasWrite_14 & _GEN_92 & (&entWrVbank_14)) + v2a_15 <= _GEN_93; + else if (io_free_mask_13 & entHasWrite_13 & _GEN_90 & (&entWrVbank_13)) + v2a_15 <= _GEN_91; + else if (io_free_mask_12 & entHasWrite_12 & _GEN_88 & (&entWrVbank_12)) + v2a_15 <= _GEN_89; + else if (io_free_mask_11 & entHasWrite_11 & _GEN_86 & (&entWrVbank_11)) + v2a_15 <= _GEN_87; + else if (io_free_mask_10 & entHasWrite_10 & _GEN_84 & (&entWrVbank_10)) + v2a_15 <= _GEN_85; + else if (io_free_mask_9 & entHasWrite_9 & _GEN_82 & (&entWrVbank_9)) + v2a_15 <= _GEN_83; + else if (io_free_mask_8 & entHasWrite_8 & _GEN_80 & (&entWrVbank_8)) + v2a_15 <= _GEN_81; + else if (io_free_mask_7 & entHasWrite_7 & _GEN_78 & (&entWrVbank_7)) + v2a_15 <= _GEN_79; + else if (io_free_mask_6 & entHasWrite_6 & _GEN_76 & (&entWrVbank_6)) + v2a_15 <= _GEN_77; + else if (io_free_mask_5 & entHasWrite_5 & _GEN_74 & (&entWrVbank_5)) + v2a_15 <= _GEN_75; + else if (io_free_mask_4 & entHasWrite_4 & _GEN_72 & (&entWrVbank_4)) + v2a_15 <= _GEN_73; + else if (io_free_mask_3 & entHasWrite_3 & _GEN_70 & (&entWrVbank_3)) + v2a_15 <= _GEN_71; + else if (io_free_mask_2 & entHasWrite_2 & _GEN_68 & (&entWrVbank_2)) + v2a_15 <= _GEN_69; + else if (io_free_mask_1 & entHasWrite_1 & _GEN_66 & (&entWrVbank_1)) + v2a_15 <= _GEN_67; + else if (io_free_mask_0 & entHasWrite_0 & _GEN_64 & (&entWrVbank_0)) + v2a_15 <= _GEN_65; + else if (_GEN_63) + v2a_15 <= _v2a_T; + end + else begin + if (_GEN_48) + v2a_0 <= _v2a_T; + if (_GEN_49) + v2a_1 <= _v2a_T; + if (_GEN_50) + v2a_2 <= _v2a_T; + if (_GEN_51) + v2a_3 <= _v2a_T; + if (_GEN_52) + v2a_4 <= _v2a_T; + if (_GEN_53) + v2a_5 <= _v2a_T; + if (_GEN_54) + v2a_6 <= _v2a_T; + if (_GEN_55) + v2a_7 <= _v2a_T; + if (_GEN_56) + v2a_8 <= _v2a_T; + if (_GEN_57) + v2a_9 <= _v2a_T; + if (_GEN_58) + v2a_10 <= _v2a_T; + if (_GEN_59) + v2a_11 <= _v2a_T; + if (_GEN_60) + v2a_12 <= _v2a_T; + if (_GEN_61) + v2a_13 <= _v2a_T; + if (_GEN_62) + v2a_14 <= _v2a_T; + if (_GEN_63) + v2a_15 <= _v2a_T; + end + aliasInUse_0 <= + ~(io_free_valid & io_free_mask_0 & entHasWrite_0) + & (io_alloc_valid & io_alloc_raw_wr_bank_valid & _GEN_17 | aliasInUse_0); + aliasInUse_1 <= + ~(io_free_valid & io_free_mask_1 & entHasWrite_1) + & (io_alloc_valid & io_alloc_raw_wr_bank_valid & _GEN_19 | aliasInUse_1); + aliasInUse_2 <= + ~(io_free_valid & io_free_mask_2 & entHasWrite_2) + & (io_alloc_valid & io_alloc_raw_wr_bank_valid & _GEN_21 | aliasInUse_2); + aliasInUse_3 <= + ~(io_free_valid & io_free_mask_3 & entHasWrite_3) + & (io_alloc_valid & io_alloc_raw_wr_bank_valid & _GEN_23 | aliasInUse_3); + aliasInUse_4 <= + ~(io_free_valid & io_free_mask_4 & entHasWrite_4) + & (io_alloc_valid & io_alloc_raw_wr_bank_valid & _GEN_25 | aliasInUse_4); + aliasInUse_5 <= + ~(io_free_valid & io_free_mask_5 & entHasWrite_5) + & (io_alloc_valid & io_alloc_raw_wr_bank_valid & _GEN_27 | aliasInUse_5); + aliasInUse_6 <= + ~(io_free_valid & io_free_mask_6 & entHasWrite_6) + & (io_alloc_valid & io_alloc_raw_wr_bank_valid & _GEN_29 | aliasInUse_6); + aliasInUse_7 <= + ~(io_free_valid & io_free_mask_7 & entHasWrite_7) + & (io_alloc_valid & io_alloc_raw_wr_bank_valid & _GEN_31 | aliasInUse_7); + aliasInUse_8 <= + ~(io_free_valid & io_free_mask_8 & entHasWrite_8) + & (io_alloc_valid & io_alloc_raw_wr_bank_valid & _GEN_33 | aliasInUse_8); + aliasInUse_9 <= + ~(io_free_valid & io_free_mask_9 & entHasWrite_9) + & (io_alloc_valid & io_alloc_raw_wr_bank_valid & _GEN_35 | aliasInUse_9); + aliasInUse_10 <= + ~(io_free_valid & io_free_mask_10 & entHasWrite_10) + & (io_alloc_valid & io_alloc_raw_wr_bank_valid & _GEN_37 | aliasInUse_10); + aliasInUse_11 <= + ~(io_free_valid & io_free_mask_11 & entHasWrite_11) + & (io_alloc_valid & io_alloc_raw_wr_bank_valid & _GEN_39 | aliasInUse_11); + aliasInUse_12 <= + ~(io_free_valid & io_free_mask_12 & entHasWrite_12) + & (io_alloc_valid & io_alloc_raw_wr_bank_valid & _GEN_41 | aliasInUse_12); + aliasInUse_13 <= + ~(io_free_valid & io_free_mask_13 & entHasWrite_13) + & (io_alloc_valid & io_alloc_raw_wr_bank_valid & _GEN_43 | aliasInUse_13); + aliasInUse_14 <= + ~(io_free_valid & io_free_mask_14 & entHasWrite_14) + & (io_alloc_valid & io_alloc_raw_wr_bank_valid & _GEN_45 | aliasInUse_14); + aliasInUse_15 <= + ~(io_free_valid & io_free_mask_15 & entHasWrite_15) + & (io_alloc_valid & io_alloc_raw_wr_bank_valid & (&io_alloc_rob_id) + | aliasInUse_15); + entHasWrite_0 <= ~_GEN_0 & (_GEN_18 ? io_alloc_raw_wr_bank_valid : entHasWrite_0); + entHasWrite_1 <= ~_GEN_1 & (_GEN_20 ? io_alloc_raw_wr_bank_valid : entHasWrite_1); + entHasWrite_2 <= ~_GEN_2 & (_GEN_22 ? io_alloc_raw_wr_bank_valid : entHasWrite_2); + entHasWrite_3 <= ~_GEN_3 & (_GEN_24 ? io_alloc_raw_wr_bank_valid : entHasWrite_3); + entHasWrite_4 <= ~_GEN_4 & (_GEN_26 ? io_alloc_raw_wr_bank_valid : entHasWrite_4); + entHasWrite_5 <= ~_GEN_5 & (_GEN_28 ? io_alloc_raw_wr_bank_valid : entHasWrite_5); + entHasWrite_6 <= ~_GEN_6 & (_GEN_30 ? io_alloc_raw_wr_bank_valid : entHasWrite_6); + entHasWrite_7 <= ~_GEN_7 & (_GEN_32 ? io_alloc_raw_wr_bank_valid : entHasWrite_7); + entHasWrite_8 <= ~_GEN_8 & (_GEN_34 ? io_alloc_raw_wr_bank_valid : entHasWrite_8); + entHasWrite_9 <= ~_GEN_9 & (_GEN_36 ? io_alloc_raw_wr_bank_valid : entHasWrite_9); + entHasWrite_10 <= + ~_GEN_10 & (_GEN_38 ? io_alloc_raw_wr_bank_valid : entHasWrite_10); + entHasWrite_11 <= + ~_GEN_11 & (_GEN_40 ? io_alloc_raw_wr_bank_valid : entHasWrite_11); + entHasWrite_12 <= + ~_GEN_12 & (_GEN_42 ? io_alloc_raw_wr_bank_valid : entHasWrite_12); + entHasWrite_13 <= + ~_GEN_13 & (_GEN_44 ? io_alloc_raw_wr_bank_valid : entHasWrite_13); + entHasWrite_14 <= + ~_GEN_14 & (_GEN_46 ? io_alloc_raw_wr_bank_valid : entHasWrite_14); + entHasWrite_15 <= + ~_GEN_15 & (_GEN_47 ? io_alloc_raw_wr_bank_valid : entHasWrite_15); + if (_GEN_0) begin + entNewAlias_0 <= 10'h0; + entWrVbank_0 <= 4'h0; + end + else if (_GEN_18) begin + entNewAlias_0 <= _entNewAlias_T_2; + entWrVbank_0 <= io_alloc_raw_wr_bank_id[3:0]; + end + if (_GEN_1) begin + entNewAlias_1 <= 10'h0; + entWrVbank_1 <= 4'h0; + end + else if (_GEN_20) begin + entNewAlias_1 <= _entNewAlias_T_2; + entWrVbank_1 <= io_alloc_raw_wr_bank_id[3:0]; + end + if (_GEN_2) begin + entNewAlias_2 <= 10'h0; + entWrVbank_2 <= 4'h0; + end + else if (_GEN_22) begin + entNewAlias_2 <= _entNewAlias_T_2; + entWrVbank_2 <= io_alloc_raw_wr_bank_id[3:0]; + end + if (_GEN_3) begin + entNewAlias_3 <= 10'h0; + entWrVbank_3 <= 4'h0; + end + else if (_GEN_24) begin + entNewAlias_3 <= _entNewAlias_T_2; + entWrVbank_3 <= io_alloc_raw_wr_bank_id[3:0]; + end + if (_GEN_4) begin + entNewAlias_4 <= 10'h0; + entWrVbank_4 <= 4'h0; + end + else if (_GEN_26) begin + entNewAlias_4 <= _entNewAlias_T_2; + entWrVbank_4 <= io_alloc_raw_wr_bank_id[3:0]; + end + if (_GEN_5) begin + entNewAlias_5 <= 10'h0; + entWrVbank_5 <= 4'h0; + end + else if (_GEN_28) begin + entNewAlias_5 <= _entNewAlias_T_2; + entWrVbank_5 <= io_alloc_raw_wr_bank_id[3:0]; + end + if (_GEN_6) begin + entNewAlias_6 <= 10'h0; + entWrVbank_6 <= 4'h0; + end + else if (_GEN_30) begin + entNewAlias_6 <= _entNewAlias_T_2; + entWrVbank_6 <= io_alloc_raw_wr_bank_id[3:0]; + end + if (_GEN_7) begin + entNewAlias_7 <= 10'h0; + entWrVbank_7 <= 4'h0; + end + else if (_GEN_32) begin + entNewAlias_7 <= _entNewAlias_T_2; + entWrVbank_7 <= io_alloc_raw_wr_bank_id[3:0]; + end + if (_GEN_8) begin + entNewAlias_8 <= 10'h0; + entWrVbank_8 <= 4'h0; + end + else if (_GEN_34) begin + entNewAlias_8 <= _entNewAlias_T_2; + entWrVbank_8 <= io_alloc_raw_wr_bank_id[3:0]; + end + if (_GEN_9) begin + entNewAlias_9 <= 10'h0; + entWrVbank_9 <= 4'h0; + end + else if (_GEN_36) begin + entNewAlias_9 <= _entNewAlias_T_2; + entWrVbank_9 <= io_alloc_raw_wr_bank_id[3:0]; + end + if (_GEN_10) begin + entNewAlias_10 <= 10'h0; + entWrVbank_10 <= 4'h0; + end + else if (_GEN_38) begin + entNewAlias_10 <= _entNewAlias_T_2; + entWrVbank_10 <= io_alloc_raw_wr_bank_id[3:0]; + end + if (_GEN_11) begin + entNewAlias_11 <= 10'h0; + entWrVbank_11 <= 4'h0; + end + else if (_GEN_40) begin + entNewAlias_11 <= _entNewAlias_T_2; + entWrVbank_11 <= io_alloc_raw_wr_bank_id[3:0]; + end + if (_GEN_12) begin + entNewAlias_12 <= 10'h0; + entWrVbank_12 <= 4'h0; + end + else if (_GEN_42) begin + entNewAlias_12 <= _entNewAlias_T_2; + entWrVbank_12 <= io_alloc_raw_wr_bank_id[3:0]; + end + if (_GEN_13) begin + entNewAlias_13 <= 10'h0; + entWrVbank_13 <= 4'h0; + end + else if (_GEN_44) begin + entNewAlias_13 <= _entNewAlias_T_2; + entWrVbank_13 <= io_alloc_raw_wr_bank_id[3:0]; + end + if (_GEN_14) begin + entNewAlias_14 <= 10'h0; + entWrVbank_14 <= 4'h0; + end + else if (_GEN_46) begin + entNewAlias_14 <= _entNewAlias_T_2; + entWrVbank_14 <= io_alloc_raw_wr_bank_id[3:0]; + end + if (_GEN_15) begin + entNewAlias_15 <= 10'h0; + entWrVbank_15 <= 4'h0; + end + else if (_GEN_47) begin + entNewAlias_15 <= _entNewAlias_T_2; + entWrVbank_15 <= io_alloc_raw_wr_bank_id[3:0]; + end + end + end // always @(posedge) + assign io_alloc_renamed_rd_bank_0_valid = io_alloc_raw_rd_bank_0_valid; + assign io_alloc_renamed_rd_bank_0_id = + io_alloc_raw_rd_bank_0_valid ? _GEN[io_alloc_raw_rd_bank_0_id[3:0]] : 10'h0; + assign io_alloc_renamed_rd_bank_1_valid = io_alloc_raw_rd_bank_1_valid; + assign io_alloc_renamed_rd_bank_1_id = + io_alloc_raw_rd_bank_1_valid ? _GEN[io_alloc_raw_rd_bank_1_id[3:0]] : 10'h0; + assign io_alloc_renamed_wr_bank_valid = io_alloc_raw_wr_bank_valid; + assign io_alloc_renamed_wr_bank_id = io_alloc_raw_wr_bank_valid ? _v2a_T : 10'h0; +endmodule + +module BankScoreboard( + input clock, + reset, + alloc_valid, + alloc_bits_wr_bank_valid, + input [9:0] alloc_bits_wr_bank_id, + input complete_valid, + complete_bits_wr_bank_valid, + input [9:0] complete_bits_wr_bank_id, + input queryVec_0_rd_bank_0_valid, + input [9:0] queryVec_0_rd_bank_0_id, + input queryVec_0_rd_bank_1_valid, + input [9:0] queryVec_0_rd_bank_1_id, + input queryVec_1_rd_bank_0_valid, + input [9:0] queryVec_1_rd_bank_0_id, + input queryVec_1_rd_bank_1_valid, + input [9:0] queryVec_1_rd_bank_1_id, + input queryVec_2_rd_bank_0_valid, + input [9:0] queryVec_2_rd_bank_0_id, + input queryVec_2_rd_bank_1_valid, + input [9:0] queryVec_2_rd_bank_1_id, + input queryVec_3_rd_bank_0_valid, + input [9:0] queryVec_3_rd_bank_0_id, + input queryVec_3_rd_bank_1_valid, + input [9:0] queryVec_3_rd_bank_1_id, + input queryVec_4_rd_bank_0_valid, + input [9:0] queryVec_4_rd_bank_0_id, + input queryVec_4_rd_bank_1_valid, + input [9:0] queryVec_4_rd_bank_1_id, + input queryVec_5_rd_bank_0_valid, + input [9:0] queryVec_5_rd_bank_0_id, + input queryVec_5_rd_bank_1_valid, + input [9:0] queryVec_5_rd_bank_1_id, + input queryVec_6_rd_bank_0_valid, + input [9:0] queryVec_6_rd_bank_0_id, + input queryVec_6_rd_bank_1_valid, + input [9:0] queryVec_6_rd_bank_1_id, + input queryVec_7_rd_bank_0_valid, + input [9:0] queryVec_7_rd_bank_0_id, + input queryVec_7_rd_bank_1_valid, + input [9:0] queryVec_7_rd_bank_1_id, + input queryVec_8_rd_bank_0_valid, + input [9:0] queryVec_8_rd_bank_0_id, + input queryVec_8_rd_bank_1_valid, + input [9:0] queryVec_8_rd_bank_1_id, + input queryVec_9_rd_bank_0_valid, + input [9:0] queryVec_9_rd_bank_0_id, + input queryVec_9_rd_bank_1_valid, + input [9:0] queryVec_9_rd_bank_1_id, + input queryVec_10_rd_bank_0_valid, + input [9:0] queryVec_10_rd_bank_0_id, + input queryVec_10_rd_bank_1_valid, + input [9:0] queryVec_10_rd_bank_1_id, + input queryVec_11_rd_bank_0_valid, + input [9:0] queryVec_11_rd_bank_0_id, + input queryVec_11_rd_bank_1_valid, + input [9:0] queryVec_11_rd_bank_1_id, + input queryVec_12_rd_bank_0_valid, + input [9:0] queryVec_12_rd_bank_0_id, + input queryVec_12_rd_bank_1_valid, + input [9:0] queryVec_12_rd_bank_1_id, + input queryVec_13_rd_bank_0_valid, + input [9:0] queryVec_13_rd_bank_0_id, + input queryVec_13_rd_bank_1_valid, + input [9:0] queryVec_13_rd_bank_1_id, + input queryVec_14_rd_bank_0_valid, + input [9:0] queryVec_14_rd_bank_0_id, + input queryVec_14_rd_bank_1_valid, + input [9:0] queryVec_14_rd_bank_1_id, + input queryVec_15_rd_bank_0_valid, + input [9:0] queryVec_15_rd_bank_0_id, + input queryVec_15_rd_bank_1_valid, + input [9:0] queryVec_15_rd_bank_1_id, + output hazardVec_0, + hazardVec_1, + hazardVec_2, + hazardVec_3, + hazardVec_4, + hazardVec_5, + hazardVec_6, + hazardVec_7, + hazardVec_8, + hazardVec_9, + hazardVec_10, + hazardVec_11, + hazardVec_12, + hazardVec_13, + hazardVec_14, + hazardVec_15 +); + + reg bankWrBusy_0; + reg bankWrBusy_1; + reg bankWrBusy_2; + reg bankWrBusy_3; + reg bankWrBusy_4; + reg bankWrBusy_5; + reg bankWrBusy_6; + reg bankWrBusy_7; + reg bankWrBusy_8; + reg bankWrBusy_9; + reg bankWrBusy_10; + reg bankWrBusy_11; + reg bankWrBusy_12; + reg bankWrBusy_13; + reg bankWrBusy_14; + reg bankWrBusy_15; + reg bankWrBusy_16; + reg bankWrBusy_17; + reg bankWrBusy_18; + reg bankWrBusy_19; + reg bankWrBusy_20; + reg bankWrBusy_21; + reg bankWrBusy_22; + reg bankWrBusy_23; + reg bankWrBusy_24; + reg bankWrBusy_25; + reg bankWrBusy_26; + reg bankWrBusy_27; + reg bankWrBusy_28; + reg bankWrBusy_29; + reg bankWrBusy_30; + reg bankWrBusy_31; + wire [31:0] _GEN = + {{bankWrBusy_31}, + {bankWrBusy_30}, + {bankWrBusy_29}, + {bankWrBusy_28}, + {bankWrBusy_27}, + {bankWrBusy_26}, + {bankWrBusy_25}, + {bankWrBusy_24}, + {bankWrBusy_23}, + {bankWrBusy_22}, + {bankWrBusy_21}, + {bankWrBusy_20}, + {bankWrBusy_19}, + {bankWrBusy_18}, + {bankWrBusy_17}, + {bankWrBusy_16}, + {bankWrBusy_15}, + {bankWrBusy_14}, + {bankWrBusy_13}, + {bankWrBusy_12}, + {bankWrBusy_11}, + {bankWrBusy_10}, + {bankWrBusy_9}, + {bankWrBusy_8}, + {bankWrBusy_7}, + {bankWrBusy_6}, + {bankWrBusy_5}, + {bankWrBusy_4}, + {bankWrBusy_3}, + {bankWrBusy_2}, + {bankWrBusy_1}, + {bankWrBusy_0}}; + always @(posedge clock) begin + if (reset) begin + bankWrBusy_0 <= 1'h0; + bankWrBusy_1 <= 1'h0; + bankWrBusy_2 <= 1'h0; + bankWrBusy_3 <= 1'h0; + bankWrBusy_4 <= 1'h0; + bankWrBusy_5 <= 1'h0; + bankWrBusy_6 <= 1'h0; + bankWrBusy_7 <= 1'h0; + bankWrBusy_8 <= 1'h0; + bankWrBusy_9 <= 1'h0; + bankWrBusy_10 <= 1'h0; + bankWrBusy_11 <= 1'h0; + bankWrBusy_12 <= 1'h0; + bankWrBusy_13 <= 1'h0; + bankWrBusy_14 <= 1'h0; + bankWrBusy_15 <= 1'h0; + bankWrBusy_16 <= 1'h0; + bankWrBusy_17 <= 1'h0; + bankWrBusy_18 <= 1'h0; + bankWrBusy_19 <= 1'h0; + bankWrBusy_20 <= 1'h0; + bankWrBusy_21 <= 1'h0; + bankWrBusy_22 <= 1'h0; + bankWrBusy_23 <= 1'h0; + bankWrBusy_24 <= 1'h0; + bankWrBusy_25 <= 1'h0; + bankWrBusy_26 <= 1'h0; + bankWrBusy_27 <= 1'h0; + bankWrBusy_28 <= 1'h0; + bankWrBusy_29 <= 1'h0; + bankWrBusy_30 <= 1'h0; + bankWrBusy_31 <= 1'h0; + end + else begin + automatic logic _allocWr_T_62 = alloc_valid & alloc_bits_wr_bank_valid; + automatic logic _cmpWr_T_62 = complete_valid & complete_bits_wr_bank_valid; + automatic logic cmpWr = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h0; + automatic logic cmpWr_1 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h1; + automatic logic cmpWr_2 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h2; + automatic logic cmpWr_3 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h3; + automatic logic cmpWr_4 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h4; + automatic logic cmpWr_5 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h5; + automatic logic cmpWr_6 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h6; + automatic logic cmpWr_7 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h7; + automatic logic cmpWr_8 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h8; + automatic logic cmpWr_9 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h9; + automatic logic cmpWr_10 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'hA; + automatic logic cmpWr_11 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'hB; + automatic logic cmpWr_12 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'hC; + automatic logic cmpWr_13 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'hD; + automatic logic cmpWr_14 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'hE; + automatic logic cmpWr_15 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'hF; + automatic logic cmpWr_16 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h10; + automatic logic cmpWr_17 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h11; + automatic logic cmpWr_18 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h12; + automatic logic cmpWr_19 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h13; + automatic logic cmpWr_20 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h14; + automatic logic cmpWr_21 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h15; + automatic logic cmpWr_22 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h16; + automatic logic cmpWr_23 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h17; + automatic logic cmpWr_24 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h18; + automatic logic cmpWr_25 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h19; + automatic logic cmpWr_26 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h1A; + automatic logic cmpWr_27 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h1B; + automatic logic cmpWr_28 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h1C; + automatic logic cmpWr_29 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h1D; + automatic logic cmpWr_30 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h1E; + automatic logic cmpWr_31 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h1F; + bankWrBusy_0 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h0 & ~cmpWr | ~cmpWr & bankWrBusy_0; + bankWrBusy_1 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h1 & ~cmpWr_1 | ~cmpWr_1 + & bankWrBusy_1; + bankWrBusy_2 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h2 & ~cmpWr_2 | ~cmpWr_2 + & bankWrBusy_2; + bankWrBusy_3 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h3 & ~cmpWr_3 | ~cmpWr_3 + & bankWrBusy_3; + bankWrBusy_4 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h4 & ~cmpWr_4 | ~cmpWr_4 + & bankWrBusy_4; + bankWrBusy_5 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h5 & ~cmpWr_5 | ~cmpWr_5 + & bankWrBusy_5; + bankWrBusy_6 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h6 & ~cmpWr_6 | ~cmpWr_6 + & bankWrBusy_6; + bankWrBusy_7 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h7 & ~cmpWr_7 | ~cmpWr_7 + & bankWrBusy_7; + bankWrBusy_8 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h8 & ~cmpWr_8 | ~cmpWr_8 + & bankWrBusy_8; + bankWrBusy_9 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h9 & ~cmpWr_9 | ~cmpWr_9 + & bankWrBusy_9; + bankWrBusy_10 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'hA & ~cmpWr_10 | ~cmpWr_10 + & bankWrBusy_10; + bankWrBusy_11 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'hB & ~cmpWr_11 | ~cmpWr_11 + & bankWrBusy_11; + bankWrBusy_12 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'hC & ~cmpWr_12 | ~cmpWr_12 + & bankWrBusy_12; + bankWrBusy_13 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'hD & ~cmpWr_13 | ~cmpWr_13 + & bankWrBusy_13; + bankWrBusy_14 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'hE & ~cmpWr_14 | ~cmpWr_14 + & bankWrBusy_14; + bankWrBusy_15 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'hF & ~cmpWr_15 | ~cmpWr_15 + & bankWrBusy_15; + bankWrBusy_16 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h10 & ~cmpWr_16 | ~cmpWr_16 + & bankWrBusy_16; + bankWrBusy_17 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h11 & ~cmpWr_17 | ~cmpWr_17 + & bankWrBusy_17; + bankWrBusy_18 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h12 & ~cmpWr_18 | ~cmpWr_18 + & bankWrBusy_18; + bankWrBusy_19 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h13 & ~cmpWr_19 | ~cmpWr_19 + & bankWrBusy_19; + bankWrBusy_20 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h14 & ~cmpWr_20 | ~cmpWr_20 + & bankWrBusy_20; + bankWrBusy_21 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h15 & ~cmpWr_21 | ~cmpWr_21 + & bankWrBusy_21; + bankWrBusy_22 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h16 & ~cmpWr_22 | ~cmpWr_22 + & bankWrBusy_22; + bankWrBusy_23 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h17 & ~cmpWr_23 | ~cmpWr_23 + & bankWrBusy_23; + bankWrBusy_24 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h18 & ~cmpWr_24 | ~cmpWr_24 + & bankWrBusy_24; + bankWrBusy_25 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h19 & ~cmpWr_25 | ~cmpWr_25 + & bankWrBusy_25; + bankWrBusy_26 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h1A & ~cmpWr_26 | ~cmpWr_26 + & bankWrBusy_26; + bankWrBusy_27 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h1B & ~cmpWr_27 | ~cmpWr_27 + & bankWrBusy_27; + bankWrBusy_28 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h1C & ~cmpWr_28 | ~cmpWr_28 + & bankWrBusy_28; + bankWrBusy_29 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h1D & ~cmpWr_29 | ~cmpWr_29 + & bankWrBusy_29; + bankWrBusy_30 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h1E & ~cmpWr_30 | ~cmpWr_30 + & bankWrBusy_30; + bankWrBusy_31 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h1F & ~cmpWr_31 | ~cmpWr_31 + & bankWrBusy_31; + end + end // always @(posedge) + assign hazardVec_0 = + queryVec_0_rd_bank_0_valid & _GEN[queryVec_0_rd_bank_0_id[4:0]] + | queryVec_0_rd_bank_1_valid & _GEN[queryVec_0_rd_bank_1_id[4:0]]; + assign hazardVec_1 = + queryVec_1_rd_bank_0_valid & _GEN[queryVec_1_rd_bank_0_id[4:0]] + | queryVec_1_rd_bank_1_valid & _GEN[queryVec_1_rd_bank_1_id[4:0]]; + assign hazardVec_2 = + queryVec_2_rd_bank_0_valid & _GEN[queryVec_2_rd_bank_0_id[4:0]] + | queryVec_2_rd_bank_1_valid & _GEN[queryVec_2_rd_bank_1_id[4:0]]; + assign hazardVec_3 = + queryVec_3_rd_bank_0_valid & _GEN[queryVec_3_rd_bank_0_id[4:0]] + | queryVec_3_rd_bank_1_valid & _GEN[queryVec_3_rd_bank_1_id[4:0]]; + assign hazardVec_4 = + queryVec_4_rd_bank_0_valid & _GEN[queryVec_4_rd_bank_0_id[4:0]] + | queryVec_4_rd_bank_1_valid & _GEN[queryVec_4_rd_bank_1_id[4:0]]; + assign hazardVec_5 = + queryVec_5_rd_bank_0_valid & _GEN[queryVec_5_rd_bank_0_id[4:0]] + | queryVec_5_rd_bank_1_valid & _GEN[queryVec_5_rd_bank_1_id[4:0]]; + assign hazardVec_6 = + queryVec_6_rd_bank_0_valid & _GEN[queryVec_6_rd_bank_0_id[4:0]] + | queryVec_6_rd_bank_1_valid & _GEN[queryVec_6_rd_bank_1_id[4:0]]; + assign hazardVec_7 = + queryVec_7_rd_bank_0_valid & _GEN[queryVec_7_rd_bank_0_id[4:0]] + | queryVec_7_rd_bank_1_valid & _GEN[queryVec_7_rd_bank_1_id[4:0]]; + assign hazardVec_8 = + queryVec_8_rd_bank_0_valid & _GEN[queryVec_8_rd_bank_0_id[4:0]] + | queryVec_8_rd_bank_1_valid & _GEN[queryVec_8_rd_bank_1_id[4:0]]; + assign hazardVec_9 = + queryVec_9_rd_bank_0_valid & _GEN[queryVec_9_rd_bank_0_id[4:0]] + | queryVec_9_rd_bank_1_valid & _GEN[queryVec_9_rd_bank_1_id[4:0]]; + assign hazardVec_10 = + queryVec_10_rd_bank_0_valid & _GEN[queryVec_10_rd_bank_0_id[4:0]] + | queryVec_10_rd_bank_1_valid & _GEN[queryVec_10_rd_bank_1_id[4:0]]; + assign hazardVec_11 = + queryVec_11_rd_bank_0_valid & _GEN[queryVec_11_rd_bank_0_id[4:0]] + | queryVec_11_rd_bank_1_valid & _GEN[queryVec_11_rd_bank_1_id[4:0]]; + assign hazardVec_12 = + queryVec_12_rd_bank_0_valid & _GEN[queryVec_12_rd_bank_0_id[4:0]] + | queryVec_12_rd_bank_1_valid & _GEN[queryVec_12_rd_bank_1_id[4:0]]; + assign hazardVec_13 = + queryVec_13_rd_bank_0_valid & _GEN[queryVec_13_rd_bank_0_id[4:0]] + | queryVec_13_rd_bank_1_valid & _GEN[queryVec_13_rd_bank_1_id[4:0]]; + assign hazardVec_14 = + queryVec_14_rd_bank_0_valid & _GEN[queryVec_14_rd_bank_0_id[4:0]] + | queryVec_14_rd_bank_1_valid & _GEN[queryVec_14_rd_bank_1_id[4:0]]; + assign hazardVec_15 = + queryVec_15_rd_bank_0_valid & _GEN[queryVec_15_rd_bank_0_id[4:0]] + | queryVec_15_rd_bank_1_valid & _GEN[queryVec_15_rd_bank_1_id[4:0]]; +endmodule + +// external module ITraceDPI + +// VCS coverage exclude_file +module robOperands_16x128( + input [3:0] R0_addr, + input R0_en, + R0_clk, + output [127:0] R0_data, + input [3:0] W0_addr, + input W0_en, + W0_clk, + input [127:0] W0_data +); + + reg [127:0] Memory[0:15]; + reg _R0_en_d0; + reg [3:0] _R0_addr_d0; + always @(posedge R0_clk) begin + _R0_en_d0 <= R0_en; + _R0_addr_d0 <= R0_addr; + end // always @(posedge) + always @(posedge W0_clk) begin + if (W0_en & 1'h1) + Memory[W0_addr] <= W0_data; + end // always @(posedge) + assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 128'bx; +endmodule + +module GlobalROB( + input clock, + reset, + output io_alloc_ready, + input io_alloc_valid, + input [3:0] io_alloc_bits_domain_id, + input [4:0] io_alloc_bits_ball_bid, + input [31:0] io_alloc_bits_cmd_raw_inst, + input [63:0] io_alloc_bits_cmd_pc, + input [6:0] io_alloc_bits_cmd_funct, + input [2:0] io_alloc_bits_cmd_funct3, + input [4:0] io_alloc_bits_cmd_rs2, + io_alloc_bits_cmd_rs1, + input io_alloc_bits_cmd_xd, + io_alloc_bits_cmd_xs1, + io_alloc_bits_cmd_xs2, + input [4:0] io_alloc_bits_cmd_rd, + input [6:0] io_alloc_bits_cmd_opcode, + input [63:0] io_alloc_bits_cmd_rs1Data, + io_alloc_bits_cmd_rs2Data, + input io_alloc_bits_bankAccess_rd_bank_0_valid, + input [9:0] io_alloc_bits_bankAccess_rd_bank_0_id, + input io_alloc_bits_bankAccess_rd_bank_1_valid, + input [9:0] io_alloc_bits_bankAccess_rd_bank_1_id, + input io_alloc_bits_bankAccess_wr_bank_valid, + input [9:0] io_alloc_bits_bankAccess_wr_bank_id, + input io_alloc_bits_isFence, + io_alloc_bits_isBarrier, + io_issue_ready, + output io_issue_valid, + output [3:0] io_issue_bits_cmd_domain_id, + output [4:0] io_issue_bits_cmd_ball_bid, + output [31:0] io_issue_bits_cmd_cmd_raw_inst, + output [63:0] io_issue_bits_cmd_cmd_pc, + output [6:0] io_issue_bits_cmd_cmd_funct, + output [2:0] io_issue_bits_cmd_cmd_funct3, + output [4:0] io_issue_bits_cmd_cmd_rs2, + io_issue_bits_cmd_cmd_rs1, + output io_issue_bits_cmd_cmd_xd, + io_issue_bits_cmd_cmd_xs1, + io_issue_bits_cmd_cmd_xs2, + output [4:0] io_issue_bits_cmd_cmd_rd, + output [6:0] io_issue_bits_cmd_cmd_opcode, + output [63:0] io_issue_bits_cmd_cmd_rs1Data, + io_issue_bits_cmd_cmd_rs2Data, + output io_issue_bits_cmd_bankAccess_rd_bank_0_valid, + output [9:0] io_issue_bits_cmd_bankAccess_rd_bank_0_id, + output io_issue_bits_cmd_bankAccess_rd_bank_1_valid, + output [9:0] io_issue_bits_cmd_bankAccess_rd_bank_1_id, + output io_issue_bits_cmd_bankAccess_wr_bank_valid, + output [9:0] io_issue_bits_cmd_bankAccess_wr_bank_id, + output [3:0] io_issue_bits_cmd_op1_col, + io_issue_bits_cmd_op2_col, + io_issue_bits_cmd_wr_col, + output io_issue_bits_cmd_isFence, + io_issue_bits_cmd_isBarrier, + io_issue_bits_renamedBankAccess_rd_bank_0_valid, + output [9:0] io_issue_bits_renamedBankAccess_rd_bank_0_id, + output io_issue_bits_renamedBankAccess_rd_bank_1_valid, + output [9:0] io_issue_bits_renamedBankAccess_rd_bank_1_id, + output io_issue_bits_renamedBankAccess_wr_bank_valid, + output [9:0] io_issue_bits_renamedBankAccess_wr_bank_id, + output [3:0] io_issue_bits_rob_id, + input io_complete_valid, + input [3:0] io_complete_bits, + output io_empty, + io_full, + output [3:0] io_head_ptr, + output [4:0] io_issued_count, + output io_entry_valid_0, + io_entry_valid_1, + io_entry_valid_2, + io_entry_valid_3, + io_entry_valid_4, + io_entry_valid_5, + io_entry_valid_6, + io_entry_valid_7, + io_entry_valid_8, + io_entry_valid_9, + io_entry_valid_10, + io_entry_valid_11, + io_entry_valid_12, + io_entry_valid_13, + io_entry_valid_14, + io_entry_valid_15, + io_entry_complete_0, + io_entry_complete_1, + io_entry_complete_2, + io_entry_complete_3, + io_entry_complete_4, + io_entry_complete_5, + io_entry_complete_6, + io_entry_complete_7, + io_entry_complete_8, + io_entry_complete_9, + io_entry_complete_10, + io_entry_complete_11, + io_entry_complete_12, + io_entry_complete_13, + io_entry_complete_14, + io_entry_complete_15, + input io_subRobActive, + output [63:0] io_inst_ids_0, + io_inst_ids_1, + io_inst_ids_2, + io_inst_ids_3, + io_inst_ids_4, + io_inst_ids_5, + io_inst_ids_6, + io_inst_ids_7, + io_inst_ids_8, + io_inst_ids_9, + io_inst_ids_10, + io_inst_ids_11, + io_inst_ids_12, + io_inst_ids_13, + io_inst_ids_14, + io_inst_ids_15 +); + + wire commitMask_15; + wire commitMask_14; + wire commitMask_13; + wire commitMask_12; + wire commitMask_11; + wire commitMask_10; + wire commitMask_9; + wire commitMask_8; + wire commitMask_7; + wire commitMask_6; + wire commitMask_5; + wire commitMask_4; + wire commitMask_3; + wire commitMask_2; + wire commitMask_1; + wire commitMask_0; + wire [127:0] _robOperands_ext_R0_data; + wire _scoreboard_hazardVec_0; + wire _scoreboard_hazardVec_1; + wire _scoreboard_hazardVec_2; + wire _scoreboard_hazardVec_3; + wire _scoreboard_hazardVec_4; + wire _scoreboard_hazardVec_5; + wire _scoreboard_hazardVec_6; + wire _scoreboard_hazardVec_7; + wire _scoreboard_hazardVec_8; + wire _scoreboard_hazardVec_9; + wire _scoreboard_hazardVec_10; + wire _scoreboard_hazardVec_11; + wire _scoreboard_hazardVec_12; + wire _scoreboard_hazardVec_13; + wire _scoreboard_hazardVec_14; + wire _scoreboard_hazardVec_15; + wire _bat_io_alloc_renamed_rd_bank_0_valid; + wire [9:0] _bat_io_alloc_renamed_rd_bank_0_id; + wire _bat_io_alloc_renamed_rd_bank_1_valid; + wire [9:0] _bat_io_alloc_renamed_rd_bank_1_id; + wire _bat_io_alloc_renamed_wr_bank_valid; + wire [9:0] _bat_io_alloc_renamed_wr_bank_id; + reg [3:0] robEntries_0_cmd_domain_id; + reg [4:0] robEntries_0_cmd_ball_bid; + reg [31:0] robEntries_0_cmd_cmd_raw_inst; + reg [63:0] robEntries_0_cmd_cmd_pc; + reg [6:0] robEntries_0_cmd_cmd_funct; + reg [2:0] robEntries_0_cmd_cmd_funct3; + reg [4:0] robEntries_0_cmd_cmd_rs2; + reg [4:0] robEntries_0_cmd_cmd_rs1; + reg robEntries_0_cmd_cmd_xd; + reg robEntries_0_cmd_cmd_xs1; + reg robEntries_0_cmd_cmd_xs2; + reg [4:0] robEntries_0_cmd_cmd_rd; + reg [6:0] robEntries_0_cmd_cmd_opcode; + reg [63:0] robEntries_0_cmd_cmd_rs1Data; + reg [63:0] robEntries_0_cmd_cmd_rs2Data; + reg robEntries_0_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_0_cmd_bankAccess_rd_bank_0_id; + reg robEntries_0_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_0_cmd_bankAccess_rd_bank_1_id; + reg robEntries_0_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_0_cmd_bankAccess_wr_bank_id; + reg robEntries_0_cmd_isFence; + reg robEntries_0_cmd_isBarrier; + reg robEntries_0_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_0_renamedBankAccess_rd_bank_0_id; + reg robEntries_0_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_0_renamedBankAccess_rd_bank_1_id; + reg robEntries_0_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_0_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_0_rob_id; + reg [3:0] robEntries_1_cmd_domain_id; + reg [4:0] robEntries_1_cmd_ball_bid; + reg [31:0] robEntries_1_cmd_cmd_raw_inst; + reg [63:0] robEntries_1_cmd_cmd_pc; + reg [6:0] robEntries_1_cmd_cmd_funct; + reg [2:0] robEntries_1_cmd_cmd_funct3; + reg [4:0] robEntries_1_cmd_cmd_rs2; + reg [4:0] robEntries_1_cmd_cmd_rs1; + reg robEntries_1_cmd_cmd_xd; + reg robEntries_1_cmd_cmd_xs1; + reg robEntries_1_cmd_cmd_xs2; + reg [4:0] robEntries_1_cmd_cmd_rd; + reg [6:0] robEntries_1_cmd_cmd_opcode; + reg [63:0] robEntries_1_cmd_cmd_rs1Data; + reg [63:0] robEntries_1_cmd_cmd_rs2Data; + reg robEntries_1_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_1_cmd_bankAccess_rd_bank_0_id; + reg robEntries_1_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_1_cmd_bankAccess_rd_bank_1_id; + reg robEntries_1_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_1_cmd_bankAccess_wr_bank_id; + reg robEntries_1_cmd_isFence; + reg robEntries_1_cmd_isBarrier; + reg robEntries_1_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_1_renamedBankAccess_rd_bank_0_id; + reg robEntries_1_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_1_renamedBankAccess_rd_bank_1_id; + reg robEntries_1_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_1_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_1_rob_id; + reg [3:0] robEntries_2_cmd_domain_id; + reg [4:0] robEntries_2_cmd_ball_bid; + reg [31:0] robEntries_2_cmd_cmd_raw_inst; + reg [63:0] robEntries_2_cmd_cmd_pc; + reg [6:0] robEntries_2_cmd_cmd_funct; + reg [2:0] robEntries_2_cmd_cmd_funct3; + reg [4:0] robEntries_2_cmd_cmd_rs2; + reg [4:0] robEntries_2_cmd_cmd_rs1; + reg robEntries_2_cmd_cmd_xd; + reg robEntries_2_cmd_cmd_xs1; + reg robEntries_2_cmd_cmd_xs2; + reg [4:0] robEntries_2_cmd_cmd_rd; + reg [6:0] robEntries_2_cmd_cmd_opcode; + reg [63:0] robEntries_2_cmd_cmd_rs1Data; + reg [63:0] robEntries_2_cmd_cmd_rs2Data; + reg robEntries_2_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_2_cmd_bankAccess_rd_bank_0_id; + reg robEntries_2_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_2_cmd_bankAccess_rd_bank_1_id; + reg robEntries_2_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_2_cmd_bankAccess_wr_bank_id; + reg robEntries_2_cmd_isFence; + reg robEntries_2_cmd_isBarrier; + reg robEntries_2_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_2_renamedBankAccess_rd_bank_0_id; + reg robEntries_2_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_2_renamedBankAccess_rd_bank_1_id; + reg robEntries_2_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_2_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_2_rob_id; + reg [3:0] robEntries_3_cmd_domain_id; + reg [4:0] robEntries_3_cmd_ball_bid; + reg [31:0] robEntries_3_cmd_cmd_raw_inst; + reg [63:0] robEntries_3_cmd_cmd_pc; + reg [6:0] robEntries_3_cmd_cmd_funct; + reg [2:0] robEntries_3_cmd_cmd_funct3; + reg [4:0] robEntries_3_cmd_cmd_rs2; + reg [4:0] robEntries_3_cmd_cmd_rs1; + reg robEntries_3_cmd_cmd_xd; + reg robEntries_3_cmd_cmd_xs1; + reg robEntries_3_cmd_cmd_xs2; + reg [4:0] robEntries_3_cmd_cmd_rd; + reg [6:0] robEntries_3_cmd_cmd_opcode; + reg [63:0] robEntries_3_cmd_cmd_rs1Data; + reg [63:0] robEntries_3_cmd_cmd_rs2Data; + reg robEntries_3_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_3_cmd_bankAccess_rd_bank_0_id; + reg robEntries_3_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_3_cmd_bankAccess_rd_bank_1_id; + reg robEntries_3_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_3_cmd_bankAccess_wr_bank_id; + reg robEntries_3_cmd_isFence; + reg robEntries_3_cmd_isBarrier; + reg robEntries_3_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_3_renamedBankAccess_rd_bank_0_id; + reg robEntries_3_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_3_renamedBankAccess_rd_bank_1_id; + reg robEntries_3_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_3_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_3_rob_id; + reg [3:0] robEntries_4_cmd_domain_id; + reg [4:0] robEntries_4_cmd_ball_bid; + reg [31:0] robEntries_4_cmd_cmd_raw_inst; + reg [63:0] robEntries_4_cmd_cmd_pc; + reg [6:0] robEntries_4_cmd_cmd_funct; + reg [2:0] robEntries_4_cmd_cmd_funct3; + reg [4:0] robEntries_4_cmd_cmd_rs2; + reg [4:0] robEntries_4_cmd_cmd_rs1; + reg robEntries_4_cmd_cmd_xd; + reg robEntries_4_cmd_cmd_xs1; + reg robEntries_4_cmd_cmd_xs2; + reg [4:0] robEntries_4_cmd_cmd_rd; + reg [6:0] robEntries_4_cmd_cmd_opcode; + reg [63:0] robEntries_4_cmd_cmd_rs1Data; + reg [63:0] robEntries_4_cmd_cmd_rs2Data; + reg robEntries_4_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_4_cmd_bankAccess_rd_bank_0_id; + reg robEntries_4_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_4_cmd_bankAccess_rd_bank_1_id; + reg robEntries_4_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_4_cmd_bankAccess_wr_bank_id; + reg robEntries_4_cmd_isFence; + reg robEntries_4_cmd_isBarrier; + reg robEntries_4_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_4_renamedBankAccess_rd_bank_0_id; + reg robEntries_4_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_4_renamedBankAccess_rd_bank_1_id; + reg robEntries_4_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_4_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_4_rob_id; + reg [3:0] robEntries_5_cmd_domain_id; + reg [4:0] robEntries_5_cmd_ball_bid; + reg [31:0] robEntries_5_cmd_cmd_raw_inst; + reg [63:0] robEntries_5_cmd_cmd_pc; + reg [6:0] robEntries_5_cmd_cmd_funct; + reg [2:0] robEntries_5_cmd_cmd_funct3; + reg [4:0] robEntries_5_cmd_cmd_rs2; + reg [4:0] robEntries_5_cmd_cmd_rs1; + reg robEntries_5_cmd_cmd_xd; + reg robEntries_5_cmd_cmd_xs1; + reg robEntries_5_cmd_cmd_xs2; + reg [4:0] robEntries_5_cmd_cmd_rd; + reg [6:0] robEntries_5_cmd_cmd_opcode; + reg [63:0] robEntries_5_cmd_cmd_rs1Data; + reg [63:0] robEntries_5_cmd_cmd_rs2Data; + reg robEntries_5_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_5_cmd_bankAccess_rd_bank_0_id; + reg robEntries_5_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_5_cmd_bankAccess_rd_bank_1_id; + reg robEntries_5_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_5_cmd_bankAccess_wr_bank_id; + reg robEntries_5_cmd_isFence; + reg robEntries_5_cmd_isBarrier; + reg robEntries_5_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_5_renamedBankAccess_rd_bank_0_id; + reg robEntries_5_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_5_renamedBankAccess_rd_bank_1_id; + reg robEntries_5_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_5_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_5_rob_id; + reg [3:0] robEntries_6_cmd_domain_id; + reg [4:0] robEntries_6_cmd_ball_bid; + reg [31:0] robEntries_6_cmd_cmd_raw_inst; + reg [63:0] robEntries_6_cmd_cmd_pc; + reg [6:0] robEntries_6_cmd_cmd_funct; + reg [2:0] robEntries_6_cmd_cmd_funct3; + reg [4:0] robEntries_6_cmd_cmd_rs2; + reg [4:0] robEntries_6_cmd_cmd_rs1; + reg robEntries_6_cmd_cmd_xd; + reg robEntries_6_cmd_cmd_xs1; + reg robEntries_6_cmd_cmd_xs2; + reg [4:0] robEntries_6_cmd_cmd_rd; + reg [6:0] robEntries_6_cmd_cmd_opcode; + reg [63:0] robEntries_6_cmd_cmd_rs1Data; + reg [63:0] robEntries_6_cmd_cmd_rs2Data; + reg robEntries_6_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_6_cmd_bankAccess_rd_bank_0_id; + reg robEntries_6_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_6_cmd_bankAccess_rd_bank_1_id; + reg robEntries_6_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_6_cmd_bankAccess_wr_bank_id; + reg robEntries_6_cmd_isFence; + reg robEntries_6_cmd_isBarrier; + reg robEntries_6_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_6_renamedBankAccess_rd_bank_0_id; + reg robEntries_6_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_6_renamedBankAccess_rd_bank_1_id; + reg robEntries_6_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_6_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_6_rob_id; + reg [3:0] robEntries_7_cmd_domain_id; + reg [4:0] robEntries_7_cmd_ball_bid; + reg [31:0] robEntries_7_cmd_cmd_raw_inst; + reg [63:0] robEntries_7_cmd_cmd_pc; + reg [6:0] robEntries_7_cmd_cmd_funct; + reg [2:0] robEntries_7_cmd_cmd_funct3; + reg [4:0] robEntries_7_cmd_cmd_rs2; + reg [4:0] robEntries_7_cmd_cmd_rs1; + reg robEntries_7_cmd_cmd_xd; + reg robEntries_7_cmd_cmd_xs1; + reg robEntries_7_cmd_cmd_xs2; + reg [4:0] robEntries_7_cmd_cmd_rd; + reg [6:0] robEntries_7_cmd_cmd_opcode; + reg [63:0] robEntries_7_cmd_cmd_rs1Data; + reg [63:0] robEntries_7_cmd_cmd_rs2Data; + reg robEntries_7_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_7_cmd_bankAccess_rd_bank_0_id; + reg robEntries_7_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_7_cmd_bankAccess_rd_bank_1_id; + reg robEntries_7_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_7_cmd_bankAccess_wr_bank_id; + reg robEntries_7_cmd_isFence; + reg robEntries_7_cmd_isBarrier; + reg robEntries_7_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_7_renamedBankAccess_rd_bank_0_id; + reg robEntries_7_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_7_renamedBankAccess_rd_bank_1_id; + reg robEntries_7_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_7_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_7_rob_id; + reg [3:0] robEntries_8_cmd_domain_id; + reg [4:0] robEntries_8_cmd_ball_bid; + reg [31:0] robEntries_8_cmd_cmd_raw_inst; + reg [63:0] robEntries_8_cmd_cmd_pc; + reg [6:0] robEntries_8_cmd_cmd_funct; + reg [2:0] robEntries_8_cmd_cmd_funct3; + reg [4:0] robEntries_8_cmd_cmd_rs2; + reg [4:0] robEntries_8_cmd_cmd_rs1; + reg robEntries_8_cmd_cmd_xd; + reg robEntries_8_cmd_cmd_xs1; + reg robEntries_8_cmd_cmd_xs2; + reg [4:0] robEntries_8_cmd_cmd_rd; + reg [6:0] robEntries_8_cmd_cmd_opcode; + reg [63:0] robEntries_8_cmd_cmd_rs1Data; + reg [63:0] robEntries_8_cmd_cmd_rs2Data; + reg robEntries_8_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_8_cmd_bankAccess_rd_bank_0_id; + reg robEntries_8_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_8_cmd_bankAccess_rd_bank_1_id; + reg robEntries_8_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_8_cmd_bankAccess_wr_bank_id; + reg robEntries_8_cmd_isFence; + reg robEntries_8_cmd_isBarrier; + reg robEntries_8_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_8_renamedBankAccess_rd_bank_0_id; + reg robEntries_8_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_8_renamedBankAccess_rd_bank_1_id; + reg robEntries_8_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_8_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_8_rob_id; + reg [3:0] robEntries_9_cmd_domain_id; + reg [4:0] robEntries_9_cmd_ball_bid; + reg [31:0] robEntries_9_cmd_cmd_raw_inst; + reg [63:0] robEntries_9_cmd_cmd_pc; + reg [6:0] robEntries_9_cmd_cmd_funct; + reg [2:0] robEntries_9_cmd_cmd_funct3; + reg [4:0] robEntries_9_cmd_cmd_rs2; + reg [4:0] robEntries_9_cmd_cmd_rs1; + reg robEntries_9_cmd_cmd_xd; + reg robEntries_9_cmd_cmd_xs1; + reg robEntries_9_cmd_cmd_xs2; + reg [4:0] robEntries_9_cmd_cmd_rd; + reg [6:0] robEntries_9_cmd_cmd_opcode; + reg [63:0] robEntries_9_cmd_cmd_rs1Data; + reg [63:0] robEntries_9_cmd_cmd_rs2Data; + reg robEntries_9_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_9_cmd_bankAccess_rd_bank_0_id; + reg robEntries_9_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_9_cmd_bankAccess_rd_bank_1_id; + reg robEntries_9_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_9_cmd_bankAccess_wr_bank_id; + reg robEntries_9_cmd_isFence; + reg robEntries_9_cmd_isBarrier; + reg robEntries_9_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_9_renamedBankAccess_rd_bank_0_id; + reg robEntries_9_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_9_renamedBankAccess_rd_bank_1_id; + reg robEntries_9_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_9_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_9_rob_id; + reg [3:0] robEntries_10_cmd_domain_id; + reg [4:0] robEntries_10_cmd_ball_bid; + reg [31:0] robEntries_10_cmd_cmd_raw_inst; + reg [63:0] robEntries_10_cmd_cmd_pc; + reg [6:0] robEntries_10_cmd_cmd_funct; + reg [2:0] robEntries_10_cmd_cmd_funct3; + reg [4:0] robEntries_10_cmd_cmd_rs2; + reg [4:0] robEntries_10_cmd_cmd_rs1; + reg robEntries_10_cmd_cmd_xd; + reg robEntries_10_cmd_cmd_xs1; + reg robEntries_10_cmd_cmd_xs2; + reg [4:0] robEntries_10_cmd_cmd_rd; + reg [6:0] robEntries_10_cmd_cmd_opcode; + reg [63:0] robEntries_10_cmd_cmd_rs1Data; + reg [63:0] robEntries_10_cmd_cmd_rs2Data; + reg robEntries_10_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_10_cmd_bankAccess_rd_bank_0_id; + reg robEntries_10_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_10_cmd_bankAccess_rd_bank_1_id; + reg robEntries_10_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_10_cmd_bankAccess_wr_bank_id; + reg robEntries_10_cmd_isFence; + reg robEntries_10_cmd_isBarrier; + reg robEntries_10_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_10_renamedBankAccess_rd_bank_0_id; + reg robEntries_10_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_10_renamedBankAccess_rd_bank_1_id; + reg robEntries_10_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_10_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_10_rob_id; + reg [3:0] robEntries_11_cmd_domain_id; + reg [4:0] robEntries_11_cmd_ball_bid; + reg [31:0] robEntries_11_cmd_cmd_raw_inst; + reg [63:0] robEntries_11_cmd_cmd_pc; + reg [6:0] robEntries_11_cmd_cmd_funct; + reg [2:0] robEntries_11_cmd_cmd_funct3; + reg [4:0] robEntries_11_cmd_cmd_rs2; + reg [4:0] robEntries_11_cmd_cmd_rs1; + reg robEntries_11_cmd_cmd_xd; + reg robEntries_11_cmd_cmd_xs1; + reg robEntries_11_cmd_cmd_xs2; + reg [4:0] robEntries_11_cmd_cmd_rd; + reg [6:0] robEntries_11_cmd_cmd_opcode; + reg [63:0] robEntries_11_cmd_cmd_rs1Data; + reg [63:0] robEntries_11_cmd_cmd_rs2Data; + reg robEntries_11_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_11_cmd_bankAccess_rd_bank_0_id; + reg robEntries_11_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_11_cmd_bankAccess_rd_bank_1_id; + reg robEntries_11_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_11_cmd_bankAccess_wr_bank_id; + reg robEntries_11_cmd_isFence; + reg robEntries_11_cmd_isBarrier; + reg robEntries_11_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_11_renamedBankAccess_rd_bank_0_id; + reg robEntries_11_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_11_renamedBankAccess_rd_bank_1_id; + reg robEntries_11_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_11_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_11_rob_id; + reg [3:0] robEntries_12_cmd_domain_id; + reg [4:0] robEntries_12_cmd_ball_bid; + reg [31:0] robEntries_12_cmd_cmd_raw_inst; + reg [63:0] robEntries_12_cmd_cmd_pc; + reg [6:0] robEntries_12_cmd_cmd_funct; + reg [2:0] robEntries_12_cmd_cmd_funct3; + reg [4:0] robEntries_12_cmd_cmd_rs2; + reg [4:0] robEntries_12_cmd_cmd_rs1; + reg robEntries_12_cmd_cmd_xd; + reg robEntries_12_cmd_cmd_xs1; + reg robEntries_12_cmd_cmd_xs2; + reg [4:0] robEntries_12_cmd_cmd_rd; + reg [6:0] robEntries_12_cmd_cmd_opcode; + reg [63:0] robEntries_12_cmd_cmd_rs1Data; + reg [63:0] robEntries_12_cmd_cmd_rs2Data; + reg robEntries_12_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_12_cmd_bankAccess_rd_bank_0_id; + reg robEntries_12_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_12_cmd_bankAccess_rd_bank_1_id; + reg robEntries_12_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_12_cmd_bankAccess_wr_bank_id; + reg robEntries_12_cmd_isFence; + reg robEntries_12_cmd_isBarrier; + reg robEntries_12_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_12_renamedBankAccess_rd_bank_0_id; + reg robEntries_12_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_12_renamedBankAccess_rd_bank_1_id; + reg robEntries_12_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_12_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_12_rob_id; + reg [3:0] robEntries_13_cmd_domain_id; + reg [4:0] robEntries_13_cmd_ball_bid; + reg [31:0] robEntries_13_cmd_cmd_raw_inst; + reg [63:0] robEntries_13_cmd_cmd_pc; + reg [6:0] robEntries_13_cmd_cmd_funct; + reg [2:0] robEntries_13_cmd_cmd_funct3; + reg [4:0] robEntries_13_cmd_cmd_rs2; + reg [4:0] robEntries_13_cmd_cmd_rs1; + reg robEntries_13_cmd_cmd_xd; + reg robEntries_13_cmd_cmd_xs1; + reg robEntries_13_cmd_cmd_xs2; + reg [4:0] robEntries_13_cmd_cmd_rd; + reg [6:0] robEntries_13_cmd_cmd_opcode; + reg [63:0] robEntries_13_cmd_cmd_rs1Data; + reg [63:0] robEntries_13_cmd_cmd_rs2Data; + reg robEntries_13_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_13_cmd_bankAccess_rd_bank_0_id; + reg robEntries_13_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_13_cmd_bankAccess_rd_bank_1_id; + reg robEntries_13_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_13_cmd_bankAccess_wr_bank_id; + reg robEntries_13_cmd_isFence; + reg robEntries_13_cmd_isBarrier; + reg robEntries_13_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_13_renamedBankAccess_rd_bank_0_id; + reg robEntries_13_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_13_renamedBankAccess_rd_bank_1_id; + reg robEntries_13_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_13_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_13_rob_id; + reg [3:0] robEntries_14_cmd_domain_id; + reg [4:0] robEntries_14_cmd_ball_bid; + reg [31:0] robEntries_14_cmd_cmd_raw_inst; + reg [63:0] robEntries_14_cmd_cmd_pc; + reg [6:0] robEntries_14_cmd_cmd_funct; + reg [2:0] robEntries_14_cmd_cmd_funct3; + reg [4:0] robEntries_14_cmd_cmd_rs2; + reg [4:0] robEntries_14_cmd_cmd_rs1; + reg robEntries_14_cmd_cmd_xd; + reg robEntries_14_cmd_cmd_xs1; + reg robEntries_14_cmd_cmd_xs2; + reg [4:0] robEntries_14_cmd_cmd_rd; + reg [6:0] robEntries_14_cmd_cmd_opcode; + reg [63:0] robEntries_14_cmd_cmd_rs1Data; + reg [63:0] robEntries_14_cmd_cmd_rs2Data; + reg robEntries_14_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_14_cmd_bankAccess_rd_bank_0_id; + reg robEntries_14_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_14_cmd_bankAccess_rd_bank_1_id; + reg robEntries_14_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_14_cmd_bankAccess_wr_bank_id; + reg robEntries_14_cmd_isFence; + reg robEntries_14_cmd_isBarrier; + reg robEntries_14_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_14_renamedBankAccess_rd_bank_0_id; + reg robEntries_14_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_14_renamedBankAccess_rd_bank_1_id; + reg robEntries_14_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_14_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_14_rob_id; + reg [3:0] robEntries_15_cmd_domain_id; + reg [4:0] robEntries_15_cmd_ball_bid; + reg [31:0] robEntries_15_cmd_cmd_raw_inst; + reg [63:0] robEntries_15_cmd_cmd_pc; + reg [6:0] robEntries_15_cmd_cmd_funct; + reg [2:0] robEntries_15_cmd_cmd_funct3; + reg [4:0] robEntries_15_cmd_cmd_rs2; + reg [4:0] robEntries_15_cmd_cmd_rs1; + reg robEntries_15_cmd_cmd_xd; + reg robEntries_15_cmd_cmd_xs1; + reg robEntries_15_cmd_cmd_xs2; + reg [4:0] robEntries_15_cmd_cmd_rd; + reg [6:0] robEntries_15_cmd_cmd_opcode; + reg [63:0] robEntries_15_cmd_cmd_rs1Data; + reg [63:0] robEntries_15_cmd_cmd_rs2Data; + reg robEntries_15_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_15_cmd_bankAccess_rd_bank_0_id; + reg robEntries_15_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_15_cmd_bankAccess_rd_bank_1_id; + reg robEntries_15_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_15_cmd_bankAccess_wr_bank_id; + reg robEntries_15_cmd_isFence; + reg robEntries_15_cmd_isBarrier; + reg robEntries_15_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_15_renamedBankAccess_rd_bank_0_id; + reg robEntries_15_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_15_renamedBankAccess_rd_bank_1_id; + reg robEntries_15_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_15_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_15_rob_id; + reg robValid_0; + reg robValid_1; + reg robValid_2; + reg robValid_3; + reg robValid_4; + reg robValid_5; + reg robValid_6; + reg robValid_7; + reg robValid_8; + reg robValid_9; + reg robValid_10; + reg robValid_11; + reg robValid_12; + reg robValid_13; + reg robValid_14; + reg robValid_15; + reg robIssued_0; + reg robIssued_1; + reg robIssued_2; + reg robIssued_3; + reg robIssued_4; + reg robIssued_5; + reg robIssued_6; + reg robIssued_7; + reg robIssued_8; + reg robIssued_9; + reg robIssued_10; + reg robIssued_11; + reg robIssued_12; + reg robIssued_13; + reg robIssued_14; + reg robIssued_15; + reg robComplete_0; + reg robComplete_1; + reg robComplete_2; + reg robComplete_3; + reg robComplete_4; + reg robComplete_5; + reg robComplete_6; + reg robComplete_7; + reg robComplete_8; + reg robComplete_9; + reg robComplete_10; + reg robComplete_11; + reg robComplete_12; + reg robComplete_13; + reg robComplete_14; + reg robComplete_15; + reg [63:0] instIds_0; + reg [63:0] instIds_1; + reg [63:0] instIds_2; + reg [63:0] instIds_3; + reg [63:0] instIds_4; + reg [63:0] instIds_5; + reg [63:0] instIds_6; + reg [63:0] instIds_7; + reg [63:0] instIds_8; + reg [63:0] instIds_9; + reg [63:0] instIds_10; + reg [63:0] instIds_11; + reg [63:0] instIds_12; + reg [63:0] instIds_13; + reg [63:0] instIds_14; + reg [63:0] instIds_15; + reg [63:0] nextInstId; + reg [3:0] ptr; + reg [3:0] tailPtr; + reg [4:0] issuedCount; + reg [3:0] bankCols_0; + reg [3:0] bankCols_1; + reg [3:0] bankCols_2; + reg [3:0] bankCols_3; + reg [3:0] bankCols_4; + reg [3:0] bankCols_5; + reg [3:0] bankCols_6; + reg [3:0] bankCols_7; + reg [3:0] bankCols_8; + reg [3:0] bankCols_9; + reg [3:0] bankCols_10; + reg [3:0] bankCols_11; + reg [3:0] bankCols_12; + reg [3:0] bankCols_13; + reg [3:0] bankCols_14; + reg [3:0] bankCols_15; + reg [15:0] vbankBusy; + reg [15:0] dependencyMask_0; + reg [15:0] dependencyMask_1; + reg [15:0] dependencyMask_2; + reg [15:0] dependencyMask_3; + reg [15:0] dependencyMask_4; + reg [15:0] dependencyMask_5; + reg [15:0] dependencyMask_6; + reg [15:0] dependencyMask_7; + reg [15:0] dependencyMask_8; + reg [15:0] dependencyMask_9; + reg [15:0] dependencyMask_10; + reg [15:0] dependencyMask_11; + reg [15:0] dependencyMask_12; + reg [15:0] dependencyMask_13; + reg [15:0] dependencyMask_14; + reg [15:0] dependencyMask_15; + wire _isFull_T = ptr == tailPtr; + wire [15:0] _GEN = + {{robValid_15}, + {robValid_14}, + {robValid_13}, + {robValid_12}, + {robValid_11}, + {robValid_10}, + {robValid_9}, + {robValid_8}, + {robValid_7}, + {robValid_6}, + {robValid_5}, + {robValid_4}, + {robValid_3}, + {robValid_2}, + {robValid_1}, + {robValid_0}}; + wire _GEN_0 = _GEN[ptr]; + wire isFull = _isFull_T & _GEN_0; + wire [15:0] _GEN_1 = + {{robComplete_15}, + {robComplete_14}, + {robComplete_13}, + {robComplete_12}, + {robComplete_11}, + {robComplete_10}, + {robComplete_9}, + {robComplete_8}, + {robComplete_7}, + {robComplete_6}, + {robComplete_5}, + {robComplete_4}, + {robComplete_3}, + {robComplete_2}, + {robComplete_1}, + {robComplete_0}}; + wire _GEN_2 = _GEN_1[ptr]; + wire commitKeep_1 = _GEN_0 & _GEN_2; + wire [3:0] _hits_ptr_T_1446 = ptr + 4'h1; + wire commitKeep_2 = + commitKeep_1 & _GEN[_hits_ptr_T_1446] & _GEN_1[_hits_ptr_T_1446]; + wire [3:0] _hits_ptr_T_1452 = ptr + 4'h2; + wire commitKeep_3 = + commitKeep_2 & _GEN[_hits_ptr_T_1452] & _GEN_1[_hits_ptr_T_1452]; + wire [3:0] _hits_ptr_T_1458 = ptr + 4'h3; + wire commitKeep_4 = + commitKeep_3 & _GEN[_hits_ptr_T_1458] & _GEN_1[_hits_ptr_T_1458]; + wire [3:0] _hits_ptr_T_1464 = ptr + 4'h4; + wire commitKeep_5 = + commitKeep_4 & _GEN[_hits_ptr_T_1464] & _GEN_1[_hits_ptr_T_1464]; + wire [3:0] _hits_ptr_T_1470 = ptr + 4'h5; + wire commitKeep_6 = + commitKeep_5 & _GEN[_hits_ptr_T_1470] & _GEN_1[_hits_ptr_T_1470]; + wire [3:0] _hits_ptr_T_1476 = ptr + 4'h6; + wire commitKeep_7 = + commitKeep_6 & _GEN[_hits_ptr_T_1476] & _GEN_1[_hits_ptr_T_1476]; + wire [3:0] _hits_ptr_T_1482 = ptr + 4'h7; + wire commitKeep_8 = + commitKeep_7 & _GEN[_hits_ptr_T_1482] & _GEN_1[_hits_ptr_T_1482]; + wire [3:0] _hits_ptr_T_1488 = ptr - 4'h8; + wire commitKeep_9 = + commitKeep_8 & _GEN[_hits_ptr_T_1488] & _GEN_1[_hits_ptr_T_1488]; + wire [3:0] _hits_ptr_T_1494 = ptr - 4'h7; + wire commitScan_9 = + commitKeep_9 & _GEN[_hits_ptr_T_1494] & _GEN_1[_hits_ptr_T_1494]; + wire [3:0] _hits_ptr_T_1500 = ptr - 4'h6; + wire commitKeep_11 = + commitScan_9 & _GEN[_hits_ptr_T_1500] & _GEN_1[_hits_ptr_T_1500]; + wire [3:0] _hits_ptr_T_1506 = ptr - 4'h5; + wire commitKeep_12 = + commitKeep_11 & _GEN[_hits_ptr_T_1506] & _GEN_1[_hits_ptr_T_1506]; + wire [3:0] _hits_ptr_T_1512 = ptr - 4'h4; + wire commitKeep_13 = + commitKeep_12 & _GEN[_hits_ptr_T_1512] & _GEN_1[_hits_ptr_T_1512]; + wire [3:0] _hits_ptr_T_1518 = ptr - 4'h3; + wire commitKeep_14 = + commitKeep_13 & _GEN[_hits_ptr_T_1518] & _GEN_1[_hits_ptr_T_1518]; + wire [3:0] _hits_ptr_T_1524 = ptr - 4'h2; + wire commitKeep_15 = + commitKeep_14 & _GEN[_hits_ptr_T_1524] & _GEN_1[_hits_ptr_T_1524]; + wire [3:0] _hits_ptr_T_1530 = ptr - 4'h1; + wire commitScan_15 = + commitKeep_15 & _GEN[_hits_ptr_T_1530] & _GEN_1[_hits_ptr_T_1530]; + wire [9:0] _tailAlias_T = {6'h0, tailPtr} + 10'h10; + wire io_alloc_ready_0 = + ~isFull + & {commitScan_15, + commitKeep_15, + commitKeep_14, + commitKeep_13, + commitKeep_12, + commitKeep_11, + commitScan_9, + commitKeep_9, + commitKeep_8, + commitKeep_7, + commitKeep_6, + commitKeep_5, + commitKeep_4, + commitKeep_3, + commitKeep_2, + commitKeep_1} == 16'h0 + & ~(robValid_15 & ~robComplete_15 + & (robEntries_15_renamedBankAccess_rd_bank_0_valid + & robEntries_15_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_15_renamedBankAccess_rd_bank_1_valid + & robEntries_15_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_15_renamedBankAccess_wr_bank_valid + & robEntries_15_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_14 + & ~robComplete_14 + & (robEntries_14_renamedBankAccess_rd_bank_0_valid + & robEntries_14_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_14_renamedBankAccess_rd_bank_1_valid + & robEntries_14_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_14_renamedBankAccess_wr_bank_valid + & robEntries_14_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_13 + & ~robComplete_13 + & (robEntries_13_renamedBankAccess_rd_bank_0_valid + & robEntries_13_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_13_renamedBankAccess_rd_bank_1_valid + & robEntries_13_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_13_renamedBankAccess_wr_bank_valid + & robEntries_13_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_12 + & ~robComplete_12 + & (robEntries_12_renamedBankAccess_rd_bank_0_valid + & robEntries_12_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_12_renamedBankAccess_rd_bank_1_valid + & robEntries_12_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_12_renamedBankAccess_wr_bank_valid + & robEntries_12_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_11 + & ~robComplete_11 + & (robEntries_11_renamedBankAccess_rd_bank_0_valid + & robEntries_11_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_11_renamedBankAccess_rd_bank_1_valid + & robEntries_11_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_11_renamedBankAccess_wr_bank_valid + & robEntries_11_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_10 + & ~robComplete_10 + & (robEntries_10_renamedBankAccess_rd_bank_0_valid + & robEntries_10_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_10_renamedBankAccess_rd_bank_1_valid + & robEntries_10_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_10_renamedBankAccess_wr_bank_valid + & robEntries_10_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_9 + & ~robComplete_9 + & (robEntries_9_renamedBankAccess_rd_bank_0_valid + & robEntries_9_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_9_renamedBankAccess_rd_bank_1_valid + & robEntries_9_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_9_renamedBankAccess_wr_bank_valid + & robEntries_9_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_8 + & ~robComplete_8 + & (robEntries_8_renamedBankAccess_rd_bank_0_valid + & robEntries_8_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_8_renamedBankAccess_rd_bank_1_valid + & robEntries_8_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_8_renamedBankAccess_wr_bank_valid + & robEntries_8_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_7 + & ~robComplete_7 + & (robEntries_7_renamedBankAccess_rd_bank_0_valid + & robEntries_7_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_7_renamedBankAccess_rd_bank_1_valid + & robEntries_7_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_7_renamedBankAccess_wr_bank_valid + & robEntries_7_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_6 + & ~robComplete_6 + & (robEntries_6_renamedBankAccess_rd_bank_0_valid + & robEntries_6_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_6_renamedBankAccess_rd_bank_1_valid + & robEntries_6_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_6_renamedBankAccess_wr_bank_valid + & robEntries_6_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_5 + & ~robComplete_5 + & (robEntries_5_renamedBankAccess_rd_bank_0_valid + & robEntries_5_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_5_renamedBankAccess_rd_bank_1_valid + & robEntries_5_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_5_renamedBankAccess_wr_bank_valid + & robEntries_5_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_4 + & ~robComplete_4 + & (robEntries_4_renamedBankAccess_rd_bank_0_valid + & robEntries_4_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_4_renamedBankAccess_rd_bank_1_valid + & robEntries_4_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_4_renamedBankAccess_wr_bank_valid + & robEntries_4_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_3 + & ~robComplete_3 + & (robEntries_3_renamedBankAccess_rd_bank_0_valid + & robEntries_3_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_3_renamedBankAccess_rd_bank_1_valid + & robEntries_3_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_3_renamedBankAccess_wr_bank_valid + & robEntries_3_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_2 + & ~robComplete_2 + & (robEntries_2_renamedBankAccess_rd_bank_0_valid + & robEntries_2_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_2_renamedBankAccess_rd_bank_1_valid + & robEntries_2_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_2_renamedBankAccess_wr_bank_valid + & robEntries_2_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_1 + & ~robComplete_1 + & (robEntries_1_renamedBankAccess_rd_bank_0_valid + & robEntries_1_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_1_renamedBankAccess_rd_bank_1_valid + & robEntries_1_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_1_renamedBankAccess_wr_bank_valid + & robEntries_1_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_0 + & ~robComplete_0 + & (robEntries_0_renamedBankAccess_rd_bank_0_valid + & robEntries_0_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_0_renamedBankAccess_rd_bank_1_valid + & robEntries_0_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_0_renamedBankAccess_wr_bank_valid + & robEntries_0_renamedBankAccess_wr_bank_id == _tailAlias_T)); + wire _isAllocatedSlot_T_30 = io_alloc_ready_0 & io_alloc_valid; + wire [15:0] entryRawWrites_0 = + robEntries_0_cmd_bankAccess_wr_bank_valid + & robEntries_0_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_0_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_1 = + robEntries_1_cmd_bankAccess_wr_bank_valid + & robEntries_1_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_1_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_2 = + robEntries_2_cmd_bankAccess_wr_bank_valid + & robEntries_2_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_2_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_3 = + robEntries_3_cmd_bankAccess_wr_bank_valid + & robEntries_3_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_3_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_4 = + robEntries_4_cmd_bankAccess_wr_bank_valid + & robEntries_4_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_4_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_5 = + robEntries_5_cmd_bankAccess_wr_bank_valid + & robEntries_5_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_5_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_6 = + robEntries_6_cmd_bankAccess_wr_bank_valid + & robEntries_6_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_6_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_7 = + robEntries_7_cmd_bankAccess_wr_bank_valid + & robEntries_7_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_7_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_8 = + robEntries_8_cmd_bankAccess_wr_bank_valid + & robEntries_8_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_8_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_9 = + robEntries_9_cmd_bankAccess_wr_bank_valid + & robEntries_9_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_9_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_10 = + robEntries_10_cmd_bankAccess_wr_bank_valid + & robEntries_10_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_10_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_11 = + robEntries_11_cmd_bankAccess_wr_bank_valid + & robEntries_11_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_11_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_12 = + robEntries_12_cmd_bankAccess_wr_bank_valid + & robEntries_12_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_12_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_13 = + robEntries_13_cmd_bankAccess_wr_bank_valid + & robEntries_13_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_13_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_14 = + robEntries_14_cmd_bankAccess_wr_bank_valid + & robEntries_14_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_14_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_15 = + robEntries_15_cmd_bankAccess_wr_bank_valid + & robEntries_15_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_15_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] olderUseMask = + (robEntries_0_cmd_bankAccess_rd_bank_0_valid + & robEntries_0_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_0_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_0_cmd_bankAccess_rd_bank_1_valid + & robEntries_0_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_0_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_0; + wire [15:0] vbankMasks_1 = + (robEntries_1_cmd_bankAccess_rd_bank_0_valid + & robEntries_1_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_1_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_1_cmd_bankAccess_rd_bank_1_valid + & robEntries_1_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_1_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_1; + wire [15:0] vbankMasks_2 = + (robEntries_2_cmd_bankAccess_rd_bank_0_valid + & robEntries_2_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_2_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_2_cmd_bankAccess_rd_bank_1_valid + & robEntries_2_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_2_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_2; + wire [15:0] vbankMasks_3 = + (robEntries_3_cmd_bankAccess_rd_bank_0_valid + & robEntries_3_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_3_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_3_cmd_bankAccess_rd_bank_1_valid + & robEntries_3_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_3_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_3; + wire [15:0] vbankMasks_4 = + (robEntries_4_cmd_bankAccess_rd_bank_0_valid + & robEntries_4_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_4_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_4_cmd_bankAccess_rd_bank_1_valid + & robEntries_4_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_4_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_4; + wire [15:0] vbankMasks_5 = + (robEntries_5_cmd_bankAccess_rd_bank_0_valid + & robEntries_5_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_5_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_5_cmd_bankAccess_rd_bank_1_valid + & robEntries_5_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_5_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_5; + wire [15:0] vbankMasks_6 = + (robEntries_6_cmd_bankAccess_rd_bank_0_valid + & robEntries_6_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_6_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_6_cmd_bankAccess_rd_bank_1_valid + & robEntries_6_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_6_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_6; + wire [15:0] vbankMasks_7 = + (robEntries_7_cmd_bankAccess_rd_bank_0_valid + & robEntries_7_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_7_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_7_cmd_bankAccess_rd_bank_1_valid + & robEntries_7_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_7_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_7; + wire [15:0] vbankMasks_8 = + (robEntries_8_cmd_bankAccess_rd_bank_0_valid + & robEntries_8_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_8_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_8_cmd_bankAccess_rd_bank_1_valid + & robEntries_8_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_8_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_8; + wire [15:0] vbankMasks_9 = + (robEntries_9_cmd_bankAccess_rd_bank_0_valid + & robEntries_9_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_9_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_9_cmd_bankAccess_rd_bank_1_valid + & robEntries_9_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_9_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_9; + wire [15:0] vbankMasks_10 = + (robEntries_10_cmd_bankAccess_rd_bank_0_valid + & robEntries_10_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_10_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_10_cmd_bankAccess_rd_bank_1_valid + & robEntries_10_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_10_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_10; + wire [15:0] vbankMasks_11 = + (robEntries_11_cmd_bankAccess_rd_bank_0_valid + & robEntries_11_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_11_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_11_cmd_bankAccess_rd_bank_1_valid + & robEntries_11_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_11_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_11; + wire [15:0] vbankMasks_12 = + (robEntries_12_cmd_bankAccess_rd_bank_0_valid + & robEntries_12_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_12_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_12_cmd_bankAccess_rd_bank_1_valid + & robEntries_12_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_12_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_12; + wire [15:0] vbankMasks_13 = + (robEntries_13_cmd_bankAccess_rd_bank_0_valid + & robEntries_13_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_13_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_13_cmd_bankAccess_rd_bank_1_valid + & robEntries_13_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_13_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_13; + wire [15:0] vbankMasks_14 = + (robEntries_14_cmd_bankAccess_rd_bank_0_valid + & robEntries_14_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_14_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_14_cmd_bankAccess_rd_bank_1_valid + & robEntries_14_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_14_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_14; + wire [15:0] vbankMasks_15 = + (robEntries_15_cmd_bankAccess_rd_bank_0_valid + & robEntries_15_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_15_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_15_cmd_bankAccess_rd_bank_1_valid + & robEntries_15_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_15_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_15; + wire _GEN_3 = _isAllocatedSlot_T_30 & (|io_alloc_bits_cmd_pc); + wire [15:0] _GEN_4 = + {{robIssued_15}, + {robIssued_14}, + {robIssued_13}, + {robIssued_12}, + {robIssued_11}, + {robIssued_10}, + {robIssued_9}, + {robIssued_8}, + {robIssued_7}, + {robIssued_6}, + {robIssued_5}, + {robIssued_4}, + {robIssued_3}, + {robIssued_2}, + {robIssued_1}, + {robIssued_0}}; + wire [15:0][3:0] _GEN_5 = + {{robEntries_15_cmd_domain_id}, + {robEntries_14_cmd_domain_id}, + {robEntries_13_cmd_domain_id}, + {robEntries_12_cmd_domain_id}, + {robEntries_11_cmd_domain_id}, + {robEntries_10_cmd_domain_id}, + {robEntries_9_cmd_domain_id}, + {robEntries_8_cmd_domain_id}, + {robEntries_7_cmd_domain_id}, + {robEntries_6_cmd_domain_id}, + {robEntries_5_cmd_domain_id}, + {robEntries_4_cmd_domain_id}, + {robEntries_3_cmd_domain_id}, + {robEntries_2_cmd_domain_id}, + {robEntries_1_cmd_domain_id}, + {robEntries_0_cmd_domain_id}}; + wire [15:0][63:0] _GEN_6 = + {{robEntries_15_cmd_cmd_pc}, + {robEntries_14_cmd_cmd_pc}, + {robEntries_13_cmd_cmd_pc}, + {robEntries_12_cmd_cmd_pc}, + {robEntries_11_cmd_cmd_pc}, + {robEntries_10_cmd_cmd_pc}, + {robEntries_9_cmd_cmd_pc}, + {robEntries_8_cmd_cmd_pc}, + {robEntries_7_cmd_cmd_pc}, + {robEntries_6_cmd_cmd_pc}, + {robEntries_5_cmd_cmd_pc}, + {robEntries_4_cmd_cmd_pc}, + {robEntries_3_cmd_cmd_pc}, + {robEntries_2_cmd_cmd_pc}, + {robEntries_1_cmd_cmd_pc}, + {robEntries_0_cmd_cmd_pc}}; + wire [15:0][6:0] _GEN_7 = + {{robEntries_15_cmd_cmd_funct}, + {robEntries_14_cmd_cmd_funct}, + {robEntries_13_cmd_cmd_funct}, + {robEntries_12_cmd_cmd_funct}, + {robEntries_11_cmd_cmd_funct}, + {robEntries_10_cmd_cmd_funct}, + {robEntries_9_cmd_cmd_funct}, + {robEntries_8_cmd_cmd_funct}, + {robEntries_7_cmd_cmd_funct}, + {robEntries_6_cmd_cmd_funct}, + {robEntries_5_cmd_cmd_funct}, + {robEntries_4_cmd_cmd_funct}, + {robEntries_3_cmd_cmd_funct}, + {robEntries_2_cmd_cmd_funct}, + {robEntries_1_cmd_cmd_funct}, + {robEntries_0_cmd_cmd_funct}}; + wire [15:0][63:0] _GEN_8 = + {{robEntries_15_cmd_cmd_rs1Data}, + {robEntries_14_cmd_cmd_rs1Data}, + {robEntries_13_cmd_cmd_rs1Data}, + {robEntries_12_cmd_cmd_rs1Data}, + {robEntries_11_cmd_cmd_rs1Data}, + {robEntries_10_cmd_cmd_rs1Data}, + {robEntries_9_cmd_cmd_rs1Data}, + {robEntries_8_cmd_cmd_rs1Data}, + {robEntries_7_cmd_cmd_rs1Data}, + {robEntries_6_cmd_cmd_rs1Data}, + {robEntries_5_cmd_cmd_rs1Data}, + {robEntries_4_cmd_cmd_rs1Data}, + {robEntries_3_cmd_cmd_rs1Data}, + {robEntries_2_cmd_cmd_rs1Data}, + {robEntries_1_cmd_cmd_rs1Data}, + {robEntries_0_cmd_cmd_rs1Data}}; + wire [15:0][63:0] _GEN_9 = + {{robEntries_15_cmd_cmd_rs2Data}, + {robEntries_14_cmd_cmd_rs2Data}, + {robEntries_13_cmd_cmd_rs2Data}, + {robEntries_12_cmd_cmd_rs2Data}, + {robEntries_11_cmd_cmd_rs2Data}, + {robEntries_10_cmd_cmd_rs2Data}, + {robEntries_9_cmd_cmd_rs2Data}, + {robEntries_8_cmd_cmd_rs2Data}, + {robEntries_7_cmd_cmd_rs2Data}, + {robEntries_6_cmd_cmd_rs2Data}, + {robEntries_5_cmd_cmd_rs2Data}, + {robEntries_4_cmd_cmd_rs2Data}, + {robEntries_3_cmd_cmd_rs2Data}, + {robEntries_2_cmd_cmd_rs2Data}, + {robEntries_1_cmd_cmd_rs2Data}, + {robEntries_0_cmd_cmd_rs2Data}}; + wire [15:0] _GEN_10 = + {{robEntries_15_renamedBankAccess_wr_bank_valid}, + {robEntries_14_renamedBankAccess_wr_bank_valid}, + {robEntries_13_renamedBankAccess_wr_bank_valid}, + {robEntries_12_renamedBankAccess_wr_bank_valid}, + {robEntries_11_renamedBankAccess_wr_bank_valid}, + {robEntries_10_renamedBankAccess_wr_bank_valid}, + {robEntries_9_renamedBankAccess_wr_bank_valid}, + {robEntries_8_renamedBankAccess_wr_bank_valid}, + {robEntries_7_renamedBankAccess_wr_bank_valid}, + {robEntries_6_renamedBankAccess_wr_bank_valid}, + {robEntries_5_renamedBankAccess_wr_bank_valid}, + {robEntries_4_renamedBankAccess_wr_bank_valid}, + {robEntries_3_renamedBankAccess_wr_bank_valid}, + {robEntries_2_renamedBankAccess_wr_bank_valid}, + {robEntries_1_renamedBankAccess_wr_bank_valid}, + {robEntries_0_renamedBankAccess_wr_bank_valid}}; + wire [15:0][9:0] _GEN_11 = + {{robEntries_15_renamedBankAccess_wr_bank_id}, + {robEntries_14_renamedBankAccess_wr_bank_id}, + {robEntries_13_renamedBankAccess_wr_bank_id}, + {robEntries_12_renamedBankAccess_wr_bank_id}, + {robEntries_11_renamedBankAccess_wr_bank_id}, + {robEntries_10_renamedBankAccess_wr_bank_id}, + {robEntries_9_renamedBankAccess_wr_bank_id}, + {robEntries_8_renamedBankAccess_wr_bank_id}, + {robEntries_7_renamedBankAccess_wr_bank_id}, + {robEntries_6_renamedBankAccess_wr_bank_id}, + {robEntries_5_renamedBankAccess_wr_bank_id}, + {robEntries_4_renamedBankAccess_wr_bank_id}, + {robEntries_3_renamedBankAccess_wr_bank_id}, + {robEntries_2_renamedBankAccess_wr_bank_id}, + {robEntries_1_renamedBankAccess_wr_bank_id}, + {robEntries_0_renamedBankAccess_wr_bank_id}}; + wire [15:0][63:0] _GEN_12 = + {{instIds_15}, + {instIds_14}, + {instIds_13}, + {instIds_12}, + {instIds_11}, + {instIds_10}, + {instIds_9}, + {instIds_8}, + {instIds_7}, + {instIds_6}, + {instIds_5}, + {instIds_4}, + {instIds_3}, + {instIds_2}, + {instIds_1}, + {instIds_0}}; + wire [15:0] _GEN_13 = + {{robEntries_15_renamedBankAccess_rd_bank_0_valid}, + {robEntries_14_renamedBankAccess_rd_bank_0_valid}, + {robEntries_13_renamedBankAccess_rd_bank_0_valid}, + {robEntries_12_renamedBankAccess_rd_bank_0_valid}, + {robEntries_11_renamedBankAccess_rd_bank_0_valid}, + {robEntries_10_renamedBankAccess_rd_bank_0_valid}, + {robEntries_9_renamedBankAccess_rd_bank_0_valid}, + {robEntries_8_renamedBankAccess_rd_bank_0_valid}, + {robEntries_7_renamedBankAccess_rd_bank_0_valid}, + {robEntries_6_renamedBankAccess_rd_bank_0_valid}, + {robEntries_5_renamedBankAccess_rd_bank_0_valid}, + {robEntries_4_renamedBankAccess_rd_bank_0_valid}, + {robEntries_3_renamedBankAccess_rd_bank_0_valid}, + {robEntries_2_renamedBankAccess_rd_bank_0_valid}, + {robEntries_1_renamedBankAccess_rd_bank_0_valid}, + {robEntries_0_renamedBankAccess_rd_bank_0_valid}}; + wire [15:0][9:0] _GEN_14 = + {{robEntries_15_renamedBankAccess_rd_bank_0_id}, + {robEntries_14_renamedBankAccess_rd_bank_0_id}, + {robEntries_13_renamedBankAccess_rd_bank_0_id}, + {robEntries_12_renamedBankAccess_rd_bank_0_id}, + {robEntries_11_renamedBankAccess_rd_bank_0_id}, + {robEntries_10_renamedBankAccess_rd_bank_0_id}, + {robEntries_9_renamedBankAccess_rd_bank_0_id}, + {robEntries_8_renamedBankAccess_rd_bank_0_id}, + {robEntries_7_renamedBankAccess_rd_bank_0_id}, + {robEntries_6_renamedBankAccess_rd_bank_0_id}, + {robEntries_5_renamedBankAccess_rd_bank_0_id}, + {robEntries_4_renamedBankAccess_rd_bank_0_id}, + {robEntries_3_renamedBankAccess_rd_bank_0_id}, + {robEntries_2_renamedBankAccess_rd_bank_0_id}, + {robEntries_1_renamedBankAccess_rd_bank_0_id}, + {robEntries_0_renamedBankAccess_rd_bank_0_id}}; + wire [15:0] _GEN_15 = + {{robEntries_15_renamedBankAccess_rd_bank_1_valid}, + {robEntries_14_renamedBankAccess_rd_bank_1_valid}, + {robEntries_13_renamedBankAccess_rd_bank_1_valid}, + {robEntries_12_renamedBankAccess_rd_bank_1_valid}, + {robEntries_11_renamedBankAccess_rd_bank_1_valid}, + {robEntries_10_renamedBankAccess_rd_bank_1_valid}, + {robEntries_9_renamedBankAccess_rd_bank_1_valid}, + {robEntries_8_renamedBankAccess_rd_bank_1_valid}, + {robEntries_7_renamedBankAccess_rd_bank_1_valid}, + {robEntries_6_renamedBankAccess_rd_bank_1_valid}, + {robEntries_5_renamedBankAccess_rd_bank_1_valid}, + {robEntries_4_renamedBankAccess_rd_bank_1_valid}, + {robEntries_3_renamedBankAccess_rd_bank_1_valid}, + {robEntries_2_renamedBankAccess_rd_bank_1_valid}, + {robEntries_1_renamedBankAccess_rd_bank_1_valid}, + {robEntries_0_renamedBankAccess_rd_bank_1_valid}}; + wire [15:0][9:0] _GEN_16 = + {{robEntries_15_renamedBankAccess_rd_bank_1_id}, + {robEntries_14_renamedBankAccess_rd_bank_1_id}, + {robEntries_13_renamedBankAccess_rd_bank_1_id}, + {robEntries_12_renamedBankAccess_rd_bank_1_id}, + {robEntries_11_renamedBankAccess_rd_bank_1_id}, + {robEntries_10_renamedBankAccess_rd_bank_1_id}, + {robEntries_9_renamedBankAccess_rd_bank_1_id}, + {robEntries_8_renamedBankAccess_rd_bank_1_id}, + {robEntries_7_renamedBankAccess_rd_bank_1_id}, + {robEntries_6_renamedBankAccess_rd_bank_1_id}, + {robEntries_5_renamedBankAccess_rd_bank_1_id}, + {robEntries_4_renamedBankAccess_rd_bank_1_id}, + {robEntries_3_renamedBankAccess_rd_bank_1_id}, + {robEntries_2_renamedBankAccess_rd_bank_1_id}, + {robEntries_1_renamedBankAccess_rd_bank_1_id}, + {robEntries_0_renamedBankAccess_rd_bank_1_id}}; + wire [15:0][15:0] _GEN_17 = + {{dependencyMask_15}, + {dependencyMask_14}, + {dependencyMask_13}, + {dependencyMask_12}, + {dependencyMask_11}, + {dependencyMask_10}, + {dependencyMask_9}, + {dependencyMask_8}, + {dependencyMask_7}, + {dependencyMask_6}, + {dependencyMask_5}, + {dependencyMask_4}, + {dependencyMask_3}, + {dependencyMask_2}, + {dependencyMask_1}, + {dependencyMask_0}}; + wire [15:0][15:0] _GEN_18 = + {{vbankMasks_15}, + {vbankMasks_14}, + {vbankMasks_13}, + {vbankMasks_12}, + {vbankMasks_11}, + {vbankMasks_10}, + {vbankMasks_9}, + {vbankMasks_8}, + {vbankMasks_7}, + {vbankMasks_6}, + {vbankMasks_5}, + {vbankMasks_4}, + {vbankMasks_3}, + {vbankMasks_2}, + {vbankMasks_1}, + {olderUseMask}}; + wire scanReady_0 = + _GEN_0 & ~_GEN_4[ptr] & ~_GEN_2 & ~_scoreboard_hazardVec_0 & _GEN_17[ptr] == 16'h0 + & (_GEN_18[ptr] & vbankBusy) == 16'h0; + wire scanReady_1 = + _GEN[_hits_ptr_T_1446] & ~_GEN_4[_hits_ptr_T_1446] & ~_GEN_1[_hits_ptr_T_1446] + & ~_scoreboard_hazardVec_1 & _GEN_17[_hits_ptr_T_1446] == 16'h0 + & (_GEN_18[_hits_ptr_T_1446] & vbankBusy) == 16'h0; + wire scanReady_2 = + _GEN[_hits_ptr_T_1452] & ~_GEN_4[_hits_ptr_T_1452] & ~_GEN_1[_hits_ptr_T_1452] + & ~_scoreboard_hazardVec_2 & _GEN_17[_hits_ptr_T_1452] == 16'h0 + & (_GEN_18[_hits_ptr_T_1452] & vbankBusy) == 16'h0; + wire scanReady_3 = + _GEN[_hits_ptr_T_1458] & ~_GEN_4[_hits_ptr_T_1458] & ~_GEN_1[_hits_ptr_T_1458] + & ~_scoreboard_hazardVec_3 & _GEN_17[_hits_ptr_T_1458] == 16'h0 + & (_GEN_18[_hits_ptr_T_1458] & vbankBusy) == 16'h0; + wire scanReady_4 = + _GEN[_hits_ptr_T_1464] & ~_GEN_4[_hits_ptr_T_1464] & ~_GEN_1[_hits_ptr_T_1464] + & ~_scoreboard_hazardVec_4 & _GEN_17[_hits_ptr_T_1464] == 16'h0 + & (_GEN_18[_hits_ptr_T_1464] & vbankBusy) == 16'h0; + wire scanReady_5 = + _GEN[_hits_ptr_T_1470] & ~_GEN_4[_hits_ptr_T_1470] & ~_GEN_1[_hits_ptr_T_1470] + & ~_scoreboard_hazardVec_5 & _GEN_17[_hits_ptr_T_1470] == 16'h0 + & (_GEN_18[_hits_ptr_T_1470] & vbankBusy) == 16'h0; + wire scanReady_6 = + _GEN[_hits_ptr_T_1476] & ~_GEN_4[_hits_ptr_T_1476] & ~_GEN_1[_hits_ptr_T_1476] + & ~_scoreboard_hazardVec_6 & _GEN_17[_hits_ptr_T_1476] == 16'h0 + & (_GEN_18[_hits_ptr_T_1476] & vbankBusy) == 16'h0; + wire scanReady_7 = + _GEN[_hits_ptr_T_1482] & ~_GEN_4[_hits_ptr_T_1482] & ~_GEN_1[_hits_ptr_T_1482] + & ~_scoreboard_hazardVec_7 & _GEN_17[_hits_ptr_T_1482] == 16'h0 + & (_GEN_18[_hits_ptr_T_1482] & vbankBusy) == 16'h0; + wire scanReady_8 = + _GEN[_hits_ptr_T_1488] & ~_GEN_4[_hits_ptr_T_1488] & ~_GEN_1[_hits_ptr_T_1488] + & ~_scoreboard_hazardVec_8 & _GEN_17[_hits_ptr_T_1488] == 16'h0 + & (_GEN_18[_hits_ptr_T_1488] & vbankBusy) == 16'h0; + wire scanReady_9 = + _GEN[_hits_ptr_T_1494] & ~_GEN_4[_hits_ptr_T_1494] & ~_GEN_1[_hits_ptr_T_1494] + & ~_scoreboard_hazardVec_9 & _GEN_17[_hits_ptr_T_1494] == 16'h0 + & (_GEN_18[_hits_ptr_T_1494] & vbankBusy) == 16'h0; + wire scanReady_10 = + _GEN[_hits_ptr_T_1500] & ~_GEN_4[_hits_ptr_T_1500] & ~_GEN_1[_hits_ptr_T_1500] + & ~_scoreboard_hazardVec_10 & _GEN_17[_hits_ptr_T_1500] == 16'h0 + & (_GEN_18[_hits_ptr_T_1500] & vbankBusy) == 16'h0; + wire scanReady_11 = + _GEN[_hits_ptr_T_1506] & ~_GEN_4[_hits_ptr_T_1506] & ~_GEN_1[_hits_ptr_T_1506] + & ~_scoreboard_hazardVec_11 & _GEN_17[_hits_ptr_T_1506] == 16'h0 + & (_GEN_18[_hits_ptr_T_1506] & vbankBusy) == 16'h0; + wire scanReady_12 = + _GEN[_hits_ptr_T_1512] & ~_GEN_4[_hits_ptr_T_1512] & ~_GEN_1[_hits_ptr_T_1512] + & ~_scoreboard_hazardVec_12 & _GEN_17[_hits_ptr_T_1512] == 16'h0 + & (_GEN_18[_hits_ptr_T_1512] & vbankBusy) == 16'h0; + wire scanReady_13 = + _GEN[_hits_ptr_T_1518] & ~_GEN_4[_hits_ptr_T_1518] & ~_GEN_1[_hits_ptr_T_1518] + & ~_scoreboard_hazardVec_13 & _GEN_17[_hits_ptr_T_1518] == 16'h0 + & (_GEN_18[_hits_ptr_T_1518] & vbankBusy) == 16'h0; + wire scanReady_14 = + _GEN[_hits_ptr_T_1524] & ~_GEN_4[_hits_ptr_T_1524] & ~_GEN_1[_hits_ptr_T_1524] + & ~_scoreboard_hazardVec_14 & _GEN_17[_hits_ptr_T_1524] == 16'h0 + & (_GEN_18[_hits_ptr_T_1524] & vbankBusy) == 16'h0; + wire [3:0] _actualIssuePtr_T = + ptr + + (scanReady_0 + ? 4'h0 + : scanReady_1 + ? 4'h1 + : scanReady_2 + ? 4'h2 + : scanReady_3 + ? 4'h3 + : scanReady_4 + ? 4'h4 + : scanReady_5 + ? 4'h5 + : scanReady_6 + ? 4'h6 + : scanReady_7 + ? 4'h7 + : scanReady_8 + ? 4'h8 + : scanReady_9 + ? 4'h9 + : scanReady_10 + ? 4'hA + : scanReady_11 + ? 4'hB + : scanReady_12 + ? 4'hC + : scanReady_13 + ? 4'hD + : {3'h7, ~scanReady_14}); + wire [15:0][3:0] _GEN_19 = + {{robEntries_15_rob_id}, + {robEntries_14_rob_id}, + {robEntries_13_rob_id}, + {robEntries_12_rob_id}, + {robEntries_11_rob_id}, + {robEntries_10_rob_id}, + {robEntries_9_rob_id}, + {robEntries_8_rob_id}, + {robEntries_7_rob_id}, + {robEntries_6_rob_id}, + {robEntries_5_rob_id}, + {robEntries_4_rob_id}, + {robEntries_3_rob_id}, + {robEntries_2_rob_id}, + {robEntries_1_rob_id}, + {robEntries_0_rob_id}}; + reg issueStageValid; + reg [3:0] issueStageEntry_cmd_domain_id; + reg [4:0] issueStageEntry_cmd_ball_bid; + reg [31:0] issueStageEntry_cmd_cmd_raw_inst; + reg [63:0] issueStageEntry_cmd_cmd_pc; + reg [6:0] issueStageEntry_cmd_cmd_funct; + reg [2:0] issueStageEntry_cmd_cmd_funct3; + reg [4:0] issueStageEntry_cmd_cmd_rs2; + reg [4:0] issueStageEntry_cmd_cmd_rs1; + reg issueStageEntry_cmd_cmd_xd; + reg issueStageEntry_cmd_cmd_xs1; + reg issueStageEntry_cmd_cmd_xs2; + reg [4:0] issueStageEntry_cmd_cmd_rd; + reg [6:0] issueStageEntry_cmd_cmd_opcode; + reg [63:0] issueStageEntry_cmd_cmd_rs1Data; + reg [63:0] issueStageEntry_cmd_cmd_rs2Data; + reg issueStageEntry_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] issueStageEntry_cmd_bankAccess_rd_bank_0_id; + reg issueStageEntry_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] issueStageEntry_cmd_bankAccess_rd_bank_1_id; + reg issueStageEntry_cmd_bankAccess_wr_bank_valid; + reg [9:0] issueStageEntry_cmd_bankAccess_wr_bank_id; + reg [3:0] issueStageEntry_cmd_op1_col; + reg [3:0] issueStageEntry_cmd_op2_col; + reg [3:0] issueStageEntry_cmd_wr_col; + reg issueStageEntry_cmd_isFence; + reg issueStageEntry_cmd_isBarrier; + reg issueStageEntry_renamedBankAccess_rd_bank_0_valid; + reg [9:0] issueStageEntry_renamedBankAccess_rd_bank_0_id; + reg issueStageEntry_renamedBankAccess_rd_bank_1_valid; + reg [9:0] issueStageEntry_renamedBankAccess_rd_bank_1_id; + reg issueStageEntry_renamedBankAccess_wr_bank_valid; + reg [9:0] issueStageEntry_renamedBankAccess_wr_bank_id; + reg [3:0] issueStageEntry_rob_id; + wire issueStageReady = + ~issueStageValid | issueStageValid & ~io_subRobActive & io_issue_ready; + reg issuePtrValid; + reg [3:0] issuePtr; + wire issuePtrFire = issuePtrValid & issueStageReady; + wire issuePtrReady = ~issuePtrValid | issuePtrFire; + wire issueLoad = + (|{_GEN[_hits_ptr_T_1530] & ~_GEN_4[_hits_ptr_T_1530] & ~_GEN_1[_hits_ptr_T_1530] + & ~_scoreboard_hazardVec_15 & _GEN_17[_hits_ptr_T_1530] == 16'h0 + & (_GEN_18[_hits_ptr_T_1530] & vbankBusy) == 16'h0, + scanReady_14, + scanReady_13, + scanReady_12, + scanReady_11, + scanReady_10, + scanReady_9, + scanReady_8, + scanReady_7, + scanReady_6, + scanReady_5, + scanReady_4, + scanReady_3, + scanReady_2, + scanReady_1, + scanReady_0}) & ~io_subRobActive & issuePtrReady; + wire [3:0] readAddress = issueLoad ? _actualIssuePtr_T : issuePtr; + wire readEnable = issueLoad | issuePtrValid; + `ifndef SYNTHESIS + always @(posedge clock) begin + if (_isAllocatedSlot_T_30 & readEnable & ~reset & tailPtr == readAddress) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: ROB operand RAM read/write collision\n at GlobalROB.scala:444 assert(tailPtr =/= readAddress, \"ROB operand RAM read/write collision\")\n"); + if (`STOP_COND_) + $fatal; + end + end // always @(posedge) + `endif // not def SYNTHESIS + assign commitMask_0 = + commitKeep_1 & ptr == 4'h0 | commitKeep_2 & _hits_ptr_T_1446 == 4'h0 | commitKeep_3 + & _hits_ptr_T_1452 == 4'h0 | commitKeep_4 & _hits_ptr_T_1458 == 4'h0 | commitKeep_5 + & _hits_ptr_T_1464 == 4'h0 | commitKeep_6 & _hits_ptr_T_1470 == 4'h0 | commitKeep_7 + & _hits_ptr_T_1476 == 4'h0 | commitKeep_8 & _hits_ptr_T_1482 == 4'h0 | commitKeep_9 + & _hits_ptr_T_1488 == 4'h0 | commitScan_9 & _hits_ptr_T_1494 == 4'h0 | commitKeep_11 + & _hits_ptr_T_1500 == 4'h0 | commitKeep_12 & _hits_ptr_T_1506 == 4'h0 | commitKeep_13 + & _hits_ptr_T_1512 == 4'h0 | commitKeep_14 & _hits_ptr_T_1518 == 4'h0 | commitKeep_15 + & _hits_ptr_T_1524 == 4'h0 | commitScan_15 & _hits_ptr_T_1530 == 4'h0; + assign commitMask_1 = + commitKeep_1 & ptr == 4'h1 | commitKeep_2 & _hits_ptr_T_1446 == 4'h1 | commitKeep_3 + & _hits_ptr_T_1452 == 4'h1 | commitKeep_4 & _hits_ptr_T_1458 == 4'h1 | commitKeep_5 + & _hits_ptr_T_1464 == 4'h1 | commitKeep_6 & _hits_ptr_T_1470 == 4'h1 | commitKeep_7 + & _hits_ptr_T_1476 == 4'h1 | commitKeep_8 & _hits_ptr_T_1482 == 4'h1 | commitKeep_9 + & _hits_ptr_T_1488 == 4'h1 | commitScan_9 & _hits_ptr_T_1494 == 4'h1 | commitKeep_11 + & _hits_ptr_T_1500 == 4'h1 | commitKeep_12 & _hits_ptr_T_1506 == 4'h1 | commitKeep_13 + & _hits_ptr_T_1512 == 4'h1 | commitKeep_14 & _hits_ptr_T_1518 == 4'h1 | commitKeep_15 + & _hits_ptr_T_1524 == 4'h1 | commitScan_15 & _hits_ptr_T_1530 == 4'h1; + assign commitMask_2 = + commitKeep_1 & ptr == 4'h2 | commitKeep_2 & _hits_ptr_T_1446 == 4'h2 | commitKeep_3 + & _hits_ptr_T_1452 == 4'h2 | commitKeep_4 & _hits_ptr_T_1458 == 4'h2 | commitKeep_5 + & _hits_ptr_T_1464 == 4'h2 | commitKeep_6 & _hits_ptr_T_1470 == 4'h2 | commitKeep_7 + & _hits_ptr_T_1476 == 4'h2 | commitKeep_8 & _hits_ptr_T_1482 == 4'h2 | commitKeep_9 + & _hits_ptr_T_1488 == 4'h2 | commitScan_9 & _hits_ptr_T_1494 == 4'h2 | commitKeep_11 + & _hits_ptr_T_1500 == 4'h2 | commitKeep_12 & _hits_ptr_T_1506 == 4'h2 | commitKeep_13 + & _hits_ptr_T_1512 == 4'h2 | commitKeep_14 & _hits_ptr_T_1518 == 4'h2 | commitKeep_15 + & _hits_ptr_T_1524 == 4'h2 | commitScan_15 & _hits_ptr_T_1530 == 4'h2; + assign commitMask_3 = + commitKeep_1 & ptr == 4'h3 | commitKeep_2 & _hits_ptr_T_1446 == 4'h3 | commitKeep_3 + & _hits_ptr_T_1452 == 4'h3 | commitKeep_4 & _hits_ptr_T_1458 == 4'h3 | commitKeep_5 + & _hits_ptr_T_1464 == 4'h3 | commitKeep_6 & _hits_ptr_T_1470 == 4'h3 | commitKeep_7 + & _hits_ptr_T_1476 == 4'h3 | commitKeep_8 & _hits_ptr_T_1482 == 4'h3 | commitKeep_9 + & _hits_ptr_T_1488 == 4'h3 | commitScan_9 & _hits_ptr_T_1494 == 4'h3 | commitKeep_11 + & _hits_ptr_T_1500 == 4'h3 | commitKeep_12 & _hits_ptr_T_1506 == 4'h3 | commitKeep_13 + & _hits_ptr_T_1512 == 4'h3 | commitKeep_14 & _hits_ptr_T_1518 == 4'h3 | commitKeep_15 + & _hits_ptr_T_1524 == 4'h3 | commitScan_15 & _hits_ptr_T_1530 == 4'h3; + assign commitMask_4 = + commitKeep_1 & ptr == 4'h4 | commitKeep_2 & _hits_ptr_T_1446 == 4'h4 | commitKeep_3 + & _hits_ptr_T_1452 == 4'h4 | commitKeep_4 & _hits_ptr_T_1458 == 4'h4 | commitKeep_5 + & _hits_ptr_T_1464 == 4'h4 | commitKeep_6 & _hits_ptr_T_1470 == 4'h4 | commitKeep_7 + & _hits_ptr_T_1476 == 4'h4 | commitKeep_8 & _hits_ptr_T_1482 == 4'h4 | commitKeep_9 + & _hits_ptr_T_1488 == 4'h4 | commitScan_9 & _hits_ptr_T_1494 == 4'h4 | commitKeep_11 + & _hits_ptr_T_1500 == 4'h4 | commitKeep_12 & _hits_ptr_T_1506 == 4'h4 | commitKeep_13 + & _hits_ptr_T_1512 == 4'h4 | commitKeep_14 & _hits_ptr_T_1518 == 4'h4 | commitKeep_15 + & _hits_ptr_T_1524 == 4'h4 | commitScan_15 & _hits_ptr_T_1530 == 4'h4; + assign commitMask_5 = + commitKeep_1 & ptr == 4'h5 | commitKeep_2 & _hits_ptr_T_1446 == 4'h5 | commitKeep_3 + & _hits_ptr_T_1452 == 4'h5 | commitKeep_4 & _hits_ptr_T_1458 == 4'h5 | commitKeep_5 + & _hits_ptr_T_1464 == 4'h5 | commitKeep_6 & _hits_ptr_T_1470 == 4'h5 | commitKeep_7 + & _hits_ptr_T_1476 == 4'h5 | commitKeep_8 & _hits_ptr_T_1482 == 4'h5 | commitKeep_9 + & _hits_ptr_T_1488 == 4'h5 | commitScan_9 & _hits_ptr_T_1494 == 4'h5 | commitKeep_11 + & _hits_ptr_T_1500 == 4'h5 | commitKeep_12 & _hits_ptr_T_1506 == 4'h5 | commitKeep_13 + & _hits_ptr_T_1512 == 4'h5 | commitKeep_14 & _hits_ptr_T_1518 == 4'h5 | commitKeep_15 + & _hits_ptr_T_1524 == 4'h5 | commitScan_15 & _hits_ptr_T_1530 == 4'h5; + assign commitMask_6 = + commitKeep_1 & ptr == 4'h6 | commitKeep_2 & _hits_ptr_T_1446 == 4'h6 | commitKeep_3 + & _hits_ptr_T_1452 == 4'h6 | commitKeep_4 & _hits_ptr_T_1458 == 4'h6 | commitKeep_5 + & _hits_ptr_T_1464 == 4'h6 | commitKeep_6 & _hits_ptr_T_1470 == 4'h6 | commitKeep_7 + & _hits_ptr_T_1476 == 4'h6 | commitKeep_8 & _hits_ptr_T_1482 == 4'h6 | commitKeep_9 + & _hits_ptr_T_1488 == 4'h6 | commitScan_9 & _hits_ptr_T_1494 == 4'h6 | commitKeep_11 + & _hits_ptr_T_1500 == 4'h6 | commitKeep_12 & _hits_ptr_T_1506 == 4'h6 | commitKeep_13 + & _hits_ptr_T_1512 == 4'h6 | commitKeep_14 & _hits_ptr_T_1518 == 4'h6 | commitKeep_15 + & _hits_ptr_T_1524 == 4'h6 | commitScan_15 & _hits_ptr_T_1530 == 4'h6; + assign commitMask_7 = + commitKeep_1 & ptr == 4'h7 | commitKeep_2 & _hits_ptr_T_1446 == 4'h7 | commitKeep_3 + & _hits_ptr_T_1452 == 4'h7 | commitKeep_4 & _hits_ptr_T_1458 == 4'h7 | commitKeep_5 + & _hits_ptr_T_1464 == 4'h7 | commitKeep_6 & _hits_ptr_T_1470 == 4'h7 | commitKeep_7 + & _hits_ptr_T_1476 == 4'h7 | commitKeep_8 & _hits_ptr_T_1482 == 4'h7 | commitKeep_9 + & _hits_ptr_T_1488 == 4'h7 | commitScan_9 & _hits_ptr_T_1494 == 4'h7 | commitKeep_11 + & _hits_ptr_T_1500 == 4'h7 | commitKeep_12 & _hits_ptr_T_1506 == 4'h7 | commitKeep_13 + & _hits_ptr_T_1512 == 4'h7 | commitKeep_14 & _hits_ptr_T_1518 == 4'h7 | commitKeep_15 + & _hits_ptr_T_1524 == 4'h7 | commitScan_15 & _hits_ptr_T_1530 == 4'h7; + assign commitMask_8 = + commitKeep_1 & ptr == 4'h8 | commitKeep_2 & _hits_ptr_T_1446 == 4'h8 | commitKeep_3 + & _hits_ptr_T_1452 == 4'h8 | commitKeep_4 & _hits_ptr_T_1458 == 4'h8 | commitKeep_5 + & _hits_ptr_T_1464 == 4'h8 | commitKeep_6 & _hits_ptr_T_1470 == 4'h8 | commitKeep_7 + & _hits_ptr_T_1476 == 4'h8 | commitKeep_8 & _hits_ptr_T_1482 == 4'h8 | commitKeep_9 + & _hits_ptr_T_1488 == 4'h8 | commitScan_9 & _hits_ptr_T_1494 == 4'h8 | commitKeep_11 + & _hits_ptr_T_1500 == 4'h8 | commitKeep_12 & _hits_ptr_T_1506 == 4'h8 | commitKeep_13 + & _hits_ptr_T_1512 == 4'h8 | commitKeep_14 & _hits_ptr_T_1518 == 4'h8 | commitKeep_15 + & _hits_ptr_T_1524 == 4'h8 | commitScan_15 & _hits_ptr_T_1530 == 4'h8; + assign commitMask_9 = + commitKeep_1 & ptr == 4'h9 | commitKeep_2 & _hits_ptr_T_1446 == 4'h9 | commitKeep_3 + & _hits_ptr_T_1452 == 4'h9 | commitKeep_4 & _hits_ptr_T_1458 == 4'h9 | commitKeep_5 + & _hits_ptr_T_1464 == 4'h9 | commitKeep_6 & _hits_ptr_T_1470 == 4'h9 | commitKeep_7 + & _hits_ptr_T_1476 == 4'h9 | commitKeep_8 & _hits_ptr_T_1482 == 4'h9 | commitKeep_9 + & _hits_ptr_T_1488 == 4'h9 | commitScan_9 & _hits_ptr_T_1494 == 4'h9 | commitKeep_11 + & _hits_ptr_T_1500 == 4'h9 | commitKeep_12 & _hits_ptr_T_1506 == 4'h9 | commitKeep_13 + & _hits_ptr_T_1512 == 4'h9 | commitKeep_14 & _hits_ptr_T_1518 == 4'h9 | commitKeep_15 + & _hits_ptr_T_1524 == 4'h9 | commitScan_15 & _hits_ptr_T_1530 == 4'h9; + assign commitMask_10 = + commitKeep_1 & ptr == 4'hA | commitKeep_2 & _hits_ptr_T_1446 == 4'hA | commitKeep_3 + & _hits_ptr_T_1452 == 4'hA | commitKeep_4 & _hits_ptr_T_1458 == 4'hA | commitKeep_5 + & _hits_ptr_T_1464 == 4'hA | commitKeep_6 & _hits_ptr_T_1470 == 4'hA | commitKeep_7 + & _hits_ptr_T_1476 == 4'hA | commitKeep_8 & _hits_ptr_T_1482 == 4'hA | commitKeep_9 + & _hits_ptr_T_1488 == 4'hA | commitScan_9 & _hits_ptr_T_1494 == 4'hA | commitKeep_11 + & _hits_ptr_T_1500 == 4'hA | commitKeep_12 & _hits_ptr_T_1506 == 4'hA | commitKeep_13 + & _hits_ptr_T_1512 == 4'hA | commitKeep_14 & _hits_ptr_T_1518 == 4'hA | commitKeep_15 + & _hits_ptr_T_1524 == 4'hA | commitScan_15 & _hits_ptr_T_1530 == 4'hA; + assign commitMask_11 = + commitKeep_1 & ptr == 4'hB | commitKeep_2 & _hits_ptr_T_1446 == 4'hB | commitKeep_3 + & _hits_ptr_T_1452 == 4'hB | commitKeep_4 & _hits_ptr_T_1458 == 4'hB | commitKeep_5 + & _hits_ptr_T_1464 == 4'hB | commitKeep_6 & _hits_ptr_T_1470 == 4'hB | commitKeep_7 + & _hits_ptr_T_1476 == 4'hB | commitKeep_8 & _hits_ptr_T_1482 == 4'hB | commitKeep_9 + & _hits_ptr_T_1488 == 4'hB | commitScan_9 & _hits_ptr_T_1494 == 4'hB | commitKeep_11 + & _hits_ptr_T_1500 == 4'hB | commitKeep_12 & _hits_ptr_T_1506 == 4'hB | commitKeep_13 + & _hits_ptr_T_1512 == 4'hB | commitKeep_14 & _hits_ptr_T_1518 == 4'hB | commitKeep_15 + & _hits_ptr_T_1524 == 4'hB | commitScan_15 & _hits_ptr_T_1530 == 4'hB; + assign commitMask_12 = + commitKeep_1 & ptr == 4'hC | commitKeep_2 & _hits_ptr_T_1446 == 4'hC | commitKeep_3 + & _hits_ptr_T_1452 == 4'hC | commitKeep_4 & _hits_ptr_T_1458 == 4'hC | commitKeep_5 + & _hits_ptr_T_1464 == 4'hC | commitKeep_6 & _hits_ptr_T_1470 == 4'hC | commitKeep_7 + & _hits_ptr_T_1476 == 4'hC | commitKeep_8 & _hits_ptr_T_1482 == 4'hC | commitKeep_9 + & _hits_ptr_T_1488 == 4'hC | commitScan_9 & _hits_ptr_T_1494 == 4'hC | commitKeep_11 + & _hits_ptr_T_1500 == 4'hC | commitKeep_12 & _hits_ptr_T_1506 == 4'hC | commitKeep_13 + & _hits_ptr_T_1512 == 4'hC | commitKeep_14 & _hits_ptr_T_1518 == 4'hC | commitKeep_15 + & _hits_ptr_T_1524 == 4'hC | commitScan_15 & _hits_ptr_T_1530 == 4'hC; + assign commitMask_13 = + commitKeep_1 & ptr == 4'hD | commitKeep_2 & _hits_ptr_T_1446 == 4'hD | commitKeep_3 + & _hits_ptr_T_1452 == 4'hD | commitKeep_4 & _hits_ptr_T_1458 == 4'hD | commitKeep_5 + & _hits_ptr_T_1464 == 4'hD | commitKeep_6 & _hits_ptr_T_1470 == 4'hD | commitKeep_7 + & _hits_ptr_T_1476 == 4'hD | commitKeep_8 & _hits_ptr_T_1482 == 4'hD | commitKeep_9 + & _hits_ptr_T_1488 == 4'hD | commitScan_9 & _hits_ptr_T_1494 == 4'hD | commitKeep_11 + & _hits_ptr_T_1500 == 4'hD | commitKeep_12 & _hits_ptr_T_1506 == 4'hD | commitKeep_13 + & _hits_ptr_T_1512 == 4'hD | commitKeep_14 & _hits_ptr_T_1518 == 4'hD | commitKeep_15 + & _hits_ptr_T_1524 == 4'hD | commitScan_15 & _hits_ptr_T_1530 == 4'hD; + assign commitMask_14 = + commitKeep_1 & ptr == 4'hE | commitKeep_2 & _hits_ptr_T_1446 == 4'hE | commitKeep_3 + & _hits_ptr_T_1452 == 4'hE | commitKeep_4 & _hits_ptr_T_1458 == 4'hE | commitKeep_5 + & _hits_ptr_T_1464 == 4'hE | commitKeep_6 & _hits_ptr_T_1470 == 4'hE | commitKeep_7 + & _hits_ptr_T_1476 == 4'hE | commitKeep_8 & _hits_ptr_T_1482 == 4'hE | commitKeep_9 + & _hits_ptr_T_1488 == 4'hE | commitScan_9 & _hits_ptr_T_1494 == 4'hE | commitKeep_11 + & _hits_ptr_T_1500 == 4'hE | commitKeep_12 & _hits_ptr_T_1506 == 4'hE | commitKeep_13 + & _hits_ptr_T_1512 == 4'hE | commitKeep_14 & _hits_ptr_T_1518 == 4'hE | commitKeep_15 + & _hits_ptr_T_1524 == 4'hE | commitScan_15 & _hits_ptr_T_1530 == 4'hE; + assign commitMask_15 = + commitKeep_1 & (&ptr) | commitKeep_2 & (&_hits_ptr_T_1446) | commitKeep_3 + & (&_hits_ptr_T_1452) | commitKeep_4 & (&_hits_ptr_T_1458) | commitKeep_5 + & (&_hits_ptr_T_1464) | commitKeep_6 & (&_hits_ptr_T_1470) | commitKeep_7 + & (&_hits_ptr_T_1476) | commitKeep_8 & (&_hits_ptr_T_1482) | commitKeep_9 + & (&_hits_ptr_T_1488) | commitScan_9 & (&_hits_ptr_T_1494) | commitKeep_11 + & (&_hits_ptr_T_1500) | commitKeep_12 & (&_hits_ptr_T_1506) | commitKeep_13 + & (&_hits_ptr_T_1512) | commitKeep_14 & (&_hits_ptr_T_1518) | commitKeep_15 + & (&_hits_ptr_T_1524) | commitScan_15 & (&_hits_ptr_T_1530); + always @(posedge clock) begin + if (reset) begin + robEntries_0_cmd_domain_id <= 4'h0; + robEntries_0_cmd_ball_bid <= 5'h0; + robEntries_0_cmd_cmd_raw_inst <= 32'h0; + robEntries_0_cmd_cmd_pc <= 64'h0; + robEntries_0_cmd_cmd_funct <= 7'h0; + robEntries_0_cmd_cmd_funct3 <= 3'h0; + robEntries_0_cmd_cmd_rs2 <= 5'h0; + robEntries_0_cmd_cmd_rs1 <= 5'h0; + robEntries_0_cmd_cmd_xd <= 1'h0; + robEntries_0_cmd_cmd_xs1 <= 1'h0; + robEntries_0_cmd_cmd_xs2 <= 1'h0; + robEntries_0_cmd_cmd_rd <= 5'h0; + robEntries_0_cmd_cmd_opcode <= 7'h0; + robEntries_0_cmd_cmd_rs1Data <= 64'h0; + robEntries_0_cmd_cmd_rs2Data <= 64'h0; + robEntries_0_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_0_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_0_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_0_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_0_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_0_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_0_cmd_isFence <= 1'h0; + robEntries_0_cmd_isBarrier <= 1'h0; + robEntries_0_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_0_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_0_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_0_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_0_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_0_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_0_rob_id <= 4'h0; + robEntries_1_cmd_domain_id <= 4'h0; + robEntries_1_cmd_ball_bid <= 5'h0; + robEntries_1_cmd_cmd_raw_inst <= 32'h0; + robEntries_1_cmd_cmd_pc <= 64'h0; + robEntries_1_cmd_cmd_funct <= 7'h0; + robEntries_1_cmd_cmd_funct3 <= 3'h0; + robEntries_1_cmd_cmd_rs2 <= 5'h0; + robEntries_1_cmd_cmd_rs1 <= 5'h0; + robEntries_1_cmd_cmd_xd <= 1'h0; + robEntries_1_cmd_cmd_xs1 <= 1'h0; + robEntries_1_cmd_cmd_xs2 <= 1'h0; + robEntries_1_cmd_cmd_rd <= 5'h0; + robEntries_1_cmd_cmd_opcode <= 7'h0; + robEntries_1_cmd_cmd_rs1Data <= 64'h0; + robEntries_1_cmd_cmd_rs2Data <= 64'h0; + robEntries_1_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_1_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_1_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_1_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_1_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_1_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_1_cmd_isFence <= 1'h0; + robEntries_1_cmd_isBarrier <= 1'h0; + robEntries_1_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_1_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_1_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_1_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_1_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_1_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_1_rob_id <= 4'h0; + robEntries_2_cmd_domain_id <= 4'h0; + robEntries_2_cmd_ball_bid <= 5'h0; + robEntries_2_cmd_cmd_raw_inst <= 32'h0; + robEntries_2_cmd_cmd_pc <= 64'h0; + robEntries_2_cmd_cmd_funct <= 7'h0; + robEntries_2_cmd_cmd_funct3 <= 3'h0; + robEntries_2_cmd_cmd_rs2 <= 5'h0; + robEntries_2_cmd_cmd_rs1 <= 5'h0; + robEntries_2_cmd_cmd_xd <= 1'h0; + robEntries_2_cmd_cmd_xs1 <= 1'h0; + robEntries_2_cmd_cmd_xs2 <= 1'h0; + robEntries_2_cmd_cmd_rd <= 5'h0; + robEntries_2_cmd_cmd_opcode <= 7'h0; + robEntries_2_cmd_cmd_rs1Data <= 64'h0; + robEntries_2_cmd_cmd_rs2Data <= 64'h0; + robEntries_2_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_2_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_2_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_2_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_2_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_2_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_2_cmd_isFence <= 1'h0; + robEntries_2_cmd_isBarrier <= 1'h0; + robEntries_2_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_2_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_2_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_2_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_2_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_2_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_2_rob_id <= 4'h0; + robEntries_3_cmd_domain_id <= 4'h0; + robEntries_3_cmd_ball_bid <= 5'h0; + robEntries_3_cmd_cmd_raw_inst <= 32'h0; + robEntries_3_cmd_cmd_pc <= 64'h0; + robEntries_3_cmd_cmd_funct <= 7'h0; + robEntries_3_cmd_cmd_funct3 <= 3'h0; + robEntries_3_cmd_cmd_rs2 <= 5'h0; + robEntries_3_cmd_cmd_rs1 <= 5'h0; + robEntries_3_cmd_cmd_xd <= 1'h0; + robEntries_3_cmd_cmd_xs1 <= 1'h0; + robEntries_3_cmd_cmd_xs2 <= 1'h0; + robEntries_3_cmd_cmd_rd <= 5'h0; + robEntries_3_cmd_cmd_opcode <= 7'h0; + robEntries_3_cmd_cmd_rs1Data <= 64'h0; + robEntries_3_cmd_cmd_rs2Data <= 64'h0; + robEntries_3_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_3_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_3_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_3_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_3_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_3_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_3_cmd_isFence <= 1'h0; + robEntries_3_cmd_isBarrier <= 1'h0; + robEntries_3_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_3_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_3_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_3_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_3_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_3_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_3_rob_id <= 4'h0; + robEntries_4_cmd_domain_id <= 4'h0; + robEntries_4_cmd_ball_bid <= 5'h0; + robEntries_4_cmd_cmd_raw_inst <= 32'h0; + robEntries_4_cmd_cmd_pc <= 64'h0; + robEntries_4_cmd_cmd_funct <= 7'h0; + robEntries_4_cmd_cmd_funct3 <= 3'h0; + robEntries_4_cmd_cmd_rs2 <= 5'h0; + robEntries_4_cmd_cmd_rs1 <= 5'h0; + robEntries_4_cmd_cmd_xd <= 1'h0; + robEntries_4_cmd_cmd_xs1 <= 1'h0; + robEntries_4_cmd_cmd_xs2 <= 1'h0; + robEntries_4_cmd_cmd_rd <= 5'h0; + robEntries_4_cmd_cmd_opcode <= 7'h0; + robEntries_4_cmd_cmd_rs1Data <= 64'h0; + robEntries_4_cmd_cmd_rs2Data <= 64'h0; + robEntries_4_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_4_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_4_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_4_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_4_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_4_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_4_cmd_isFence <= 1'h0; + robEntries_4_cmd_isBarrier <= 1'h0; + robEntries_4_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_4_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_4_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_4_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_4_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_4_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_4_rob_id <= 4'h0; + robEntries_5_cmd_domain_id <= 4'h0; + robEntries_5_cmd_ball_bid <= 5'h0; + robEntries_5_cmd_cmd_raw_inst <= 32'h0; + robEntries_5_cmd_cmd_pc <= 64'h0; + robEntries_5_cmd_cmd_funct <= 7'h0; + robEntries_5_cmd_cmd_funct3 <= 3'h0; + robEntries_5_cmd_cmd_rs2 <= 5'h0; + robEntries_5_cmd_cmd_rs1 <= 5'h0; + robEntries_5_cmd_cmd_xd <= 1'h0; + robEntries_5_cmd_cmd_xs1 <= 1'h0; + robEntries_5_cmd_cmd_xs2 <= 1'h0; + robEntries_5_cmd_cmd_rd <= 5'h0; + robEntries_5_cmd_cmd_opcode <= 7'h0; + robEntries_5_cmd_cmd_rs1Data <= 64'h0; + robEntries_5_cmd_cmd_rs2Data <= 64'h0; + robEntries_5_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_5_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_5_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_5_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_5_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_5_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_5_cmd_isFence <= 1'h0; + robEntries_5_cmd_isBarrier <= 1'h0; + robEntries_5_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_5_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_5_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_5_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_5_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_5_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_5_rob_id <= 4'h0; + robEntries_6_cmd_domain_id <= 4'h0; + robEntries_6_cmd_ball_bid <= 5'h0; + robEntries_6_cmd_cmd_raw_inst <= 32'h0; + robEntries_6_cmd_cmd_pc <= 64'h0; + robEntries_6_cmd_cmd_funct <= 7'h0; + robEntries_6_cmd_cmd_funct3 <= 3'h0; + robEntries_6_cmd_cmd_rs2 <= 5'h0; + robEntries_6_cmd_cmd_rs1 <= 5'h0; + robEntries_6_cmd_cmd_xd <= 1'h0; + robEntries_6_cmd_cmd_xs1 <= 1'h0; + robEntries_6_cmd_cmd_xs2 <= 1'h0; + robEntries_6_cmd_cmd_rd <= 5'h0; + robEntries_6_cmd_cmd_opcode <= 7'h0; + robEntries_6_cmd_cmd_rs1Data <= 64'h0; + robEntries_6_cmd_cmd_rs2Data <= 64'h0; + robEntries_6_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_6_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_6_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_6_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_6_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_6_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_6_cmd_isFence <= 1'h0; + robEntries_6_cmd_isBarrier <= 1'h0; + robEntries_6_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_6_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_6_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_6_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_6_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_6_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_6_rob_id <= 4'h0; + robEntries_7_cmd_domain_id <= 4'h0; + robEntries_7_cmd_ball_bid <= 5'h0; + robEntries_7_cmd_cmd_raw_inst <= 32'h0; + robEntries_7_cmd_cmd_pc <= 64'h0; + robEntries_7_cmd_cmd_funct <= 7'h0; + robEntries_7_cmd_cmd_funct3 <= 3'h0; + robEntries_7_cmd_cmd_rs2 <= 5'h0; + robEntries_7_cmd_cmd_rs1 <= 5'h0; + robEntries_7_cmd_cmd_xd <= 1'h0; + robEntries_7_cmd_cmd_xs1 <= 1'h0; + robEntries_7_cmd_cmd_xs2 <= 1'h0; + robEntries_7_cmd_cmd_rd <= 5'h0; + robEntries_7_cmd_cmd_opcode <= 7'h0; + robEntries_7_cmd_cmd_rs1Data <= 64'h0; + robEntries_7_cmd_cmd_rs2Data <= 64'h0; + robEntries_7_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_7_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_7_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_7_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_7_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_7_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_7_cmd_isFence <= 1'h0; + robEntries_7_cmd_isBarrier <= 1'h0; + robEntries_7_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_7_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_7_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_7_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_7_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_7_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_7_rob_id <= 4'h0; + robEntries_8_cmd_domain_id <= 4'h0; + robEntries_8_cmd_ball_bid <= 5'h0; + robEntries_8_cmd_cmd_raw_inst <= 32'h0; + robEntries_8_cmd_cmd_pc <= 64'h0; + robEntries_8_cmd_cmd_funct <= 7'h0; + robEntries_8_cmd_cmd_funct3 <= 3'h0; + robEntries_8_cmd_cmd_rs2 <= 5'h0; + robEntries_8_cmd_cmd_rs1 <= 5'h0; + robEntries_8_cmd_cmd_xd <= 1'h0; + robEntries_8_cmd_cmd_xs1 <= 1'h0; + robEntries_8_cmd_cmd_xs2 <= 1'h0; + robEntries_8_cmd_cmd_rd <= 5'h0; + robEntries_8_cmd_cmd_opcode <= 7'h0; + robEntries_8_cmd_cmd_rs1Data <= 64'h0; + robEntries_8_cmd_cmd_rs2Data <= 64'h0; + robEntries_8_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_8_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_8_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_8_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_8_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_8_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_8_cmd_isFence <= 1'h0; + robEntries_8_cmd_isBarrier <= 1'h0; + robEntries_8_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_8_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_8_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_8_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_8_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_8_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_8_rob_id <= 4'h0; + robEntries_9_cmd_domain_id <= 4'h0; + robEntries_9_cmd_ball_bid <= 5'h0; + robEntries_9_cmd_cmd_raw_inst <= 32'h0; + robEntries_9_cmd_cmd_pc <= 64'h0; + robEntries_9_cmd_cmd_funct <= 7'h0; + robEntries_9_cmd_cmd_funct3 <= 3'h0; + robEntries_9_cmd_cmd_rs2 <= 5'h0; + robEntries_9_cmd_cmd_rs1 <= 5'h0; + robEntries_9_cmd_cmd_xd <= 1'h0; + robEntries_9_cmd_cmd_xs1 <= 1'h0; + robEntries_9_cmd_cmd_xs2 <= 1'h0; + robEntries_9_cmd_cmd_rd <= 5'h0; + robEntries_9_cmd_cmd_opcode <= 7'h0; + robEntries_9_cmd_cmd_rs1Data <= 64'h0; + robEntries_9_cmd_cmd_rs2Data <= 64'h0; + robEntries_9_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_9_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_9_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_9_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_9_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_9_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_9_cmd_isFence <= 1'h0; + robEntries_9_cmd_isBarrier <= 1'h0; + robEntries_9_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_9_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_9_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_9_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_9_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_9_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_9_rob_id <= 4'h0; + robEntries_10_cmd_domain_id <= 4'h0; + robEntries_10_cmd_ball_bid <= 5'h0; + robEntries_10_cmd_cmd_raw_inst <= 32'h0; + robEntries_10_cmd_cmd_pc <= 64'h0; + robEntries_10_cmd_cmd_funct <= 7'h0; + robEntries_10_cmd_cmd_funct3 <= 3'h0; + robEntries_10_cmd_cmd_rs2 <= 5'h0; + robEntries_10_cmd_cmd_rs1 <= 5'h0; + robEntries_10_cmd_cmd_xd <= 1'h0; + robEntries_10_cmd_cmd_xs1 <= 1'h0; + robEntries_10_cmd_cmd_xs2 <= 1'h0; + robEntries_10_cmd_cmd_rd <= 5'h0; + robEntries_10_cmd_cmd_opcode <= 7'h0; + robEntries_10_cmd_cmd_rs1Data <= 64'h0; + robEntries_10_cmd_cmd_rs2Data <= 64'h0; + robEntries_10_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_10_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_10_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_10_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_10_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_10_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_10_cmd_isFence <= 1'h0; + robEntries_10_cmd_isBarrier <= 1'h0; + robEntries_10_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_10_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_10_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_10_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_10_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_10_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_10_rob_id <= 4'h0; + robEntries_11_cmd_domain_id <= 4'h0; + robEntries_11_cmd_ball_bid <= 5'h0; + robEntries_11_cmd_cmd_raw_inst <= 32'h0; + robEntries_11_cmd_cmd_pc <= 64'h0; + robEntries_11_cmd_cmd_funct <= 7'h0; + robEntries_11_cmd_cmd_funct3 <= 3'h0; + robEntries_11_cmd_cmd_rs2 <= 5'h0; + robEntries_11_cmd_cmd_rs1 <= 5'h0; + robEntries_11_cmd_cmd_xd <= 1'h0; + robEntries_11_cmd_cmd_xs1 <= 1'h0; + robEntries_11_cmd_cmd_xs2 <= 1'h0; + robEntries_11_cmd_cmd_rd <= 5'h0; + robEntries_11_cmd_cmd_opcode <= 7'h0; + robEntries_11_cmd_cmd_rs1Data <= 64'h0; + robEntries_11_cmd_cmd_rs2Data <= 64'h0; + robEntries_11_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_11_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_11_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_11_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_11_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_11_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_11_cmd_isFence <= 1'h0; + robEntries_11_cmd_isBarrier <= 1'h0; + robEntries_11_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_11_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_11_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_11_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_11_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_11_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_11_rob_id <= 4'h0; + robEntries_12_cmd_domain_id <= 4'h0; + robEntries_12_cmd_ball_bid <= 5'h0; + robEntries_12_cmd_cmd_raw_inst <= 32'h0; + robEntries_12_cmd_cmd_pc <= 64'h0; + robEntries_12_cmd_cmd_funct <= 7'h0; + robEntries_12_cmd_cmd_funct3 <= 3'h0; + robEntries_12_cmd_cmd_rs2 <= 5'h0; + robEntries_12_cmd_cmd_rs1 <= 5'h0; + robEntries_12_cmd_cmd_xd <= 1'h0; + robEntries_12_cmd_cmd_xs1 <= 1'h0; + robEntries_12_cmd_cmd_xs2 <= 1'h0; + robEntries_12_cmd_cmd_rd <= 5'h0; + robEntries_12_cmd_cmd_opcode <= 7'h0; + robEntries_12_cmd_cmd_rs1Data <= 64'h0; + robEntries_12_cmd_cmd_rs2Data <= 64'h0; + robEntries_12_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_12_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_12_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_12_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_12_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_12_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_12_cmd_isFence <= 1'h0; + robEntries_12_cmd_isBarrier <= 1'h0; + robEntries_12_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_12_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_12_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_12_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_12_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_12_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_12_rob_id <= 4'h0; + robEntries_13_cmd_domain_id <= 4'h0; + robEntries_13_cmd_ball_bid <= 5'h0; + robEntries_13_cmd_cmd_raw_inst <= 32'h0; + robEntries_13_cmd_cmd_pc <= 64'h0; + robEntries_13_cmd_cmd_funct <= 7'h0; + robEntries_13_cmd_cmd_funct3 <= 3'h0; + robEntries_13_cmd_cmd_rs2 <= 5'h0; + robEntries_13_cmd_cmd_rs1 <= 5'h0; + robEntries_13_cmd_cmd_xd <= 1'h0; + robEntries_13_cmd_cmd_xs1 <= 1'h0; + robEntries_13_cmd_cmd_xs2 <= 1'h0; + robEntries_13_cmd_cmd_rd <= 5'h0; + robEntries_13_cmd_cmd_opcode <= 7'h0; + robEntries_13_cmd_cmd_rs1Data <= 64'h0; + robEntries_13_cmd_cmd_rs2Data <= 64'h0; + robEntries_13_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_13_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_13_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_13_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_13_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_13_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_13_cmd_isFence <= 1'h0; + robEntries_13_cmd_isBarrier <= 1'h0; + robEntries_13_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_13_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_13_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_13_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_13_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_13_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_13_rob_id <= 4'h0; + robEntries_14_cmd_domain_id <= 4'h0; + robEntries_14_cmd_ball_bid <= 5'h0; + robEntries_14_cmd_cmd_raw_inst <= 32'h0; + robEntries_14_cmd_cmd_pc <= 64'h0; + robEntries_14_cmd_cmd_funct <= 7'h0; + robEntries_14_cmd_cmd_funct3 <= 3'h0; + robEntries_14_cmd_cmd_rs2 <= 5'h0; + robEntries_14_cmd_cmd_rs1 <= 5'h0; + robEntries_14_cmd_cmd_xd <= 1'h0; + robEntries_14_cmd_cmd_xs1 <= 1'h0; + robEntries_14_cmd_cmd_xs2 <= 1'h0; + robEntries_14_cmd_cmd_rd <= 5'h0; + robEntries_14_cmd_cmd_opcode <= 7'h0; + robEntries_14_cmd_cmd_rs1Data <= 64'h0; + robEntries_14_cmd_cmd_rs2Data <= 64'h0; + robEntries_14_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_14_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_14_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_14_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_14_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_14_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_14_cmd_isFence <= 1'h0; + robEntries_14_cmd_isBarrier <= 1'h0; + robEntries_14_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_14_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_14_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_14_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_14_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_14_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_14_rob_id <= 4'h0; + robEntries_15_cmd_domain_id <= 4'h0; + robEntries_15_cmd_ball_bid <= 5'h0; + robEntries_15_cmd_cmd_raw_inst <= 32'h0; + robEntries_15_cmd_cmd_pc <= 64'h0; + robEntries_15_cmd_cmd_funct <= 7'h0; + robEntries_15_cmd_cmd_funct3 <= 3'h0; + robEntries_15_cmd_cmd_rs2 <= 5'h0; + robEntries_15_cmd_cmd_rs1 <= 5'h0; + robEntries_15_cmd_cmd_xd <= 1'h0; + robEntries_15_cmd_cmd_xs1 <= 1'h0; + robEntries_15_cmd_cmd_xs2 <= 1'h0; + robEntries_15_cmd_cmd_rd <= 5'h0; + robEntries_15_cmd_cmd_opcode <= 7'h0; + robEntries_15_cmd_cmd_rs1Data <= 64'h0; + robEntries_15_cmd_cmd_rs2Data <= 64'h0; + robEntries_15_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_15_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_15_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_15_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_15_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_15_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_15_cmd_isFence <= 1'h0; + robEntries_15_cmd_isBarrier <= 1'h0; + robEntries_15_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_15_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_15_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_15_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_15_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_15_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_15_rob_id <= 4'h0; + robValid_0 <= 1'h0; + robValid_1 <= 1'h0; + robValid_2 <= 1'h0; + robValid_3 <= 1'h0; + robValid_4 <= 1'h0; + robValid_5 <= 1'h0; + robValid_6 <= 1'h0; + robValid_7 <= 1'h0; + robValid_8 <= 1'h0; + robValid_9 <= 1'h0; + robValid_10 <= 1'h0; + robValid_11 <= 1'h0; + robValid_12 <= 1'h0; + robValid_13 <= 1'h0; + robValid_14 <= 1'h0; + robValid_15 <= 1'h0; + robIssued_0 <= 1'h0; + robIssued_1 <= 1'h0; + robIssued_2 <= 1'h0; + robIssued_3 <= 1'h0; + robIssued_4 <= 1'h0; + robIssued_5 <= 1'h0; + robIssued_6 <= 1'h0; + robIssued_7 <= 1'h0; + robIssued_8 <= 1'h0; + robIssued_9 <= 1'h0; + robIssued_10 <= 1'h0; + robIssued_11 <= 1'h0; + robIssued_12 <= 1'h0; + robIssued_13 <= 1'h0; + robIssued_14 <= 1'h0; + robIssued_15 <= 1'h0; + robComplete_0 <= 1'h0; + robComplete_1 <= 1'h0; + robComplete_2 <= 1'h0; + robComplete_3 <= 1'h0; + robComplete_4 <= 1'h0; + robComplete_5 <= 1'h0; + robComplete_6 <= 1'h0; + robComplete_7 <= 1'h0; + robComplete_8 <= 1'h0; + robComplete_9 <= 1'h0; + robComplete_10 <= 1'h0; + robComplete_11 <= 1'h0; + robComplete_12 <= 1'h0; + robComplete_13 <= 1'h0; + robComplete_14 <= 1'h0; + robComplete_15 <= 1'h0; + instIds_0 <= 64'h0; + instIds_1 <= 64'h0; + instIds_2 <= 64'h0; + instIds_3 <= 64'h0; + instIds_4 <= 64'h0; + instIds_5 <= 64'h0; + instIds_6 <= 64'h0; + instIds_7 <= 64'h0; + instIds_8 <= 64'h0; + instIds_9 <= 64'h0; + instIds_10 <= 64'h0; + instIds_11 <= 64'h0; + instIds_12 <= 64'h0; + instIds_13 <= 64'h0; + instIds_14 <= 64'h0; + instIds_15 <= 64'h0; + nextInstId <= 64'h1; + ptr <= 4'h0; + tailPtr <= 4'h0; + issuedCount <= 5'h0; + bankCols_0 <= 4'h0; + bankCols_1 <= 4'h0; + bankCols_2 <= 4'h0; + bankCols_3 <= 4'h0; + bankCols_4 <= 4'h0; + bankCols_5 <= 4'h0; + bankCols_6 <= 4'h0; + bankCols_7 <= 4'h0; + bankCols_8 <= 4'h0; + bankCols_9 <= 4'h0; + bankCols_10 <= 4'h0; + bankCols_11 <= 4'h0; + bankCols_12 <= 4'h0; + bankCols_13 <= 4'h0; + bankCols_14 <= 4'h0; + bankCols_15 <= 4'h0; + vbankBusy <= 16'h0; + dependencyMask_0 <= 16'h0; + dependencyMask_1 <= 16'h0; + dependencyMask_2 <= 16'h0; + dependencyMask_3 <= 16'h0; + dependencyMask_4 <= 16'h0; + dependencyMask_5 <= 16'h0; + dependencyMask_6 <= 16'h0; + dependencyMask_7 <= 16'h0; + dependencyMask_8 <= 16'h0; + dependencyMask_9 <= 16'h0; + dependencyMask_10 <= 16'h0; + dependencyMask_11 <= 16'h0; + dependencyMask_12 <= 16'h0; + dependencyMask_13 <= 16'h0; + dependencyMask_14 <= 16'h0; + dependencyMask_15 <= 16'h0; + issueStageValid <= 1'h0; + issuePtrValid <= 1'h0; + end + else begin + automatic logic _entryIsConfig_0_T = robEntries_0_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_0 = + _entryIsConfig_0_T & robEntries_0_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_1_T = robEntries_1_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_1 = + _entryIsConfig_1_T & robEntries_1_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_2_T = robEntries_2_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_2 = + _entryIsConfig_2_T & robEntries_2_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_3_T = robEntries_3_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_3 = + _entryIsConfig_3_T & robEntries_3_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_4_T = robEntries_4_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_4 = + _entryIsConfig_4_T & robEntries_4_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_5_T = robEntries_5_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_5 = + _entryIsConfig_5_T & robEntries_5_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_6_T = robEntries_6_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_6 = + _entryIsConfig_6_T & robEntries_6_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_7_T = robEntries_7_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_7 = + _entryIsConfig_7_T & robEntries_7_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_8_T = robEntries_8_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_8 = + _entryIsConfig_8_T & robEntries_8_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_9_T = robEntries_9_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_9 = + _entryIsConfig_9_T & robEntries_9_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_10_T = robEntries_10_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_10 = + _entryIsConfig_10_T & robEntries_10_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_11_T = robEntries_11_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_11 = + _entryIsConfig_11_T & robEntries_11_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_12_T = robEntries_12_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_12 = + _entryIsConfig_12_T & robEntries_12_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_13_T = robEntries_13_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_13 = + _entryIsConfig_13_T & robEntries_13_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_14_T = robEntries_14_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_14 = + _entryIsConfig_14_T & robEntries_14_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_15_T = robEntries_15_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_15 = + _entryIsConfig_15_T & robEntries_15_cmd_cmd_funct == 7'h20; + automatic logic [15:0] allocReadMask = + (io_alloc_bits_bankAccess_rd_bank_0_valid + & io_alloc_bits_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << io_alloc_bits_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (io_alloc_bits_bankAccess_rd_bank_1_valid + & io_alloc_bits_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << io_alloc_bits_bankAccess_rd_bank_1_id[3:0] + : 16'h0); + automatic logic [15:0] allocWriteMask = + io_alloc_bits_bankAccess_wr_bank_valid + & io_alloc_bits_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << io_alloc_bits_bankAccess_wr_bank_id[3:0] + : 16'h0; + automatic logic allocIsConfig = + io_alloc_bits_domain_id == 4'h1 & io_alloc_bits_cmd_funct == 7'h20; + automatic logic allocIsBall = io_alloc_bits_domain_id == 4'h3; + automatic logic [15:0] _configConflict_T_92 = allocReadMask | allocWriteMask; + automatic logic [15:0] allocDependencies; + automatic logic [63:0] _instIds_T; + automatic logic _GEN_20 = _isAllocatedSlot_T_30 & ~(|tailPtr); + automatic logic _GEN_21 = _isAllocatedSlot_T_30 & tailPtr == 4'h1; + automatic logic _GEN_22 = _isAllocatedSlot_T_30 & tailPtr == 4'h2; + automatic logic _GEN_23 = _isAllocatedSlot_T_30 & tailPtr == 4'h3; + automatic logic _GEN_24 = _isAllocatedSlot_T_30 & tailPtr == 4'h4; + automatic logic _GEN_25 = _isAllocatedSlot_T_30 & tailPtr == 4'h5; + automatic logic _GEN_26 = _isAllocatedSlot_T_30 & tailPtr == 4'h6; + automatic logic _GEN_27 = _isAllocatedSlot_T_30 & tailPtr == 4'h7; + automatic logic _GEN_28 = _isAllocatedSlot_T_30 & tailPtr == 4'h8; + automatic logic _GEN_29 = _isAllocatedSlot_T_30 & tailPtr == 4'h9; + automatic logic _GEN_30 = _isAllocatedSlot_T_30 & tailPtr == 4'hA; + automatic logic _GEN_31 = _isAllocatedSlot_T_30 & tailPtr == 4'hB; + automatic logic _GEN_32 = _isAllocatedSlot_T_30 & tailPtr == 4'hC; + automatic logic _GEN_33 = _isAllocatedSlot_T_30 & tailPtr == 4'hD; + automatic logic _GEN_34 = _isAllocatedSlot_T_30 & tailPtr == 4'hE; + automatic logic _GEN_35 = _isAllocatedSlot_T_30 & (&tailPtr); + automatic logic [15:0] completedBitMask = + io_complete_valid ? 16'h1 << io_complete_bits : 16'h0; + automatic logic [3:0] _GEN_36; + automatic logic _GEN_37; + automatic logic [3:0] _GEN_38; + automatic logic _GEN_39; + automatic logic [3:0] _GEN_40; + automatic logic _GEN_41; + automatic logic [3:0] _GEN_42; + automatic logic _GEN_43; + automatic logic [3:0] _GEN_44; + automatic logic _GEN_45; + automatic logic [3:0] _GEN_46; + automatic logic _GEN_47; + automatic logic [3:0] _GEN_48; + automatic logic _GEN_49; + automatic logic [3:0] _GEN_50; + automatic logic _GEN_51; + automatic logic [3:0] _GEN_52; + automatic logic _GEN_53; + automatic logic [3:0] _GEN_54; + automatic logic _GEN_55; + automatic logic [3:0] _GEN_56; + automatic logic _GEN_57; + automatic logic [3:0] _GEN_58; + automatic logic _GEN_59; + automatic logic [3:0] _GEN_60; + automatic logic _GEN_61; + automatic logic [3:0] _GEN_62; + automatic logic _GEN_63; + automatic logic [3:0] _GEN_64; + automatic logic _GEN_65; + automatic logic [3:0] _GEN_66; + automatic logic _GEN_67 = + commitMask_15 & _entryIsConfig_15_T & robEntries_15_cmd_cmd_funct == 7'h20; + automatic logic [15:0] configEntryMask = + {entryIsConfig_15, + entryIsConfig_14, + entryIsConfig_13, + entryIsConfig_12, + entryIsConfig_11, + entryIsConfig_10, + entryIsConfig_9, + entryIsConfig_8, + entryIsConfig_7, + entryIsConfig_6, + entryIsConfig_5, + entryIsConfig_4, + entryIsConfig_3, + entryIsConfig_2, + entryIsConfig_1, + entryIsConfig_0}; + automatic logic isAllocatedSlot = _isAllocatedSlot_T_30 & ~(|tailPtr); + automatic logic [15:0] clearMask; + automatic logic isAllocatedSlot_1 = _isAllocatedSlot_T_30 & tailPtr == 4'h1; + automatic logic [15:0] clearMask_1; + automatic logic isAllocatedSlot_2 = _isAllocatedSlot_T_30 & tailPtr == 4'h2; + automatic logic [15:0] clearMask_2; + automatic logic isAllocatedSlot_3 = _isAllocatedSlot_T_30 & tailPtr == 4'h3; + automatic logic [15:0] clearMask_3; + automatic logic isAllocatedSlot_4 = _isAllocatedSlot_T_30 & tailPtr == 4'h4; + automatic logic [15:0] clearMask_4; + automatic logic isAllocatedSlot_5 = _isAllocatedSlot_T_30 & tailPtr == 4'h5; + automatic logic [15:0] clearMask_5; + automatic logic isAllocatedSlot_6 = _isAllocatedSlot_T_30 & tailPtr == 4'h6; + automatic logic [15:0] clearMask_6; + automatic logic isAllocatedSlot_7 = _isAllocatedSlot_T_30 & tailPtr == 4'h7; + automatic logic [15:0] clearMask_7; + automatic logic isAllocatedSlot_8 = _isAllocatedSlot_T_30 & tailPtr == 4'h8; + automatic logic [15:0] clearMask_8; + automatic logic isAllocatedSlot_9 = _isAllocatedSlot_T_30 & tailPtr == 4'h9; + automatic logic [15:0] clearMask_9; + automatic logic isAllocatedSlot_10 = _isAllocatedSlot_T_30 & tailPtr == 4'hA; + automatic logic [15:0] clearMask_10; + automatic logic isAllocatedSlot_11 = _isAllocatedSlot_T_30 & tailPtr == 4'hB; + automatic logic [15:0] clearMask_11; + automatic logic isAllocatedSlot_12 = _isAllocatedSlot_T_30 & tailPtr == 4'hC; + automatic logic [15:0] clearMask_12; + automatic logic isAllocatedSlot_13 = _isAllocatedSlot_T_30 & tailPtr == 4'hD; + automatic logic [15:0] clearMask_13; + automatic logic isAllocatedSlot_14 = _isAllocatedSlot_T_30 & tailPtr == 4'hE; + automatic logic [15:0] clearMask_14; + automatic logic isAllocatedSlot_15 = _isAllocatedSlot_T_30 & (&tailPtr); + automatic logic [15:0] clearMask_15; + allocDependencies = + {robValid_15 & ~robComplete_15 + & ((|(allocReadMask & entryRawWrites_15 | allocWriteMask & vbankMasks_15)) + | allocIsBall & robEntries_15_cmd_domain_id == 4'h3 + & robEntries_15_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_15 + & (allocIsConfig & entryIsConfig_15 | (allocIsConfig | entryIsConfig_15) + & (|(_configConflict_T_92 & vbankMasks_15))), + robValid_14 & ~robComplete_14 + & ((|(allocReadMask & entryRawWrites_14 | allocWriteMask & vbankMasks_14)) + | allocIsBall & robEntries_14_cmd_domain_id == 4'h3 + & robEntries_14_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_14 + & (allocIsConfig & entryIsConfig_14 | (allocIsConfig | entryIsConfig_14) + & (|(_configConflict_T_92 & vbankMasks_14))), + robValid_13 & ~robComplete_13 + & ((|(allocReadMask & entryRawWrites_13 | allocWriteMask & vbankMasks_13)) + | allocIsBall & robEntries_13_cmd_domain_id == 4'h3 + & robEntries_13_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_13 + & (allocIsConfig & entryIsConfig_13 | (allocIsConfig | entryIsConfig_13) + & (|(_configConflict_T_92 & vbankMasks_13))), + robValid_12 & ~robComplete_12 + & ((|(allocReadMask & entryRawWrites_12 | allocWriteMask & vbankMasks_12)) + | allocIsBall & robEntries_12_cmd_domain_id == 4'h3 + & robEntries_12_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_12 + & (allocIsConfig & entryIsConfig_12 | (allocIsConfig | entryIsConfig_12) + & (|(_configConflict_T_92 & vbankMasks_12))), + robValid_11 & ~robComplete_11 + & ((|(allocReadMask & entryRawWrites_11 | allocWriteMask & vbankMasks_11)) + | allocIsBall & robEntries_11_cmd_domain_id == 4'h3 + & robEntries_11_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_11 + & (allocIsConfig & entryIsConfig_11 | (allocIsConfig | entryIsConfig_11) + & (|(_configConflict_T_92 & vbankMasks_11))), + robValid_10 & ~robComplete_10 + & ((|(allocReadMask & entryRawWrites_10 | allocWriteMask & vbankMasks_10)) + | allocIsBall & robEntries_10_cmd_domain_id == 4'h3 + & robEntries_10_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_10 + & (allocIsConfig & entryIsConfig_10 | (allocIsConfig | entryIsConfig_10) + & (|(_configConflict_T_92 & vbankMasks_10))), + robValid_9 & ~robComplete_9 + & ((|(allocReadMask & entryRawWrites_9 | allocWriteMask & vbankMasks_9)) + | allocIsBall & robEntries_9_cmd_domain_id == 4'h3 + & robEntries_9_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_9 + & (allocIsConfig & entryIsConfig_9 | (allocIsConfig | entryIsConfig_9) + & (|(_configConflict_T_92 & vbankMasks_9))), + robValid_8 & ~robComplete_8 + & ((|(allocReadMask & entryRawWrites_8 | allocWriteMask & vbankMasks_8)) + | allocIsBall & robEntries_8_cmd_domain_id == 4'h3 + & robEntries_8_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_8 + & (allocIsConfig & entryIsConfig_8 | (allocIsConfig | entryIsConfig_8) + & (|(_configConflict_T_92 & vbankMasks_8))), + robValid_7 & ~robComplete_7 + & ((|(allocReadMask & entryRawWrites_7 | allocWriteMask & vbankMasks_7)) + | allocIsBall & robEntries_7_cmd_domain_id == 4'h3 + & robEntries_7_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_7 + & (allocIsConfig & entryIsConfig_7 | (allocIsConfig | entryIsConfig_7) + & (|(_configConflict_T_92 & vbankMasks_7))), + robValid_6 & ~robComplete_6 + & ((|(allocReadMask & entryRawWrites_6 | allocWriteMask & vbankMasks_6)) + | allocIsBall & robEntries_6_cmd_domain_id == 4'h3 + & robEntries_6_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_6 + & (allocIsConfig & entryIsConfig_6 | (allocIsConfig | entryIsConfig_6) + & (|(_configConflict_T_92 & vbankMasks_6))), + robValid_5 & ~robComplete_5 + & ((|(allocReadMask & entryRawWrites_5 | allocWriteMask & vbankMasks_5)) + | allocIsBall & robEntries_5_cmd_domain_id == 4'h3 + & robEntries_5_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_5 + & (allocIsConfig & entryIsConfig_5 | (allocIsConfig | entryIsConfig_5) + & (|(_configConflict_T_92 & vbankMasks_5))), + robValid_4 & ~robComplete_4 + & ((|(allocReadMask & entryRawWrites_4 | allocWriteMask & vbankMasks_4)) + | allocIsBall & robEntries_4_cmd_domain_id == 4'h3 + & robEntries_4_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_4 + & (allocIsConfig & entryIsConfig_4 | (allocIsConfig | entryIsConfig_4) + & (|(_configConflict_T_92 & vbankMasks_4))), + robValid_3 & ~robComplete_3 + & ((|(allocReadMask & entryRawWrites_3 | allocWriteMask & vbankMasks_3)) + | allocIsBall & robEntries_3_cmd_domain_id == 4'h3 + & robEntries_3_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_3 + & (allocIsConfig & entryIsConfig_3 | (allocIsConfig | entryIsConfig_3) + & (|(_configConflict_T_92 & vbankMasks_3))), + robValid_2 & ~robComplete_2 + & ((|(allocReadMask & entryRawWrites_2 | allocWriteMask & vbankMasks_2)) + | allocIsBall & robEntries_2_cmd_domain_id == 4'h3 + & robEntries_2_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_2 + & (allocIsConfig & entryIsConfig_2 | (allocIsConfig | entryIsConfig_2) + & (|(_configConflict_T_92 & vbankMasks_2))), + robValid_1 & ~robComplete_1 + & ((|(allocReadMask & entryRawWrites_1 | allocWriteMask & vbankMasks_1)) + | allocIsBall & robEntries_1_cmd_domain_id == 4'h3 + & robEntries_1_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_1 + & (allocIsConfig & entryIsConfig_1 | (allocIsConfig | entryIsConfig_1) + & (|(_configConflict_T_92 & vbankMasks_1))), + robValid_0 & ~robComplete_0 + & ((|(allocReadMask & entryRawWrites_0 | allocWriteMask & olderUseMask)) + | allocIsBall & robEntries_0_cmd_domain_id == 4'h3 + & robEntries_0_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_0 + & (allocIsConfig & entryIsConfig_0 | (allocIsConfig | entryIsConfig_0) + & (|(_configConflict_T_92 & olderUseMask)))}; + _instIds_T = (|io_alloc_bits_cmd_pc) ? nextInstId : 64'h0; + _GEN_36 = + robEntries_0_cmd_cmd_rs2Data[10] + ? (robEntries_0_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_0_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_37 = commitMask_0 & _entryIsConfig_0_T & robEntries_0_cmd_cmd_funct == 7'h20; + _GEN_38 = + robEntries_1_cmd_cmd_rs2Data[10] + ? (robEntries_1_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_1_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_39 = commitMask_1 & _entryIsConfig_1_T & robEntries_1_cmd_cmd_funct == 7'h20; + _GEN_40 = + robEntries_2_cmd_cmd_rs2Data[10] + ? (robEntries_2_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_2_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_41 = commitMask_2 & _entryIsConfig_2_T & robEntries_2_cmd_cmd_funct == 7'h20; + _GEN_42 = + robEntries_3_cmd_cmd_rs2Data[10] + ? (robEntries_3_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_3_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_43 = commitMask_3 & _entryIsConfig_3_T & robEntries_3_cmd_cmd_funct == 7'h20; + _GEN_44 = + robEntries_4_cmd_cmd_rs2Data[10] + ? (robEntries_4_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_4_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_45 = commitMask_4 & _entryIsConfig_4_T & robEntries_4_cmd_cmd_funct == 7'h20; + _GEN_46 = + robEntries_5_cmd_cmd_rs2Data[10] + ? (robEntries_5_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_5_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_47 = commitMask_5 & _entryIsConfig_5_T & robEntries_5_cmd_cmd_funct == 7'h20; + _GEN_48 = + robEntries_6_cmd_cmd_rs2Data[10] + ? (robEntries_6_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_6_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_49 = commitMask_6 & _entryIsConfig_6_T & robEntries_6_cmd_cmd_funct == 7'h20; + _GEN_50 = + robEntries_7_cmd_cmd_rs2Data[10] + ? (robEntries_7_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_7_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_51 = commitMask_7 & _entryIsConfig_7_T & robEntries_7_cmd_cmd_funct == 7'h20; + _GEN_52 = + robEntries_8_cmd_cmd_rs2Data[10] + ? (robEntries_8_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_8_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_53 = commitMask_8 & _entryIsConfig_8_T & robEntries_8_cmd_cmd_funct == 7'h20; + _GEN_54 = + robEntries_9_cmd_cmd_rs2Data[10] + ? (robEntries_9_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_9_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_55 = commitMask_9 & _entryIsConfig_9_T & robEntries_9_cmd_cmd_funct == 7'h20; + _GEN_56 = + robEntries_10_cmd_cmd_rs2Data[10] + ? (robEntries_10_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_10_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_57 = + commitMask_10 & _entryIsConfig_10_T & robEntries_10_cmd_cmd_funct == 7'h20; + _GEN_58 = + robEntries_11_cmd_cmd_rs2Data[10] + ? (robEntries_11_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_11_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_59 = + commitMask_11 & _entryIsConfig_11_T & robEntries_11_cmd_cmd_funct == 7'h20; + _GEN_60 = + robEntries_12_cmd_cmd_rs2Data[10] + ? (robEntries_12_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_12_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_61 = + commitMask_12 & _entryIsConfig_12_T & robEntries_12_cmd_cmd_funct == 7'h20; + _GEN_62 = + robEntries_13_cmd_cmd_rs2Data[10] + ? (robEntries_13_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_13_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_63 = + commitMask_13 & _entryIsConfig_13_T & robEntries_13_cmd_cmd_funct == 7'h20; + _GEN_64 = + robEntries_14_cmd_cmd_rs2Data[10] + ? (robEntries_14_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_14_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_65 = + commitMask_14 & _entryIsConfig_14_T & robEntries_14_cmd_cmd_funct == 7'h20; + _GEN_66 = + robEntries_15_cmd_cmd_rs2Data[10] + ? (robEntries_15_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_15_cmd_cmd_rs2Data[8:5]) + : 4'h0; + clearMask = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask | {16{isAllocatedSlot ? allocIsConfig : entryIsConfig_0}}); + clearMask_1 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask | {16{isAllocatedSlot_1 ? allocIsConfig : entryIsConfig_1}}); + clearMask_2 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask | {16{isAllocatedSlot_2 ? allocIsConfig : entryIsConfig_2}}); + clearMask_3 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask | {16{isAllocatedSlot_3 ? allocIsConfig : entryIsConfig_3}}); + clearMask_4 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask | {16{isAllocatedSlot_4 ? allocIsConfig : entryIsConfig_4}}); + clearMask_5 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask | {16{isAllocatedSlot_5 ? allocIsConfig : entryIsConfig_5}}); + clearMask_6 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask | {16{isAllocatedSlot_6 ? allocIsConfig : entryIsConfig_6}}); + clearMask_7 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask | {16{isAllocatedSlot_7 ? allocIsConfig : entryIsConfig_7}}); + clearMask_8 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask | {16{isAllocatedSlot_8 ? allocIsConfig : entryIsConfig_8}}); + clearMask_9 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask | {16{isAllocatedSlot_9 ? allocIsConfig : entryIsConfig_9}}); + clearMask_10 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask + | {16{isAllocatedSlot_10 ? allocIsConfig : entryIsConfig_10}}); + clearMask_11 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask + | {16{isAllocatedSlot_11 ? allocIsConfig : entryIsConfig_11}}); + clearMask_12 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask + | {16{isAllocatedSlot_12 ? allocIsConfig : entryIsConfig_12}}); + clearMask_13 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask + | {16{isAllocatedSlot_13 ? allocIsConfig : entryIsConfig_13}}); + clearMask_14 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask + | {16{isAllocatedSlot_14 ? allocIsConfig : entryIsConfig_14}}); + clearMask_15 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask + | {16{isAllocatedSlot_15 ? allocIsConfig : entryIsConfig_15}}); + if (_GEN_20) begin + robEntries_0_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_0_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_0_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_0_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_0_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_0_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_0_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_0_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_0_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_0_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_0_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_0_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_0_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_0_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_0_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_0_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_0_cmd_bankAccess_rd_bank_0_id <= io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_0_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_0_cmd_bankAccess_rd_bank_1_id <= io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_0_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_0_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_0_cmd_isFence <= io_alloc_bits_isFence; + robEntries_0_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_0_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_0_renamedBankAccess_rd_bank_0_id <= _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_0_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_0_renamedBankAccess_rd_bank_1_id <= _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_0_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_0_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_0_rob_id <= tailPtr; + instIds_0 <= _instIds_T; + end + if (_GEN_21) begin + robEntries_1_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_1_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_1_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_1_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_1_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_1_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_1_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_1_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_1_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_1_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_1_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_1_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_1_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_1_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_1_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_1_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_1_cmd_bankAccess_rd_bank_0_id <= io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_1_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_1_cmd_bankAccess_rd_bank_1_id <= io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_1_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_1_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_1_cmd_isFence <= io_alloc_bits_isFence; + robEntries_1_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_1_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_1_renamedBankAccess_rd_bank_0_id <= _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_1_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_1_renamedBankAccess_rd_bank_1_id <= _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_1_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_1_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_1_rob_id <= tailPtr; + instIds_1 <= _instIds_T; + end + if (_GEN_22) begin + robEntries_2_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_2_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_2_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_2_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_2_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_2_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_2_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_2_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_2_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_2_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_2_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_2_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_2_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_2_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_2_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_2_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_2_cmd_bankAccess_rd_bank_0_id <= io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_2_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_2_cmd_bankAccess_rd_bank_1_id <= io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_2_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_2_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_2_cmd_isFence <= io_alloc_bits_isFence; + robEntries_2_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_2_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_2_renamedBankAccess_rd_bank_0_id <= _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_2_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_2_renamedBankAccess_rd_bank_1_id <= _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_2_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_2_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_2_rob_id <= tailPtr; + instIds_2 <= _instIds_T; + end + if (_GEN_23) begin + robEntries_3_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_3_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_3_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_3_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_3_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_3_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_3_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_3_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_3_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_3_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_3_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_3_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_3_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_3_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_3_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_3_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_3_cmd_bankAccess_rd_bank_0_id <= io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_3_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_3_cmd_bankAccess_rd_bank_1_id <= io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_3_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_3_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_3_cmd_isFence <= io_alloc_bits_isFence; + robEntries_3_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_3_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_3_renamedBankAccess_rd_bank_0_id <= _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_3_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_3_renamedBankAccess_rd_bank_1_id <= _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_3_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_3_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_3_rob_id <= tailPtr; + instIds_3 <= _instIds_T; + end + if (_GEN_24) begin + robEntries_4_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_4_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_4_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_4_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_4_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_4_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_4_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_4_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_4_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_4_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_4_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_4_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_4_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_4_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_4_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_4_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_4_cmd_bankAccess_rd_bank_0_id <= io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_4_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_4_cmd_bankAccess_rd_bank_1_id <= io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_4_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_4_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_4_cmd_isFence <= io_alloc_bits_isFence; + robEntries_4_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_4_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_4_renamedBankAccess_rd_bank_0_id <= _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_4_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_4_renamedBankAccess_rd_bank_1_id <= _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_4_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_4_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_4_rob_id <= tailPtr; + instIds_4 <= _instIds_T; + end + if (_GEN_25) begin + robEntries_5_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_5_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_5_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_5_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_5_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_5_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_5_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_5_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_5_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_5_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_5_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_5_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_5_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_5_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_5_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_5_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_5_cmd_bankAccess_rd_bank_0_id <= io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_5_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_5_cmd_bankAccess_rd_bank_1_id <= io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_5_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_5_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_5_cmd_isFence <= io_alloc_bits_isFence; + robEntries_5_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_5_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_5_renamedBankAccess_rd_bank_0_id <= _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_5_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_5_renamedBankAccess_rd_bank_1_id <= _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_5_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_5_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_5_rob_id <= tailPtr; + instIds_5 <= _instIds_T; + end + if (_GEN_26) begin + robEntries_6_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_6_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_6_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_6_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_6_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_6_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_6_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_6_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_6_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_6_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_6_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_6_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_6_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_6_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_6_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_6_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_6_cmd_bankAccess_rd_bank_0_id <= io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_6_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_6_cmd_bankAccess_rd_bank_1_id <= io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_6_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_6_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_6_cmd_isFence <= io_alloc_bits_isFence; + robEntries_6_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_6_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_6_renamedBankAccess_rd_bank_0_id <= _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_6_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_6_renamedBankAccess_rd_bank_1_id <= _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_6_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_6_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_6_rob_id <= tailPtr; + instIds_6 <= _instIds_T; + end + if (_GEN_27) begin + robEntries_7_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_7_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_7_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_7_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_7_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_7_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_7_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_7_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_7_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_7_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_7_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_7_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_7_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_7_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_7_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_7_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_7_cmd_bankAccess_rd_bank_0_id <= io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_7_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_7_cmd_bankAccess_rd_bank_1_id <= io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_7_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_7_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_7_cmd_isFence <= io_alloc_bits_isFence; + robEntries_7_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_7_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_7_renamedBankAccess_rd_bank_0_id <= _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_7_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_7_renamedBankAccess_rd_bank_1_id <= _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_7_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_7_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_7_rob_id <= tailPtr; + instIds_7 <= _instIds_T; + end + if (_GEN_28) begin + robEntries_8_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_8_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_8_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_8_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_8_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_8_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_8_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_8_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_8_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_8_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_8_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_8_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_8_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_8_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_8_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_8_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_8_cmd_bankAccess_rd_bank_0_id <= io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_8_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_8_cmd_bankAccess_rd_bank_1_id <= io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_8_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_8_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_8_cmd_isFence <= io_alloc_bits_isFence; + robEntries_8_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_8_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_8_renamedBankAccess_rd_bank_0_id <= _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_8_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_8_renamedBankAccess_rd_bank_1_id <= _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_8_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_8_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_8_rob_id <= tailPtr; + instIds_8 <= _instIds_T; + end + if (_GEN_29) begin + robEntries_9_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_9_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_9_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_9_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_9_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_9_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_9_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_9_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_9_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_9_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_9_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_9_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_9_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_9_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_9_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_9_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_9_cmd_bankAccess_rd_bank_0_id <= io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_9_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_9_cmd_bankAccess_rd_bank_1_id <= io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_9_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_9_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_9_cmd_isFence <= io_alloc_bits_isFence; + robEntries_9_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_9_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_9_renamedBankAccess_rd_bank_0_id <= _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_9_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_9_renamedBankAccess_rd_bank_1_id <= _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_9_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_9_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_9_rob_id <= tailPtr; + instIds_9 <= _instIds_T; + end + if (_GEN_30) begin + robEntries_10_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_10_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_10_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_10_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_10_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_10_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_10_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_10_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_10_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_10_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_10_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_10_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_10_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_10_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_10_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_10_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_10_cmd_bankAccess_rd_bank_0_id <= + io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_10_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_10_cmd_bankAccess_rd_bank_1_id <= + io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_10_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_10_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_10_cmd_isFence <= io_alloc_bits_isFence; + robEntries_10_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_10_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_10_renamedBankAccess_rd_bank_0_id <= + _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_10_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_10_renamedBankAccess_rd_bank_1_id <= + _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_10_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_10_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_10_rob_id <= tailPtr; + instIds_10 <= _instIds_T; + end + if (_GEN_31) begin + robEntries_11_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_11_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_11_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_11_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_11_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_11_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_11_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_11_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_11_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_11_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_11_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_11_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_11_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_11_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_11_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_11_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_11_cmd_bankAccess_rd_bank_0_id <= + io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_11_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_11_cmd_bankAccess_rd_bank_1_id <= + io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_11_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_11_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_11_cmd_isFence <= io_alloc_bits_isFence; + robEntries_11_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_11_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_11_renamedBankAccess_rd_bank_0_id <= + _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_11_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_11_renamedBankAccess_rd_bank_1_id <= + _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_11_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_11_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_11_rob_id <= tailPtr; + instIds_11 <= _instIds_T; + end + if (_GEN_32) begin + robEntries_12_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_12_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_12_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_12_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_12_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_12_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_12_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_12_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_12_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_12_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_12_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_12_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_12_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_12_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_12_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_12_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_12_cmd_bankAccess_rd_bank_0_id <= + io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_12_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_12_cmd_bankAccess_rd_bank_1_id <= + io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_12_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_12_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_12_cmd_isFence <= io_alloc_bits_isFence; + robEntries_12_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_12_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_12_renamedBankAccess_rd_bank_0_id <= + _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_12_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_12_renamedBankAccess_rd_bank_1_id <= + _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_12_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_12_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_12_rob_id <= tailPtr; + instIds_12 <= _instIds_T; + end + if (_GEN_33) begin + robEntries_13_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_13_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_13_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_13_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_13_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_13_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_13_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_13_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_13_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_13_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_13_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_13_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_13_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_13_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_13_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_13_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_13_cmd_bankAccess_rd_bank_0_id <= + io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_13_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_13_cmd_bankAccess_rd_bank_1_id <= + io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_13_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_13_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_13_cmd_isFence <= io_alloc_bits_isFence; + robEntries_13_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_13_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_13_renamedBankAccess_rd_bank_0_id <= + _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_13_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_13_renamedBankAccess_rd_bank_1_id <= + _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_13_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_13_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_13_rob_id <= tailPtr; + instIds_13 <= _instIds_T; + end + if (_GEN_34) begin + robEntries_14_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_14_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_14_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_14_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_14_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_14_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_14_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_14_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_14_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_14_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_14_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_14_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_14_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_14_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_14_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_14_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_14_cmd_bankAccess_rd_bank_0_id <= + io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_14_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_14_cmd_bankAccess_rd_bank_1_id <= + io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_14_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_14_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_14_cmd_isFence <= io_alloc_bits_isFence; + robEntries_14_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_14_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_14_renamedBankAccess_rd_bank_0_id <= + _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_14_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_14_renamedBankAccess_rd_bank_1_id <= + _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_14_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_14_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_14_rob_id <= tailPtr; + instIds_14 <= _instIds_T; + end + if (_GEN_35) begin + robEntries_15_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_15_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_15_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_15_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_15_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_15_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_15_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_15_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_15_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_15_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_15_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_15_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_15_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_15_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_15_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_15_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_15_cmd_bankAccess_rd_bank_0_id <= + io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_15_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_15_cmd_bankAccess_rd_bank_1_id <= + io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_15_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_15_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_15_cmd_isFence <= io_alloc_bits_isFence; + robEntries_15_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_15_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_15_renamedBankAccess_rd_bank_0_id <= + _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_15_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_15_renamedBankAccess_rd_bank_1_id <= + _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_15_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_15_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_15_rob_id <= tailPtr; + instIds_15 <= _instIds_T; + end + robValid_0 <= ~commitMask_0 & (_GEN_20 | robValid_0); + robValid_1 <= ~commitMask_1 & (_GEN_21 | robValid_1); + robValid_2 <= ~commitMask_2 & (_GEN_22 | robValid_2); + robValid_3 <= ~commitMask_3 & (_GEN_23 | robValid_3); + robValid_4 <= ~commitMask_4 & (_GEN_24 | robValid_4); + robValid_5 <= ~commitMask_5 & (_GEN_25 | robValid_5); + robValid_6 <= ~commitMask_6 & (_GEN_26 | robValid_6); + robValid_7 <= ~commitMask_7 & (_GEN_27 | robValid_7); + robValid_8 <= ~commitMask_8 & (_GEN_28 | robValid_8); + robValid_9 <= ~commitMask_9 & (_GEN_29 | robValid_9); + robValid_10 <= ~commitMask_10 & (_GEN_30 | robValid_10); + robValid_11 <= ~commitMask_11 & (_GEN_31 | robValid_11); + robValid_12 <= ~commitMask_12 & (_GEN_32 | robValid_12); + robValid_13 <= ~commitMask_13 & (_GEN_33 | robValid_13); + robValid_14 <= ~commitMask_14 & (_GEN_34 | robValid_14); + robValid_15 <= ~commitMask_15 & (_GEN_35 | robValid_15); + robIssued_0 <= + ~commitMask_0 & (issueLoad & _actualIssuePtr_T == 4'h0 | ~_GEN_20 & robIssued_0); + robIssued_1 <= + ~commitMask_1 & (issueLoad & _actualIssuePtr_T == 4'h1 | ~_GEN_21 & robIssued_1); + robIssued_2 <= + ~commitMask_2 & (issueLoad & _actualIssuePtr_T == 4'h2 | ~_GEN_22 & robIssued_2); + robIssued_3 <= + ~commitMask_3 & (issueLoad & _actualIssuePtr_T == 4'h3 | ~_GEN_23 & robIssued_3); + robIssued_4 <= + ~commitMask_4 & (issueLoad & _actualIssuePtr_T == 4'h4 | ~_GEN_24 & robIssued_4); + robIssued_5 <= + ~commitMask_5 & (issueLoad & _actualIssuePtr_T == 4'h5 | ~_GEN_25 & robIssued_5); + robIssued_6 <= + ~commitMask_6 & (issueLoad & _actualIssuePtr_T == 4'h6 | ~_GEN_26 & robIssued_6); + robIssued_7 <= + ~commitMask_7 & (issueLoad & _actualIssuePtr_T == 4'h7 | ~_GEN_27 & robIssued_7); + robIssued_8 <= + ~commitMask_8 & (issueLoad & _actualIssuePtr_T == 4'h8 | ~_GEN_28 & robIssued_8); + robIssued_9 <= + ~commitMask_9 & (issueLoad & _actualIssuePtr_T == 4'h9 | ~_GEN_29 & robIssued_9); + robIssued_10 <= + ~commitMask_10 + & (issueLoad & _actualIssuePtr_T == 4'hA | ~_GEN_30 & robIssued_10); + robIssued_11 <= + ~commitMask_11 + & (issueLoad & _actualIssuePtr_T == 4'hB | ~_GEN_31 & robIssued_11); + robIssued_12 <= + ~commitMask_12 + & (issueLoad & _actualIssuePtr_T == 4'hC | ~_GEN_32 & robIssued_12); + robIssued_13 <= + ~commitMask_13 + & (issueLoad & _actualIssuePtr_T == 4'hD | ~_GEN_33 & robIssued_13); + robIssued_14 <= + ~commitMask_14 + & (issueLoad & _actualIssuePtr_T == 4'hE | ~_GEN_34 & robIssued_14); + robIssued_15 <= + ~commitMask_15 & (issueLoad & (&_actualIssuePtr_T) | ~_GEN_35 & robIssued_15); + robComplete_0 <= + ~commitMask_0 + & (io_complete_valid & io_complete_bits == 4'h0 | ~_GEN_20 & robComplete_0); + robComplete_1 <= + ~commitMask_1 + & (io_complete_valid & io_complete_bits == 4'h1 | ~_GEN_21 & robComplete_1); + robComplete_2 <= + ~commitMask_2 + & (io_complete_valid & io_complete_bits == 4'h2 | ~_GEN_22 & robComplete_2); + robComplete_3 <= + ~commitMask_3 + & (io_complete_valid & io_complete_bits == 4'h3 | ~_GEN_23 & robComplete_3); + robComplete_4 <= + ~commitMask_4 + & (io_complete_valid & io_complete_bits == 4'h4 | ~_GEN_24 & robComplete_4); + robComplete_5 <= + ~commitMask_5 + & (io_complete_valid & io_complete_bits == 4'h5 | ~_GEN_25 & robComplete_5); + robComplete_6 <= + ~commitMask_6 + & (io_complete_valid & io_complete_bits == 4'h6 | ~_GEN_26 & robComplete_6); + robComplete_7 <= + ~commitMask_7 + & (io_complete_valid & io_complete_bits == 4'h7 | ~_GEN_27 & robComplete_7); + robComplete_8 <= + ~commitMask_8 + & (io_complete_valid & io_complete_bits == 4'h8 | ~_GEN_28 & robComplete_8); + robComplete_9 <= + ~commitMask_9 + & (io_complete_valid & io_complete_bits == 4'h9 | ~_GEN_29 & robComplete_9); + robComplete_10 <= + ~commitMask_10 + & (io_complete_valid & io_complete_bits == 4'hA | ~_GEN_30 & robComplete_10); + robComplete_11 <= + ~commitMask_11 + & (io_complete_valid & io_complete_bits == 4'hB | ~_GEN_31 & robComplete_11); + robComplete_12 <= + ~commitMask_12 + & (io_complete_valid & io_complete_bits == 4'hC | ~_GEN_32 & robComplete_12); + robComplete_13 <= + ~commitMask_13 + & (io_complete_valid & io_complete_bits == 4'hD | ~_GEN_33 & robComplete_13); + robComplete_14 <= + ~commitMask_14 + & (io_complete_valid & io_complete_bits == 4'hE | ~_GEN_34 & robComplete_14); + robComplete_15 <= + ~commitMask_15 + & (io_complete_valid & (&io_complete_bits) | ~_GEN_35 & robComplete_15); + if (_GEN_3) + nextInstId <= nextInstId + 64'h1; + ptr <= + ptr + + {1'h0, + {1'h0, {1'h0, commitKeep_1} + {1'h0, commitKeep_2}} + + {1'h0, {1'h0, commitKeep_3} + {1'h0, commitKeep_4}}} + + {1'h0, + {1'h0, {1'h0, commitKeep_5} + {1'h0, commitKeep_6}} + + {1'h0, {1'h0, commitKeep_7} + {1'h0, commitKeep_8}}} + + {1'h0, + {1'h0, {1'h0, commitKeep_9} + {1'h0, commitScan_9}} + + {1'h0, {1'h0, commitKeep_11} + {1'h0, commitKeep_12}}} + + {1'h0, + {1'h0, {1'h0, commitKeep_13} + {1'h0, commitKeep_14}} + + {1'h0, {1'h0, commitKeep_15} + {1'h0, commitScan_15}}}; + if (_isAllocatedSlot_T_30) begin + if (&tailPtr) + tailPtr <= 4'h0; + else + tailPtr <= tailPtr + 4'h1; + end + issuedCount <= + issuedCount + {4'h0, issueLoad} + - {4'h0, io_complete_valid & _GEN_4[io_complete_bits]}; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_36; + if (_GEN_67 & (&(robEntries_15_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_66; + else if (_GEN_65 & (&(robEntries_14_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_64; + else if (_GEN_63 & (&(robEntries_13_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_62; + else if (_GEN_61 & (&(robEntries_12_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_60; + else if (_GEN_59 & (&(robEntries_11_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_58; + else if (_GEN_57 & (&(robEntries_10_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_56; + else if (_GEN_55 & (&(robEntries_9_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_54; + else if (_GEN_53 & (&(robEntries_8_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_52; + else if (_GEN_51 & (&(robEntries_7_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_50; + else if (_GEN_49 & (&(robEntries_6_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_48; + else if (_GEN_47 & (&(robEntries_5_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_46; + else if (_GEN_45 & (&(robEntries_4_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_44; + else if (_GEN_43 & (&(robEntries_3_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_42; + else if (_GEN_41 & (&(robEntries_2_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_40; + else if (_GEN_39 & (&(robEntries_1_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_38; + else if (_GEN_37 & (&(robEntries_0_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_36; + if (issueLoad | io_complete_valid) + vbankBusy <= + vbankBusy & ~(io_complete_valid ? _GEN_18[io_complete_bits] : 16'h0) + | (issueLoad ? _GEN_18[_actualIssuePtr_T] : 16'h0); + if (isAllocatedSlot) + dependencyMask_0 <= allocDependencies & ~clearMask; + else + dependencyMask_0 <= dependencyMask_0 & ~clearMask; + if (isAllocatedSlot_1) + dependencyMask_1 <= allocDependencies & ~clearMask_1; + else + dependencyMask_1 <= dependencyMask_1 & ~clearMask_1; + if (isAllocatedSlot_2) + dependencyMask_2 <= allocDependencies & ~clearMask_2; + else + dependencyMask_2 <= dependencyMask_2 & ~clearMask_2; + if (isAllocatedSlot_3) + dependencyMask_3 <= allocDependencies & ~clearMask_3; + else + dependencyMask_3 <= dependencyMask_3 & ~clearMask_3; + if (isAllocatedSlot_4) + dependencyMask_4 <= allocDependencies & ~clearMask_4; + else + dependencyMask_4 <= dependencyMask_4 & ~clearMask_4; + if (isAllocatedSlot_5) + dependencyMask_5 <= allocDependencies & ~clearMask_5; + else + dependencyMask_5 <= dependencyMask_5 & ~clearMask_5; + if (isAllocatedSlot_6) + dependencyMask_6 <= allocDependencies & ~clearMask_6; + else + dependencyMask_6 <= dependencyMask_6 & ~clearMask_6; + if (isAllocatedSlot_7) + dependencyMask_7 <= allocDependencies & ~clearMask_7; + else + dependencyMask_7 <= dependencyMask_7 & ~clearMask_7; + if (isAllocatedSlot_8) + dependencyMask_8 <= allocDependencies & ~clearMask_8; + else + dependencyMask_8 <= dependencyMask_8 & ~clearMask_8; + if (isAllocatedSlot_9) + dependencyMask_9 <= allocDependencies & ~clearMask_9; + else + dependencyMask_9 <= dependencyMask_9 & ~clearMask_9; + if (isAllocatedSlot_10) + dependencyMask_10 <= allocDependencies & ~clearMask_10; + else + dependencyMask_10 <= dependencyMask_10 & ~clearMask_10; + if (isAllocatedSlot_11) + dependencyMask_11 <= allocDependencies & ~clearMask_11; + else + dependencyMask_11 <= dependencyMask_11 & ~clearMask_11; + if (isAllocatedSlot_12) + dependencyMask_12 <= allocDependencies & ~clearMask_12; + else + dependencyMask_12 <= dependencyMask_12 & ~clearMask_12; + if (isAllocatedSlot_13) + dependencyMask_13 <= allocDependencies & ~clearMask_13; + else + dependencyMask_13 <= dependencyMask_13 & ~clearMask_13; + if (isAllocatedSlot_14) + dependencyMask_14 <= allocDependencies & ~clearMask_14; + else + dependencyMask_14 <= dependencyMask_14 & ~clearMask_14; + if (isAllocatedSlot_15) + dependencyMask_15 <= allocDependencies & ~clearMask_15; + else + dependencyMask_15 <= dependencyMask_15 & ~clearMask_15; + if (issueStageReady) + issueStageValid <= issuePtrValid; + if (issuePtrReady) + issuePtrValid <= issueLoad; + end + if (issueStageReady & issuePtrFire) begin + automatic logic [15:0] _GEN_68 = + {{robEntries_15_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_14_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_13_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_12_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_11_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_10_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_9_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_8_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_7_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_6_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_5_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_4_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_3_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_2_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_1_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_0_cmd_bankAccess_rd_bank_0_valid}}; + automatic logic issuePayload_cmd_bankAccess_rd_bank_0_valid = + _GEN_68[issuePtr]; + automatic logic [15:0][9:0] _GEN_69 = + {{robEntries_15_cmd_bankAccess_rd_bank_0_id}, + {robEntries_14_cmd_bankAccess_rd_bank_0_id}, + {robEntries_13_cmd_bankAccess_rd_bank_0_id}, + {robEntries_12_cmd_bankAccess_rd_bank_0_id}, + {robEntries_11_cmd_bankAccess_rd_bank_0_id}, + {robEntries_10_cmd_bankAccess_rd_bank_0_id}, + {robEntries_9_cmd_bankAccess_rd_bank_0_id}, + {robEntries_8_cmd_bankAccess_rd_bank_0_id}, + {robEntries_7_cmd_bankAccess_rd_bank_0_id}, + {robEntries_6_cmd_bankAccess_rd_bank_0_id}, + {robEntries_5_cmd_bankAccess_rd_bank_0_id}, + {robEntries_4_cmd_bankAccess_rd_bank_0_id}, + {robEntries_3_cmd_bankAccess_rd_bank_0_id}, + {robEntries_2_cmd_bankAccess_rd_bank_0_id}, + {robEntries_1_cmd_bankAccess_rd_bank_0_id}, + {robEntries_0_cmd_bankAccess_rd_bank_0_id}}; + automatic logic [9:0] issuePayload_cmd_bankAccess_rd_bank_0_id = + _GEN_69[issuePtr]; + automatic logic [15:0] _GEN_70 = + {{robEntries_15_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_14_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_13_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_12_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_11_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_10_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_9_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_8_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_7_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_6_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_5_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_4_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_3_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_2_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_1_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_0_cmd_bankAccess_rd_bank_1_valid}}; + automatic logic issuePayload_cmd_bankAccess_rd_bank_1_valid = + _GEN_70[issuePtr]; + automatic logic [15:0][9:0] _GEN_71 = + {{robEntries_15_cmd_bankAccess_rd_bank_1_id}, + {robEntries_14_cmd_bankAccess_rd_bank_1_id}, + {robEntries_13_cmd_bankAccess_rd_bank_1_id}, + {robEntries_12_cmd_bankAccess_rd_bank_1_id}, + {robEntries_11_cmd_bankAccess_rd_bank_1_id}, + {robEntries_10_cmd_bankAccess_rd_bank_1_id}, + {robEntries_9_cmd_bankAccess_rd_bank_1_id}, + {robEntries_8_cmd_bankAccess_rd_bank_1_id}, + {robEntries_7_cmd_bankAccess_rd_bank_1_id}, + {robEntries_6_cmd_bankAccess_rd_bank_1_id}, + {robEntries_5_cmd_bankAccess_rd_bank_1_id}, + {robEntries_4_cmd_bankAccess_rd_bank_1_id}, + {robEntries_3_cmd_bankAccess_rd_bank_1_id}, + {robEntries_2_cmd_bankAccess_rd_bank_1_id}, + {robEntries_1_cmd_bankAccess_rd_bank_1_id}, + {robEntries_0_cmd_bankAccess_rd_bank_1_id}}; + automatic logic [9:0] issuePayload_cmd_bankAccess_rd_bank_1_id = + _GEN_71[issuePtr]; + automatic logic [15:0] _GEN_72 = + {{robEntries_15_cmd_bankAccess_wr_bank_valid}, + {robEntries_14_cmd_bankAccess_wr_bank_valid}, + {robEntries_13_cmd_bankAccess_wr_bank_valid}, + {robEntries_12_cmd_bankAccess_wr_bank_valid}, + {robEntries_11_cmd_bankAccess_wr_bank_valid}, + {robEntries_10_cmd_bankAccess_wr_bank_valid}, + {robEntries_9_cmd_bankAccess_wr_bank_valid}, + {robEntries_8_cmd_bankAccess_wr_bank_valid}, + {robEntries_7_cmd_bankAccess_wr_bank_valid}, + {robEntries_6_cmd_bankAccess_wr_bank_valid}, + {robEntries_5_cmd_bankAccess_wr_bank_valid}, + {robEntries_4_cmd_bankAccess_wr_bank_valid}, + {robEntries_3_cmd_bankAccess_wr_bank_valid}, + {robEntries_2_cmd_bankAccess_wr_bank_valid}, + {robEntries_1_cmd_bankAccess_wr_bank_valid}, + {robEntries_0_cmd_bankAccess_wr_bank_valid}}; + automatic logic issuePayload_cmd_bankAccess_wr_bank_valid = + _GEN_72[issuePtr]; + automatic logic [15:0][9:0] _GEN_73 = + {{robEntries_15_cmd_bankAccess_wr_bank_id}, + {robEntries_14_cmd_bankAccess_wr_bank_id}, + {robEntries_13_cmd_bankAccess_wr_bank_id}, + {robEntries_12_cmd_bankAccess_wr_bank_id}, + {robEntries_11_cmd_bankAccess_wr_bank_id}, + {robEntries_10_cmd_bankAccess_wr_bank_id}, + {robEntries_9_cmd_bankAccess_wr_bank_id}, + {robEntries_8_cmd_bankAccess_wr_bank_id}, + {robEntries_7_cmd_bankAccess_wr_bank_id}, + {robEntries_6_cmd_bankAccess_wr_bank_id}, + {robEntries_5_cmd_bankAccess_wr_bank_id}, + {robEntries_4_cmd_bankAccess_wr_bank_id}, + {robEntries_3_cmd_bankAccess_wr_bank_id}, + {robEntries_2_cmd_bankAccess_wr_bank_id}, + {robEntries_1_cmd_bankAccess_wr_bank_id}, + {robEntries_0_cmd_bankAccess_wr_bank_id}}; + automatic logic [9:0] issuePayload_cmd_bankAccess_wr_bank_id = + _GEN_73[issuePtr]; + automatic logic [15:0][3:0] _GEN_74 = + {{bankCols_15}, + {bankCols_14}, + {bankCols_13}, + {bankCols_12}, + {bankCols_11}, + {bankCols_10}, + {bankCols_9}, + {bankCols_8}, + {bankCols_7}, + {bankCols_6}, + {bankCols_5}, + {bankCols_4}, + {bankCols_3}, + {bankCols_2}, + {bankCols_1}, + {bankCols_0}}; + automatic logic [15:0][4:0] _GEN_75 = + {{robEntries_15_cmd_ball_bid}, + {robEntries_14_cmd_ball_bid}, + {robEntries_13_cmd_ball_bid}, + {robEntries_12_cmd_ball_bid}, + {robEntries_11_cmd_ball_bid}, + {robEntries_10_cmd_ball_bid}, + {robEntries_9_cmd_ball_bid}, + {robEntries_8_cmd_ball_bid}, + {robEntries_7_cmd_ball_bid}, + {robEntries_6_cmd_ball_bid}, + {robEntries_5_cmd_ball_bid}, + {robEntries_4_cmd_ball_bid}, + {robEntries_3_cmd_ball_bid}, + {robEntries_2_cmd_ball_bid}, + {robEntries_1_cmd_ball_bid}, + {robEntries_0_cmd_ball_bid}}; + automatic logic [15:0][31:0] _GEN_76 = + {{robEntries_15_cmd_cmd_raw_inst}, + {robEntries_14_cmd_cmd_raw_inst}, + {robEntries_13_cmd_cmd_raw_inst}, + {robEntries_12_cmd_cmd_raw_inst}, + {robEntries_11_cmd_cmd_raw_inst}, + {robEntries_10_cmd_cmd_raw_inst}, + {robEntries_9_cmd_cmd_raw_inst}, + {robEntries_8_cmd_cmd_raw_inst}, + {robEntries_7_cmd_cmd_raw_inst}, + {robEntries_6_cmd_cmd_raw_inst}, + {robEntries_5_cmd_cmd_raw_inst}, + {robEntries_4_cmd_cmd_raw_inst}, + {robEntries_3_cmd_cmd_raw_inst}, + {robEntries_2_cmd_cmd_raw_inst}, + {robEntries_1_cmd_cmd_raw_inst}, + {robEntries_0_cmd_cmd_raw_inst}}; + automatic logic [15:0][2:0] _GEN_77 = + {{robEntries_15_cmd_cmd_funct3}, + {robEntries_14_cmd_cmd_funct3}, + {robEntries_13_cmd_cmd_funct3}, + {robEntries_12_cmd_cmd_funct3}, + {robEntries_11_cmd_cmd_funct3}, + {robEntries_10_cmd_cmd_funct3}, + {robEntries_9_cmd_cmd_funct3}, + {robEntries_8_cmd_cmd_funct3}, + {robEntries_7_cmd_cmd_funct3}, + {robEntries_6_cmd_cmd_funct3}, + {robEntries_5_cmd_cmd_funct3}, + {robEntries_4_cmd_cmd_funct3}, + {robEntries_3_cmd_cmd_funct3}, + {robEntries_2_cmd_cmd_funct3}, + {robEntries_1_cmd_cmd_funct3}, + {robEntries_0_cmd_cmd_funct3}}; + automatic logic [15:0][4:0] _GEN_78 = + {{robEntries_15_cmd_cmd_rs2}, + {robEntries_14_cmd_cmd_rs2}, + {robEntries_13_cmd_cmd_rs2}, + {robEntries_12_cmd_cmd_rs2}, + {robEntries_11_cmd_cmd_rs2}, + {robEntries_10_cmd_cmd_rs2}, + {robEntries_9_cmd_cmd_rs2}, + {robEntries_8_cmd_cmd_rs2}, + {robEntries_7_cmd_cmd_rs2}, + {robEntries_6_cmd_cmd_rs2}, + {robEntries_5_cmd_cmd_rs2}, + {robEntries_4_cmd_cmd_rs2}, + {robEntries_3_cmd_cmd_rs2}, + {robEntries_2_cmd_cmd_rs2}, + {robEntries_1_cmd_cmd_rs2}, + {robEntries_0_cmd_cmd_rs2}}; + automatic logic [15:0][4:0] _GEN_79 = + {{robEntries_15_cmd_cmd_rs1}, + {robEntries_14_cmd_cmd_rs1}, + {robEntries_13_cmd_cmd_rs1}, + {robEntries_12_cmd_cmd_rs1}, + {robEntries_11_cmd_cmd_rs1}, + {robEntries_10_cmd_cmd_rs1}, + {robEntries_9_cmd_cmd_rs1}, + {robEntries_8_cmd_cmd_rs1}, + {robEntries_7_cmd_cmd_rs1}, + {robEntries_6_cmd_cmd_rs1}, + {robEntries_5_cmd_cmd_rs1}, + {robEntries_4_cmd_cmd_rs1}, + {robEntries_3_cmd_cmd_rs1}, + {robEntries_2_cmd_cmd_rs1}, + {robEntries_1_cmd_cmd_rs1}, + {robEntries_0_cmd_cmd_rs1}}; + automatic logic [15:0] _GEN_80 = + {{robEntries_15_cmd_cmd_xd}, + {robEntries_14_cmd_cmd_xd}, + {robEntries_13_cmd_cmd_xd}, + {robEntries_12_cmd_cmd_xd}, + {robEntries_11_cmd_cmd_xd}, + {robEntries_10_cmd_cmd_xd}, + {robEntries_9_cmd_cmd_xd}, + {robEntries_8_cmd_cmd_xd}, + {robEntries_7_cmd_cmd_xd}, + {robEntries_6_cmd_cmd_xd}, + {robEntries_5_cmd_cmd_xd}, + {robEntries_4_cmd_cmd_xd}, + {robEntries_3_cmd_cmd_xd}, + {robEntries_2_cmd_cmd_xd}, + {robEntries_1_cmd_cmd_xd}, + {robEntries_0_cmd_cmd_xd}}; + automatic logic [15:0] _GEN_81 = + {{robEntries_15_cmd_cmd_xs1}, + {robEntries_14_cmd_cmd_xs1}, + {robEntries_13_cmd_cmd_xs1}, + {robEntries_12_cmd_cmd_xs1}, + {robEntries_11_cmd_cmd_xs1}, + {robEntries_10_cmd_cmd_xs1}, + {robEntries_9_cmd_cmd_xs1}, + {robEntries_8_cmd_cmd_xs1}, + {robEntries_7_cmd_cmd_xs1}, + {robEntries_6_cmd_cmd_xs1}, + {robEntries_5_cmd_cmd_xs1}, + {robEntries_4_cmd_cmd_xs1}, + {robEntries_3_cmd_cmd_xs1}, + {robEntries_2_cmd_cmd_xs1}, + {robEntries_1_cmd_cmd_xs1}, + {robEntries_0_cmd_cmd_xs1}}; + automatic logic [15:0] _GEN_82 = + {{robEntries_15_cmd_cmd_xs2}, + {robEntries_14_cmd_cmd_xs2}, + {robEntries_13_cmd_cmd_xs2}, + {robEntries_12_cmd_cmd_xs2}, + {robEntries_11_cmd_cmd_xs2}, + {robEntries_10_cmd_cmd_xs2}, + {robEntries_9_cmd_cmd_xs2}, + {robEntries_8_cmd_cmd_xs2}, + {robEntries_7_cmd_cmd_xs2}, + {robEntries_6_cmd_cmd_xs2}, + {robEntries_5_cmd_cmd_xs2}, + {robEntries_4_cmd_cmd_xs2}, + {robEntries_3_cmd_cmd_xs2}, + {robEntries_2_cmd_cmd_xs2}, + {robEntries_1_cmd_cmd_xs2}, + {robEntries_0_cmd_cmd_xs2}}; + automatic logic [15:0][4:0] _GEN_83 = + {{robEntries_15_cmd_cmd_rd}, + {robEntries_14_cmd_cmd_rd}, + {robEntries_13_cmd_cmd_rd}, + {robEntries_12_cmd_cmd_rd}, + {robEntries_11_cmd_cmd_rd}, + {robEntries_10_cmd_cmd_rd}, + {robEntries_9_cmd_cmd_rd}, + {robEntries_8_cmd_cmd_rd}, + {robEntries_7_cmd_cmd_rd}, + {robEntries_6_cmd_cmd_rd}, + {robEntries_5_cmd_cmd_rd}, + {robEntries_4_cmd_cmd_rd}, + {robEntries_3_cmd_cmd_rd}, + {robEntries_2_cmd_cmd_rd}, + {robEntries_1_cmd_cmd_rd}, + {robEntries_0_cmd_cmd_rd}}; + automatic logic [15:0][6:0] _GEN_84 = + {{robEntries_15_cmd_cmd_opcode}, + {robEntries_14_cmd_cmd_opcode}, + {robEntries_13_cmd_cmd_opcode}, + {robEntries_12_cmd_cmd_opcode}, + {robEntries_11_cmd_cmd_opcode}, + {robEntries_10_cmd_cmd_opcode}, + {robEntries_9_cmd_cmd_opcode}, + {robEntries_8_cmd_cmd_opcode}, + {robEntries_7_cmd_cmd_opcode}, + {robEntries_6_cmd_cmd_opcode}, + {robEntries_5_cmd_cmd_opcode}, + {robEntries_4_cmd_cmd_opcode}, + {robEntries_3_cmd_cmd_opcode}, + {robEntries_2_cmd_cmd_opcode}, + {robEntries_1_cmd_cmd_opcode}, + {robEntries_0_cmd_cmd_opcode}}; + automatic logic [15:0] _GEN_85 = + {{robEntries_15_cmd_isFence}, + {robEntries_14_cmd_isFence}, + {robEntries_13_cmd_isFence}, + {robEntries_12_cmd_isFence}, + {robEntries_11_cmd_isFence}, + {robEntries_10_cmd_isFence}, + {robEntries_9_cmd_isFence}, + {robEntries_8_cmd_isFence}, + {robEntries_7_cmd_isFence}, + {robEntries_6_cmd_isFence}, + {robEntries_5_cmd_isFence}, + {robEntries_4_cmd_isFence}, + {robEntries_3_cmd_isFence}, + {robEntries_2_cmd_isFence}, + {robEntries_1_cmd_isFence}, + {robEntries_0_cmd_isFence}}; + automatic logic [15:0] _GEN_86 = + {{robEntries_15_cmd_isBarrier}, + {robEntries_14_cmd_isBarrier}, + {robEntries_13_cmd_isBarrier}, + {robEntries_12_cmd_isBarrier}, + {robEntries_11_cmd_isBarrier}, + {robEntries_10_cmd_isBarrier}, + {robEntries_9_cmd_isBarrier}, + {robEntries_8_cmd_isBarrier}, + {robEntries_7_cmd_isBarrier}, + {robEntries_6_cmd_isBarrier}, + {robEntries_5_cmd_isBarrier}, + {robEntries_4_cmd_isBarrier}, + {robEntries_3_cmd_isBarrier}, + {robEntries_2_cmd_isBarrier}, + {robEntries_1_cmd_isBarrier}, + {robEntries_0_cmd_isBarrier}}; + issueStageEntry_cmd_domain_id <= _GEN_5[issuePtr]; + issueStageEntry_cmd_ball_bid <= _GEN_75[issuePtr]; + issueStageEntry_cmd_cmd_raw_inst <= _GEN_76[issuePtr]; + issueStageEntry_cmd_cmd_pc <= _GEN_6[issuePtr]; + issueStageEntry_cmd_cmd_funct <= _GEN_7[issuePtr]; + issueStageEntry_cmd_cmd_funct3 <= _GEN_77[issuePtr]; + issueStageEntry_cmd_cmd_rs2 <= _GEN_78[issuePtr]; + issueStageEntry_cmd_cmd_rs1 <= _GEN_79[issuePtr]; + issueStageEntry_cmd_cmd_xd <= _GEN_80[issuePtr]; + issueStageEntry_cmd_cmd_xs1 <= _GEN_81[issuePtr]; + issueStageEntry_cmd_cmd_xs2 <= _GEN_82[issuePtr]; + issueStageEntry_cmd_cmd_rd <= _GEN_83[issuePtr]; + issueStageEntry_cmd_cmd_opcode <= _GEN_84[issuePtr]; + issueStageEntry_cmd_cmd_rs1Data <= _robOperands_ext_R0_data[127:64]; + issueStageEntry_cmd_cmd_rs2Data <= _robOperands_ext_R0_data[63:0]; + issueStageEntry_cmd_bankAccess_rd_bank_0_valid <= + issuePayload_cmd_bankAccess_rd_bank_0_valid; + issueStageEntry_cmd_bankAccess_rd_bank_0_id <= + issuePayload_cmd_bankAccess_rd_bank_0_id; + issueStageEntry_cmd_bankAccess_rd_bank_1_valid <= + issuePayload_cmd_bankAccess_rd_bank_1_valid; + issueStageEntry_cmd_bankAccess_rd_bank_1_id <= + issuePayload_cmd_bankAccess_rd_bank_1_id; + issueStageEntry_cmd_bankAccess_wr_bank_valid <= + issuePayload_cmd_bankAccess_wr_bank_valid; + issueStageEntry_cmd_bankAccess_wr_bank_id <= issuePayload_cmd_bankAccess_wr_bank_id; + issueStageEntry_cmd_op1_col <= + issuePayload_cmd_bankAccess_rd_bank_0_valid + ? _GEN_74[issuePayload_cmd_bankAccess_rd_bank_0_id[3:0]] + : 4'h0; + issueStageEntry_cmd_op2_col <= + issuePayload_cmd_bankAccess_rd_bank_1_valid + ? _GEN_74[issuePayload_cmd_bankAccess_rd_bank_1_id[3:0]] + : 4'h0; + issueStageEntry_cmd_wr_col <= + issuePayload_cmd_bankAccess_wr_bank_valid + ? _GEN_74[issuePayload_cmd_bankAccess_wr_bank_id[3:0]] + : 4'h0; + issueStageEntry_cmd_isFence <= _GEN_85[issuePtr]; + issueStageEntry_cmd_isBarrier <= _GEN_86[issuePtr]; + issueStageEntry_renamedBankAccess_rd_bank_0_valid <= _GEN_13[issuePtr]; + issueStageEntry_renamedBankAccess_rd_bank_0_id <= _GEN_14[issuePtr]; + issueStageEntry_renamedBankAccess_rd_bank_1_valid <= _GEN_15[issuePtr]; + issueStageEntry_renamedBankAccess_rd_bank_1_id <= _GEN_16[issuePtr]; + issueStageEntry_renamedBankAccess_wr_bank_valid <= _GEN_10[issuePtr]; + issueStageEntry_renamedBankAccess_wr_bank_id <= _GEN_11[issuePtr]; + issueStageEntry_rob_id <= _GEN_19[issuePtr]; + end + if (issuePtrReady & issueLoad) + issuePtr <= _actualIssuePtr_T; + end // always @(posedge) + BankAliasTable bat ( + .clock (clock), + .reset (reset), + .io_alloc_valid (_isAllocatedSlot_T_30), + .io_alloc_rob_id (tailPtr), + .io_alloc_raw_rd_bank_0_valid (io_alloc_bits_bankAccess_rd_bank_0_valid), + .io_alloc_raw_rd_bank_0_id (io_alloc_bits_bankAccess_rd_bank_0_id), + .io_alloc_raw_rd_bank_1_valid (io_alloc_bits_bankAccess_rd_bank_1_valid), + .io_alloc_raw_rd_bank_1_id (io_alloc_bits_bankAccess_rd_bank_1_id), + .io_alloc_raw_wr_bank_valid (io_alloc_bits_bankAccess_wr_bank_valid), + .io_alloc_raw_wr_bank_id (io_alloc_bits_bankAccess_wr_bank_id), + .io_alloc_renamed_rd_bank_0_valid (_bat_io_alloc_renamed_rd_bank_0_valid), + .io_alloc_renamed_rd_bank_0_id (_bat_io_alloc_renamed_rd_bank_0_id), + .io_alloc_renamed_rd_bank_1_valid (_bat_io_alloc_renamed_rd_bank_1_valid), + .io_alloc_renamed_rd_bank_1_id (_bat_io_alloc_renamed_rd_bank_1_id), + .io_alloc_renamed_wr_bank_valid (_bat_io_alloc_renamed_wr_bank_valid), + .io_alloc_renamed_wr_bank_id (_bat_io_alloc_renamed_wr_bank_id), + .io_free_valid + (|{commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0}), + .io_free_mask_0 (commitMask_0), + .io_free_mask_1 (commitMask_1), + .io_free_mask_2 (commitMask_2), + .io_free_mask_3 (commitMask_3), + .io_free_mask_4 (commitMask_4), + .io_free_mask_5 (commitMask_5), + .io_free_mask_6 (commitMask_6), + .io_free_mask_7 (commitMask_7), + .io_free_mask_8 (commitMask_8), + .io_free_mask_9 (commitMask_9), + .io_free_mask_10 (commitMask_10), + .io_free_mask_11 (commitMask_11), + .io_free_mask_12 (commitMask_12), + .io_free_mask_13 (commitMask_13), + .io_free_mask_14 (commitMask_14), + .io_free_mask_15 (commitMask_15) + ); + BankScoreboard scoreboard ( + .clock (clock), + .reset (reset), + .alloc_valid + (_isAllocatedSlot_T_30 & io_alloc_bits_bankAccess_wr_bank_valid), + .alloc_bits_wr_bank_valid (_bat_io_alloc_renamed_wr_bank_valid), + .alloc_bits_wr_bank_id (_bat_io_alloc_renamed_wr_bank_id), + .complete_valid (io_complete_valid), + .complete_bits_wr_bank_valid (io_complete_valid & _GEN_10[io_complete_bits]), + .complete_bits_wr_bank_id (io_complete_valid ? _GEN_11[io_complete_bits] : 10'h0), + .queryVec_0_rd_bank_0_valid (_GEN_13[ptr]), + .queryVec_0_rd_bank_0_id (_GEN_14[ptr]), + .queryVec_0_rd_bank_1_valid (_GEN_15[ptr]), + .queryVec_0_rd_bank_1_id (_GEN_16[ptr]), + .queryVec_1_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1446]), + .queryVec_1_rd_bank_0_id (_GEN_14[_hits_ptr_T_1446]), + .queryVec_1_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1446]), + .queryVec_1_rd_bank_1_id (_GEN_16[_hits_ptr_T_1446]), + .queryVec_2_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1452]), + .queryVec_2_rd_bank_0_id (_GEN_14[_hits_ptr_T_1452]), + .queryVec_2_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1452]), + .queryVec_2_rd_bank_1_id (_GEN_16[_hits_ptr_T_1452]), + .queryVec_3_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1458]), + .queryVec_3_rd_bank_0_id (_GEN_14[_hits_ptr_T_1458]), + .queryVec_3_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1458]), + .queryVec_3_rd_bank_1_id (_GEN_16[_hits_ptr_T_1458]), + .queryVec_4_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1464]), + .queryVec_4_rd_bank_0_id (_GEN_14[_hits_ptr_T_1464]), + .queryVec_4_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1464]), + .queryVec_4_rd_bank_1_id (_GEN_16[_hits_ptr_T_1464]), + .queryVec_5_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1470]), + .queryVec_5_rd_bank_0_id (_GEN_14[_hits_ptr_T_1470]), + .queryVec_5_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1470]), + .queryVec_5_rd_bank_1_id (_GEN_16[_hits_ptr_T_1470]), + .queryVec_6_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1476]), + .queryVec_6_rd_bank_0_id (_GEN_14[_hits_ptr_T_1476]), + .queryVec_6_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1476]), + .queryVec_6_rd_bank_1_id (_GEN_16[_hits_ptr_T_1476]), + .queryVec_7_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1482]), + .queryVec_7_rd_bank_0_id (_GEN_14[_hits_ptr_T_1482]), + .queryVec_7_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1482]), + .queryVec_7_rd_bank_1_id (_GEN_16[_hits_ptr_T_1482]), + .queryVec_8_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1488]), + .queryVec_8_rd_bank_0_id (_GEN_14[_hits_ptr_T_1488]), + .queryVec_8_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1488]), + .queryVec_8_rd_bank_1_id (_GEN_16[_hits_ptr_T_1488]), + .queryVec_9_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1494]), + .queryVec_9_rd_bank_0_id (_GEN_14[_hits_ptr_T_1494]), + .queryVec_9_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1494]), + .queryVec_9_rd_bank_1_id (_GEN_16[_hits_ptr_T_1494]), + .queryVec_10_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1500]), + .queryVec_10_rd_bank_0_id (_GEN_14[_hits_ptr_T_1500]), + .queryVec_10_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1500]), + .queryVec_10_rd_bank_1_id (_GEN_16[_hits_ptr_T_1500]), + .queryVec_11_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1506]), + .queryVec_11_rd_bank_0_id (_GEN_14[_hits_ptr_T_1506]), + .queryVec_11_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1506]), + .queryVec_11_rd_bank_1_id (_GEN_16[_hits_ptr_T_1506]), + .queryVec_12_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1512]), + .queryVec_12_rd_bank_0_id (_GEN_14[_hits_ptr_T_1512]), + .queryVec_12_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1512]), + .queryVec_12_rd_bank_1_id (_GEN_16[_hits_ptr_T_1512]), + .queryVec_13_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1518]), + .queryVec_13_rd_bank_0_id (_GEN_14[_hits_ptr_T_1518]), + .queryVec_13_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1518]), + .queryVec_13_rd_bank_1_id (_GEN_16[_hits_ptr_T_1518]), + .queryVec_14_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1524]), + .queryVec_14_rd_bank_0_id (_GEN_14[_hits_ptr_T_1524]), + .queryVec_14_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1524]), + .queryVec_14_rd_bank_1_id (_GEN_16[_hits_ptr_T_1524]), + .queryVec_15_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1530]), + .queryVec_15_rd_bank_0_id (_GEN_14[_hits_ptr_T_1530]), + .queryVec_15_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1530]), + .queryVec_15_rd_bank_1_id (_GEN_16[_hits_ptr_T_1530]), + .hazardVec_0 (_scoreboard_hazardVec_0), + .hazardVec_1 (_scoreboard_hazardVec_1), + .hazardVec_2 (_scoreboard_hazardVec_2), + .hazardVec_3 (_scoreboard_hazardVec_3), + .hazardVec_4 (_scoreboard_hazardVec_4), + .hazardVec_5 (_scoreboard_hazardVec_5), + .hazardVec_6 (_scoreboard_hazardVec_6), + .hazardVec_7 (_scoreboard_hazardVec_7), + .hazardVec_8 (_scoreboard_hazardVec_8), + .hazardVec_9 (_scoreboard_hazardVec_9), + .hazardVec_10 (_scoreboard_hazardVec_10), + .hazardVec_11 (_scoreboard_hazardVec_11), + .hazardVec_12 (_scoreboard_hazardVec_12), + .hazardVec_13 (_scoreboard_hazardVec_13), + .hazardVec_14 (_scoreboard_hazardVec_14), + .hazardVec_15 (_scoreboard_hazardVec_15) + ); + ITraceDPI itraceAlloc ( + .clock (clock), + .reset (reset), + .is_issue ({6'h0, _isAllocatedSlot_T_30, 1'h0}), + .hart_id (64'h0), + .rob_id (_isAllocatedSlot_T_30 ? {28'h0, tailPtr} : 32'h0), + .inst_id (_GEN_3 ? nextInstId : 64'h0), + .domain_id (_isAllocatedSlot_T_30 ? {28'h0, io_alloc_bits_domain_id} : 32'h0), + .funct (_isAllocatedSlot_T_30 ? {25'h0, io_alloc_bits_cmd_funct} : 32'h0), + .pc (_isAllocatedSlot_T_30 ? io_alloc_bits_cmd_pc : 64'h0), + .rs1_data (_isAllocatedSlot_T_30 ? io_alloc_bits_cmd_rs1Data : 64'h0), + .rs2_data (_isAllocatedSlot_T_30 ? io_alloc_bits_cmd_rs2Data : 64'h0), + .enable (_isAllocatedSlot_T_30) + ); + ITraceDPI itraceIssue ( + .clock (clock), + .reset (reset), + .is_issue ({7'h0, issueLoad}), + .hart_id (64'h0), + .rob_id (issueLoad ? {28'h0, _GEN_19[_actualIssuePtr_T]} : 32'h0), + .inst_id (issueLoad ? _GEN_12[_actualIssuePtr_T] : 64'h0), + .domain_id (issueLoad ? {28'h0, _GEN_5[_actualIssuePtr_T]} : 32'h0), + .funct (issueLoad ? {25'h0, _GEN_7[_actualIssuePtr_T]} : 32'h0), + .pc (issueLoad ? _GEN_6[_actualIssuePtr_T] : 64'h0), + .rs1_data (issueLoad ? _GEN_8[_actualIssuePtr_T] : 64'h0), + .rs2_data (issueLoad ? _GEN_9[_actualIssuePtr_T] : 64'h0), + .enable (issueLoad) + ); + ITraceDPI itraceComp ( + .clock (clock), + .reset (reset), + .is_issue (8'h0), + .hart_id (64'h0), + .rob_id (io_complete_valid ? {28'h0, io_complete_bits} : 32'h0), + .inst_id (io_complete_valid ? _GEN_12[io_complete_bits] : 64'h0), + .domain_id (io_complete_valid ? {28'h0, _GEN_5[io_complete_bits]} : 32'h0), + .funct (io_complete_valid ? {25'h0, _GEN_7[io_complete_bits]} : 32'h0), + .pc (io_complete_valid ? _GEN_6[io_complete_bits] : 64'h0), + .rs1_data (io_complete_valid ? _GEN_8[io_complete_bits] : 64'h0), + .rs2_data (io_complete_valid ? _GEN_9[io_complete_bits] : 64'h0), + .enable (io_complete_valid) + ); + robOperands_16x128 robOperands_ext ( + .R0_addr (readAddress), + .R0_en (readEnable), + .R0_clk (clock), + .R0_data (_robOperands_ext_R0_data), + .W0_addr (tailPtr), + .W0_en (_isAllocatedSlot_T_30), + .W0_clk (clock), + .W0_data ({io_alloc_bits_cmd_rs1Data, io_alloc_bits_cmd_rs2Data}) + ); + assign io_alloc_ready = io_alloc_ready_0; + assign io_issue_valid = issueStageValid & ~io_subRobActive; + assign io_issue_bits_cmd_domain_id = issueStageEntry_cmd_domain_id; + assign io_issue_bits_cmd_ball_bid = issueStageEntry_cmd_ball_bid; + assign io_issue_bits_cmd_cmd_raw_inst = issueStageEntry_cmd_cmd_raw_inst; + assign io_issue_bits_cmd_cmd_pc = issueStageEntry_cmd_cmd_pc; + assign io_issue_bits_cmd_cmd_funct = issueStageEntry_cmd_cmd_funct; + assign io_issue_bits_cmd_cmd_funct3 = issueStageEntry_cmd_cmd_funct3; + assign io_issue_bits_cmd_cmd_rs2 = issueStageEntry_cmd_cmd_rs2; + assign io_issue_bits_cmd_cmd_rs1 = issueStageEntry_cmd_cmd_rs1; + assign io_issue_bits_cmd_cmd_xd = issueStageEntry_cmd_cmd_xd; + assign io_issue_bits_cmd_cmd_xs1 = issueStageEntry_cmd_cmd_xs1; + assign io_issue_bits_cmd_cmd_xs2 = issueStageEntry_cmd_cmd_xs2; + assign io_issue_bits_cmd_cmd_rd = issueStageEntry_cmd_cmd_rd; + assign io_issue_bits_cmd_cmd_opcode = issueStageEntry_cmd_cmd_opcode; + assign io_issue_bits_cmd_cmd_rs1Data = issueStageEntry_cmd_cmd_rs1Data; + assign io_issue_bits_cmd_cmd_rs2Data = issueStageEntry_cmd_cmd_rs2Data; + assign io_issue_bits_cmd_bankAccess_rd_bank_0_valid = + issueStageEntry_cmd_bankAccess_rd_bank_0_valid; + assign io_issue_bits_cmd_bankAccess_rd_bank_0_id = + issueStageEntry_cmd_bankAccess_rd_bank_0_id; + assign io_issue_bits_cmd_bankAccess_rd_bank_1_valid = + issueStageEntry_cmd_bankAccess_rd_bank_1_valid; + assign io_issue_bits_cmd_bankAccess_rd_bank_1_id = + issueStageEntry_cmd_bankAccess_rd_bank_1_id; + assign io_issue_bits_cmd_bankAccess_wr_bank_valid = + issueStageEntry_cmd_bankAccess_wr_bank_valid; + assign io_issue_bits_cmd_bankAccess_wr_bank_id = + issueStageEntry_cmd_bankAccess_wr_bank_id; + assign io_issue_bits_cmd_op1_col = issueStageEntry_cmd_op1_col; + assign io_issue_bits_cmd_op2_col = issueStageEntry_cmd_op2_col; + assign io_issue_bits_cmd_wr_col = issueStageEntry_cmd_wr_col; + assign io_issue_bits_cmd_isFence = issueStageEntry_cmd_isFence; + assign io_issue_bits_cmd_isBarrier = issueStageEntry_cmd_isBarrier; + assign io_issue_bits_renamedBankAccess_rd_bank_0_valid = + issueStageEntry_renamedBankAccess_rd_bank_0_valid; + assign io_issue_bits_renamedBankAccess_rd_bank_0_id = + issueStageEntry_renamedBankAccess_rd_bank_0_id; + assign io_issue_bits_renamedBankAccess_rd_bank_1_valid = + issueStageEntry_renamedBankAccess_rd_bank_1_valid; + assign io_issue_bits_renamedBankAccess_rd_bank_1_id = + issueStageEntry_renamedBankAccess_rd_bank_1_id; + assign io_issue_bits_renamedBankAccess_wr_bank_valid = + issueStageEntry_renamedBankAccess_wr_bank_valid; + assign io_issue_bits_renamedBankAccess_wr_bank_id = + issueStageEntry_renamedBankAccess_wr_bank_id; + assign io_issue_bits_rob_id = issueStageEntry_rob_id; + assign io_empty = _isFull_T & ~_GEN_0; + assign io_full = isFull; + assign io_head_ptr = ptr; + assign io_issued_count = issuedCount; + assign io_entry_valid_0 = robValid_0; + assign io_entry_valid_1 = robValid_1; + assign io_entry_valid_2 = robValid_2; + assign io_entry_valid_3 = robValid_3; + assign io_entry_valid_4 = robValid_4; + assign io_entry_valid_5 = robValid_5; + assign io_entry_valid_6 = robValid_6; + assign io_entry_valid_7 = robValid_7; + assign io_entry_valid_8 = robValid_8; + assign io_entry_valid_9 = robValid_9; + assign io_entry_valid_10 = robValid_10; + assign io_entry_valid_11 = robValid_11; + assign io_entry_valid_12 = robValid_12; + assign io_entry_valid_13 = robValid_13; + assign io_entry_valid_14 = robValid_14; + assign io_entry_valid_15 = robValid_15; + assign io_entry_complete_0 = robComplete_0; + assign io_entry_complete_1 = robComplete_1; + assign io_entry_complete_2 = robComplete_2; + assign io_entry_complete_3 = robComplete_3; + assign io_entry_complete_4 = robComplete_4; + assign io_entry_complete_5 = robComplete_5; + assign io_entry_complete_6 = robComplete_6; + assign io_entry_complete_7 = robComplete_7; + assign io_entry_complete_8 = robComplete_8; + assign io_entry_complete_9 = robComplete_9; + assign io_entry_complete_10 = robComplete_10; + assign io_entry_complete_11 = robComplete_11; + assign io_entry_complete_12 = robComplete_12; + assign io_entry_complete_13 = robComplete_13; + assign io_entry_complete_14 = robComplete_14; + assign io_entry_complete_15 = robComplete_15; + assign io_inst_ids_0 = instIds_0; + assign io_inst_ids_1 = instIds_1; + assign io_inst_ids_2 = instIds_2; + assign io_inst_ids_3 = instIds_3; + assign io_inst_ids_4 = instIds_4; + assign io_inst_ids_5 = instIds_5; + assign io_inst_ids_6 = instIds_6; + assign io_inst_ids_7 = instIds_7; + assign io_inst_ids_8 = instIds_8; + assign io_inst_ids_9 = instIds_9; + assign io_inst_ids_10 = instIds_10; + assign io_inst_ids_11 = instIds_11; + assign io_inst_ids_12 = instIds_12; + assign io_inst_ids_13 = instIds_13; + assign io_inst_ids_14 = instIds_14; + assign io_inst_ids_15 = instIds_15; +endmodule + +module GlobalROB_1( + input clock, + reset, + output io_alloc_ready, + input io_alloc_valid, + input [3:0] io_alloc_bits_domain_id, + input [4:0] io_alloc_bits_ball_bid, + input [31:0] io_alloc_bits_cmd_raw_inst, + input [63:0] io_alloc_bits_cmd_pc, + input [6:0] io_alloc_bits_cmd_funct, + input [2:0] io_alloc_bits_cmd_funct3, + input [4:0] io_alloc_bits_cmd_rs2, + io_alloc_bits_cmd_rs1, + input io_alloc_bits_cmd_xd, + io_alloc_bits_cmd_xs1, + io_alloc_bits_cmd_xs2, + input [4:0] io_alloc_bits_cmd_rd, + input [6:0] io_alloc_bits_cmd_opcode, + input [63:0] io_alloc_bits_cmd_rs1Data, + io_alloc_bits_cmd_rs2Data, + input io_alloc_bits_bankAccess_rd_bank_0_valid, + input [9:0] io_alloc_bits_bankAccess_rd_bank_0_id, + input io_alloc_bits_bankAccess_rd_bank_1_valid, + input [9:0] io_alloc_bits_bankAccess_rd_bank_1_id, + input io_alloc_bits_bankAccess_wr_bank_valid, + input [9:0] io_alloc_bits_bankAccess_wr_bank_id, + input io_alloc_bits_isFence, + io_alloc_bits_isBarrier, + io_issue_ready, + output io_issue_valid, + output [3:0] io_issue_bits_cmd_domain_id, + output [4:0] io_issue_bits_cmd_ball_bid, + output [31:0] io_issue_bits_cmd_cmd_raw_inst, + output [63:0] io_issue_bits_cmd_cmd_pc, + output [6:0] io_issue_bits_cmd_cmd_funct, + output [2:0] io_issue_bits_cmd_cmd_funct3, + output [4:0] io_issue_bits_cmd_cmd_rs2, + io_issue_bits_cmd_cmd_rs1, + output io_issue_bits_cmd_cmd_xd, + io_issue_bits_cmd_cmd_xs1, + io_issue_bits_cmd_cmd_xs2, + output [4:0] io_issue_bits_cmd_cmd_rd, + output [6:0] io_issue_bits_cmd_cmd_opcode, + output [63:0] io_issue_bits_cmd_cmd_rs1Data, + io_issue_bits_cmd_cmd_rs2Data, + output io_issue_bits_cmd_bankAccess_rd_bank_0_valid, + output [9:0] io_issue_bits_cmd_bankAccess_rd_bank_0_id, + output io_issue_bits_cmd_bankAccess_rd_bank_1_valid, + output [9:0] io_issue_bits_cmd_bankAccess_rd_bank_1_id, + output io_issue_bits_cmd_bankAccess_wr_bank_valid, + output [9:0] io_issue_bits_cmd_bankAccess_wr_bank_id, + output [3:0] io_issue_bits_cmd_op1_col, + io_issue_bits_cmd_op2_col, + io_issue_bits_cmd_wr_col, + output io_issue_bits_cmd_isFence, + io_issue_bits_cmd_isBarrier, + io_issue_bits_renamedBankAccess_rd_bank_0_valid, + output [9:0] io_issue_bits_renamedBankAccess_rd_bank_0_id, + output io_issue_bits_renamedBankAccess_rd_bank_1_valid, + output [9:0] io_issue_bits_renamedBankAccess_rd_bank_1_id, + output io_issue_bits_renamedBankAccess_wr_bank_valid, + output [9:0] io_issue_bits_renamedBankAccess_wr_bank_id, + output [3:0] io_issue_bits_rob_id, + input io_complete_valid, + input [3:0] io_complete_bits, + output io_empty, + io_full, + output [3:0] io_head_ptr, + output [4:0] io_issued_count, + output io_entry_valid_0, + io_entry_valid_1, + io_entry_valid_2, + io_entry_valid_3, + io_entry_valid_4, + io_entry_valid_5, + io_entry_valid_6, + io_entry_valid_7, + io_entry_valid_8, + io_entry_valid_9, + io_entry_valid_10, + io_entry_valid_11, + io_entry_valid_12, + io_entry_valid_13, + io_entry_valid_14, + io_entry_valid_15, + io_entry_complete_0, + io_entry_complete_1, + io_entry_complete_2, + io_entry_complete_3, + io_entry_complete_4, + io_entry_complete_5, + io_entry_complete_6, + io_entry_complete_7, + io_entry_complete_8, + io_entry_complete_9, + io_entry_complete_10, + io_entry_complete_11, + io_entry_complete_12, + io_entry_complete_13, + io_entry_complete_14, + io_entry_complete_15, + input io_subRobActive, + output [63:0] io_inst_ids_0, + io_inst_ids_1, + io_inst_ids_2, + io_inst_ids_3, + io_inst_ids_4, + io_inst_ids_5, + io_inst_ids_6, + io_inst_ids_7, + io_inst_ids_8, + io_inst_ids_9, + io_inst_ids_10, + io_inst_ids_11, + io_inst_ids_12, + io_inst_ids_13, + io_inst_ids_14, + io_inst_ids_15 +); + + wire commitMask_15; + wire commitMask_14; + wire commitMask_13; + wire commitMask_12; + wire commitMask_11; + wire commitMask_10; + wire commitMask_9; + wire commitMask_8; + wire commitMask_7; + wire commitMask_6; + wire commitMask_5; + wire commitMask_4; + wire commitMask_3; + wire commitMask_2; + wire commitMask_1; + wire commitMask_0; + wire _scoreboard_hazardVec_0; + wire _scoreboard_hazardVec_1; + wire _scoreboard_hazardVec_2; + wire _scoreboard_hazardVec_3; + wire _scoreboard_hazardVec_4; + wire _scoreboard_hazardVec_5; + wire _scoreboard_hazardVec_6; + wire _scoreboard_hazardVec_7; + wire _scoreboard_hazardVec_8; + wire _scoreboard_hazardVec_9; + wire _scoreboard_hazardVec_10; + wire _scoreboard_hazardVec_11; + wire _scoreboard_hazardVec_12; + wire _scoreboard_hazardVec_13; + wire _scoreboard_hazardVec_14; + wire _scoreboard_hazardVec_15; + wire _bat_io_alloc_renamed_rd_bank_0_valid; + wire [9:0] _bat_io_alloc_renamed_rd_bank_0_id; + wire _bat_io_alloc_renamed_rd_bank_1_valid; + wire [9:0] _bat_io_alloc_renamed_rd_bank_1_id; + wire _bat_io_alloc_renamed_wr_bank_valid; + wire [9:0] _bat_io_alloc_renamed_wr_bank_id; + reg [3:0] robEntries_0_cmd_domain_id; + reg [4:0] robEntries_0_cmd_ball_bid; + reg [31:0] robEntries_0_cmd_cmd_raw_inst; + reg [63:0] robEntries_0_cmd_cmd_pc; + reg [6:0] robEntries_0_cmd_cmd_funct; + reg [2:0] robEntries_0_cmd_cmd_funct3; + reg [4:0] robEntries_0_cmd_cmd_rs2; + reg [4:0] robEntries_0_cmd_cmd_rs1; + reg robEntries_0_cmd_cmd_xd; + reg robEntries_0_cmd_cmd_xs1; + reg robEntries_0_cmd_cmd_xs2; + reg [4:0] robEntries_0_cmd_cmd_rd; + reg [6:0] robEntries_0_cmd_cmd_opcode; + reg [63:0] robEntries_0_cmd_cmd_rs1Data; + reg [63:0] robEntries_0_cmd_cmd_rs2Data; + reg robEntries_0_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_0_cmd_bankAccess_rd_bank_0_id; + reg robEntries_0_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_0_cmd_bankAccess_rd_bank_1_id; + reg robEntries_0_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_0_cmd_bankAccess_wr_bank_id; + reg robEntries_0_cmd_isFence; + reg robEntries_0_cmd_isBarrier; + reg robEntries_0_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_0_renamedBankAccess_rd_bank_0_id; + reg robEntries_0_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_0_renamedBankAccess_rd_bank_1_id; + reg robEntries_0_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_0_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_0_rob_id; + reg [3:0] robEntries_1_cmd_domain_id; + reg [4:0] robEntries_1_cmd_ball_bid; + reg [31:0] robEntries_1_cmd_cmd_raw_inst; + reg [63:0] robEntries_1_cmd_cmd_pc; + reg [6:0] robEntries_1_cmd_cmd_funct; + reg [2:0] robEntries_1_cmd_cmd_funct3; + reg [4:0] robEntries_1_cmd_cmd_rs2; + reg [4:0] robEntries_1_cmd_cmd_rs1; + reg robEntries_1_cmd_cmd_xd; + reg robEntries_1_cmd_cmd_xs1; + reg robEntries_1_cmd_cmd_xs2; + reg [4:0] robEntries_1_cmd_cmd_rd; + reg [6:0] robEntries_1_cmd_cmd_opcode; + reg [63:0] robEntries_1_cmd_cmd_rs1Data; + reg [63:0] robEntries_1_cmd_cmd_rs2Data; + reg robEntries_1_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_1_cmd_bankAccess_rd_bank_0_id; + reg robEntries_1_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_1_cmd_bankAccess_rd_bank_1_id; + reg robEntries_1_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_1_cmd_bankAccess_wr_bank_id; + reg robEntries_1_cmd_isFence; + reg robEntries_1_cmd_isBarrier; + reg robEntries_1_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_1_renamedBankAccess_rd_bank_0_id; + reg robEntries_1_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_1_renamedBankAccess_rd_bank_1_id; + reg robEntries_1_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_1_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_1_rob_id; + reg [3:0] robEntries_2_cmd_domain_id; + reg [4:0] robEntries_2_cmd_ball_bid; + reg [31:0] robEntries_2_cmd_cmd_raw_inst; + reg [63:0] robEntries_2_cmd_cmd_pc; + reg [6:0] robEntries_2_cmd_cmd_funct; + reg [2:0] robEntries_2_cmd_cmd_funct3; + reg [4:0] robEntries_2_cmd_cmd_rs2; + reg [4:0] robEntries_2_cmd_cmd_rs1; + reg robEntries_2_cmd_cmd_xd; + reg robEntries_2_cmd_cmd_xs1; + reg robEntries_2_cmd_cmd_xs2; + reg [4:0] robEntries_2_cmd_cmd_rd; + reg [6:0] robEntries_2_cmd_cmd_opcode; + reg [63:0] robEntries_2_cmd_cmd_rs1Data; + reg [63:0] robEntries_2_cmd_cmd_rs2Data; + reg robEntries_2_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_2_cmd_bankAccess_rd_bank_0_id; + reg robEntries_2_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_2_cmd_bankAccess_rd_bank_1_id; + reg robEntries_2_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_2_cmd_bankAccess_wr_bank_id; + reg robEntries_2_cmd_isFence; + reg robEntries_2_cmd_isBarrier; + reg robEntries_2_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_2_renamedBankAccess_rd_bank_0_id; + reg robEntries_2_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_2_renamedBankAccess_rd_bank_1_id; + reg robEntries_2_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_2_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_2_rob_id; + reg [3:0] robEntries_3_cmd_domain_id; + reg [4:0] robEntries_3_cmd_ball_bid; + reg [31:0] robEntries_3_cmd_cmd_raw_inst; + reg [63:0] robEntries_3_cmd_cmd_pc; + reg [6:0] robEntries_3_cmd_cmd_funct; + reg [2:0] robEntries_3_cmd_cmd_funct3; + reg [4:0] robEntries_3_cmd_cmd_rs2; + reg [4:0] robEntries_3_cmd_cmd_rs1; + reg robEntries_3_cmd_cmd_xd; + reg robEntries_3_cmd_cmd_xs1; + reg robEntries_3_cmd_cmd_xs2; + reg [4:0] robEntries_3_cmd_cmd_rd; + reg [6:0] robEntries_3_cmd_cmd_opcode; + reg [63:0] robEntries_3_cmd_cmd_rs1Data; + reg [63:0] robEntries_3_cmd_cmd_rs2Data; + reg robEntries_3_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_3_cmd_bankAccess_rd_bank_0_id; + reg robEntries_3_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_3_cmd_bankAccess_rd_bank_1_id; + reg robEntries_3_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_3_cmd_bankAccess_wr_bank_id; + reg robEntries_3_cmd_isFence; + reg robEntries_3_cmd_isBarrier; + reg robEntries_3_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_3_renamedBankAccess_rd_bank_0_id; + reg robEntries_3_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_3_renamedBankAccess_rd_bank_1_id; + reg robEntries_3_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_3_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_3_rob_id; + reg [3:0] robEntries_4_cmd_domain_id; + reg [4:0] robEntries_4_cmd_ball_bid; + reg [31:0] robEntries_4_cmd_cmd_raw_inst; + reg [63:0] robEntries_4_cmd_cmd_pc; + reg [6:0] robEntries_4_cmd_cmd_funct; + reg [2:0] robEntries_4_cmd_cmd_funct3; + reg [4:0] robEntries_4_cmd_cmd_rs2; + reg [4:0] robEntries_4_cmd_cmd_rs1; + reg robEntries_4_cmd_cmd_xd; + reg robEntries_4_cmd_cmd_xs1; + reg robEntries_4_cmd_cmd_xs2; + reg [4:0] robEntries_4_cmd_cmd_rd; + reg [6:0] robEntries_4_cmd_cmd_opcode; + reg [63:0] robEntries_4_cmd_cmd_rs1Data; + reg [63:0] robEntries_4_cmd_cmd_rs2Data; + reg robEntries_4_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_4_cmd_bankAccess_rd_bank_0_id; + reg robEntries_4_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_4_cmd_bankAccess_rd_bank_1_id; + reg robEntries_4_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_4_cmd_bankAccess_wr_bank_id; + reg robEntries_4_cmd_isFence; + reg robEntries_4_cmd_isBarrier; + reg robEntries_4_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_4_renamedBankAccess_rd_bank_0_id; + reg robEntries_4_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_4_renamedBankAccess_rd_bank_1_id; + reg robEntries_4_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_4_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_4_rob_id; + reg [3:0] robEntries_5_cmd_domain_id; + reg [4:0] robEntries_5_cmd_ball_bid; + reg [31:0] robEntries_5_cmd_cmd_raw_inst; + reg [63:0] robEntries_5_cmd_cmd_pc; + reg [6:0] robEntries_5_cmd_cmd_funct; + reg [2:0] robEntries_5_cmd_cmd_funct3; + reg [4:0] robEntries_5_cmd_cmd_rs2; + reg [4:0] robEntries_5_cmd_cmd_rs1; + reg robEntries_5_cmd_cmd_xd; + reg robEntries_5_cmd_cmd_xs1; + reg robEntries_5_cmd_cmd_xs2; + reg [4:0] robEntries_5_cmd_cmd_rd; + reg [6:0] robEntries_5_cmd_cmd_opcode; + reg [63:0] robEntries_5_cmd_cmd_rs1Data; + reg [63:0] robEntries_5_cmd_cmd_rs2Data; + reg robEntries_5_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_5_cmd_bankAccess_rd_bank_0_id; + reg robEntries_5_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_5_cmd_bankAccess_rd_bank_1_id; + reg robEntries_5_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_5_cmd_bankAccess_wr_bank_id; + reg robEntries_5_cmd_isFence; + reg robEntries_5_cmd_isBarrier; + reg robEntries_5_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_5_renamedBankAccess_rd_bank_0_id; + reg robEntries_5_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_5_renamedBankAccess_rd_bank_1_id; + reg robEntries_5_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_5_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_5_rob_id; + reg [3:0] robEntries_6_cmd_domain_id; + reg [4:0] robEntries_6_cmd_ball_bid; + reg [31:0] robEntries_6_cmd_cmd_raw_inst; + reg [63:0] robEntries_6_cmd_cmd_pc; + reg [6:0] robEntries_6_cmd_cmd_funct; + reg [2:0] robEntries_6_cmd_cmd_funct3; + reg [4:0] robEntries_6_cmd_cmd_rs2; + reg [4:0] robEntries_6_cmd_cmd_rs1; + reg robEntries_6_cmd_cmd_xd; + reg robEntries_6_cmd_cmd_xs1; + reg robEntries_6_cmd_cmd_xs2; + reg [4:0] robEntries_6_cmd_cmd_rd; + reg [6:0] robEntries_6_cmd_cmd_opcode; + reg [63:0] robEntries_6_cmd_cmd_rs1Data; + reg [63:0] robEntries_6_cmd_cmd_rs2Data; + reg robEntries_6_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_6_cmd_bankAccess_rd_bank_0_id; + reg robEntries_6_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_6_cmd_bankAccess_rd_bank_1_id; + reg robEntries_6_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_6_cmd_bankAccess_wr_bank_id; + reg robEntries_6_cmd_isFence; + reg robEntries_6_cmd_isBarrier; + reg robEntries_6_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_6_renamedBankAccess_rd_bank_0_id; + reg robEntries_6_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_6_renamedBankAccess_rd_bank_1_id; + reg robEntries_6_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_6_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_6_rob_id; + reg [3:0] robEntries_7_cmd_domain_id; + reg [4:0] robEntries_7_cmd_ball_bid; + reg [31:0] robEntries_7_cmd_cmd_raw_inst; + reg [63:0] robEntries_7_cmd_cmd_pc; + reg [6:0] robEntries_7_cmd_cmd_funct; + reg [2:0] robEntries_7_cmd_cmd_funct3; + reg [4:0] robEntries_7_cmd_cmd_rs2; + reg [4:0] robEntries_7_cmd_cmd_rs1; + reg robEntries_7_cmd_cmd_xd; + reg robEntries_7_cmd_cmd_xs1; + reg robEntries_7_cmd_cmd_xs2; + reg [4:0] robEntries_7_cmd_cmd_rd; + reg [6:0] robEntries_7_cmd_cmd_opcode; + reg [63:0] robEntries_7_cmd_cmd_rs1Data; + reg [63:0] robEntries_7_cmd_cmd_rs2Data; + reg robEntries_7_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_7_cmd_bankAccess_rd_bank_0_id; + reg robEntries_7_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_7_cmd_bankAccess_rd_bank_1_id; + reg robEntries_7_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_7_cmd_bankAccess_wr_bank_id; + reg robEntries_7_cmd_isFence; + reg robEntries_7_cmd_isBarrier; + reg robEntries_7_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_7_renamedBankAccess_rd_bank_0_id; + reg robEntries_7_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_7_renamedBankAccess_rd_bank_1_id; + reg robEntries_7_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_7_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_7_rob_id; + reg [3:0] robEntries_8_cmd_domain_id; + reg [4:0] robEntries_8_cmd_ball_bid; + reg [31:0] robEntries_8_cmd_cmd_raw_inst; + reg [63:0] robEntries_8_cmd_cmd_pc; + reg [6:0] robEntries_8_cmd_cmd_funct; + reg [2:0] robEntries_8_cmd_cmd_funct3; + reg [4:0] robEntries_8_cmd_cmd_rs2; + reg [4:0] robEntries_8_cmd_cmd_rs1; + reg robEntries_8_cmd_cmd_xd; + reg robEntries_8_cmd_cmd_xs1; + reg robEntries_8_cmd_cmd_xs2; + reg [4:0] robEntries_8_cmd_cmd_rd; + reg [6:0] robEntries_8_cmd_cmd_opcode; + reg [63:0] robEntries_8_cmd_cmd_rs1Data; + reg [63:0] robEntries_8_cmd_cmd_rs2Data; + reg robEntries_8_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_8_cmd_bankAccess_rd_bank_0_id; + reg robEntries_8_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_8_cmd_bankAccess_rd_bank_1_id; + reg robEntries_8_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_8_cmd_bankAccess_wr_bank_id; + reg robEntries_8_cmd_isFence; + reg robEntries_8_cmd_isBarrier; + reg robEntries_8_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_8_renamedBankAccess_rd_bank_0_id; + reg robEntries_8_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_8_renamedBankAccess_rd_bank_1_id; + reg robEntries_8_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_8_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_8_rob_id; + reg [3:0] robEntries_9_cmd_domain_id; + reg [4:0] robEntries_9_cmd_ball_bid; + reg [31:0] robEntries_9_cmd_cmd_raw_inst; + reg [63:0] robEntries_9_cmd_cmd_pc; + reg [6:0] robEntries_9_cmd_cmd_funct; + reg [2:0] robEntries_9_cmd_cmd_funct3; + reg [4:0] robEntries_9_cmd_cmd_rs2; + reg [4:0] robEntries_9_cmd_cmd_rs1; + reg robEntries_9_cmd_cmd_xd; + reg robEntries_9_cmd_cmd_xs1; + reg robEntries_9_cmd_cmd_xs2; + reg [4:0] robEntries_9_cmd_cmd_rd; + reg [6:0] robEntries_9_cmd_cmd_opcode; + reg [63:0] robEntries_9_cmd_cmd_rs1Data; + reg [63:0] robEntries_9_cmd_cmd_rs2Data; + reg robEntries_9_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_9_cmd_bankAccess_rd_bank_0_id; + reg robEntries_9_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_9_cmd_bankAccess_rd_bank_1_id; + reg robEntries_9_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_9_cmd_bankAccess_wr_bank_id; + reg robEntries_9_cmd_isFence; + reg robEntries_9_cmd_isBarrier; + reg robEntries_9_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_9_renamedBankAccess_rd_bank_0_id; + reg robEntries_9_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_9_renamedBankAccess_rd_bank_1_id; + reg robEntries_9_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_9_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_9_rob_id; + reg [3:0] robEntries_10_cmd_domain_id; + reg [4:0] robEntries_10_cmd_ball_bid; + reg [31:0] robEntries_10_cmd_cmd_raw_inst; + reg [63:0] robEntries_10_cmd_cmd_pc; + reg [6:0] robEntries_10_cmd_cmd_funct; + reg [2:0] robEntries_10_cmd_cmd_funct3; + reg [4:0] robEntries_10_cmd_cmd_rs2; + reg [4:0] robEntries_10_cmd_cmd_rs1; + reg robEntries_10_cmd_cmd_xd; + reg robEntries_10_cmd_cmd_xs1; + reg robEntries_10_cmd_cmd_xs2; + reg [4:0] robEntries_10_cmd_cmd_rd; + reg [6:0] robEntries_10_cmd_cmd_opcode; + reg [63:0] robEntries_10_cmd_cmd_rs1Data; + reg [63:0] robEntries_10_cmd_cmd_rs2Data; + reg robEntries_10_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_10_cmd_bankAccess_rd_bank_0_id; + reg robEntries_10_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_10_cmd_bankAccess_rd_bank_1_id; + reg robEntries_10_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_10_cmd_bankAccess_wr_bank_id; + reg robEntries_10_cmd_isFence; + reg robEntries_10_cmd_isBarrier; + reg robEntries_10_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_10_renamedBankAccess_rd_bank_0_id; + reg robEntries_10_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_10_renamedBankAccess_rd_bank_1_id; + reg robEntries_10_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_10_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_10_rob_id; + reg [3:0] robEntries_11_cmd_domain_id; + reg [4:0] robEntries_11_cmd_ball_bid; + reg [31:0] robEntries_11_cmd_cmd_raw_inst; + reg [63:0] robEntries_11_cmd_cmd_pc; + reg [6:0] robEntries_11_cmd_cmd_funct; + reg [2:0] robEntries_11_cmd_cmd_funct3; + reg [4:0] robEntries_11_cmd_cmd_rs2; + reg [4:0] robEntries_11_cmd_cmd_rs1; + reg robEntries_11_cmd_cmd_xd; + reg robEntries_11_cmd_cmd_xs1; + reg robEntries_11_cmd_cmd_xs2; + reg [4:0] robEntries_11_cmd_cmd_rd; + reg [6:0] robEntries_11_cmd_cmd_opcode; + reg [63:0] robEntries_11_cmd_cmd_rs1Data; + reg [63:0] robEntries_11_cmd_cmd_rs2Data; + reg robEntries_11_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_11_cmd_bankAccess_rd_bank_0_id; + reg robEntries_11_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_11_cmd_bankAccess_rd_bank_1_id; + reg robEntries_11_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_11_cmd_bankAccess_wr_bank_id; + reg robEntries_11_cmd_isFence; + reg robEntries_11_cmd_isBarrier; + reg robEntries_11_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_11_renamedBankAccess_rd_bank_0_id; + reg robEntries_11_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_11_renamedBankAccess_rd_bank_1_id; + reg robEntries_11_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_11_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_11_rob_id; + reg [3:0] robEntries_12_cmd_domain_id; + reg [4:0] robEntries_12_cmd_ball_bid; + reg [31:0] robEntries_12_cmd_cmd_raw_inst; + reg [63:0] robEntries_12_cmd_cmd_pc; + reg [6:0] robEntries_12_cmd_cmd_funct; + reg [2:0] robEntries_12_cmd_cmd_funct3; + reg [4:0] robEntries_12_cmd_cmd_rs2; + reg [4:0] robEntries_12_cmd_cmd_rs1; + reg robEntries_12_cmd_cmd_xd; + reg robEntries_12_cmd_cmd_xs1; + reg robEntries_12_cmd_cmd_xs2; + reg [4:0] robEntries_12_cmd_cmd_rd; + reg [6:0] robEntries_12_cmd_cmd_opcode; + reg [63:0] robEntries_12_cmd_cmd_rs1Data; + reg [63:0] robEntries_12_cmd_cmd_rs2Data; + reg robEntries_12_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_12_cmd_bankAccess_rd_bank_0_id; + reg robEntries_12_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_12_cmd_bankAccess_rd_bank_1_id; + reg robEntries_12_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_12_cmd_bankAccess_wr_bank_id; + reg robEntries_12_cmd_isFence; + reg robEntries_12_cmd_isBarrier; + reg robEntries_12_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_12_renamedBankAccess_rd_bank_0_id; + reg robEntries_12_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_12_renamedBankAccess_rd_bank_1_id; + reg robEntries_12_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_12_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_12_rob_id; + reg [3:0] robEntries_13_cmd_domain_id; + reg [4:0] robEntries_13_cmd_ball_bid; + reg [31:0] robEntries_13_cmd_cmd_raw_inst; + reg [63:0] robEntries_13_cmd_cmd_pc; + reg [6:0] robEntries_13_cmd_cmd_funct; + reg [2:0] robEntries_13_cmd_cmd_funct3; + reg [4:0] robEntries_13_cmd_cmd_rs2; + reg [4:0] robEntries_13_cmd_cmd_rs1; + reg robEntries_13_cmd_cmd_xd; + reg robEntries_13_cmd_cmd_xs1; + reg robEntries_13_cmd_cmd_xs2; + reg [4:0] robEntries_13_cmd_cmd_rd; + reg [6:0] robEntries_13_cmd_cmd_opcode; + reg [63:0] robEntries_13_cmd_cmd_rs1Data; + reg [63:0] robEntries_13_cmd_cmd_rs2Data; + reg robEntries_13_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_13_cmd_bankAccess_rd_bank_0_id; + reg robEntries_13_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_13_cmd_bankAccess_rd_bank_1_id; + reg robEntries_13_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_13_cmd_bankAccess_wr_bank_id; + reg robEntries_13_cmd_isFence; + reg robEntries_13_cmd_isBarrier; + reg robEntries_13_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_13_renamedBankAccess_rd_bank_0_id; + reg robEntries_13_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_13_renamedBankAccess_rd_bank_1_id; + reg robEntries_13_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_13_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_13_rob_id; + reg [3:0] robEntries_14_cmd_domain_id; + reg [4:0] robEntries_14_cmd_ball_bid; + reg [31:0] robEntries_14_cmd_cmd_raw_inst; + reg [63:0] robEntries_14_cmd_cmd_pc; + reg [6:0] robEntries_14_cmd_cmd_funct; + reg [2:0] robEntries_14_cmd_cmd_funct3; + reg [4:0] robEntries_14_cmd_cmd_rs2; + reg [4:0] robEntries_14_cmd_cmd_rs1; + reg robEntries_14_cmd_cmd_xd; + reg robEntries_14_cmd_cmd_xs1; + reg robEntries_14_cmd_cmd_xs2; + reg [4:0] robEntries_14_cmd_cmd_rd; + reg [6:0] robEntries_14_cmd_cmd_opcode; + reg [63:0] robEntries_14_cmd_cmd_rs1Data; + reg [63:0] robEntries_14_cmd_cmd_rs2Data; + reg robEntries_14_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_14_cmd_bankAccess_rd_bank_0_id; + reg robEntries_14_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_14_cmd_bankAccess_rd_bank_1_id; + reg robEntries_14_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_14_cmd_bankAccess_wr_bank_id; + reg robEntries_14_cmd_isFence; + reg robEntries_14_cmd_isBarrier; + reg robEntries_14_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_14_renamedBankAccess_rd_bank_0_id; + reg robEntries_14_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_14_renamedBankAccess_rd_bank_1_id; + reg robEntries_14_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_14_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_14_rob_id; + reg [3:0] robEntries_15_cmd_domain_id; + reg [4:0] robEntries_15_cmd_ball_bid; + reg [31:0] robEntries_15_cmd_cmd_raw_inst; + reg [63:0] robEntries_15_cmd_cmd_pc; + reg [6:0] robEntries_15_cmd_cmd_funct; + reg [2:0] robEntries_15_cmd_cmd_funct3; + reg [4:0] robEntries_15_cmd_cmd_rs2; + reg [4:0] robEntries_15_cmd_cmd_rs1; + reg robEntries_15_cmd_cmd_xd; + reg robEntries_15_cmd_cmd_xs1; + reg robEntries_15_cmd_cmd_xs2; + reg [4:0] robEntries_15_cmd_cmd_rd; + reg [6:0] robEntries_15_cmd_cmd_opcode; + reg [63:0] robEntries_15_cmd_cmd_rs1Data; + reg [63:0] robEntries_15_cmd_cmd_rs2Data; + reg robEntries_15_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_15_cmd_bankAccess_rd_bank_0_id; + reg robEntries_15_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_15_cmd_bankAccess_rd_bank_1_id; + reg robEntries_15_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_15_cmd_bankAccess_wr_bank_id; + reg robEntries_15_cmd_isFence; + reg robEntries_15_cmd_isBarrier; + reg robEntries_15_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_15_renamedBankAccess_rd_bank_0_id; + reg robEntries_15_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_15_renamedBankAccess_rd_bank_1_id; + reg robEntries_15_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_15_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_15_rob_id; + reg robValid_0; + reg robValid_1; + reg robValid_2; + reg robValid_3; + reg robValid_4; + reg robValid_5; + reg robValid_6; + reg robValid_7; + reg robValid_8; + reg robValid_9; + reg robValid_10; + reg robValid_11; + reg robValid_12; + reg robValid_13; + reg robValid_14; + reg robValid_15; + reg robIssued_0; + reg robIssued_1; + reg robIssued_2; + reg robIssued_3; + reg robIssued_4; + reg robIssued_5; + reg robIssued_6; + reg robIssued_7; + reg robIssued_8; + reg robIssued_9; + reg robIssued_10; + reg robIssued_11; + reg robIssued_12; + reg robIssued_13; + reg robIssued_14; + reg robIssued_15; + reg robComplete_0; + reg robComplete_1; + reg robComplete_2; + reg robComplete_3; + reg robComplete_4; + reg robComplete_5; + reg robComplete_6; + reg robComplete_7; + reg robComplete_8; + reg robComplete_9; + reg robComplete_10; + reg robComplete_11; + reg robComplete_12; + reg robComplete_13; + reg robComplete_14; + reg robComplete_15; + reg [63:0] instIds_0; + reg [63:0] instIds_1; + reg [63:0] instIds_2; + reg [63:0] instIds_3; + reg [63:0] instIds_4; + reg [63:0] instIds_5; + reg [63:0] instIds_6; + reg [63:0] instIds_7; + reg [63:0] instIds_8; + reg [63:0] instIds_9; + reg [63:0] instIds_10; + reg [63:0] instIds_11; + reg [63:0] instIds_12; + reg [63:0] instIds_13; + reg [63:0] instIds_14; + reg [63:0] instIds_15; + reg [63:0] nextInstId; + reg [3:0] ptr; + reg [3:0] tailPtr; + reg [4:0] issuedCount; + reg [3:0] bankCols_0; + reg [3:0] bankCols_1; + reg [3:0] bankCols_2; + reg [3:0] bankCols_3; + reg [3:0] bankCols_4; + reg [3:0] bankCols_5; + reg [3:0] bankCols_6; + reg [3:0] bankCols_7; + reg [3:0] bankCols_8; + reg [3:0] bankCols_9; + reg [3:0] bankCols_10; + reg [3:0] bankCols_11; + reg [3:0] bankCols_12; + reg [3:0] bankCols_13; + reg [3:0] bankCols_14; + reg [3:0] bankCols_15; + reg [15:0] vbankBusy; + reg [15:0] dependencyMask_0; + reg [15:0] dependencyMask_1; + reg [15:0] dependencyMask_2; + reg [15:0] dependencyMask_3; + reg [15:0] dependencyMask_4; + reg [15:0] dependencyMask_5; + reg [15:0] dependencyMask_6; + reg [15:0] dependencyMask_7; + reg [15:0] dependencyMask_8; + reg [15:0] dependencyMask_9; + reg [15:0] dependencyMask_10; + reg [15:0] dependencyMask_11; + reg [15:0] dependencyMask_12; + reg [15:0] dependencyMask_13; + reg [15:0] dependencyMask_14; + reg [15:0] dependencyMask_15; + wire _isFull_T = ptr == tailPtr; + wire [15:0] _GEN = + {{robValid_15}, + {robValid_14}, + {robValid_13}, + {robValid_12}, + {robValid_11}, + {robValid_10}, + {robValid_9}, + {robValid_8}, + {robValid_7}, + {robValid_6}, + {robValid_5}, + {robValid_4}, + {robValid_3}, + {robValid_2}, + {robValid_1}, + {robValid_0}}; + wire _GEN_0 = _GEN[ptr]; + wire isFull = _isFull_T & _GEN_0; + wire [15:0] _GEN_1 = + {{robComplete_15}, + {robComplete_14}, + {robComplete_13}, + {robComplete_12}, + {robComplete_11}, + {robComplete_10}, + {robComplete_9}, + {robComplete_8}, + {robComplete_7}, + {robComplete_6}, + {robComplete_5}, + {robComplete_4}, + {robComplete_3}, + {robComplete_2}, + {robComplete_1}, + {robComplete_0}}; + wire _GEN_2 = _GEN_1[ptr]; + wire commitKeep_1 = _GEN_0 & _GEN_2; + wire [3:0] _hits_ptr_T_1446 = ptr + 4'h1; + wire commitKeep_2 = + commitKeep_1 & _GEN[_hits_ptr_T_1446] & _GEN_1[_hits_ptr_T_1446]; + wire [3:0] _hits_ptr_T_1452 = ptr + 4'h2; + wire commitKeep_3 = + commitKeep_2 & _GEN[_hits_ptr_T_1452] & _GEN_1[_hits_ptr_T_1452]; + wire [3:0] _hits_ptr_T_1458 = ptr + 4'h3; + wire commitKeep_4 = + commitKeep_3 & _GEN[_hits_ptr_T_1458] & _GEN_1[_hits_ptr_T_1458]; + wire [3:0] _hits_ptr_T_1464 = ptr + 4'h4; + wire commitKeep_5 = + commitKeep_4 & _GEN[_hits_ptr_T_1464] & _GEN_1[_hits_ptr_T_1464]; + wire [3:0] _hits_ptr_T_1470 = ptr + 4'h5; + wire commitKeep_6 = + commitKeep_5 & _GEN[_hits_ptr_T_1470] & _GEN_1[_hits_ptr_T_1470]; + wire [3:0] _hits_ptr_T_1476 = ptr + 4'h6; + wire commitKeep_7 = + commitKeep_6 & _GEN[_hits_ptr_T_1476] & _GEN_1[_hits_ptr_T_1476]; + wire [3:0] _hits_ptr_T_1482 = ptr + 4'h7; + wire commitKeep_8 = + commitKeep_7 & _GEN[_hits_ptr_T_1482] & _GEN_1[_hits_ptr_T_1482]; + wire [3:0] _hits_ptr_T_1488 = ptr - 4'h8; + wire commitKeep_9 = + commitKeep_8 & _GEN[_hits_ptr_T_1488] & _GEN_1[_hits_ptr_T_1488]; + wire [3:0] _hits_ptr_T_1494 = ptr - 4'h7; + wire commitScan_9 = + commitKeep_9 & _GEN[_hits_ptr_T_1494] & _GEN_1[_hits_ptr_T_1494]; + wire [3:0] _hits_ptr_T_1500 = ptr - 4'h6; + wire commitKeep_11 = + commitScan_9 & _GEN[_hits_ptr_T_1500] & _GEN_1[_hits_ptr_T_1500]; + wire [3:0] _hits_ptr_T_1506 = ptr - 4'h5; + wire commitKeep_12 = + commitKeep_11 & _GEN[_hits_ptr_T_1506] & _GEN_1[_hits_ptr_T_1506]; + wire [3:0] _hits_ptr_T_1512 = ptr - 4'h4; + wire commitKeep_13 = + commitKeep_12 & _GEN[_hits_ptr_T_1512] & _GEN_1[_hits_ptr_T_1512]; + wire [3:0] _hits_ptr_T_1518 = ptr - 4'h3; + wire commitKeep_14 = + commitKeep_13 & _GEN[_hits_ptr_T_1518] & _GEN_1[_hits_ptr_T_1518]; + wire [3:0] _hits_ptr_T_1524 = ptr - 4'h2; + wire commitKeep_15 = + commitKeep_14 & _GEN[_hits_ptr_T_1524] & _GEN_1[_hits_ptr_T_1524]; + wire [3:0] _hits_ptr_T_1530 = ptr - 4'h1; + wire commitScan_15 = + commitKeep_15 & _GEN[_hits_ptr_T_1530] & _GEN_1[_hits_ptr_T_1530]; + wire [9:0] _tailAlias_T = {6'h0, tailPtr} + 10'h10; + wire io_alloc_ready_0 = + ~isFull + & {commitScan_15, + commitKeep_15, + commitKeep_14, + commitKeep_13, + commitKeep_12, + commitKeep_11, + commitScan_9, + commitKeep_9, + commitKeep_8, + commitKeep_7, + commitKeep_6, + commitKeep_5, + commitKeep_4, + commitKeep_3, + commitKeep_2, + commitKeep_1} == 16'h0 + & ~(robValid_15 & ~robComplete_15 + & (robEntries_15_renamedBankAccess_rd_bank_0_valid + & robEntries_15_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_15_renamedBankAccess_rd_bank_1_valid + & robEntries_15_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_15_renamedBankAccess_wr_bank_valid + & robEntries_15_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_14 + & ~robComplete_14 + & (robEntries_14_renamedBankAccess_rd_bank_0_valid + & robEntries_14_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_14_renamedBankAccess_rd_bank_1_valid + & robEntries_14_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_14_renamedBankAccess_wr_bank_valid + & robEntries_14_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_13 + & ~robComplete_13 + & (robEntries_13_renamedBankAccess_rd_bank_0_valid + & robEntries_13_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_13_renamedBankAccess_rd_bank_1_valid + & robEntries_13_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_13_renamedBankAccess_wr_bank_valid + & robEntries_13_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_12 + & ~robComplete_12 + & (robEntries_12_renamedBankAccess_rd_bank_0_valid + & robEntries_12_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_12_renamedBankAccess_rd_bank_1_valid + & robEntries_12_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_12_renamedBankAccess_wr_bank_valid + & robEntries_12_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_11 + & ~robComplete_11 + & (robEntries_11_renamedBankAccess_rd_bank_0_valid + & robEntries_11_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_11_renamedBankAccess_rd_bank_1_valid + & robEntries_11_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_11_renamedBankAccess_wr_bank_valid + & robEntries_11_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_10 + & ~robComplete_10 + & (robEntries_10_renamedBankAccess_rd_bank_0_valid + & robEntries_10_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_10_renamedBankAccess_rd_bank_1_valid + & robEntries_10_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_10_renamedBankAccess_wr_bank_valid + & robEntries_10_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_9 + & ~robComplete_9 + & (robEntries_9_renamedBankAccess_rd_bank_0_valid + & robEntries_9_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_9_renamedBankAccess_rd_bank_1_valid + & robEntries_9_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_9_renamedBankAccess_wr_bank_valid + & robEntries_9_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_8 + & ~robComplete_8 + & (robEntries_8_renamedBankAccess_rd_bank_0_valid + & robEntries_8_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_8_renamedBankAccess_rd_bank_1_valid + & robEntries_8_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_8_renamedBankAccess_wr_bank_valid + & robEntries_8_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_7 + & ~robComplete_7 + & (robEntries_7_renamedBankAccess_rd_bank_0_valid + & robEntries_7_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_7_renamedBankAccess_rd_bank_1_valid + & robEntries_7_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_7_renamedBankAccess_wr_bank_valid + & robEntries_7_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_6 + & ~robComplete_6 + & (robEntries_6_renamedBankAccess_rd_bank_0_valid + & robEntries_6_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_6_renamedBankAccess_rd_bank_1_valid + & robEntries_6_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_6_renamedBankAccess_wr_bank_valid + & robEntries_6_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_5 + & ~robComplete_5 + & (robEntries_5_renamedBankAccess_rd_bank_0_valid + & robEntries_5_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_5_renamedBankAccess_rd_bank_1_valid + & robEntries_5_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_5_renamedBankAccess_wr_bank_valid + & robEntries_5_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_4 + & ~robComplete_4 + & (robEntries_4_renamedBankAccess_rd_bank_0_valid + & robEntries_4_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_4_renamedBankAccess_rd_bank_1_valid + & robEntries_4_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_4_renamedBankAccess_wr_bank_valid + & robEntries_4_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_3 + & ~robComplete_3 + & (robEntries_3_renamedBankAccess_rd_bank_0_valid + & robEntries_3_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_3_renamedBankAccess_rd_bank_1_valid + & robEntries_3_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_3_renamedBankAccess_wr_bank_valid + & robEntries_3_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_2 + & ~robComplete_2 + & (robEntries_2_renamedBankAccess_rd_bank_0_valid + & robEntries_2_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_2_renamedBankAccess_rd_bank_1_valid + & robEntries_2_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_2_renamedBankAccess_wr_bank_valid + & robEntries_2_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_1 + & ~robComplete_1 + & (robEntries_1_renamedBankAccess_rd_bank_0_valid + & robEntries_1_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_1_renamedBankAccess_rd_bank_1_valid + & robEntries_1_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_1_renamedBankAccess_wr_bank_valid + & robEntries_1_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_0 + & ~robComplete_0 + & (robEntries_0_renamedBankAccess_rd_bank_0_valid + & robEntries_0_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_0_renamedBankAccess_rd_bank_1_valid + & robEntries_0_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_0_renamedBankAccess_wr_bank_valid + & robEntries_0_renamedBankAccess_wr_bank_id == _tailAlias_T)); + wire _isAllocatedSlot_T_30 = io_alloc_ready_0 & io_alloc_valid; + wire [15:0] entryRawWrites_0 = + robEntries_0_cmd_bankAccess_wr_bank_valid + & robEntries_0_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_0_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_1 = + robEntries_1_cmd_bankAccess_wr_bank_valid + & robEntries_1_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_1_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_2 = + robEntries_2_cmd_bankAccess_wr_bank_valid + & robEntries_2_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_2_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_3 = + robEntries_3_cmd_bankAccess_wr_bank_valid + & robEntries_3_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_3_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_4 = + robEntries_4_cmd_bankAccess_wr_bank_valid + & robEntries_4_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_4_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_5 = + robEntries_5_cmd_bankAccess_wr_bank_valid + & robEntries_5_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_5_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_6 = + robEntries_6_cmd_bankAccess_wr_bank_valid + & robEntries_6_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_6_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_7 = + robEntries_7_cmd_bankAccess_wr_bank_valid + & robEntries_7_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_7_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_8 = + robEntries_8_cmd_bankAccess_wr_bank_valid + & robEntries_8_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_8_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_9 = + robEntries_9_cmd_bankAccess_wr_bank_valid + & robEntries_9_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_9_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_10 = + robEntries_10_cmd_bankAccess_wr_bank_valid + & robEntries_10_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_10_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_11 = + robEntries_11_cmd_bankAccess_wr_bank_valid + & robEntries_11_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_11_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_12 = + robEntries_12_cmd_bankAccess_wr_bank_valid + & robEntries_12_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_12_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_13 = + robEntries_13_cmd_bankAccess_wr_bank_valid + & robEntries_13_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_13_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_14 = + robEntries_14_cmd_bankAccess_wr_bank_valid + & robEntries_14_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_14_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_15 = + robEntries_15_cmd_bankAccess_wr_bank_valid + & robEntries_15_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_15_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] olderUseMask = + (robEntries_0_cmd_bankAccess_rd_bank_0_valid + & robEntries_0_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_0_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_0_cmd_bankAccess_rd_bank_1_valid + & robEntries_0_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_0_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_0; + wire [15:0] vbankMasks_1 = + (robEntries_1_cmd_bankAccess_rd_bank_0_valid + & robEntries_1_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_1_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_1_cmd_bankAccess_rd_bank_1_valid + & robEntries_1_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_1_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_1; + wire [15:0] vbankMasks_2 = + (robEntries_2_cmd_bankAccess_rd_bank_0_valid + & robEntries_2_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_2_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_2_cmd_bankAccess_rd_bank_1_valid + & robEntries_2_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_2_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_2; + wire [15:0] vbankMasks_3 = + (robEntries_3_cmd_bankAccess_rd_bank_0_valid + & robEntries_3_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_3_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_3_cmd_bankAccess_rd_bank_1_valid + & robEntries_3_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_3_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_3; + wire [15:0] vbankMasks_4 = + (robEntries_4_cmd_bankAccess_rd_bank_0_valid + & robEntries_4_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_4_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_4_cmd_bankAccess_rd_bank_1_valid + & robEntries_4_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_4_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_4; + wire [15:0] vbankMasks_5 = + (robEntries_5_cmd_bankAccess_rd_bank_0_valid + & robEntries_5_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_5_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_5_cmd_bankAccess_rd_bank_1_valid + & robEntries_5_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_5_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_5; + wire [15:0] vbankMasks_6 = + (robEntries_6_cmd_bankAccess_rd_bank_0_valid + & robEntries_6_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_6_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_6_cmd_bankAccess_rd_bank_1_valid + & robEntries_6_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_6_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_6; + wire [15:0] vbankMasks_7 = + (robEntries_7_cmd_bankAccess_rd_bank_0_valid + & robEntries_7_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_7_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_7_cmd_bankAccess_rd_bank_1_valid + & robEntries_7_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_7_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_7; + wire [15:0] vbankMasks_8 = + (robEntries_8_cmd_bankAccess_rd_bank_0_valid + & robEntries_8_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_8_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_8_cmd_bankAccess_rd_bank_1_valid + & robEntries_8_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_8_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_8; + wire [15:0] vbankMasks_9 = + (robEntries_9_cmd_bankAccess_rd_bank_0_valid + & robEntries_9_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_9_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_9_cmd_bankAccess_rd_bank_1_valid + & robEntries_9_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_9_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_9; + wire [15:0] vbankMasks_10 = + (robEntries_10_cmd_bankAccess_rd_bank_0_valid + & robEntries_10_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_10_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_10_cmd_bankAccess_rd_bank_1_valid + & robEntries_10_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_10_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_10; + wire [15:0] vbankMasks_11 = + (robEntries_11_cmd_bankAccess_rd_bank_0_valid + & robEntries_11_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_11_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_11_cmd_bankAccess_rd_bank_1_valid + & robEntries_11_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_11_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_11; + wire [15:0] vbankMasks_12 = + (robEntries_12_cmd_bankAccess_rd_bank_0_valid + & robEntries_12_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_12_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_12_cmd_bankAccess_rd_bank_1_valid + & robEntries_12_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_12_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_12; + wire [15:0] vbankMasks_13 = + (robEntries_13_cmd_bankAccess_rd_bank_0_valid + & robEntries_13_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_13_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_13_cmd_bankAccess_rd_bank_1_valid + & robEntries_13_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_13_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_13; + wire [15:0] vbankMasks_14 = + (robEntries_14_cmd_bankAccess_rd_bank_0_valid + & robEntries_14_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_14_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_14_cmd_bankAccess_rd_bank_1_valid + & robEntries_14_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_14_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_14; + wire [15:0] vbankMasks_15 = + (robEntries_15_cmd_bankAccess_rd_bank_0_valid + & robEntries_15_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_15_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_15_cmd_bankAccess_rd_bank_1_valid + & robEntries_15_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_15_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_15; + wire _GEN_3 = _isAllocatedSlot_T_30 & (|io_alloc_bits_cmd_pc); + wire [15:0] _GEN_4 = + {{robIssued_15}, + {robIssued_14}, + {robIssued_13}, + {robIssued_12}, + {robIssued_11}, + {robIssued_10}, + {robIssued_9}, + {robIssued_8}, + {robIssued_7}, + {robIssued_6}, + {robIssued_5}, + {robIssued_4}, + {robIssued_3}, + {robIssued_2}, + {robIssued_1}, + {robIssued_0}}; + wire [15:0][3:0] _GEN_5 = + {{robEntries_15_cmd_domain_id}, + {robEntries_14_cmd_domain_id}, + {robEntries_13_cmd_domain_id}, + {robEntries_12_cmd_domain_id}, + {robEntries_11_cmd_domain_id}, + {robEntries_10_cmd_domain_id}, + {robEntries_9_cmd_domain_id}, + {robEntries_8_cmd_domain_id}, + {robEntries_7_cmd_domain_id}, + {robEntries_6_cmd_domain_id}, + {robEntries_5_cmd_domain_id}, + {robEntries_4_cmd_domain_id}, + {robEntries_3_cmd_domain_id}, + {robEntries_2_cmd_domain_id}, + {robEntries_1_cmd_domain_id}, + {robEntries_0_cmd_domain_id}}; + wire [15:0][63:0] _GEN_6 = + {{robEntries_15_cmd_cmd_pc}, + {robEntries_14_cmd_cmd_pc}, + {robEntries_13_cmd_cmd_pc}, + {robEntries_12_cmd_cmd_pc}, + {robEntries_11_cmd_cmd_pc}, + {robEntries_10_cmd_cmd_pc}, + {robEntries_9_cmd_cmd_pc}, + {robEntries_8_cmd_cmd_pc}, + {robEntries_7_cmd_cmd_pc}, + {robEntries_6_cmd_cmd_pc}, + {robEntries_5_cmd_cmd_pc}, + {robEntries_4_cmd_cmd_pc}, + {robEntries_3_cmd_cmd_pc}, + {robEntries_2_cmd_cmd_pc}, + {robEntries_1_cmd_cmd_pc}, + {robEntries_0_cmd_cmd_pc}}; + wire [15:0][6:0] _GEN_7 = + {{robEntries_15_cmd_cmd_funct}, + {robEntries_14_cmd_cmd_funct}, + {robEntries_13_cmd_cmd_funct}, + {robEntries_12_cmd_cmd_funct}, + {robEntries_11_cmd_cmd_funct}, + {robEntries_10_cmd_cmd_funct}, + {robEntries_9_cmd_cmd_funct}, + {robEntries_8_cmd_cmd_funct}, + {robEntries_7_cmd_cmd_funct}, + {robEntries_6_cmd_cmd_funct}, + {robEntries_5_cmd_cmd_funct}, + {robEntries_4_cmd_cmd_funct}, + {robEntries_3_cmd_cmd_funct}, + {robEntries_2_cmd_cmd_funct}, + {robEntries_1_cmd_cmd_funct}, + {robEntries_0_cmd_cmd_funct}}; + wire [15:0][63:0] _GEN_8 = + {{robEntries_15_cmd_cmd_rs1Data}, + {robEntries_14_cmd_cmd_rs1Data}, + {robEntries_13_cmd_cmd_rs1Data}, + {robEntries_12_cmd_cmd_rs1Data}, + {robEntries_11_cmd_cmd_rs1Data}, + {robEntries_10_cmd_cmd_rs1Data}, + {robEntries_9_cmd_cmd_rs1Data}, + {robEntries_8_cmd_cmd_rs1Data}, + {robEntries_7_cmd_cmd_rs1Data}, + {robEntries_6_cmd_cmd_rs1Data}, + {robEntries_5_cmd_cmd_rs1Data}, + {robEntries_4_cmd_cmd_rs1Data}, + {robEntries_3_cmd_cmd_rs1Data}, + {robEntries_2_cmd_cmd_rs1Data}, + {robEntries_1_cmd_cmd_rs1Data}, + {robEntries_0_cmd_cmd_rs1Data}}; + wire [15:0][63:0] _GEN_9 = + {{robEntries_15_cmd_cmd_rs2Data}, + {robEntries_14_cmd_cmd_rs2Data}, + {robEntries_13_cmd_cmd_rs2Data}, + {robEntries_12_cmd_cmd_rs2Data}, + {robEntries_11_cmd_cmd_rs2Data}, + {robEntries_10_cmd_cmd_rs2Data}, + {robEntries_9_cmd_cmd_rs2Data}, + {robEntries_8_cmd_cmd_rs2Data}, + {robEntries_7_cmd_cmd_rs2Data}, + {robEntries_6_cmd_cmd_rs2Data}, + {robEntries_5_cmd_cmd_rs2Data}, + {robEntries_4_cmd_cmd_rs2Data}, + {robEntries_3_cmd_cmd_rs2Data}, + {robEntries_2_cmd_cmd_rs2Data}, + {robEntries_1_cmd_cmd_rs2Data}, + {robEntries_0_cmd_cmd_rs2Data}}; + wire [15:0] _GEN_10 = + {{robEntries_15_renamedBankAccess_wr_bank_valid}, + {robEntries_14_renamedBankAccess_wr_bank_valid}, + {robEntries_13_renamedBankAccess_wr_bank_valid}, + {robEntries_12_renamedBankAccess_wr_bank_valid}, + {robEntries_11_renamedBankAccess_wr_bank_valid}, + {robEntries_10_renamedBankAccess_wr_bank_valid}, + {robEntries_9_renamedBankAccess_wr_bank_valid}, + {robEntries_8_renamedBankAccess_wr_bank_valid}, + {robEntries_7_renamedBankAccess_wr_bank_valid}, + {robEntries_6_renamedBankAccess_wr_bank_valid}, + {robEntries_5_renamedBankAccess_wr_bank_valid}, + {robEntries_4_renamedBankAccess_wr_bank_valid}, + {robEntries_3_renamedBankAccess_wr_bank_valid}, + {robEntries_2_renamedBankAccess_wr_bank_valid}, + {robEntries_1_renamedBankAccess_wr_bank_valid}, + {robEntries_0_renamedBankAccess_wr_bank_valid}}; + wire [15:0][9:0] _GEN_11 = + {{robEntries_15_renamedBankAccess_wr_bank_id}, + {robEntries_14_renamedBankAccess_wr_bank_id}, + {robEntries_13_renamedBankAccess_wr_bank_id}, + {robEntries_12_renamedBankAccess_wr_bank_id}, + {robEntries_11_renamedBankAccess_wr_bank_id}, + {robEntries_10_renamedBankAccess_wr_bank_id}, + {robEntries_9_renamedBankAccess_wr_bank_id}, + {robEntries_8_renamedBankAccess_wr_bank_id}, + {robEntries_7_renamedBankAccess_wr_bank_id}, + {robEntries_6_renamedBankAccess_wr_bank_id}, + {robEntries_5_renamedBankAccess_wr_bank_id}, + {robEntries_4_renamedBankAccess_wr_bank_id}, + {robEntries_3_renamedBankAccess_wr_bank_id}, + {robEntries_2_renamedBankAccess_wr_bank_id}, + {robEntries_1_renamedBankAccess_wr_bank_id}, + {robEntries_0_renamedBankAccess_wr_bank_id}}; + wire [15:0][63:0] _GEN_12 = + {{instIds_15}, + {instIds_14}, + {instIds_13}, + {instIds_12}, + {instIds_11}, + {instIds_10}, + {instIds_9}, + {instIds_8}, + {instIds_7}, + {instIds_6}, + {instIds_5}, + {instIds_4}, + {instIds_3}, + {instIds_2}, + {instIds_1}, + {instIds_0}}; + wire [15:0] _GEN_13 = + {{robEntries_15_renamedBankAccess_rd_bank_0_valid}, + {robEntries_14_renamedBankAccess_rd_bank_0_valid}, + {robEntries_13_renamedBankAccess_rd_bank_0_valid}, + {robEntries_12_renamedBankAccess_rd_bank_0_valid}, + {robEntries_11_renamedBankAccess_rd_bank_0_valid}, + {robEntries_10_renamedBankAccess_rd_bank_0_valid}, + {robEntries_9_renamedBankAccess_rd_bank_0_valid}, + {robEntries_8_renamedBankAccess_rd_bank_0_valid}, + {robEntries_7_renamedBankAccess_rd_bank_0_valid}, + {robEntries_6_renamedBankAccess_rd_bank_0_valid}, + {robEntries_5_renamedBankAccess_rd_bank_0_valid}, + {robEntries_4_renamedBankAccess_rd_bank_0_valid}, + {robEntries_3_renamedBankAccess_rd_bank_0_valid}, + {robEntries_2_renamedBankAccess_rd_bank_0_valid}, + {robEntries_1_renamedBankAccess_rd_bank_0_valid}, + {robEntries_0_renamedBankAccess_rd_bank_0_valid}}; + wire [15:0][9:0] _GEN_14 = + {{robEntries_15_renamedBankAccess_rd_bank_0_id}, + {robEntries_14_renamedBankAccess_rd_bank_0_id}, + {robEntries_13_renamedBankAccess_rd_bank_0_id}, + {robEntries_12_renamedBankAccess_rd_bank_0_id}, + {robEntries_11_renamedBankAccess_rd_bank_0_id}, + {robEntries_10_renamedBankAccess_rd_bank_0_id}, + {robEntries_9_renamedBankAccess_rd_bank_0_id}, + {robEntries_8_renamedBankAccess_rd_bank_0_id}, + {robEntries_7_renamedBankAccess_rd_bank_0_id}, + {robEntries_6_renamedBankAccess_rd_bank_0_id}, + {robEntries_5_renamedBankAccess_rd_bank_0_id}, + {robEntries_4_renamedBankAccess_rd_bank_0_id}, + {robEntries_3_renamedBankAccess_rd_bank_0_id}, + {robEntries_2_renamedBankAccess_rd_bank_0_id}, + {robEntries_1_renamedBankAccess_rd_bank_0_id}, + {robEntries_0_renamedBankAccess_rd_bank_0_id}}; + wire [15:0] _GEN_15 = + {{robEntries_15_renamedBankAccess_rd_bank_1_valid}, + {robEntries_14_renamedBankAccess_rd_bank_1_valid}, + {robEntries_13_renamedBankAccess_rd_bank_1_valid}, + {robEntries_12_renamedBankAccess_rd_bank_1_valid}, + {robEntries_11_renamedBankAccess_rd_bank_1_valid}, + {robEntries_10_renamedBankAccess_rd_bank_1_valid}, + {robEntries_9_renamedBankAccess_rd_bank_1_valid}, + {robEntries_8_renamedBankAccess_rd_bank_1_valid}, + {robEntries_7_renamedBankAccess_rd_bank_1_valid}, + {robEntries_6_renamedBankAccess_rd_bank_1_valid}, + {robEntries_5_renamedBankAccess_rd_bank_1_valid}, + {robEntries_4_renamedBankAccess_rd_bank_1_valid}, + {robEntries_3_renamedBankAccess_rd_bank_1_valid}, + {robEntries_2_renamedBankAccess_rd_bank_1_valid}, + {robEntries_1_renamedBankAccess_rd_bank_1_valid}, + {robEntries_0_renamedBankAccess_rd_bank_1_valid}}; + wire [15:0][9:0] _GEN_16 = + {{robEntries_15_renamedBankAccess_rd_bank_1_id}, + {robEntries_14_renamedBankAccess_rd_bank_1_id}, + {robEntries_13_renamedBankAccess_rd_bank_1_id}, + {robEntries_12_renamedBankAccess_rd_bank_1_id}, + {robEntries_11_renamedBankAccess_rd_bank_1_id}, + {robEntries_10_renamedBankAccess_rd_bank_1_id}, + {robEntries_9_renamedBankAccess_rd_bank_1_id}, + {robEntries_8_renamedBankAccess_rd_bank_1_id}, + {robEntries_7_renamedBankAccess_rd_bank_1_id}, + {robEntries_6_renamedBankAccess_rd_bank_1_id}, + {robEntries_5_renamedBankAccess_rd_bank_1_id}, + {robEntries_4_renamedBankAccess_rd_bank_1_id}, + {robEntries_3_renamedBankAccess_rd_bank_1_id}, + {robEntries_2_renamedBankAccess_rd_bank_1_id}, + {robEntries_1_renamedBankAccess_rd_bank_1_id}, + {robEntries_0_renamedBankAccess_rd_bank_1_id}}; + wire [15:0][15:0] _GEN_17 = + {{dependencyMask_15}, + {dependencyMask_14}, + {dependencyMask_13}, + {dependencyMask_12}, + {dependencyMask_11}, + {dependencyMask_10}, + {dependencyMask_9}, + {dependencyMask_8}, + {dependencyMask_7}, + {dependencyMask_6}, + {dependencyMask_5}, + {dependencyMask_4}, + {dependencyMask_3}, + {dependencyMask_2}, + {dependencyMask_1}, + {dependencyMask_0}}; + wire [15:0][15:0] _GEN_18 = + {{vbankMasks_15}, + {vbankMasks_14}, + {vbankMasks_13}, + {vbankMasks_12}, + {vbankMasks_11}, + {vbankMasks_10}, + {vbankMasks_9}, + {vbankMasks_8}, + {vbankMasks_7}, + {vbankMasks_6}, + {vbankMasks_5}, + {vbankMasks_4}, + {vbankMasks_3}, + {vbankMasks_2}, + {vbankMasks_1}, + {olderUseMask}}; + wire scanReady_0 = + _GEN_0 & ~_GEN_4[ptr] & ~_GEN_2 & ~_scoreboard_hazardVec_0 & _GEN_17[ptr] == 16'h0 + & (_GEN_18[ptr] & vbankBusy) == 16'h0; + wire scanReady_1 = + _GEN[_hits_ptr_T_1446] & ~_GEN_4[_hits_ptr_T_1446] & ~_GEN_1[_hits_ptr_T_1446] + & ~_scoreboard_hazardVec_1 & _GEN_17[_hits_ptr_T_1446] == 16'h0 + & (_GEN_18[_hits_ptr_T_1446] & vbankBusy) == 16'h0; + wire scanReady_2 = + _GEN[_hits_ptr_T_1452] & ~_GEN_4[_hits_ptr_T_1452] & ~_GEN_1[_hits_ptr_T_1452] + & ~_scoreboard_hazardVec_2 & _GEN_17[_hits_ptr_T_1452] == 16'h0 + & (_GEN_18[_hits_ptr_T_1452] & vbankBusy) == 16'h0; + wire scanReady_3 = + _GEN[_hits_ptr_T_1458] & ~_GEN_4[_hits_ptr_T_1458] & ~_GEN_1[_hits_ptr_T_1458] + & ~_scoreboard_hazardVec_3 & _GEN_17[_hits_ptr_T_1458] == 16'h0 + & (_GEN_18[_hits_ptr_T_1458] & vbankBusy) == 16'h0; + wire scanReady_4 = + _GEN[_hits_ptr_T_1464] & ~_GEN_4[_hits_ptr_T_1464] & ~_GEN_1[_hits_ptr_T_1464] + & ~_scoreboard_hazardVec_4 & _GEN_17[_hits_ptr_T_1464] == 16'h0 + & (_GEN_18[_hits_ptr_T_1464] & vbankBusy) == 16'h0; + wire scanReady_5 = + _GEN[_hits_ptr_T_1470] & ~_GEN_4[_hits_ptr_T_1470] & ~_GEN_1[_hits_ptr_T_1470] + & ~_scoreboard_hazardVec_5 & _GEN_17[_hits_ptr_T_1470] == 16'h0 + & (_GEN_18[_hits_ptr_T_1470] & vbankBusy) == 16'h0; + wire scanReady_6 = + _GEN[_hits_ptr_T_1476] & ~_GEN_4[_hits_ptr_T_1476] & ~_GEN_1[_hits_ptr_T_1476] + & ~_scoreboard_hazardVec_6 & _GEN_17[_hits_ptr_T_1476] == 16'h0 + & (_GEN_18[_hits_ptr_T_1476] & vbankBusy) == 16'h0; + wire scanReady_7 = + _GEN[_hits_ptr_T_1482] & ~_GEN_4[_hits_ptr_T_1482] & ~_GEN_1[_hits_ptr_T_1482] + & ~_scoreboard_hazardVec_7 & _GEN_17[_hits_ptr_T_1482] == 16'h0 + & (_GEN_18[_hits_ptr_T_1482] & vbankBusy) == 16'h0; + wire scanReady_8 = + _GEN[_hits_ptr_T_1488] & ~_GEN_4[_hits_ptr_T_1488] & ~_GEN_1[_hits_ptr_T_1488] + & ~_scoreboard_hazardVec_8 & _GEN_17[_hits_ptr_T_1488] == 16'h0 + & (_GEN_18[_hits_ptr_T_1488] & vbankBusy) == 16'h0; + wire scanReady_9 = + _GEN[_hits_ptr_T_1494] & ~_GEN_4[_hits_ptr_T_1494] & ~_GEN_1[_hits_ptr_T_1494] + & ~_scoreboard_hazardVec_9 & _GEN_17[_hits_ptr_T_1494] == 16'h0 + & (_GEN_18[_hits_ptr_T_1494] & vbankBusy) == 16'h0; + wire scanReady_10 = + _GEN[_hits_ptr_T_1500] & ~_GEN_4[_hits_ptr_T_1500] & ~_GEN_1[_hits_ptr_T_1500] + & ~_scoreboard_hazardVec_10 & _GEN_17[_hits_ptr_T_1500] == 16'h0 + & (_GEN_18[_hits_ptr_T_1500] & vbankBusy) == 16'h0; + wire scanReady_11 = + _GEN[_hits_ptr_T_1506] & ~_GEN_4[_hits_ptr_T_1506] & ~_GEN_1[_hits_ptr_T_1506] + & ~_scoreboard_hazardVec_11 & _GEN_17[_hits_ptr_T_1506] == 16'h0 + & (_GEN_18[_hits_ptr_T_1506] & vbankBusy) == 16'h0; + wire scanReady_12 = + _GEN[_hits_ptr_T_1512] & ~_GEN_4[_hits_ptr_T_1512] & ~_GEN_1[_hits_ptr_T_1512] + & ~_scoreboard_hazardVec_12 & _GEN_17[_hits_ptr_T_1512] == 16'h0 + & (_GEN_18[_hits_ptr_T_1512] & vbankBusy) == 16'h0; + wire scanReady_13 = + _GEN[_hits_ptr_T_1518] & ~_GEN_4[_hits_ptr_T_1518] & ~_GEN_1[_hits_ptr_T_1518] + & ~_scoreboard_hazardVec_13 & _GEN_17[_hits_ptr_T_1518] == 16'h0 + & (_GEN_18[_hits_ptr_T_1518] & vbankBusy) == 16'h0; + wire scanReady_14 = + _GEN[_hits_ptr_T_1524] & ~_GEN_4[_hits_ptr_T_1524] & ~_GEN_1[_hits_ptr_T_1524] + & ~_scoreboard_hazardVec_14 & _GEN_17[_hits_ptr_T_1524] == 16'h0 + & (_GEN_18[_hits_ptr_T_1524] & vbankBusy) == 16'h0; + wire [3:0] _actualIssuePtr_T = + ptr + + (scanReady_0 + ? 4'h0 + : scanReady_1 + ? 4'h1 + : scanReady_2 + ? 4'h2 + : scanReady_3 + ? 4'h3 + : scanReady_4 + ? 4'h4 + : scanReady_5 + ? 4'h5 + : scanReady_6 + ? 4'h6 + : scanReady_7 + ? 4'h7 + : scanReady_8 + ? 4'h8 + : scanReady_9 + ? 4'h9 + : scanReady_10 + ? 4'hA + : scanReady_11 + ? 4'hB + : scanReady_12 + ? 4'hC + : scanReady_13 + ? 4'hD + : {3'h7, ~scanReady_14}); + wire [15:0][3:0] _GEN_19 = + {{robEntries_15_rob_id}, + {robEntries_14_rob_id}, + {robEntries_13_rob_id}, + {robEntries_12_rob_id}, + {robEntries_11_rob_id}, + {robEntries_10_rob_id}, + {robEntries_9_rob_id}, + {robEntries_8_rob_id}, + {robEntries_7_rob_id}, + {robEntries_6_rob_id}, + {robEntries_5_rob_id}, + {robEntries_4_rob_id}, + {robEntries_3_rob_id}, + {robEntries_2_rob_id}, + {robEntries_1_rob_id}, + {robEntries_0_rob_id}}; + reg issueStageValid; + reg [3:0] issueStageEntry_cmd_domain_id; + reg [4:0] issueStageEntry_cmd_ball_bid; + reg [31:0] issueStageEntry_cmd_cmd_raw_inst; + reg [63:0] issueStageEntry_cmd_cmd_pc; + reg [6:0] issueStageEntry_cmd_cmd_funct; + reg [2:0] issueStageEntry_cmd_cmd_funct3; + reg [4:0] issueStageEntry_cmd_cmd_rs2; + reg [4:0] issueStageEntry_cmd_cmd_rs1; + reg issueStageEntry_cmd_cmd_xd; + reg issueStageEntry_cmd_cmd_xs1; + reg issueStageEntry_cmd_cmd_xs2; + reg [4:0] issueStageEntry_cmd_cmd_rd; + reg [6:0] issueStageEntry_cmd_cmd_opcode; + reg [63:0] issueStageEntry_cmd_cmd_rs1Data; + reg [63:0] issueStageEntry_cmd_cmd_rs2Data; + reg issueStageEntry_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] issueStageEntry_cmd_bankAccess_rd_bank_0_id; + reg issueStageEntry_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] issueStageEntry_cmd_bankAccess_rd_bank_1_id; + reg issueStageEntry_cmd_bankAccess_wr_bank_valid; + reg [9:0] issueStageEntry_cmd_bankAccess_wr_bank_id; + reg [3:0] issueStageEntry_cmd_op1_col; + reg [3:0] issueStageEntry_cmd_op2_col; + reg [3:0] issueStageEntry_cmd_wr_col; + reg issueStageEntry_cmd_isFence; + reg issueStageEntry_cmd_isBarrier; + reg issueStageEntry_renamedBankAccess_rd_bank_0_valid; + reg [9:0] issueStageEntry_renamedBankAccess_rd_bank_0_id; + reg issueStageEntry_renamedBankAccess_rd_bank_1_valid; + reg [9:0] issueStageEntry_renamedBankAccess_rd_bank_1_id; + reg issueStageEntry_renamedBankAccess_wr_bank_valid; + reg [9:0] issueStageEntry_renamedBankAccess_wr_bank_id; + reg [3:0] issueStageEntry_rob_id; + wire issueStageReady = + ~issueStageValid | issueStageValid & ~io_subRobActive & io_issue_ready; + reg issuePtrValid; + reg [3:0] issuePtr; + wire issuePtrFire = issuePtrValid & issueStageReady; + wire issuePtrReady = ~issuePtrValid | issuePtrFire; + wire issueLoad = + (|{_GEN[_hits_ptr_T_1530] & ~_GEN_4[_hits_ptr_T_1530] & ~_GEN_1[_hits_ptr_T_1530] + & ~_scoreboard_hazardVec_15 & _GEN_17[_hits_ptr_T_1530] == 16'h0 + & (_GEN_18[_hits_ptr_T_1530] & vbankBusy) == 16'h0, + scanReady_14, + scanReady_13, + scanReady_12, + scanReady_11, + scanReady_10, + scanReady_9, + scanReady_8, + scanReady_7, + scanReady_6, + scanReady_5, + scanReady_4, + scanReady_3, + scanReady_2, + scanReady_1, + scanReady_0}) & ~io_subRobActive & issuePtrReady; + assign commitMask_0 = + commitKeep_1 & ptr == 4'h0 | commitKeep_2 & _hits_ptr_T_1446 == 4'h0 | commitKeep_3 + & _hits_ptr_T_1452 == 4'h0 | commitKeep_4 & _hits_ptr_T_1458 == 4'h0 | commitKeep_5 + & _hits_ptr_T_1464 == 4'h0 | commitKeep_6 & _hits_ptr_T_1470 == 4'h0 | commitKeep_7 + & _hits_ptr_T_1476 == 4'h0 | commitKeep_8 & _hits_ptr_T_1482 == 4'h0 | commitKeep_9 + & _hits_ptr_T_1488 == 4'h0 | commitScan_9 & _hits_ptr_T_1494 == 4'h0 | commitKeep_11 + & _hits_ptr_T_1500 == 4'h0 | commitKeep_12 & _hits_ptr_T_1506 == 4'h0 | commitKeep_13 + & _hits_ptr_T_1512 == 4'h0 | commitKeep_14 & _hits_ptr_T_1518 == 4'h0 | commitKeep_15 + & _hits_ptr_T_1524 == 4'h0 | commitScan_15 & _hits_ptr_T_1530 == 4'h0; + assign commitMask_1 = + commitKeep_1 & ptr == 4'h1 | commitKeep_2 & _hits_ptr_T_1446 == 4'h1 | commitKeep_3 + & _hits_ptr_T_1452 == 4'h1 | commitKeep_4 & _hits_ptr_T_1458 == 4'h1 | commitKeep_5 + & _hits_ptr_T_1464 == 4'h1 | commitKeep_6 & _hits_ptr_T_1470 == 4'h1 | commitKeep_7 + & _hits_ptr_T_1476 == 4'h1 | commitKeep_8 & _hits_ptr_T_1482 == 4'h1 | commitKeep_9 + & _hits_ptr_T_1488 == 4'h1 | commitScan_9 & _hits_ptr_T_1494 == 4'h1 | commitKeep_11 + & _hits_ptr_T_1500 == 4'h1 | commitKeep_12 & _hits_ptr_T_1506 == 4'h1 | commitKeep_13 + & _hits_ptr_T_1512 == 4'h1 | commitKeep_14 & _hits_ptr_T_1518 == 4'h1 | commitKeep_15 + & _hits_ptr_T_1524 == 4'h1 | commitScan_15 & _hits_ptr_T_1530 == 4'h1; + assign commitMask_2 = + commitKeep_1 & ptr == 4'h2 | commitKeep_2 & _hits_ptr_T_1446 == 4'h2 | commitKeep_3 + & _hits_ptr_T_1452 == 4'h2 | commitKeep_4 & _hits_ptr_T_1458 == 4'h2 | commitKeep_5 + & _hits_ptr_T_1464 == 4'h2 | commitKeep_6 & _hits_ptr_T_1470 == 4'h2 | commitKeep_7 + & _hits_ptr_T_1476 == 4'h2 | commitKeep_8 & _hits_ptr_T_1482 == 4'h2 | commitKeep_9 + & _hits_ptr_T_1488 == 4'h2 | commitScan_9 & _hits_ptr_T_1494 == 4'h2 | commitKeep_11 + & _hits_ptr_T_1500 == 4'h2 | commitKeep_12 & _hits_ptr_T_1506 == 4'h2 | commitKeep_13 + & _hits_ptr_T_1512 == 4'h2 | commitKeep_14 & _hits_ptr_T_1518 == 4'h2 | commitKeep_15 + & _hits_ptr_T_1524 == 4'h2 | commitScan_15 & _hits_ptr_T_1530 == 4'h2; + assign commitMask_3 = + commitKeep_1 & ptr == 4'h3 | commitKeep_2 & _hits_ptr_T_1446 == 4'h3 | commitKeep_3 + & _hits_ptr_T_1452 == 4'h3 | commitKeep_4 & _hits_ptr_T_1458 == 4'h3 | commitKeep_5 + & _hits_ptr_T_1464 == 4'h3 | commitKeep_6 & _hits_ptr_T_1470 == 4'h3 | commitKeep_7 + & _hits_ptr_T_1476 == 4'h3 | commitKeep_8 & _hits_ptr_T_1482 == 4'h3 | commitKeep_9 + & _hits_ptr_T_1488 == 4'h3 | commitScan_9 & _hits_ptr_T_1494 == 4'h3 | commitKeep_11 + & _hits_ptr_T_1500 == 4'h3 | commitKeep_12 & _hits_ptr_T_1506 == 4'h3 | commitKeep_13 + & _hits_ptr_T_1512 == 4'h3 | commitKeep_14 & _hits_ptr_T_1518 == 4'h3 | commitKeep_15 + & _hits_ptr_T_1524 == 4'h3 | commitScan_15 & _hits_ptr_T_1530 == 4'h3; + assign commitMask_4 = + commitKeep_1 & ptr == 4'h4 | commitKeep_2 & _hits_ptr_T_1446 == 4'h4 | commitKeep_3 + & _hits_ptr_T_1452 == 4'h4 | commitKeep_4 & _hits_ptr_T_1458 == 4'h4 | commitKeep_5 + & _hits_ptr_T_1464 == 4'h4 | commitKeep_6 & _hits_ptr_T_1470 == 4'h4 | commitKeep_7 + & _hits_ptr_T_1476 == 4'h4 | commitKeep_8 & _hits_ptr_T_1482 == 4'h4 | commitKeep_9 + & _hits_ptr_T_1488 == 4'h4 | commitScan_9 & _hits_ptr_T_1494 == 4'h4 | commitKeep_11 + & _hits_ptr_T_1500 == 4'h4 | commitKeep_12 & _hits_ptr_T_1506 == 4'h4 | commitKeep_13 + & _hits_ptr_T_1512 == 4'h4 | commitKeep_14 & _hits_ptr_T_1518 == 4'h4 | commitKeep_15 + & _hits_ptr_T_1524 == 4'h4 | commitScan_15 & _hits_ptr_T_1530 == 4'h4; + assign commitMask_5 = + commitKeep_1 & ptr == 4'h5 | commitKeep_2 & _hits_ptr_T_1446 == 4'h5 | commitKeep_3 + & _hits_ptr_T_1452 == 4'h5 | commitKeep_4 & _hits_ptr_T_1458 == 4'h5 | commitKeep_5 + & _hits_ptr_T_1464 == 4'h5 | commitKeep_6 & _hits_ptr_T_1470 == 4'h5 | commitKeep_7 + & _hits_ptr_T_1476 == 4'h5 | commitKeep_8 & _hits_ptr_T_1482 == 4'h5 | commitKeep_9 + & _hits_ptr_T_1488 == 4'h5 | commitScan_9 & _hits_ptr_T_1494 == 4'h5 | commitKeep_11 + & _hits_ptr_T_1500 == 4'h5 | commitKeep_12 & _hits_ptr_T_1506 == 4'h5 | commitKeep_13 + & _hits_ptr_T_1512 == 4'h5 | commitKeep_14 & _hits_ptr_T_1518 == 4'h5 | commitKeep_15 + & _hits_ptr_T_1524 == 4'h5 | commitScan_15 & _hits_ptr_T_1530 == 4'h5; + assign commitMask_6 = + commitKeep_1 & ptr == 4'h6 | commitKeep_2 & _hits_ptr_T_1446 == 4'h6 | commitKeep_3 + & _hits_ptr_T_1452 == 4'h6 | commitKeep_4 & _hits_ptr_T_1458 == 4'h6 | commitKeep_5 + & _hits_ptr_T_1464 == 4'h6 | commitKeep_6 & _hits_ptr_T_1470 == 4'h6 | commitKeep_7 + & _hits_ptr_T_1476 == 4'h6 | commitKeep_8 & _hits_ptr_T_1482 == 4'h6 | commitKeep_9 + & _hits_ptr_T_1488 == 4'h6 | commitScan_9 & _hits_ptr_T_1494 == 4'h6 | commitKeep_11 + & _hits_ptr_T_1500 == 4'h6 | commitKeep_12 & _hits_ptr_T_1506 == 4'h6 | commitKeep_13 + & _hits_ptr_T_1512 == 4'h6 | commitKeep_14 & _hits_ptr_T_1518 == 4'h6 | commitKeep_15 + & _hits_ptr_T_1524 == 4'h6 | commitScan_15 & _hits_ptr_T_1530 == 4'h6; + assign commitMask_7 = + commitKeep_1 & ptr == 4'h7 | commitKeep_2 & _hits_ptr_T_1446 == 4'h7 | commitKeep_3 + & _hits_ptr_T_1452 == 4'h7 | commitKeep_4 & _hits_ptr_T_1458 == 4'h7 | commitKeep_5 + & _hits_ptr_T_1464 == 4'h7 | commitKeep_6 & _hits_ptr_T_1470 == 4'h7 | commitKeep_7 + & _hits_ptr_T_1476 == 4'h7 | commitKeep_8 & _hits_ptr_T_1482 == 4'h7 | commitKeep_9 + & _hits_ptr_T_1488 == 4'h7 | commitScan_9 & _hits_ptr_T_1494 == 4'h7 | commitKeep_11 + & _hits_ptr_T_1500 == 4'h7 | commitKeep_12 & _hits_ptr_T_1506 == 4'h7 | commitKeep_13 + & _hits_ptr_T_1512 == 4'h7 | commitKeep_14 & _hits_ptr_T_1518 == 4'h7 | commitKeep_15 + & _hits_ptr_T_1524 == 4'h7 | commitScan_15 & _hits_ptr_T_1530 == 4'h7; + assign commitMask_8 = + commitKeep_1 & ptr == 4'h8 | commitKeep_2 & _hits_ptr_T_1446 == 4'h8 | commitKeep_3 + & _hits_ptr_T_1452 == 4'h8 | commitKeep_4 & _hits_ptr_T_1458 == 4'h8 | commitKeep_5 + & _hits_ptr_T_1464 == 4'h8 | commitKeep_6 & _hits_ptr_T_1470 == 4'h8 | commitKeep_7 + & _hits_ptr_T_1476 == 4'h8 | commitKeep_8 & _hits_ptr_T_1482 == 4'h8 | commitKeep_9 + & _hits_ptr_T_1488 == 4'h8 | commitScan_9 & _hits_ptr_T_1494 == 4'h8 | commitKeep_11 + & _hits_ptr_T_1500 == 4'h8 | commitKeep_12 & _hits_ptr_T_1506 == 4'h8 | commitKeep_13 + & _hits_ptr_T_1512 == 4'h8 | commitKeep_14 & _hits_ptr_T_1518 == 4'h8 | commitKeep_15 + & _hits_ptr_T_1524 == 4'h8 | commitScan_15 & _hits_ptr_T_1530 == 4'h8; + assign commitMask_9 = + commitKeep_1 & ptr == 4'h9 | commitKeep_2 & _hits_ptr_T_1446 == 4'h9 | commitKeep_3 + & _hits_ptr_T_1452 == 4'h9 | commitKeep_4 & _hits_ptr_T_1458 == 4'h9 | commitKeep_5 + & _hits_ptr_T_1464 == 4'h9 | commitKeep_6 & _hits_ptr_T_1470 == 4'h9 | commitKeep_7 + & _hits_ptr_T_1476 == 4'h9 | commitKeep_8 & _hits_ptr_T_1482 == 4'h9 | commitKeep_9 + & _hits_ptr_T_1488 == 4'h9 | commitScan_9 & _hits_ptr_T_1494 == 4'h9 | commitKeep_11 + & _hits_ptr_T_1500 == 4'h9 | commitKeep_12 & _hits_ptr_T_1506 == 4'h9 | commitKeep_13 + & _hits_ptr_T_1512 == 4'h9 | commitKeep_14 & _hits_ptr_T_1518 == 4'h9 | commitKeep_15 + & _hits_ptr_T_1524 == 4'h9 | commitScan_15 & _hits_ptr_T_1530 == 4'h9; + assign commitMask_10 = + commitKeep_1 & ptr == 4'hA | commitKeep_2 & _hits_ptr_T_1446 == 4'hA | commitKeep_3 + & _hits_ptr_T_1452 == 4'hA | commitKeep_4 & _hits_ptr_T_1458 == 4'hA | commitKeep_5 + & _hits_ptr_T_1464 == 4'hA | commitKeep_6 & _hits_ptr_T_1470 == 4'hA | commitKeep_7 + & _hits_ptr_T_1476 == 4'hA | commitKeep_8 & _hits_ptr_T_1482 == 4'hA | commitKeep_9 + & _hits_ptr_T_1488 == 4'hA | commitScan_9 & _hits_ptr_T_1494 == 4'hA | commitKeep_11 + & _hits_ptr_T_1500 == 4'hA | commitKeep_12 & _hits_ptr_T_1506 == 4'hA | commitKeep_13 + & _hits_ptr_T_1512 == 4'hA | commitKeep_14 & _hits_ptr_T_1518 == 4'hA | commitKeep_15 + & _hits_ptr_T_1524 == 4'hA | commitScan_15 & _hits_ptr_T_1530 == 4'hA; + assign commitMask_11 = + commitKeep_1 & ptr == 4'hB | commitKeep_2 & _hits_ptr_T_1446 == 4'hB | commitKeep_3 + & _hits_ptr_T_1452 == 4'hB | commitKeep_4 & _hits_ptr_T_1458 == 4'hB | commitKeep_5 + & _hits_ptr_T_1464 == 4'hB | commitKeep_6 & _hits_ptr_T_1470 == 4'hB | commitKeep_7 + & _hits_ptr_T_1476 == 4'hB | commitKeep_8 & _hits_ptr_T_1482 == 4'hB | commitKeep_9 + & _hits_ptr_T_1488 == 4'hB | commitScan_9 & _hits_ptr_T_1494 == 4'hB | commitKeep_11 + & _hits_ptr_T_1500 == 4'hB | commitKeep_12 & _hits_ptr_T_1506 == 4'hB | commitKeep_13 + & _hits_ptr_T_1512 == 4'hB | commitKeep_14 & _hits_ptr_T_1518 == 4'hB | commitKeep_15 + & _hits_ptr_T_1524 == 4'hB | commitScan_15 & _hits_ptr_T_1530 == 4'hB; + assign commitMask_12 = + commitKeep_1 & ptr == 4'hC | commitKeep_2 & _hits_ptr_T_1446 == 4'hC | commitKeep_3 + & _hits_ptr_T_1452 == 4'hC | commitKeep_4 & _hits_ptr_T_1458 == 4'hC | commitKeep_5 + & _hits_ptr_T_1464 == 4'hC | commitKeep_6 & _hits_ptr_T_1470 == 4'hC | commitKeep_7 + & _hits_ptr_T_1476 == 4'hC | commitKeep_8 & _hits_ptr_T_1482 == 4'hC | commitKeep_9 + & _hits_ptr_T_1488 == 4'hC | commitScan_9 & _hits_ptr_T_1494 == 4'hC | commitKeep_11 + & _hits_ptr_T_1500 == 4'hC | commitKeep_12 & _hits_ptr_T_1506 == 4'hC | commitKeep_13 + & _hits_ptr_T_1512 == 4'hC | commitKeep_14 & _hits_ptr_T_1518 == 4'hC | commitKeep_15 + & _hits_ptr_T_1524 == 4'hC | commitScan_15 & _hits_ptr_T_1530 == 4'hC; + assign commitMask_13 = + commitKeep_1 & ptr == 4'hD | commitKeep_2 & _hits_ptr_T_1446 == 4'hD | commitKeep_3 + & _hits_ptr_T_1452 == 4'hD | commitKeep_4 & _hits_ptr_T_1458 == 4'hD | commitKeep_5 + & _hits_ptr_T_1464 == 4'hD | commitKeep_6 & _hits_ptr_T_1470 == 4'hD | commitKeep_7 + & _hits_ptr_T_1476 == 4'hD | commitKeep_8 & _hits_ptr_T_1482 == 4'hD | commitKeep_9 + & _hits_ptr_T_1488 == 4'hD | commitScan_9 & _hits_ptr_T_1494 == 4'hD | commitKeep_11 + & _hits_ptr_T_1500 == 4'hD | commitKeep_12 & _hits_ptr_T_1506 == 4'hD | commitKeep_13 + & _hits_ptr_T_1512 == 4'hD | commitKeep_14 & _hits_ptr_T_1518 == 4'hD | commitKeep_15 + & _hits_ptr_T_1524 == 4'hD | commitScan_15 & _hits_ptr_T_1530 == 4'hD; + assign commitMask_14 = + commitKeep_1 & ptr == 4'hE | commitKeep_2 & _hits_ptr_T_1446 == 4'hE | commitKeep_3 + & _hits_ptr_T_1452 == 4'hE | commitKeep_4 & _hits_ptr_T_1458 == 4'hE | commitKeep_5 + & _hits_ptr_T_1464 == 4'hE | commitKeep_6 & _hits_ptr_T_1470 == 4'hE | commitKeep_7 + & _hits_ptr_T_1476 == 4'hE | commitKeep_8 & _hits_ptr_T_1482 == 4'hE | commitKeep_9 + & _hits_ptr_T_1488 == 4'hE | commitScan_9 & _hits_ptr_T_1494 == 4'hE | commitKeep_11 + & _hits_ptr_T_1500 == 4'hE | commitKeep_12 & _hits_ptr_T_1506 == 4'hE | commitKeep_13 + & _hits_ptr_T_1512 == 4'hE | commitKeep_14 & _hits_ptr_T_1518 == 4'hE | commitKeep_15 + & _hits_ptr_T_1524 == 4'hE | commitScan_15 & _hits_ptr_T_1530 == 4'hE; + assign commitMask_15 = + commitKeep_1 & (&ptr) | commitKeep_2 & (&_hits_ptr_T_1446) | commitKeep_3 + & (&_hits_ptr_T_1452) | commitKeep_4 & (&_hits_ptr_T_1458) | commitKeep_5 + & (&_hits_ptr_T_1464) | commitKeep_6 & (&_hits_ptr_T_1470) | commitKeep_7 + & (&_hits_ptr_T_1476) | commitKeep_8 & (&_hits_ptr_T_1482) | commitKeep_9 + & (&_hits_ptr_T_1488) | commitScan_9 & (&_hits_ptr_T_1494) | commitKeep_11 + & (&_hits_ptr_T_1500) | commitKeep_12 & (&_hits_ptr_T_1506) | commitKeep_13 + & (&_hits_ptr_T_1512) | commitKeep_14 & (&_hits_ptr_T_1518) | commitKeep_15 + & (&_hits_ptr_T_1524) | commitScan_15 & (&_hits_ptr_T_1530); + always @(posedge clock) begin + if (reset) begin + robEntries_0_cmd_domain_id <= 4'h0; + robEntries_0_cmd_ball_bid <= 5'h0; + robEntries_0_cmd_cmd_raw_inst <= 32'h0; + robEntries_0_cmd_cmd_pc <= 64'h0; + robEntries_0_cmd_cmd_funct <= 7'h0; + robEntries_0_cmd_cmd_funct3 <= 3'h0; + robEntries_0_cmd_cmd_rs2 <= 5'h0; + robEntries_0_cmd_cmd_rs1 <= 5'h0; + robEntries_0_cmd_cmd_xd <= 1'h0; + robEntries_0_cmd_cmd_xs1 <= 1'h0; + robEntries_0_cmd_cmd_xs2 <= 1'h0; + robEntries_0_cmd_cmd_rd <= 5'h0; + robEntries_0_cmd_cmd_opcode <= 7'h0; + robEntries_0_cmd_cmd_rs1Data <= 64'h0; + robEntries_0_cmd_cmd_rs2Data <= 64'h0; + robEntries_0_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_0_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_0_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_0_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_0_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_0_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_0_cmd_isFence <= 1'h0; + robEntries_0_cmd_isBarrier <= 1'h0; + robEntries_0_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_0_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_0_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_0_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_0_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_0_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_0_rob_id <= 4'h0; + robEntries_1_cmd_domain_id <= 4'h0; + robEntries_1_cmd_ball_bid <= 5'h0; + robEntries_1_cmd_cmd_raw_inst <= 32'h0; + robEntries_1_cmd_cmd_pc <= 64'h0; + robEntries_1_cmd_cmd_funct <= 7'h0; + robEntries_1_cmd_cmd_funct3 <= 3'h0; + robEntries_1_cmd_cmd_rs2 <= 5'h0; + robEntries_1_cmd_cmd_rs1 <= 5'h0; + robEntries_1_cmd_cmd_xd <= 1'h0; + robEntries_1_cmd_cmd_xs1 <= 1'h0; + robEntries_1_cmd_cmd_xs2 <= 1'h0; + robEntries_1_cmd_cmd_rd <= 5'h0; + robEntries_1_cmd_cmd_opcode <= 7'h0; + robEntries_1_cmd_cmd_rs1Data <= 64'h0; + robEntries_1_cmd_cmd_rs2Data <= 64'h0; + robEntries_1_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_1_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_1_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_1_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_1_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_1_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_1_cmd_isFence <= 1'h0; + robEntries_1_cmd_isBarrier <= 1'h0; + robEntries_1_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_1_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_1_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_1_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_1_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_1_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_1_rob_id <= 4'h0; + robEntries_2_cmd_domain_id <= 4'h0; + robEntries_2_cmd_ball_bid <= 5'h0; + robEntries_2_cmd_cmd_raw_inst <= 32'h0; + robEntries_2_cmd_cmd_pc <= 64'h0; + robEntries_2_cmd_cmd_funct <= 7'h0; + robEntries_2_cmd_cmd_funct3 <= 3'h0; + robEntries_2_cmd_cmd_rs2 <= 5'h0; + robEntries_2_cmd_cmd_rs1 <= 5'h0; + robEntries_2_cmd_cmd_xd <= 1'h0; + robEntries_2_cmd_cmd_xs1 <= 1'h0; + robEntries_2_cmd_cmd_xs2 <= 1'h0; + robEntries_2_cmd_cmd_rd <= 5'h0; + robEntries_2_cmd_cmd_opcode <= 7'h0; + robEntries_2_cmd_cmd_rs1Data <= 64'h0; + robEntries_2_cmd_cmd_rs2Data <= 64'h0; + robEntries_2_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_2_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_2_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_2_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_2_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_2_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_2_cmd_isFence <= 1'h0; + robEntries_2_cmd_isBarrier <= 1'h0; + robEntries_2_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_2_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_2_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_2_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_2_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_2_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_2_rob_id <= 4'h0; + robEntries_3_cmd_domain_id <= 4'h0; + robEntries_3_cmd_ball_bid <= 5'h0; + robEntries_3_cmd_cmd_raw_inst <= 32'h0; + robEntries_3_cmd_cmd_pc <= 64'h0; + robEntries_3_cmd_cmd_funct <= 7'h0; + robEntries_3_cmd_cmd_funct3 <= 3'h0; + robEntries_3_cmd_cmd_rs2 <= 5'h0; + robEntries_3_cmd_cmd_rs1 <= 5'h0; + robEntries_3_cmd_cmd_xd <= 1'h0; + robEntries_3_cmd_cmd_xs1 <= 1'h0; + robEntries_3_cmd_cmd_xs2 <= 1'h0; + robEntries_3_cmd_cmd_rd <= 5'h0; + robEntries_3_cmd_cmd_opcode <= 7'h0; + robEntries_3_cmd_cmd_rs1Data <= 64'h0; + robEntries_3_cmd_cmd_rs2Data <= 64'h0; + robEntries_3_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_3_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_3_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_3_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_3_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_3_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_3_cmd_isFence <= 1'h0; + robEntries_3_cmd_isBarrier <= 1'h0; + robEntries_3_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_3_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_3_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_3_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_3_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_3_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_3_rob_id <= 4'h0; + robEntries_4_cmd_domain_id <= 4'h0; + robEntries_4_cmd_ball_bid <= 5'h0; + robEntries_4_cmd_cmd_raw_inst <= 32'h0; + robEntries_4_cmd_cmd_pc <= 64'h0; + robEntries_4_cmd_cmd_funct <= 7'h0; + robEntries_4_cmd_cmd_funct3 <= 3'h0; + robEntries_4_cmd_cmd_rs2 <= 5'h0; + robEntries_4_cmd_cmd_rs1 <= 5'h0; + robEntries_4_cmd_cmd_xd <= 1'h0; + robEntries_4_cmd_cmd_xs1 <= 1'h0; + robEntries_4_cmd_cmd_xs2 <= 1'h0; + robEntries_4_cmd_cmd_rd <= 5'h0; + robEntries_4_cmd_cmd_opcode <= 7'h0; + robEntries_4_cmd_cmd_rs1Data <= 64'h0; + robEntries_4_cmd_cmd_rs2Data <= 64'h0; + robEntries_4_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_4_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_4_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_4_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_4_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_4_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_4_cmd_isFence <= 1'h0; + robEntries_4_cmd_isBarrier <= 1'h0; + robEntries_4_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_4_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_4_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_4_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_4_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_4_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_4_rob_id <= 4'h0; + robEntries_5_cmd_domain_id <= 4'h0; + robEntries_5_cmd_ball_bid <= 5'h0; + robEntries_5_cmd_cmd_raw_inst <= 32'h0; + robEntries_5_cmd_cmd_pc <= 64'h0; + robEntries_5_cmd_cmd_funct <= 7'h0; + robEntries_5_cmd_cmd_funct3 <= 3'h0; + robEntries_5_cmd_cmd_rs2 <= 5'h0; + robEntries_5_cmd_cmd_rs1 <= 5'h0; + robEntries_5_cmd_cmd_xd <= 1'h0; + robEntries_5_cmd_cmd_xs1 <= 1'h0; + robEntries_5_cmd_cmd_xs2 <= 1'h0; + robEntries_5_cmd_cmd_rd <= 5'h0; + robEntries_5_cmd_cmd_opcode <= 7'h0; + robEntries_5_cmd_cmd_rs1Data <= 64'h0; + robEntries_5_cmd_cmd_rs2Data <= 64'h0; + robEntries_5_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_5_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_5_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_5_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_5_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_5_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_5_cmd_isFence <= 1'h0; + robEntries_5_cmd_isBarrier <= 1'h0; + robEntries_5_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_5_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_5_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_5_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_5_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_5_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_5_rob_id <= 4'h0; + robEntries_6_cmd_domain_id <= 4'h0; + robEntries_6_cmd_ball_bid <= 5'h0; + robEntries_6_cmd_cmd_raw_inst <= 32'h0; + robEntries_6_cmd_cmd_pc <= 64'h0; + robEntries_6_cmd_cmd_funct <= 7'h0; + robEntries_6_cmd_cmd_funct3 <= 3'h0; + robEntries_6_cmd_cmd_rs2 <= 5'h0; + robEntries_6_cmd_cmd_rs1 <= 5'h0; + robEntries_6_cmd_cmd_xd <= 1'h0; + robEntries_6_cmd_cmd_xs1 <= 1'h0; + robEntries_6_cmd_cmd_xs2 <= 1'h0; + robEntries_6_cmd_cmd_rd <= 5'h0; + robEntries_6_cmd_cmd_opcode <= 7'h0; + robEntries_6_cmd_cmd_rs1Data <= 64'h0; + robEntries_6_cmd_cmd_rs2Data <= 64'h0; + robEntries_6_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_6_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_6_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_6_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_6_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_6_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_6_cmd_isFence <= 1'h0; + robEntries_6_cmd_isBarrier <= 1'h0; + robEntries_6_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_6_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_6_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_6_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_6_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_6_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_6_rob_id <= 4'h0; + robEntries_7_cmd_domain_id <= 4'h0; + robEntries_7_cmd_ball_bid <= 5'h0; + robEntries_7_cmd_cmd_raw_inst <= 32'h0; + robEntries_7_cmd_cmd_pc <= 64'h0; + robEntries_7_cmd_cmd_funct <= 7'h0; + robEntries_7_cmd_cmd_funct3 <= 3'h0; + robEntries_7_cmd_cmd_rs2 <= 5'h0; + robEntries_7_cmd_cmd_rs1 <= 5'h0; + robEntries_7_cmd_cmd_xd <= 1'h0; + robEntries_7_cmd_cmd_xs1 <= 1'h0; + robEntries_7_cmd_cmd_xs2 <= 1'h0; + robEntries_7_cmd_cmd_rd <= 5'h0; + robEntries_7_cmd_cmd_opcode <= 7'h0; + robEntries_7_cmd_cmd_rs1Data <= 64'h0; + robEntries_7_cmd_cmd_rs2Data <= 64'h0; + robEntries_7_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_7_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_7_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_7_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_7_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_7_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_7_cmd_isFence <= 1'h0; + robEntries_7_cmd_isBarrier <= 1'h0; + robEntries_7_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_7_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_7_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_7_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_7_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_7_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_7_rob_id <= 4'h0; + robEntries_8_cmd_domain_id <= 4'h0; + robEntries_8_cmd_ball_bid <= 5'h0; + robEntries_8_cmd_cmd_raw_inst <= 32'h0; + robEntries_8_cmd_cmd_pc <= 64'h0; + robEntries_8_cmd_cmd_funct <= 7'h0; + robEntries_8_cmd_cmd_funct3 <= 3'h0; + robEntries_8_cmd_cmd_rs2 <= 5'h0; + robEntries_8_cmd_cmd_rs1 <= 5'h0; + robEntries_8_cmd_cmd_xd <= 1'h0; + robEntries_8_cmd_cmd_xs1 <= 1'h0; + robEntries_8_cmd_cmd_xs2 <= 1'h0; + robEntries_8_cmd_cmd_rd <= 5'h0; + robEntries_8_cmd_cmd_opcode <= 7'h0; + robEntries_8_cmd_cmd_rs1Data <= 64'h0; + robEntries_8_cmd_cmd_rs2Data <= 64'h0; + robEntries_8_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_8_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_8_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_8_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_8_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_8_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_8_cmd_isFence <= 1'h0; + robEntries_8_cmd_isBarrier <= 1'h0; + robEntries_8_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_8_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_8_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_8_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_8_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_8_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_8_rob_id <= 4'h0; + robEntries_9_cmd_domain_id <= 4'h0; + robEntries_9_cmd_ball_bid <= 5'h0; + robEntries_9_cmd_cmd_raw_inst <= 32'h0; + robEntries_9_cmd_cmd_pc <= 64'h0; + robEntries_9_cmd_cmd_funct <= 7'h0; + robEntries_9_cmd_cmd_funct3 <= 3'h0; + robEntries_9_cmd_cmd_rs2 <= 5'h0; + robEntries_9_cmd_cmd_rs1 <= 5'h0; + robEntries_9_cmd_cmd_xd <= 1'h0; + robEntries_9_cmd_cmd_xs1 <= 1'h0; + robEntries_9_cmd_cmd_xs2 <= 1'h0; + robEntries_9_cmd_cmd_rd <= 5'h0; + robEntries_9_cmd_cmd_opcode <= 7'h0; + robEntries_9_cmd_cmd_rs1Data <= 64'h0; + robEntries_9_cmd_cmd_rs2Data <= 64'h0; + robEntries_9_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_9_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_9_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_9_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_9_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_9_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_9_cmd_isFence <= 1'h0; + robEntries_9_cmd_isBarrier <= 1'h0; + robEntries_9_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_9_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_9_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_9_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_9_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_9_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_9_rob_id <= 4'h0; + robEntries_10_cmd_domain_id <= 4'h0; + robEntries_10_cmd_ball_bid <= 5'h0; + robEntries_10_cmd_cmd_raw_inst <= 32'h0; + robEntries_10_cmd_cmd_pc <= 64'h0; + robEntries_10_cmd_cmd_funct <= 7'h0; + robEntries_10_cmd_cmd_funct3 <= 3'h0; + robEntries_10_cmd_cmd_rs2 <= 5'h0; + robEntries_10_cmd_cmd_rs1 <= 5'h0; + robEntries_10_cmd_cmd_xd <= 1'h0; + robEntries_10_cmd_cmd_xs1 <= 1'h0; + robEntries_10_cmd_cmd_xs2 <= 1'h0; + robEntries_10_cmd_cmd_rd <= 5'h0; + robEntries_10_cmd_cmd_opcode <= 7'h0; + robEntries_10_cmd_cmd_rs1Data <= 64'h0; + robEntries_10_cmd_cmd_rs2Data <= 64'h0; + robEntries_10_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_10_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_10_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_10_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_10_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_10_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_10_cmd_isFence <= 1'h0; + robEntries_10_cmd_isBarrier <= 1'h0; + robEntries_10_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_10_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_10_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_10_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_10_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_10_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_10_rob_id <= 4'h0; + robEntries_11_cmd_domain_id <= 4'h0; + robEntries_11_cmd_ball_bid <= 5'h0; + robEntries_11_cmd_cmd_raw_inst <= 32'h0; + robEntries_11_cmd_cmd_pc <= 64'h0; + robEntries_11_cmd_cmd_funct <= 7'h0; + robEntries_11_cmd_cmd_funct3 <= 3'h0; + robEntries_11_cmd_cmd_rs2 <= 5'h0; + robEntries_11_cmd_cmd_rs1 <= 5'h0; + robEntries_11_cmd_cmd_xd <= 1'h0; + robEntries_11_cmd_cmd_xs1 <= 1'h0; + robEntries_11_cmd_cmd_xs2 <= 1'h0; + robEntries_11_cmd_cmd_rd <= 5'h0; + robEntries_11_cmd_cmd_opcode <= 7'h0; + robEntries_11_cmd_cmd_rs1Data <= 64'h0; + robEntries_11_cmd_cmd_rs2Data <= 64'h0; + robEntries_11_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_11_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_11_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_11_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_11_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_11_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_11_cmd_isFence <= 1'h0; + robEntries_11_cmd_isBarrier <= 1'h0; + robEntries_11_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_11_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_11_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_11_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_11_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_11_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_11_rob_id <= 4'h0; + robEntries_12_cmd_domain_id <= 4'h0; + robEntries_12_cmd_ball_bid <= 5'h0; + robEntries_12_cmd_cmd_raw_inst <= 32'h0; + robEntries_12_cmd_cmd_pc <= 64'h0; + robEntries_12_cmd_cmd_funct <= 7'h0; + robEntries_12_cmd_cmd_funct3 <= 3'h0; + robEntries_12_cmd_cmd_rs2 <= 5'h0; + robEntries_12_cmd_cmd_rs1 <= 5'h0; + robEntries_12_cmd_cmd_xd <= 1'h0; + robEntries_12_cmd_cmd_xs1 <= 1'h0; + robEntries_12_cmd_cmd_xs2 <= 1'h0; + robEntries_12_cmd_cmd_rd <= 5'h0; + robEntries_12_cmd_cmd_opcode <= 7'h0; + robEntries_12_cmd_cmd_rs1Data <= 64'h0; + robEntries_12_cmd_cmd_rs2Data <= 64'h0; + robEntries_12_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_12_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_12_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_12_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_12_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_12_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_12_cmd_isFence <= 1'h0; + robEntries_12_cmd_isBarrier <= 1'h0; + robEntries_12_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_12_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_12_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_12_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_12_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_12_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_12_rob_id <= 4'h0; + robEntries_13_cmd_domain_id <= 4'h0; + robEntries_13_cmd_ball_bid <= 5'h0; + robEntries_13_cmd_cmd_raw_inst <= 32'h0; + robEntries_13_cmd_cmd_pc <= 64'h0; + robEntries_13_cmd_cmd_funct <= 7'h0; + robEntries_13_cmd_cmd_funct3 <= 3'h0; + robEntries_13_cmd_cmd_rs2 <= 5'h0; + robEntries_13_cmd_cmd_rs1 <= 5'h0; + robEntries_13_cmd_cmd_xd <= 1'h0; + robEntries_13_cmd_cmd_xs1 <= 1'h0; + robEntries_13_cmd_cmd_xs2 <= 1'h0; + robEntries_13_cmd_cmd_rd <= 5'h0; + robEntries_13_cmd_cmd_opcode <= 7'h0; + robEntries_13_cmd_cmd_rs1Data <= 64'h0; + robEntries_13_cmd_cmd_rs2Data <= 64'h0; + robEntries_13_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_13_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_13_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_13_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_13_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_13_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_13_cmd_isFence <= 1'h0; + robEntries_13_cmd_isBarrier <= 1'h0; + robEntries_13_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_13_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_13_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_13_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_13_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_13_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_13_rob_id <= 4'h0; + robEntries_14_cmd_domain_id <= 4'h0; + robEntries_14_cmd_ball_bid <= 5'h0; + robEntries_14_cmd_cmd_raw_inst <= 32'h0; + robEntries_14_cmd_cmd_pc <= 64'h0; + robEntries_14_cmd_cmd_funct <= 7'h0; + robEntries_14_cmd_cmd_funct3 <= 3'h0; + robEntries_14_cmd_cmd_rs2 <= 5'h0; + robEntries_14_cmd_cmd_rs1 <= 5'h0; + robEntries_14_cmd_cmd_xd <= 1'h0; + robEntries_14_cmd_cmd_xs1 <= 1'h0; + robEntries_14_cmd_cmd_xs2 <= 1'h0; + robEntries_14_cmd_cmd_rd <= 5'h0; + robEntries_14_cmd_cmd_opcode <= 7'h0; + robEntries_14_cmd_cmd_rs1Data <= 64'h0; + robEntries_14_cmd_cmd_rs2Data <= 64'h0; + robEntries_14_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_14_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_14_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_14_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_14_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_14_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_14_cmd_isFence <= 1'h0; + robEntries_14_cmd_isBarrier <= 1'h0; + robEntries_14_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_14_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_14_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_14_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_14_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_14_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_14_rob_id <= 4'h0; + robEntries_15_cmd_domain_id <= 4'h0; + robEntries_15_cmd_ball_bid <= 5'h0; + robEntries_15_cmd_cmd_raw_inst <= 32'h0; + robEntries_15_cmd_cmd_pc <= 64'h0; + robEntries_15_cmd_cmd_funct <= 7'h0; + robEntries_15_cmd_cmd_funct3 <= 3'h0; + robEntries_15_cmd_cmd_rs2 <= 5'h0; + robEntries_15_cmd_cmd_rs1 <= 5'h0; + robEntries_15_cmd_cmd_xd <= 1'h0; + robEntries_15_cmd_cmd_xs1 <= 1'h0; + robEntries_15_cmd_cmd_xs2 <= 1'h0; + robEntries_15_cmd_cmd_rd <= 5'h0; + robEntries_15_cmd_cmd_opcode <= 7'h0; + robEntries_15_cmd_cmd_rs1Data <= 64'h0; + robEntries_15_cmd_cmd_rs2Data <= 64'h0; + robEntries_15_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_15_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_15_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_15_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_15_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_15_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_15_cmd_isFence <= 1'h0; + robEntries_15_cmd_isBarrier <= 1'h0; + robEntries_15_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_15_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_15_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_15_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_15_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_15_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_15_rob_id <= 4'h0; + robValid_0 <= 1'h0; + robValid_1 <= 1'h0; + robValid_2 <= 1'h0; + robValid_3 <= 1'h0; + robValid_4 <= 1'h0; + robValid_5 <= 1'h0; + robValid_6 <= 1'h0; + robValid_7 <= 1'h0; + robValid_8 <= 1'h0; + robValid_9 <= 1'h0; + robValid_10 <= 1'h0; + robValid_11 <= 1'h0; + robValid_12 <= 1'h0; + robValid_13 <= 1'h0; + robValid_14 <= 1'h0; + robValid_15 <= 1'h0; + robIssued_0 <= 1'h0; + robIssued_1 <= 1'h0; + robIssued_2 <= 1'h0; + robIssued_3 <= 1'h0; + robIssued_4 <= 1'h0; + robIssued_5 <= 1'h0; + robIssued_6 <= 1'h0; + robIssued_7 <= 1'h0; + robIssued_8 <= 1'h0; + robIssued_9 <= 1'h0; + robIssued_10 <= 1'h0; + robIssued_11 <= 1'h0; + robIssued_12 <= 1'h0; + robIssued_13 <= 1'h0; + robIssued_14 <= 1'h0; + robIssued_15 <= 1'h0; + robComplete_0 <= 1'h0; + robComplete_1 <= 1'h0; + robComplete_2 <= 1'h0; + robComplete_3 <= 1'h0; + robComplete_4 <= 1'h0; + robComplete_5 <= 1'h0; + robComplete_6 <= 1'h0; + robComplete_7 <= 1'h0; + robComplete_8 <= 1'h0; + robComplete_9 <= 1'h0; + robComplete_10 <= 1'h0; + robComplete_11 <= 1'h0; + robComplete_12 <= 1'h0; + robComplete_13 <= 1'h0; + robComplete_14 <= 1'h0; + robComplete_15 <= 1'h0; + instIds_0 <= 64'h0; + instIds_1 <= 64'h0; + instIds_2 <= 64'h0; + instIds_3 <= 64'h0; + instIds_4 <= 64'h0; + instIds_5 <= 64'h0; + instIds_6 <= 64'h0; + instIds_7 <= 64'h0; + instIds_8 <= 64'h0; + instIds_9 <= 64'h0; + instIds_10 <= 64'h0; + instIds_11 <= 64'h0; + instIds_12 <= 64'h0; + instIds_13 <= 64'h0; + instIds_14 <= 64'h0; + instIds_15 <= 64'h0; + nextInstId <= 64'h1; + ptr <= 4'h0; + tailPtr <= 4'h0; + issuedCount <= 5'h0; + bankCols_0 <= 4'h0; + bankCols_1 <= 4'h0; + bankCols_2 <= 4'h0; + bankCols_3 <= 4'h0; + bankCols_4 <= 4'h0; + bankCols_5 <= 4'h0; + bankCols_6 <= 4'h0; + bankCols_7 <= 4'h0; + bankCols_8 <= 4'h0; + bankCols_9 <= 4'h0; + bankCols_10 <= 4'h0; + bankCols_11 <= 4'h0; + bankCols_12 <= 4'h0; + bankCols_13 <= 4'h0; + bankCols_14 <= 4'h0; + bankCols_15 <= 4'h0; + vbankBusy <= 16'h0; + dependencyMask_0 <= 16'h0; + dependencyMask_1 <= 16'h0; + dependencyMask_2 <= 16'h0; + dependencyMask_3 <= 16'h0; + dependencyMask_4 <= 16'h0; + dependencyMask_5 <= 16'h0; + dependencyMask_6 <= 16'h0; + dependencyMask_7 <= 16'h0; + dependencyMask_8 <= 16'h0; + dependencyMask_9 <= 16'h0; + dependencyMask_10 <= 16'h0; + dependencyMask_11 <= 16'h0; + dependencyMask_12 <= 16'h0; + dependencyMask_13 <= 16'h0; + dependencyMask_14 <= 16'h0; + dependencyMask_15 <= 16'h0; + issueStageValid <= 1'h0; + issuePtrValid <= 1'h0; + end + else begin + automatic logic _entryIsConfig_0_T = robEntries_0_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_0 = + _entryIsConfig_0_T & robEntries_0_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_1_T = robEntries_1_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_1 = + _entryIsConfig_1_T & robEntries_1_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_2_T = robEntries_2_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_2 = + _entryIsConfig_2_T & robEntries_2_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_3_T = robEntries_3_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_3 = + _entryIsConfig_3_T & robEntries_3_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_4_T = robEntries_4_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_4 = + _entryIsConfig_4_T & robEntries_4_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_5_T = robEntries_5_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_5 = + _entryIsConfig_5_T & robEntries_5_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_6_T = robEntries_6_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_6 = + _entryIsConfig_6_T & robEntries_6_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_7_T = robEntries_7_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_7 = + _entryIsConfig_7_T & robEntries_7_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_8_T = robEntries_8_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_8 = + _entryIsConfig_8_T & robEntries_8_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_9_T = robEntries_9_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_9 = + _entryIsConfig_9_T & robEntries_9_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_10_T = robEntries_10_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_10 = + _entryIsConfig_10_T & robEntries_10_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_11_T = robEntries_11_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_11 = + _entryIsConfig_11_T & robEntries_11_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_12_T = robEntries_12_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_12 = + _entryIsConfig_12_T & robEntries_12_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_13_T = robEntries_13_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_13 = + _entryIsConfig_13_T & robEntries_13_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_14_T = robEntries_14_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_14 = + _entryIsConfig_14_T & robEntries_14_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_15_T = robEntries_15_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_15 = + _entryIsConfig_15_T & robEntries_15_cmd_cmd_funct == 7'h20; + automatic logic [15:0] allocReadMask = + (io_alloc_bits_bankAccess_rd_bank_0_valid + & io_alloc_bits_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << io_alloc_bits_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (io_alloc_bits_bankAccess_rd_bank_1_valid + & io_alloc_bits_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << io_alloc_bits_bankAccess_rd_bank_1_id[3:0] + : 16'h0); + automatic logic [15:0] allocWriteMask = + io_alloc_bits_bankAccess_wr_bank_valid + & io_alloc_bits_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << io_alloc_bits_bankAccess_wr_bank_id[3:0] + : 16'h0; + automatic logic allocIsConfig = + io_alloc_bits_domain_id == 4'h1 & io_alloc_bits_cmd_funct == 7'h20; + automatic logic allocIsBall = io_alloc_bits_domain_id == 4'h3; + automatic logic [15:0] _configConflict_T_92 = allocReadMask | allocWriteMask; + automatic logic [15:0] allocDependencies; + automatic logic [63:0] _instIds_T; + automatic logic _GEN_20 = _isAllocatedSlot_T_30 & ~(|tailPtr); + automatic logic _GEN_21 = _isAllocatedSlot_T_30 & tailPtr == 4'h1; + automatic logic _GEN_22 = _isAllocatedSlot_T_30 & tailPtr == 4'h2; + automatic logic _GEN_23 = _isAllocatedSlot_T_30 & tailPtr == 4'h3; + automatic logic _GEN_24 = _isAllocatedSlot_T_30 & tailPtr == 4'h4; + automatic logic _GEN_25 = _isAllocatedSlot_T_30 & tailPtr == 4'h5; + automatic logic _GEN_26 = _isAllocatedSlot_T_30 & tailPtr == 4'h6; + automatic logic _GEN_27 = _isAllocatedSlot_T_30 & tailPtr == 4'h7; + automatic logic _GEN_28 = _isAllocatedSlot_T_30 & tailPtr == 4'h8; + automatic logic _GEN_29 = _isAllocatedSlot_T_30 & tailPtr == 4'h9; + automatic logic _GEN_30 = _isAllocatedSlot_T_30 & tailPtr == 4'hA; + automatic logic _GEN_31 = _isAllocatedSlot_T_30 & tailPtr == 4'hB; + automatic logic _GEN_32 = _isAllocatedSlot_T_30 & tailPtr == 4'hC; + automatic logic _GEN_33 = _isAllocatedSlot_T_30 & tailPtr == 4'hD; + automatic logic _GEN_34 = _isAllocatedSlot_T_30 & tailPtr == 4'hE; + automatic logic _GEN_35 = _isAllocatedSlot_T_30 & (&tailPtr); + automatic logic [15:0] completedBitMask = + io_complete_valid ? 16'h1 << io_complete_bits : 16'h0; + automatic logic [3:0] _GEN_36; + automatic logic _GEN_37; + automatic logic [3:0] _GEN_38; + automatic logic _GEN_39; + automatic logic [3:0] _GEN_40; + automatic logic _GEN_41; + automatic logic [3:0] _GEN_42; + automatic logic _GEN_43; + automatic logic [3:0] _GEN_44; + automatic logic _GEN_45; + automatic logic [3:0] _GEN_46; + automatic logic _GEN_47; + automatic logic [3:0] _GEN_48; + automatic logic _GEN_49; + automatic logic [3:0] _GEN_50; + automatic logic _GEN_51; + automatic logic [3:0] _GEN_52; + automatic logic _GEN_53; + automatic logic [3:0] _GEN_54; + automatic logic _GEN_55; + automatic logic [3:0] _GEN_56; + automatic logic _GEN_57; + automatic logic [3:0] _GEN_58; + automatic logic _GEN_59; + automatic logic [3:0] _GEN_60; + automatic logic _GEN_61; + automatic logic [3:0] _GEN_62; + automatic logic _GEN_63; + automatic logic [3:0] _GEN_64; + automatic logic _GEN_65; + automatic logic [3:0] _GEN_66; + automatic logic _GEN_67 = + commitMask_15 & _entryIsConfig_15_T & robEntries_15_cmd_cmd_funct == 7'h20; + automatic logic [15:0] configEntryMask = + {entryIsConfig_15, + entryIsConfig_14, + entryIsConfig_13, + entryIsConfig_12, + entryIsConfig_11, + entryIsConfig_10, + entryIsConfig_9, + entryIsConfig_8, + entryIsConfig_7, + entryIsConfig_6, + entryIsConfig_5, + entryIsConfig_4, + entryIsConfig_3, + entryIsConfig_2, + entryIsConfig_1, + entryIsConfig_0}; + automatic logic isAllocatedSlot = _isAllocatedSlot_T_30 & ~(|tailPtr); + automatic logic [15:0] clearMask; + automatic logic isAllocatedSlot_1 = _isAllocatedSlot_T_30 & tailPtr == 4'h1; + automatic logic [15:0] clearMask_1; + automatic logic isAllocatedSlot_2 = _isAllocatedSlot_T_30 & tailPtr == 4'h2; + automatic logic [15:0] clearMask_2; + automatic logic isAllocatedSlot_3 = _isAllocatedSlot_T_30 & tailPtr == 4'h3; + automatic logic [15:0] clearMask_3; + automatic logic isAllocatedSlot_4 = _isAllocatedSlot_T_30 & tailPtr == 4'h4; + automatic logic [15:0] clearMask_4; + automatic logic isAllocatedSlot_5 = _isAllocatedSlot_T_30 & tailPtr == 4'h5; + automatic logic [15:0] clearMask_5; + automatic logic isAllocatedSlot_6 = _isAllocatedSlot_T_30 & tailPtr == 4'h6; + automatic logic [15:0] clearMask_6; + automatic logic isAllocatedSlot_7 = _isAllocatedSlot_T_30 & tailPtr == 4'h7; + automatic logic [15:0] clearMask_7; + automatic logic isAllocatedSlot_8 = _isAllocatedSlot_T_30 & tailPtr == 4'h8; + automatic logic [15:0] clearMask_8; + automatic logic isAllocatedSlot_9 = _isAllocatedSlot_T_30 & tailPtr == 4'h9; + automatic logic [15:0] clearMask_9; + automatic logic isAllocatedSlot_10 = _isAllocatedSlot_T_30 & tailPtr == 4'hA; + automatic logic [15:0] clearMask_10; + automatic logic isAllocatedSlot_11 = _isAllocatedSlot_T_30 & tailPtr == 4'hB; + automatic logic [15:0] clearMask_11; + automatic logic isAllocatedSlot_12 = _isAllocatedSlot_T_30 & tailPtr == 4'hC; + automatic logic [15:0] clearMask_12; + automatic logic isAllocatedSlot_13 = _isAllocatedSlot_T_30 & tailPtr == 4'hD; + automatic logic [15:0] clearMask_13; + automatic logic isAllocatedSlot_14 = _isAllocatedSlot_T_30 & tailPtr == 4'hE; + automatic logic [15:0] clearMask_14; + automatic logic isAllocatedSlot_15 = _isAllocatedSlot_T_30 & (&tailPtr); + automatic logic [15:0] clearMask_15; + allocDependencies = + {robValid_15 & ~robComplete_15 + & ((|(allocReadMask & entryRawWrites_15 | allocWriteMask & vbankMasks_15)) + | allocIsBall & robEntries_15_cmd_domain_id == 4'h3 + & robEntries_15_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_15 + & (allocIsConfig & entryIsConfig_15 | (allocIsConfig | entryIsConfig_15) + & (|(_configConflict_T_92 & vbankMasks_15))), + robValid_14 & ~robComplete_14 + & ((|(allocReadMask & entryRawWrites_14 | allocWriteMask & vbankMasks_14)) + | allocIsBall & robEntries_14_cmd_domain_id == 4'h3 + & robEntries_14_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_14 + & (allocIsConfig & entryIsConfig_14 | (allocIsConfig | entryIsConfig_14) + & (|(_configConflict_T_92 & vbankMasks_14))), + robValid_13 & ~robComplete_13 + & ((|(allocReadMask & entryRawWrites_13 | allocWriteMask & vbankMasks_13)) + | allocIsBall & robEntries_13_cmd_domain_id == 4'h3 + & robEntries_13_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_13 + & (allocIsConfig & entryIsConfig_13 | (allocIsConfig | entryIsConfig_13) + & (|(_configConflict_T_92 & vbankMasks_13))), + robValid_12 & ~robComplete_12 + & ((|(allocReadMask & entryRawWrites_12 | allocWriteMask & vbankMasks_12)) + | allocIsBall & robEntries_12_cmd_domain_id == 4'h3 + & robEntries_12_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_12 + & (allocIsConfig & entryIsConfig_12 | (allocIsConfig | entryIsConfig_12) + & (|(_configConflict_T_92 & vbankMasks_12))), + robValid_11 & ~robComplete_11 + & ((|(allocReadMask & entryRawWrites_11 | allocWriteMask & vbankMasks_11)) + | allocIsBall & robEntries_11_cmd_domain_id == 4'h3 + & robEntries_11_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_11 + & (allocIsConfig & entryIsConfig_11 | (allocIsConfig | entryIsConfig_11) + & (|(_configConflict_T_92 & vbankMasks_11))), + robValid_10 & ~robComplete_10 + & ((|(allocReadMask & entryRawWrites_10 | allocWriteMask & vbankMasks_10)) + | allocIsBall & robEntries_10_cmd_domain_id == 4'h3 + & robEntries_10_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_10 + & (allocIsConfig & entryIsConfig_10 | (allocIsConfig | entryIsConfig_10) + & (|(_configConflict_T_92 & vbankMasks_10))), + robValid_9 & ~robComplete_9 + & ((|(allocReadMask & entryRawWrites_9 | allocWriteMask & vbankMasks_9)) + | allocIsBall & robEntries_9_cmd_domain_id == 4'h3 + & robEntries_9_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_9 + & (allocIsConfig & entryIsConfig_9 | (allocIsConfig | entryIsConfig_9) + & (|(_configConflict_T_92 & vbankMasks_9))), + robValid_8 & ~robComplete_8 + & ((|(allocReadMask & entryRawWrites_8 | allocWriteMask & vbankMasks_8)) + | allocIsBall & robEntries_8_cmd_domain_id == 4'h3 + & robEntries_8_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_8 + & (allocIsConfig & entryIsConfig_8 | (allocIsConfig | entryIsConfig_8) + & (|(_configConflict_T_92 & vbankMasks_8))), + robValid_7 & ~robComplete_7 + & ((|(allocReadMask & entryRawWrites_7 | allocWriteMask & vbankMasks_7)) + | allocIsBall & robEntries_7_cmd_domain_id == 4'h3 + & robEntries_7_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_7 + & (allocIsConfig & entryIsConfig_7 | (allocIsConfig | entryIsConfig_7) + & (|(_configConflict_T_92 & vbankMasks_7))), + robValid_6 & ~robComplete_6 + & ((|(allocReadMask & entryRawWrites_6 | allocWriteMask & vbankMasks_6)) + | allocIsBall & robEntries_6_cmd_domain_id == 4'h3 + & robEntries_6_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_6 + & (allocIsConfig & entryIsConfig_6 | (allocIsConfig | entryIsConfig_6) + & (|(_configConflict_T_92 & vbankMasks_6))), + robValid_5 & ~robComplete_5 + & ((|(allocReadMask & entryRawWrites_5 | allocWriteMask & vbankMasks_5)) + | allocIsBall & robEntries_5_cmd_domain_id == 4'h3 + & robEntries_5_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_5 + & (allocIsConfig & entryIsConfig_5 | (allocIsConfig | entryIsConfig_5) + & (|(_configConflict_T_92 & vbankMasks_5))), + robValid_4 & ~robComplete_4 + & ((|(allocReadMask & entryRawWrites_4 | allocWriteMask & vbankMasks_4)) + | allocIsBall & robEntries_4_cmd_domain_id == 4'h3 + & robEntries_4_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_4 + & (allocIsConfig & entryIsConfig_4 | (allocIsConfig | entryIsConfig_4) + & (|(_configConflict_T_92 & vbankMasks_4))), + robValid_3 & ~robComplete_3 + & ((|(allocReadMask & entryRawWrites_3 | allocWriteMask & vbankMasks_3)) + | allocIsBall & robEntries_3_cmd_domain_id == 4'h3 + & robEntries_3_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_3 + & (allocIsConfig & entryIsConfig_3 | (allocIsConfig | entryIsConfig_3) + & (|(_configConflict_T_92 & vbankMasks_3))), + robValid_2 & ~robComplete_2 + & ((|(allocReadMask & entryRawWrites_2 | allocWriteMask & vbankMasks_2)) + | allocIsBall & robEntries_2_cmd_domain_id == 4'h3 + & robEntries_2_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_2 + & (allocIsConfig & entryIsConfig_2 | (allocIsConfig | entryIsConfig_2) + & (|(_configConflict_T_92 & vbankMasks_2))), + robValid_1 & ~robComplete_1 + & ((|(allocReadMask & entryRawWrites_1 | allocWriteMask & vbankMasks_1)) + | allocIsBall & robEntries_1_cmd_domain_id == 4'h3 + & robEntries_1_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_1 + & (allocIsConfig & entryIsConfig_1 | (allocIsConfig | entryIsConfig_1) + & (|(_configConflict_T_92 & vbankMasks_1))), + robValid_0 & ~robComplete_0 + & ((|(allocReadMask & entryRawWrites_0 | allocWriteMask & olderUseMask)) + | allocIsBall & robEntries_0_cmd_domain_id == 4'h3 + & robEntries_0_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_0 + & (allocIsConfig & entryIsConfig_0 | (allocIsConfig | entryIsConfig_0) + & (|(_configConflict_T_92 & olderUseMask)))}; + _instIds_T = (|io_alloc_bits_cmd_pc) ? nextInstId : 64'h0; + _GEN_36 = + robEntries_0_cmd_cmd_rs2Data[10] + ? (robEntries_0_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_0_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_37 = commitMask_0 & _entryIsConfig_0_T & robEntries_0_cmd_cmd_funct == 7'h20; + _GEN_38 = + robEntries_1_cmd_cmd_rs2Data[10] + ? (robEntries_1_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_1_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_39 = commitMask_1 & _entryIsConfig_1_T & robEntries_1_cmd_cmd_funct == 7'h20; + _GEN_40 = + robEntries_2_cmd_cmd_rs2Data[10] + ? (robEntries_2_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_2_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_41 = commitMask_2 & _entryIsConfig_2_T & robEntries_2_cmd_cmd_funct == 7'h20; + _GEN_42 = + robEntries_3_cmd_cmd_rs2Data[10] + ? (robEntries_3_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_3_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_43 = commitMask_3 & _entryIsConfig_3_T & robEntries_3_cmd_cmd_funct == 7'h20; + _GEN_44 = + robEntries_4_cmd_cmd_rs2Data[10] + ? (robEntries_4_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_4_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_45 = commitMask_4 & _entryIsConfig_4_T & robEntries_4_cmd_cmd_funct == 7'h20; + _GEN_46 = + robEntries_5_cmd_cmd_rs2Data[10] + ? (robEntries_5_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_5_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_47 = commitMask_5 & _entryIsConfig_5_T & robEntries_5_cmd_cmd_funct == 7'h20; + _GEN_48 = + robEntries_6_cmd_cmd_rs2Data[10] + ? (robEntries_6_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_6_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_49 = commitMask_6 & _entryIsConfig_6_T & robEntries_6_cmd_cmd_funct == 7'h20; + _GEN_50 = + robEntries_7_cmd_cmd_rs2Data[10] + ? (robEntries_7_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_7_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_51 = commitMask_7 & _entryIsConfig_7_T & robEntries_7_cmd_cmd_funct == 7'h20; + _GEN_52 = + robEntries_8_cmd_cmd_rs2Data[10] + ? (robEntries_8_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_8_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_53 = commitMask_8 & _entryIsConfig_8_T & robEntries_8_cmd_cmd_funct == 7'h20; + _GEN_54 = + robEntries_9_cmd_cmd_rs2Data[10] + ? (robEntries_9_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_9_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_55 = commitMask_9 & _entryIsConfig_9_T & robEntries_9_cmd_cmd_funct == 7'h20; + _GEN_56 = + robEntries_10_cmd_cmd_rs2Data[10] + ? (robEntries_10_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_10_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_57 = + commitMask_10 & _entryIsConfig_10_T & robEntries_10_cmd_cmd_funct == 7'h20; + _GEN_58 = + robEntries_11_cmd_cmd_rs2Data[10] + ? (robEntries_11_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_11_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_59 = + commitMask_11 & _entryIsConfig_11_T & robEntries_11_cmd_cmd_funct == 7'h20; + _GEN_60 = + robEntries_12_cmd_cmd_rs2Data[10] + ? (robEntries_12_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_12_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_61 = + commitMask_12 & _entryIsConfig_12_T & robEntries_12_cmd_cmd_funct == 7'h20; + _GEN_62 = + robEntries_13_cmd_cmd_rs2Data[10] + ? (robEntries_13_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_13_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_63 = + commitMask_13 & _entryIsConfig_13_T & robEntries_13_cmd_cmd_funct == 7'h20; + _GEN_64 = + robEntries_14_cmd_cmd_rs2Data[10] + ? (robEntries_14_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_14_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_65 = + commitMask_14 & _entryIsConfig_14_T & robEntries_14_cmd_cmd_funct == 7'h20; + _GEN_66 = + robEntries_15_cmd_cmd_rs2Data[10] + ? (robEntries_15_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_15_cmd_cmd_rs2Data[8:5]) + : 4'h0; + clearMask = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask | {16{isAllocatedSlot ? allocIsConfig : entryIsConfig_0}}); + clearMask_1 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask | {16{isAllocatedSlot_1 ? allocIsConfig : entryIsConfig_1}}); + clearMask_2 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask | {16{isAllocatedSlot_2 ? allocIsConfig : entryIsConfig_2}}); + clearMask_3 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask | {16{isAllocatedSlot_3 ? allocIsConfig : entryIsConfig_3}}); + clearMask_4 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask | {16{isAllocatedSlot_4 ? allocIsConfig : entryIsConfig_4}}); + clearMask_5 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask | {16{isAllocatedSlot_5 ? allocIsConfig : entryIsConfig_5}}); + clearMask_6 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask | {16{isAllocatedSlot_6 ? allocIsConfig : entryIsConfig_6}}); + clearMask_7 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask | {16{isAllocatedSlot_7 ? allocIsConfig : entryIsConfig_7}}); + clearMask_8 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask | {16{isAllocatedSlot_8 ? allocIsConfig : entryIsConfig_8}}); + clearMask_9 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask | {16{isAllocatedSlot_9 ? allocIsConfig : entryIsConfig_9}}); + clearMask_10 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask + | {16{isAllocatedSlot_10 ? allocIsConfig : entryIsConfig_10}}); + clearMask_11 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask + | {16{isAllocatedSlot_11 ? allocIsConfig : entryIsConfig_11}}); + clearMask_12 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask + | {16{isAllocatedSlot_12 ? allocIsConfig : entryIsConfig_12}}); + clearMask_13 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask + | {16{isAllocatedSlot_13 ? allocIsConfig : entryIsConfig_13}}); + clearMask_14 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask + | {16{isAllocatedSlot_14 ? allocIsConfig : entryIsConfig_14}}); + clearMask_15 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask + | {16{isAllocatedSlot_15 ? allocIsConfig : entryIsConfig_15}}); + if (_GEN_20) begin + robEntries_0_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_0_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_0_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_0_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_0_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_0_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_0_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_0_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_0_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_0_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_0_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_0_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_0_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_0_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_0_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_0_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_0_cmd_bankAccess_rd_bank_0_id <= io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_0_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_0_cmd_bankAccess_rd_bank_1_id <= io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_0_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_0_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_0_cmd_isFence <= io_alloc_bits_isFence; + robEntries_0_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_0_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_0_renamedBankAccess_rd_bank_0_id <= _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_0_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_0_renamedBankAccess_rd_bank_1_id <= _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_0_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_0_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_0_rob_id <= tailPtr; + instIds_0 <= _instIds_T; + end + if (_GEN_21) begin + robEntries_1_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_1_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_1_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_1_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_1_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_1_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_1_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_1_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_1_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_1_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_1_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_1_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_1_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_1_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_1_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_1_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_1_cmd_bankAccess_rd_bank_0_id <= io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_1_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_1_cmd_bankAccess_rd_bank_1_id <= io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_1_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_1_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_1_cmd_isFence <= io_alloc_bits_isFence; + robEntries_1_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_1_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_1_renamedBankAccess_rd_bank_0_id <= _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_1_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_1_renamedBankAccess_rd_bank_1_id <= _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_1_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_1_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_1_rob_id <= tailPtr; + instIds_1 <= _instIds_T; + end + if (_GEN_22) begin + robEntries_2_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_2_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_2_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_2_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_2_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_2_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_2_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_2_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_2_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_2_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_2_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_2_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_2_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_2_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_2_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_2_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_2_cmd_bankAccess_rd_bank_0_id <= io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_2_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_2_cmd_bankAccess_rd_bank_1_id <= io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_2_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_2_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_2_cmd_isFence <= io_alloc_bits_isFence; + robEntries_2_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_2_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_2_renamedBankAccess_rd_bank_0_id <= _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_2_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_2_renamedBankAccess_rd_bank_1_id <= _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_2_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_2_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_2_rob_id <= tailPtr; + instIds_2 <= _instIds_T; + end + if (_GEN_23) begin + robEntries_3_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_3_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_3_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_3_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_3_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_3_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_3_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_3_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_3_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_3_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_3_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_3_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_3_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_3_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_3_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_3_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_3_cmd_bankAccess_rd_bank_0_id <= io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_3_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_3_cmd_bankAccess_rd_bank_1_id <= io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_3_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_3_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_3_cmd_isFence <= io_alloc_bits_isFence; + robEntries_3_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_3_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_3_renamedBankAccess_rd_bank_0_id <= _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_3_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_3_renamedBankAccess_rd_bank_1_id <= _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_3_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_3_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_3_rob_id <= tailPtr; + instIds_3 <= _instIds_T; + end + if (_GEN_24) begin + robEntries_4_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_4_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_4_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_4_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_4_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_4_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_4_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_4_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_4_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_4_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_4_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_4_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_4_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_4_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_4_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_4_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_4_cmd_bankAccess_rd_bank_0_id <= io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_4_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_4_cmd_bankAccess_rd_bank_1_id <= io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_4_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_4_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_4_cmd_isFence <= io_alloc_bits_isFence; + robEntries_4_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_4_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_4_renamedBankAccess_rd_bank_0_id <= _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_4_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_4_renamedBankAccess_rd_bank_1_id <= _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_4_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_4_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_4_rob_id <= tailPtr; + instIds_4 <= _instIds_T; + end + if (_GEN_25) begin + robEntries_5_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_5_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_5_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_5_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_5_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_5_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_5_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_5_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_5_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_5_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_5_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_5_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_5_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_5_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_5_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_5_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_5_cmd_bankAccess_rd_bank_0_id <= io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_5_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_5_cmd_bankAccess_rd_bank_1_id <= io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_5_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_5_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_5_cmd_isFence <= io_alloc_bits_isFence; + robEntries_5_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_5_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_5_renamedBankAccess_rd_bank_0_id <= _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_5_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_5_renamedBankAccess_rd_bank_1_id <= _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_5_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_5_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_5_rob_id <= tailPtr; + instIds_5 <= _instIds_T; + end + if (_GEN_26) begin + robEntries_6_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_6_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_6_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_6_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_6_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_6_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_6_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_6_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_6_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_6_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_6_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_6_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_6_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_6_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_6_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_6_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_6_cmd_bankAccess_rd_bank_0_id <= io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_6_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_6_cmd_bankAccess_rd_bank_1_id <= io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_6_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_6_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_6_cmd_isFence <= io_alloc_bits_isFence; + robEntries_6_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_6_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_6_renamedBankAccess_rd_bank_0_id <= _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_6_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_6_renamedBankAccess_rd_bank_1_id <= _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_6_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_6_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_6_rob_id <= tailPtr; + instIds_6 <= _instIds_T; + end + if (_GEN_27) begin + robEntries_7_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_7_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_7_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_7_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_7_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_7_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_7_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_7_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_7_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_7_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_7_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_7_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_7_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_7_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_7_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_7_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_7_cmd_bankAccess_rd_bank_0_id <= io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_7_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_7_cmd_bankAccess_rd_bank_1_id <= io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_7_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_7_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_7_cmd_isFence <= io_alloc_bits_isFence; + robEntries_7_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_7_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_7_renamedBankAccess_rd_bank_0_id <= _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_7_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_7_renamedBankAccess_rd_bank_1_id <= _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_7_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_7_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_7_rob_id <= tailPtr; + instIds_7 <= _instIds_T; + end + if (_GEN_28) begin + robEntries_8_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_8_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_8_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_8_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_8_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_8_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_8_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_8_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_8_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_8_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_8_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_8_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_8_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_8_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_8_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_8_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_8_cmd_bankAccess_rd_bank_0_id <= io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_8_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_8_cmd_bankAccess_rd_bank_1_id <= io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_8_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_8_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_8_cmd_isFence <= io_alloc_bits_isFence; + robEntries_8_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_8_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_8_renamedBankAccess_rd_bank_0_id <= _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_8_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_8_renamedBankAccess_rd_bank_1_id <= _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_8_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_8_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_8_rob_id <= tailPtr; + instIds_8 <= _instIds_T; + end + if (_GEN_29) begin + robEntries_9_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_9_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_9_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_9_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_9_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_9_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_9_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_9_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_9_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_9_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_9_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_9_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_9_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_9_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_9_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_9_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_9_cmd_bankAccess_rd_bank_0_id <= io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_9_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_9_cmd_bankAccess_rd_bank_1_id <= io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_9_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_9_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_9_cmd_isFence <= io_alloc_bits_isFence; + robEntries_9_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_9_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_9_renamedBankAccess_rd_bank_0_id <= _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_9_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_9_renamedBankAccess_rd_bank_1_id <= _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_9_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_9_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_9_rob_id <= tailPtr; + instIds_9 <= _instIds_T; + end + if (_GEN_30) begin + robEntries_10_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_10_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_10_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_10_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_10_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_10_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_10_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_10_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_10_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_10_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_10_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_10_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_10_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_10_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_10_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_10_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_10_cmd_bankAccess_rd_bank_0_id <= + io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_10_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_10_cmd_bankAccess_rd_bank_1_id <= + io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_10_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_10_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_10_cmd_isFence <= io_alloc_bits_isFence; + robEntries_10_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_10_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_10_renamedBankAccess_rd_bank_0_id <= + _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_10_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_10_renamedBankAccess_rd_bank_1_id <= + _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_10_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_10_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_10_rob_id <= tailPtr; + instIds_10 <= _instIds_T; + end + if (_GEN_31) begin + robEntries_11_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_11_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_11_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_11_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_11_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_11_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_11_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_11_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_11_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_11_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_11_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_11_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_11_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_11_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_11_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_11_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_11_cmd_bankAccess_rd_bank_0_id <= + io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_11_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_11_cmd_bankAccess_rd_bank_1_id <= + io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_11_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_11_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_11_cmd_isFence <= io_alloc_bits_isFence; + robEntries_11_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_11_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_11_renamedBankAccess_rd_bank_0_id <= + _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_11_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_11_renamedBankAccess_rd_bank_1_id <= + _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_11_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_11_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_11_rob_id <= tailPtr; + instIds_11 <= _instIds_T; + end + if (_GEN_32) begin + robEntries_12_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_12_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_12_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_12_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_12_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_12_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_12_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_12_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_12_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_12_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_12_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_12_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_12_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_12_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_12_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_12_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_12_cmd_bankAccess_rd_bank_0_id <= + io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_12_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_12_cmd_bankAccess_rd_bank_1_id <= + io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_12_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_12_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_12_cmd_isFence <= io_alloc_bits_isFence; + robEntries_12_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_12_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_12_renamedBankAccess_rd_bank_0_id <= + _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_12_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_12_renamedBankAccess_rd_bank_1_id <= + _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_12_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_12_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_12_rob_id <= tailPtr; + instIds_12 <= _instIds_T; + end + if (_GEN_33) begin + robEntries_13_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_13_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_13_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_13_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_13_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_13_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_13_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_13_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_13_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_13_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_13_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_13_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_13_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_13_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_13_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_13_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_13_cmd_bankAccess_rd_bank_0_id <= + io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_13_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_13_cmd_bankAccess_rd_bank_1_id <= + io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_13_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_13_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_13_cmd_isFence <= io_alloc_bits_isFence; + robEntries_13_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_13_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_13_renamedBankAccess_rd_bank_0_id <= + _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_13_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_13_renamedBankAccess_rd_bank_1_id <= + _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_13_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_13_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_13_rob_id <= tailPtr; + instIds_13 <= _instIds_T; + end + if (_GEN_34) begin + robEntries_14_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_14_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_14_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_14_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_14_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_14_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_14_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_14_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_14_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_14_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_14_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_14_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_14_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_14_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_14_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_14_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_14_cmd_bankAccess_rd_bank_0_id <= + io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_14_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_14_cmd_bankAccess_rd_bank_1_id <= + io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_14_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_14_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_14_cmd_isFence <= io_alloc_bits_isFence; + robEntries_14_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_14_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_14_renamedBankAccess_rd_bank_0_id <= + _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_14_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_14_renamedBankAccess_rd_bank_1_id <= + _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_14_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_14_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_14_rob_id <= tailPtr; + instIds_14 <= _instIds_T; + end + if (_GEN_35) begin + robEntries_15_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_15_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_15_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_15_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_15_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_15_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_15_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_15_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_15_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_15_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_15_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_15_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_15_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_15_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_15_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_15_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_15_cmd_bankAccess_rd_bank_0_id <= + io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_15_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_15_cmd_bankAccess_rd_bank_1_id <= + io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_15_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_15_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_15_cmd_isFence <= io_alloc_bits_isFence; + robEntries_15_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_15_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_15_renamedBankAccess_rd_bank_0_id <= + _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_15_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_15_renamedBankAccess_rd_bank_1_id <= + _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_15_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_15_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_15_rob_id <= tailPtr; + instIds_15 <= _instIds_T; + end + robValid_0 <= ~commitMask_0 & (_GEN_20 | robValid_0); + robValid_1 <= ~commitMask_1 & (_GEN_21 | robValid_1); + robValid_2 <= ~commitMask_2 & (_GEN_22 | robValid_2); + robValid_3 <= ~commitMask_3 & (_GEN_23 | robValid_3); + robValid_4 <= ~commitMask_4 & (_GEN_24 | robValid_4); + robValid_5 <= ~commitMask_5 & (_GEN_25 | robValid_5); + robValid_6 <= ~commitMask_6 & (_GEN_26 | robValid_6); + robValid_7 <= ~commitMask_7 & (_GEN_27 | robValid_7); + robValid_8 <= ~commitMask_8 & (_GEN_28 | robValid_8); + robValid_9 <= ~commitMask_9 & (_GEN_29 | robValid_9); + robValid_10 <= ~commitMask_10 & (_GEN_30 | robValid_10); + robValid_11 <= ~commitMask_11 & (_GEN_31 | robValid_11); + robValid_12 <= ~commitMask_12 & (_GEN_32 | robValid_12); + robValid_13 <= ~commitMask_13 & (_GEN_33 | robValid_13); + robValid_14 <= ~commitMask_14 & (_GEN_34 | robValid_14); + robValid_15 <= ~commitMask_15 & (_GEN_35 | robValid_15); + robIssued_0 <= + ~commitMask_0 & (issueLoad & _actualIssuePtr_T == 4'h0 | ~_GEN_20 & robIssued_0); + robIssued_1 <= + ~commitMask_1 & (issueLoad & _actualIssuePtr_T == 4'h1 | ~_GEN_21 & robIssued_1); + robIssued_2 <= + ~commitMask_2 & (issueLoad & _actualIssuePtr_T == 4'h2 | ~_GEN_22 & robIssued_2); + robIssued_3 <= + ~commitMask_3 & (issueLoad & _actualIssuePtr_T == 4'h3 | ~_GEN_23 & robIssued_3); + robIssued_4 <= + ~commitMask_4 & (issueLoad & _actualIssuePtr_T == 4'h4 | ~_GEN_24 & robIssued_4); + robIssued_5 <= + ~commitMask_5 & (issueLoad & _actualIssuePtr_T == 4'h5 | ~_GEN_25 & robIssued_5); + robIssued_6 <= + ~commitMask_6 & (issueLoad & _actualIssuePtr_T == 4'h6 | ~_GEN_26 & robIssued_6); + robIssued_7 <= + ~commitMask_7 & (issueLoad & _actualIssuePtr_T == 4'h7 | ~_GEN_27 & robIssued_7); + robIssued_8 <= + ~commitMask_8 & (issueLoad & _actualIssuePtr_T == 4'h8 | ~_GEN_28 & robIssued_8); + robIssued_9 <= + ~commitMask_9 & (issueLoad & _actualIssuePtr_T == 4'h9 | ~_GEN_29 & robIssued_9); + robIssued_10 <= + ~commitMask_10 + & (issueLoad & _actualIssuePtr_T == 4'hA | ~_GEN_30 & robIssued_10); + robIssued_11 <= + ~commitMask_11 + & (issueLoad & _actualIssuePtr_T == 4'hB | ~_GEN_31 & robIssued_11); + robIssued_12 <= + ~commitMask_12 + & (issueLoad & _actualIssuePtr_T == 4'hC | ~_GEN_32 & robIssued_12); + robIssued_13 <= + ~commitMask_13 + & (issueLoad & _actualIssuePtr_T == 4'hD | ~_GEN_33 & robIssued_13); + robIssued_14 <= + ~commitMask_14 + & (issueLoad & _actualIssuePtr_T == 4'hE | ~_GEN_34 & robIssued_14); + robIssued_15 <= + ~commitMask_15 & (issueLoad & (&_actualIssuePtr_T) | ~_GEN_35 & robIssued_15); + robComplete_0 <= + ~commitMask_0 + & (io_complete_valid & io_complete_bits == 4'h0 | ~_GEN_20 & robComplete_0); + robComplete_1 <= + ~commitMask_1 + & (io_complete_valid & io_complete_bits == 4'h1 | ~_GEN_21 & robComplete_1); + robComplete_2 <= + ~commitMask_2 + & (io_complete_valid & io_complete_bits == 4'h2 | ~_GEN_22 & robComplete_2); + robComplete_3 <= + ~commitMask_3 + & (io_complete_valid & io_complete_bits == 4'h3 | ~_GEN_23 & robComplete_3); + robComplete_4 <= + ~commitMask_4 + & (io_complete_valid & io_complete_bits == 4'h4 | ~_GEN_24 & robComplete_4); + robComplete_5 <= + ~commitMask_5 + & (io_complete_valid & io_complete_bits == 4'h5 | ~_GEN_25 & robComplete_5); + robComplete_6 <= + ~commitMask_6 + & (io_complete_valid & io_complete_bits == 4'h6 | ~_GEN_26 & robComplete_6); + robComplete_7 <= + ~commitMask_7 + & (io_complete_valid & io_complete_bits == 4'h7 | ~_GEN_27 & robComplete_7); + robComplete_8 <= + ~commitMask_8 + & (io_complete_valid & io_complete_bits == 4'h8 | ~_GEN_28 & robComplete_8); + robComplete_9 <= + ~commitMask_9 + & (io_complete_valid & io_complete_bits == 4'h9 | ~_GEN_29 & robComplete_9); + robComplete_10 <= + ~commitMask_10 + & (io_complete_valid & io_complete_bits == 4'hA | ~_GEN_30 & robComplete_10); + robComplete_11 <= + ~commitMask_11 + & (io_complete_valid & io_complete_bits == 4'hB | ~_GEN_31 & robComplete_11); + robComplete_12 <= + ~commitMask_12 + & (io_complete_valid & io_complete_bits == 4'hC | ~_GEN_32 & robComplete_12); + robComplete_13 <= + ~commitMask_13 + & (io_complete_valid & io_complete_bits == 4'hD | ~_GEN_33 & robComplete_13); + robComplete_14 <= + ~commitMask_14 + & (io_complete_valid & io_complete_bits == 4'hE | ~_GEN_34 & robComplete_14); + robComplete_15 <= + ~commitMask_15 + & (io_complete_valid & (&io_complete_bits) | ~_GEN_35 & robComplete_15); + if (_GEN_3) + nextInstId <= nextInstId + 64'h1; + ptr <= + ptr + + {1'h0, + {1'h0, {1'h0, commitKeep_1} + {1'h0, commitKeep_2}} + + {1'h0, {1'h0, commitKeep_3} + {1'h0, commitKeep_4}}} + + {1'h0, + {1'h0, {1'h0, commitKeep_5} + {1'h0, commitKeep_6}} + + {1'h0, {1'h0, commitKeep_7} + {1'h0, commitKeep_8}}} + + {1'h0, + {1'h0, {1'h0, commitKeep_9} + {1'h0, commitScan_9}} + + {1'h0, {1'h0, commitKeep_11} + {1'h0, commitKeep_12}}} + + {1'h0, + {1'h0, {1'h0, commitKeep_13} + {1'h0, commitKeep_14}} + + {1'h0, {1'h0, commitKeep_15} + {1'h0, commitScan_15}}}; + if (_isAllocatedSlot_T_30) begin + if (&tailPtr) + tailPtr <= 4'h0; + else + tailPtr <= tailPtr + 4'h1; + end + issuedCount <= + issuedCount + {4'h0, issueLoad} + - {4'h0, io_complete_valid & _GEN_4[io_complete_bits]}; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_36; + if (_GEN_67 & (&(robEntries_15_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_66; + else if (_GEN_65 & (&(robEntries_14_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_64; + else if (_GEN_63 & (&(robEntries_13_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_62; + else if (_GEN_61 & (&(robEntries_12_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_60; + else if (_GEN_59 & (&(robEntries_11_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_58; + else if (_GEN_57 & (&(robEntries_10_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_56; + else if (_GEN_55 & (&(robEntries_9_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_54; + else if (_GEN_53 & (&(robEntries_8_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_52; + else if (_GEN_51 & (&(robEntries_7_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_50; + else if (_GEN_49 & (&(robEntries_6_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_48; + else if (_GEN_47 & (&(robEntries_5_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_46; + else if (_GEN_45 & (&(robEntries_4_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_44; + else if (_GEN_43 & (&(robEntries_3_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_42; + else if (_GEN_41 & (&(robEntries_2_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_40; + else if (_GEN_39 & (&(robEntries_1_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_38; + else if (_GEN_37 & (&(robEntries_0_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_36; + if (issueLoad | io_complete_valid) + vbankBusy <= + vbankBusy & ~(io_complete_valid ? _GEN_18[io_complete_bits] : 16'h0) + | (issueLoad ? _GEN_18[_actualIssuePtr_T] : 16'h0); + if (isAllocatedSlot) + dependencyMask_0 <= allocDependencies & ~clearMask; + else + dependencyMask_0 <= dependencyMask_0 & ~clearMask; + if (isAllocatedSlot_1) + dependencyMask_1 <= allocDependencies & ~clearMask_1; + else + dependencyMask_1 <= dependencyMask_1 & ~clearMask_1; + if (isAllocatedSlot_2) + dependencyMask_2 <= allocDependencies & ~clearMask_2; + else + dependencyMask_2 <= dependencyMask_2 & ~clearMask_2; + if (isAllocatedSlot_3) + dependencyMask_3 <= allocDependencies & ~clearMask_3; + else + dependencyMask_3 <= dependencyMask_3 & ~clearMask_3; + if (isAllocatedSlot_4) + dependencyMask_4 <= allocDependencies & ~clearMask_4; + else + dependencyMask_4 <= dependencyMask_4 & ~clearMask_4; + if (isAllocatedSlot_5) + dependencyMask_5 <= allocDependencies & ~clearMask_5; + else + dependencyMask_5 <= dependencyMask_5 & ~clearMask_5; + if (isAllocatedSlot_6) + dependencyMask_6 <= allocDependencies & ~clearMask_6; + else + dependencyMask_6 <= dependencyMask_6 & ~clearMask_6; + if (isAllocatedSlot_7) + dependencyMask_7 <= allocDependencies & ~clearMask_7; + else + dependencyMask_7 <= dependencyMask_7 & ~clearMask_7; + if (isAllocatedSlot_8) + dependencyMask_8 <= allocDependencies & ~clearMask_8; + else + dependencyMask_8 <= dependencyMask_8 & ~clearMask_8; + if (isAllocatedSlot_9) + dependencyMask_9 <= allocDependencies & ~clearMask_9; + else + dependencyMask_9 <= dependencyMask_9 & ~clearMask_9; + if (isAllocatedSlot_10) + dependencyMask_10 <= allocDependencies & ~clearMask_10; + else + dependencyMask_10 <= dependencyMask_10 & ~clearMask_10; + if (isAllocatedSlot_11) + dependencyMask_11 <= allocDependencies & ~clearMask_11; + else + dependencyMask_11 <= dependencyMask_11 & ~clearMask_11; + if (isAllocatedSlot_12) + dependencyMask_12 <= allocDependencies & ~clearMask_12; + else + dependencyMask_12 <= dependencyMask_12 & ~clearMask_12; + if (isAllocatedSlot_13) + dependencyMask_13 <= allocDependencies & ~clearMask_13; + else + dependencyMask_13 <= dependencyMask_13 & ~clearMask_13; + if (isAllocatedSlot_14) + dependencyMask_14 <= allocDependencies & ~clearMask_14; + else + dependencyMask_14 <= dependencyMask_14 & ~clearMask_14; + if (isAllocatedSlot_15) + dependencyMask_15 <= allocDependencies & ~clearMask_15; + else + dependencyMask_15 <= dependencyMask_15 & ~clearMask_15; + if (issueStageReady) + issueStageValid <= issuePtrValid; + if (issuePtrReady) + issuePtrValid <= issueLoad; + end + if (issueStageReady & issuePtrFire) begin + automatic logic [15:0] _GEN_68 = + {{robEntries_15_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_14_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_13_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_12_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_11_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_10_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_9_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_8_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_7_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_6_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_5_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_4_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_3_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_2_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_1_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_0_cmd_bankAccess_rd_bank_0_valid}}; + automatic logic issuePayload_cmd_bankAccess_rd_bank_0_valid = + _GEN_68[issuePtr]; + automatic logic [15:0][9:0] _GEN_69 = + {{robEntries_15_cmd_bankAccess_rd_bank_0_id}, + {robEntries_14_cmd_bankAccess_rd_bank_0_id}, + {robEntries_13_cmd_bankAccess_rd_bank_0_id}, + {robEntries_12_cmd_bankAccess_rd_bank_0_id}, + {robEntries_11_cmd_bankAccess_rd_bank_0_id}, + {robEntries_10_cmd_bankAccess_rd_bank_0_id}, + {robEntries_9_cmd_bankAccess_rd_bank_0_id}, + {robEntries_8_cmd_bankAccess_rd_bank_0_id}, + {robEntries_7_cmd_bankAccess_rd_bank_0_id}, + {robEntries_6_cmd_bankAccess_rd_bank_0_id}, + {robEntries_5_cmd_bankAccess_rd_bank_0_id}, + {robEntries_4_cmd_bankAccess_rd_bank_0_id}, + {robEntries_3_cmd_bankAccess_rd_bank_0_id}, + {robEntries_2_cmd_bankAccess_rd_bank_0_id}, + {robEntries_1_cmd_bankAccess_rd_bank_0_id}, + {robEntries_0_cmd_bankAccess_rd_bank_0_id}}; + automatic logic [9:0] issuePayload_cmd_bankAccess_rd_bank_0_id = + _GEN_69[issuePtr]; + automatic logic [15:0] _GEN_70 = + {{robEntries_15_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_14_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_13_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_12_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_11_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_10_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_9_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_8_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_7_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_6_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_5_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_4_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_3_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_2_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_1_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_0_cmd_bankAccess_rd_bank_1_valid}}; + automatic logic issuePayload_cmd_bankAccess_rd_bank_1_valid = + _GEN_70[issuePtr]; + automatic logic [15:0][9:0] _GEN_71 = + {{robEntries_15_cmd_bankAccess_rd_bank_1_id}, + {robEntries_14_cmd_bankAccess_rd_bank_1_id}, + {robEntries_13_cmd_bankAccess_rd_bank_1_id}, + {robEntries_12_cmd_bankAccess_rd_bank_1_id}, + {robEntries_11_cmd_bankAccess_rd_bank_1_id}, + {robEntries_10_cmd_bankAccess_rd_bank_1_id}, + {robEntries_9_cmd_bankAccess_rd_bank_1_id}, + {robEntries_8_cmd_bankAccess_rd_bank_1_id}, + {robEntries_7_cmd_bankAccess_rd_bank_1_id}, + {robEntries_6_cmd_bankAccess_rd_bank_1_id}, + {robEntries_5_cmd_bankAccess_rd_bank_1_id}, + {robEntries_4_cmd_bankAccess_rd_bank_1_id}, + {robEntries_3_cmd_bankAccess_rd_bank_1_id}, + {robEntries_2_cmd_bankAccess_rd_bank_1_id}, + {robEntries_1_cmd_bankAccess_rd_bank_1_id}, + {robEntries_0_cmd_bankAccess_rd_bank_1_id}}; + automatic logic [9:0] issuePayload_cmd_bankAccess_rd_bank_1_id = + _GEN_71[issuePtr]; + automatic logic [15:0] _GEN_72 = + {{robEntries_15_cmd_bankAccess_wr_bank_valid}, + {robEntries_14_cmd_bankAccess_wr_bank_valid}, + {robEntries_13_cmd_bankAccess_wr_bank_valid}, + {robEntries_12_cmd_bankAccess_wr_bank_valid}, + {robEntries_11_cmd_bankAccess_wr_bank_valid}, + {robEntries_10_cmd_bankAccess_wr_bank_valid}, + {robEntries_9_cmd_bankAccess_wr_bank_valid}, + {robEntries_8_cmd_bankAccess_wr_bank_valid}, + {robEntries_7_cmd_bankAccess_wr_bank_valid}, + {robEntries_6_cmd_bankAccess_wr_bank_valid}, + {robEntries_5_cmd_bankAccess_wr_bank_valid}, + {robEntries_4_cmd_bankAccess_wr_bank_valid}, + {robEntries_3_cmd_bankAccess_wr_bank_valid}, + {robEntries_2_cmd_bankAccess_wr_bank_valid}, + {robEntries_1_cmd_bankAccess_wr_bank_valid}, + {robEntries_0_cmd_bankAccess_wr_bank_valid}}; + automatic logic issuePayload_cmd_bankAccess_wr_bank_valid = + _GEN_72[issuePtr]; + automatic logic [15:0][9:0] _GEN_73 = + {{robEntries_15_cmd_bankAccess_wr_bank_id}, + {robEntries_14_cmd_bankAccess_wr_bank_id}, + {robEntries_13_cmd_bankAccess_wr_bank_id}, + {robEntries_12_cmd_bankAccess_wr_bank_id}, + {robEntries_11_cmd_bankAccess_wr_bank_id}, + {robEntries_10_cmd_bankAccess_wr_bank_id}, + {robEntries_9_cmd_bankAccess_wr_bank_id}, + {robEntries_8_cmd_bankAccess_wr_bank_id}, + {robEntries_7_cmd_bankAccess_wr_bank_id}, + {robEntries_6_cmd_bankAccess_wr_bank_id}, + {robEntries_5_cmd_bankAccess_wr_bank_id}, + {robEntries_4_cmd_bankAccess_wr_bank_id}, + {robEntries_3_cmd_bankAccess_wr_bank_id}, + {robEntries_2_cmd_bankAccess_wr_bank_id}, + {robEntries_1_cmd_bankAccess_wr_bank_id}, + {robEntries_0_cmd_bankAccess_wr_bank_id}}; + automatic logic [9:0] issuePayload_cmd_bankAccess_wr_bank_id = + _GEN_73[issuePtr]; + automatic logic [15:0][3:0] _GEN_74 = + {{bankCols_15}, + {bankCols_14}, + {bankCols_13}, + {bankCols_12}, + {bankCols_11}, + {bankCols_10}, + {bankCols_9}, + {bankCols_8}, + {bankCols_7}, + {bankCols_6}, + {bankCols_5}, + {bankCols_4}, + {bankCols_3}, + {bankCols_2}, + {bankCols_1}, + {bankCols_0}}; + automatic logic [15:0][4:0] _GEN_75 = + {{robEntries_15_cmd_ball_bid}, + {robEntries_14_cmd_ball_bid}, + {robEntries_13_cmd_ball_bid}, + {robEntries_12_cmd_ball_bid}, + {robEntries_11_cmd_ball_bid}, + {robEntries_10_cmd_ball_bid}, + {robEntries_9_cmd_ball_bid}, + {robEntries_8_cmd_ball_bid}, + {robEntries_7_cmd_ball_bid}, + {robEntries_6_cmd_ball_bid}, + {robEntries_5_cmd_ball_bid}, + {robEntries_4_cmd_ball_bid}, + {robEntries_3_cmd_ball_bid}, + {robEntries_2_cmd_ball_bid}, + {robEntries_1_cmd_ball_bid}, + {robEntries_0_cmd_ball_bid}}; + automatic logic [15:0][31:0] _GEN_76 = + {{robEntries_15_cmd_cmd_raw_inst}, + {robEntries_14_cmd_cmd_raw_inst}, + {robEntries_13_cmd_cmd_raw_inst}, + {robEntries_12_cmd_cmd_raw_inst}, + {robEntries_11_cmd_cmd_raw_inst}, + {robEntries_10_cmd_cmd_raw_inst}, + {robEntries_9_cmd_cmd_raw_inst}, + {robEntries_8_cmd_cmd_raw_inst}, + {robEntries_7_cmd_cmd_raw_inst}, + {robEntries_6_cmd_cmd_raw_inst}, + {robEntries_5_cmd_cmd_raw_inst}, + {robEntries_4_cmd_cmd_raw_inst}, + {robEntries_3_cmd_cmd_raw_inst}, + {robEntries_2_cmd_cmd_raw_inst}, + {robEntries_1_cmd_cmd_raw_inst}, + {robEntries_0_cmd_cmd_raw_inst}}; + automatic logic [15:0][2:0] _GEN_77 = + {{robEntries_15_cmd_cmd_funct3}, + {robEntries_14_cmd_cmd_funct3}, + {robEntries_13_cmd_cmd_funct3}, + {robEntries_12_cmd_cmd_funct3}, + {robEntries_11_cmd_cmd_funct3}, + {robEntries_10_cmd_cmd_funct3}, + {robEntries_9_cmd_cmd_funct3}, + {robEntries_8_cmd_cmd_funct3}, + {robEntries_7_cmd_cmd_funct3}, + {robEntries_6_cmd_cmd_funct3}, + {robEntries_5_cmd_cmd_funct3}, + {robEntries_4_cmd_cmd_funct3}, + {robEntries_3_cmd_cmd_funct3}, + {robEntries_2_cmd_cmd_funct3}, + {robEntries_1_cmd_cmd_funct3}, + {robEntries_0_cmd_cmd_funct3}}; + automatic logic [15:0][4:0] _GEN_78 = + {{robEntries_15_cmd_cmd_rs2}, + {robEntries_14_cmd_cmd_rs2}, + {robEntries_13_cmd_cmd_rs2}, + {robEntries_12_cmd_cmd_rs2}, + {robEntries_11_cmd_cmd_rs2}, + {robEntries_10_cmd_cmd_rs2}, + {robEntries_9_cmd_cmd_rs2}, + {robEntries_8_cmd_cmd_rs2}, + {robEntries_7_cmd_cmd_rs2}, + {robEntries_6_cmd_cmd_rs2}, + {robEntries_5_cmd_cmd_rs2}, + {robEntries_4_cmd_cmd_rs2}, + {robEntries_3_cmd_cmd_rs2}, + {robEntries_2_cmd_cmd_rs2}, + {robEntries_1_cmd_cmd_rs2}, + {robEntries_0_cmd_cmd_rs2}}; + automatic logic [15:0][4:0] _GEN_79 = + {{robEntries_15_cmd_cmd_rs1}, + {robEntries_14_cmd_cmd_rs1}, + {robEntries_13_cmd_cmd_rs1}, + {robEntries_12_cmd_cmd_rs1}, + {robEntries_11_cmd_cmd_rs1}, + {robEntries_10_cmd_cmd_rs1}, + {robEntries_9_cmd_cmd_rs1}, + {robEntries_8_cmd_cmd_rs1}, + {robEntries_7_cmd_cmd_rs1}, + {robEntries_6_cmd_cmd_rs1}, + {robEntries_5_cmd_cmd_rs1}, + {robEntries_4_cmd_cmd_rs1}, + {robEntries_3_cmd_cmd_rs1}, + {robEntries_2_cmd_cmd_rs1}, + {robEntries_1_cmd_cmd_rs1}, + {robEntries_0_cmd_cmd_rs1}}; + automatic logic [15:0] _GEN_80 = + {{robEntries_15_cmd_cmd_xd}, + {robEntries_14_cmd_cmd_xd}, + {robEntries_13_cmd_cmd_xd}, + {robEntries_12_cmd_cmd_xd}, + {robEntries_11_cmd_cmd_xd}, + {robEntries_10_cmd_cmd_xd}, + {robEntries_9_cmd_cmd_xd}, + {robEntries_8_cmd_cmd_xd}, + {robEntries_7_cmd_cmd_xd}, + {robEntries_6_cmd_cmd_xd}, + {robEntries_5_cmd_cmd_xd}, + {robEntries_4_cmd_cmd_xd}, + {robEntries_3_cmd_cmd_xd}, + {robEntries_2_cmd_cmd_xd}, + {robEntries_1_cmd_cmd_xd}, + {robEntries_0_cmd_cmd_xd}}; + automatic logic [15:0] _GEN_81 = + {{robEntries_15_cmd_cmd_xs1}, + {robEntries_14_cmd_cmd_xs1}, + {robEntries_13_cmd_cmd_xs1}, + {robEntries_12_cmd_cmd_xs1}, + {robEntries_11_cmd_cmd_xs1}, + {robEntries_10_cmd_cmd_xs1}, + {robEntries_9_cmd_cmd_xs1}, + {robEntries_8_cmd_cmd_xs1}, + {robEntries_7_cmd_cmd_xs1}, + {robEntries_6_cmd_cmd_xs1}, + {robEntries_5_cmd_cmd_xs1}, + {robEntries_4_cmd_cmd_xs1}, + {robEntries_3_cmd_cmd_xs1}, + {robEntries_2_cmd_cmd_xs1}, + {robEntries_1_cmd_cmd_xs1}, + {robEntries_0_cmd_cmd_xs1}}; + automatic logic [15:0] _GEN_82 = + {{robEntries_15_cmd_cmd_xs2}, + {robEntries_14_cmd_cmd_xs2}, + {robEntries_13_cmd_cmd_xs2}, + {robEntries_12_cmd_cmd_xs2}, + {robEntries_11_cmd_cmd_xs2}, + {robEntries_10_cmd_cmd_xs2}, + {robEntries_9_cmd_cmd_xs2}, + {robEntries_8_cmd_cmd_xs2}, + {robEntries_7_cmd_cmd_xs2}, + {robEntries_6_cmd_cmd_xs2}, + {robEntries_5_cmd_cmd_xs2}, + {robEntries_4_cmd_cmd_xs2}, + {robEntries_3_cmd_cmd_xs2}, + {robEntries_2_cmd_cmd_xs2}, + {robEntries_1_cmd_cmd_xs2}, + {robEntries_0_cmd_cmd_xs2}}; + automatic logic [15:0][4:0] _GEN_83 = + {{robEntries_15_cmd_cmd_rd}, + {robEntries_14_cmd_cmd_rd}, + {robEntries_13_cmd_cmd_rd}, + {robEntries_12_cmd_cmd_rd}, + {robEntries_11_cmd_cmd_rd}, + {robEntries_10_cmd_cmd_rd}, + {robEntries_9_cmd_cmd_rd}, + {robEntries_8_cmd_cmd_rd}, + {robEntries_7_cmd_cmd_rd}, + {robEntries_6_cmd_cmd_rd}, + {robEntries_5_cmd_cmd_rd}, + {robEntries_4_cmd_cmd_rd}, + {robEntries_3_cmd_cmd_rd}, + {robEntries_2_cmd_cmd_rd}, + {robEntries_1_cmd_cmd_rd}, + {robEntries_0_cmd_cmd_rd}}; + automatic logic [15:0][6:0] _GEN_84 = + {{robEntries_15_cmd_cmd_opcode}, + {robEntries_14_cmd_cmd_opcode}, + {robEntries_13_cmd_cmd_opcode}, + {robEntries_12_cmd_cmd_opcode}, + {robEntries_11_cmd_cmd_opcode}, + {robEntries_10_cmd_cmd_opcode}, + {robEntries_9_cmd_cmd_opcode}, + {robEntries_8_cmd_cmd_opcode}, + {robEntries_7_cmd_cmd_opcode}, + {robEntries_6_cmd_cmd_opcode}, + {robEntries_5_cmd_cmd_opcode}, + {robEntries_4_cmd_cmd_opcode}, + {robEntries_3_cmd_cmd_opcode}, + {robEntries_2_cmd_cmd_opcode}, + {robEntries_1_cmd_cmd_opcode}, + {robEntries_0_cmd_cmd_opcode}}; + automatic logic [15:0] _GEN_85 = + {{robEntries_15_cmd_isFence}, + {robEntries_14_cmd_isFence}, + {robEntries_13_cmd_isFence}, + {robEntries_12_cmd_isFence}, + {robEntries_11_cmd_isFence}, + {robEntries_10_cmd_isFence}, + {robEntries_9_cmd_isFence}, + {robEntries_8_cmd_isFence}, + {robEntries_7_cmd_isFence}, + {robEntries_6_cmd_isFence}, + {robEntries_5_cmd_isFence}, + {robEntries_4_cmd_isFence}, + {robEntries_3_cmd_isFence}, + {robEntries_2_cmd_isFence}, + {robEntries_1_cmd_isFence}, + {robEntries_0_cmd_isFence}}; + automatic logic [15:0] _GEN_86 = + {{robEntries_15_cmd_isBarrier}, + {robEntries_14_cmd_isBarrier}, + {robEntries_13_cmd_isBarrier}, + {robEntries_12_cmd_isBarrier}, + {robEntries_11_cmd_isBarrier}, + {robEntries_10_cmd_isBarrier}, + {robEntries_9_cmd_isBarrier}, + {robEntries_8_cmd_isBarrier}, + {robEntries_7_cmd_isBarrier}, + {robEntries_6_cmd_isBarrier}, + {robEntries_5_cmd_isBarrier}, + {robEntries_4_cmd_isBarrier}, + {robEntries_3_cmd_isBarrier}, + {robEntries_2_cmd_isBarrier}, + {robEntries_1_cmd_isBarrier}, + {robEntries_0_cmd_isBarrier}}; + issueStageEntry_cmd_domain_id <= _GEN_5[issuePtr]; + issueStageEntry_cmd_ball_bid <= _GEN_75[issuePtr]; + issueStageEntry_cmd_cmd_raw_inst <= _GEN_76[issuePtr]; + issueStageEntry_cmd_cmd_pc <= _GEN_6[issuePtr]; + issueStageEntry_cmd_cmd_funct <= _GEN_7[issuePtr]; + issueStageEntry_cmd_cmd_funct3 <= _GEN_77[issuePtr]; + issueStageEntry_cmd_cmd_rs2 <= _GEN_78[issuePtr]; + issueStageEntry_cmd_cmd_rs1 <= _GEN_79[issuePtr]; + issueStageEntry_cmd_cmd_xd <= _GEN_80[issuePtr]; + issueStageEntry_cmd_cmd_xs1 <= _GEN_81[issuePtr]; + issueStageEntry_cmd_cmd_xs2 <= _GEN_82[issuePtr]; + issueStageEntry_cmd_cmd_rd <= _GEN_83[issuePtr]; + issueStageEntry_cmd_cmd_opcode <= _GEN_84[issuePtr]; + issueStageEntry_cmd_cmd_rs1Data <= _GEN_8[issuePtr]; + issueStageEntry_cmd_cmd_rs2Data <= _GEN_9[issuePtr]; + issueStageEntry_cmd_bankAccess_rd_bank_0_valid <= + issuePayload_cmd_bankAccess_rd_bank_0_valid; + issueStageEntry_cmd_bankAccess_rd_bank_0_id <= + issuePayload_cmd_bankAccess_rd_bank_0_id; + issueStageEntry_cmd_bankAccess_rd_bank_1_valid <= + issuePayload_cmd_bankAccess_rd_bank_1_valid; + issueStageEntry_cmd_bankAccess_rd_bank_1_id <= + issuePayload_cmd_bankAccess_rd_bank_1_id; + issueStageEntry_cmd_bankAccess_wr_bank_valid <= + issuePayload_cmd_bankAccess_wr_bank_valid; + issueStageEntry_cmd_bankAccess_wr_bank_id <= issuePayload_cmd_bankAccess_wr_bank_id; + issueStageEntry_cmd_op1_col <= + issuePayload_cmd_bankAccess_rd_bank_0_valid + ? _GEN_74[issuePayload_cmd_bankAccess_rd_bank_0_id[3:0]] + : 4'h0; + issueStageEntry_cmd_op2_col <= + issuePayload_cmd_bankAccess_rd_bank_1_valid + ? _GEN_74[issuePayload_cmd_bankAccess_rd_bank_1_id[3:0]] + : 4'h0; + issueStageEntry_cmd_wr_col <= + issuePayload_cmd_bankAccess_wr_bank_valid + ? _GEN_74[issuePayload_cmd_bankAccess_wr_bank_id[3:0]] + : 4'h0; + issueStageEntry_cmd_isFence <= _GEN_85[issuePtr]; + issueStageEntry_cmd_isBarrier <= _GEN_86[issuePtr]; + issueStageEntry_renamedBankAccess_rd_bank_0_valid <= _GEN_13[issuePtr]; + issueStageEntry_renamedBankAccess_rd_bank_0_id <= _GEN_14[issuePtr]; + issueStageEntry_renamedBankAccess_rd_bank_1_valid <= _GEN_15[issuePtr]; + issueStageEntry_renamedBankAccess_rd_bank_1_id <= _GEN_16[issuePtr]; + issueStageEntry_renamedBankAccess_wr_bank_valid <= _GEN_10[issuePtr]; + issueStageEntry_renamedBankAccess_wr_bank_id <= _GEN_11[issuePtr]; + issueStageEntry_rob_id <= _GEN_19[issuePtr]; + end + if (issuePtrReady & issueLoad) + issuePtr <= _actualIssuePtr_T; + end // always @(posedge) + BankAliasTable bat ( + .clock (clock), + .reset (reset), + .io_alloc_valid (_isAllocatedSlot_T_30), + .io_alloc_rob_id (tailPtr), + .io_alloc_raw_rd_bank_0_valid (io_alloc_bits_bankAccess_rd_bank_0_valid), + .io_alloc_raw_rd_bank_0_id (io_alloc_bits_bankAccess_rd_bank_0_id), + .io_alloc_raw_rd_bank_1_valid (io_alloc_bits_bankAccess_rd_bank_1_valid), + .io_alloc_raw_rd_bank_1_id (io_alloc_bits_bankAccess_rd_bank_1_id), + .io_alloc_raw_wr_bank_valid (io_alloc_bits_bankAccess_wr_bank_valid), + .io_alloc_raw_wr_bank_id (io_alloc_bits_bankAccess_wr_bank_id), + .io_alloc_renamed_rd_bank_0_valid (_bat_io_alloc_renamed_rd_bank_0_valid), + .io_alloc_renamed_rd_bank_0_id (_bat_io_alloc_renamed_rd_bank_0_id), + .io_alloc_renamed_rd_bank_1_valid (_bat_io_alloc_renamed_rd_bank_1_valid), + .io_alloc_renamed_rd_bank_1_id (_bat_io_alloc_renamed_rd_bank_1_id), + .io_alloc_renamed_wr_bank_valid (_bat_io_alloc_renamed_wr_bank_valid), + .io_alloc_renamed_wr_bank_id (_bat_io_alloc_renamed_wr_bank_id), + .io_free_valid + (|{commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0}), + .io_free_mask_0 (commitMask_0), + .io_free_mask_1 (commitMask_1), + .io_free_mask_2 (commitMask_2), + .io_free_mask_3 (commitMask_3), + .io_free_mask_4 (commitMask_4), + .io_free_mask_5 (commitMask_5), + .io_free_mask_6 (commitMask_6), + .io_free_mask_7 (commitMask_7), + .io_free_mask_8 (commitMask_8), + .io_free_mask_9 (commitMask_9), + .io_free_mask_10 (commitMask_10), + .io_free_mask_11 (commitMask_11), + .io_free_mask_12 (commitMask_12), + .io_free_mask_13 (commitMask_13), + .io_free_mask_14 (commitMask_14), + .io_free_mask_15 (commitMask_15) + ); + BankScoreboard scoreboard ( + .clock (clock), + .reset (reset), + .alloc_valid + (_isAllocatedSlot_T_30 & io_alloc_bits_bankAccess_wr_bank_valid), + .alloc_bits_wr_bank_valid (_bat_io_alloc_renamed_wr_bank_valid), + .alloc_bits_wr_bank_id (_bat_io_alloc_renamed_wr_bank_id), + .complete_valid (io_complete_valid), + .complete_bits_wr_bank_valid (io_complete_valid & _GEN_10[io_complete_bits]), + .complete_bits_wr_bank_id (io_complete_valid ? _GEN_11[io_complete_bits] : 10'h0), + .queryVec_0_rd_bank_0_valid (_GEN_13[ptr]), + .queryVec_0_rd_bank_0_id (_GEN_14[ptr]), + .queryVec_0_rd_bank_1_valid (_GEN_15[ptr]), + .queryVec_0_rd_bank_1_id (_GEN_16[ptr]), + .queryVec_1_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1446]), + .queryVec_1_rd_bank_0_id (_GEN_14[_hits_ptr_T_1446]), + .queryVec_1_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1446]), + .queryVec_1_rd_bank_1_id (_GEN_16[_hits_ptr_T_1446]), + .queryVec_2_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1452]), + .queryVec_2_rd_bank_0_id (_GEN_14[_hits_ptr_T_1452]), + .queryVec_2_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1452]), + .queryVec_2_rd_bank_1_id (_GEN_16[_hits_ptr_T_1452]), + .queryVec_3_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1458]), + .queryVec_3_rd_bank_0_id (_GEN_14[_hits_ptr_T_1458]), + .queryVec_3_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1458]), + .queryVec_3_rd_bank_1_id (_GEN_16[_hits_ptr_T_1458]), + .queryVec_4_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1464]), + .queryVec_4_rd_bank_0_id (_GEN_14[_hits_ptr_T_1464]), + .queryVec_4_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1464]), + .queryVec_4_rd_bank_1_id (_GEN_16[_hits_ptr_T_1464]), + .queryVec_5_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1470]), + .queryVec_5_rd_bank_0_id (_GEN_14[_hits_ptr_T_1470]), + .queryVec_5_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1470]), + .queryVec_5_rd_bank_1_id (_GEN_16[_hits_ptr_T_1470]), + .queryVec_6_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1476]), + .queryVec_6_rd_bank_0_id (_GEN_14[_hits_ptr_T_1476]), + .queryVec_6_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1476]), + .queryVec_6_rd_bank_1_id (_GEN_16[_hits_ptr_T_1476]), + .queryVec_7_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1482]), + .queryVec_7_rd_bank_0_id (_GEN_14[_hits_ptr_T_1482]), + .queryVec_7_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1482]), + .queryVec_7_rd_bank_1_id (_GEN_16[_hits_ptr_T_1482]), + .queryVec_8_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1488]), + .queryVec_8_rd_bank_0_id (_GEN_14[_hits_ptr_T_1488]), + .queryVec_8_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1488]), + .queryVec_8_rd_bank_1_id (_GEN_16[_hits_ptr_T_1488]), + .queryVec_9_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1494]), + .queryVec_9_rd_bank_0_id (_GEN_14[_hits_ptr_T_1494]), + .queryVec_9_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1494]), + .queryVec_9_rd_bank_1_id (_GEN_16[_hits_ptr_T_1494]), + .queryVec_10_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1500]), + .queryVec_10_rd_bank_0_id (_GEN_14[_hits_ptr_T_1500]), + .queryVec_10_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1500]), + .queryVec_10_rd_bank_1_id (_GEN_16[_hits_ptr_T_1500]), + .queryVec_11_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1506]), + .queryVec_11_rd_bank_0_id (_GEN_14[_hits_ptr_T_1506]), + .queryVec_11_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1506]), + .queryVec_11_rd_bank_1_id (_GEN_16[_hits_ptr_T_1506]), + .queryVec_12_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1512]), + .queryVec_12_rd_bank_0_id (_GEN_14[_hits_ptr_T_1512]), + .queryVec_12_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1512]), + .queryVec_12_rd_bank_1_id (_GEN_16[_hits_ptr_T_1512]), + .queryVec_13_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1518]), + .queryVec_13_rd_bank_0_id (_GEN_14[_hits_ptr_T_1518]), + .queryVec_13_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1518]), + .queryVec_13_rd_bank_1_id (_GEN_16[_hits_ptr_T_1518]), + .queryVec_14_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1524]), + .queryVec_14_rd_bank_0_id (_GEN_14[_hits_ptr_T_1524]), + .queryVec_14_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1524]), + .queryVec_14_rd_bank_1_id (_GEN_16[_hits_ptr_T_1524]), + .queryVec_15_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1530]), + .queryVec_15_rd_bank_0_id (_GEN_14[_hits_ptr_T_1530]), + .queryVec_15_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1530]), + .queryVec_15_rd_bank_1_id (_GEN_16[_hits_ptr_T_1530]), + .hazardVec_0 (_scoreboard_hazardVec_0), + .hazardVec_1 (_scoreboard_hazardVec_1), + .hazardVec_2 (_scoreboard_hazardVec_2), + .hazardVec_3 (_scoreboard_hazardVec_3), + .hazardVec_4 (_scoreboard_hazardVec_4), + .hazardVec_5 (_scoreboard_hazardVec_5), + .hazardVec_6 (_scoreboard_hazardVec_6), + .hazardVec_7 (_scoreboard_hazardVec_7), + .hazardVec_8 (_scoreboard_hazardVec_8), + .hazardVec_9 (_scoreboard_hazardVec_9), + .hazardVec_10 (_scoreboard_hazardVec_10), + .hazardVec_11 (_scoreboard_hazardVec_11), + .hazardVec_12 (_scoreboard_hazardVec_12), + .hazardVec_13 (_scoreboard_hazardVec_13), + .hazardVec_14 (_scoreboard_hazardVec_14), + .hazardVec_15 (_scoreboard_hazardVec_15) + ); + ITraceDPI itraceAlloc ( + .clock (clock), + .reset (reset), + .is_issue ({6'h0, _isAllocatedSlot_T_30, 1'h0}), + .hart_id (64'h0), + .rob_id (_isAllocatedSlot_T_30 ? {28'h0, tailPtr} : 32'h0), + .inst_id (_GEN_3 ? nextInstId : 64'h0), + .domain_id (_isAllocatedSlot_T_30 ? {28'h0, io_alloc_bits_domain_id} : 32'h0), + .funct (_isAllocatedSlot_T_30 ? {25'h0, io_alloc_bits_cmd_funct} : 32'h0), + .pc (_isAllocatedSlot_T_30 ? io_alloc_bits_cmd_pc : 64'h0), + .rs1_data (_isAllocatedSlot_T_30 ? io_alloc_bits_cmd_rs1Data : 64'h0), + .rs2_data (_isAllocatedSlot_T_30 ? io_alloc_bits_cmd_rs2Data : 64'h0), + .enable (_isAllocatedSlot_T_30) + ); + ITraceDPI itraceIssue ( + .clock (clock), + .reset (reset), + .is_issue ({7'h0, issueLoad}), + .hart_id (64'h0), + .rob_id (issueLoad ? {28'h0, _GEN_19[_actualIssuePtr_T]} : 32'h0), + .inst_id (issueLoad ? _GEN_12[_actualIssuePtr_T] : 64'h0), + .domain_id (issueLoad ? {28'h0, _GEN_5[_actualIssuePtr_T]} : 32'h0), + .funct (issueLoad ? {25'h0, _GEN_7[_actualIssuePtr_T]} : 32'h0), + .pc (issueLoad ? _GEN_6[_actualIssuePtr_T] : 64'h0), + .rs1_data (issueLoad ? _GEN_8[_actualIssuePtr_T] : 64'h0), + .rs2_data (issueLoad ? _GEN_9[_actualIssuePtr_T] : 64'h0), + .enable (issueLoad) + ); + ITraceDPI itraceComp ( + .clock (clock), + .reset (reset), + .is_issue (8'h0), + .hart_id (64'h0), + .rob_id (io_complete_valid ? {28'h0, io_complete_bits} : 32'h0), + .inst_id (io_complete_valid ? _GEN_12[io_complete_bits] : 64'h0), + .domain_id (io_complete_valid ? {28'h0, _GEN_5[io_complete_bits]} : 32'h0), + .funct (io_complete_valid ? {25'h0, _GEN_7[io_complete_bits]} : 32'h0), + .pc (io_complete_valid ? _GEN_6[io_complete_bits] : 64'h0), + .rs1_data (io_complete_valid ? _GEN_8[io_complete_bits] : 64'h0), + .rs2_data (io_complete_valid ? _GEN_9[io_complete_bits] : 64'h0), + .enable (io_complete_valid) + ); + assign io_alloc_ready = io_alloc_ready_0; + assign io_issue_valid = issueStageValid & ~io_subRobActive; + assign io_issue_bits_cmd_domain_id = issueStageEntry_cmd_domain_id; + assign io_issue_bits_cmd_ball_bid = issueStageEntry_cmd_ball_bid; + assign io_issue_bits_cmd_cmd_raw_inst = issueStageEntry_cmd_cmd_raw_inst; + assign io_issue_bits_cmd_cmd_pc = issueStageEntry_cmd_cmd_pc; + assign io_issue_bits_cmd_cmd_funct = issueStageEntry_cmd_cmd_funct; + assign io_issue_bits_cmd_cmd_funct3 = issueStageEntry_cmd_cmd_funct3; + assign io_issue_bits_cmd_cmd_rs2 = issueStageEntry_cmd_cmd_rs2; + assign io_issue_bits_cmd_cmd_rs1 = issueStageEntry_cmd_cmd_rs1; + assign io_issue_bits_cmd_cmd_xd = issueStageEntry_cmd_cmd_xd; + assign io_issue_bits_cmd_cmd_xs1 = issueStageEntry_cmd_cmd_xs1; + assign io_issue_bits_cmd_cmd_xs2 = issueStageEntry_cmd_cmd_xs2; + assign io_issue_bits_cmd_cmd_rd = issueStageEntry_cmd_cmd_rd; + assign io_issue_bits_cmd_cmd_opcode = issueStageEntry_cmd_cmd_opcode; + assign io_issue_bits_cmd_cmd_rs1Data = issueStageEntry_cmd_cmd_rs1Data; + assign io_issue_bits_cmd_cmd_rs2Data = issueStageEntry_cmd_cmd_rs2Data; + assign io_issue_bits_cmd_bankAccess_rd_bank_0_valid = + issueStageEntry_cmd_bankAccess_rd_bank_0_valid; + assign io_issue_bits_cmd_bankAccess_rd_bank_0_id = + issueStageEntry_cmd_bankAccess_rd_bank_0_id; + assign io_issue_bits_cmd_bankAccess_rd_bank_1_valid = + issueStageEntry_cmd_bankAccess_rd_bank_1_valid; + assign io_issue_bits_cmd_bankAccess_rd_bank_1_id = + issueStageEntry_cmd_bankAccess_rd_bank_1_id; + assign io_issue_bits_cmd_bankAccess_wr_bank_valid = + issueStageEntry_cmd_bankAccess_wr_bank_valid; + assign io_issue_bits_cmd_bankAccess_wr_bank_id = + issueStageEntry_cmd_bankAccess_wr_bank_id; + assign io_issue_bits_cmd_op1_col = issueStageEntry_cmd_op1_col; + assign io_issue_bits_cmd_op2_col = issueStageEntry_cmd_op2_col; + assign io_issue_bits_cmd_wr_col = issueStageEntry_cmd_wr_col; + assign io_issue_bits_cmd_isFence = issueStageEntry_cmd_isFence; + assign io_issue_bits_cmd_isBarrier = issueStageEntry_cmd_isBarrier; + assign io_issue_bits_renamedBankAccess_rd_bank_0_valid = + issueStageEntry_renamedBankAccess_rd_bank_0_valid; + assign io_issue_bits_renamedBankAccess_rd_bank_0_id = + issueStageEntry_renamedBankAccess_rd_bank_0_id; + assign io_issue_bits_renamedBankAccess_rd_bank_1_valid = + issueStageEntry_renamedBankAccess_rd_bank_1_valid; + assign io_issue_bits_renamedBankAccess_rd_bank_1_id = + issueStageEntry_renamedBankAccess_rd_bank_1_id; + assign io_issue_bits_renamedBankAccess_wr_bank_valid = + issueStageEntry_renamedBankAccess_wr_bank_valid; + assign io_issue_bits_renamedBankAccess_wr_bank_id = + issueStageEntry_renamedBankAccess_wr_bank_id; + assign io_issue_bits_rob_id = issueStageEntry_rob_id; + assign io_empty = _isFull_T & ~_GEN_0; + assign io_full = isFull; + assign io_head_ptr = ptr; + assign io_issued_count = issuedCount; + assign io_entry_valid_0 = robValid_0; + assign io_entry_valid_1 = robValid_1; + assign io_entry_valid_2 = robValid_2; + assign io_entry_valid_3 = robValid_3; + assign io_entry_valid_4 = robValid_4; + assign io_entry_valid_5 = robValid_5; + assign io_entry_valid_6 = robValid_6; + assign io_entry_valid_7 = robValid_7; + assign io_entry_valid_8 = robValid_8; + assign io_entry_valid_9 = robValid_9; + assign io_entry_valid_10 = robValid_10; + assign io_entry_valid_11 = robValid_11; + assign io_entry_valid_12 = robValid_12; + assign io_entry_valid_13 = robValid_13; + assign io_entry_valid_14 = robValid_14; + assign io_entry_valid_15 = robValid_15; + assign io_entry_complete_0 = robComplete_0; + assign io_entry_complete_1 = robComplete_1; + assign io_entry_complete_2 = robComplete_2; + assign io_entry_complete_3 = robComplete_3; + assign io_entry_complete_4 = robComplete_4; + assign io_entry_complete_5 = robComplete_5; + assign io_entry_complete_6 = robComplete_6; + assign io_entry_complete_7 = robComplete_7; + assign io_entry_complete_8 = robComplete_8; + assign io_entry_complete_9 = robComplete_9; + assign io_entry_complete_10 = robComplete_10; + assign io_entry_complete_11 = robComplete_11; + assign io_entry_complete_12 = robComplete_12; + assign io_entry_complete_13 = robComplete_13; + assign io_entry_complete_14 = robComplete_14; + assign io_entry_complete_15 = robComplete_15; + assign io_inst_ids_0 = instIds_0; + assign io_inst_ids_1 = instIds_1; + assign io_inst_ids_2 = instIds_2; + assign io_inst_ids_3 = instIds_3; + assign io_inst_ids_4 = instIds_4; + assign io_inst_ids_5 = instIds_5; + assign io_inst_ids_6 = instIds_6; + assign io_inst_ids_7 = instIds_7; + assign io_inst_ids_8 = instIds_8; + assign io_inst_ids_9 = instIds_9; + assign io_inst_ids_10 = instIds_10; + assign io_inst_ids_11 = instIds_11; + assign io_inst_ids_12 = instIds_12; + assign io_inst_ids_13 = instIds_13; + assign io_inst_ids_14 = instIds_14; + assign io_inst_ids_15 = instIds_15; +endmodule + +// VCS coverage exclude_file +module ram_2x303( + input R0_addr, + R0_en, + R0_clk, + output [302:0] R0_data, + input W0_addr, + W0_en, + W0_clk, + input [302:0] W0_data +); + + reg [302:0] Memory[0:1]; + always @(posedge W0_clk) begin + if (W0_en & 1'h1) + Memory[W0_addr] <= W0_data; + end // always @(posedge) + assign R0_data = R0_en ? Memory[R0_addr] : 303'bx; +endmodule + +module Queue2_PostGDCmd( + input clock, + reset, + io_enq_valid, + input [3:0] io_enq_bits_domain_id, + input [31:0] io_enq_bits_cmd_raw_inst, + input [63:0] io_enq_bits_cmd_pc, + input [6:0] io_enq_bits_cmd_funct, + input [63:0] io_enq_bits_cmd_rs1Data, + io_enq_bits_cmd_rs2Data, + input io_enq_bits_bankAccess_rd_bank_0_valid, + input [9:0] io_enq_bits_bankAccess_rd_bank_0_id, + input io_enq_bits_bankAccess_rd_bank_1_valid, + input [9:0] io_enq_bits_bankAccess_rd_bank_1_id, + input io_enq_bits_bankAccess_wr_bank_valid, + input [9:0] io_enq_bits_bankAccess_wr_bank_id, + input io_deq_ready, + output io_deq_valid, + output [3:0] io_deq_bits_domain_id, + output [4:0] io_deq_bits_ball_bid, + output [31:0] io_deq_bits_cmd_raw_inst, + output [63:0] io_deq_bits_cmd_pc, + output [6:0] io_deq_bits_cmd_funct, + output [2:0] io_deq_bits_cmd_funct3, + output [4:0] io_deq_bits_cmd_rs2, + io_deq_bits_cmd_rs1, + output io_deq_bits_cmd_xd, + io_deq_bits_cmd_xs1, + io_deq_bits_cmd_xs2, + output [4:0] io_deq_bits_cmd_rd, + output [6:0] io_deq_bits_cmd_opcode, + output [63:0] io_deq_bits_cmd_rs1Data, + io_deq_bits_cmd_rs2Data, + output io_deq_bits_bankAccess_rd_bank_0_valid, + output [9:0] io_deq_bits_bankAccess_rd_bank_0_id, + output io_deq_bits_bankAccess_rd_bank_1_valid, + output [9:0] io_deq_bits_bankAccess_rd_bank_1_id, + output io_deq_bits_bankAccess_wr_bank_valid, + output [9:0] io_deq_bits_bankAccess_wr_bank_id, + output io_deq_bits_isFence, + io_deq_bits_isBarrier +); + + wire io_enq_ready; + wire [302:0] _ram_ext_R0_data; + reg wrap; + reg wrap_1; + reg maybe_full; + wire ptr_match = wrap == wrap_1; + wire empty = ptr_match & ~maybe_full; + wire do_enq = io_enq_ready & io_enq_valid; + assign io_enq_ready = ~(ptr_match & maybe_full); + always @(posedge clock) begin + if (reset) begin + wrap <= 1'h0; + wrap_1 <= 1'h0; + maybe_full <= 1'h0; + end + else begin + automatic logic do_deq = io_deq_ready & ~empty; + if (do_enq) + wrap <= wrap - 1'h1; + if (do_deq) + wrap_1 <= wrap_1 - 1'h1; + if (~(do_enq == do_deq)) + maybe_full <= do_enq; + end + end // always @(posedge) + ram_2x303 ram_ext ( + .R0_addr (wrap_1), + .R0_en (1'h1), + .R0_clk (clock), + .R0_data (_ram_ext_R0_data), + .W0_addr (wrap), + .W0_en (do_enq), + .W0_clk (clock), + .W0_data + ({2'h0, + io_enq_bits_bankAccess_wr_bank_id, + io_enq_bits_bankAccess_wr_bank_valid, + io_enq_bits_bankAccess_rd_bank_1_id, + io_enq_bits_bankAccess_rd_bank_1_valid, + io_enq_bits_bankAccess_rd_bank_0_id, + io_enq_bits_bankAccess_rd_bank_0_valid, + io_enq_bits_cmd_rs2Data, + io_enq_bits_cmd_rs1Data, + 28'h0, + io_enq_bits_cmd_funct, + io_enq_bits_cmd_pc, + io_enq_bits_cmd_raw_inst, + 5'h0, + io_enq_bits_domain_id}) + ); + assign io_deq_valid = ~empty; + assign io_deq_bits_domain_id = _ram_ext_R0_data[3:0]; + assign io_deq_bits_ball_bid = _ram_ext_R0_data[8:4]; + assign io_deq_bits_cmd_raw_inst = _ram_ext_R0_data[40:9]; + assign io_deq_bits_cmd_pc = _ram_ext_R0_data[104:41]; + assign io_deq_bits_cmd_funct = _ram_ext_R0_data[111:105]; + assign io_deq_bits_cmd_funct3 = _ram_ext_R0_data[114:112]; + assign io_deq_bits_cmd_rs2 = _ram_ext_R0_data[119:115]; + assign io_deq_bits_cmd_rs1 = _ram_ext_R0_data[124:120]; + assign io_deq_bits_cmd_xd = _ram_ext_R0_data[125]; + assign io_deq_bits_cmd_xs1 = _ram_ext_R0_data[126]; + assign io_deq_bits_cmd_xs2 = _ram_ext_R0_data[127]; + assign io_deq_bits_cmd_rd = _ram_ext_R0_data[132:128]; + assign io_deq_bits_cmd_opcode = _ram_ext_R0_data[139:133]; + assign io_deq_bits_cmd_rs1Data = _ram_ext_R0_data[203:140]; + assign io_deq_bits_cmd_rs2Data = _ram_ext_R0_data[267:204]; + assign io_deq_bits_bankAccess_rd_bank_0_valid = _ram_ext_R0_data[268]; + assign io_deq_bits_bankAccess_rd_bank_0_id = _ram_ext_R0_data[278:269]; + assign io_deq_bits_bankAccess_rd_bank_1_valid = _ram_ext_R0_data[279]; + assign io_deq_bits_bankAccess_rd_bank_1_id = _ram_ext_R0_data[289:280]; + assign io_deq_bits_bankAccess_wr_bank_valid = _ram_ext_R0_data[290]; + assign io_deq_bits_bankAccess_wr_bank_id = _ram_ext_R0_data[300:291]; + assign io_deq_bits_isFence = _ram_ext_R0_data[301]; + assign io_deq_bits_isBarrier = _ram_ext_R0_data[302]; +endmodule + +// VCS coverage exclude_file +module ram_16x4( + input [3:0] R0_addr, + input R0_en, + R0_clk, + output [3:0] R0_data, + input [3:0] W0_addr, + input W0_en, + W0_clk, + input [3:0] W0_data +); + + reg [3:0] Memory[0:15]; + always @(posedge W0_clk) begin + if (W0_en & 1'h1) + Memory[W0_addr] <= W0_data; + end // always @(posedge) + assign R0_data = R0_en ? Memory[R0_addr] : 4'bx; +endmodule + +module Queue16_UInt4( + input clock, + reset, + output io_enq_ready, + input io_enq_valid, + input [3:0] io_enq_bits, + input io_deq_ready, + output io_deq_valid, + output [3:0] io_deq_bits +); + + reg [3:0] enq_ptr_value; + reg [3:0] deq_ptr_value; + reg maybe_full; + wire ptr_match = enq_ptr_value == deq_ptr_value; + wire empty = ptr_match & ~maybe_full; + wire full = ptr_match & maybe_full; + wire do_enq = ~full & io_enq_valid; + always @(posedge clock) begin + if (reset) begin + enq_ptr_value <= 4'h0; + deq_ptr_value <= 4'h0; + maybe_full <= 1'h0; + end + else begin + automatic logic do_deq = io_deq_ready & ~empty; + if (do_enq) + enq_ptr_value <= enq_ptr_value + 4'h1; + if (do_deq) + deq_ptr_value <= deq_ptr_value + 4'h1; + if (~(do_enq == do_deq)) + maybe_full <= do_enq; + end + end // always @(posedge) + ram_16x4 ram_ext ( + .R0_addr (deq_ptr_value), + .R0_en (1'h1), + .R0_clk (clock), + .R0_data (io_deq_bits), + .W0_addr (enq_ptr_value), + .W0_en (do_enq), + .W0_clk (clock), + .W0_data (io_enq_bits) + ); + assign io_enq_ready = ~full; + assign io_deq_valid = ~empty; +endmodule + +module GlobalRobCheck( + input clock, + reset, + input [31:0] seed, + output passed +); + + wire _completions_io_enq_ready; + wire _completions_io_deq_valid; + wire [3:0] _completions_io_deq_bits; + wire _source_io_deq_valid; + wire [3:0] _source_io_deq_bits_domain_id; + wire [4:0] _source_io_deq_bits_ball_bid; + wire [31:0] _source_io_deq_bits_cmd_raw_inst; + wire [63:0] _source_io_deq_bits_cmd_pc; + wire [6:0] _source_io_deq_bits_cmd_funct; + wire [2:0] _source_io_deq_bits_cmd_funct3; + wire [4:0] _source_io_deq_bits_cmd_rs2; + wire [4:0] _source_io_deq_bits_cmd_rs1; + wire _source_io_deq_bits_cmd_xd; + wire _source_io_deq_bits_cmd_xs1; + wire _source_io_deq_bits_cmd_xs2; + wire [4:0] _source_io_deq_bits_cmd_rd; + wire [6:0] _source_io_deq_bits_cmd_opcode; + wire [63:0] _source_io_deq_bits_cmd_rs1Data; + wire [63:0] _source_io_deq_bits_cmd_rs2Data; + wire _source_io_deq_bits_bankAccess_rd_bank_0_valid; + wire [9:0] _source_io_deq_bits_bankAccess_rd_bank_0_id; + wire _source_io_deq_bits_bankAccess_rd_bank_1_valid; + wire [9:0] _source_io_deq_bits_bankAccess_rd_bank_1_id; + wire _source_io_deq_bits_bankAccess_wr_bank_valid; + wire [9:0] _source_io_deq_bits_bankAccess_wr_bank_id; + wire _source_io_deq_bits_isFence; + wire _source_io_deq_bits_isBarrier; + wire _reference_io_alloc_ready; + wire _reference_io_issue_valid; + wire [3:0] _reference_io_issue_bits_cmd_domain_id; + wire [4:0] _reference_io_issue_bits_cmd_ball_bid; + wire [31:0] _reference_io_issue_bits_cmd_cmd_raw_inst; + wire [63:0] _reference_io_issue_bits_cmd_cmd_pc; + wire [6:0] _reference_io_issue_bits_cmd_cmd_funct; + wire [2:0] _reference_io_issue_bits_cmd_cmd_funct3; + wire [4:0] _reference_io_issue_bits_cmd_cmd_rs2; + wire [4:0] _reference_io_issue_bits_cmd_cmd_rs1; + wire _reference_io_issue_bits_cmd_cmd_xd; + wire _reference_io_issue_bits_cmd_cmd_xs1; + wire _reference_io_issue_bits_cmd_cmd_xs2; + wire [4:0] _reference_io_issue_bits_cmd_cmd_rd; + wire [6:0] _reference_io_issue_bits_cmd_cmd_opcode; + wire [63:0] _reference_io_issue_bits_cmd_cmd_rs1Data; + wire [63:0] _reference_io_issue_bits_cmd_cmd_rs2Data; + wire _reference_io_issue_bits_cmd_bankAccess_rd_bank_0_valid; + wire [9:0] _reference_io_issue_bits_cmd_bankAccess_rd_bank_0_id; + wire _reference_io_issue_bits_cmd_bankAccess_rd_bank_1_valid; + wire [9:0] _reference_io_issue_bits_cmd_bankAccess_rd_bank_1_id; + wire _reference_io_issue_bits_cmd_bankAccess_wr_bank_valid; + wire [9:0] _reference_io_issue_bits_cmd_bankAccess_wr_bank_id; + wire [3:0] _reference_io_issue_bits_cmd_op1_col; + wire [3:0] _reference_io_issue_bits_cmd_op2_col; + wire [3:0] _reference_io_issue_bits_cmd_wr_col; + wire _reference_io_issue_bits_cmd_isFence; + wire _reference_io_issue_bits_cmd_isBarrier; + wire _reference_io_issue_bits_renamedBankAccess_rd_bank_0_valid; + wire [9:0] _reference_io_issue_bits_renamedBankAccess_rd_bank_0_id; + wire _reference_io_issue_bits_renamedBankAccess_rd_bank_1_valid; + wire [9:0] _reference_io_issue_bits_renamedBankAccess_rd_bank_1_id; + wire _reference_io_issue_bits_renamedBankAccess_wr_bank_valid; + wire [9:0] _reference_io_issue_bits_renamedBankAccess_wr_bank_id; + wire [3:0] _reference_io_issue_bits_rob_id; + wire _reference_io_empty; + wire _reference_io_full; + wire [3:0] _reference_io_head_ptr; + wire [4:0] _reference_io_issued_count; + wire _reference_io_entry_valid_0; + wire _reference_io_entry_valid_1; + wire _reference_io_entry_valid_2; + wire _reference_io_entry_valid_3; + wire _reference_io_entry_valid_4; + wire _reference_io_entry_valid_5; + wire _reference_io_entry_valid_6; + wire _reference_io_entry_valid_7; + wire _reference_io_entry_valid_8; + wire _reference_io_entry_valid_9; + wire _reference_io_entry_valid_10; + wire _reference_io_entry_valid_11; + wire _reference_io_entry_valid_12; + wire _reference_io_entry_valid_13; + wire _reference_io_entry_valid_14; + wire _reference_io_entry_valid_15; + wire _reference_io_entry_complete_0; + wire _reference_io_entry_complete_1; + wire _reference_io_entry_complete_2; + wire _reference_io_entry_complete_3; + wire _reference_io_entry_complete_4; + wire _reference_io_entry_complete_5; + wire _reference_io_entry_complete_6; + wire _reference_io_entry_complete_7; + wire _reference_io_entry_complete_8; + wire _reference_io_entry_complete_9; + wire _reference_io_entry_complete_10; + wire _reference_io_entry_complete_11; + wire _reference_io_entry_complete_12; + wire _reference_io_entry_complete_13; + wire _reference_io_entry_complete_14; + wire _reference_io_entry_complete_15; + wire [63:0] _reference_io_inst_ids_0; + wire [63:0] _reference_io_inst_ids_1; + wire [63:0] _reference_io_inst_ids_2; + wire [63:0] _reference_io_inst_ids_3; + wire [63:0] _reference_io_inst_ids_4; + wire [63:0] _reference_io_inst_ids_5; + wire [63:0] _reference_io_inst_ids_6; + wire [63:0] _reference_io_inst_ids_7; + wire [63:0] _reference_io_inst_ids_8; + wire [63:0] _reference_io_inst_ids_9; + wire [63:0] _reference_io_inst_ids_10; + wire [63:0] _reference_io_inst_ids_11; + wire [63:0] _reference_io_inst_ids_12; + wire [63:0] _reference_io_inst_ids_13; + wire [63:0] _reference_io_inst_ids_14; + wire [63:0] _reference_io_inst_ids_15; + wire _dut_io_alloc_ready; + wire _dut_io_issue_valid; + wire [3:0] _dut_io_issue_bits_cmd_domain_id; + wire [4:0] _dut_io_issue_bits_cmd_ball_bid; + wire [31:0] _dut_io_issue_bits_cmd_cmd_raw_inst; + wire [63:0] _dut_io_issue_bits_cmd_cmd_pc; + wire [6:0] _dut_io_issue_bits_cmd_cmd_funct; + wire [2:0] _dut_io_issue_bits_cmd_cmd_funct3; + wire [4:0] _dut_io_issue_bits_cmd_cmd_rs2; + wire [4:0] _dut_io_issue_bits_cmd_cmd_rs1; + wire _dut_io_issue_bits_cmd_cmd_xd; + wire _dut_io_issue_bits_cmd_cmd_xs1; + wire _dut_io_issue_bits_cmd_cmd_xs2; + wire [4:0] _dut_io_issue_bits_cmd_cmd_rd; + wire [6:0] _dut_io_issue_bits_cmd_cmd_opcode; + wire [63:0] _dut_io_issue_bits_cmd_cmd_rs1Data; + wire [63:0] _dut_io_issue_bits_cmd_cmd_rs2Data; + wire _dut_io_issue_bits_cmd_bankAccess_rd_bank_0_valid; + wire [9:0] _dut_io_issue_bits_cmd_bankAccess_rd_bank_0_id; + wire _dut_io_issue_bits_cmd_bankAccess_rd_bank_1_valid; + wire [9:0] _dut_io_issue_bits_cmd_bankAccess_rd_bank_1_id; + wire _dut_io_issue_bits_cmd_bankAccess_wr_bank_valid; + wire [9:0] _dut_io_issue_bits_cmd_bankAccess_wr_bank_id; + wire [3:0] _dut_io_issue_bits_cmd_op1_col; + wire [3:0] _dut_io_issue_bits_cmd_op2_col; + wire [3:0] _dut_io_issue_bits_cmd_wr_col; + wire _dut_io_issue_bits_cmd_isFence; + wire _dut_io_issue_bits_cmd_isBarrier; + wire _dut_io_issue_bits_renamedBankAccess_rd_bank_0_valid; + wire [9:0] _dut_io_issue_bits_renamedBankAccess_rd_bank_0_id; + wire _dut_io_issue_bits_renamedBankAccess_rd_bank_1_valid; + wire [9:0] _dut_io_issue_bits_renamedBankAccess_rd_bank_1_id; + wire _dut_io_issue_bits_renamedBankAccess_wr_bank_valid; + wire [9:0] _dut_io_issue_bits_renamedBankAccess_wr_bank_id; + wire [3:0] _dut_io_issue_bits_rob_id; + wire _dut_io_empty; + wire _dut_io_full; + wire [3:0] _dut_io_head_ptr; + wire [4:0] _dut_io_issued_count; + wire _dut_io_entry_valid_0; + wire _dut_io_entry_valid_1; + wire _dut_io_entry_valid_2; + wire _dut_io_entry_valid_3; + wire _dut_io_entry_valid_4; + wire _dut_io_entry_valid_5; + wire _dut_io_entry_valid_6; + wire _dut_io_entry_valid_7; + wire _dut_io_entry_valid_8; + wire _dut_io_entry_valid_9; + wire _dut_io_entry_valid_10; + wire _dut_io_entry_valid_11; + wire _dut_io_entry_valid_12; + wire _dut_io_entry_valid_13; + wire _dut_io_entry_valid_14; + wire _dut_io_entry_valid_15; + wire _dut_io_entry_complete_0; + wire _dut_io_entry_complete_1; + wire _dut_io_entry_complete_2; + wire _dut_io_entry_complete_3; + wire _dut_io_entry_complete_4; + wire _dut_io_entry_complete_5; + wire _dut_io_entry_complete_6; + wire _dut_io_entry_complete_7; + wire _dut_io_entry_complete_8; + wire _dut_io_entry_complete_9; + wire _dut_io_entry_complete_10; + wire _dut_io_entry_complete_11; + wire _dut_io_entry_complete_12; + wire _dut_io_entry_complete_13; + wire _dut_io_entry_complete_14; + wire _dut_io_entry_complete_15; + wire [63:0] _dut_io_inst_ids_0; + wire [63:0] _dut_io_inst_ids_1; + wire [63:0] _dut_io_inst_ids_2; + wire [63:0] _dut_io_inst_ids_3; + wire [63:0] _dut_io_inst_ids_4; + wire [63:0] _dut_io_inst_ids_5; + wire [63:0] _dut_io_inst_ids_6; + wire [63:0] _dut_io_inst_ids_7; + wire [63:0] _dut_io_inst_ids_8; + wire [63:0] _dut_io_inst_ids_9; + wire [63:0] _dut_io_inst_ids_10; + wire [63:0] _dut_io_inst_ids_11; + wire [63:0] _dut_io_inst_ids_12; + wire [63:0] _dut_io_inst_ids_13; + wire [63:0] _dut_io_inst_ids_14; + wire [63:0] _dut_io_inst_ids_15; + reg [15:0] cycle; + reg [31:0] random; + wire active = cycle[9:6] == 4'hD; + wire ready = _completions_io_enq_ready & random[7] & cycle[8:5] != 4'h7; + wire _completions_io_enq_valid_T = ready & _dut_io_issue_valid; + wire _dut_io_complete_valid_T_1 = _completions_io_deq_valid & random[4]; + reg [15:0] allocated; + reg [15:0] issued; + reg [15:0] completed; + reg sawFull; + reg sawStall; + reg [31:0] expected_0_raw_inst; + reg [63:0] expected_0_pc; + reg [6:0] expected_0_funct; + reg [2:0] expected_0_funct3; + reg [4:0] expected_0_rs2; + reg [4:0] expected_0_rs1; + reg expected_0_xd; + reg expected_0_xs1; + reg expected_0_xs2; + reg [4:0] expected_0_rd; + reg [6:0] expected_0_opcode; + reg [63:0] expected_0_rs1Data; + reg [63:0] expected_0_rs2Data; + reg [31:0] expected_1_raw_inst; + reg [63:0] expected_1_pc; + reg [6:0] expected_1_funct; + reg [2:0] expected_1_funct3; + reg [4:0] expected_1_rs2; + reg [4:0] expected_1_rs1; + reg expected_1_xd; + reg expected_1_xs1; + reg expected_1_xs2; + reg [4:0] expected_1_rd; + reg [6:0] expected_1_opcode; + reg [63:0] expected_1_rs1Data; + reg [63:0] expected_1_rs2Data; + reg [31:0] expected_2_raw_inst; + reg [63:0] expected_2_pc; + reg [6:0] expected_2_funct; + reg [2:0] expected_2_funct3; + reg [4:0] expected_2_rs2; + reg [4:0] expected_2_rs1; + reg expected_2_xd; + reg expected_2_xs1; + reg expected_2_xs2; + reg [4:0] expected_2_rd; + reg [6:0] expected_2_opcode; + reg [63:0] expected_2_rs1Data; + reg [63:0] expected_2_rs2Data; + reg [31:0] expected_3_raw_inst; + reg [63:0] expected_3_pc; + reg [6:0] expected_3_funct; + reg [2:0] expected_3_funct3; + reg [4:0] expected_3_rs2; + reg [4:0] expected_3_rs1; + reg expected_3_xd; + reg expected_3_xs1; + reg expected_3_xs2; + reg [4:0] expected_3_rd; + reg [6:0] expected_3_opcode; + reg [63:0] expected_3_rs1Data; + reg [63:0] expected_3_rs2Data; + reg [31:0] expected_4_raw_inst; + reg [63:0] expected_4_pc; + reg [6:0] expected_4_funct; + reg [2:0] expected_4_funct3; + reg [4:0] expected_4_rs2; + reg [4:0] expected_4_rs1; + reg expected_4_xd; + reg expected_4_xs1; + reg expected_4_xs2; + reg [4:0] expected_4_rd; + reg [6:0] expected_4_opcode; + reg [63:0] expected_4_rs1Data; + reg [63:0] expected_4_rs2Data; + reg [31:0] expected_5_raw_inst; + reg [63:0] expected_5_pc; + reg [6:0] expected_5_funct; + reg [2:0] expected_5_funct3; + reg [4:0] expected_5_rs2; + reg [4:0] expected_5_rs1; + reg expected_5_xd; + reg expected_5_xs1; + reg expected_5_xs2; + reg [4:0] expected_5_rd; + reg [6:0] expected_5_opcode; + reg [63:0] expected_5_rs1Data; + reg [63:0] expected_5_rs2Data; + reg [31:0] expected_6_raw_inst; + reg [63:0] expected_6_pc; + reg [6:0] expected_6_funct; + reg [2:0] expected_6_funct3; + reg [4:0] expected_6_rs2; + reg [4:0] expected_6_rs1; + reg expected_6_xd; + reg expected_6_xs1; + reg expected_6_xs2; + reg [4:0] expected_6_rd; + reg [6:0] expected_6_opcode; + reg [63:0] expected_6_rs1Data; + reg [63:0] expected_6_rs2Data; + reg [31:0] expected_7_raw_inst; + reg [63:0] expected_7_pc; + reg [6:0] expected_7_funct; + reg [2:0] expected_7_funct3; + reg [4:0] expected_7_rs2; + reg [4:0] expected_7_rs1; + reg expected_7_xd; + reg expected_7_xs1; + reg expected_7_xs2; + reg [4:0] expected_7_rd; + reg [6:0] expected_7_opcode; + reg [63:0] expected_7_rs1Data; + reg [63:0] expected_7_rs2Data; + reg [31:0] expected_8_raw_inst; + reg [63:0] expected_8_pc; + reg [6:0] expected_8_funct; + reg [2:0] expected_8_funct3; + reg [4:0] expected_8_rs2; + reg [4:0] expected_8_rs1; + reg expected_8_xd; + reg expected_8_xs1; + reg expected_8_xs2; + reg [4:0] expected_8_rd; + reg [6:0] expected_8_opcode; + reg [63:0] expected_8_rs1Data; + reg [63:0] expected_8_rs2Data; + reg [31:0] expected_9_raw_inst; + reg [63:0] expected_9_pc; + reg [6:0] expected_9_funct; + reg [2:0] expected_9_funct3; + reg [4:0] expected_9_rs2; + reg [4:0] expected_9_rs1; + reg expected_9_xd; + reg expected_9_xs1; + reg expected_9_xs2; + reg [4:0] expected_9_rd; + reg [6:0] expected_9_opcode; + reg [63:0] expected_9_rs1Data; + reg [63:0] expected_9_rs2Data; + reg [31:0] expected_10_raw_inst; + reg [63:0] expected_10_pc; + reg [6:0] expected_10_funct; + reg [2:0] expected_10_funct3; + reg [4:0] expected_10_rs2; + reg [4:0] expected_10_rs1; + reg expected_10_xd; + reg expected_10_xs1; + reg expected_10_xs2; + reg [4:0] expected_10_rd; + reg [6:0] expected_10_opcode; + reg [63:0] expected_10_rs1Data; + reg [63:0] expected_10_rs2Data; + reg [31:0] expected_11_raw_inst; + reg [63:0] expected_11_pc; + reg [6:0] expected_11_funct; + reg [2:0] expected_11_funct3; + reg [4:0] expected_11_rs2; + reg [4:0] expected_11_rs1; + reg expected_11_xd; + reg expected_11_xs1; + reg expected_11_xs2; + reg [4:0] expected_11_rd; + reg [6:0] expected_11_opcode; + reg [63:0] expected_11_rs1Data; + reg [63:0] expected_11_rs2Data; + reg [31:0] expected_12_raw_inst; + reg [63:0] expected_12_pc; + reg [6:0] expected_12_funct; + reg [2:0] expected_12_funct3; + reg [4:0] expected_12_rs2; + reg [4:0] expected_12_rs1; + reg expected_12_xd; + reg expected_12_xs1; + reg expected_12_xs2; + reg [4:0] expected_12_rd; + reg [6:0] expected_12_opcode; + reg [63:0] expected_12_rs1Data; + reg [63:0] expected_12_rs2Data; + reg [31:0] expected_13_raw_inst; + reg [63:0] expected_13_pc; + reg [6:0] expected_13_funct; + reg [2:0] expected_13_funct3; + reg [4:0] expected_13_rs2; + reg [4:0] expected_13_rs1; + reg expected_13_xd; + reg expected_13_xs1; + reg expected_13_xs2; + reg [4:0] expected_13_rd; + reg [6:0] expected_13_opcode; + reg [63:0] expected_13_rs1Data; + reg [63:0] expected_13_rs2Data; + reg [31:0] expected_14_raw_inst; + reg [63:0] expected_14_pc; + reg [6:0] expected_14_funct; + reg [2:0] expected_14_funct3; + reg [4:0] expected_14_rs2; + reg [4:0] expected_14_rs1; + reg expected_14_xd; + reg expected_14_xs1; + reg expected_14_xs2; + reg [4:0] expected_14_rd; + reg [6:0] expected_14_opcode; + reg [63:0] expected_14_rs1Data; + reg [63:0] expected_14_rs2Data; + reg [31:0] expected_15_raw_inst; + reg [63:0] expected_15_pc; + reg [6:0] expected_15_funct; + reg [2:0] expected_15_funct3; + reg [4:0] expected_15_rs2; + reg [4:0] expected_15_rs1; + reg expected_15_xd; + reg expected_15_xs1; + reg expected_15_xs2; + reg [4:0] expected_15_rd; + reg [6:0] expected_15_opcode; + reg [63:0] expected_15_rs1Data; + reg [63:0] expected_15_rs2Data; + reg [3:0] allocationSlot; + wire _passed_output = + cycle > 16'h138D & ~_source_io_deq_valid & _dut_io_empty & ~_completions_io_deq_valid; + `ifndef SYNTHESIS + always @(posedge clock) begin + automatic logic _GEN = _passed_output & ~reset; + automatic logic [15:0][63:0] _GEN_0 = + {{expected_15_rs2Data}, + {expected_14_rs2Data}, + {expected_13_rs2Data}, + {expected_12_rs2Data}, + {expected_11_rs2Data}, + {expected_10_rs2Data}, + {expected_9_rs2Data}, + {expected_8_rs2Data}, + {expected_7_rs2Data}, + {expected_6_rs2Data}, + {expected_5_rs2Data}, + {expected_4_rs2Data}, + {expected_3_rs2Data}, + {expected_2_rs2Data}, + {expected_1_rs2Data}, + {expected_0_rs2Data}}; + automatic logic [15:0][63:0] _GEN_1 = + {{expected_15_rs1Data}, + {expected_14_rs1Data}, + {expected_13_rs1Data}, + {expected_12_rs1Data}, + {expected_11_rs1Data}, + {expected_10_rs1Data}, + {expected_9_rs1Data}, + {expected_8_rs1Data}, + {expected_7_rs1Data}, + {expected_6_rs1Data}, + {expected_5_rs1Data}, + {expected_4_rs1Data}, + {expected_3_rs1Data}, + {expected_2_rs1Data}, + {expected_1_rs1Data}, + {expected_0_rs1Data}}; + automatic logic [15:0][6:0] _GEN_2 = + {{expected_15_opcode}, + {expected_14_opcode}, + {expected_13_opcode}, + {expected_12_opcode}, + {expected_11_opcode}, + {expected_10_opcode}, + {expected_9_opcode}, + {expected_8_opcode}, + {expected_7_opcode}, + {expected_6_opcode}, + {expected_5_opcode}, + {expected_4_opcode}, + {expected_3_opcode}, + {expected_2_opcode}, + {expected_1_opcode}, + {expected_0_opcode}}; + automatic logic [15:0][4:0] _GEN_3 = + {{expected_15_rd}, + {expected_14_rd}, + {expected_13_rd}, + {expected_12_rd}, + {expected_11_rd}, + {expected_10_rd}, + {expected_9_rd}, + {expected_8_rd}, + {expected_7_rd}, + {expected_6_rd}, + {expected_5_rd}, + {expected_4_rd}, + {expected_3_rd}, + {expected_2_rd}, + {expected_1_rd}, + {expected_0_rd}}; + automatic logic [15:0] _GEN_4 = + {{expected_15_xs2}, + {expected_14_xs2}, + {expected_13_xs2}, + {expected_12_xs2}, + {expected_11_xs2}, + {expected_10_xs2}, + {expected_9_xs2}, + {expected_8_xs2}, + {expected_7_xs2}, + {expected_6_xs2}, + {expected_5_xs2}, + {expected_4_xs2}, + {expected_3_xs2}, + {expected_2_xs2}, + {expected_1_xs2}, + {expected_0_xs2}}; + automatic logic [15:0] _GEN_5 = + {{expected_15_xs1}, + {expected_14_xs1}, + {expected_13_xs1}, + {expected_12_xs1}, + {expected_11_xs1}, + {expected_10_xs1}, + {expected_9_xs1}, + {expected_8_xs1}, + {expected_7_xs1}, + {expected_6_xs1}, + {expected_5_xs1}, + {expected_4_xs1}, + {expected_3_xs1}, + {expected_2_xs1}, + {expected_1_xs1}, + {expected_0_xs1}}; + automatic logic [15:0] _GEN_6 = + {{expected_15_xd}, + {expected_14_xd}, + {expected_13_xd}, + {expected_12_xd}, + {expected_11_xd}, + {expected_10_xd}, + {expected_9_xd}, + {expected_8_xd}, + {expected_7_xd}, + {expected_6_xd}, + {expected_5_xd}, + {expected_4_xd}, + {expected_3_xd}, + {expected_2_xd}, + {expected_1_xd}, + {expected_0_xd}}; + automatic logic [15:0][4:0] _GEN_7 = + {{expected_15_rs1}, + {expected_14_rs1}, + {expected_13_rs1}, + {expected_12_rs1}, + {expected_11_rs1}, + {expected_10_rs1}, + {expected_9_rs1}, + {expected_8_rs1}, + {expected_7_rs1}, + {expected_6_rs1}, + {expected_5_rs1}, + {expected_4_rs1}, + {expected_3_rs1}, + {expected_2_rs1}, + {expected_1_rs1}, + {expected_0_rs1}}; + automatic logic [15:0][4:0] _GEN_8 = + {{expected_15_rs2}, + {expected_14_rs2}, + {expected_13_rs2}, + {expected_12_rs2}, + {expected_11_rs2}, + {expected_10_rs2}, + {expected_9_rs2}, + {expected_8_rs2}, + {expected_7_rs2}, + {expected_6_rs2}, + {expected_5_rs2}, + {expected_4_rs2}, + {expected_3_rs2}, + {expected_2_rs2}, + {expected_1_rs2}, + {expected_0_rs2}}; + automatic logic [15:0][2:0] _GEN_9 = + {{expected_15_funct3}, + {expected_14_funct3}, + {expected_13_funct3}, + {expected_12_funct3}, + {expected_11_funct3}, + {expected_10_funct3}, + {expected_9_funct3}, + {expected_8_funct3}, + {expected_7_funct3}, + {expected_6_funct3}, + {expected_5_funct3}, + {expected_4_funct3}, + {expected_3_funct3}, + {expected_2_funct3}, + {expected_1_funct3}, + {expected_0_funct3}}; + automatic logic [15:0][6:0] _GEN_10 = + {{expected_15_funct}, + {expected_14_funct}, + {expected_13_funct}, + {expected_12_funct}, + {expected_11_funct}, + {expected_10_funct}, + {expected_9_funct}, + {expected_8_funct}, + {expected_7_funct}, + {expected_6_funct}, + {expected_5_funct}, + {expected_4_funct}, + {expected_3_funct}, + {expected_2_funct}, + {expected_1_funct}, + {expected_0_funct}}; + automatic logic [15:0][63:0] _GEN_11 = + {{expected_15_pc}, + {expected_14_pc}, + {expected_13_pc}, + {expected_12_pc}, + {expected_11_pc}, + {expected_10_pc}, + {expected_9_pc}, + {expected_8_pc}, + {expected_7_pc}, + {expected_6_pc}, + {expected_5_pc}, + {expected_4_pc}, + {expected_3_pc}, + {expected_2_pc}, + {expected_1_pc}, + {expected_0_pc}}; + automatic logic [15:0][31:0] _GEN_12 = + {{expected_15_raw_inst}, + {expected_14_raw_inst}, + {expected_13_raw_inst}, + {expected_12_raw_inst}, + {expected_11_raw_inst}, + {expected_10_raw_inst}, + {expected_9_raw_inst}, + {expected_8_raw_inst}, + {expected_7_raw_inst}, + {expected_6_raw_inst}, + {expected_5_raw_inst}, + {expected_4_raw_inst}, + {expected_3_raw_inst}, + {expected_2_raw_inst}, + {expected_1_raw_inst}, + {expected_0_raw_inst}}; + if (~reset & cycle > 16'h2327) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: GlobalROB drain timeout\n at EmitGlobalRobCheck.scala:21 assert(cycle < 9000.U, \"GlobalROB drain timeout\")\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & _dut_io_alloc_ready != _reference_io_alloc_ready) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: ROB allocation timing mismatch\n at EmitGlobalRobCheck.scala:65 assert(dut.io.alloc.ready === reference.io.alloc.ready, \"ROB allocation timing mismatch\")\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & _dut_io_issue_valid != _reference_io_issue_valid) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: ROB issue timing mismatch\n at EmitGlobalRobCheck.scala:67 assert(dut.io.issue.valid === reference.io.issue.valid, \"ROB issue timing mismatch\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_dut_io_issue_valid & ~reset + & {_dut_io_issue_bits_cmd_domain_id, + _dut_io_issue_bits_cmd_ball_bid, + _dut_io_issue_bits_cmd_cmd_raw_inst, + _dut_io_issue_bits_cmd_cmd_pc, + _dut_io_issue_bits_cmd_cmd_funct, + _dut_io_issue_bits_cmd_cmd_funct3, + _dut_io_issue_bits_cmd_cmd_rs2, + _dut_io_issue_bits_cmd_cmd_rs1, + _dut_io_issue_bits_cmd_cmd_xd, + _dut_io_issue_bits_cmd_cmd_xs1, + _dut_io_issue_bits_cmd_cmd_xs2, + _dut_io_issue_bits_cmd_cmd_rd, + _dut_io_issue_bits_cmd_cmd_opcode, + _dut_io_issue_bits_cmd_cmd_rs1Data, + _dut_io_issue_bits_cmd_cmd_rs2Data, + _dut_io_issue_bits_cmd_bankAccess_rd_bank_0_valid, + _dut_io_issue_bits_cmd_bankAccess_rd_bank_0_id, + _dut_io_issue_bits_cmd_bankAccess_rd_bank_1_valid, + _dut_io_issue_bits_cmd_bankAccess_rd_bank_1_id, + _dut_io_issue_bits_cmd_bankAccess_wr_bank_valid, + _dut_io_issue_bits_cmd_bankAccess_wr_bank_id, + _dut_io_issue_bits_cmd_op1_col, + _dut_io_issue_bits_cmd_op2_col, + _dut_io_issue_bits_cmd_wr_col, + _dut_io_issue_bits_cmd_isFence, + _dut_io_issue_bits_cmd_isBarrier, + _dut_io_issue_bits_renamedBankAccess_rd_bank_0_valid, + _dut_io_issue_bits_renamedBankAccess_rd_bank_0_id, + _dut_io_issue_bits_renamedBankAccess_rd_bank_1_valid, + _dut_io_issue_bits_renamedBankAccess_rd_bank_1_id, + _dut_io_issue_bits_renamedBankAccess_wr_bank_valid, + _dut_io_issue_bits_renamedBankAccess_wr_bank_id, + _dut_io_issue_bits_rob_id} != {_reference_io_issue_bits_cmd_domain_id, + _reference_io_issue_bits_cmd_ball_bid, + _reference_io_issue_bits_cmd_cmd_raw_inst, + _reference_io_issue_bits_cmd_cmd_pc, + _reference_io_issue_bits_cmd_cmd_funct, + _reference_io_issue_bits_cmd_cmd_funct3, + _reference_io_issue_bits_cmd_cmd_rs2, + _reference_io_issue_bits_cmd_cmd_rs1, + _reference_io_issue_bits_cmd_cmd_xd, + _reference_io_issue_bits_cmd_cmd_xs1, + _reference_io_issue_bits_cmd_cmd_xs2, + _reference_io_issue_bits_cmd_cmd_rd, + _reference_io_issue_bits_cmd_cmd_opcode, + _reference_io_issue_bits_cmd_cmd_rs1Data, + _reference_io_issue_bits_cmd_cmd_rs2Data, + _reference_io_issue_bits_cmd_bankAccess_rd_bank_0_valid, + _reference_io_issue_bits_cmd_bankAccess_rd_bank_0_id, + _reference_io_issue_bits_cmd_bankAccess_rd_bank_1_valid, + _reference_io_issue_bits_cmd_bankAccess_rd_bank_1_id, + _reference_io_issue_bits_cmd_bankAccess_wr_bank_valid, + _reference_io_issue_bits_cmd_bankAccess_wr_bank_id, + _reference_io_issue_bits_cmd_op1_col, + _reference_io_issue_bits_cmd_op2_col, + _reference_io_issue_bits_cmd_wr_col, + _reference_io_issue_bits_cmd_isFence, + _reference_io_issue_bits_cmd_isBarrier, + _reference_io_issue_bits_renamedBankAccess_rd_bank_0_valid, + _reference_io_issue_bits_renamedBankAccess_rd_bank_0_id, + _reference_io_issue_bits_renamedBankAccess_rd_bank_1_valid, + _reference_io_issue_bits_renamedBankAccess_rd_bank_1_id, + _reference_io_issue_bits_renamedBankAccess_wr_bank_valid, + _reference_io_issue_bits_renamedBankAccess_wr_bank_id, + _reference_io_issue_bits_rob_id}) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: ROB issue payload mismatch\n at EmitGlobalRobCheck.scala:69 assert(dut.io.issue.bits.asUInt === reference.io.issue.bits.asUInt, \"ROB issue payload mismatch\")\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset + & ~(_dut_io_empty == _reference_io_empty + & _dut_io_full == _reference_io_full)) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitGlobalRobCheck.scala:71 assert(dut.io.empty === reference.io.empty && dut.io.full === reference.io.full)\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & _dut_io_head_ptr != _reference_io_head_ptr) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitGlobalRobCheck.scala:72 assert(dut.io.head_ptr === reference.io.head_ptr)\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & _dut_io_issued_count != _reference_io_issued_count) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitGlobalRobCheck.scala:73 assert(dut.io.issued_count === reference.io.issued_count)\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset + & {_dut_io_entry_valid_15, + _dut_io_entry_valid_14, + _dut_io_entry_valid_13, + _dut_io_entry_valid_12, + _dut_io_entry_valid_11, + _dut_io_entry_valid_10, + _dut_io_entry_valid_9, + _dut_io_entry_valid_8, + _dut_io_entry_valid_7, + _dut_io_entry_valid_6, + _dut_io_entry_valid_5, + _dut_io_entry_valid_4, + _dut_io_entry_valid_3, + _dut_io_entry_valid_2, + _dut_io_entry_valid_1, + _dut_io_entry_valid_0} != {_reference_io_entry_valid_15, + _reference_io_entry_valid_14, + _reference_io_entry_valid_13, + _reference_io_entry_valid_12, + _reference_io_entry_valid_11, + _reference_io_entry_valid_10, + _reference_io_entry_valid_9, + _reference_io_entry_valid_8, + _reference_io_entry_valid_7, + _reference_io_entry_valid_6, + _reference_io_entry_valid_5, + _reference_io_entry_valid_4, + _reference_io_entry_valid_3, + _reference_io_entry_valid_2, + _reference_io_entry_valid_1, + _reference_io_entry_valid_0}) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitGlobalRobCheck.scala:74 assert(dut.io.entry_valid.asUInt === reference.io.entry_valid.asUInt)\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset + & {_dut_io_entry_complete_15, + _dut_io_entry_complete_14, + _dut_io_entry_complete_13, + _dut_io_entry_complete_12, + _dut_io_entry_complete_11, + _dut_io_entry_complete_10, + _dut_io_entry_complete_9, + _dut_io_entry_complete_8, + _dut_io_entry_complete_7, + _dut_io_entry_complete_6, + _dut_io_entry_complete_5, + _dut_io_entry_complete_4, + _dut_io_entry_complete_3, + _dut_io_entry_complete_2, + _dut_io_entry_complete_1, + _dut_io_entry_complete_0} != {_reference_io_entry_complete_15, + _reference_io_entry_complete_14, + _reference_io_entry_complete_13, + _reference_io_entry_complete_12, + _reference_io_entry_complete_11, + _reference_io_entry_complete_10, + _reference_io_entry_complete_9, + _reference_io_entry_complete_8, + _reference_io_entry_complete_7, + _reference_io_entry_complete_6, + _reference_io_entry_complete_5, + _reference_io_entry_complete_4, + _reference_io_entry_complete_3, + _reference_io_entry_complete_2, + _reference_io_entry_complete_1, + _reference_io_entry_complete_0}) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitGlobalRobCheck.scala:75 assert(dut.io.entry_complete.asUInt === reference.io.entry_complete.asUInt)\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset + & {_dut_io_inst_ids_15, + _dut_io_inst_ids_14, + _dut_io_inst_ids_13, + _dut_io_inst_ids_12, + _dut_io_inst_ids_11, + _dut_io_inst_ids_10, + _dut_io_inst_ids_9, + _dut_io_inst_ids_8, + _dut_io_inst_ids_7, + _dut_io_inst_ids_6, + _dut_io_inst_ids_5, + _dut_io_inst_ids_4, + _dut_io_inst_ids_3, + _dut_io_inst_ids_2, + _dut_io_inst_ids_1, + _dut_io_inst_ids_0} != {_reference_io_inst_ids_15, + _reference_io_inst_ids_14, + _reference_io_inst_ids_13, + _reference_io_inst_ids_12, + _reference_io_inst_ids_11, + _reference_io_inst_ids_10, + _reference_io_inst_ids_9, + _reference_io_inst_ids_8, + _reference_io_inst_ids_7, + _reference_io_inst_ids_6, + _reference_io_inst_ids_5, + _reference_io_inst_ids_4, + _reference_io_inst_ids_3, + _reference_io_inst_ids_2, + _reference_io_inst_ids_1, + _reference_io_inst_ids_0}) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitGlobalRobCheck.scala:76 assert(dut.io.inst_ids.asUInt === reference.io.inst_ids.asUInt)\n"); + if (`STOP_COND_) + $fatal; + end + if (_completions_io_enq_valid_T & ~reset + & {_dut_io_issue_bits_cmd_cmd_raw_inst, + _dut_io_issue_bits_cmd_cmd_pc, + _dut_io_issue_bits_cmd_cmd_funct, + _dut_io_issue_bits_cmd_cmd_funct3, + _dut_io_issue_bits_cmd_cmd_rs2, + _dut_io_issue_bits_cmd_cmd_rs1, + _dut_io_issue_bits_cmd_cmd_xd, + _dut_io_issue_bits_cmd_cmd_xs1, + _dut_io_issue_bits_cmd_cmd_xs2, + _dut_io_issue_bits_cmd_cmd_rd, + _dut_io_issue_bits_cmd_cmd_opcode, + _dut_io_issue_bits_cmd_cmd_rs1Data, + _dut_io_issue_bits_cmd_cmd_rs2Data} != {_GEN_12[_dut_io_issue_bits_rob_id], + _GEN_11[_dut_io_issue_bits_rob_id], + _GEN_10[_dut_io_issue_bits_rob_id], + _GEN_9[_dut_io_issue_bits_rob_id], + _GEN_8[_dut_io_issue_bits_rob_id], + _GEN_7[_dut_io_issue_bits_rob_id], + _GEN_6[_dut_io_issue_bits_rob_id], + _GEN_5[_dut_io_issue_bits_rob_id], + _GEN_4[_dut_io_issue_bits_rob_id], + _GEN_3[_dut_io_issue_bits_rob_id], + _GEN_2[_dut_io_issue_bits_rob_id], + _GEN_1[_dut_io_issue_bits_rob_id], + _GEN_0[_dut_io_issue_bits_rob_id]}) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: ROB changed accepted command operands\n at EmitGlobalRobCheck.scala:93 assert(dut.io.issue.bits.cmd.cmd.asUInt === expected(dut.io.issue.bits.rob_id).asUInt,\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN & ~(allocated == issued & issued == completed & allocated > 16'h40)) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitGlobalRobCheck.scala:101 assert(allocated === issued && issued === completed && allocated > 64.U)\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN & ~(sawFull & sawStall)) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: Missing ROB full/stall coverage\n at EmitGlobalRobCheck.scala:102 assert(sawFull && sawStall, \"Missing ROB full/stall coverage\")\n"); + if (`STOP_COND_) + $fatal; + end + end // always @(posedge) + `endif // not def SYNTHESIS + always @(posedge clock) begin + automatic logic _GEN_13; + _GEN_13 = _dut_io_alloc_ready & _source_io_deq_valid; + if (reset) begin + cycle <= 16'h0; + random <= seed; + allocated <= 16'h0; + issued <= 16'h0; + completed <= 16'h0; + sawFull <= 1'h0; + sawStall <= 1'h0; + allocationSlot <= 4'h0; + end + else begin + cycle <= cycle + 16'h1; + random <= {random[30:0], random[31] ^ random[21] ^ random[1] ^ random[0]}; + if (_GEN_13) begin + allocated <= allocated + 16'h1; + if (&allocationSlot) + allocationSlot <= 4'h0; + else + allocationSlot <= allocationSlot + 4'h1; + end + if (_completions_io_enq_valid_T) + issued <= issued + 16'h1; + if (_dut_io_complete_valid_T_1) + completed <= completed + 16'h1; + sawFull <= _dut_io_full | sawFull; + sawStall <= _dut_io_issue_valid & ~ready | sawStall; + end + if (_GEN_13 & allocationSlot == 4'h0) begin + expected_0_raw_inst <= _source_io_deq_bits_cmd_raw_inst; + expected_0_pc <= _source_io_deq_bits_cmd_pc; + expected_0_funct <= _source_io_deq_bits_cmd_funct; + expected_0_funct3 <= _source_io_deq_bits_cmd_funct3; + expected_0_rs2 <= _source_io_deq_bits_cmd_rs2; + expected_0_rs1 <= _source_io_deq_bits_cmd_rs1; + expected_0_xd <= _source_io_deq_bits_cmd_xd; + expected_0_xs1 <= _source_io_deq_bits_cmd_xs1; + expected_0_xs2 <= _source_io_deq_bits_cmd_xs2; + expected_0_rd <= _source_io_deq_bits_cmd_rd; + expected_0_opcode <= _source_io_deq_bits_cmd_opcode; + expected_0_rs1Data <= _source_io_deq_bits_cmd_rs1Data; + expected_0_rs2Data <= _source_io_deq_bits_cmd_rs2Data; + end + if (_GEN_13 & allocationSlot == 4'h1) begin + expected_1_raw_inst <= _source_io_deq_bits_cmd_raw_inst; + expected_1_pc <= _source_io_deq_bits_cmd_pc; + expected_1_funct <= _source_io_deq_bits_cmd_funct; + expected_1_funct3 <= _source_io_deq_bits_cmd_funct3; + expected_1_rs2 <= _source_io_deq_bits_cmd_rs2; + expected_1_rs1 <= _source_io_deq_bits_cmd_rs1; + expected_1_xd <= _source_io_deq_bits_cmd_xd; + expected_1_xs1 <= _source_io_deq_bits_cmd_xs1; + expected_1_xs2 <= _source_io_deq_bits_cmd_xs2; + expected_1_rd <= _source_io_deq_bits_cmd_rd; + expected_1_opcode <= _source_io_deq_bits_cmd_opcode; + expected_1_rs1Data <= _source_io_deq_bits_cmd_rs1Data; + expected_1_rs2Data <= _source_io_deq_bits_cmd_rs2Data; + end + if (_GEN_13 & allocationSlot == 4'h2) begin + expected_2_raw_inst <= _source_io_deq_bits_cmd_raw_inst; + expected_2_pc <= _source_io_deq_bits_cmd_pc; + expected_2_funct <= _source_io_deq_bits_cmd_funct; + expected_2_funct3 <= _source_io_deq_bits_cmd_funct3; + expected_2_rs2 <= _source_io_deq_bits_cmd_rs2; + expected_2_rs1 <= _source_io_deq_bits_cmd_rs1; + expected_2_xd <= _source_io_deq_bits_cmd_xd; + expected_2_xs1 <= _source_io_deq_bits_cmd_xs1; + expected_2_xs2 <= _source_io_deq_bits_cmd_xs2; + expected_2_rd <= _source_io_deq_bits_cmd_rd; + expected_2_opcode <= _source_io_deq_bits_cmd_opcode; + expected_2_rs1Data <= _source_io_deq_bits_cmd_rs1Data; + expected_2_rs2Data <= _source_io_deq_bits_cmd_rs2Data; + end + if (_GEN_13 & allocationSlot == 4'h3) begin + expected_3_raw_inst <= _source_io_deq_bits_cmd_raw_inst; + expected_3_pc <= _source_io_deq_bits_cmd_pc; + expected_3_funct <= _source_io_deq_bits_cmd_funct; + expected_3_funct3 <= _source_io_deq_bits_cmd_funct3; + expected_3_rs2 <= _source_io_deq_bits_cmd_rs2; + expected_3_rs1 <= _source_io_deq_bits_cmd_rs1; + expected_3_xd <= _source_io_deq_bits_cmd_xd; + expected_3_xs1 <= _source_io_deq_bits_cmd_xs1; + expected_3_xs2 <= _source_io_deq_bits_cmd_xs2; + expected_3_rd <= _source_io_deq_bits_cmd_rd; + expected_3_opcode <= _source_io_deq_bits_cmd_opcode; + expected_3_rs1Data <= _source_io_deq_bits_cmd_rs1Data; + expected_3_rs2Data <= _source_io_deq_bits_cmd_rs2Data; + end + if (_GEN_13 & allocationSlot == 4'h4) begin + expected_4_raw_inst <= _source_io_deq_bits_cmd_raw_inst; + expected_4_pc <= _source_io_deq_bits_cmd_pc; + expected_4_funct <= _source_io_deq_bits_cmd_funct; + expected_4_funct3 <= _source_io_deq_bits_cmd_funct3; + expected_4_rs2 <= _source_io_deq_bits_cmd_rs2; + expected_4_rs1 <= _source_io_deq_bits_cmd_rs1; + expected_4_xd <= _source_io_deq_bits_cmd_xd; + expected_4_xs1 <= _source_io_deq_bits_cmd_xs1; + expected_4_xs2 <= _source_io_deq_bits_cmd_xs2; + expected_4_rd <= _source_io_deq_bits_cmd_rd; + expected_4_opcode <= _source_io_deq_bits_cmd_opcode; + expected_4_rs1Data <= _source_io_deq_bits_cmd_rs1Data; + expected_4_rs2Data <= _source_io_deq_bits_cmd_rs2Data; + end + if (_GEN_13 & allocationSlot == 4'h5) begin + expected_5_raw_inst <= _source_io_deq_bits_cmd_raw_inst; + expected_5_pc <= _source_io_deq_bits_cmd_pc; + expected_5_funct <= _source_io_deq_bits_cmd_funct; + expected_5_funct3 <= _source_io_deq_bits_cmd_funct3; + expected_5_rs2 <= _source_io_deq_bits_cmd_rs2; + expected_5_rs1 <= _source_io_deq_bits_cmd_rs1; + expected_5_xd <= _source_io_deq_bits_cmd_xd; + expected_5_xs1 <= _source_io_deq_bits_cmd_xs1; + expected_5_xs2 <= _source_io_deq_bits_cmd_xs2; + expected_5_rd <= _source_io_deq_bits_cmd_rd; + expected_5_opcode <= _source_io_deq_bits_cmd_opcode; + expected_5_rs1Data <= _source_io_deq_bits_cmd_rs1Data; + expected_5_rs2Data <= _source_io_deq_bits_cmd_rs2Data; + end + if (_GEN_13 & allocationSlot == 4'h6) begin + expected_6_raw_inst <= _source_io_deq_bits_cmd_raw_inst; + expected_6_pc <= _source_io_deq_bits_cmd_pc; + expected_6_funct <= _source_io_deq_bits_cmd_funct; + expected_6_funct3 <= _source_io_deq_bits_cmd_funct3; + expected_6_rs2 <= _source_io_deq_bits_cmd_rs2; + expected_6_rs1 <= _source_io_deq_bits_cmd_rs1; + expected_6_xd <= _source_io_deq_bits_cmd_xd; + expected_6_xs1 <= _source_io_deq_bits_cmd_xs1; + expected_6_xs2 <= _source_io_deq_bits_cmd_xs2; + expected_6_rd <= _source_io_deq_bits_cmd_rd; + expected_6_opcode <= _source_io_deq_bits_cmd_opcode; + expected_6_rs1Data <= _source_io_deq_bits_cmd_rs1Data; + expected_6_rs2Data <= _source_io_deq_bits_cmd_rs2Data; + end + if (_GEN_13 & allocationSlot == 4'h7) begin + expected_7_raw_inst <= _source_io_deq_bits_cmd_raw_inst; + expected_7_pc <= _source_io_deq_bits_cmd_pc; + expected_7_funct <= _source_io_deq_bits_cmd_funct; + expected_7_funct3 <= _source_io_deq_bits_cmd_funct3; + expected_7_rs2 <= _source_io_deq_bits_cmd_rs2; + expected_7_rs1 <= _source_io_deq_bits_cmd_rs1; + expected_7_xd <= _source_io_deq_bits_cmd_xd; + expected_7_xs1 <= _source_io_deq_bits_cmd_xs1; + expected_7_xs2 <= _source_io_deq_bits_cmd_xs2; + expected_7_rd <= _source_io_deq_bits_cmd_rd; + expected_7_opcode <= _source_io_deq_bits_cmd_opcode; + expected_7_rs1Data <= _source_io_deq_bits_cmd_rs1Data; + expected_7_rs2Data <= _source_io_deq_bits_cmd_rs2Data; + end + if (_GEN_13 & allocationSlot == 4'h8) begin + expected_8_raw_inst <= _source_io_deq_bits_cmd_raw_inst; + expected_8_pc <= _source_io_deq_bits_cmd_pc; + expected_8_funct <= _source_io_deq_bits_cmd_funct; + expected_8_funct3 <= _source_io_deq_bits_cmd_funct3; + expected_8_rs2 <= _source_io_deq_bits_cmd_rs2; + expected_8_rs1 <= _source_io_deq_bits_cmd_rs1; + expected_8_xd <= _source_io_deq_bits_cmd_xd; + expected_8_xs1 <= _source_io_deq_bits_cmd_xs1; + expected_8_xs2 <= _source_io_deq_bits_cmd_xs2; + expected_8_rd <= _source_io_deq_bits_cmd_rd; + expected_8_opcode <= _source_io_deq_bits_cmd_opcode; + expected_8_rs1Data <= _source_io_deq_bits_cmd_rs1Data; + expected_8_rs2Data <= _source_io_deq_bits_cmd_rs2Data; + end + if (_GEN_13 & allocationSlot == 4'h9) begin + expected_9_raw_inst <= _source_io_deq_bits_cmd_raw_inst; + expected_9_pc <= _source_io_deq_bits_cmd_pc; + expected_9_funct <= _source_io_deq_bits_cmd_funct; + expected_9_funct3 <= _source_io_deq_bits_cmd_funct3; + expected_9_rs2 <= _source_io_deq_bits_cmd_rs2; + expected_9_rs1 <= _source_io_deq_bits_cmd_rs1; + expected_9_xd <= _source_io_deq_bits_cmd_xd; + expected_9_xs1 <= _source_io_deq_bits_cmd_xs1; + expected_9_xs2 <= _source_io_deq_bits_cmd_xs2; + expected_9_rd <= _source_io_deq_bits_cmd_rd; + expected_9_opcode <= _source_io_deq_bits_cmd_opcode; + expected_9_rs1Data <= _source_io_deq_bits_cmd_rs1Data; + expected_9_rs2Data <= _source_io_deq_bits_cmd_rs2Data; + end + if (_GEN_13 & allocationSlot == 4'hA) begin + expected_10_raw_inst <= _source_io_deq_bits_cmd_raw_inst; + expected_10_pc <= _source_io_deq_bits_cmd_pc; + expected_10_funct <= _source_io_deq_bits_cmd_funct; + expected_10_funct3 <= _source_io_deq_bits_cmd_funct3; + expected_10_rs2 <= _source_io_deq_bits_cmd_rs2; + expected_10_rs1 <= _source_io_deq_bits_cmd_rs1; + expected_10_xd <= _source_io_deq_bits_cmd_xd; + expected_10_xs1 <= _source_io_deq_bits_cmd_xs1; + expected_10_xs2 <= _source_io_deq_bits_cmd_xs2; + expected_10_rd <= _source_io_deq_bits_cmd_rd; + expected_10_opcode <= _source_io_deq_bits_cmd_opcode; + expected_10_rs1Data <= _source_io_deq_bits_cmd_rs1Data; + expected_10_rs2Data <= _source_io_deq_bits_cmd_rs2Data; + end + if (_GEN_13 & allocationSlot == 4'hB) begin + expected_11_raw_inst <= _source_io_deq_bits_cmd_raw_inst; + expected_11_pc <= _source_io_deq_bits_cmd_pc; + expected_11_funct <= _source_io_deq_bits_cmd_funct; + expected_11_funct3 <= _source_io_deq_bits_cmd_funct3; + expected_11_rs2 <= _source_io_deq_bits_cmd_rs2; + expected_11_rs1 <= _source_io_deq_bits_cmd_rs1; + expected_11_xd <= _source_io_deq_bits_cmd_xd; + expected_11_xs1 <= _source_io_deq_bits_cmd_xs1; + expected_11_xs2 <= _source_io_deq_bits_cmd_xs2; + expected_11_rd <= _source_io_deq_bits_cmd_rd; + expected_11_opcode <= _source_io_deq_bits_cmd_opcode; + expected_11_rs1Data <= _source_io_deq_bits_cmd_rs1Data; + expected_11_rs2Data <= _source_io_deq_bits_cmd_rs2Data; + end + if (_GEN_13 & allocationSlot == 4'hC) begin + expected_12_raw_inst <= _source_io_deq_bits_cmd_raw_inst; + expected_12_pc <= _source_io_deq_bits_cmd_pc; + expected_12_funct <= _source_io_deq_bits_cmd_funct; + expected_12_funct3 <= _source_io_deq_bits_cmd_funct3; + expected_12_rs2 <= _source_io_deq_bits_cmd_rs2; + expected_12_rs1 <= _source_io_deq_bits_cmd_rs1; + expected_12_xd <= _source_io_deq_bits_cmd_xd; + expected_12_xs1 <= _source_io_deq_bits_cmd_xs1; + expected_12_xs2 <= _source_io_deq_bits_cmd_xs2; + expected_12_rd <= _source_io_deq_bits_cmd_rd; + expected_12_opcode <= _source_io_deq_bits_cmd_opcode; + expected_12_rs1Data <= _source_io_deq_bits_cmd_rs1Data; + expected_12_rs2Data <= _source_io_deq_bits_cmd_rs2Data; + end + if (_GEN_13 & allocationSlot == 4'hD) begin + expected_13_raw_inst <= _source_io_deq_bits_cmd_raw_inst; + expected_13_pc <= _source_io_deq_bits_cmd_pc; + expected_13_funct <= _source_io_deq_bits_cmd_funct; + expected_13_funct3 <= _source_io_deq_bits_cmd_funct3; + expected_13_rs2 <= _source_io_deq_bits_cmd_rs2; + expected_13_rs1 <= _source_io_deq_bits_cmd_rs1; + expected_13_xd <= _source_io_deq_bits_cmd_xd; + expected_13_xs1 <= _source_io_deq_bits_cmd_xs1; + expected_13_xs2 <= _source_io_deq_bits_cmd_xs2; + expected_13_rd <= _source_io_deq_bits_cmd_rd; + expected_13_opcode <= _source_io_deq_bits_cmd_opcode; + expected_13_rs1Data <= _source_io_deq_bits_cmd_rs1Data; + expected_13_rs2Data <= _source_io_deq_bits_cmd_rs2Data; + end + if (_GEN_13 & allocationSlot == 4'hE) begin + expected_14_raw_inst <= _source_io_deq_bits_cmd_raw_inst; + expected_14_pc <= _source_io_deq_bits_cmd_pc; + expected_14_funct <= _source_io_deq_bits_cmd_funct; + expected_14_funct3 <= _source_io_deq_bits_cmd_funct3; + expected_14_rs2 <= _source_io_deq_bits_cmd_rs2; + expected_14_rs1 <= _source_io_deq_bits_cmd_rs1; + expected_14_xd <= _source_io_deq_bits_cmd_xd; + expected_14_xs1 <= _source_io_deq_bits_cmd_xs1; + expected_14_xs2 <= _source_io_deq_bits_cmd_xs2; + expected_14_rd <= _source_io_deq_bits_cmd_rd; + expected_14_opcode <= _source_io_deq_bits_cmd_opcode; + expected_14_rs1Data <= _source_io_deq_bits_cmd_rs1Data; + expected_14_rs2Data <= _source_io_deq_bits_cmd_rs2Data; + end + if (_GEN_13 & (&allocationSlot)) begin + expected_15_raw_inst <= _source_io_deq_bits_cmd_raw_inst; + expected_15_pc <= _source_io_deq_bits_cmd_pc; + expected_15_funct <= _source_io_deq_bits_cmd_funct; + expected_15_funct3 <= _source_io_deq_bits_cmd_funct3; + expected_15_rs2 <= _source_io_deq_bits_cmd_rs2; + expected_15_rs1 <= _source_io_deq_bits_cmd_rs1; + expected_15_xd <= _source_io_deq_bits_cmd_xd; + expected_15_xs1 <= _source_io_deq_bits_cmd_xs1; + expected_15_xs2 <= _source_io_deq_bits_cmd_xs2; + expected_15_rd <= _source_io_deq_bits_cmd_rd; + expected_15_opcode <= _source_io_deq_bits_cmd_opcode; + expected_15_rs1Data <= _source_io_deq_bits_cmd_rs1Data; + expected_15_rs2Data <= _source_io_deq_bits_cmd_rs2Data; + end + end // always @(posedge) + GlobalROB dut ( + .clock (clock), + .reset (reset), + .io_alloc_ready (_dut_io_alloc_ready), + .io_alloc_valid (_source_io_deq_valid), + .io_alloc_bits_domain_id (_source_io_deq_bits_domain_id), + .io_alloc_bits_ball_bid (_source_io_deq_bits_ball_bid), + .io_alloc_bits_cmd_raw_inst (_source_io_deq_bits_cmd_raw_inst), + .io_alloc_bits_cmd_pc (_source_io_deq_bits_cmd_pc), + .io_alloc_bits_cmd_funct (_source_io_deq_bits_cmd_funct), + .io_alloc_bits_cmd_funct3 (_source_io_deq_bits_cmd_funct3), + .io_alloc_bits_cmd_rs2 (_source_io_deq_bits_cmd_rs2), + .io_alloc_bits_cmd_rs1 (_source_io_deq_bits_cmd_rs1), + .io_alloc_bits_cmd_xd (_source_io_deq_bits_cmd_xd), + .io_alloc_bits_cmd_xs1 (_source_io_deq_bits_cmd_xs1), + .io_alloc_bits_cmd_xs2 (_source_io_deq_bits_cmd_xs2), + .io_alloc_bits_cmd_rd (_source_io_deq_bits_cmd_rd), + .io_alloc_bits_cmd_opcode (_source_io_deq_bits_cmd_opcode), + .io_alloc_bits_cmd_rs1Data (_source_io_deq_bits_cmd_rs1Data), + .io_alloc_bits_cmd_rs2Data (_source_io_deq_bits_cmd_rs2Data), + .io_alloc_bits_bankAccess_rd_bank_0_valid + (_source_io_deq_bits_bankAccess_rd_bank_0_valid), + .io_alloc_bits_bankAccess_rd_bank_0_id + (_source_io_deq_bits_bankAccess_rd_bank_0_id), + .io_alloc_bits_bankAccess_rd_bank_1_valid + (_source_io_deq_bits_bankAccess_rd_bank_1_valid), + .io_alloc_bits_bankAccess_rd_bank_1_id + (_source_io_deq_bits_bankAccess_rd_bank_1_id), + .io_alloc_bits_bankAccess_wr_bank_valid + (_source_io_deq_bits_bankAccess_wr_bank_valid), + .io_alloc_bits_bankAccess_wr_bank_id + (_source_io_deq_bits_bankAccess_wr_bank_id), + .io_alloc_bits_isFence (_source_io_deq_bits_isFence), + .io_alloc_bits_isBarrier (_source_io_deq_bits_isBarrier), + .io_issue_ready (ready), + .io_issue_valid (_dut_io_issue_valid), + .io_issue_bits_cmd_domain_id (_dut_io_issue_bits_cmd_domain_id), + .io_issue_bits_cmd_ball_bid (_dut_io_issue_bits_cmd_ball_bid), + .io_issue_bits_cmd_cmd_raw_inst + (_dut_io_issue_bits_cmd_cmd_raw_inst), + .io_issue_bits_cmd_cmd_pc (_dut_io_issue_bits_cmd_cmd_pc), + .io_issue_bits_cmd_cmd_funct (_dut_io_issue_bits_cmd_cmd_funct), + .io_issue_bits_cmd_cmd_funct3 (_dut_io_issue_bits_cmd_cmd_funct3), + .io_issue_bits_cmd_cmd_rs2 (_dut_io_issue_bits_cmd_cmd_rs2), + .io_issue_bits_cmd_cmd_rs1 (_dut_io_issue_bits_cmd_cmd_rs1), + .io_issue_bits_cmd_cmd_xd (_dut_io_issue_bits_cmd_cmd_xd), + .io_issue_bits_cmd_cmd_xs1 (_dut_io_issue_bits_cmd_cmd_xs1), + .io_issue_bits_cmd_cmd_xs2 (_dut_io_issue_bits_cmd_cmd_xs2), + .io_issue_bits_cmd_cmd_rd (_dut_io_issue_bits_cmd_cmd_rd), + .io_issue_bits_cmd_cmd_opcode (_dut_io_issue_bits_cmd_cmd_opcode), + .io_issue_bits_cmd_cmd_rs1Data (_dut_io_issue_bits_cmd_cmd_rs1Data), + .io_issue_bits_cmd_cmd_rs2Data (_dut_io_issue_bits_cmd_cmd_rs2Data), + .io_issue_bits_cmd_bankAccess_rd_bank_0_valid + (_dut_io_issue_bits_cmd_bankAccess_rd_bank_0_valid), + .io_issue_bits_cmd_bankAccess_rd_bank_0_id + (_dut_io_issue_bits_cmd_bankAccess_rd_bank_0_id), + .io_issue_bits_cmd_bankAccess_rd_bank_1_valid + (_dut_io_issue_bits_cmd_bankAccess_rd_bank_1_valid), + .io_issue_bits_cmd_bankAccess_rd_bank_1_id + (_dut_io_issue_bits_cmd_bankAccess_rd_bank_1_id), + .io_issue_bits_cmd_bankAccess_wr_bank_valid + (_dut_io_issue_bits_cmd_bankAccess_wr_bank_valid), + .io_issue_bits_cmd_bankAccess_wr_bank_id + (_dut_io_issue_bits_cmd_bankAccess_wr_bank_id), + .io_issue_bits_cmd_op1_col (_dut_io_issue_bits_cmd_op1_col), + .io_issue_bits_cmd_op2_col (_dut_io_issue_bits_cmd_op2_col), + .io_issue_bits_cmd_wr_col (_dut_io_issue_bits_cmd_wr_col), + .io_issue_bits_cmd_isFence (_dut_io_issue_bits_cmd_isFence), + .io_issue_bits_cmd_isBarrier (_dut_io_issue_bits_cmd_isBarrier), + .io_issue_bits_renamedBankAccess_rd_bank_0_valid + (_dut_io_issue_bits_renamedBankAccess_rd_bank_0_valid), + .io_issue_bits_renamedBankAccess_rd_bank_0_id + (_dut_io_issue_bits_renamedBankAccess_rd_bank_0_id), + .io_issue_bits_renamedBankAccess_rd_bank_1_valid + (_dut_io_issue_bits_renamedBankAccess_rd_bank_1_valid), + .io_issue_bits_renamedBankAccess_rd_bank_1_id + (_dut_io_issue_bits_renamedBankAccess_rd_bank_1_id), + .io_issue_bits_renamedBankAccess_wr_bank_valid + (_dut_io_issue_bits_renamedBankAccess_wr_bank_valid), + .io_issue_bits_renamedBankAccess_wr_bank_id + (_dut_io_issue_bits_renamedBankAccess_wr_bank_id), + .io_issue_bits_rob_id (_dut_io_issue_bits_rob_id), + .io_complete_valid (_dut_io_complete_valid_T_1), + .io_complete_bits (_completions_io_deq_bits), + .io_empty (_dut_io_empty), + .io_full (_dut_io_full), + .io_head_ptr (_dut_io_head_ptr), + .io_issued_count (_dut_io_issued_count), + .io_entry_valid_0 (_dut_io_entry_valid_0), + .io_entry_valid_1 (_dut_io_entry_valid_1), + .io_entry_valid_2 (_dut_io_entry_valid_2), + .io_entry_valid_3 (_dut_io_entry_valid_3), + .io_entry_valid_4 (_dut_io_entry_valid_4), + .io_entry_valid_5 (_dut_io_entry_valid_5), + .io_entry_valid_6 (_dut_io_entry_valid_6), + .io_entry_valid_7 (_dut_io_entry_valid_7), + .io_entry_valid_8 (_dut_io_entry_valid_8), + .io_entry_valid_9 (_dut_io_entry_valid_9), + .io_entry_valid_10 (_dut_io_entry_valid_10), + .io_entry_valid_11 (_dut_io_entry_valid_11), + .io_entry_valid_12 (_dut_io_entry_valid_12), + .io_entry_valid_13 (_dut_io_entry_valid_13), + .io_entry_valid_14 (_dut_io_entry_valid_14), + .io_entry_valid_15 (_dut_io_entry_valid_15), + .io_entry_complete_0 (_dut_io_entry_complete_0), + .io_entry_complete_1 (_dut_io_entry_complete_1), + .io_entry_complete_2 (_dut_io_entry_complete_2), + .io_entry_complete_3 (_dut_io_entry_complete_3), + .io_entry_complete_4 (_dut_io_entry_complete_4), + .io_entry_complete_5 (_dut_io_entry_complete_5), + .io_entry_complete_6 (_dut_io_entry_complete_6), + .io_entry_complete_7 (_dut_io_entry_complete_7), + .io_entry_complete_8 (_dut_io_entry_complete_8), + .io_entry_complete_9 (_dut_io_entry_complete_9), + .io_entry_complete_10 (_dut_io_entry_complete_10), + .io_entry_complete_11 (_dut_io_entry_complete_11), + .io_entry_complete_12 (_dut_io_entry_complete_12), + .io_entry_complete_13 (_dut_io_entry_complete_13), + .io_entry_complete_14 (_dut_io_entry_complete_14), + .io_entry_complete_15 (_dut_io_entry_complete_15), + .io_subRobActive (active), + .io_inst_ids_0 (_dut_io_inst_ids_0), + .io_inst_ids_1 (_dut_io_inst_ids_1), + .io_inst_ids_2 (_dut_io_inst_ids_2), + .io_inst_ids_3 (_dut_io_inst_ids_3), + .io_inst_ids_4 (_dut_io_inst_ids_4), + .io_inst_ids_5 (_dut_io_inst_ids_5), + .io_inst_ids_6 (_dut_io_inst_ids_6), + .io_inst_ids_7 (_dut_io_inst_ids_7), + .io_inst_ids_8 (_dut_io_inst_ids_8), + .io_inst_ids_9 (_dut_io_inst_ids_9), + .io_inst_ids_10 (_dut_io_inst_ids_10), + .io_inst_ids_11 (_dut_io_inst_ids_11), + .io_inst_ids_12 (_dut_io_inst_ids_12), + .io_inst_ids_13 (_dut_io_inst_ids_13), + .io_inst_ids_14 (_dut_io_inst_ids_14), + .io_inst_ids_15 (_dut_io_inst_ids_15) + ); + GlobalROB_1 reference ( + .clock (clock), + .reset (reset), + .io_alloc_ready (_reference_io_alloc_ready), + .io_alloc_valid (_source_io_deq_valid), + .io_alloc_bits_domain_id (_source_io_deq_bits_domain_id), + .io_alloc_bits_ball_bid (_source_io_deq_bits_ball_bid), + .io_alloc_bits_cmd_raw_inst (_source_io_deq_bits_cmd_raw_inst), + .io_alloc_bits_cmd_pc (_source_io_deq_bits_cmd_pc), + .io_alloc_bits_cmd_funct (_source_io_deq_bits_cmd_funct), + .io_alloc_bits_cmd_funct3 (_source_io_deq_bits_cmd_funct3), + .io_alloc_bits_cmd_rs2 (_source_io_deq_bits_cmd_rs2), + .io_alloc_bits_cmd_rs1 (_source_io_deq_bits_cmd_rs1), + .io_alloc_bits_cmd_xd (_source_io_deq_bits_cmd_xd), + .io_alloc_bits_cmd_xs1 (_source_io_deq_bits_cmd_xs1), + .io_alloc_bits_cmd_xs2 (_source_io_deq_bits_cmd_xs2), + .io_alloc_bits_cmd_rd (_source_io_deq_bits_cmd_rd), + .io_alloc_bits_cmd_opcode (_source_io_deq_bits_cmd_opcode), + .io_alloc_bits_cmd_rs1Data (_source_io_deq_bits_cmd_rs1Data), + .io_alloc_bits_cmd_rs2Data (_source_io_deq_bits_cmd_rs2Data), + .io_alloc_bits_bankAccess_rd_bank_0_valid + (_source_io_deq_bits_bankAccess_rd_bank_0_valid), + .io_alloc_bits_bankAccess_rd_bank_0_id + (_source_io_deq_bits_bankAccess_rd_bank_0_id), + .io_alloc_bits_bankAccess_rd_bank_1_valid + (_source_io_deq_bits_bankAccess_rd_bank_1_valid), + .io_alloc_bits_bankAccess_rd_bank_1_id + (_source_io_deq_bits_bankAccess_rd_bank_1_id), + .io_alloc_bits_bankAccess_wr_bank_valid + (_source_io_deq_bits_bankAccess_wr_bank_valid), + .io_alloc_bits_bankAccess_wr_bank_id + (_source_io_deq_bits_bankAccess_wr_bank_id), + .io_alloc_bits_isFence (_source_io_deq_bits_isFence), + .io_alloc_bits_isBarrier (_source_io_deq_bits_isBarrier), + .io_issue_ready (ready), + .io_issue_valid (_reference_io_issue_valid), + .io_issue_bits_cmd_domain_id + (_reference_io_issue_bits_cmd_domain_id), + .io_issue_bits_cmd_ball_bid + (_reference_io_issue_bits_cmd_ball_bid), + .io_issue_bits_cmd_cmd_raw_inst + (_reference_io_issue_bits_cmd_cmd_raw_inst), + .io_issue_bits_cmd_cmd_pc + (_reference_io_issue_bits_cmd_cmd_pc), + .io_issue_bits_cmd_cmd_funct + (_reference_io_issue_bits_cmd_cmd_funct), + .io_issue_bits_cmd_cmd_funct3 + (_reference_io_issue_bits_cmd_cmd_funct3), + .io_issue_bits_cmd_cmd_rs2 + (_reference_io_issue_bits_cmd_cmd_rs2), + .io_issue_bits_cmd_cmd_rs1 + (_reference_io_issue_bits_cmd_cmd_rs1), + .io_issue_bits_cmd_cmd_xd + (_reference_io_issue_bits_cmd_cmd_xd), + .io_issue_bits_cmd_cmd_xs1 + (_reference_io_issue_bits_cmd_cmd_xs1), + .io_issue_bits_cmd_cmd_xs2 + (_reference_io_issue_bits_cmd_cmd_xs2), + .io_issue_bits_cmd_cmd_rd + (_reference_io_issue_bits_cmd_cmd_rd), + .io_issue_bits_cmd_cmd_opcode + (_reference_io_issue_bits_cmd_cmd_opcode), + .io_issue_bits_cmd_cmd_rs1Data + (_reference_io_issue_bits_cmd_cmd_rs1Data), + .io_issue_bits_cmd_cmd_rs2Data + (_reference_io_issue_bits_cmd_cmd_rs2Data), + .io_issue_bits_cmd_bankAccess_rd_bank_0_valid + (_reference_io_issue_bits_cmd_bankAccess_rd_bank_0_valid), + .io_issue_bits_cmd_bankAccess_rd_bank_0_id + (_reference_io_issue_bits_cmd_bankAccess_rd_bank_0_id), + .io_issue_bits_cmd_bankAccess_rd_bank_1_valid + (_reference_io_issue_bits_cmd_bankAccess_rd_bank_1_valid), + .io_issue_bits_cmd_bankAccess_rd_bank_1_id + (_reference_io_issue_bits_cmd_bankAccess_rd_bank_1_id), + .io_issue_bits_cmd_bankAccess_wr_bank_valid + (_reference_io_issue_bits_cmd_bankAccess_wr_bank_valid), + .io_issue_bits_cmd_bankAccess_wr_bank_id + (_reference_io_issue_bits_cmd_bankAccess_wr_bank_id), + .io_issue_bits_cmd_op1_col + (_reference_io_issue_bits_cmd_op1_col), + .io_issue_bits_cmd_op2_col + (_reference_io_issue_bits_cmd_op2_col), + .io_issue_bits_cmd_wr_col + (_reference_io_issue_bits_cmd_wr_col), + .io_issue_bits_cmd_isFence + (_reference_io_issue_bits_cmd_isFence), + .io_issue_bits_cmd_isBarrier + (_reference_io_issue_bits_cmd_isBarrier), + .io_issue_bits_renamedBankAccess_rd_bank_0_valid + (_reference_io_issue_bits_renamedBankAccess_rd_bank_0_valid), + .io_issue_bits_renamedBankAccess_rd_bank_0_id + (_reference_io_issue_bits_renamedBankAccess_rd_bank_0_id), + .io_issue_bits_renamedBankAccess_rd_bank_1_valid + (_reference_io_issue_bits_renamedBankAccess_rd_bank_1_valid), + .io_issue_bits_renamedBankAccess_rd_bank_1_id + (_reference_io_issue_bits_renamedBankAccess_rd_bank_1_id), + .io_issue_bits_renamedBankAccess_wr_bank_valid + (_reference_io_issue_bits_renamedBankAccess_wr_bank_valid), + .io_issue_bits_renamedBankAccess_wr_bank_id + (_reference_io_issue_bits_renamedBankAccess_wr_bank_id), + .io_issue_bits_rob_id (_reference_io_issue_bits_rob_id), + .io_complete_valid (_dut_io_complete_valid_T_1), + .io_complete_bits (_completions_io_deq_bits), + .io_empty (_reference_io_empty), + .io_full (_reference_io_full), + .io_head_ptr (_reference_io_head_ptr), + .io_issued_count (_reference_io_issued_count), + .io_entry_valid_0 (_reference_io_entry_valid_0), + .io_entry_valid_1 (_reference_io_entry_valid_1), + .io_entry_valid_2 (_reference_io_entry_valid_2), + .io_entry_valid_3 (_reference_io_entry_valid_3), + .io_entry_valid_4 (_reference_io_entry_valid_4), + .io_entry_valid_5 (_reference_io_entry_valid_5), + .io_entry_valid_6 (_reference_io_entry_valid_6), + .io_entry_valid_7 (_reference_io_entry_valid_7), + .io_entry_valid_8 (_reference_io_entry_valid_8), + .io_entry_valid_9 (_reference_io_entry_valid_9), + .io_entry_valid_10 (_reference_io_entry_valid_10), + .io_entry_valid_11 (_reference_io_entry_valid_11), + .io_entry_valid_12 (_reference_io_entry_valid_12), + .io_entry_valid_13 (_reference_io_entry_valid_13), + .io_entry_valid_14 (_reference_io_entry_valid_14), + .io_entry_valid_15 (_reference_io_entry_valid_15), + .io_entry_complete_0 (_reference_io_entry_complete_0), + .io_entry_complete_1 (_reference_io_entry_complete_1), + .io_entry_complete_2 (_reference_io_entry_complete_2), + .io_entry_complete_3 (_reference_io_entry_complete_3), + .io_entry_complete_4 (_reference_io_entry_complete_4), + .io_entry_complete_5 (_reference_io_entry_complete_5), + .io_entry_complete_6 (_reference_io_entry_complete_6), + .io_entry_complete_7 (_reference_io_entry_complete_7), + .io_entry_complete_8 (_reference_io_entry_complete_8), + .io_entry_complete_9 (_reference_io_entry_complete_9), + .io_entry_complete_10 (_reference_io_entry_complete_10), + .io_entry_complete_11 (_reference_io_entry_complete_11), + .io_entry_complete_12 (_reference_io_entry_complete_12), + .io_entry_complete_13 (_reference_io_entry_complete_13), + .io_entry_complete_14 (_reference_io_entry_complete_14), + .io_entry_complete_15 (_reference_io_entry_complete_15), + .io_subRobActive (active), + .io_inst_ids_0 (_reference_io_inst_ids_0), + .io_inst_ids_1 (_reference_io_inst_ids_1), + .io_inst_ids_2 (_reference_io_inst_ids_2), + .io_inst_ids_3 (_reference_io_inst_ids_3), + .io_inst_ids_4 (_reference_io_inst_ids_4), + .io_inst_ids_5 (_reference_io_inst_ids_5), + .io_inst_ids_6 (_reference_io_inst_ids_6), + .io_inst_ids_7 (_reference_io_inst_ids_7), + .io_inst_ids_8 (_reference_io_inst_ids_8), + .io_inst_ids_9 (_reference_io_inst_ids_9), + .io_inst_ids_10 (_reference_io_inst_ids_10), + .io_inst_ids_11 (_reference_io_inst_ids_11), + .io_inst_ids_12 (_reference_io_inst_ids_12), + .io_inst_ids_13 (_reference_io_inst_ids_13), + .io_inst_ids_14 (_reference_io_inst_ids_14), + .io_inst_ids_15 (_reference_io_inst_ids_15) + ); + Queue2_PostGDCmd source ( + .clock (clock), + .reset (reset), + .io_enq_valid (cycle < 16'h1388 & random[0]), + .io_enq_bits_domain_id + ({2'h0, ~(~(|(random[5:2])) | random[2]), 1'h1}), + .io_enq_bits_cmd_raw_inst (random), + .io_enq_bits_cmd_pc ({random, ~random}), + .io_enq_bits_cmd_funct + ((|(random[5:2])) ? (random[3] ? 7'h35 : 7'h42) : 7'h20), + .io_enq_bits_cmd_rs1Data + ({random, random[31], random[30:0] ^ 31'h597BDF03}), + .io_enq_bits_cmd_rs2Data + ((|(random[5:2])) + ? {~random, random[31:30], random[29:0] ^ 30'h26AC048E} + : {random, 25'h8, random[1:0], 5'h0}), + .io_enq_bits_bankAccess_rd_bank_0_valid ((|(random[5:2])) & random[8]), + .io_enq_bits_bankAccess_rd_bank_0_id ({6'h0, random[14:11]}), + .io_enq_bits_bankAccess_rd_bank_1_valid ((|(random[5:2])) & random[9]), + .io_enq_bits_bankAccess_rd_bank_1_id ({6'h0, random[18:15]}), + .io_enq_bits_bankAccess_wr_bank_valid (~(|(random[5:2])) | random[10]), + .io_enq_bits_bankAccess_wr_bank_id ({6'h0, random[22:19]}), + .io_deq_ready (_dut_io_alloc_ready), + .io_deq_valid (_source_io_deq_valid), + .io_deq_bits_domain_id (_source_io_deq_bits_domain_id), + .io_deq_bits_ball_bid (_source_io_deq_bits_ball_bid), + .io_deq_bits_cmd_raw_inst (_source_io_deq_bits_cmd_raw_inst), + .io_deq_bits_cmd_pc (_source_io_deq_bits_cmd_pc), + .io_deq_bits_cmd_funct (_source_io_deq_bits_cmd_funct), + .io_deq_bits_cmd_funct3 (_source_io_deq_bits_cmd_funct3), + .io_deq_bits_cmd_rs2 (_source_io_deq_bits_cmd_rs2), + .io_deq_bits_cmd_rs1 (_source_io_deq_bits_cmd_rs1), + .io_deq_bits_cmd_xd (_source_io_deq_bits_cmd_xd), + .io_deq_bits_cmd_xs1 (_source_io_deq_bits_cmd_xs1), + .io_deq_bits_cmd_xs2 (_source_io_deq_bits_cmd_xs2), + .io_deq_bits_cmd_rd (_source_io_deq_bits_cmd_rd), + .io_deq_bits_cmd_opcode (_source_io_deq_bits_cmd_opcode), + .io_deq_bits_cmd_rs1Data (_source_io_deq_bits_cmd_rs1Data), + .io_deq_bits_cmd_rs2Data (_source_io_deq_bits_cmd_rs2Data), + .io_deq_bits_bankAccess_rd_bank_0_valid + (_source_io_deq_bits_bankAccess_rd_bank_0_valid), + .io_deq_bits_bankAccess_rd_bank_0_id (_source_io_deq_bits_bankAccess_rd_bank_0_id), + .io_deq_bits_bankAccess_rd_bank_1_valid + (_source_io_deq_bits_bankAccess_rd_bank_1_valid), + .io_deq_bits_bankAccess_rd_bank_1_id (_source_io_deq_bits_bankAccess_rd_bank_1_id), + .io_deq_bits_bankAccess_wr_bank_valid + (_source_io_deq_bits_bankAccess_wr_bank_valid), + .io_deq_bits_bankAccess_wr_bank_id (_source_io_deq_bits_bankAccess_wr_bank_id), + .io_deq_bits_isFence (_source_io_deq_bits_isFence), + .io_deq_bits_isBarrier (_source_io_deq_bits_isBarrier) + ); + Queue16_UInt4 completions ( + .clock (clock), + .reset (reset), + .io_enq_ready (_completions_io_enq_ready), + .io_enq_valid (_completions_io_enq_valid_T), + .io_enq_bits (_dut_io_issue_bits_rob_id), + .io_deq_ready (random[4]), + .io_deq_valid (_completions_io_deq_valid), + .io_deq_bits (_completions_io_deq_bits) + ); + assign passed = _passed_output; +endmodule + + + + + + +module ITraceDPI( + input clock, + input reset, + input [7:0] is_issue, + input [63:0] hart_id, + input [31:0] rob_id, + input [63:0] inst_id, + input [31:0] domain_id, + input [31:0] funct, + input [63:0] pc, + input [63:0] rs1_data, + input [63:0] rs2_data, + input enable +); +`ifndef BUCKYBALL_DISABLE_DPI +`ifndef BUCKYBALL_DISABLE_TRACE_DPI +`ifndef BUCKYBALL_DISABLE_ITRACE_DPI + + import "DPI-C" context function void dpi_itrace( + input int unsigned is_issue, + input int unsigned hart_id_lo, + input int unsigned hart_id_hi, + input int unsigned rob_id, + input int unsigned inst_id_lo, + input int unsigned inst_id_hi, + input int unsigned domain_id, + input int unsigned funct, + input int unsigned pc_lo, + input int unsigned pc_hi, + input int unsigned rs1_data_lo, + input int unsigned rs1_data_hi, + input int unsigned rs2_data_lo, + input int unsigned rs2_data_hi + ); + reg [7:0] is_issue_reg; + reg [63:0] hart_id_reg; + reg [31:0] rob_id_reg; + reg [63:0] inst_id_reg; + reg [31:0] domain_id_reg; + reg [31:0] funct_reg; + reg [63:0] pc_reg; + reg [63:0] rs1_data_reg; + reg [63:0] rs2_data_reg; + reg valid_reg; + + always @(posedge clock) begin + if (reset) begin + valid_reg <= 1'b0; + end else begin + if (valid_reg) begin + dpi_itrace(is_issue_reg, hart_id_reg[31:0], hart_id_reg[63:32], rob_id_reg, inst_id_reg[31:0], inst_id_reg[63:32], domain_id_reg, funct_reg, pc_reg[31:0], pc_reg[63:32], rs1_data_reg[31:0], rs1_data_reg[63:32], rs2_data_reg[31:0], rs2_data_reg[63:32]); + end + + valid_reg <= enable; + if (enable) begin + is_issue_reg <= is_issue; + hart_id_reg <= hart_id; + rob_id_reg <= rob_id; + inst_id_reg <= inst_id; + domain_id_reg <= domain_id; + funct_reg <= funct; + pc_reg <= pc; + rs1_data_reg <= rs1_data; + rs2_data_reg <= rs2_data; + end + end + end +`endif +`endif +`endif + +endmodule + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/globalrob-check/GlobalRobCheck.sv b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/globalrob-check/GlobalRobCheck.sv new file mode 100644 index 0000000..326fb63 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/globalrob-check/GlobalRobCheck.sv @@ -0,0 +1,13684 @@ +// Generated by CIRCT firtool-1.62.1 +// Standard header to adapt well known macros for prints and assertions. + +// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. +`ifndef ASSERT_VERBOSE_COND_ + `ifdef ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) + `else // ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ 1 + `endif // ASSERT_VERBOSE_COND +`endif // not def ASSERT_VERBOSE_COND_ + +// Users can define 'STOP_COND' to add an extra gate to stop conditions. +`ifndef STOP_COND_ + `ifdef STOP_COND + `define STOP_COND_ (`STOP_COND) + `else // STOP_COND + `define STOP_COND_ 1 + `endif // STOP_COND +`endif // not def STOP_COND_ + +module BankAliasTable( + input clock, + reset, + io_alloc_valid, + input [3:0] io_alloc_rob_id, + input io_alloc_raw_rd_bank_0_valid, + input [9:0] io_alloc_raw_rd_bank_0_id, + input io_alloc_raw_rd_bank_1_valid, + input [9:0] io_alloc_raw_rd_bank_1_id, + input io_alloc_raw_wr_bank_valid, + input [9:0] io_alloc_raw_wr_bank_id, + output io_alloc_renamed_rd_bank_0_valid, + output [9:0] io_alloc_renamed_rd_bank_0_id, + output io_alloc_renamed_rd_bank_1_valid, + output [9:0] io_alloc_renamed_rd_bank_1_id, + output io_alloc_renamed_wr_bank_valid, + output [9:0] io_alloc_renamed_wr_bank_id, + input io_free_valid, + io_free_mask_0, + io_free_mask_1, + io_free_mask_2, + io_free_mask_3, + io_free_mask_4, + io_free_mask_5, + io_free_mask_6, + io_free_mask_7, + io_free_mask_8, + io_free_mask_9, + io_free_mask_10, + io_free_mask_11, + io_free_mask_12, + io_free_mask_13, + io_free_mask_14, + io_free_mask_15 +); + + reg [9:0] v2a_0; + reg [9:0] v2a_1; + reg [9:0] v2a_2; + reg [9:0] v2a_3; + reg [9:0] v2a_4; + reg [9:0] v2a_5; + reg [9:0] v2a_6; + reg [9:0] v2a_7; + reg [9:0] v2a_8; + reg [9:0] v2a_9; + reg [9:0] v2a_10; + reg [9:0] v2a_11; + reg [9:0] v2a_12; + reg [9:0] v2a_13; + reg [9:0] v2a_14; + reg [9:0] v2a_15; + reg aliasInUse_0; + reg aliasInUse_1; + reg aliasInUse_2; + reg aliasInUse_3; + reg aliasInUse_4; + reg aliasInUse_5; + reg aliasInUse_6; + reg aliasInUse_7; + reg aliasInUse_8; + reg aliasInUse_9; + reg aliasInUse_10; + reg aliasInUse_11; + reg aliasInUse_12; + reg aliasInUse_13; + reg aliasInUse_14; + reg aliasInUse_15; + reg entHasWrite_0; + reg entHasWrite_1; + reg entHasWrite_2; + reg entHasWrite_3; + reg entHasWrite_4; + reg entHasWrite_5; + reg entHasWrite_6; + reg entHasWrite_7; + reg entHasWrite_8; + reg entHasWrite_9; + reg entHasWrite_10; + reg entHasWrite_11; + reg entHasWrite_12; + reg entHasWrite_13; + reg entHasWrite_14; + reg entHasWrite_15; + reg [9:0] entNewAlias_0; + reg [9:0] entNewAlias_1; + reg [9:0] entNewAlias_2; + reg [9:0] entNewAlias_3; + reg [9:0] entNewAlias_4; + reg [9:0] entNewAlias_5; + reg [9:0] entNewAlias_6; + reg [9:0] entNewAlias_7; + reg [9:0] entNewAlias_8; + reg [9:0] entNewAlias_9; + reg [9:0] entNewAlias_10; + reg [9:0] entNewAlias_11; + reg [9:0] entNewAlias_12; + reg [9:0] entNewAlias_13; + reg [9:0] entNewAlias_14; + reg [9:0] entNewAlias_15; + reg [3:0] entWrVbank_0; + reg [3:0] entWrVbank_1; + reg [3:0] entWrVbank_2; + reg [3:0] entWrVbank_3; + reg [3:0] entWrVbank_4; + reg [3:0] entWrVbank_5; + reg [3:0] entWrVbank_6; + reg [3:0] entWrVbank_7; + reg [3:0] entWrVbank_8; + reg [3:0] entWrVbank_9; + reg [3:0] entWrVbank_10; + reg [3:0] entWrVbank_11; + reg [3:0] entWrVbank_12; + reg [3:0] entWrVbank_13; + reg [3:0] entWrVbank_14; + reg [3:0] entWrVbank_15; + wire [15:0][9:0] _GEN = + {{v2a_15}, + {v2a_14}, + {v2a_13}, + {v2a_12}, + {v2a_11}, + {v2a_10}, + {v2a_9}, + {v2a_8}, + {v2a_7}, + {v2a_6}, + {v2a_5}, + {v2a_4}, + {v2a_3}, + {v2a_2}, + {v2a_1}, + {v2a_0}}; + wire [9:0] _v2a_T = {6'h0, io_alloc_rob_id} + 10'h10; + wire _GEN_0 = io_free_valid & io_free_mask_0; + wire _GEN_1 = io_free_valid & io_free_mask_1; + wire _GEN_2 = io_free_valid & io_free_mask_2; + wire _GEN_3 = io_free_valid & io_free_mask_3; + wire _GEN_4 = io_free_valid & io_free_mask_4; + wire _GEN_5 = io_free_valid & io_free_mask_5; + wire _GEN_6 = io_free_valid & io_free_mask_6; + wire _GEN_7 = io_free_valid & io_free_mask_7; + wire _GEN_8 = io_free_valid & io_free_mask_8; + wire _GEN_9 = io_free_valid & io_free_mask_9; + wire _GEN_10 = io_free_valid & io_free_mask_10; + wire _GEN_11 = io_free_valid & io_free_mask_11; + wire _GEN_12 = io_free_valid & io_free_mask_12; + wire _GEN_13 = io_free_valid & io_free_mask_13; + wire _GEN_14 = io_free_valid & io_free_mask_14; + wire _GEN_15 = io_free_valid & io_free_mask_15; + `ifndef SYNTHESIS + always @(posedge clock) begin + automatic logic [15:0] _GEN_16 = + {{aliasInUse_15}, + {aliasInUse_14}, + {aliasInUse_13}, + {aliasInUse_12}, + {aliasInUse_11}, + {aliasInUse_10}, + {aliasInUse_9}, + {aliasInUse_8}, + {aliasInUse_7}, + {aliasInUse_6}, + {aliasInUse_5}, + {aliasInUse_4}, + {aliasInUse_3}, + {aliasInUse_2}, + {aliasInUse_1}, + {aliasInUse_0}}; + if (io_alloc_valid & io_alloc_raw_wr_bank_valid & ~reset + & _GEN_16[io_alloc_rob_id]) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: BAT alias reused before free\n at BankAliasTable.scala:101 assert(!aliasInUse(rid), \"BAT alias reused before free\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_0 & entHasWrite_0 & ~reset & ~aliasInUse_0) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: BAT free on non-allocated alias\n at BankAliasTable.scala:111 assert(aliasInUse(i), \"BAT free on non-allocated alias\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_1 & entHasWrite_1 & ~reset & ~aliasInUse_1) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: BAT free on non-allocated alias\n at BankAliasTable.scala:111 assert(aliasInUse(i), \"BAT free on non-allocated alias\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_2 & entHasWrite_2 & ~reset & ~aliasInUse_2) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: BAT free on non-allocated alias\n at BankAliasTable.scala:111 assert(aliasInUse(i), \"BAT free on non-allocated alias\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_3 & entHasWrite_3 & ~reset & ~aliasInUse_3) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: BAT free on non-allocated alias\n at BankAliasTable.scala:111 assert(aliasInUse(i), \"BAT free on non-allocated alias\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_4 & entHasWrite_4 & ~reset & ~aliasInUse_4) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: BAT free on non-allocated alias\n at BankAliasTable.scala:111 assert(aliasInUse(i), \"BAT free on non-allocated alias\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_5 & entHasWrite_5 & ~reset & ~aliasInUse_5) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: BAT free on non-allocated alias\n at BankAliasTable.scala:111 assert(aliasInUse(i), \"BAT free on non-allocated alias\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_6 & entHasWrite_6 & ~reset & ~aliasInUse_6) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: BAT free on non-allocated alias\n at BankAliasTable.scala:111 assert(aliasInUse(i), \"BAT free on non-allocated alias\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_7 & entHasWrite_7 & ~reset & ~aliasInUse_7) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: BAT free on non-allocated alias\n at BankAliasTable.scala:111 assert(aliasInUse(i), \"BAT free on non-allocated alias\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_8 & entHasWrite_8 & ~reset & ~aliasInUse_8) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: BAT free on non-allocated alias\n at BankAliasTable.scala:111 assert(aliasInUse(i), \"BAT free on non-allocated alias\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_9 & entHasWrite_9 & ~reset & ~aliasInUse_9) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: BAT free on non-allocated alias\n at BankAliasTable.scala:111 assert(aliasInUse(i), \"BAT free on non-allocated alias\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_10 & entHasWrite_10 & ~reset & ~aliasInUse_10) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: BAT free on non-allocated alias\n at BankAliasTable.scala:111 assert(aliasInUse(i), \"BAT free on non-allocated alias\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_11 & entHasWrite_11 & ~reset & ~aliasInUse_11) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: BAT free on non-allocated alias\n at BankAliasTable.scala:111 assert(aliasInUse(i), \"BAT free on non-allocated alias\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_12 & entHasWrite_12 & ~reset & ~aliasInUse_12) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: BAT free on non-allocated alias\n at BankAliasTable.scala:111 assert(aliasInUse(i), \"BAT free on non-allocated alias\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_13 & entHasWrite_13 & ~reset & ~aliasInUse_13) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: BAT free on non-allocated alias\n at BankAliasTable.scala:111 assert(aliasInUse(i), \"BAT free on non-allocated alias\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_14 & entHasWrite_14 & ~reset & ~aliasInUse_14) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: BAT free on non-allocated alias\n at BankAliasTable.scala:111 assert(aliasInUse(i), \"BAT free on non-allocated alias\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_15 & entHasWrite_15 & ~reset & ~aliasInUse_15) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: BAT free on non-allocated alias\n at BankAliasTable.scala:111 assert(aliasInUse(i), \"BAT free on non-allocated alias\")\n"); + if (`STOP_COND_) + $fatal; + end + end // always @(posedge) + `endif // not def SYNTHESIS + always @(posedge clock) begin + if (reset) begin + v2a_0 <= 10'h0; + v2a_1 <= 10'h1; + v2a_2 <= 10'h2; + v2a_3 <= 10'h3; + v2a_4 <= 10'h4; + v2a_5 <= 10'h5; + v2a_6 <= 10'h6; + v2a_7 <= 10'h7; + v2a_8 <= 10'h8; + v2a_9 <= 10'h9; + v2a_10 <= 10'hA; + v2a_11 <= 10'hB; + v2a_12 <= 10'hC; + v2a_13 <= 10'hD; + v2a_14 <= 10'hE; + v2a_15 <= 10'hF; + aliasInUse_0 <= 1'h0; + aliasInUse_1 <= 1'h0; + aliasInUse_2 <= 1'h0; + aliasInUse_3 <= 1'h0; + aliasInUse_4 <= 1'h0; + aliasInUse_5 <= 1'h0; + aliasInUse_6 <= 1'h0; + aliasInUse_7 <= 1'h0; + aliasInUse_8 <= 1'h0; + aliasInUse_9 <= 1'h0; + aliasInUse_10 <= 1'h0; + aliasInUse_11 <= 1'h0; + aliasInUse_12 <= 1'h0; + aliasInUse_13 <= 1'h0; + aliasInUse_14 <= 1'h0; + aliasInUse_15 <= 1'h0; + entHasWrite_0 <= 1'h0; + entHasWrite_1 <= 1'h0; + entHasWrite_2 <= 1'h0; + entHasWrite_3 <= 1'h0; + entHasWrite_4 <= 1'h0; + entHasWrite_5 <= 1'h0; + entHasWrite_6 <= 1'h0; + entHasWrite_7 <= 1'h0; + entHasWrite_8 <= 1'h0; + entHasWrite_9 <= 1'h0; + entHasWrite_10 <= 1'h0; + entHasWrite_11 <= 1'h0; + entHasWrite_12 <= 1'h0; + entHasWrite_13 <= 1'h0; + entHasWrite_14 <= 1'h0; + entHasWrite_15 <= 1'h0; + entNewAlias_0 <= 10'h0; + entNewAlias_1 <= 10'h0; + entNewAlias_2 <= 10'h0; + entNewAlias_3 <= 10'h0; + entNewAlias_4 <= 10'h0; + entNewAlias_5 <= 10'h0; + entNewAlias_6 <= 10'h0; + entNewAlias_7 <= 10'h0; + entNewAlias_8 <= 10'h0; + entNewAlias_9 <= 10'h0; + entNewAlias_10 <= 10'h0; + entNewAlias_11 <= 10'h0; + entNewAlias_12 <= 10'h0; + entNewAlias_13 <= 10'h0; + entNewAlias_14 <= 10'h0; + entNewAlias_15 <= 10'h0; + entWrVbank_0 <= 4'h0; + entWrVbank_1 <= 4'h0; + entWrVbank_2 <= 4'h0; + entWrVbank_3 <= 4'h0; + entWrVbank_4 <= 4'h0; + entWrVbank_5 <= 4'h0; + entWrVbank_6 <= 4'h0; + entWrVbank_7 <= 4'h0; + entWrVbank_8 <= 4'h0; + entWrVbank_9 <= 4'h0; + entWrVbank_10 <= 4'h0; + entWrVbank_11 <= 4'h0; + entWrVbank_12 <= 4'h0; + entWrVbank_13 <= 4'h0; + entWrVbank_14 <= 4'h0; + entWrVbank_15 <= 4'h0; + end + else begin + automatic logic _GEN_17 = io_alloc_rob_id == 4'h0; + automatic logic _GEN_18; + automatic logic _GEN_19 = io_alloc_rob_id == 4'h1; + automatic logic _GEN_20; + automatic logic _GEN_21 = io_alloc_rob_id == 4'h2; + automatic logic _GEN_22; + automatic logic _GEN_23 = io_alloc_rob_id == 4'h3; + automatic logic _GEN_24; + automatic logic _GEN_25 = io_alloc_rob_id == 4'h4; + automatic logic _GEN_26; + automatic logic _GEN_27 = io_alloc_rob_id == 4'h5; + automatic logic _GEN_28; + automatic logic _GEN_29 = io_alloc_rob_id == 4'h6; + automatic logic _GEN_30; + automatic logic _GEN_31 = io_alloc_rob_id == 4'h7; + automatic logic _GEN_32; + automatic logic _GEN_33 = io_alloc_rob_id == 4'h8; + automatic logic _GEN_34; + automatic logic _GEN_35 = io_alloc_rob_id == 4'h9; + automatic logic _GEN_36; + automatic logic _GEN_37 = io_alloc_rob_id == 4'hA; + automatic logic _GEN_38; + automatic logic _GEN_39 = io_alloc_rob_id == 4'hB; + automatic logic _GEN_40; + automatic logic _GEN_41 = io_alloc_rob_id == 4'hC; + automatic logic _GEN_42; + automatic logic _GEN_43 = io_alloc_rob_id == 4'hD; + automatic logic _GEN_44; + automatic logic _GEN_45 = io_alloc_rob_id == 4'hE; + automatic logic _GEN_46; + automatic logic _GEN_47; + automatic logic [9:0] _entNewAlias_T_2; + automatic logic _GEN_48; + automatic logic _GEN_49; + automatic logic _GEN_50; + automatic logic _GEN_51; + automatic logic _GEN_52; + automatic logic _GEN_53; + automatic logic _GEN_54; + automatic logic _GEN_55; + automatic logic _GEN_56; + automatic logic _GEN_57; + automatic logic _GEN_58; + automatic logic _GEN_59; + automatic logic _GEN_60; + automatic logic _GEN_61; + automatic logic _GEN_62; + automatic logic _GEN_63; + _GEN_18 = io_alloc_valid & _GEN_17; + _GEN_20 = io_alloc_valid & _GEN_19; + _GEN_22 = io_alloc_valid & _GEN_21; + _GEN_24 = io_alloc_valid & _GEN_23; + _GEN_26 = io_alloc_valid & _GEN_25; + _GEN_28 = io_alloc_valid & _GEN_27; + _GEN_30 = io_alloc_valid & _GEN_29; + _GEN_32 = io_alloc_valid & _GEN_31; + _GEN_34 = io_alloc_valid & _GEN_33; + _GEN_36 = io_alloc_valid & _GEN_35; + _GEN_38 = io_alloc_valid & _GEN_37; + _GEN_40 = io_alloc_valid & _GEN_39; + _GEN_42 = io_alloc_valid & _GEN_41; + _GEN_44 = io_alloc_valid & _GEN_43; + _GEN_46 = io_alloc_valid & _GEN_45; + _GEN_47 = io_alloc_valid & (&io_alloc_rob_id); + _entNewAlias_T_2 = io_alloc_raw_wr_bank_valid ? _v2a_T : 10'h0; + _GEN_48 = + io_alloc_valid & io_alloc_raw_wr_bank_valid + & io_alloc_raw_wr_bank_id[3:0] == 4'h0; + _GEN_49 = + io_alloc_valid & io_alloc_raw_wr_bank_valid + & io_alloc_raw_wr_bank_id[3:0] == 4'h1; + _GEN_50 = + io_alloc_valid & io_alloc_raw_wr_bank_valid + & io_alloc_raw_wr_bank_id[3:0] == 4'h2; + _GEN_51 = + io_alloc_valid & io_alloc_raw_wr_bank_valid + & io_alloc_raw_wr_bank_id[3:0] == 4'h3; + _GEN_52 = + io_alloc_valid & io_alloc_raw_wr_bank_valid + & io_alloc_raw_wr_bank_id[3:0] == 4'h4; + _GEN_53 = + io_alloc_valid & io_alloc_raw_wr_bank_valid + & io_alloc_raw_wr_bank_id[3:0] == 4'h5; + _GEN_54 = + io_alloc_valid & io_alloc_raw_wr_bank_valid + & io_alloc_raw_wr_bank_id[3:0] == 4'h6; + _GEN_55 = + io_alloc_valid & io_alloc_raw_wr_bank_valid + & io_alloc_raw_wr_bank_id[3:0] == 4'h7; + _GEN_56 = + io_alloc_valid & io_alloc_raw_wr_bank_valid + & io_alloc_raw_wr_bank_id[3:0] == 4'h8; + _GEN_57 = + io_alloc_valid & io_alloc_raw_wr_bank_valid + & io_alloc_raw_wr_bank_id[3:0] == 4'h9; + _GEN_58 = + io_alloc_valid & io_alloc_raw_wr_bank_valid + & io_alloc_raw_wr_bank_id[3:0] == 4'hA; + _GEN_59 = + io_alloc_valid & io_alloc_raw_wr_bank_valid + & io_alloc_raw_wr_bank_id[3:0] == 4'hB; + _GEN_60 = + io_alloc_valid & io_alloc_raw_wr_bank_valid + & io_alloc_raw_wr_bank_id[3:0] == 4'hC; + _GEN_61 = + io_alloc_valid & io_alloc_raw_wr_bank_valid + & io_alloc_raw_wr_bank_id[3:0] == 4'hD; + _GEN_62 = + io_alloc_valid & io_alloc_raw_wr_bank_valid + & io_alloc_raw_wr_bank_id[3:0] == 4'hE; + _GEN_63 = + io_alloc_valid & io_alloc_raw_wr_bank_valid & (&(io_alloc_raw_wr_bank_id[3:0])); + if (io_free_valid) begin + automatic logic _GEN_64; + automatic logic [9:0] _GEN_65; + automatic logic _GEN_66; + automatic logic [9:0] _GEN_67; + automatic logic _GEN_68; + automatic logic [9:0] _GEN_69; + automatic logic _GEN_70; + automatic logic [9:0] _GEN_71; + automatic logic _GEN_72; + automatic logic [9:0] _GEN_73; + automatic logic _GEN_74; + automatic logic [9:0] _GEN_75; + automatic logic _GEN_76; + automatic logic [9:0] _GEN_77; + automatic logic _GEN_78; + automatic logic [9:0] _GEN_79; + automatic logic _GEN_80; + automatic logic [9:0] _GEN_81; + automatic logic _GEN_82; + automatic logic [9:0] _GEN_83; + automatic logic _GEN_84; + automatic logic [9:0] _GEN_85; + automatic logic _GEN_86; + automatic logic [9:0] _GEN_87; + automatic logic _GEN_88; + automatic logic [9:0] _GEN_89; + automatic logic _GEN_90; + automatic logic [9:0] _GEN_91; + automatic logic _GEN_92; + automatic logic [9:0] _GEN_93; + automatic logic _GEN_94 = _GEN[entWrVbank_15] == entNewAlias_15; + automatic logic [9:0] _GEN_95; + _GEN_64 = _GEN[entWrVbank_0] == entNewAlias_0; + _GEN_65 = {6'h0, entWrVbank_0}; + _GEN_66 = _GEN[entWrVbank_1] == entNewAlias_1; + _GEN_67 = {6'h0, entWrVbank_1}; + _GEN_68 = _GEN[entWrVbank_2] == entNewAlias_2; + _GEN_69 = {6'h0, entWrVbank_2}; + _GEN_70 = _GEN[entWrVbank_3] == entNewAlias_3; + _GEN_71 = {6'h0, entWrVbank_3}; + _GEN_72 = _GEN[entWrVbank_4] == entNewAlias_4; + _GEN_73 = {6'h0, entWrVbank_4}; + _GEN_74 = _GEN[entWrVbank_5] == entNewAlias_5; + _GEN_75 = {6'h0, entWrVbank_5}; + _GEN_76 = _GEN[entWrVbank_6] == entNewAlias_6; + _GEN_77 = {6'h0, entWrVbank_6}; + _GEN_78 = _GEN[entWrVbank_7] == entNewAlias_7; + _GEN_79 = {6'h0, entWrVbank_7}; + _GEN_80 = _GEN[entWrVbank_8] == entNewAlias_8; + _GEN_81 = {6'h0, entWrVbank_8}; + _GEN_82 = _GEN[entWrVbank_9] == entNewAlias_9; + _GEN_83 = {6'h0, entWrVbank_9}; + _GEN_84 = _GEN[entWrVbank_10] == entNewAlias_10; + _GEN_85 = {6'h0, entWrVbank_10}; + _GEN_86 = _GEN[entWrVbank_11] == entNewAlias_11; + _GEN_87 = {6'h0, entWrVbank_11}; + _GEN_88 = _GEN[entWrVbank_12] == entNewAlias_12; + _GEN_89 = {6'h0, entWrVbank_12}; + _GEN_90 = _GEN[entWrVbank_13] == entNewAlias_13; + _GEN_91 = {6'h0, entWrVbank_13}; + _GEN_92 = _GEN[entWrVbank_14] == entNewAlias_14; + _GEN_93 = {6'h0, entWrVbank_14}; + _GEN_95 = {6'h0, entWrVbank_15}; + if (io_free_mask_15 & entHasWrite_15 & _GEN_94 & entWrVbank_15 == 4'h0) + v2a_0 <= _GEN_95; + else if (io_free_mask_14 & entHasWrite_14 & _GEN_92 & entWrVbank_14 == 4'h0) + v2a_0 <= _GEN_93; + else if (io_free_mask_13 & entHasWrite_13 & _GEN_90 & entWrVbank_13 == 4'h0) + v2a_0 <= _GEN_91; + else if (io_free_mask_12 & entHasWrite_12 & _GEN_88 & entWrVbank_12 == 4'h0) + v2a_0 <= _GEN_89; + else if (io_free_mask_11 & entHasWrite_11 & _GEN_86 & entWrVbank_11 == 4'h0) + v2a_0 <= _GEN_87; + else if (io_free_mask_10 & entHasWrite_10 & _GEN_84 & entWrVbank_10 == 4'h0) + v2a_0 <= _GEN_85; + else if (io_free_mask_9 & entHasWrite_9 & _GEN_82 & entWrVbank_9 == 4'h0) + v2a_0 <= _GEN_83; + else if (io_free_mask_8 & entHasWrite_8 & _GEN_80 & entWrVbank_8 == 4'h0) + v2a_0 <= _GEN_81; + else if (io_free_mask_7 & entHasWrite_7 & _GEN_78 & entWrVbank_7 == 4'h0) + v2a_0 <= _GEN_79; + else if (io_free_mask_6 & entHasWrite_6 & _GEN_76 & entWrVbank_6 == 4'h0) + v2a_0 <= _GEN_77; + else if (io_free_mask_5 & entHasWrite_5 & _GEN_74 & entWrVbank_5 == 4'h0) + v2a_0 <= _GEN_75; + else if (io_free_mask_4 & entHasWrite_4 & _GEN_72 & entWrVbank_4 == 4'h0) + v2a_0 <= _GEN_73; + else if (io_free_mask_3 & entHasWrite_3 & _GEN_70 & entWrVbank_3 == 4'h0) + v2a_0 <= _GEN_71; + else if (io_free_mask_2 & entHasWrite_2 & _GEN_68 & entWrVbank_2 == 4'h0) + v2a_0 <= _GEN_69; + else if (io_free_mask_1 & entHasWrite_1 & _GEN_66 & entWrVbank_1 == 4'h0) + v2a_0 <= _GEN_67; + else if (io_free_mask_0 & entHasWrite_0 & _GEN_64 & entWrVbank_0 == 4'h0) + v2a_0 <= _GEN_65; + else if (_GEN_48) + v2a_0 <= _v2a_T; + if (io_free_mask_15 & entHasWrite_15 & _GEN_94 & entWrVbank_15 == 4'h1) + v2a_1 <= _GEN_95; + else if (io_free_mask_14 & entHasWrite_14 & _GEN_92 & entWrVbank_14 == 4'h1) + v2a_1 <= _GEN_93; + else if (io_free_mask_13 & entHasWrite_13 & _GEN_90 & entWrVbank_13 == 4'h1) + v2a_1 <= _GEN_91; + else if (io_free_mask_12 & entHasWrite_12 & _GEN_88 & entWrVbank_12 == 4'h1) + v2a_1 <= _GEN_89; + else if (io_free_mask_11 & entHasWrite_11 & _GEN_86 & entWrVbank_11 == 4'h1) + v2a_1 <= _GEN_87; + else if (io_free_mask_10 & entHasWrite_10 & _GEN_84 & entWrVbank_10 == 4'h1) + v2a_1 <= _GEN_85; + else if (io_free_mask_9 & entHasWrite_9 & _GEN_82 & entWrVbank_9 == 4'h1) + v2a_1 <= _GEN_83; + else if (io_free_mask_8 & entHasWrite_8 & _GEN_80 & entWrVbank_8 == 4'h1) + v2a_1 <= _GEN_81; + else if (io_free_mask_7 & entHasWrite_7 & _GEN_78 & entWrVbank_7 == 4'h1) + v2a_1 <= _GEN_79; + else if (io_free_mask_6 & entHasWrite_6 & _GEN_76 & entWrVbank_6 == 4'h1) + v2a_1 <= _GEN_77; + else if (io_free_mask_5 & entHasWrite_5 & _GEN_74 & entWrVbank_5 == 4'h1) + v2a_1 <= _GEN_75; + else if (io_free_mask_4 & entHasWrite_4 & _GEN_72 & entWrVbank_4 == 4'h1) + v2a_1 <= _GEN_73; + else if (io_free_mask_3 & entHasWrite_3 & _GEN_70 & entWrVbank_3 == 4'h1) + v2a_1 <= _GEN_71; + else if (io_free_mask_2 & entHasWrite_2 & _GEN_68 & entWrVbank_2 == 4'h1) + v2a_1 <= _GEN_69; + else if (io_free_mask_1 & entHasWrite_1 & _GEN_66 & entWrVbank_1 == 4'h1) + v2a_1 <= _GEN_67; + else if (io_free_mask_0 & entHasWrite_0 & _GEN_64 & entWrVbank_0 == 4'h1) + v2a_1 <= _GEN_65; + else if (_GEN_49) + v2a_1 <= _v2a_T; + if (io_free_mask_15 & entHasWrite_15 & _GEN_94 & entWrVbank_15 == 4'h2) + v2a_2 <= _GEN_95; + else if (io_free_mask_14 & entHasWrite_14 & _GEN_92 & entWrVbank_14 == 4'h2) + v2a_2 <= _GEN_93; + else if (io_free_mask_13 & entHasWrite_13 & _GEN_90 & entWrVbank_13 == 4'h2) + v2a_2 <= _GEN_91; + else if (io_free_mask_12 & entHasWrite_12 & _GEN_88 & entWrVbank_12 == 4'h2) + v2a_2 <= _GEN_89; + else if (io_free_mask_11 & entHasWrite_11 & _GEN_86 & entWrVbank_11 == 4'h2) + v2a_2 <= _GEN_87; + else if (io_free_mask_10 & entHasWrite_10 & _GEN_84 & entWrVbank_10 == 4'h2) + v2a_2 <= _GEN_85; + else if (io_free_mask_9 & entHasWrite_9 & _GEN_82 & entWrVbank_9 == 4'h2) + v2a_2 <= _GEN_83; + else if (io_free_mask_8 & entHasWrite_8 & _GEN_80 & entWrVbank_8 == 4'h2) + v2a_2 <= _GEN_81; + else if (io_free_mask_7 & entHasWrite_7 & _GEN_78 & entWrVbank_7 == 4'h2) + v2a_2 <= _GEN_79; + else if (io_free_mask_6 & entHasWrite_6 & _GEN_76 & entWrVbank_6 == 4'h2) + v2a_2 <= _GEN_77; + else if (io_free_mask_5 & entHasWrite_5 & _GEN_74 & entWrVbank_5 == 4'h2) + v2a_2 <= _GEN_75; + else if (io_free_mask_4 & entHasWrite_4 & _GEN_72 & entWrVbank_4 == 4'h2) + v2a_2 <= _GEN_73; + else if (io_free_mask_3 & entHasWrite_3 & _GEN_70 & entWrVbank_3 == 4'h2) + v2a_2 <= _GEN_71; + else if (io_free_mask_2 & entHasWrite_2 & _GEN_68 & entWrVbank_2 == 4'h2) + v2a_2 <= _GEN_69; + else if (io_free_mask_1 & entHasWrite_1 & _GEN_66 & entWrVbank_1 == 4'h2) + v2a_2 <= _GEN_67; + else if (io_free_mask_0 & entHasWrite_0 & _GEN_64 & entWrVbank_0 == 4'h2) + v2a_2 <= _GEN_65; + else if (_GEN_50) + v2a_2 <= _v2a_T; + if (io_free_mask_15 & entHasWrite_15 & _GEN_94 & entWrVbank_15 == 4'h3) + v2a_3 <= _GEN_95; + else if (io_free_mask_14 & entHasWrite_14 & _GEN_92 & entWrVbank_14 == 4'h3) + v2a_3 <= _GEN_93; + else if (io_free_mask_13 & entHasWrite_13 & _GEN_90 & entWrVbank_13 == 4'h3) + v2a_3 <= _GEN_91; + else if (io_free_mask_12 & entHasWrite_12 & _GEN_88 & entWrVbank_12 == 4'h3) + v2a_3 <= _GEN_89; + else if (io_free_mask_11 & entHasWrite_11 & _GEN_86 & entWrVbank_11 == 4'h3) + v2a_3 <= _GEN_87; + else if (io_free_mask_10 & entHasWrite_10 & _GEN_84 & entWrVbank_10 == 4'h3) + v2a_3 <= _GEN_85; + else if (io_free_mask_9 & entHasWrite_9 & _GEN_82 & entWrVbank_9 == 4'h3) + v2a_3 <= _GEN_83; + else if (io_free_mask_8 & entHasWrite_8 & _GEN_80 & entWrVbank_8 == 4'h3) + v2a_3 <= _GEN_81; + else if (io_free_mask_7 & entHasWrite_7 & _GEN_78 & entWrVbank_7 == 4'h3) + v2a_3 <= _GEN_79; + else if (io_free_mask_6 & entHasWrite_6 & _GEN_76 & entWrVbank_6 == 4'h3) + v2a_3 <= _GEN_77; + else if (io_free_mask_5 & entHasWrite_5 & _GEN_74 & entWrVbank_5 == 4'h3) + v2a_3 <= _GEN_75; + else if (io_free_mask_4 & entHasWrite_4 & _GEN_72 & entWrVbank_4 == 4'h3) + v2a_3 <= _GEN_73; + else if (io_free_mask_3 & entHasWrite_3 & _GEN_70 & entWrVbank_3 == 4'h3) + v2a_3 <= _GEN_71; + else if (io_free_mask_2 & entHasWrite_2 & _GEN_68 & entWrVbank_2 == 4'h3) + v2a_3 <= _GEN_69; + else if (io_free_mask_1 & entHasWrite_1 & _GEN_66 & entWrVbank_1 == 4'h3) + v2a_3 <= _GEN_67; + else if (io_free_mask_0 & entHasWrite_0 & _GEN_64 & entWrVbank_0 == 4'h3) + v2a_3 <= _GEN_65; + else if (_GEN_51) + v2a_3 <= _v2a_T; + if (io_free_mask_15 & entHasWrite_15 & _GEN_94 & entWrVbank_15 == 4'h4) + v2a_4 <= _GEN_95; + else if (io_free_mask_14 & entHasWrite_14 & _GEN_92 & entWrVbank_14 == 4'h4) + v2a_4 <= _GEN_93; + else if (io_free_mask_13 & entHasWrite_13 & _GEN_90 & entWrVbank_13 == 4'h4) + v2a_4 <= _GEN_91; + else if (io_free_mask_12 & entHasWrite_12 & _GEN_88 & entWrVbank_12 == 4'h4) + v2a_4 <= _GEN_89; + else if (io_free_mask_11 & entHasWrite_11 & _GEN_86 & entWrVbank_11 == 4'h4) + v2a_4 <= _GEN_87; + else if (io_free_mask_10 & entHasWrite_10 & _GEN_84 & entWrVbank_10 == 4'h4) + v2a_4 <= _GEN_85; + else if (io_free_mask_9 & entHasWrite_9 & _GEN_82 & entWrVbank_9 == 4'h4) + v2a_4 <= _GEN_83; + else if (io_free_mask_8 & entHasWrite_8 & _GEN_80 & entWrVbank_8 == 4'h4) + v2a_4 <= _GEN_81; + else if (io_free_mask_7 & entHasWrite_7 & _GEN_78 & entWrVbank_7 == 4'h4) + v2a_4 <= _GEN_79; + else if (io_free_mask_6 & entHasWrite_6 & _GEN_76 & entWrVbank_6 == 4'h4) + v2a_4 <= _GEN_77; + else if (io_free_mask_5 & entHasWrite_5 & _GEN_74 & entWrVbank_5 == 4'h4) + v2a_4 <= _GEN_75; + else if (io_free_mask_4 & entHasWrite_4 & _GEN_72 & entWrVbank_4 == 4'h4) + v2a_4 <= _GEN_73; + else if (io_free_mask_3 & entHasWrite_3 & _GEN_70 & entWrVbank_3 == 4'h4) + v2a_4 <= _GEN_71; + else if (io_free_mask_2 & entHasWrite_2 & _GEN_68 & entWrVbank_2 == 4'h4) + v2a_4 <= _GEN_69; + else if (io_free_mask_1 & entHasWrite_1 & _GEN_66 & entWrVbank_1 == 4'h4) + v2a_4 <= _GEN_67; + else if (io_free_mask_0 & entHasWrite_0 & _GEN_64 & entWrVbank_0 == 4'h4) + v2a_4 <= _GEN_65; + else if (_GEN_52) + v2a_4 <= _v2a_T; + if (io_free_mask_15 & entHasWrite_15 & _GEN_94 & entWrVbank_15 == 4'h5) + v2a_5 <= _GEN_95; + else if (io_free_mask_14 & entHasWrite_14 & _GEN_92 & entWrVbank_14 == 4'h5) + v2a_5 <= _GEN_93; + else if (io_free_mask_13 & entHasWrite_13 & _GEN_90 & entWrVbank_13 == 4'h5) + v2a_5 <= _GEN_91; + else if (io_free_mask_12 & entHasWrite_12 & _GEN_88 & entWrVbank_12 == 4'h5) + v2a_5 <= _GEN_89; + else if (io_free_mask_11 & entHasWrite_11 & _GEN_86 & entWrVbank_11 == 4'h5) + v2a_5 <= _GEN_87; + else if (io_free_mask_10 & entHasWrite_10 & _GEN_84 & entWrVbank_10 == 4'h5) + v2a_5 <= _GEN_85; + else if (io_free_mask_9 & entHasWrite_9 & _GEN_82 & entWrVbank_9 == 4'h5) + v2a_5 <= _GEN_83; + else if (io_free_mask_8 & entHasWrite_8 & _GEN_80 & entWrVbank_8 == 4'h5) + v2a_5 <= _GEN_81; + else if (io_free_mask_7 & entHasWrite_7 & _GEN_78 & entWrVbank_7 == 4'h5) + v2a_5 <= _GEN_79; + else if (io_free_mask_6 & entHasWrite_6 & _GEN_76 & entWrVbank_6 == 4'h5) + v2a_5 <= _GEN_77; + else if (io_free_mask_5 & entHasWrite_5 & _GEN_74 & entWrVbank_5 == 4'h5) + v2a_5 <= _GEN_75; + else if (io_free_mask_4 & entHasWrite_4 & _GEN_72 & entWrVbank_4 == 4'h5) + v2a_5 <= _GEN_73; + else if (io_free_mask_3 & entHasWrite_3 & _GEN_70 & entWrVbank_3 == 4'h5) + v2a_5 <= _GEN_71; + else if (io_free_mask_2 & entHasWrite_2 & _GEN_68 & entWrVbank_2 == 4'h5) + v2a_5 <= _GEN_69; + else if (io_free_mask_1 & entHasWrite_1 & _GEN_66 & entWrVbank_1 == 4'h5) + v2a_5 <= _GEN_67; + else if (io_free_mask_0 & entHasWrite_0 & _GEN_64 & entWrVbank_0 == 4'h5) + v2a_5 <= _GEN_65; + else if (_GEN_53) + v2a_5 <= _v2a_T; + if (io_free_mask_15 & entHasWrite_15 & _GEN_94 & entWrVbank_15 == 4'h6) + v2a_6 <= _GEN_95; + else if (io_free_mask_14 & entHasWrite_14 & _GEN_92 & entWrVbank_14 == 4'h6) + v2a_6 <= _GEN_93; + else if (io_free_mask_13 & entHasWrite_13 & _GEN_90 & entWrVbank_13 == 4'h6) + v2a_6 <= _GEN_91; + else if (io_free_mask_12 & entHasWrite_12 & _GEN_88 & entWrVbank_12 == 4'h6) + v2a_6 <= _GEN_89; + else if (io_free_mask_11 & entHasWrite_11 & _GEN_86 & entWrVbank_11 == 4'h6) + v2a_6 <= _GEN_87; + else if (io_free_mask_10 & entHasWrite_10 & _GEN_84 & entWrVbank_10 == 4'h6) + v2a_6 <= _GEN_85; + else if (io_free_mask_9 & entHasWrite_9 & _GEN_82 & entWrVbank_9 == 4'h6) + v2a_6 <= _GEN_83; + else if (io_free_mask_8 & entHasWrite_8 & _GEN_80 & entWrVbank_8 == 4'h6) + v2a_6 <= _GEN_81; + else if (io_free_mask_7 & entHasWrite_7 & _GEN_78 & entWrVbank_7 == 4'h6) + v2a_6 <= _GEN_79; + else if (io_free_mask_6 & entHasWrite_6 & _GEN_76 & entWrVbank_6 == 4'h6) + v2a_6 <= _GEN_77; + else if (io_free_mask_5 & entHasWrite_5 & _GEN_74 & entWrVbank_5 == 4'h6) + v2a_6 <= _GEN_75; + else if (io_free_mask_4 & entHasWrite_4 & _GEN_72 & entWrVbank_4 == 4'h6) + v2a_6 <= _GEN_73; + else if (io_free_mask_3 & entHasWrite_3 & _GEN_70 & entWrVbank_3 == 4'h6) + v2a_6 <= _GEN_71; + else if (io_free_mask_2 & entHasWrite_2 & _GEN_68 & entWrVbank_2 == 4'h6) + v2a_6 <= _GEN_69; + else if (io_free_mask_1 & entHasWrite_1 & _GEN_66 & entWrVbank_1 == 4'h6) + v2a_6 <= _GEN_67; + else if (io_free_mask_0 & entHasWrite_0 & _GEN_64 & entWrVbank_0 == 4'h6) + v2a_6 <= _GEN_65; + else if (_GEN_54) + v2a_6 <= _v2a_T; + if (io_free_mask_15 & entHasWrite_15 & _GEN_94 & entWrVbank_15 == 4'h7) + v2a_7 <= _GEN_95; + else if (io_free_mask_14 & entHasWrite_14 & _GEN_92 & entWrVbank_14 == 4'h7) + v2a_7 <= _GEN_93; + else if (io_free_mask_13 & entHasWrite_13 & _GEN_90 & entWrVbank_13 == 4'h7) + v2a_7 <= _GEN_91; + else if (io_free_mask_12 & entHasWrite_12 & _GEN_88 & entWrVbank_12 == 4'h7) + v2a_7 <= _GEN_89; + else if (io_free_mask_11 & entHasWrite_11 & _GEN_86 & entWrVbank_11 == 4'h7) + v2a_7 <= _GEN_87; + else if (io_free_mask_10 & entHasWrite_10 & _GEN_84 & entWrVbank_10 == 4'h7) + v2a_7 <= _GEN_85; + else if (io_free_mask_9 & entHasWrite_9 & _GEN_82 & entWrVbank_9 == 4'h7) + v2a_7 <= _GEN_83; + else if (io_free_mask_8 & entHasWrite_8 & _GEN_80 & entWrVbank_8 == 4'h7) + v2a_7 <= _GEN_81; + else if (io_free_mask_7 & entHasWrite_7 & _GEN_78 & entWrVbank_7 == 4'h7) + v2a_7 <= _GEN_79; + else if (io_free_mask_6 & entHasWrite_6 & _GEN_76 & entWrVbank_6 == 4'h7) + v2a_7 <= _GEN_77; + else if (io_free_mask_5 & entHasWrite_5 & _GEN_74 & entWrVbank_5 == 4'h7) + v2a_7 <= _GEN_75; + else if (io_free_mask_4 & entHasWrite_4 & _GEN_72 & entWrVbank_4 == 4'h7) + v2a_7 <= _GEN_73; + else if (io_free_mask_3 & entHasWrite_3 & _GEN_70 & entWrVbank_3 == 4'h7) + v2a_7 <= _GEN_71; + else if (io_free_mask_2 & entHasWrite_2 & _GEN_68 & entWrVbank_2 == 4'h7) + v2a_7 <= _GEN_69; + else if (io_free_mask_1 & entHasWrite_1 & _GEN_66 & entWrVbank_1 == 4'h7) + v2a_7 <= _GEN_67; + else if (io_free_mask_0 & entHasWrite_0 & _GEN_64 & entWrVbank_0 == 4'h7) + v2a_7 <= _GEN_65; + else if (_GEN_55) + v2a_7 <= _v2a_T; + if (io_free_mask_15 & entHasWrite_15 & _GEN_94 & entWrVbank_15 == 4'h8) + v2a_8 <= _GEN_95; + else if (io_free_mask_14 & entHasWrite_14 & _GEN_92 & entWrVbank_14 == 4'h8) + v2a_8 <= _GEN_93; + else if (io_free_mask_13 & entHasWrite_13 & _GEN_90 & entWrVbank_13 == 4'h8) + v2a_8 <= _GEN_91; + else if (io_free_mask_12 & entHasWrite_12 & _GEN_88 & entWrVbank_12 == 4'h8) + v2a_8 <= _GEN_89; + else if (io_free_mask_11 & entHasWrite_11 & _GEN_86 & entWrVbank_11 == 4'h8) + v2a_8 <= _GEN_87; + else if (io_free_mask_10 & entHasWrite_10 & _GEN_84 & entWrVbank_10 == 4'h8) + v2a_8 <= _GEN_85; + else if (io_free_mask_9 & entHasWrite_9 & _GEN_82 & entWrVbank_9 == 4'h8) + v2a_8 <= _GEN_83; + else if (io_free_mask_8 & entHasWrite_8 & _GEN_80 & entWrVbank_8 == 4'h8) + v2a_8 <= _GEN_81; + else if (io_free_mask_7 & entHasWrite_7 & _GEN_78 & entWrVbank_7 == 4'h8) + v2a_8 <= _GEN_79; + else if (io_free_mask_6 & entHasWrite_6 & _GEN_76 & entWrVbank_6 == 4'h8) + v2a_8 <= _GEN_77; + else if (io_free_mask_5 & entHasWrite_5 & _GEN_74 & entWrVbank_5 == 4'h8) + v2a_8 <= _GEN_75; + else if (io_free_mask_4 & entHasWrite_4 & _GEN_72 & entWrVbank_4 == 4'h8) + v2a_8 <= _GEN_73; + else if (io_free_mask_3 & entHasWrite_3 & _GEN_70 & entWrVbank_3 == 4'h8) + v2a_8 <= _GEN_71; + else if (io_free_mask_2 & entHasWrite_2 & _GEN_68 & entWrVbank_2 == 4'h8) + v2a_8 <= _GEN_69; + else if (io_free_mask_1 & entHasWrite_1 & _GEN_66 & entWrVbank_1 == 4'h8) + v2a_8 <= _GEN_67; + else if (io_free_mask_0 & entHasWrite_0 & _GEN_64 & entWrVbank_0 == 4'h8) + v2a_8 <= _GEN_65; + else if (_GEN_56) + v2a_8 <= _v2a_T; + if (io_free_mask_15 & entHasWrite_15 & _GEN_94 & entWrVbank_15 == 4'h9) + v2a_9 <= _GEN_95; + else if (io_free_mask_14 & entHasWrite_14 & _GEN_92 & entWrVbank_14 == 4'h9) + v2a_9 <= _GEN_93; + else if (io_free_mask_13 & entHasWrite_13 & _GEN_90 & entWrVbank_13 == 4'h9) + v2a_9 <= _GEN_91; + else if (io_free_mask_12 & entHasWrite_12 & _GEN_88 & entWrVbank_12 == 4'h9) + v2a_9 <= _GEN_89; + else if (io_free_mask_11 & entHasWrite_11 & _GEN_86 & entWrVbank_11 == 4'h9) + v2a_9 <= _GEN_87; + else if (io_free_mask_10 & entHasWrite_10 & _GEN_84 & entWrVbank_10 == 4'h9) + v2a_9 <= _GEN_85; + else if (io_free_mask_9 & entHasWrite_9 & _GEN_82 & entWrVbank_9 == 4'h9) + v2a_9 <= _GEN_83; + else if (io_free_mask_8 & entHasWrite_8 & _GEN_80 & entWrVbank_8 == 4'h9) + v2a_9 <= _GEN_81; + else if (io_free_mask_7 & entHasWrite_7 & _GEN_78 & entWrVbank_7 == 4'h9) + v2a_9 <= _GEN_79; + else if (io_free_mask_6 & entHasWrite_6 & _GEN_76 & entWrVbank_6 == 4'h9) + v2a_9 <= _GEN_77; + else if (io_free_mask_5 & entHasWrite_5 & _GEN_74 & entWrVbank_5 == 4'h9) + v2a_9 <= _GEN_75; + else if (io_free_mask_4 & entHasWrite_4 & _GEN_72 & entWrVbank_4 == 4'h9) + v2a_9 <= _GEN_73; + else if (io_free_mask_3 & entHasWrite_3 & _GEN_70 & entWrVbank_3 == 4'h9) + v2a_9 <= _GEN_71; + else if (io_free_mask_2 & entHasWrite_2 & _GEN_68 & entWrVbank_2 == 4'h9) + v2a_9 <= _GEN_69; + else if (io_free_mask_1 & entHasWrite_1 & _GEN_66 & entWrVbank_1 == 4'h9) + v2a_9 <= _GEN_67; + else if (io_free_mask_0 & entHasWrite_0 & _GEN_64 & entWrVbank_0 == 4'h9) + v2a_9 <= _GEN_65; + else if (_GEN_57) + v2a_9 <= _v2a_T; + if (io_free_mask_15 & entHasWrite_15 & _GEN_94 & entWrVbank_15 == 4'hA) + v2a_10 <= _GEN_95; + else if (io_free_mask_14 & entHasWrite_14 & _GEN_92 & entWrVbank_14 == 4'hA) + v2a_10 <= _GEN_93; + else if (io_free_mask_13 & entHasWrite_13 & _GEN_90 & entWrVbank_13 == 4'hA) + v2a_10 <= _GEN_91; + else if (io_free_mask_12 & entHasWrite_12 & _GEN_88 & entWrVbank_12 == 4'hA) + v2a_10 <= _GEN_89; + else if (io_free_mask_11 & entHasWrite_11 & _GEN_86 & entWrVbank_11 == 4'hA) + v2a_10 <= _GEN_87; + else if (io_free_mask_10 & entHasWrite_10 & _GEN_84 & entWrVbank_10 == 4'hA) + v2a_10 <= _GEN_85; + else if (io_free_mask_9 & entHasWrite_9 & _GEN_82 & entWrVbank_9 == 4'hA) + v2a_10 <= _GEN_83; + else if (io_free_mask_8 & entHasWrite_8 & _GEN_80 & entWrVbank_8 == 4'hA) + v2a_10 <= _GEN_81; + else if (io_free_mask_7 & entHasWrite_7 & _GEN_78 & entWrVbank_7 == 4'hA) + v2a_10 <= _GEN_79; + else if (io_free_mask_6 & entHasWrite_6 & _GEN_76 & entWrVbank_6 == 4'hA) + v2a_10 <= _GEN_77; + else if (io_free_mask_5 & entHasWrite_5 & _GEN_74 & entWrVbank_5 == 4'hA) + v2a_10 <= _GEN_75; + else if (io_free_mask_4 & entHasWrite_4 & _GEN_72 & entWrVbank_4 == 4'hA) + v2a_10 <= _GEN_73; + else if (io_free_mask_3 & entHasWrite_3 & _GEN_70 & entWrVbank_3 == 4'hA) + v2a_10 <= _GEN_71; + else if (io_free_mask_2 & entHasWrite_2 & _GEN_68 & entWrVbank_2 == 4'hA) + v2a_10 <= _GEN_69; + else if (io_free_mask_1 & entHasWrite_1 & _GEN_66 & entWrVbank_1 == 4'hA) + v2a_10 <= _GEN_67; + else if (io_free_mask_0 & entHasWrite_0 & _GEN_64 & entWrVbank_0 == 4'hA) + v2a_10 <= _GEN_65; + else if (_GEN_58) + v2a_10 <= _v2a_T; + if (io_free_mask_15 & entHasWrite_15 & _GEN_94 & entWrVbank_15 == 4'hB) + v2a_11 <= _GEN_95; + else if (io_free_mask_14 & entHasWrite_14 & _GEN_92 & entWrVbank_14 == 4'hB) + v2a_11 <= _GEN_93; + else if (io_free_mask_13 & entHasWrite_13 & _GEN_90 & entWrVbank_13 == 4'hB) + v2a_11 <= _GEN_91; + else if (io_free_mask_12 & entHasWrite_12 & _GEN_88 & entWrVbank_12 == 4'hB) + v2a_11 <= _GEN_89; + else if (io_free_mask_11 & entHasWrite_11 & _GEN_86 & entWrVbank_11 == 4'hB) + v2a_11 <= _GEN_87; + else if (io_free_mask_10 & entHasWrite_10 & _GEN_84 & entWrVbank_10 == 4'hB) + v2a_11 <= _GEN_85; + else if (io_free_mask_9 & entHasWrite_9 & _GEN_82 & entWrVbank_9 == 4'hB) + v2a_11 <= _GEN_83; + else if (io_free_mask_8 & entHasWrite_8 & _GEN_80 & entWrVbank_8 == 4'hB) + v2a_11 <= _GEN_81; + else if (io_free_mask_7 & entHasWrite_7 & _GEN_78 & entWrVbank_7 == 4'hB) + v2a_11 <= _GEN_79; + else if (io_free_mask_6 & entHasWrite_6 & _GEN_76 & entWrVbank_6 == 4'hB) + v2a_11 <= _GEN_77; + else if (io_free_mask_5 & entHasWrite_5 & _GEN_74 & entWrVbank_5 == 4'hB) + v2a_11 <= _GEN_75; + else if (io_free_mask_4 & entHasWrite_4 & _GEN_72 & entWrVbank_4 == 4'hB) + v2a_11 <= _GEN_73; + else if (io_free_mask_3 & entHasWrite_3 & _GEN_70 & entWrVbank_3 == 4'hB) + v2a_11 <= _GEN_71; + else if (io_free_mask_2 & entHasWrite_2 & _GEN_68 & entWrVbank_2 == 4'hB) + v2a_11 <= _GEN_69; + else if (io_free_mask_1 & entHasWrite_1 & _GEN_66 & entWrVbank_1 == 4'hB) + v2a_11 <= _GEN_67; + else if (io_free_mask_0 & entHasWrite_0 & _GEN_64 & entWrVbank_0 == 4'hB) + v2a_11 <= _GEN_65; + else if (_GEN_59) + v2a_11 <= _v2a_T; + if (io_free_mask_15 & entHasWrite_15 & _GEN_94 & entWrVbank_15 == 4'hC) + v2a_12 <= _GEN_95; + else if (io_free_mask_14 & entHasWrite_14 & _GEN_92 & entWrVbank_14 == 4'hC) + v2a_12 <= _GEN_93; + else if (io_free_mask_13 & entHasWrite_13 & _GEN_90 & entWrVbank_13 == 4'hC) + v2a_12 <= _GEN_91; + else if (io_free_mask_12 & entHasWrite_12 & _GEN_88 & entWrVbank_12 == 4'hC) + v2a_12 <= _GEN_89; + else if (io_free_mask_11 & entHasWrite_11 & _GEN_86 & entWrVbank_11 == 4'hC) + v2a_12 <= _GEN_87; + else if (io_free_mask_10 & entHasWrite_10 & _GEN_84 & entWrVbank_10 == 4'hC) + v2a_12 <= _GEN_85; + else if (io_free_mask_9 & entHasWrite_9 & _GEN_82 & entWrVbank_9 == 4'hC) + v2a_12 <= _GEN_83; + else if (io_free_mask_8 & entHasWrite_8 & _GEN_80 & entWrVbank_8 == 4'hC) + v2a_12 <= _GEN_81; + else if (io_free_mask_7 & entHasWrite_7 & _GEN_78 & entWrVbank_7 == 4'hC) + v2a_12 <= _GEN_79; + else if (io_free_mask_6 & entHasWrite_6 & _GEN_76 & entWrVbank_6 == 4'hC) + v2a_12 <= _GEN_77; + else if (io_free_mask_5 & entHasWrite_5 & _GEN_74 & entWrVbank_5 == 4'hC) + v2a_12 <= _GEN_75; + else if (io_free_mask_4 & entHasWrite_4 & _GEN_72 & entWrVbank_4 == 4'hC) + v2a_12 <= _GEN_73; + else if (io_free_mask_3 & entHasWrite_3 & _GEN_70 & entWrVbank_3 == 4'hC) + v2a_12 <= _GEN_71; + else if (io_free_mask_2 & entHasWrite_2 & _GEN_68 & entWrVbank_2 == 4'hC) + v2a_12 <= _GEN_69; + else if (io_free_mask_1 & entHasWrite_1 & _GEN_66 & entWrVbank_1 == 4'hC) + v2a_12 <= _GEN_67; + else if (io_free_mask_0 & entHasWrite_0 & _GEN_64 & entWrVbank_0 == 4'hC) + v2a_12 <= _GEN_65; + else if (_GEN_60) + v2a_12 <= _v2a_T; + if (io_free_mask_15 & entHasWrite_15 & _GEN_94 & entWrVbank_15 == 4'hD) + v2a_13 <= _GEN_95; + else if (io_free_mask_14 & entHasWrite_14 & _GEN_92 & entWrVbank_14 == 4'hD) + v2a_13 <= _GEN_93; + else if (io_free_mask_13 & entHasWrite_13 & _GEN_90 & entWrVbank_13 == 4'hD) + v2a_13 <= _GEN_91; + else if (io_free_mask_12 & entHasWrite_12 & _GEN_88 & entWrVbank_12 == 4'hD) + v2a_13 <= _GEN_89; + else if (io_free_mask_11 & entHasWrite_11 & _GEN_86 & entWrVbank_11 == 4'hD) + v2a_13 <= _GEN_87; + else if (io_free_mask_10 & entHasWrite_10 & _GEN_84 & entWrVbank_10 == 4'hD) + v2a_13 <= _GEN_85; + else if (io_free_mask_9 & entHasWrite_9 & _GEN_82 & entWrVbank_9 == 4'hD) + v2a_13 <= _GEN_83; + else if (io_free_mask_8 & entHasWrite_8 & _GEN_80 & entWrVbank_8 == 4'hD) + v2a_13 <= _GEN_81; + else if (io_free_mask_7 & entHasWrite_7 & _GEN_78 & entWrVbank_7 == 4'hD) + v2a_13 <= _GEN_79; + else if (io_free_mask_6 & entHasWrite_6 & _GEN_76 & entWrVbank_6 == 4'hD) + v2a_13 <= _GEN_77; + else if (io_free_mask_5 & entHasWrite_5 & _GEN_74 & entWrVbank_5 == 4'hD) + v2a_13 <= _GEN_75; + else if (io_free_mask_4 & entHasWrite_4 & _GEN_72 & entWrVbank_4 == 4'hD) + v2a_13 <= _GEN_73; + else if (io_free_mask_3 & entHasWrite_3 & _GEN_70 & entWrVbank_3 == 4'hD) + v2a_13 <= _GEN_71; + else if (io_free_mask_2 & entHasWrite_2 & _GEN_68 & entWrVbank_2 == 4'hD) + v2a_13 <= _GEN_69; + else if (io_free_mask_1 & entHasWrite_1 & _GEN_66 & entWrVbank_1 == 4'hD) + v2a_13 <= _GEN_67; + else if (io_free_mask_0 & entHasWrite_0 & _GEN_64 & entWrVbank_0 == 4'hD) + v2a_13 <= _GEN_65; + else if (_GEN_61) + v2a_13 <= _v2a_T; + if (io_free_mask_15 & entHasWrite_15 & _GEN_94 & entWrVbank_15 == 4'hE) + v2a_14 <= _GEN_95; + else if (io_free_mask_14 & entHasWrite_14 & _GEN_92 & entWrVbank_14 == 4'hE) + v2a_14 <= _GEN_93; + else if (io_free_mask_13 & entHasWrite_13 & _GEN_90 & entWrVbank_13 == 4'hE) + v2a_14 <= _GEN_91; + else if (io_free_mask_12 & entHasWrite_12 & _GEN_88 & entWrVbank_12 == 4'hE) + v2a_14 <= _GEN_89; + else if (io_free_mask_11 & entHasWrite_11 & _GEN_86 & entWrVbank_11 == 4'hE) + v2a_14 <= _GEN_87; + else if (io_free_mask_10 & entHasWrite_10 & _GEN_84 & entWrVbank_10 == 4'hE) + v2a_14 <= _GEN_85; + else if (io_free_mask_9 & entHasWrite_9 & _GEN_82 & entWrVbank_9 == 4'hE) + v2a_14 <= _GEN_83; + else if (io_free_mask_8 & entHasWrite_8 & _GEN_80 & entWrVbank_8 == 4'hE) + v2a_14 <= _GEN_81; + else if (io_free_mask_7 & entHasWrite_7 & _GEN_78 & entWrVbank_7 == 4'hE) + v2a_14 <= _GEN_79; + else if (io_free_mask_6 & entHasWrite_6 & _GEN_76 & entWrVbank_6 == 4'hE) + v2a_14 <= _GEN_77; + else if (io_free_mask_5 & entHasWrite_5 & _GEN_74 & entWrVbank_5 == 4'hE) + v2a_14 <= _GEN_75; + else if (io_free_mask_4 & entHasWrite_4 & _GEN_72 & entWrVbank_4 == 4'hE) + v2a_14 <= _GEN_73; + else if (io_free_mask_3 & entHasWrite_3 & _GEN_70 & entWrVbank_3 == 4'hE) + v2a_14 <= _GEN_71; + else if (io_free_mask_2 & entHasWrite_2 & _GEN_68 & entWrVbank_2 == 4'hE) + v2a_14 <= _GEN_69; + else if (io_free_mask_1 & entHasWrite_1 & _GEN_66 & entWrVbank_1 == 4'hE) + v2a_14 <= _GEN_67; + else if (io_free_mask_0 & entHasWrite_0 & _GEN_64 & entWrVbank_0 == 4'hE) + v2a_14 <= _GEN_65; + else if (_GEN_62) + v2a_14 <= _v2a_T; + if (io_free_mask_15 & entHasWrite_15 & _GEN_94 & (&entWrVbank_15)) + v2a_15 <= _GEN_95; + else if (io_free_mask_14 & entHasWrite_14 & _GEN_92 & (&entWrVbank_14)) + v2a_15 <= _GEN_93; + else if (io_free_mask_13 & entHasWrite_13 & _GEN_90 & (&entWrVbank_13)) + v2a_15 <= _GEN_91; + else if (io_free_mask_12 & entHasWrite_12 & _GEN_88 & (&entWrVbank_12)) + v2a_15 <= _GEN_89; + else if (io_free_mask_11 & entHasWrite_11 & _GEN_86 & (&entWrVbank_11)) + v2a_15 <= _GEN_87; + else if (io_free_mask_10 & entHasWrite_10 & _GEN_84 & (&entWrVbank_10)) + v2a_15 <= _GEN_85; + else if (io_free_mask_9 & entHasWrite_9 & _GEN_82 & (&entWrVbank_9)) + v2a_15 <= _GEN_83; + else if (io_free_mask_8 & entHasWrite_8 & _GEN_80 & (&entWrVbank_8)) + v2a_15 <= _GEN_81; + else if (io_free_mask_7 & entHasWrite_7 & _GEN_78 & (&entWrVbank_7)) + v2a_15 <= _GEN_79; + else if (io_free_mask_6 & entHasWrite_6 & _GEN_76 & (&entWrVbank_6)) + v2a_15 <= _GEN_77; + else if (io_free_mask_5 & entHasWrite_5 & _GEN_74 & (&entWrVbank_5)) + v2a_15 <= _GEN_75; + else if (io_free_mask_4 & entHasWrite_4 & _GEN_72 & (&entWrVbank_4)) + v2a_15 <= _GEN_73; + else if (io_free_mask_3 & entHasWrite_3 & _GEN_70 & (&entWrVbank_3)) + v2a_15 <= _GEN_71; + else if (io_free_mask_2 & entHasWrite_2 & _GEN_68 & (&entWrVbank_2)) + v2a_15 <= _GEN_69; + else if (io_free_mask_1 & entHasWrite_1 & _GEN_66 & (&entWrVbank_1)) + v2a_15 <= _GEN_67; + else if (io_free_mask_0 & entHasWrite_0 & _GEN_64 & (&entWrVbank_0)) + v2a_15 <= _GEN_65; + else if (_GEN_63) + v2a_15 <= _v2a_T; + end + else begin + if (_GEN_48) + v2a_0 <= _v2a_T; + if (_GEN_49) + v2a_1 <= _v2a_T; + if (_GEN_50) + v2a_2 <= _v2a_T; + if (_GEN_51) + v2a_3 <= _v2a_T; + if (_GEN_52) + v2a_4 <= _v2a_T; + if (_GEN_53) + v2a_5 <= _v2a_T; + if (_GEN_54) + v2a_6 <= _v2a_T; + if (_GEN_55) + v2a_7 <= _v2a_T; + if (_GEN_56) + v2a_8 <= _v2a_T; + if (_GEN_57) + v2a_9 <= _v2a_T; + if (_GEN_58) + v2a_10 <= _v2a_T; + if (_GEN_59) + v2a_11 <= _v2a_T; + if (_GEN_60) + v2a_12 <= _v2a_T; + if (_GEN_61) + v2a_13 <= _v2a_T; + if (_GEN_62) + v2a_14 <= _v2a_T; + if (_GEN_63) + v2a_15 <= _v2a_T; + end + aliasInUse_0 <= + ~(io_free_valid & io_free_mask_0 & entHasWrite_0) + & (io_alloc_valid & io_alloc_raw_wr_bank_valid & _GEN_17 | aliasInUse_0); + aliasInUse_1 <= + ~(io_free_valid & io_free_mask_1 & entHasWrite_1) + & (io_alloc_valid & io_alloc_raw_wr_bank_valid & _GEN_19 | aliasInUse_1); + aliasInUse_2 <= + ~(io_free_valid & io_free_mask_2 & entHasWrite_2) + & (io_alloc_valid & io_alloc_raw_wr_bank_valid & _GEN_21 | aliasInUse_2); + aliasInUse_3 <= + ~(io_free_valid & io_free_mask_3 & entHasWrite_3) + & (io_alloc_valid & io_alloc_raw_wr_bank_valid & _GEN_23 | aliasInUse_3); + aliasInUse_4 <= + ~(io_free_valid & io_free_mask_4 & entHasWrite_4) + & (io_alloc_valid & io_alloc_raw_wr_bank_valid & _GEN_25 | aliasInUse_4); + aliasInUse_5 <= + ~(io_free_valid & io_free_mask_5 & entHasWrite_5) + & (io_alloc_valid & io_alloc_raw_wr_bank_valid & _GEN_27 | aliasInUse_5); + aliasInUse_6 <= + ~(io_free_valid & io_free_mask_6 & entHasWrite_6) + & (io_alloc_valid & io_alloc_raw_wr_bank_valid & _GEN_29 | aliasInUse_6); + aliasInUse_7 <= + ~(io_free_valid & io_free_mask_7 & entHasWrite_7) + & (io_alloc_valid & io_alloc_raw_wr_bank_valid & _GEN_31 | aliasInUse_7); + aliasInUse_8 <= + ~(io_free_valid & io_free_mask_8 & entHasWrite_8) + & (io_alloc_valid & io_alloc_raw_wr_bank_valid & _GEN_33 | aliasInUse_8); + aliasInUse_9 <= + ~(io_free_valid & io_free_mask_9 & entHasWrite_9) + & (io_alloc_valid & io_alloc_raw_wr_bank_valid & _GEN_35 | aliasInUse_9); + aliasInUse_10 <= + ~(io_free_valid & io_free_mask_10 & entHasWrite_10) + & (io_alloc_valid & io_alloc_raw_wr_bank_valid & _GEN_37 | aliasInUse_10); + aliasInUse_11 <= + ~(io_free_valid & io_free_mask_11 & entHasWrite_11) + & (io_alloc_valid & io_alloc_raw_wr_bank_valid & _GEN_39 | aliasInUse_11); + aliasInUse_12 <= + ~(io_free_valid & io_free_mask_12 & entHasWrite_12) + & (io_alloc_valid & io_alloc_raw_wr_bank_valid & _GEN_41 | aliasInUse_12); + aliasInUse_13 <= + ~(io_free_valid & io_free_mask_13 & entHasWrite_13) + & (io_alloc_valid & io_alloc_raw_wr_bank_valid & _GEN_43 | aliasInUse_13); + aliasInUse_14 <= + ~(io_free_valid & io_free_mask_14 & entHasWrite_14) + & (io_alloc_valid & io_alloc_raw_wr_bank_valid & _GEN_45 | aliasInUse_14); + aliasInUse_15 <= + ~(io_free_valid & io_free_mask_15 & entHasWrite_15) + & (io_alloc_valid & io_alloc_raw_wr_bank_valid & (&io_alloc_rob_id) + | aliasInUse_15); + entHasWrite_0 <= ~_GEN_0 & (_GEN_18 ? io_alloc_raw_wr_bank_valid : entHasWrite_0); + entHasWrite_1 <= ~_GEN_1 & (_GEN_20 ? io_alloc_raw_wr_bank_valid : entHasWrite_1); + entHasWrite_2 <= ~_GEN_2 & (_GEN_22 ? io_alloc_raw_wr_bank_valid : entHasWrite_2); + entHasWrite_3 <= ~_GEN_3 & (_GEN_24 ? io_alloc_raw_wr_bank_valid : entHasWrite_3); + entHasWrite_4 <= ~_GEN_4 & (_GEN_26 ? io_alloc_raw_wr_bank_valid : entHasWrite_4); + entHasWrite_5 <= ~_GEN_5 & (_GEN_28 ? io_alloc_raw_wr_bank_valid : entHasWrite_5); + entHasWrite_6 <= ~_GEN_6 & (_GEN_30 ? io_alloc_raw_wr_bank_valid : entHasWrite_6); + entHasWrite_7 <= ~_GEN_7 & (_GEN_32 ? io_alloc_raw_wr_bank_valid : entHasWrite_7); + entHasWrite_8 <= ~_GEN_8 & (_GEN_34 ? io_alloc_raw_wr_bank_valid : entHasWrite_8); + entHasWrite_9 <= ~_GEN_9 & (_GEN_36 ? io_alloc_raw_wr_bank_valid : entHasWrite_9); + entHasWrite_10 <= + ~_GEN_10 & (_GEN_38 ? io_alloc_raw_wr_bank_valid : entHasWrite_10); + entHasWrite_11 <= + ~_GEN_11 & (_GEN_40 ? io_alloc_raw_wr_bank_valid : entHasWrite_11); + entHasWrite_12 <= + ~_GEN_12 & (_GEN_42 ? io_alloc_raw_wr_bank_valid : entHasWrite_12); + entHasWrite_13 <= + ~_GEN_13 & (_GEN_44 ? io_alloc_raw_wr_bank_valid : entHasWrite_13); + entHasWrite_14 <= + ~_GEN_14 & (_GEN_46 ? io_alloc_raw_wr_bank_valid : entHasWrite_14); + entHasWrite_15 <= + ~_GEN_15 & (_GEN_47 ? io_alloc_raw_wr_bank_valid : entHasWrite_15); + if (_GEN_0) begin + entNewAlias_0 <= 10'h0; + entWrVbank_0 <= 4'h0; + end + else if (_GEN_18) begin + entNewAlias_0 <= _entNewAlias_T_2; + entWrVbank_0 <= io_alloc_raw_wr_bank_id[3:0]; + end + if (_GEN_1) begin + entNewAlias_1 <= 10'h0; + entWrVbank_1 <= 4'h0; + end + else if (_GEN_20) begin + entNewAlias_1 <= _entNewAlias_T_2; + entWrVbank_1 <= io_alloc_raw_wr_bank_id[3:0]; + end + if (_GEN_2) begin + entNewAlias_2 <= 10'h0; + entWrVbank_2 <= 4'h0; + end + else if (_GEN_22) begin + entNewAlias_2 <= _entNewAlias_T_2; + entWrVbank_2 <= io_alloc_raw_wr_bank_id[3:0]; + end + if (_GEN_3) begin + entNewAlias_3 <= 10'h0; + entWrVbank_3 <= 4'h0; + end + else if (_GEN_24) begin + entNewAlias_3 <= _entNewAlias_T_2; + entWrVbank_3 <= io_alloc_raw_wr_bank_id[3:0]; + end + if (_GEN_4) begin + entNewAlias_4 <= 10'h0; + entWrVbank_4 <= 4'h0; + end + else if (_GEN_26) begin + entNewAlias_4 <= _entNewAlias_T_2; + entWrVbank_4 <= io_alloc_raw_wr_bank_id[3:0]; + end + if (_GEN_5) begin + entNewAlias_5 <= 10'h0; + entWrVbank_5 <= 4'h0; + end + else if (_GEN_28) begin + entNewAlias_5 <= _entNewAlias_T_2; + entWrVbank_5 <= io_alloc_raw_wr_bank_id[3:0]; + end + if (_GEN_6) begin + entNewAlias_6 <= 10'h0; + entWrVbank_6 <= 4'h0; + end + else if (_GEN_30) begin + entNewAlias_6 <= _entNewAlias_T_2; + entWrVbank_6 <= io_alloc_raw_wr_bank_id[3:0]; + end + if (_GEN_7) begin + entNewAlias_7 <= 10'h0; + entWrVbank_7 <= 4'h0; + end + else if (_GEN_32) begin + entNewAlias_7 <= _entNewAlias_T_2; + entWrVbank_7 <= io_alloc_raw_wr_bank_id[3:0]; + end + if (_GEN_8) begin + entNewAlias_8 <= 10'h0; + entWrVbank_8 <= 4'h0; + end + else if (_GEN_34) begin + entNewAlias_8 <= _entNewAlias_T_2; + entWrVbank_8 <= io_alloc_raw_wr_bank_id[3:0]; + end + if (_GEN_9) begin + entNewAlias_9 <= 10'h0; + entWrVbank_9 <= 4'h0; + end + else if (_GEN_36) begin + entNewAlias_9 <= _entNewAlias_T_2; + entWrVbank_9 <= io_alloc_raw_wr_bank_id[3:0]; + end + if (_GEN_10) begin + entNewAlias_10 <= 10'h0; + entWrVbank_10 <= 4'h0; + end + else if (_GEN_38) begin + entNewAlias_10 <= _entNewAlias_T_2; + entWrVbank_10 <= io_alloc_raw_wr_bank_id[3:0]; + end + if (_GEN_11) begin + entNewAlias_11 <= 10'h0; + entWrVbank_11 <= 4'h0; + end + else if (_GEN_40) begin + entNewAlias_11 <= _entNewAlias_T_2; + entWrVbank_11 <= io_alloc_raw_wr_bank_id[3:0]; + end + if (_GEN_12) begin + entNewAlias_12 <= 10'h0; + entWrVbank_12 <= 4'h0; + end + else if (_GEN_42) begin + entNewAlias_12 <= _entNewAlias_T_2; + entWrVbank_12 <= io_alloc_raw_wr_bank_id[3:0]; + end + if (_GEN_13) begin + entNewAlias_13 <= 10'h0; + entWrVbank_13 <= 4'h0; + end + else if (_GEN_44) begin + entNewAlias_13 <= _entNewAlias_T_2; + entWrVbank_13 <= io_alloc_raw_wr_bank_id[3:0]; + end + if (_GEN_14) begin + entNewAlias_14 <= 10'h0; + entWrVbank_14 <= 4'h0; + end + else if (_GEN_46) begin + entNewAlias_14 <= _entNewAlias_T_2; + entWrVbank_14 <= io_alloc_raw_wr_bank_id[3:0]; + end + if (_GEN_15) begin + entNewAlias_15 <= 10'h0; + entWrVbank_15 <= 4'h0; + end + else if (_GEN_47) begin + entNewAlias_15 <= _entNewAlias_T_2; + entWrVbank_15 <= io_alloc_raw_wr_bank_id[3:0]; + end + end + end // always @(posedge) + assign io_alloc_renamed_rd_bank_0_valid = io_alloc_raw_rd_bank_0_valid; + assign io_alloc_renamed_rd_bank_0_id = + io_alloc_raw_rd_bank_0_valid ? _GEN[io_alloc_raw_rd_bank_0_id[3:0]] : 10'h0; + assign io_alloc_renamed_rd_bank_1_valid = io_alloc_raw_rd_bank_1_valid; + assign io_alloc_renamed_rd_bank_1_id = + io_alloc_raw_rd_bank_1_valid ? _GEN[io_alloc_raw_rd_bank_1_id[3:0]] : 10'h0; + assign io_alloc_renamed_wr_bank_valid = io_alloc_raw_wr_bank_valid; + assign io_alloc_renamed_wr_bank_id = io_alloc_raw_wr_bank_valid ? _v2a_T : 10'h0; +endmodule + +module BankScoreboard( + input clock, + reset, + alloc_valid, + alloc_bits_wr_bank_valid, + input [9:0] alloc_bits_wr_bank_id, + input complete_valid, + complete_bits_wr_bank_valid, + input [9:0] complete_bits_wr_bank_id, + input queryVec_0_rd_bank_0_valid, + input [9:0] queryVec_0_rd_bank_0_id, + input queryVec_0_rd_bank_1_valid, + input [9:0] queryVec_0_rd_bank_1_id, + input queryVec_1_rd_bank_0_valid, + input [9:0] queryVec_1_rd_bank_0_id, + input queryVec_1_rd_bank_1_valid, + input [9:0] queryVec_1_rd_bank_1_id, + input queryVec_2_rd_bank_0_valid, + input [9:0] queryVec_2_rd_bank_0_id, + input queryVec_2_rd_bank_1_valid, + input [9:0] queryVec_2_rd_bank_1_id, + input queryVec_3_rd_bank_0_valid, + input [9:0] queryVec_3_rd_bank_0_id, + input queryVec_3_rd_bank_1_valid, + input [9:0] queryVec_3_rd_bank_1_id, + input queryVec_4_rd_bank_0_valid, + input [9:0] queryVec_4_rd_bank_0_id, + input queryVec_4_rd_bank_1_valid, + input [9:0] queryVec_4_rd_bank_1_id, + input queryVec_5_rd_bank_0_valid, + input [9:0] queryVec_5_rd_bank_0_id, + input queryVec_5_rd_bank_1_valid, + input [9:0] queryVec_5_rd_bank_1_id, + input queryVec_6_rd_bank_0_valid, + input [9:0] queryVec_6_rd_bank_0_id, + input queryVec_6_rd_bank_1_valid, + input [9:0] queryVec_6_rd_bank_1_id, + input queryVec_7_rd_bank_0_valid, + input [9:0] queryVec_7_rd_bank_0_id, + input queryVec_7_rd_bank_1_valid, + input [9:0] queryVec_7_rd_bank_1_id, + input queryVec_8_rd_bank_0_valid, + input [9:0] queryVec_8_rd_bank_0_id, + input queryVec_8_rd_bank_1_valid, + input [9:0] queryVec_8_rd_bank_1_id, + input queryVec_9_rd_bank_0_valid, + input [9:0] queryVec_9_rd_bank_0_id, + input queryVec_9_rd_bank_1_valid, + input [9:0] queryVec_9_rd_bank_1_id, + input queryVec_10_rd_bank_0_valid, + input [9:0] queryVec_10_rd_bank_0_id, + input queryVec_10_rd_bank_1_valid, + input [9:0] queryVec_10_rd_bank_1_id, + input queryVec_11_rd_bank_0_valid, + input [9:0] queryVec_11_rd_bank_0_id, + input queryVec_11_rd_bank_1_valid, + input [9:0] queryVec_11_rd_bank_1_id, + input queryVec_12_rd_bank_0_valid, + input [9:0] queryVec_12_rd_bank_0_id, + input queryVec_12_rd_bank_1_valid, + input [9:0] queryVec_12_rd_bank_1_id, + input queryVec_13_rd_bank_0_valid, + input [9:0] queryVec_13_rd_bank_0_id, + input queryVec_13_rd_bank_1_valid, + input [9:0] queryVec_13_rd_bank_1_id, + input queryVec_14_rd_bank_0_valid, + input [9:0] queryVec_14_rd_bank_0_id, + input queryVec_14_rd_bank_1_valid, + input [9:0] queryVec_14_rd_bank_1_id, + input queryVec_15_rd_bank_0_valid, + input [9:0] queryVec_15_rd_bank_0_id, + input queryVec_15_rd_bank_1_valid, + input [9:0] queryVec_15_rd_bank_1_id, + output hazardVec_0, + hazardVec_1, + hazardVec_2, + hazardVec_3, + hazardVec_4, + hazardVec_5, + hazardVec_6, + hazardVec_7, + hazardVec_8, + hazardVec_9, + hazardVec_10, + hazardVec_11, + hazardVec_12, + hazardVec_13, + hazardVec_14, + hazardVec_15 +); + + reg bankWrBusy_0; + reg bankWrBusy_1; + reg bankWrBusy_2; + reg bankWrBusy_3; + reg bankWrBusy_4; + reg bankWrBusy_5; + reg bankWrBusy_6; + reg bankWrBusy_7; + reg bankWrBusy_8; + reg bankWrBusy_9; + reg bankWrBusy_10; + reg bankWrBusy_11; + reg bankWrBusy_12; + reg bankWrBusy_13; + reg bankWrBusy_14; + reg bankWrBusy_15; + reg bankWrBusy_16; + reg bankWrBusy_17; + reg bankWrBusy_18; + reg bankWrBusy_19; + reg bankWrBusy_20; + reg bankWrBusy_21; + reg bankWrBusy_22; + reg bankWrBusy_23; + reg bankWrBusy_24; + reg bankWrBusy_25; + reg bankWrBusy_26; + reg bankWrBusy_27; + reg bankWrBusy_28; + reg bankWrBusy_29; + reg bankWrBusy_30; + reg bankWrBusy_31; + wire [31:0] _GEN = + {{bankWrBusy_31}, + {bankWrBusy_30}, + {bankWrBusy_29}, + {bankWrBusy_28}, + {bankWrBusy_27}, + {bankWrBusy_26}, + {bankWrBusy_25}, + {bankWrBusy_24}, + {bankWrBusy_23}, + {bankWrBusy_22}, + {bankWrBusy_21}, + {bankWrBusy_20}, + {bankWrBusy_19}, + {bankWrBusy_18}, + {bankWrBusy_17}, + {bankWrBusy_16}, + {bankWrBusy_15}, + {bankWrBusy_14}, + {bankWrBusy_13}, + {bankWrBusy_12}, + {bankWrBusy_11}, + {bankWrBusy_10}, + {bankWrBusy_9}, + {bankWrBusy_8}, + {bankWrBusy_7}, + {bankWrBusy_6}, + {bankWrBusy_5}, + {bankWrBusy_4}, + {bankWrBusy_3}, + {bankWrBusy_2}, + {bankWrBusy_1}, + {bankWrBusy_0}}; + always @(posedge clock) begin + if (reset) begin + bankWrBusy_0 <= 1'h0; + bankWrBusy_1 <= 1'h0; + bankWrBusy_2 <= 1'h0; + bankWrBusy_3 <= 1'h0; + bankWrBusy_4 <= 1'h0; + bankWrBusy_5 <= 1'h0; + bankWrBusy_6 <= 1'h0; + bankWrBusy_7 <= 1'h0; + bankWrBusy_8 <= 1'h0; + bankWrBusy_9 <= 1'h0; + bankWrBusy_10 <= 1'h0; + bankWrBusy_11 <= 1'h0; + bankWrBusy_12 <= 1'h0; + bankWrBusy_13 <= 1'h0; + bankWrBusy_14 <= 1'h0; + bankWrBusy_15 <= 1'h0; + bankWrBusy_16 <= 1'h0; + bankWrBusy_17 <= 1'h0; + bankWrBusy_18 <= 1'h0; + bankWrBusy_19 <= 1'h0; + bankWrBusy_20 <= 1'h0; + bankWrBusy_21 <= 1'h0; + bankWrBusy_22 <= 1'h0; + bankWrBusy_23 <= 1'h0; + bankWrBusy_24 <= 1'h0; + bankWrBusy_25 <= 1'h0; + bankWrBusy_26 <= 1'h0; + bankWrBusy_27 <= 1'h0; + bankWrBusy_28 <= 1'h0; + bankWrBusy_29 <= 1'h0; + bankWrBusy_30 <= 1'h0; + bankWrBusy_31 <= 1'h0; + end + else begin + automatic logic _allocWr_T_62 = alloc_valid & alloc_bits_wr_bank_valid; + automatic logic _cmpWr_T_62 = complete_valid & complete_bits_wr_bank_valid; + automatic logic cmpWr = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h0; + automatic logic cmpWr_1 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h1; + automatic logic cmpWr_2 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h2; + automatic logic cmpWr_3 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h3; + automatic logic cmpWr_4 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h4; + automatic logic cmpWr_5 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h5; + automatic logic cmpWr_6 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h6; + automatic logic cmpWr_7 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h7; + automatic logic cmpWr_8 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h8; + automatic logic cmpWr_9 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h9; + automatic logic cmpWr_10 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'hA; + automatic logic cmpWr_11 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'hB; + automatic logic cmpWr_12 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'hC; + automatic logic cmpWr_13 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'hD; + automatic logic cmpWr_14 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'hE; + automatic logic cmpWr_15 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'hF; + automatic logic cmpWr_16 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h10; + automatic logic cmpWr_17 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h11; + automatic logic cmpWr_18 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h12; + automatic logic cmpWr_19 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h13; + automatic logic cmpWr_20 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h14; + automatic logic cmpWr_21 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h15; + automatic logic cmpWr_22 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h16; + automatic logic cmpWr_23 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h17; + automatic logic cmpWr_24 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h18; + automatic logic cmpWr_25 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h19; + automatic logic cmpWr_26 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h1A; + automatic logic cmpWr_27 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h1B; + automatic logic cmpWr_28 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h1C; + automatic logic cmpWr_29 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h1D; + automatic logic cmpWr_30 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h1E; + automatic logic cmpWr_31 = _cmpWr_T_62 & complete_bits_wr_bank_id == 10'h1F; + bankWrBusy_0 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h0 & ~cmpWr | ~cmpWr & bankWrBusy_0; + bankWrBusy_1 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h1 & ~cmpWr_1 | ~cmpWr_1 + & bankWrBusy_1; + bankWrBusy_2 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h2 & ~cmpWr_2 | ~cmpWr_2 + & bankWrBusy_2; + bankWrBusy_3 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h3 & ~cmpWr_3 | ~cmpWr_3 + & bankWrBusy_3; + bankWrBusy_4 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h4 & ~cmpWr_4 | ~cmpWr_4 + & bankWrBusy_4; + bankWrBusy_5 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h5 & ~cmpWr_5 | ~cmpWr_5 + & bankWrBusy_5; + bankWrBusy_6 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h6 & ~cmpWr_6 | ~cmpWr_6 + & bankWrBusy_6; + bankWrBusy_7 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h7 & ~cmpWr_7 | ~cmpWr_7 + & bankWrBusy_7; + bankWrBusy_8 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h8 & ~cmpWr_8 | ~cmpWr_8 + & bankWrBusy_8; + bankWrBusy_9 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h9 & ~cmpWr_9 | ~cmpWr_9 + & bankWrBusy_9; + bankWrBusy_10 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'hA & ~cmpWr_10 | ~cmpWr_10 + & bankWrBusy_10; + bankWrBusy_11 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'hB & ~cmpWr_11 | ~cmpWr_11 + & bankWrBusy_11; + bankWrBusy_12 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'hC & ~cmpWr_12 | ~cmpWr_12 + & bankWrBusy_12; + bankWrBusy_13 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'hD & ~cmpWr_13 | ~cmpWr_13 + & bankWrBusy_13; + bankWrBusy_14 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'hE & ~cmpWr_14 | ~cmpWr_14 + & bankWrBusy_14; + bankWrBusy_15 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'hF & ~cmpWr_15 | ~cmpWr_15 + & bankWrBusy_15; + bankWrBusy_16 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h10 & ~cmpWr_16 | ~cmpWr_16 + & bankWrBusy_16; + bankWrBusy_17 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h11 & ~cmpWr_17 | ~cmpWr_17 + & bankWrBusy_17; + bankWrBusy_18 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h12 & ~cmpWr_18 | ~cmpWr_18 + & bankWrBusy_18; + bankWrBusy_19 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h13 & ~cmpWr_19 | ~cmpWr_19 + & bankWrBusy_19; + bankWrBusy_20 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h14 & ~cmpWr_20 | ~cmpWr_20 + & bankWrBusy_20; + bankWrBusy_21 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h15 & ~cmpWr_21 | ~cmpWr_21 + & bankWrBusy_21; + bankWrBusy_22 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h16 & ~cmpWr_22 | ~cmpWr_22 + & bankWrBusy_22; + bankWrBusy_23 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h17 & ~cmpWr_23 | ~cmpWr_23 + & bankWrBusy_23; + bankWrBusy_24 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h18 & ~cmpWr_24 | ~cmpWr_24 + & bankWrBusy_24; + bankWrBusy_25 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h19 & ~cmpWr_25 | ~cmpWr_25 + & bankWrBusy_25; + bankWrBusy_26 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h1A & ~cmpWr_26 | ~cmpWr_26 + & bankWrBusy_26; + bankWrBusy_27 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h1B & ~cmpWr_27 | ~cmpWr_27 + & bankWrBusy_27; + bankWrBusy_28 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h1C & ~cmpWr_28 | ~cmpWr_28 + & bankWrBusy_28; + bankWrBusy_29 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h1D & ~cmpWr_29 | ~cmpWr_29 + & bankWrBusy_29; + bankWrBusy_30 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h1E & ~cmpWr_30 | ~cmpWr_30 + & bankWrBusy_30; + bankWrBusy_31 <= + _allocWr_T_62 & alloc_bits_wr_bank_id == 10'h1F & ~cmpWr_31 | ~cmpWr_31 + & bankWrBusy_31; + end + end // always @(posedge) + assign hazardVec_0 = + queryVec_0_rd_bank_0_valid & _GEN[queryVec_0_rd_bank_0_id[4:0]] + | queryVec_0_rd_bank_1_valid & _GEN[queryVec_0_rd_bank_1_id[4:0]]; + assign hazardVec_1 = + queryVec_1_rd_bank_0_valid & _GEN[queryVec_1_rd_bank_0_id[4:0]] + | queryVec_1_rd_bank_1_valid & _GEN[queryVec_1_rd_bank_1_id[4:0]]; + assign hazardVec_2 = + queryVec_2_rd_bank_0_valid & _GEN[queryVec_2_rd_bank_0_id[4:0]] + | queryVec_2_rd_bank_1_valid & _GEN[queryVec_2_rd_bank_1_id[4:0]]; + assign hazardVec_3 = + queryVec_3_rd_bank_0_valid & _GEN[queryVec_3_rd_bank_0_id[4:0]] + | queryVec_3_rd_bank_1_valid & _GEN[queryVec_3_rd_bank_1_id[4:0]]; + assign hazardVec_4 = + queryVec_4_rd_bank_0_valid & _GEN[queryVec_4_rd_bank_0_id[4:0]] + | queryVec_4_rd_bank_1_valid & _GEN[queryVec_4_rd_bank_1_id[4:0]]; + assign hazardVec_5 = + queryVec_5_rd_bank_0_valid & _GEN[queryVec_5_rd_bank_0_id[4:0]] + | queryVec_5_rd_bank_1_valid & _GEN[queryVec_5_rd_bank_1_id[4:0]]; + assign hazardVec_6 = + queryVec_6_rd_bank_0_valid & _GEN[queryVec_6_rd_bank_0_id[4:0]] + | queryVec_6_rd_bank_1_valid & _GEN[queryVec_6_rd_bank_1_id[4:0]]; + assign hazardVec_7 = + queryVec_7_rd_bank_0_valid & _GEN[queryVec_7_rd_bank_0_id[4:0]] + | queryVec_7_rd_bank_1_valid & _GEN[queryVec_7_rd_bank_1_id[4:0]]; + assign hazardVec_8 = + queryVec_8_rd_bank_0_valid & _GEN[queryVec_8_rd_bank_0_id[4:0]] + | queryVec_8_rd_bank_1_valid & _GEN[queryVec_8_rd_bank_1_id[4:0]]; + assign hazardVec_9 = + queryVec_9_rd_bank_0_valid & _GEN[queryVec_9_rd_bank_0_id[4:0]] + | queryVec_9_rd_bank_1_valid & _GEN[queryVec_9_rd_bank_1_id[4:0]]; + assign hazardVec_10 = + queryVec_10_rd_bank_0_valid & _GEN[queryVec_10_rd_bank_0_id[4:0]] + | queryVec_10_rd_bank_1_valid & _GEN[queryVec_10_rd_bank_1_id[4:0]]; + assign hazardVec_11 = + queryVec_11_rd_bank_0_valid & _GEN[queryVec_11_rd_bank_0_id[4:0]] + | queryVec_11_rd_bank_1_valid & _GEN[queryVec_11_rd_bank_1_id[4:0]]; + assign hazardVec_12 = + queryVec_12_rd_bank_0_valid & _GEN[queryVec_12_rd_bank_0_id[4:0]] + | queryVec_12_rd_bank_1_valid & _GEN[queryVec_12_rd_bank_1_id[4:0]]; + assign hazardVec_13 = + queryVec_13_rd_bank_0_valid & _GEN[queryVec_13_rd_bank_0_id[4:0]] + | queryVec_13_rd_bank_1_valid & _GEN[queryVec_13_rd_bank_1_id[4:0]]; + assign hazardVec_14 = + queryVec_14_rd_bank_0_valid & _GEN[queryVec_14_rd_bank_0_id[4:0]] + | queryVec_14_rd_bank_1_valid & _GEN[queryVec_14_rd_bank_1_id[4:0]]; + assign hazardVec_15 = + queryVec_15_rd_bank_0_valid & _GEN[queryVec_15_rd_bank_0_id[4:0]] + | queryVec_15_rd_bank_1_valid & _GEN[queryVec_15_rd_bank_1_id[4:0]]; +endmodule + +// external module ITraceDPI + +// VCS coverage exclude_file +module robOperands_16x128( + input [3:0] R0_addr, + input R0_en, + R0_clk, + output [127:0] R0_data, + input [3:0] W0_addr, + input W0_en, + W0_clk, + input [127:0] W0_data +); + + reg [127:0] Memory[0:15]; + reg _R0_en_d0; + reg [3:0] _R0_addr_d0; + always @(posedge R0_clk) begin + _R0_en_d0 <= R0_en; + _R0_addr_d0 <= R0_addr; + end // always @(posedge) + always @(posedge W0_clk) begin + if (W0_en & 1'h1) + Memory[W0_addr] <= W0_data; + end // always @(posedge) + assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 128'bx; +endmodule + +module GlobalROB( + input clock, + reset, + output io_alloc_ready, + input io_alloc_valid, + input [3:0] io_alloc_bits_domain_id, + input [4:0] io_alloc_bits_ball_bid, + input [31:0] io_alloc_bits_cmd_raw_inst, + input [63:0] io_alloc_bits_cmd_pc, + input [6:0] io_alloc_bits_cmd_funct, + input [2:0] io_alloc_bits_cmd_funct3, + input [4:0] io_alloc_bits_cmd_rs2, + io_alloc_bits_cmd_rs1, + input io_alloc_bits_cmd_xd, + io_alloc_bits_cmd_xs1, + io_alloc_bits_cmd_xs2, + input [4:0] io_alloc_bits_cmd_rd, + input [6:0] io_alloc_bits_cmd_opcode, + input [63:0] io_alloc_bits_cmd_rs1Data, + io_alloc_bits_cmd_rs2Data, + input io_alloc_bits_bankAccess_rd_bank_0_valid, + input [9:0] io_alloc_bits_bankAccess_rd_bank_0_id, + input io_alloc_bits_bankAccess_rd_bank_1_valid, + input [9:0] io_alloc_bits_bankAccess_rd_bank_1_id, + input io_alloc_bits_bankAccess_wr_bank_valid, + input [9:0] io_alloc_bits_bankAccess_wr_bank_id, + input io_alloc_bits_isFence, + io_alloc_bits_isBarrier, + io_issue_ready, + output io_issue_valid, + output [3:0] io_issue_bits_cmd_domain_id, + output [4:0] io_issue_bits_cmd_ball_bid, + output [31:0] io_issue_bits_cmd_cmd_raw_inst, + output [63:0] io_issue_bits_cmd_cmd_pc, + output [6:0] io_issue_bits_cmd_cmd_funct, + output [2:0] io_issue_bits_cmd_cmd_funct3, + output [4:0] io_issue_bits_cmd_cmd_rs2, + io_issue_bits_cmd_cmd_rs1, + output io_issue_bits_cmd_cmd_xd, + io_issue_bits_cmd_cmd_xs1, + io_issue_bits_cmd_cmd_xs2, + output [4:0] io_issue_bits_cmd_cmd_rd, + output [6:0] io_issue_bits_cmd_cmd_opcode, + output [63:0] io_issue_bits_cmd_cmd_rs1Data, + io_issue_bits_cmd_cmd_rs2Data, + output io_issue_bits_cmd_bankAccess_rd_bank_0_valid, + output [9:0] io_issue_bits_cmd_bankAccess_rd_bank_0_id, + output io_issue_bits_cmd_bankAccess_rd_bank_1_valid, + output [9:0] io_issue_bits_cmd_bankAccess_rd_bank_1_id, + output io_issue_bits_cmd_bankAccess_wr_bank_valid, + output [9:0] io_issue_bits_cmd_bankAccess_wr_bank_id, + output [3:0] io_issue_bits_cmd_op1_col, + io_issue_bits_cmd_op2_col, + io_issue_bits_cmd_wr_col, + output io_issue_bits_cmd_isFence, + io_issue_bits_cmd_isBarrier, + io_issue_bits_renamedBankAccess_rd_bank_0_valid, + output [9:0] io_issue_bits_renamedBankAccess_rd_bank_0_id, + output io_issue_bits_renamedBankAccess_rd_bank_1_valid, + output [9:0] io_issue_bits_renamedBankAccess_rd_bank_1_id, + output io_issue_bits_renamedBankAccess_wr_bank_valid, + output [9:0] io_issue_bits_renamedBankAccess_wr_bank_id, + output [3:0] io_issue_bits_rob_id, + input io_complete_valid, + input [3:0] io_complete_bits, + output io_empty, + io_full, + output [3:0] io_head_ptr, + output [4:0] io_issued_count, + output io_entry_valid_0, + io_entry_valid_1, + io_entry_valid_2, + io_entry_valid_3, + io_entry_valid_4, + io_entry_valid_5, + io_entry_valid_6, + io_entry_valid_7, + io_entry_valid_8, + io_entry_valid_9, + io_entry_valid_10, + io_entry_valid_11, + io_entry_valid_12, + io_entry_valid_13, + io_entry_valid_14, + io_entry_valid_15, + io_entry_complete_0, + io_entry_complete_1, + io_entry_complete_2, + io_entry_complete_3, + io_entry_complete_4, + io_entry_complete_5, + io_entry_complete_6, + io_entry_complete_7, + io_entry_complete_8, + io_entry_complete_9, + io_entry_complete_10, + io_entry_complete_11, + io_entry_complete_12, + io_entry_complete_13, + io_entry_complete_14, + io_entry_complete_15, + input io_subRobActive, + output [63:0] io_inst_ids_0, + io_inst_ids_1, + io_inst_ids_2, + io_inst_ids_3, + io_inst_ids_4, + io_inst_ids_5, + io_inst_ids_6, + io_inst_ids_7, + io_inst_ids_8, + io_inst_ids_9, + io_inst_ids_10, + io_inst_ids_11, + io_inst_ids_12, + io_inst_ids_13, + io_inst_ids_14, + io_inst_ids_15 +); + + wire commitMask_15; + wire commitMask_14; + wire commitMask_13; + wire commitMask_12; + wire commitMask_11; + wire commitMask_10; + wire commitMask_9; + wire commitMask_8; + wire commitMask_7; + wire commitMask_6; + wire commitMask_5; + wire commitMask_4; + wire commitMask_3; + wire commitMask_2; + wire commitMask_1; + wire commitMask_0; + wire [127:0] _robOperands_ext_R0_data; + wire _scoreboard_hazardVec_0; + wire _scoreboard_hazardVec_1; + wire _scoreboard_hazardVec_2; + wire _scoreboard_hazardVec_3; + wire _scoreboard_hazardVec_4; + wire _scoreboard_hazardVec_5; + wire _scoreboard_hazardVec_6; + wire _scoreboard_hazardVec_7; + wire _scoreboard_hazardVec_8; + wire _scoreboard_hazardVec_9; + wire _scoreboard_hazardVec_10; + wire _scoreboard_hazardVec_11; + wire _scoreboard_hazardVec_12; + wire _scoreboard_hazardVec_13; + wire _scoreboard_hazardVec_14; + wire _scoreboard_hazardVec_15; + wire _bat_io_alloc_renamed_rd_bank_0_valid; + wire [9:0] _bat_io_alloc_renamed_rd_bank_0_id; + wire _bat_io_alloc_renamed_rd_bank_1_valid; + wire [9:0] _bat_io_alloc_renamed_rd_bank_1_id; + wire _bat_io_alloc_renamed_wr_bank_valid; + wire [9:0] _bat_io_alloc_renamed_wr_bank_id; + reg [3:0] robEntries_0_cmd_domain_id; + reg [4:0] robEntries_0_cmd_ball_bid; + reg [31:0] robEntries_0_cmd_cmd_raw_inst; + reg [63:0] robEntries_0_cmd_cmd_pc; + reg [6:0] robEntries_0_cmd_cmd_funct; + reg [2:0] robEntries_0_cmd_cmd_funct3; + reg [4:0] robEntries_0_cmd_cmd_rs2; + reg [4:0] robEntries_0_cmd_cmd_rs1; + reg robEntries_0_cmd_cmd_xd; + reg robEntries_0_cmd_cmd_xs1; + reg robEntries_0_cmd_cmd_xs2; + reg [4:0] robEntries_0_cmd_cmd_rd; + reg [6:0] robEntries_0_cmd_cmd_opcode; + reg [63:0] robEntries_0_cmd_cmd_rs1Data; + reg [63:0] robEntries_0_cmd_cmd_rs2Data; + reg robEntries_0_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_0_cmd_bankAccess_rd_bank_0_id; + reg robEntries_0_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_0_cmd_bankAccess_rd_bank_1_id; + reg robEntries_0_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_0_cmd_bankAccess_wr_bank_id; + reg robEntries_0_cmd_isFence; + reg robEntries_0_cmd_isBarrier; + reg robEntries_0_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_0_renamedBankAccess_rd_bank_0_id; + reg robEntries_0_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_0_renamedBankAccess_rd_bank_1_id; + reg robEntries_0_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_0_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_0_rob_id; + reg [3:0] robEntries_1_cmd_domain_id; + reg [4:0] robEntries_1_cmd_ball_bid; + reg [31:0] robEntries_1_cmd_cmd_raw_inst; + reg [63:0] robEntries_1_cmd_cmd_pc; + reg [6:0] robEntries_1_cmd_cmd_funct; + reg [2:0] robEntries_1_cmd_cmd_funct3; + reg [4:0] robEntries_1_cmd_cmd_rs2; + reg [4:0] robEntries_1_cmd_cmd_rs1; + reg robEntries_1_cmd_cmd_xd; + reg robEntries_1_cmd_cmd_xs1; + reg robEntries_1_cmd_cmd_xs2; + reg [4:0] robEntries_1_cmd_cmd_rd; + reg [6:0] robEntries_1_cmd_cmd_opcode; + reg [63:0] robEntries_1_cmd_cmd_rs1Data; + reg [63:0] robEntries_1_cmd_cmd_rs2Data; + reg robEntries_1_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_1_cmd_bankAccess_rd_bank_0_id; + reg robEntries_1_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_1_cmd_bankAccess_rd_bank_1_id; + reg robEntries_1_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_1_cmd_bankAccess_wr_bank_id; + reg robEntries_1_cmd_isFence; + reg robEntries_1_cmd_isBarrier; + reg robEntries_1_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_1_renamedBankAccess_rd_bank_0_id; + reg robEntries_1_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_1_renamedBankAccess_rd_bank_1_id; + reg robEntries_1_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_1_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_1_rob_id; + reg [3:0] robEntries_2_cmd_domain_id; + reg [4:0] robEntries_2_cmd_ball_bid; + reg [31:0] robEntries_2_cmd_cmd_raw_inst; + reg [63:0] robEntries_2_cmd_cmd_pc; + reg [6:0] robEntries_2_cmd_cmd_funct; + reg [2:0] robEntries_2_cmd_cmd_funct3; + reg [4:0] robEntries_2_cmd_cmd_rs2; + reg [4:0] robEntries_2_cmd_cmd_rs1; + reg robEntries_2_cmd_cmd_xd; + reg robEntries_2_cmd_cmd_xs1; + reg robEntries_2_cmd_cmd_xs2; + reg [4:0] robEntries_2_cmd_cmd_rd; + reg [6:0] robEntries_2_cmd_cmd_opcode; + reg [63:0] robEntries_2_cmd_cmd_rs1Data; + reg [63:0] robEntries_2_cmd_cmd_rs2Data; + reg robEntries_2_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_2_cmd_bankAccess_rd_bank_0_id; + reg robEntries_2_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_2_cmd_bankAccess_rd_bank_1_id; + reg robEntries_2_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_2_cmd_bankAccess_wr_bank_id; + reg robEntries_2_cmd_isFence; + reg robEntries_2_cmd_isBarrier; + reg robEntries_2_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_2_renamedBankAccess_rd_bank_0_id; + reg robEntries_2_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_2_renamedBankAccess_rd_bank_1_id; + reg robEntries_2_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_2_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_2_rob_id; + reg [3:0] robEntries_3_cmd_domain_id; + reg [4:0] robEntries_3_cmd_ball_bid; + reg [31:0] robEntries_3_cmd_cmd_raw_inst; + reg [63:0] robEntries_3_cmd_cmd_pc; + reg [6:0] robEntries_3_cmd_cmd_funct; + reg [2:0] robEntries_3_cmd_cmd_funct3; + reg [4:0] robEntries_3_cmd_cmd_rs2; + reg [4:0] robEntries_3_cmd_cmd_rs1; + reg robEntries_3_cmd_cmd_xd; + reg robEntries_3_cmd_cmd_xs1; + reg robEntries_3_cmd_cmd_xs2; + reg [4:0] robEntries_3_cmd_cmd_rd; + reg [6:0] robEntries_3_cmd_cmd_opcode; + reg [63:0] robEntries_3_cmd_cmd_rs1Data; + reg [63:0] robEntries_3_cmd_cmd_rs2Data; + reg robEntries_3_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_3_cmd_bankAccess_rd_bank_0_id; + reg robEntries_3_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_3_cmd_bankAccess_rd_bank_1_id; + reg robEntries_3_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_3_cmd_bankAccess_wr_bank_id; + reg robEntries_3_cmd_isFence; + reg robEntries_3_cmd_isBarrier; + reg robEntries_3_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_3_renamedBankAccess_rd_bank_0_id; + reg robEntries_3_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_3_renamedBankAccess_rd_bank_1_id; + reg robEntries_3_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_3_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_3_rob_id; + reg [3:0] robEntries_4_cmd_domain_id; + reg [4:0] robEntries_4_cmd_ball_bid; + reg [31:0] robEntries_4_cmd_cmd_raw_inst; + reg [63:0] robEntries_4_cmd_cmd_pc; + reg [6:0] robEntries_4_cmd_cmd_funct; + reg [2:0] robEntries_4_cmd_cmd_funct3; + reg [4:0] robEntries_4_cmd_cmd_rs2; + reg [4:0] robEntries_4_cmd_cmd_rs1; + reg robEntries_4_cmd_cmd_xd; + reg robEntries_4_cmd_cmd_xs1; + reg robEntries_4_cmd_cmd_xs2; + reg [4:0] robEntries_4_cmd_cmd_rd; + reg [6:0] robEntries_4_cmd_cmd_opcode; + reg [63:0] robEntries_4_cmd_cmd_rs1Data; + reg [63:0] robEntries_4_cmd_cmd_rs2Data; + reg robEntries_4_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_4_cmd_bankAccess_rd_bank_0_id; + reg robEntries_4_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_4_cmd_bankAccess_rd_bank_1_id; + reg robEntries_4_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_4_cmd_bankAccess_wr_bank_id; + reg robEntries_4_cmd_isFence; + reg robEntries_4_cmd_isBarrier; + reg robEntries_4_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_4_renamedBankAccess_rd_bank_0_id; + reg robEntries_4_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_4_renamedBankAccess_rd_bank_1_id; + reg robEntries_4_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_4_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_4_rob_id; + reg [3:0] robEntries_5_cmd_domain_id; + reg [4:0] robEntries_5_cmd_ball_bid; + reg [31:0] robEntries_5_cmd_cmd_raw_inst; + reg [63:0] robEntries_5_cmd_cmd_pc; + reg [6:0] robEntries_5_cmd_cmd_funct; + reg [2:0] robEntries_5_cmd_cmd_funct3; + reg [4:0] robEntries_5_cmd_cmd_rs2; + reg [4:0] robEntries_5_cmd_cmd_rs1; + reg robEntries_5_cmd_cmd_xd; + reg robEntries_5_cmd_cmd_xs1; + reg robEntries_5_cmd_cmd_xs2; + reg [4:0] robEntries_5_cmd_cmd_rd; + reg [6:0] robEntries_5_cmd_cmd_opcode; + reg [63:0] robEntries_5_cmd_cmd_rs1Data; + reg [63:0] robEntries_5_cmd_cmd_rs2Data; + reg robEntries_5_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_5_cmd_bankAccess_rd_bank_0_id; + reg robEntries_5_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_5_cmd_bankAccess_rd_bank_1_id; + reg robEntries_5_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_5_cmd_bankAccess_wr_bank_id; + reg robEntries_5_cmd_isFence; + reg robEntries_5_cmd_isBarrier; + reg robEntries_5_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_5_renamedBankAccess_rd_bank_0_id; + reg robEntries_5_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_5_renamedBankAccess_rd_bank_1_id; + reg robEntries_5_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_5_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_5_rob_id; + reg [3:0] robEntries_6_cmd_domain_id; + reg [4:0] robEntries_6_cmd_ball_bid; + reg [31:0] robEntries_6_cmd_cmd_raw_inst; + reg [63:0] robEntries_6_cmd_cmd_pc; + reg [6:0] robEntries_6_cmd_cmd_funct; + reg [2:0] robEntries_6_cmd_cmd_funct3; + reg [4:0] robEntries_6_cmd_cmd_rs2; + reg [4:0] robEntries_6_cmd_cmd_rs1; + reg robEntries_6_cmd_cmd_xd; + reg robEntries_6_cmd_cmd_xs1; + reg robEntries_6_cmd_cmd_xs2; + reg [4:0] robEntries_6_cmd_cmd_rd; + reg [6:0] robEntries_6_cmd_cmd_opcode; + reg [63:0] robEntries_6_cmd_cmd_rs1Data; + reg [63:0] robEntries_6_cmd_cmd_rs2Data; + reg robEntries_6_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_6_cmd_bankAccess_rd_bank_0_id; + reg robEntries_6_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_6_cmd_bankAccess_rd_bank_1_id; + reg robEntries_6_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_6_cmd_bankAccess_wr_bank_id; + reg robEntries_6_cmd_isFence; + reg robEntries_6_cmd_isBarrier; + reg robEntries_6_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_6_renamedBankAccess_rd_bank_0_id; + reg robEntries_6_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_6_renamedBankAccess_rd_bank_1_id; + reg robEntries_6_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_6_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_6_rob_id; + reg [3:0] robEntries_7_cmd_domain_id; + reg [4:0] robEntries_7_cmd_ball_bid; + reg [31:0] robEntries_7_cmd_cmd_raw_inst; + reg [63:0] robEntries_7_cmd_cmd_pc; + reg [6:0] robEntries_7_cmd_cmd_funct; + reg [2:0] robEntries_7_cmd_cmd_funct3; + reg [4:0] robEntries_7_cmd_cmd_rs2; + reg [4:0] robEntries_7_cmd_cmd_rs1; + reg robEntries_7_cmd_cmd_xd; + reg robEntries_7_cmd_cmd_xs1; + reg robEntries_7_cmd_cmd_xs2; + reg [4:0] robEntries_7_cmd_cmd_rd; + reg [6:0] robEntries_7_cmd_cmd_opcode; + reg [63:0] robEntries_7_cmd_cmd_rs1Data; + reg [63:0] robEntries_7_cmd_cmd_rs2Data; + reg robEntries_7_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_7_cmd_bankAccess_rd_bank_0_id; + reg robEntries_7_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_7_cmd_bankAccess_rd_bank_1_id; + reg robEntries_7_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_7_cmd_bankAccess_wr_bank_id; + reg robEntries_7_cmd_isFence; + reg robEntries_7_cmd_isBarrier; + reg robEntries_7_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_7_renamedBankAccess_rd_bank_0_id; + reg robEntries_7_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_7_renamedBankAccess_rd_bank_1_id; + reg robEntries_7_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_7_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_7_rob_id; + reg [3:0] robEntries_8_cmd_domain_id; + reg [4:0] robEntries_8_cmd_ball_bid; + reg [31:0] robEntries_8_cmd_cmd_raw_inst; + reg [63:0] robEntries_8_cmd_cmd_pc; + reg [6:0] robEntries_8_cmd_cmd_funct; + reg [2:0] robEntries_8_cmd_cmd_funct3; + reg [4:0] robEntries_8_cmd_cmd_rs2; + reg [4:0] robEntries_8_cmd_cmd_rs1; + reg robEntries_8_cmd_cmd_xd; + reg robEntries_8_cmd_cmd_xs1; + reg robEntries_8_cmd_cmd_xs2; + reg [4:0] robEntries_8_cmd_cmd_rd; + reg [6:0] robEntries_8_cmd_cmd_opcode; + reg [63:0] robEntries_8_cmd_cmd_rs1Data; + reg [63:0] robEntries_8_cmd_cmd_rs2Data; + reg robEntries_8_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_8_cmd_bankAccess_rd_bank_0_id; + reg robEntries_8_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_8_cmd_bankAccess_rd_bank_1_id; + reg robEntries_8_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_8_cmd_bankAccess_wr_bank_id; + reg robEntries_8_cmd_isFence; + reg robEntries_8_cmd_isBarrier; + reg robEntries_8_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_8_renamedBankAccess_rd_bank_0_id; + reg robEntries_8_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_8_renamedBankAccess_rd_bank_1_id; + reg robEntries_8_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_8_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_8_rob_id; + reg [3:0] robEntries_9_cmd_domain_id; + reg [4:0] robEntries_9_cmd_ball_bid; + reg [31:0] robEntries_9_cmd_cmd_raw_inst; + reg [63:0] robEntries_9_cmd_cmd_pc; + reg [6:0] robEntries_9_cmd_cmd_funct; + reg [2:0] robEntries_9_cmd_cmd_funct3; + reg [4:0] robEntries_9_cmd_cmd_rs2; + reg [4:0] robEntries_9_cmd_cmd_rs1; + reg robEntries_9_cmd_cmd_xd; + reg robEntries_9_cmd_cmd_xs1; + reg robEntries_9_cmd_cmd_xs2; + reg [4:0] robEntries_9_cmd_cmd_rd; + reg [6:0] robEntries_9_cmd_cmd_opcode; + reg [63:0] robEntries_9_cmd_cmd_rs1Data; + reg [63:0] robEntries_9_cmd_cmd_rs2Data; + reg robEntries_9_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_9_cmd_bankAccess_rd_bank_0_id; + reg robEntries_9_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_9_cmd_bankAccess_rd_bank_1_id; + reg robEntries_9_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_9_cmd_bankAccess_wr_bank_id; + reg robEntries_9_cmd_isFence; + reg robEntries_9_cmd_isBarrier; + reg robEntries_9_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_9_renamedBankAccess_rd_bank_0_id; + reg robEntries_9_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_9_renamedBankAccess_rd_bank_1_id; + reg robEntries_9_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_9_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_9_rob_id; + reg [3:0] robEntries_10_cmd_domain_id; + reg [4:0] robEntries_10_cmd_ball_bid; + reg [31:0] robEntries_10_cmd_cmd_raw_inst; + reg [63:0] robEntries_10_cmd_cmd_pc; + reg [6:0] robEntries_10_cmd_cmd_funct; + reg [2:0] robEntries_10_cmd_cmd_funct3; + reg [4:0] robEntries_10_cmd_cmd_rs2; + reg [4:0] robEntries_10_cmd_cmd_rs1; + reg robEntries_10_cmd_cmd_xd; + reg robEntries_10_cmd_cmd_xs1; + reg robEntries_10_cmd_cmd_xs2; + reg [4:0] robEntries_10_cmd_cmd_rd; + reg [6:0] robEntries_10_cmd_cmd_opcode; + reg [63:0] robEntries_10_cmd_cmd_rs1Data; + reg [63:0] robEntries_10_cmd_cmd_rs2Data; + reg robEntries_10_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_10_cmd_bankAccess_rd_bank_0_id; + reg robEntries_10_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_10_cmd_bankAccess_rd_bank_1_id; + reg robEntries_10_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_10_cmd_bankAccess_wr_bank_id; + reg robEntries_10_cmd_isFence; + reg robEntries_10_cmd_isBarrier; + reg robEntries_10_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_10_renamedBankAccess_rd_bank_0_id; + reg robEntries_10_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_10_renamedBankAccess_rd_bank_1_id; + reg robEntries_10_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_10_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_10_rob_id; + reg [3:0] robEntries_11_cmd_domain_id; + reg [4:0] robEntries_11_cmd_ball_bid; + reg [31:0] robEntries_11_cmd_cmd_raw_inst; + reg [63:0] robEntries_11_cmd_cmd_pc; + reg [6:0] robEntries_11_cmd_cmd_funct; + reg [2:0] robEntries_11_cmd_cmd_funct3; + reg [4:0] robEntries_11_cmd_cmd_rs2; + reg [4:0] robEntries_11_cmd_cmd_rs1; + reg robEntries_11_cmd_cmd_xd; + reg robEntries_11_cmd_cmd_xs1; + reg robEntries_11_cmd_cmd_xs2; + reg [4:0] robEntries_11_cmd_cmd_rd; + reg [6:0] robEntries_11_cmd_cmd_opcode; + reg [63:0] robEntries_11_cmd_cmd_rs1Data; + reg [63:0] robEntries_11_cmd_cmd_rs2Data; + reg robEntries_11_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_11_cmd_bankAccess_rd_bank_0_id; + reg robEntries_11_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_11_cmd_bankAccess_rd_bank_1_id; + reg robEntries_11_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_11_cmd_bankAccess_wr_bank_id; + reg robEntries_11_cmd_isFence; + reg robEntries_11_cmd_isBarrier; + reg robEntries_11_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_11_renamedBankAccess_rd_bank_0_id; + reg robEntries_11_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_11_renamedBankAccess_rd_bank_1_id; + reg robEntries_11_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_11_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_11_rob_id; + reg [3:0] robEntries_12_cmd_domain_id; + reg [4:0] robEntries_12_cmd_ball_bid; + reg [31:0] robEntries_12_cmd_cmd_raw_inst; + reg [63:0] robEntries_12_cmd_cmd_pc; + reg [6:0] robEntries_12_cmd_cmd_funct; + reg [2:0] robEntries_12_cmd_cmd_funct3; + reg [4:0] robEntries_12_cmd_cmd_rs2; + reg [4:0] robEntries_12_cmd_cmd_rs1; + reg robEntries_12_cmd_cmd_xd; + reg robEntries_12_cmd_cmd_xs1; + reg robEntries_12_cmd_cmd_xs2; + reg [4:0] robEntries_12_cmd_cmd_rd; + reg [6:0] robEntries_12_cmd_cmd_opcode; + reg [63:0] robEntries_12_cmd_cmd_rs1Data; + reg [63:0] robEntries_12_cmd_cmd_rs2Data; + reg robEntries_12_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_12_cmd_bankAccess_rd_bank_0_id; + reg robEntries_12_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_12_cmd_bankAccess_rd_bank_1_id; + reg robEntries_12_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_12_cmd_bankAccess_wr_bank_id; + reg robEntries_12_cmd_isFence; + reg robEntries_12_cmd_isBarrier; + reg robEntries_12_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_12_renamedBankAccess_rd_bank_0_id; + reg robEntries_12_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_12_renamedBankAccess_rd_bank_1_id; + reg robEntries_12_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_12_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_12_rob_id; + reg [3:0] robEntries_13_cmd_domain_id; + reg [4:0] robEntries_13_cmd_ball_bid; + reg [31:0] robEntries_13_cmd_cmd_raw_inst; + reg [63:0] robEntries_13_cmd_cmd_pc; + reg [6:0] robEntries_13_cmd_cmd_funct; + reg [2:0] robEntries_13_cmd_cmd_funct3; + reg [4:0] robEntries_13_cmd_cmd_rs2; + reg [4:0] robEntries_13_cmd_cmd_rs1; + reg robEntries_13_cmd_cmd_xd; + reg robEntries_13_cmd_cmd_xs1; + reg robEntries_13_cmd_cmd_xs2; + reg [4:0] robEntries_13_cmd_cmd_rd; + reg [6:0] robEntries_13_cmd_cmd_opcode; + reg [63:0] robEntries_13_cmd_cmd_rs1Data; + reg [63:0] robEntries_13_cmd_cmd_rs2Data; + reg robEntries_13_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_13_cmd_bankAccess_rd_bank_0_id; + reg robEntries_13_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_13_cmd_bankAccess_rd_bank_1_id; + reg robEntries_13_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_13_cmd_bankAccess_wr_bank_id; + reg robEntries_13_cmd_isFence; + reg robEntries_13_cmd_isBarrier; + reg robEntries_13_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_13_renamedBankAccess_rd_bank_0_id; + reg robEntries_13_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_13_renamedBankAccess_rd_bank_1_id; + reg robEntries_13_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_13_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_13_rob_id; + reg [3:0] robEntries_14_cmd_domain_id; + reg [4:0] robEntries_14_cmd_ball_bid; + reg [31:0] robEntries_14_cmd_cmd_raw_inst; + reg [63:0] robEntries_14_cmd_cmd_pc; + reg [6:0] robEntries_14_cmd_cmd_funct; + reg [2:0] robEntries_14_cmd_cmd_funct3; + reg [4:0] robEntries_14_cmd_cmd_rs2; + reg [4:0] robEntries_14_cmd_cmd_rs1; + reg robEntries_14_cmd_cmd_xd; + reg robEntries_14_cmd_cmd_xs1; + reg robEntries_14_cmd_cmd_xs2; + reg [4:0] robEntries_14_cmd_cmd_rd; + reg [6:0] robEntries_14_cmd_cmd_opcode; + reg [63:0] robEntries_14_cmd_cmd_rs1Data; + reg [63:0] robEntries_14_cmd_cmd_rs2Data; + reg robEntries_14_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_14_cmd_bankAccess_rd_bank_0_id; + reg robEntries_14_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_14_cmd_bankAccess_rd_bank_1_id; + reg robEntries_14_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_14_cmd_bankAccess_wr_bank_id; + reg robEntries_14_cmd_isFence; + reg robEntries_14_cmd_isBarrier; + reg robEntries_14_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_14_renamedBankAccess_rd_bank_0_id; + reg robEntries_14_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_14_renamedBankAccess_rd_bank_1_id; + reg robEntries_14_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_14_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_14_rob_id; + reg [3:0] robEntries_15_cmd_domain_id; + reg [4:0] robEntries_15_cmd_ball_bid; + reg [31:0] robEntries_15_cmd_cmd_raw_inst; + reg [63:0] robEntries_15_cmd_cmd_pc; + reg [6:0] robEntries_15_cmd_cmd_funct; + reg [2:0] robEntries_15_cmd_cmd_funct3; + reg [4:0] robEntries_15_cmd_cmd_rs2; + reg [4:0] robEntries_15_cmd_cmd_rs1; + reg robEntries_15_cmd_cmd_xd; + reg robEntries_15_cmd_cmd_xs1; + reg robEntries_15_cmd_cmd_xs2; + reg [4:0] robEntries_15_cmd_cmd_rd; + reg [6:0] robEntries_15_cmd_cmd_opcode; + reg [63:0] robEntries_15_cmd_cmd_rs1Data; + reg [63:0] robEntries_15_cmd_cmd_rs2Data; + reg robEntries_15_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_15_cmd_bankAccess_rd_bank_0_id; + reg robEntries_15_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_15_cmd_bankAccess_rd_bank_1_id; + reg robEntries_15_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_15_cmd_bankAccess_wr_bank_id; + reg robEntries_15_cmd_isFence; + reg robEntries_15_cmd_isBarrier; + reg robEntries_15_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_15_renamedBankAccess_rd_bank_0_id; + reg robEntries_15_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_15_renamedBankAccess_rd_bank_1_id; + reg robEntries_15_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_15_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_15_rob_id; + reg robValid_0; + reg robValid_1; + reg robValid_2; + reg robValid_3; + reg robValid_4; + reg robValid_5; + reg robValid_6; + reg robValid_7; + reg robValid_8; + reg robValid_9; + reg robValid_10; + reg robValid_11; + reg robValid_12; + reg robValid_13; + reg robValid_14; + reg robValid_15; + reg robIssued_0; + reg robIssued_1; + reg robIssued_2; + reg robIssued_3; + reg robIssued_4; + reg robIssued_5; + reg robIssued_6; + reg robIssued_7; + reg robIssued_8; + reg robIssued_9; + reg robIssued_10; + reg robIssued_11; + reg robIssued_12; + reg robIssued_13; + reg robIssued_14; + reg robIssued_15; + reg robComplete_0; + reg robComplete_1; + reg robComplete_2; + reg robComplete_3; + reg robComplete_4; + reg robComplete_5; + reg robComplete_6; + reg robComplete_7; + reg robComplete_8; + reg robComplete_9; + reg robComplete_10; + reg robComplete_11; + reg robComplete_12; + reg robComplete_13; + reg robComplete_14; + reg robComplete_15; + reg [63:0] instIds_0; + reg [63:0] instIds_1; + reg [63:0] instIds_2; + reg [63:0] instIds_3; + reg [63:0] instIds_4; + reg [63:0] instIds_5; + reg [63:0] instIds_6; + reg [63:0] instIds_7; + reg [63:0] instIds_8; + reg [63:0] instIds_9; + reg [63:0] instIds_10; + reg [63:0] instIds_11; + reg [63:0] instIds_12; + reg [63:0] instIds_13; + reg [63:0] instIds_14; + reg [63:0] instIds_15; + reg [63:0] nextInstId; + reg [3:0] ptr; + reg [3:0] tailPtr; + reg [4:0] issuedCount; + reg [3:0] bankCols_0; + reg [3:0] bankCols_1; + reg [3:0] bankCols_2; + reg [3:0] bankCols_3; + reg [3:0] bankCols_4; + reg [3:0] bankCols_5; + reg [3:0] bankCols_6; + reg [3:0] bankCols_7; + reg [3:0] bankCols_8; + reg [3:0] bankCols_9; + reg [3:0] bankCols_10; + reg [3:0] bankCols_11; + reg [3:0] bankCols_12; + reg [3:0] bankCols_13; + reg [3:0] bankCols_14; + reg [3:0] bankCols_15; + reg [15:0] vbankBusy; + reg [15:0] dependencyMask_0; + reg [15:0] dependencyMask_1; + reg [15:0] dependencyMask_2; + reg [15:0] dependencyMask_3; + reg [15:0] dependencyMask_4; + reg [15:0] dependencyMask_5; + reg [15:0] dependencyMask_6; + reg [15:0] dependencyMask_7; + reg [15:0] dependencyMask_8; + reg [15:0] dependencyMask_9; + reg [15:0] dependencyMask_10; + reg [15:0] dependencyMask_11; + reg [15:0] dependencyMask_12; + reg [15:0] dependencyMask_13; + reg [15:0] dependencyMask_14; + reg [15:0] dependencyMask_15; + wire _isFull_T = ptr == tailPtr; + wire [15:0] _GEN = + {{robValid_15}, + {robValid_14}, + {robValid_13}, + {robValid_12}, + {robValid_11}, + {robValid_10}, + {robValid_9}, + {robValid_8}, + {robValid_7}, + {robValid_6}, + {robValid_5}, + {robValid_4}, + {robValid_3}, + {robValid_2}, + {robValid_1}, + {robValid_0}}; + wire _GEN_0 = _GEN[ptr]; + wire isFull = _isFull_T & _GEN_0; + wire [15:0] _GEN_1 = + {{robComplete_15}, + {robComplete_14}, + {robComplete_13}, + {robComplete_12}, + {robComplete_11}, + {robComplete_10}, + {robComplete_9}, + {robComplete_8}, + {robComplete_7}, + {robComplete_6}, + {robComplete_5}, + {robComplete_4}, + {robComplete_3}, + {robComplete_2}, + {robComplete_1}, + {robComplete_0}}; + wire _GEN_2 = _GEN_1[ptr]; + wire commitKeep_1 = _GEN_0 & _GEN_2; + wire [3:0] _hits_ptr_T_1446 = ptr + 4'h1; + wire commitKeep_2 = + commitKeep_1 & _GEN[_hits_ptr_T_1446] & _GEN_1[_hits_ptr_T_1446]; + wire [3:0] _hits_ptr_T_1452 = ptr + 4'h2; + wire commitKeep_3 = + commitKeep_2 & _GEN[_hits_ptr_T_1452] & _GEN_1[_hits_ptr_T_1452]; + wire [3:0] _hits_ptr_T_1458 = ptr + 4'h3; + wire commitKeep_4 = + commitKeep_3 & _GEN[_hits_ptr_T_1458] & _GEN_1[_hits_ptr_T_1458]; + wire [3:0] _hits_ptr_T_1464 = ptr + 4'h4; + wire commitKeep_5 = + commitKeep_4 & _GEN[_hits_ptr_T_1464] & _GEN_1[_hits_ptr_T_1464]; + wire [3:0] _hits_ptr_T_1470 = ptr + 4'h5; + wire commitKeep_6 = + commitKeep_5 & _GEN[_hits_ptr_T_1470] & _GEN_1[_hits_ptr_T_1470]; + wire [3:0] _hits_ptr_T_1476 = ptr + 4'h6; + wire commitKeep_7 = + commitKeep_6 & _GEN[_hits_ptr_T_1476] & _GEN_1[_hits_ptr_T_1476]; + wire [3:0] _hits_ptr_T_1482 = ptr + 4'h7; + wire commitKeep_8 = + commitKeep_7 & _GEN[_hits_ptr_T_1482] & _GEN_1[_hits_ptr_T_1482]; + wire [3:0] _hits_ptr_T_1488 = ptr - 4'h8; + wire commitKeep_9 = + commitKeep_8 & _GEN[_hits_ptr_T_1488] & _GEN_1[_hits_ptr_T_1488]; + wire [3:0] _hits_ptr_T_1494 = ptr - 4'h7; + wire commitScan_9 = + commitKeep_9 & _GEN[_hits_ptr_T_1494] & _GEN_1[_hits_ptr_T_1494]; + wire [3:0] _hits_ptr_T_1500 = ptr - 4'h6; + wire commitKeep_11 = + commitScan_9 & _GEN[_hits_ptr_T_1500] & _GEN_1[_hits_ptr_T_1500]; + wire [3:0] _hits_ptr_T_1506 = ptr - 4'h5; + wire commitKeep_12 = + commitKeep_11 & _GEN[_hits_ptr_T_1506] & _GEN_1[_hits_ptr_T_1506]; + wire [3:0] _hits_ptr_T_1512 = ptr - 4'h4; + wire commitKeep_13 = + commitKeep_12 & _GEN[_hits_ptr_T_1512] & _GEN_1[_hits_ptr_T_1512]; + wire [3:0] _hits_ptr_T_1518 = ptr - 4'h3; + wire commitKeep_14 = + commitKeep_13 & _GEN[_hits_ptr_T_1518] & _GEN_1[_hits_ptr_T_1518]; + wire [3:0] _hits_ptr_T_1524 = ptr - 4'h2; + wire commitKeep_15 = + commitKeep_14 & _GEN[_hits_ptr_T_1524] & _GEN_1[_hits_ptr_T_1524]; + wire [3:0] _hits_ptr_T_1530 = ptr - 4'h1; + wire commitScan_15 = + commitKeep_15 & _GEN[_hits_ptr_T_1530] & _GEN_1[_hits_ptr_T_1530]; + wire [9:0] _tailAlias_T = {6'h0, tailPtr} + 10'h10; + wire io_alloc_ready_0 = + ~isFull + & {commitScan_15, + commitKeep_15, + commitKeep_14, + commitKeep_13, + commitKeep_12, + commitKeep_11, + commitScan_9, + commitKeep_9, + commitKeep_8, + commitKeep_7, + commitKeep_6, + commitKeep_5, + commitKeep_4, + commitKeep_3, + commitKeep_2, + commitKeep_1} == 16'h0 + & ~(robValid_15 & ~robComplete_15 + & (robEntries_15_renamedBankAccess_rd_bank_0_valid + & robEntries_15_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_15_renamedBankAccess_rd_bank_1_valid + & robEntries_15_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_15_renamedBankAccess_wr_bank_valid + & robEntries_15_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_14 + & ~robComplete_14 + & (robEntries_14_renamedBankAccess_rd_bank_0_valid + & robEntries_14_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_14_renamedBankAccess_rd_bank_1_valid + & robEntries_14_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_14_renamedBankAccess_wr_bank_valid + & robEntries_14_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_13 + & ~robComplete_13 + & (robEntries_13_renamedBankAccess_rd_bank_0_valid + & robEntries_13_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_13_renamedBankAccess_rd_bank_1_valid + & robEntries_13_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_13_renamedBankAccess_wr_bank_valid + & robEntries_13_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_12 + & ~robComplete_12 + & (robEntries_12_renamedBankAccess_rd_bank_0_valid + & robEntries_12_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_12_renamedBankAccess_rd_bank_1_valid + & robEntries_12_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_12_renamedBankAccess_wr_bank_valid + & robEntries_12_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_11 + & ~robComplete_11 + & (robEntries_11_renamedBankAccess_rd_bank_0_valid + & robEntries_11_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_11_renamedBankAccess_rd_bank_1_valid + & robEntries_11_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_11_renamedBankAccess_wr_bank_valid + & robEntries_11_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_10 + & ~robComplete_10 + & (robEntries_10_renamedBankAccess_rd_bank_0_valid + & robEntries_10_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_10_renamedBankAccess_rd_bank_1_valid + & robEntries_10_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_10_renamedBankAccess_wr_bank_valid + & robEntries_10_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_9 + & ~robComplete_9 + & (robEntries_9_renamedBankAccess_rd_bank_0_valid + & robEntries_9_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_9_renamedBankAccess_rd_bank_1_valid + & robEntries_9_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_9_renamedBankAccess_wr_bank_valid + & robEntries_9_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_8 + & ~robComplete_8 + & (robEntries_8_renamedBankAccess_rd_bank_0_valid + & robEntries_8_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_8_renamedBankAccess_rd_bank_1_valid + & robEntries_8_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_8_renamedBankAccess_wr_bank_valid + & robEntries_8_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_7 + & ~robComplete_7 + & (robEntries_7_renamedBankAccess_rd_bank_0_valid + & robEntries_7_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_7_renamedBankAccess_rd_bank_1_valid + & robEntries_7_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_7_renamedBankAccess_wr_bank_valid + & robEntries_7_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_6 + & ~robComplete_6 + & (robEntries_6_renamedBankAccess_rd_bank_0_valid + & robEntries_6_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_6_renamedBankAccess_rd_bank_1_valid + & robEntries_6_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_6_renamedBankAccess_wr_bank_valid + & robEntries_6_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_5 + & ~robComplete_5 + & (robEntries_5_renamedBankAccess_rd_bank_0_valid + & robEntries_5_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_5_renamedBankAccess_rd_bank_1_valid + & robEntries_5_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_5_renamedBankAccess_wr_bank_valid + & robEntries_5_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_4 + & ~robComplete_4 + & (robEntries_4_renamedBankAccess_rd_bank_0_valid + & robEntries_4_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_4_renamedBankAccess_rd_bank_1_valid + & robEntries_4_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_4_renamedBankAccess_wr_bank_valid + & robEntries_4_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_3 + & ~robComplete_3 + & (robEntries_3_renamedBankAccess_rd_bank_0_valid + & robEntries_3_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_3_renamedBankAccess_rd_bank_1_valid + & robEntries_3_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_3_renamedBankAccess_wr_bank_valid + & robEntries_3_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_2 + & ~robComplete_2 + & (robEntries_2_renamedBankAccess_rd_bank_0_valid + & robEntries_2_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_2_renamedBankAccess_rd_bank_1_valid + & robEntries_2_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_2_renamedBankAccess_wr_bank_valid + & robEntries_2_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_1 + & ~robComplete_1 + & (robEntries_1_renamedBankAccess_rd_bank_0_valid + & robEntries_1_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_1_renamedBankAccess_rd_bank_1_valid + & robEntries_1_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_1_renamedBankAccess_wr_bank_valid + & robEntries_1_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_0 + & ~robComplete_0 + & (robEntries_0_renamedBankAccess_rd_bank_0_valid + & robEntries_0_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_0_renamedBankAccess_rd_bank_1_valid + & robEntries_0_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_0_renamedBankAccess_wr_bank_valid + & robEntries_0_renamedBankAccess_wr_bank_id == _tailAlias_T)); + wire _isAllocatedSlot_T_30 = io_alloc_ready_0 & io_alloc_valid; + wire [15:0] entryRawWrites_0 = + robEntries_0_cmd_bankAccess_wr_bank_valid + & robEntries_0_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_0_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_1 = + robEntries_1_cmd_bankAccess_wr_bank_valid + & robEntries_1_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_1_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_2 = + robEntries_2_cmd_bankAccess_wr_bank_valid + & robEntries_2_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_2_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_3 = + robEntries_3_cmd_bankAccess_wr_bank_valid + & robEntries_3_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_3_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_4 = + robEntries_4_cmd_bankAccess_wr_bank_valid + & robEntries_4_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_4_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_5 = + robEntries_5_cmd_bankAccess_wr_bank_valid + & robEntries_5_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_5_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_6 = + robEntries_6_cmd_bankAccess_wr_bank_valid + & robEntries_6_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_6_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_7 = + robEntries_7_cmd_bankAccess_wr_bank_valid + & robEntries_7_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_7_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_8 = + robEntries_8_cmd_bankAccess_wr_bank_valid + & robEntries_8_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_8_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_9 = + robEntries_9_cmd_bankAccess_wr_bank_valid + & robEntries_9_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_9_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_10 = + robEntries_10_cmd_bankAccess_wr_bank_valid + & robEntries_10_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_10_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_11 = + robEntries_11_cmd_bankAccess_wr_bank_valid + & robEntries_11_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_11_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_12 = + robEntries_12_cmd_bankAccess_wr_bank_valid + & robEntries_12_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_12_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_13 = + robEntries_13_cmd_bankAccess_wr_bank_valid + & robEntries_13_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_13_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_14 = + robEntries_14_cmd_bankAccess_wr_bank_valid + & robEntries_14_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_14_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_15 = + robEntries_15_cmd_bankAccess_wr_bank_valid + & robEntries_15_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_15_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] olderUseMask = + (robEntries_0_cmd_bankAccess_rd_bank_0_valid + & robEntries_0_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_0_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_0_cmd_bankAccess_rd_bank_1_valid + & robEntries_0_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_0_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_0; + wire [15:0] vbankMasks_1 = + (robEntries_1_cmd_bankAccess_rd_bank_0_valid + & robEntries_1_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_1_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_1_cmd_bankAccess_rd_bank_1_valid + & robEntries_1_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_1_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_1; + wire [15:0] vbankMasks_2 = + (robEntries_2_cmd_bankAccess_rd_bank_0_valid + & robEntries_2_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_2_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_2_cmd_bankAccess_rd_bank_1_valid + & robEntries_2_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_2_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_2; + wire [15:0] vbankMasks_3 = + (robEntries_3_cmd_bankAccess_rd_bank_0_valid + & robEntries_3_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_3_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_3_cmd_bankAccess_rd_bank_1_valid + & robEntries_3_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_3_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_3; + wire [15:0] vbankMasks_4 = + (robEntries_4_cmd_bankAccess_rd_bank_0_valid + & robEntries_4_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_4_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_4_cmd_bankAccess_rd_bank_1_valid + & robEntries_4_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_4_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_4; + wire [15:0] vbankMasks_5 = + (robEntries_5_cmd_bankAccess_rd_bank_0_valid + & robEntries_5_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_5_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_5_cmd_bankAccess_rd_bank_1_valid + & robEntries_5_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_5_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_5; + wire [15:0] vbankMasks_6 = + (robEntries_6_cmd_bankAccess_rd_bank_0_valid + & robEntries_6_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_6_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_6_cmd_bankAccess_rd_bank_1_valid + & robEntries_6_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_6_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_6; + wire [15:0] vbankMasks_7 = + (robEntries_7_cmd_bankAccess_rd_bank_0_valid + & robEntries_7_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_7_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_7_cmd_bankAccess_rd_bank_1_valid + & robEntries_7_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_7_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_7; + wire [15:0] vbankMasks_8 = + (robEntries_8_cmd_bankAccess_rd_bank_0_valid + & robEntries_8_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_8_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_8_cmd_bankAccess_rd_bank_1_valid + & robEntries_8_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_8_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_8; + wire [15:0] vbankMasks_9 = + (robEntries_9_cmd_bankAccess_rd_bank_0_valid + & robEntries_9_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_9_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_9_cmd_bankAccess_rd_bank_1_valid + & robEntries_9_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_9_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_9; + wire [15:0] vbankMasks_10 = + (robEntries_10_cmd_bankAccess_rd_bank_0_valid + & robEntries_10_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_10_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_10_cmd_bankAccess_rd_bank_1_valid + & robEntries_10_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_10_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_10; + wire [15:0] vbankMasks_11 = + (robEntries_11_cmd_bankAccess_rd_bank_0_valid + & robEntries_11_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_11_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_11_cmd_bankAccess_rd_bank_1_valid + & robEntries_11_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_11_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_11; + wire [15:0] vbankMasks_12 = + (robEntries_12_cmd_bankAccess_rd_bank_0_valid + & robEntries_12_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_12_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_12_cmd_bankAccess_rd_bank_1_valid + & robEntries_12_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_12_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_12; + wire [15:0] vbankMasks_13 = + (robEntries_13_cmd_bankAccess_rd_bank_0_valid + & robEntries_13_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_13_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_13_cmd_bankAccess_rd_bank_1_valid + & robEntries_13_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_13_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_13; + wire [15:0] vbankMasks_14 = + (robEntries_14_cmd_bankAccess_rd_bank_0_valid + & robEntries_14_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_14_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_14_cmd_bankAccess_rd_bank_1_valid + & robEntries_14_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_14_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_14; + wire [15:0] vbankMasks_15 = + (robEntries_15_cmd_bankAccess_rd_bank_0_valid + & robEntries_15_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_15_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_15_cmd_bankAccess_rd_bank_1_valid + & robEntries_15_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_15_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_15; + wire _GEN_3 = _isAllocatedSlot_T_30 & (|io_alloc_bits_cmd_pc); + wire [15:0] _GEN_4 = + {{robIssued_15}, + {robIssued_14}, + {robIssued_13}, + {robIssued_12}, + {robIssued_11}, + {robIssued_10}, + {robIssued_9}, + {robIssued_8}, + {robIssued_7}, + {robIssued_6}, + {robIssued_5}, + {robIssued_4}, + {robIssued_3}, + {robIssued_2}, + {robIssued_1}, + {robIssued_0}}; + wire [15:0][3:0] _GEN_5 = + {{robEntries_15_cmd_domain_id}, + {robEntries_14_cmd_domain_id}, + {robEntries_13_cmd_domain_id}, + {robEntries_12_cmd_domain_id}, + {robEntries_11_cmd_domain_id}, + {robEntries_10_cmd_domain_id}, + {robEntries_9_cmd_domain_id}, + {robEntries_8_cmd_domain_id}, + {robEntries_7_cmd_domain_id}, + {robEntries_6_cmd_domain_id}, + {robEntries_5_cmd_domain_id}, + {robEntries_4_cmd_domain_id}, + {robEntries_3_cmd_domain_id}, + {robEntries_2_cmd_domain_id}, + {robEntries_1_cmd_domain_id}, + {robEntries_0_cmd_domain_id}}; + wire [15:0][63:0] _GEN_6 = + {{robEntries_15_cmd_cmd_pc}, + {robEntries_14_cmd_cmd_pc}, + {robEntries_13_cmd_cmd_pc}, + {robEntries_12_cmd_cmd_pc}, + {robEntries_11_cmd_cmd_pc}, + {robEntries_10_cmd_cmd_pc}, + {robEntries_9_cmd_cmd_pc}, + {robEntries_8_cmd_cmd_pc}, + {robEntries_7_cmd_cmd_pc}, + {robEntries_6_cmd_cmd_pc}, + {robEntries_5_cmd_cmd_pc}, + {robEntries_4_cmd_cmd_pc}, + {robEntries_3_cmd_cmd_pc}, + {robEntries_2_cmd_cmd_pc}, + {robEntries_1_cmd_cmd_pc}, + {robEntries_0_cmd_cmd_pc}}; + wire [15:0][6:0] _GEN_7 = + {{robEntries_15_cmd_cmd_funct}, + {robEntries_14_cmd_cmd_funct}, + {robEntries_13_cmd_cmd_funct}, + {robEntries_12_cmd_cmd_funct}, + {robEntries_11_cmd_cmd_funct}, + {robEntries_10_cmd_cmd_funct}, + {robEntries_9_cmd_cmd_funct}, + {robEntries_8_cmd_cmd_funct}, + {robEntries_7_cmd_cmd_funct}, + {robEntries_6_cmd_cmd_funct}, + {robEntries_5_cmd_cmd_funct}, + {robEntries_4_cmd_cmd_funct}, + {robEntries_3_cmd_cmd_funct}, + {robEntries_2_cmd_cmd_funct}, + {robEntries_1_cmd_cmd_funct}, + {robEntries_0_cmd_cmd_funct}}; + wire [15:0][63:0] _GEN_8 = + {{robEntries_15_cmd_cmd_rs1Data}, + {robEntries_14_cmd_cmd_rs1Data}, + {robEntries_13_cmd_cmd_rs1Data}, + {robEntries_12_cmd_cmd_rs1Data}, + {robEntries_11_cmd_cmd_rs1Data}, + {robEntries_10_cmd_cmd_rs1Data}, + {robEntries_9_cmd_cmd_rs1Data}, + {robEntries_8_cmd_cmd_rs1Data}, + {robEntries_7_cmd_cmd_rs1Data}, + {robEntries_6_cmd_cmd_rs1Data}, + {robEntries_5_cmd_cmd_rs1Data}, + {robEntries_4_cmd_cmd_rs1Data}, + {robEntries_3_cmd_cmd_rs1Data}, + {robEntries_2_cmd_cmd_rs1Data}, + {robEntries_1_cmd_cmd_rs1Data}, + {robEntries_0_cmd_cmd_rs1Data}}; + wire [15:0][63:0] _GEN_9 = + {{robEntries_15_cmd_cmd_rs2Data}, + {robEntries_14_cmd_cmd_rs2Data}, + {robEntries_13_cmd_cmd_rs2Data}, + {robEntries_12_cmd_cmd_rs2Data}, + {robEntries_11_cmd_cmd_rs2Data}, + {robEntries_10_cmd_cmd_rs2Data}, + {robEntries_9_cmd_cmd_rs2Data}, + {robEntries_8_cmd_cmd_rs2Data}, + {robEntries_7_cmd_cmd_rs2Data}, + {robEntries_6_cmd_cmd_rs2Data}, + {robEntries_5_cmd_cmd_rs2Data}, + {robEntries_4_cmd_cmd_rs2Data}, + {robEntries_3_cmd_cmd_rs2Data}, + {robEntries_2_cmd_cmd_rs2Data}, + {robEntries_1_cmd_cmd_rs2Data}, + {robEntries_0_cmd_cmd_rs2Data}}; + wire [15:0] _GEN_10 = + {{robEntries_15_renamedBankAccess_wr_bank_valid}, + {robEntries_14_renamedBankAccess_wr_bank_valid}, + {robEntries_13_renamedBankAccess_wr_bank_valid}, + {robEntries_12_renamedBankAccess_wr_bank_valid}, + {robEntries_11_renamedBankAccess_wr_bank_valid}, + {robEntries_10_renamedBankAccess_wr_bank_valid}, + {robEntries_9_renamedBankAccess_wr_bank_valid}, + {robEntries_8_renamedBankAccess_wr_bank_valid}, + {robEntries_7_renamedBankAccess_wr_bank_valid}, + {robEntries_6_renamedBankAccess_wr_bank_valid}, + {robEntries_5_renamedBankAccess_wr_bank_valid}, + {robEntries_4_renamedBankAccess_wr_bank_valid}, + {robEntries_3_renamedBankAccess_wr_bank_valid}, + {robEntries_2_renamedBankAccess_wr_bank_valid}, + {robEntries_1_renamedBankAccess_wr_bank_valid}, + {robEntries_0_renamedBankAccess_wr_bank_valid}}; + wire [15:0][9:0] _GEN_11 = + {{robEntries_15_renamedBankAccess_wr_bank_id}, + {robEntries_14_renamedBankAccess_wr_bank_id}, + {robEntries_13_renamedBankAccess_wr_bank_id}, + {robEntries_12_renamedBankAccess_wr_bank_id}, + {robEntries_11_renamedBankAccess_wr_bank_id}, + {robEntries_10_renamedBankAccess_wr_bank_id}, + {robEntries_9_renamedBankAccess_wr_bank_id}, + {robEntries_8_renamedBankAccess_wr_bank_id}, + {robEntries_7_renamedBankAccess_wr_bank_id}, + {robEntries_6_renamedBankAccess_wr_bank_id}, + {robEntries_5_renamedBankAccess_wr_bank_id}, + {robEntries_4_renamedBankAccess_wr_bank_id}, + {robEntries_3_renamedBankAccess_wr_bank_id}, + {robEntries_2_renamedBankAccess_wr_bank_id}, + {robEntries_1_renamedBankAccess_wr_bank_id}, + {robEntries_0_renamedBankAccess_wr_bank_id}}; + wire [15:0][63:0] _GEN_12 = + {{instIds_15}, + {instIds_14}, + {instIds_13}, + {instIds_12}, + {instIds_11}, + {instIds_10}, + {instIds_9}, + {instIds_8}, + {instIds_7}, + {instIds_6}, + {instIds_5}, + {instIds_4}, + {instIds_3}, + {instIds_2}, + {instIds_1}, + {instIds_0}}; + wire [15:0] _GEN_13 = + {{robEntries_15_renamedBankAccess_rd_bank_0_valid}, + {robEntries_14_renamedBankAccess_rd_bank_0_valid}, + {robEntries_13_renamedBankAccess_rd_bank_0_valid}, + {robEntries_12_renamedBankAccess_rd_bank_0_valid}, + {robEntries_11_renamedBankAccess_rd_bank_0_valid}, + {robEntries_10_renamedBankAccess_rd_bank_0_valid}, + {robEntries_9_renamedBankAccess_rd_bank_0_valid}, + {robEntries_8_renamedBankAccess_rd_bank_0_valid}, + {robEntries_7_renamedBankAccess_rd_bank_0_valid}, + {robEntries_6_renamedBankAccess_rd_bank_0_valid}, + {robEntries_5_renamedBankAccess_rd_bank_0_valid}, + {robEntries_4_renamedBankAccess_rd_bank_0_valid}, + {robEntries_3_renamedBankAccess_rd_bank_0_valid}, + {robEntries_2_renamedBankAccess_rd_bank_0_valid}, + {robEntries_1_renamedBankAccess_rd_bank_0_valid}, + {robEntries_0_renamedBankAccess_rd_bank_0_valid}}; + wire [15:0][9:0] _GEN_14 = + {{robEntries_15_renamedBankAccess_rd_bank_0_id}, + {robEntries_14_renamedBankAccess_rd_bank_0_id}, + {robEntries_13_renamedBankAccess_rd_bank_0_id}, + {robEntries_12_renamedBankAccess_rd_bank_0_id}, + {robEntries_11_renamedBankAccess_rd_bank_0_id}, + {robEntries_10_renamedBankAccess_rd_bank_0_id}, + {robEntries_9_renamedBankAccess_rd_bank_0_id}, + {robEntries_8_renamedBankAccess_rd_bank_0_id}, + {robEntries_7_renamedBankAccess_rd_bank_0_id}, + {robEntries_6_renamedBankAccess_rd_bank_0_id}, + {robEntries_5_renamedBankAccess_rd_bank_0_id}, + {robEntries_4_renamedBankAccess_rd_bank_0_id}, + {robEntries_3_renamedBankAccess_rd_bank_0_id}, + {robEntries_2_renamedBankAccess_rd_bank_0_id}, + {robEntries_1_renamedBankAccess_rd_bank_0_id}, + {robEntries_0_renamedBankAccess_rd_bank_0_id}}; + wire [15:0] _GEN_15 = + {{robEntries_15_renamedBankAccess_rd_bank_1_valid}, + {robEntries_14_renamedBankAccess_rd_bank_1_valid}, + {robEntries_13_renamedBankAccess_rd_bank_1_valid}, + {robEntries_12_renamedBankAccess_rd_bank_1_valid}, + {robEntries_11_renamedBankAccess_rd_bank_1_valid}, + {robEntries_10_renamedBankAccess_rd_bank_1_valid}, + {robEntries_9_renamedBankAccess_rd_bank_1_valid}, + {robEntries_8_renamedBankAccess_rd_bank_1_valid}, + {robEntries_7_renamedBankAccess_rd_bank_1_valid}, + {robEntries_6_renamedBankAccess_rd_bank_1_valid}, + {robEntries_5_renamedBankAccess_rd_bank_1_valid}, + {robEntries_4_renamedBankAccess_rd_bank_1_valid}, + {robEntries_3_renamedBankAccess_rd_bank_1_valid}, + {robEntries_2_renamedBankAccess_rd_bank_1_valid}, + {robEntries_1_renamedBankAccess_rd_bank_1_valid}, + {robEntries_0_renamedBankAccess_rd_bank_1_valid}}; + wire [15:0][9:0] _GEN_16 = + {{robEntries_15_renamedBankAccess_rd_bank_1_id}, + {robEntries_14_renamedBankAccess_rd_bank_1_id}, + {robEntries_13_renamedBankAccess_rd_bank_1_id}, + {robEntries_12_renamedBankAccess_rd_bank_1_id}, + {robEntries_11_renamedBankAccess_rd_bank_1_id}, + {robEntries_10_renamedBankAccess_rd_bank_1_id}, + {robEntries_9_renamedBankAccess_rd_bank_1_id}, + {robEntries_8_renamedBankAccess_rd_bank_1_id}, + {robEntries_7_renamedBankAccess_rd_bank_1_id}, + {robEntries_6_renamedBankAccess_rd_bank_1_id}, + {robEntries_5_renamedBankAccess_rd_bank_1_id}, + {robEntries_4_renamedBankAccess_rd_bank_1_id}, + {robEntries_3_renamedBankAccess_rd_bank_1_id}, + {robEntries_2_renamedBankAccess_rd_bank_1_id}, + {robEntries_1_renamedBankAccess_rd_bank_1_id}, + {robEntries_0_renamedBankAccess_rd_bank_1_id}}; + wire [15:0][15:0] _GEN_17 = + {{dependencyMask_15}, + {dependencyMask_14}, + {dependencyMask_13}, + {dependencyMask_12}, + {dependencyMask_11}, + {dependencyMask_10}, + {dependencyMask_9}, + {dependencyMask_8}, + {dependencyMask_7}, + {dependencyMask_6}, + {dependencyMask_5}, + {dependencyMask_4}, + {dependencyMask_3}, + {dependencyMask_2}, + {dependencyMask_1}, + {dependencyMask_0}}; + wire [15:0][15:0] _GEN_18 = + {{vbankMasks_15}, + {vbankMasks_14}, + {vbankMasks_13}, + {vbankMasks_12}, + {vbankMasks_11}, + {vbankMasks_10}, + {vbankMasks_9}, + {vbankMasks_8}, + {vbankMasks_7}, + {vbankMasks_6}, + {vbankMasks_5}, + {vbankMasks_4}, + {vbankMasks_3}, + {vbankMasks_2}, + {vbankMasks_1}, + {olderUseMask}}; + wire scanReady_0 = + _GEN_0 & ~_GEN_4[ptr] & ~_GEN_2 & ~_scoreboard_hazardVec_0 & _GEN_17[ptr] == 16'h0 + & (_GEN_18[ptr] & vbankBusy) == 16'h0; + wire scanReady_1 = + _GEN[_hits_ptr_T_1446] & ~_GEN_4[_hits_ptr_T_1446] & ~_GEN_1[_hits_ptr_T_1446] + & ~_scoreboard_hazardVec_1 & _GEN_17[_hits_ptr_T_1446] == 16'h0 + & (_GEN_18[_hits_ptr_T_1446] & vbankBusy) == 16'h0; + wire scanReady_2 = + _GEN[_hits_ptr_T_1452] & ~_GEN_4[_hits_ptr_T_1452] & ~_GEN_1[_hits_ptr_T_1452] + & ~_scoreboard_hazardVec_2 & _GEN_17[_hits_ptr_T_1452] == 16'h0 + & (_GEN_18[_hits_ptr_T_1452] & vbankBusy) == 16'h0; + wire scanReady_3 = + _GEN[_hits_ptr_T_1458] & ~_GEN_4[_hits_ptr_T_1458] & ~_GEN_1[_hits_ptr_T_1458] + & ~_scoreboard_hazardVec_3 & _GEN_17[_hits_ptr_T_1458] == 16'h0 + & (_GEN_18[_hits_ptr_T_1458] & vbankBusy) == 16'h0; + wire scanReady_4 = + _GEN[_hits_ptr_T_1464] & ~_GEN_4[_hits_ptr_T_1464] & ~_GEN_1[_hits_ptr_T_1464] + & ~_scoreboard_hazardVec_4 & _GEN_17[_hits_ptr_T_1464] == 16'h0 + & (_GEN_18[_hits_ptr_T_1464] & vbankBusy) == 16'h0; + wire scanReady_5 = + _GEN[_hits_ptr_T_1470] & ~_GEN_4[_hits_ptr_T_1470] & ~_GEN_1[_hits_ptr_T_1470] + & ~_scoreboard_hazardVec_5 & _GEN_17[_hits_ptr_T_1470] == 16'h0 + & (_GEN_18[_hits_ptr_T_1470] & vbankBusy) == 16'h0; + wire scanReady_6 = + _GEN[_hits_ptr_T_1476] & ~_GEN_4[_hits_ptr_T_1476] & ~_GEN_1[_hits_ptr_T_1476] + & ~_scoreboard_hazardVec_6 & _GEN_17[_hits_ptr_T_1476] == 16'h0 + & (_GEN_18[_hits_ptr_T_1476] & vbankBusy) == 16'h0; + wire scanReady_7 = + _GEN[_hits_ptr_T_1482] & ~_GEN_4[_hits_ptr_T_1482] & ~_GEN_1[_hits_ptr_T_1482] + & ~_scoreboard_hazardVec_7 & _GEN_17[_hits_ptr_T_1482] == 16'h0 + & (_GEN_18[_hits_ptr_T_1482] & vbankBusy) == 16'h0; + wire scanReady_8 = + _GEN[_hits_ptr_T_1488] & ~_GEN_4[_hits_ptr_T_1488] & ~_GEN_1[_hits_ptr_T_1488] + & ~_scoreboard_hazardVec_8 & _GEN_17[_hits_ptr_T_1488] == 16'h0 + & (_GEN_18[_hits_ptr_T_1488] & vbankBusy) == 16'h0; + wire scanReady_9 = + _GEN[_hits_ptr_T_1494] & ~_GEN_4[_hits_ptr_T_1494] & ~_GEN_1[_hits_ptr_T_1494] + & ~_scoreboard_hazardVec_9 & _GEN_17[_hits_ptr_T_1494] == 16'h0 + & (_GEN_18[_hits_ptr_T_1494] & vbankBusy) == 16'h0; + wire scanReady_10 = + _GEN[_hits_ptr_T_1500] & ~_GEN_4[_hits_ptr_T_1500] & ~_GEN_1[_hits_ptr_T_1500] + & ~_scoreboard_hazardVec_10 & _GEN_17[_hits_ptr_T_1500] == 16'h0 + & (_GEN_18[_hits_ptr_T_1500] & vbankBusy) == 16'h0; + wire scanReady_11 = + _GEN[_hits_ptr_T_1506] & ~_GEN_4[_hits_ptr_T_1506] & ~_GEN_1[_hits_ptr_T_1506] + & ~_scoreboard_hazardVec_11 & _GEN_17[_hits_ptr_T_1506] == 16'h0 + & (_GEN_18[_hits_ptr_T_1506] & vbankBusy) == 16'h0; + wire scanReady_12 = + _GEN[_hits_ptr_T_1512] & ~_GEN_4[_hits_ptr_T_1512] & ~_GEN_1[_hits_ptr_T_1512] + & ~_scoreboard_hazardVec_12 & _GEN_17[_hits_ptr_T_1512] == 16'h0 + & (_GEN_18[_hits_ptr_T_1512] & vbankBusy) == 16'h0; + wire scanReady_13 = + _GEN[_hits_ptr_T_1518] & ~_GEN_4[_hits_ptr_T_1518] & ~_GEN_1[_hits_ptr_T_1518] + & ~_scoreboard_hazardVec_13 & _GEN_17[_hits_ptr_T_1518] == 16'h0 + & (_GEN_18[_hits_ptr_T_1518] & vbankBusy) == 16'h0; + wire scanReady_14 = + _GEN[_hits_ptr_T_1524] & ~_GEN_4[_hits_ptr_T_1524] & ~_GEN_1[_hits_ptr_T_1524] + & ~_scoreboard_hazardVec_14 & _GEN_17[_hits_ptr_T_1524] == 16'h0 + & (_GEN_18[_hits_ptr_T_1524] & vbankBusy) == 16'h0; + wire [3:0] _actualIssuePtr_T = + ptr + + (scanReady_0 + ? 4'h0 + : scanReady_1 + ? 4'h1 + : scanReady_2 + ? 4'h2 + : scanReady_3 + ? 4'h3 + : scanReady_4 + ? 4'h4 + : scanReady_5 + ? 4'h5 + : scanReady_6 + ? 4'h6 + : scanReady_7 + ? 4'h7 + : scanReady_8 + ? 4'h8 + : scanReady_9 + ? 4'h9 + : scanReady_10 + ? 4'hA + : scanReady_11 + ? 4'hB + : scanReady_12 + ? 4'hC + : scanReady_13 + ? 4'hD + : {3'h7, ~scanReady_14}); + wire [15:0][3:0] _GEN_19 = + {{robEntries_15_rob_id}, + {robEntries_14_rob_id}, + {robEntries_13_rob_id}, + {robEntries_12_rob_id}, + {robEntries_11_rob_id}, + {robEntries_10_rob_id}, + {robEntries_9_rob_id}, + {robEntries_8_rob_id}, + {robEntries_7_rob_id}, + {robEntries_6_rob_id}, + {robEntries_5_rob_id}, + {robEntries_4_rob_id}, + {robEntries_3_rob_id}, + {robEntries_2_rob_id}, + {robEntries_1_rob_id}, + {robEntries_0_rob_id}}; + reg issueStageValid; + reg [3:0] issueStageEntry_cmd_domain_id; + reg [4:0] issueStageEntry_cmd_ball_bid; + reg [31:0] issueStageEntry_cmd_cmd_raw_inst; + reg [63:0] issueStageEntry_cmd_cmd_pc; + reg [6:0] issueStageEntry_cmd_cmd_funct; + reg [2:0] issueStageEntry_cmd_cmd_funct3; + reg [4:0] issueStageEntry_cmd_cmd_rs2; + reg [4:0] issueStageEntry_cmd_cmd_rs1; + reg issueStageEntry_cmd_cmd_xd; + reg issueStageEntry_cmd_cmd_xs1; + reg issueStageEntry_cmd_cmd_xs2; + reg [4:0] issueStageEntry_cmd_cmd_rd; + reg [6:0] issueStageEntry_cmd_cmd_opcode; + reg [63:0] issueStageEntry_cmd_cmd_rs1Data; + reg [63:0] issueStageEntry_cmd_cmd_rs2Data; + reg issueStageEntry_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] issueStageEntry_cmd_bankAccess_rd_bank_0_id; + reg issueStageEntry_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] issueStageEntry_cmd_bankAccess_rd_bank_1_id; + reg issueStageEntry_cmd_bankAccess_wr_bank_valid; + reg [9:0] issueStageEntry_cmd_bankAccess_wr_bank_id; + reg [3:0] issueStageEntry_cmd_op1_col; + reg [3:0] issueStageEntry_cmd_op2_col; + reg [3:0] issueStageEntry_cmd_wr_col; + reg issueStageEntry_cmd_isFence; + reg issueStageEntry_cmd_isBarrier; + reg issueStageEntry_renamedBankAccess_rd_bank_0_valid; + reg [9:0] issueStageEntry_renamedBankAccess_rd_bank_0_id; + reg issueStageEntry_renamedBankAccess_rd_bank_1_valid; + reg [9:0] issueStageEntry_renamedBankAccess_rd_bank_1_id; + reg issueStageEntry_renamedBankAccess_wr_bank_valid; + reg [9:0] issueStageEntry_renamedBankAccess_wr_bank_id; + reg [3:0] issueStageEntry_rob_id; + wire issueStageReady = + ~issueStageValid | issueStageValid & ~io_subRobActive & io_issue_ready; + reg issuePtrValid; + reg [3:0] issuePtr; + wire issuePtrFire = issuePtrValid & issueStageReady; + wire issuePtrReady = ~issuePtrValid | issuePtrFire; + wire issueLoad = + (|{_GEN[_hits_ptr_T_1530] & ~_GEN_4[_hits_ptr_T_1530] & ~_GEN_1[_hits_ptr_T_1530] + & ~_scoreboard_hazardVec_15 & _GEN_17[_hits_ptr_T_1530] == 16'h0 + & (_GEN_18[_hits_ptr_T_1530] & vbankBusy) == 16'h0, + scanReady_14, + scanReady_13, + scanReady_12, + scanReady_11, + scanReady_10, + scanReady_9, + scanReady_8, + scanReady_7, + scanReady_6, + scanReady_5, + scanReady_4, + scanReady_3, + scanReady_2, + scanReady_1, + scanReady_0}) & ~io_subRobActive & issuePtrReady; + wire [3:0] readAddress = issueLoad ? _actualIssuePtr_T : issuePtr; + wire readEnable = issueLoad | issuePtrValid; + `ifndef SYNTHESIS + always @(posedge clock) begin + if (_isAllocatedSlot_T_30 & readEnable & ~reset & tailPtr == readAddress) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: ROB operand RAM read/write collision\n at GlobalROB.scala:444 assert(tailPtr =/= readAddress, \"ROB operand RAM read/write collision\")\n"); + if (`STOP_COND_) + $fatal; + end + end // always @(posedge) + `endif // not def SYNTHESIS + assign commitMask_0 = + commitKeep_1 & ptr == 4'h0 | commitKeep_2 & _hits_ptr_T_1446 == 4'h0 | commitKeep_3 + & _hits_ptr_T_1452 == 4'h0 | commitKeep_4 & _hits_ptr_T_1458 == 4'h0 | commitKeep_5 + & _hits_ptr_T_1464 == 4'h0 | commitKeep_6 & _hits_ptr_T_1470 == 4'h0 | commitKeep_7 + & _hits_ptr_T_1476 == 4'h0 | commitKeep_8 & _hits_ptr_T_1482 == 4'h0 | commitKeep_9 + & _hits_ptr_T_1488 == 4'h0 | commitScan_9 & _hits_ptr_T_1494 == 4'h0 | commitKeep_11 + & _hits_ptr_T_1500 == 4'h0 | commitKeep_12 & _hits_ptr_T_1506 == 4'h0 | commitKeep_13 + & _hits_ptr_T_1512 == 4'h0 | commitKeep_14 & _hits_ptr_T_1518 == 4'h0 | commitKeep_15 + & _hits_ptr_T_1524 == 4'h0 | commitScan_15 & _hits_ptr_T_1530 == 4'h0; + assign commitMask_1 = + commitKeep_1 & ptr == 4'h1 | commitKeep_2 & _hits_ptr_T_1446 == 4'h1 | commitKeep_3 + & _hits_ptr_T_1452 == 4'h1 | commitKeep_4 & _hits_ptr_T_1458 == 4'h1 | commitKeep_5 + & _hits_ptr_T_1464 == 4'h1 | commitKeep_6 & _hits_ptr_T_1470 == 4'h1 | commitKeep_7 + & _hits_ptr_T_1476 == 4'h1 | commitKeep_8 & _hits_ptr_T_1482 == 4'h1 | commitKeep_9 + & _hits_ptr_T_1488 == 4'h1 | commitScan_9 & _hits_ptr_T_1494 == 4'h1 | commitKeep_11 + & _hits_ptr_T_1500 == 4'h1 | commitKeep_12 & _hits_ptr_T_1506 == 4'h1 | commitKeep_13 + & _hits_ptr_T_1512 == 4'h1 | commitKeep_14 & _hits_ptr_T_1518 == 4'h1 | commitKeep_15 + & _hits_ptr_T_1524 == 4'h1 | commitScan_15 & _hits_ptr_T_1530 == 4'h1; + assign commitMask_2 = + commitKeep_1 & ptr == 4'h2 | commitKeep_2 & _hits_ptr_T_1446 == 4'h2 | commitKeep_3 + & _hits_ptr_T_1452 == 4'h2 | commitKeep_4 & _hits_ptr_T_1458 == 4'h2 | commitKeep_5 + & _hits_ptr_T_1464 == 4'h2 | commitKeep_6 & _hits_ptr_T_1470 == 4'h2 | commitKeep_7 + & _hits_ptr_T_1476 == 4'h2 | commitKeep_8 & _hits_ptr_T_1482 == 4'h2 | commitKeep_9 + & _hits_ptr_T_1488 == 4'h2 | commitScan_9 & _hits_ptr_T_1494 == 4'h2 | commitKeep_11 + & _hits_ptr_T_1500 == 4'h2 | commitKeep_12 & _hits_ptr_T_1506 == 4'h2 | commitKeep_13 + & _hits_ptr_T_1512 == 4'h2 | commitKeep_14 & _hits_ptr_T_1518 == 4'h2 | commitKeep_15 + & _hits_ptr_T_1524 == 4'h2 | commitScan_15 & _hits_ptr_T_1530 == 4'h2; + assign commitMask_3 = + commitKeep_1 & ptr == 4'h3 | commitKeep_2 & _hits_ptr_T_1446 == 4'h3 | commitKeep_3 + & _hits_ptr_T_1452 == 4'h3 | commitKeep_4 & _hits_ptr_T_1458 == 4'h3 | commitKeep_5 + & _hits_ptr_T_1464 == 4'h3 | commitKeep_6 & _hits_ptr_T_1470 == 4'h3 | commitKeep_7 + & _hits_ptr_T_1476 == 4'h3 | commitKeep_8 & _hits_ptr_T_1482 == 4'h3 | commitKeep_9 + & _hits_ptr_T_1488 == 4'h3 | commitScan_9 & _hits_ptr_T_1494 == 4'h3 | commitKeep_11 + & _hits_ptr_T_1500 == 4'h3 | commitKeep_12 & _hits_ptr_T_1506 == 4'h3 | commitKeep_13 + & _hits_ptr_T_1512 == 4'h3 | commitKeep_14 & _hits_ptr_T_1518 == 4'h3 | commitKeep_15 + & _hits_ptr_T_1524 == 4'h3 | commitScan_15 & _hits_ptr_T_1530 == 4'h3; + assign commitMask_4 = + commitKeep_1 & ptr == 4'h4 | commitKeep_2 & _hits_ptr_T_1446 == 4'h4 | commitKeep_3 + & _hits_ptr_T_1452 == 4'h4 | commitKeep_4 & _hits_ptr_T_1458 == 4'h4 | commitKeep_5 + & _hits_ptr_T_1464 == 4'h4 | commitKeep_6 & _hits_ptr_T_1470 == 4'h4 | commitKeep_7 + & _hits_ptr_T_1476 == 4'h4 | commitKeep_8 & _hits_ptr_T_1482 == 4'h4 | commitKeep_9 + & _hits_ptr_T_1488 == 4'h4 | commitScan_9 & _hits_ptr_T_1494 == 4'h4 | commitKeep_11 + & _hits_ptr_T_1500 == 4'h4 | commitKeep_12 & _hits_ptr_T_1506 == 4'h4 | commitKeep_13 + & _hits_ptr_T_1512 == 4'h4 | commitKeep_14 & _hits_ptr_T_1518 == 4'h4 | commitKeep_15 + & _hits_ptr_T_1524 == 4'h4 | commitScan_15 & _hits_ptr_T_1530 == 4'h4; + assign commitMask_5 = + commitKeep_1 & ptr == 4'h5 | commitKeep_2 & _hits_ptr_T_1446 == 4'h5 | commitKeep_3 + & _hits_ptr_T_1452 == 4'h5 | commitKeep_4 & _hits_ptr_T_1458 == 4'h5 | commitKeep_5 + & _hits_ptr_T_1464 == 4'h5 | commitKeep_6 & _hits_ptr_T_1470 == 4'h5 | commitKeep_7 + & _hits_ptr_T_1476 == 4'h5 | commitKeep_8 & _hits_ptr_T_1482 == 4'h5 | commitKeep_9 + & _hits_ptr_T_1488 == 4'h5 | commitScan_9 & _hits_ptr_T_1494 == 4'h5 | commitKeep_11 + & _hits_ptr_T_1500 == 4'h5 | commitKeep_12 & _hits_ptr_T_1506 == 4'h5 | commitKeep_13 + & _hits_ptr_T_1512 == 4'h5 | commitKeep_14 & _hits_ptr_T_1518 == 4'h5 | commitKeep_15 + & _hits_ptr_T_1524 == 4'h5 | commitScan_15 & _hits_ptr_T_1530 == 4'h5; + assign commitMask_6 = + commitKeep_1 & ptr == 4'h6 | commitKeep_2 & _hits_ptr_T_1446 == 4'h6 | commitKeep_3 + & _hits_ptr_T_1452 == 4'h6 | commitKeep_4 & _hits_ptr_T_1458 == 4'h6 | commitKeep_5 + & _hits_ptr_T_1464 == 4'h6 | commitKeep_6 & _hits_ptr_T_1470 == 4'h6 | commitKeep_7 + & _hits_ptr_T_1476 == 4'h6 | commitKeep_8 & _hits_ptr_T_1482 == 4'h6 | commitKeep_9 + & _hits_ptr_T_1488 == 4'h6 | commitScan_9 & _hits_ptr_T_1494 == 4'h6 | commitKeep_11 + & _hits_ptr_T_1500 == 4'h6 | commitKeep_12 & _hits_ptr_T_1506 == 4'h6 | commitKeep_13 + & _hits_ptr_T_1512 == 4'h6 | commitKeep_14 & _hits_ptr_T_1518 == 4'h6 | commitKeep_15 + & _hits_ptr_T_1524 == 4'h6 | commitScan_15 & _hits_ptr_T_1530 == 4'h6; + assign commitMask_7 = + commitKeep_1 & ptr == 4'h7 | commitKeep_2 & _hits_ptr_T_1446 == 4'h7 | commitKeep_3 + & _hits_ptr_T_1452 == 4'h7 | commitKeep_4 & _hits_ptr_T_1458 == 4'h7 | commitKeep_5 + & _hits_ptr_T_1464 == 4'h7 | commitKeep_6 & _hits_ptr_T_1470 == 4'h7 | commitKeep_7 + & _hits_ptr_T_1476 == 4'h7 | commitKeep_8 & _hits_ptr_T_1482 == 4'h7 | commitKeep_9 + & _hits_ptr_T_1488 == 4'h7 | commitScan_9 & _hits_ptr_T_1494 == 4'h7 | commitKeep_11 + & _hits_ptr_T_1500 == 4'h7 | commitKeep_12 & _hits_ptr_T_1506 == 4'h7 | commitKeep_13 + & _hits_ptr_T_1512 == 4'h7 | commitKeep_14 & _hits_ptr_T_1518 == 4'h7 | commitKeep_15 + & _hits_ptr_T_1524 == 4'h7 | commitScan_15 & _hits_ptr_T_1530 == 4'h7; + assign commitMask_8 = + commitKeep_1 & ptr == 4'h8 | commitKeep_2 & _hits_ptr_T_1446 == 4'h8 | commitKeep_3 + & _hits_ptr_T_1452 == 4'h8 | commitKeep_4 & _hits_ptr_T_1458 == 4'h8 | commitKeep_5 + & _hits_ptr_T_1464 == 4'h8 | commitKeep_6 & _hits_ptr_T_1470 == 4'h8 | commitKeep_7 + & _hits_ptr_T_1476 == 4'h8 | commitKeep_8 & _hits_ptr_T_1482 == 4'h8 | commitKeep_9 + & _hits_ptr_T_1488 == 4'h8 | commitScan_9 & _hits_ptr_T_1494 == 4'h8 | commitKeep_11 + & _hits_ptr_T_1500 == 4'h8 | commitKeep_12 & _hits_ptr_T_1506 == 4'h8 | commitKeep_13 + & _hits_ptr_T_1512 == 4'h8 | commitKeep_14 & _hits_ptr_T_1518 == 4'h8 | commitKeep_15 + & _hits_ptr_T_1524 == 4'h8 | commitScan_15 & _hits_ptr_T_1530 == 4'h8; + assign commitMask_9 = + commitKeep_1 & ptr == 4'h9 | commitKeep_2 & _hits_ptr_T_1446 == 4'h9 | commitKeep_3 + & _hits_ptr_T_1452 == 4'h9 | commitKeep_4 & _hits_ptr_T_1458 == 4'h9 | commitKeep_5 + & _hits_ptr_T_1464 == 4'h9 | commitKeep_6 & _hits_ptr_T_1470 == 4'h9 | commitKeep_7 + & _hits_ptr_T_1476 == 4'h9 | commitKeep_8 & _hits_ptr_T_1482 == 4'h9 | commitKeep_9 + & _hits_ptr_T_1488 == 4'h9 | commitScan_9 & _hits_ptr_T_1494 == 4'h9 | commitKeep_11 + & _hits_ptr_T_1500 == 4'h9 | commitKeep_12 & _hits_ptr_T_1506 == 4'h9 | commitKeep_13 + & _hits_ptr_T_1512 == 4'h9 | commitKeep_14 & _hits_ptr_T_1518 == 4'h9 | commitKeep_15 + & _hits_ptr_T_1524 == 4'h9 | commitScan_15 & _hits_ptr_T_1530 == 4'h9; + assign commitMask_10 = + commitKeep_1 & ptr == 4'hA | commitKeep_2 & _hits_ptr_T_1446 == 4'hA | commitKeep_3 + & _hits_ptr_T_1452 == 4'hA | commitKeep_4 & _hits_ptr_T_1458 == 4'hA | commitKeep_5 + & _hits_ptr_T_1464 == 4'hA | commitKeep_6 & _hits_ptr_T_1470 == 4'hA | commitKeep_7 + & _hits_ptr_T_1476 == 4'hA | commitKeep_8 & _hits_ptr_T_1482 == 4'hA | commitKeep_9 + & _hits_ptr_T_1488 == 4'hA | commitScan_9 & _hits_ptr_T_1494 == 4'hA | commitKeep_11 + & _hits_ptr_T_1500 == 4'hA | commitKeep_12 & _hits_ptr_T_1506 == 4'hA | commitKeep_13 + & _hits_ptr_T_1512 == 4'hA | commitKeep_14 & _hits_ptr_T_1518 == 4'hA | commitKeep_15 + & _hits_ptr_T_1524 == 4'hA | commitScan_15 & _hits_ptr_T_1530 == 4'hA; + assign commitMask_11 = + commitKeep_1 & ptr == 4'hB | commitKeep_2 & _hits_ptr_T_1446 == 4'hB | commitKeep_3 + & _hits_ptr_T_1452 == 4'hB | commitKeep_4 & _hits_ptr_T_1458 == 4'hB | commitKeep_5 + & _hits_ptr_T_1464 == 4'hB | commitKeep_6 & _hits_ptr_T_1470 == 4'hB | commitKeep_7 + & _hits_ptr_T_1476 == 4'hB | commitKeep_8 & _hits_ptr_T_1482 == 4'hB | commitKeep_9 + & _hits_ptr_T_1488 == 4'hB | commitScan_9 & _hits_ptr_T_1494 == 4'hB | commitKeep_11 + & _hits_ptr_T_1500 == 4'hB | commitKeep_12 & _hits_ptr_T_1506 == 4'hB | commitKeep_13 + & _hits_ptr_T_1512 == 4'hB | commitKeep_14 & _hits_ptr_T_1518 == 4'hB | commitKeep_15 + & _hits_ptr_T_1524 == 4'hB | commitScan_15 & _hits_ptr_T_1530 == 4'hB; + assign commitMask_12 = + commitKeep_1 & ptr == 4'hC | commitKeep_2 & _hits_ptr_T_1446 == 4'hC | commitKeep_3 + & _hits_ptr_T_1452 == 4'hC | commitKeep_4 & _hits_ptr_T_1458 == 4'hC | commitKeep_5 + & _hits_ptr_T_1464 == 4'hC | commitKeep_6 & _hits_ptr_T_1470 == 4'hC | commitKeep_7 + & _hits_ptr_T_1476 == 4'hC | commitKeep_8 & _hits_ptr_T_1482 == 4'hC | commitKeep_9 + & _hits_ptr_T_1488 == 4'hC | commitScan_9 & _hits_ptr_T_1494 == 4'hC | commitKeep_11 + & _hits_ptr_T_1500 == 4'hC | commitKeep_12 & _hits_ptr_T_1506 == 4'hC | commitKeep_13 + & _hits_ptr_T_1512 == 4'hC | commitKeep_14 & _hits_ptr_T_1518 == 4'hC | commitKeep_15 + & _hits_ptr_T_1524 == 4'hC | commitScan_15 & _hits_ptr_T_1530 == 4'hC; + assign commitMask_13 = + commitKeep_1 & ptr == 4'hD | commitKeep_2 & _hits_ptr_T_1446 == 4'hD | commitKeep_3 + & _hits_ptr_T_1452 == 4'hD | commitKeep_4 & _hits_ptr_T_1458 == 4'hD | commitKeep_5 + & _hits_ptr_T_1464 == 4'hD | commitKeep_6 & _hits_ptr_T_1470 == 4'hD | commitKeep_7 + & _hits_ptr_T_1476 == 4'hD | commitKeep_8 & _hits_ptr_T_1482 == 4'hD | commitKeep_9 + & _hits_ptr_T_1488 == 4'hD | commitScan_9 & _hits_ptr_T_1494 == 4'hD | commitKeep_11 + & _hits_ptr_T_1500 == 4'hD | commitKeep_12 & _hits_ptr_T_1506 == 4'hD | commitKeep_13 + & _hits_ptr_T_1512 == 4'hD | commitKeep_14 & _hits_ptr_T_1518 == 4'hD | commitKeep_15 + & _hits_ptr_T_1524 == 4'hD | commitScan_15 & _hits_ptr_T_1530 == 4'hD; + assign commitMask_14 = + commitKeep_1 & ptr == 4'hE | commitKeep_2 & _hits_ptr_T_1446 == 4'hE | commitKeep_3 + & _hits_ptr_T_1452 == 4'hE | commitKeep_4 & _hits_ptr_T_1458 == 4'hE | commitKeep_5 + & _hits_ptr_T_1464 == 4'hE | commitKeep_6 & _hits_ptr_T_1470 == 4'hE | commitKeep_7 + & _hits_ptr_T_1476 == 4'hE | commitKeep_8 & _hits_ptr_T_1482 == 4'hE | commitKeep_9 + & _hits_ptr_T_1488 == 4'hE | commitScan_9 & _hits_ptr_T_1494 == 4'hE | commitKeep_11 + & _hits_ptr_T_1500 == 4'hE | commitKeep_12 & _hits_ptr_T_1506 == 4'hE | commitKeep_13 + & _hits_ptr_T_1512 == 4'hE | commitKeep_14 & _hits_ptr_T_1518 == 4'hE | commitKeep_15 + & _hits_ptr_T_1524 == 4'hE | commitScan_15 & _hits_ptr_T_1530 == 4'hE; + assign commitMask_15 = + commitKeep_1 & (&ptr) | commitKeep_2 & (&_hits_ptr_T_1446) | commitKeep_3 + & (&_hits_ptr_T_1452) | commitKeep_4 & (&_hits_ptr_T_1458) | commitKeep_5 + & (&_hits_ptr_T_1464) | commitKeep_6 & (&_hits_ptr_T_1470) | commitKeep_7 + & (&_hits_ptr_T_1476) | commitKeep_8 & (&_hits_ptr_T_1482) | commitKeep_9 + & (&_hits_ptr_T_1488) | commitScan_9 & (&_hits_ptr_T_1494) | commitKeep_11 + & (&_hits_ptr_T_1500) | commitKeep_12 & (&_hits_ptr_T_1506) | commitKeep_13 + & (&_hits_ptr_T_1512) | commitKeep_14 & (&_hits_ptr_T_1518) | commitKeep_15 + & (&_hits_ptr_T_1524) | commitScan_15 & (&_hits_ptr_T_1530); + always @(posedge clock) begin + if (reset) begin + robEntries_0_cmd_domain_id <= 4'h0; + robEntries_0_cmd_ball_bid <= 5'h0; + robEntries_0_cmd_cmd_raw_inst <= 32'h0; + robEntries_0_cmd_cmd_pc <= 64'h0; + robEntries_0_cmd_cmd_funct <= 7'h0; + robEntries_0_cmd_cmd_funct3 <= 3'h0; + robEntries_0_cmd_cmd_rs2 <= 5'h0; + robEntries_0_cmd_cmd_rs1 <= 5'h0; + robEntries_0_cmd_cmd_xd <= 1'h0; + robEntries_0_cmd_cmd_xs1 <= 1'h0; + robEntries_0_cmd_cmd_xs2 <= 1'h0; + robEntries_0_cmd_cmd_rd <= 5'h0; + robEntries_0_cmd_cmd_opcode <= 7'h0; + robEntries_0_cmd_cmd_rs1Data <= 64'h0; + robEntries_0_cmd_cmd_rs2Data <= 64'h0; + robEntries_0_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_0_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_0_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_0_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_0_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_0_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_0_cmd_isFence <= 1'h0; + robEntries_0_cmd_isBarrier <= 1'h0; + robEntries_0_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_0_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_0_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_0_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_0_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_0_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_0_rob_id <= 4'h0; + robEntries_1_cmd_domain_id <= 4'h0; + robEntries_1_cmd_ball_bid <= 5'h0; + robEntries_1_cmd_cmd_raw_inst <= 32'h0; + robEntries_1_cmd_cmd_pc <= 64'h0; + robEntries_1_cmd_cmd_funct <= 7'h0; + robEntries_1_cmd_cmd_funct3 <= 3'h0; + robEntries_1_cmd_cmd_rs2 <= 5'h0; + robEntries_1_cmd_cmd_rs1 <= 5'h0; + robEntries_1_cmd_cmd_xd <= 1'h0; + robEntries_1_cmd_cmd_xs1 <= 1'h0; + robEntries_1_cmd_cmd_xs2 <= 1'h0; + robEntries_1_cmd_cmd_rd <= 5'h0; + robEntries_1_cmd_cmd_opcode <= 7'h0; + robEntries_1_cmd_cmd_rs1Data <= 64'h0; + robEntries_1_cmd_cmd_rs2Data <= 64'h0; + robEntries_1_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_1_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_1_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_1_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_1_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_1_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_1_cmd_isFence <= 1'h0; + robEntries_1_cmd_isBarrier <= 1'h0; + robEntries_1_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_1_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_1_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_1_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_1_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_1_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_1_rob_id <= 4'h0; + robEntries_2_cmd_domain_id <= 4'h0; + robEntries_2_cmd_ball_bid <= 5'h0; + robEntries_2_cmd_cmd_raw_inst <= 32'h0; + robEntries_2_cmd_cmd_pc <= 64'h0; + robEntries_2_cmd_cmd_funct <= 7'h0; + robEntries_2_cmd_cmd_funct3 <= 3'h0; + robEntries_2_cmd_cmd_rs2 <= 5'h0; + robEntries_2_cmd_cmd_rs1 <= 5'h0; + robEntries_2_cmd_cmd_xd <= 1'h0; + robEntries_2_cmd_cmd_xs1 <= 1'h0; + robEntries_2_cmd_cmd_xs2 <= 1'h0; + robEntries_2_cmd_cmd_rd <= 5'h0; + robEntries_2_cmd_cmd_opcode <= 7'h0; + robEntries_2_cmd_cmd_rs1Data <= 64'h0; + robEntries_2_cmd_cmd_rs2Data <= 64'h0; + robEntries_2_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_2_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_2_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_2_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_2_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_2_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_2_cmd_isFence <= 1'h0; + robEntries_2_cmd_isBarrier <= 1'h0; + robEntries_2_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_2_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_2_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_2_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_2_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_2_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_2_rob_id <= 4'h0; + robEntries_3_cmd_domain_id <= 4'h0; + robEntries_3_cmd_ball_bid <= 5'h0; + robEntries_3_cmd_cmd_raw_inst <= 32'h0; + robEntries_3_cmd_cmd_pc <= 64'h0; + robEntries_3_cmd_cmd_funct <= 7'h0; + robEntries_3_cmd_cmd_funct3 <= 3'h0; + robEntries_3_cmd_cmd_rs2 <= 5'h0; + robEntries_3_cmd_cmd_rs1 <= 5'h0; + robEntries_3_cmd_cmd_xd <= 1'h0; + robEntries_3_cmd_cmd_xs1 <= 1'h0; + robEntries_3_cmd_cmd_xs2 <= 1'h0; + robEntries_3_cmd_cmd_rd <= 5'h0; + robEntries_3_cmd_cmd_opcode <= 7'h0; + robEntries_3_cmd_cmd_rs1Data <= 64'h0; + robEntries_3_cmd_cmd_rs2Data <= 64'h0; + robEntries_3_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_3_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_3_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_3_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_3_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_3_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_3_cmd_isFence <= 1'h0; + robEntries_3_cmd_isBarrier <= 1'h0; + robEntries_3_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_3_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_3_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_3_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_3_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_3_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_3_rob_id <= 4'h0; + robEntries_4_cmd_domain_id <= 4'h0; + robEntries_4_cmd_ball_bid <= 5'h0; + robEntries_4_cmd_cmd_raw_inst <= 32'h0; + robEntries_4_cmd_cmd_pc <= 64'h0; + robEntries_4_cmd_cmd_funct <= 7'h0; + robEntries_4_cmd_cmd_funct3 <= 3'h0; + robEntries_4_cmd_cmd_rs2 <= 5'h0; + robEntries_4_cmd_cmd_rs1 <= 5'h0; + robEntries_4_cmd_cmd_xd <= 1'h0; + robEntries_4_cmd_cmd_xs1 <= 1'h0; + robEntries_4_cmd_cmd_xs2 <= 1'h0; + robEntries_4_cmd_cmd_rd <= 5'h0; + robEntries_4_cmd_cmd_opcode <= 7'h0; + robEntries_4_cmd_cmd_rs1Data <= 64'h0; + robEntries_4_cmd_cmd_rs2Data <= 64'h0; + robEntries_4_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_4_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_4_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_4_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_4_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_4_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_4_cmd_isFence <= 1'h0; + robEntries_4_cmd_isBarrier <= 1'h0; + robEntries_4_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_4_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_4_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_4_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_4_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_4_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_4_rob_id <= 4'h0; + robEntries_5_cmd_domain_id <= 4'h0; + robEntries_5_cmd_ball_bid <= 5'h0; + robEntries_5_cmd_cmd_raw_inst <= 32'h0; + robEntries_5_cmd_cmd_pc <= 64'h0; + robEntries_5_cmd_cmd_funct <= 7'h0; + robEntries_5_cmd_cmd_funct3 <= 3'h0; + robEntries_5_cmd_cmd_rs2 <= 5'h0; + robEntries_5_cmd_cmd_rs1 <= 5'h0; + robEntries_5_cmd_cmd_xd <= 1'h0; + robEntries_5_cmd_cmd_xs1 <= 1'h0; + robEntries_5_cmd_cmd_xs2 <= 1'h0; + robEntries_5_cmd_cmd_rd <= 5'h0; + robEntries_5_cmd_cmd_opcode <= 7'h0; + robEntries_5_cmd_cmd_rs1Data <= 64'h0; + robEntries_5_cmd_cmd_rs2Data <= 64'h0; + robEntries_5_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_5_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_5_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_5_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_5_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_5_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_5_cmd_isFence <= 1'h0; + robEntries_5_cmd_isBarrier <= 1'h0; + robEntries_5_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_5_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_5_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_5_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_5_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_5_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_5_rob_id <= 4'h0; + robEntries_6_cmd_domain_id <= 4'h0; + robEntries_6_cmd_ball_bid <= 5'h0; + robEntries_6_cmd_cmd_raw_inst <= 32'h0; + robEntries_6_cmd_cmd_pc <= 64'h0; + robEntries_6_cmd_cmd_funct <= 7'h0; + robEntries_6_cmd_cmd_funct3 <= 3'h0; + robEntries_6_cmd_cmd_rs2 <= 5'h0; + robEntries_6_cmd_cmd_rs1 <= 5'h0; + robEntries_6_cmd_cmd_xd <= 1'h0; + robEntries_6_cmd_cmd_xs1 <= 1'h0; + robEntries_6_cmd_cmd_xs2 <= 1'h0; + robEntries_6_cmd_cmd_rd <= 5'h0; + robEntries_6_cmd_cmd_opcode <= 7'h0; + robEntries_6_cmd_cmd_rs1Data <= 64'h0; + robEntries_6_cmd_cmd_rs2Data <= 64'h0; + robEntries_6_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_6_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_6_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_6_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_6_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_6_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_6_cmd_isFence <= 1'h0; + robEntries_6_cmd_isBarrier <= 1'h0; + robEntries_6_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_6_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_6_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_6_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_6_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_6_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_6_rob_id <= 4'h0; + robEntries_7_cmd_domain_id <= 4'h0; + robEntries_7_cmd_ball_bid <= 5'h0; + robEntries_7_cmd_cmd_raw_inst <= 32'h0; + robEntries_7_cmd_cmd_pc <= 64'h0; + robEntries_7_cmd_cmd_funct <= 7'h0; + robEntries_7_cmd_cmd_funct3 <= 3'h0; + robEntries_7_cmd_cmd_rs2 <= 5'h0; + robEntries_7_cmd_cmd_rs1 <= 5'h0; + robEntries_7_cmd_cmd_xd <= 1'h0; + robEntries_7_cmd_cmd_xs1 <= 1'h0; + robEntries_7_cmd_cmd_xs2 <= 1'h0; + robEntries_7_cmd_cmd_rd <= 5'h0; + robEntries_7_cmd_cmd_opcode <= 7'h0; + robEntries_7_cmd_cmd_rs1Data <= 64'h0; + robEntries_7_cmd_cmd_rs2Data <= 64'h0; + robEntries_7_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_7_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_7_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_7_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_7_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_7_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_7_cmd_isFence <= 1'h0; + robEntries_7_cmd_isBarrier <= 1'h0; + robEntries_7_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_7_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_7_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_7_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_7_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_7_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_7_rob_id <= 4'h0; + robEntries_8_cmd_domain_id <= 4'h0; + robEntries_8_cmd_ball_bid <= 5'h0; + robEntries_8_cmd_cmd_raw_inst <= 32'h0; + robEntries_8_cmd_cmd_pc <= 64'h0; + robEntries_8_cmd_cmd_funct <= 7'h0; + robEntries_8_cmd_cmd_funct3 <= 3'h0; + robEntries_8_cmd_cmd_rs2 <= 5'h0; + robEntries_8_cmd_cmd_rs1 <= 5'h0; + robEntries_8_cmd_cmd_xd <= 1'h0; + robEntries_8_cmd_cmd_xs1 <= 1'h0; + robEntries_8_cmd_cmd_xs2 <= 1'h0; + robEntries_8_cmd_cmd_rd <= 5'h0; + robEntries_8_cmd_cmd_opcode <= 7'h0; + robEntries_8_cmd_cmd_rs1Data <= 64'h0; + robEntries_8_cmd_cmd_rs2Data <= 64'h0; + robEntries_8_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_8_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_8_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_8_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_8_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_8_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_8_cmd_isFence <= 1'h0; + robEntries_8_cmd_isBarrier <= 1'h0; + robEntries_8_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_8_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_8_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_8_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_8_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_8_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_8_rob_id <= 4'h0; + robEntries_9_cmd_domain_id <= 4'h0; + robEntries_9_cmd_ball_bid <= 5'h0; + robEntries_9_cmd_cmd_raw_inst <= 32'h0; + robEntries_9_cmd_cmd_pc <= 64'h0; + robEntries_9_cmd_cmd_funct <= 7'h0; + robEntries_9_cmd_cmd_funct3 <= 3'h0; + robEntries_9_cmd_cmd_rs2 <= 5'h0; + robEntries_9_cmd_cmd_rs1 <= 5'h0; + robEntries_9_cmd_cmd_xd <= 1'h0; + robEntries_9_cmd_cmd_xs1 <= 1'h0; + robEntries_9_cmd_cmd_xs2 <= 1'h0; + robEntries_9_cmd_cmd_rd <= 5'h0; + robEntries_9_cmd_cmd_opcode <= 7'h0; + robEntries_9_cmd_cmd_rs1Data <= 64'h0; + robEntries_9_cmd_cmd_rs2Data <= 64'h0; + robEntries_9_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_9_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_9_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_9_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_9_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_9_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_9_cmd_isFence <= 1'h0; + robEntries_9_cmd_isBarrier <= 1'h0; + robEntries_9_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_9_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_9_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_9_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_9_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_9_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_9_rob_id <= 4'h0; + robEntries_10_cmd_domain_id <= 4'h0; + robEntries_10_cmd_ball_bid <= 5'h0; + robEntries_10_cmd_cmd_raw_inst <= 32'h0; + robEntries_10_cmd_cmd_pc <= 64'h0; + robEntries_10_cmd_cmd_funct <= 7'h0; + robEntries_10_cmd_cmd_funct3 <= 3'h0; + robEntries_10_cmd_cmd_rs2 <= 5'h0; + robEntries_10_cmd_cmd_rs1 <= 5'h0; + robEntries_10_cmd_cmd_xd <= 1'h0; + robEntries_10_cmd_cmd_xs1 <= 1'h0; + robEntries_10_cmd_cmd_xs2 <= 1'h0; + robEntries_10_cmd_cmd_rd <= 5'h0; + robEntries_10_cmd_cmd_opcode <= 7'h0; + robEntries_10_cmd_cmd_rs1Data <= 64'h0; + robEntries_10_cmd_cmd_rs2Data <= 64'h0; + robEntries_10_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_10_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_10_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_10_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_10_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_10_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_10_cmd_isFence <= 1'h0; + robEntries_10_cmd_isBarrier <= 1'h0; + robEntries_10_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_10_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_10_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_10_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_10_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_10_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_10_rob_id <= 4'h0; + robEntries_11_cmd_domain_id <= 4'h0; + robEntries_11_cmd_ball_bid <= 5'h0; + robEntries_11_cmd_cmd_raw_inst <= 32'h0; + robEntries_11_cmd_cmd_pc <= 64'h0; + robEntries_11_cmd_cmd_funct <= 7'h0; + robEntries_11_cmd_cmd_funct3 <= 3'h0; + robEntries_11_cmd_cmd_rs2 <= 5'h0; + robEntries_11_cmd_cmd_rs1 <= 5'h0; + robEntries_11_cmd_cmd_xd <= 1'h0; + robEntries_11_cmd_cmd_xs1 <= 1'h0; + robEntries_11_cmd_cmd_xs2 <= 1'h0; + robEntries_11_cmd_cmd_rd <= 5'h0; + robEntries_11_cmd_cmd_opcode <= 7'h0; + robEntries_11_cmd_cmd_rs1Data <= 64'h0; + robEntries_11_cmd_cmd_rs2Data <= 64'h0; + robEntries_11_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_11_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_11_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_11_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_11_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_11_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_11_cmd_isFence <= 1'h0; + robEntries_11_cmd_isBarrier <= 1'h0; + robEntries_11_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_11_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_11_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_11_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_11_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_11_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_11_rob_id <= 4'h0; + robEntries_12_cmd_domain_id <= 4'h0; + robEntries_12_cmd_ball_bid <= 5'h0; + robEntries_12_cmd_cmd_raw_inst <= 32'h0; + robEntries_12_cmd_cmd_pc <= 64'h0; + robEntries_12_cmd_cmd_funct <= 7'h0; + robEntries_12_cmd_cmd_funct3 <= 3'h0; + robEntries_12_cmd_cmd_rs2 <= 5'h0; + robEntries_12_cmd_cmd_rs1 <= 5'h0; + robEntries_12_cmd_cmd_xd <= 1'h0; + robEntries_12_cmd_cmd_xs1 <= 1'h0; + robEntries_12_cmd_cmd_xs2 <= 1'h0; + robEntries_12_cmd_cmd_rd <= 5'h0; + robEntries_12_cmd_cmd_opcode <= 7'h0; + robEntries_12_cmd_cmd_rs1Data <= 64'h0; + robEntries_12_cmd_cmd_rs2Data <= 64'h0; + robEntries_12_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_12_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_12_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_12_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_12_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_12_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_12_cmd_isFence <= 1'h0; + robEntries_12_cmd_isBarrier <= 1'h0; + robEntries_12_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_12_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_12_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_12_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_12_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_12_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_12_rob_id <= 4'h0; + robEntries_13_cmd_domain_id <= 4'h0; + robEntries_13_cmd_ball_bid <= 5'h0; + robEntries_13_cmd_cmd_raw_inst <= 32'h0; + robEntries_13_cmd_cmd_pc <= 64'h0; + robEntries_13_cmd_cmd_funct <= 7'h0; + robEntries_13_cmd_cmd_funct3 <= 3'h0; + robEntries_13_cmd_cmd_rs2 <= 5'h0; + robEntries_13_cmd_cmd_rs1 <= 5'h0; + robEntries_13_cmd_cmd_xd <= 1'h0; + robEntries_13_cmd_cmd_xs1 <= 1'h0; + robEntries_13_cmd_cmd_xs2 <= 1'h0; + robEntries_13_cmd_cmd_rd <= 5'h0; + robEntries_13_cmd_cmd_opcode <= 7'h0; + robEntries_13_cmd_cmd_rs1Data <= 64'h0; + robEntries_13_cmd_cmd_rs2Data <= 64'h0; + robEntries_13_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_13_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_13_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_13_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_13_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_13_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_13_cmd_isFence <= 1'h0; + robEntries_13_cmd_isBarrier <= 1'h0; + robEntries_13_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_13_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_13_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_13_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_13_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_13_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_13_rob_id <= 4'h0; + robEntries_14_cmd_domain_id <= 4'h0; + robEntries_14_cmd_ball_bid <= 5'h0; + robEntries_14_cmd_cmd_raw_inst <= 32'h0; + robEntries_14_cmd_cmd_pc <= 64'h0; + robEntries_14_cmd_cmd_funct <= 7'h0; + robEntries_14_cmd_cmd_funct3 <= 3'h0; + robEntries_14_cmd_cmd_rs2 <= 5'h0; + robEntries_14_cmd_cmd_rs1 <= 5'h0; + robEntries_14_cmd_cmd_xd <= 1'h0; + robEntries_14_cmd_cmd_xs1 <= 1'h0; + robEntries_14_cmd_cmd_xs2 <= 1'h0; + robEntries_14_cmd_cmd_rd <= 5'h0; + robEntries_14_cmd_cmd_opcode <= 7'h0; + robEntries_14_cmd_cmd_rs1Data <= 64'h0; + robEntries_14_cmd_cmd_rs2Data <= 64'h0; + robEntries_14_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_14_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_14_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_14_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_14_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_14_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_14_cmd_isFence <= 1'h0; + robEntries_14_cmd_isBarrier <= 1'h0; + robEntries_14_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_14_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_14_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_14_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_14_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_14_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_14_rob_id <= 4'h0; + robEntries_15_cmd_domain_id <= 4'h0; + robEntries_15_cmd_ball_bid <= 5'h0; + robEntries_15_cmd_cmd_raw_inst <= 32'h0; + robEntries_15_cmd_cmd_pc <= 64'h0; + robEntries_15_cmd_cmd_funct <= 7'h0; + robEntries_15_cmd_cmd_funct3 <= 3'h0; + robEntries_15_cmd_cmd_rs2 <= 5'h0; + robEntries_15_cmd_cmd_rs1 <= 5'h0; + robEntries_15_cmd_cmd_xd <= 1'h0; + robEntries_15_cmd_cmd_xs1 <= 1'h0; + robEntries_15_cmd_cmd_xs2 <= 1'h0; + robEntries_15_cmd_cmd_rd <= 5'h0; + robEntries_15_cmd_cmd_opcode <= 7'h0; + robEntries_15_cmd_cmd_rs1Data <= 64'h0; + robEntries_15_cmd_cmd_rs2Data <= 64'h0; + robEntries_15_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_15_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_15_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_15_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_15_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_15_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_15_cmd_isFence <= 1'h0; + robEntries_15_cmd_isBarrier <= 1'h0; + robEntries_15_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_15_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_15_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_15_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_15_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_15_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_15_rob_id <= 4'h0; + robValid_0 <= 1'h0; + robValid_1 <= 1'h0; + robValid_2 <= 1'h0; + robValid_3 <= 1'h0; + robValid_4 <= 1'h0; + robValid_5 <= 1'h0; + robValid_6 <= 1'h0; + robValid_7 <= 1'h0; + robValid_8 <= 1'h0; + robValid_9 <= 1'h0; + robValid_10 <= 1'h0; + robValid_11 <= 1'h0; + robValid_12 <= 1'h0; + robValid_13 <= 1'h0; + robValid_14 <= 1'h0; + robValid_15 <= 1'h0; + robIssued_0 <= 1'h0; + robIssued_1 <= 1'h0; + robIssued_2 <= 1'h0; + robIssued_3 <= 1'h0; + robIssued_4 <= 1'h0; + robIssued_5 <= 1'h0; + robIssued_6 <= 1'h0; + robIssued_7 <= 1'h0; + robIssued_8 <= 1'h0; + robIssued_9 <= 1'h0; + robIssued_10 <= 1'h0; + robIssued_11 <= 1'h0; + robIssued_12 <= 1'h0; + robIssued_13 <= 1'h0; + robIssued_14 <= 1'h0; + robIssued_15 <= 1'h0; + robComplete_0 <= 1'h0; + robComplete_1 <= 1'h0; + robComplete_2 <= 1'h0; + robComplete_3 <= 1'h0; + robComplete_4 <= 1'h0; + robComplete_5 <= 1'h0; + robComplete_6 <= 1'h0; + robComplete_7 <= 1'h0; + robComplete_8 <= 1'h0; + robComplete_9 <= 1'h0; + robComplete_10 <= 1'h0; + robComplete_11 <= 1'h0; + robComplete_12 <= 1'h0; + robComplete_13 <= 1'h0; + robComplete_14 <= 1'h0; + robComplete_15 <= 1'h0; + instIds_0 <= 64'h0; + instIds_1 <= 64'h0; + instIds_2 <= 64'h0; + instIds_3 <= 64'h0; + instIds_4 <= 64'h0; + instIds_5 <= 64'h0; + instIds_6 <= 64'h0; + instIds_7 <= 64'h0; + instIds_8 <= 64'h0; + instIds_9 <= 64'h0; + instIds_10 <= 64'h0; + instIds_11 <= 64'h0; + instIds_12 <= 64'h0; + instIds_13 <= 64'h0; + instIds_14 <= 64'h0; + instIds_15 <= 64'h0; + nextInstId <= 64'h1; + ptr <= 4'h0; + tailPtr <= 4'h0; + issuedCount <= 5'h0; + bankCols_0 <= 4'h0; + bankCols_1 <= 4'h0; + bankCols_2 <= 4'h0; + bankCols_3 <= 4'h0; + bankCols_4 <= 4'h0; + bankCols_5 <= 4'h0; + bankCols_6 <= 4'h0; + bankCols_7 <= 4'h0; + bankCols_8 <= 4'h0; + bankCols_9 <= 4'h0; + bankCols_10 <= 4'h0; + bankCols_11 <= 4'h0; + bankCols_12 <= 4'h0; + bankCols_13 <= 4'h0; + bankCols_14 <= 4'h0; + bankCols_15 <= 4'h0; + vbankBusy <= 16'h0; + dependencyMask_0 <= 16'h0; + dependencyMask_1 <= 16'h0; + dependencyMask_2 <= 16'h0; + dependencyMask_3 <= 16'h0; + dependencyMask_4 <= 16'h0; + dependencyMask_5 <= 16'h0; + dependencyMask_6 <= 16'h0; + dependencyMask_7 <= 16'h0; + dependencyMask_8 <= 16'h0; + dependencyMask_9 <= 16'h0; + dependencyMask_10 <= 16'h0; + dependencyMask_11 <= 16'h0; + dependencyMask_12 <= 16'h0; + dependencyMask_13 <= 16'h0; + dependencyMask_14 <= 16'h0; + dependencyMask_15 <= 16'h0; + issueStageValid <= 1'h0; + issuePtrValid <= 1'h0; + end + else begin + automatic logic _entryIsConfig_0_T = robEntries_0_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_0 = + _entryIsConfig_0_T & robEntries_0_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_1_T = robEntries_1_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_1 = + _entryIsConfig_1_T & robEntries_1_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_2_T = robEntries_2_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_2 = + _entryIsConfig_2_T & robEntries_2_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_3_T = robEntries_3_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_3 = + _entryIsConfig_3_T & robEntries_3_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_4_T = robEntries_4_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_4 = + _entryIsConfig_4_T & robEntries_4_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_5_T = robEntries_5_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_5 = + _entryIsConfig_5_T & robEntries_5_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_6_T = robEntries_6_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_6 = + _entryIsConfig_6_T & robEntries_6_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_7_T = robEntries_7_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_7 = + _entryIsConfig_7_T & robEntries_7_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_8_T = robEntries_8_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_8 = + _entryIsConfig_8_T & robEntries_8_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_9_T = robEntries_9_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_9 = + _entryIsConfig_9_T & robEntries_9_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_10_T = robEntries_10_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_10 = + _entryIsConfig_10_T & robEntries_10_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_11_T = robEntries_11_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_11 = + _entryIsConfig_11_T & robEntries_11_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_12_T = robEntries_12_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_12 = + _entryIsConfig_12_T & robEntries_12_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_13_T = robEntries_13_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_13 = + _entryIsConfig_13_T & robEntries_13_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_14_T = robEntries_14_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_14 = + _entryIsConfig_14_T & robEntries_14_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_15_T = robEntries_15_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_15 = + _entryIsConfig_15_T & robEntries_15_cmd_cmd_funct == 7'h20; + automatic logic [15:0] allocReadMask = + (io_alloc_bits_bankAccess_rd_bank_0_valid + & io_alloc_bits_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << io_alloc_bits_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (io_alloc_bits_bankAccess_rd_bank_1_valid + & io_alloc_bits_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << io_alloc_bits_bankAccess_rd_bank_1_id[3:0] + : 16'h0); + automatic logic [15:0] allocWriteMask = + io_alloc_bits_bankAccess_wr_bank_valid + & io_alloc_bits_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << io_alloc_bits_bankAccess_wr_bank_id[3:0] + : 16'h0; + automatic logic allocIsConfig = + io_alloc_bits_domain_id == 4'h1 & io_alloc_bits_cmd_funct == 7'h20; + automatic logic allocIsBall = io_alloc_bits_domain_id == 4'h3; + automatic logic [15:0] _configConflict_T_92 = allocReadMask | allocWriteMask; + automatic logic [15:0] allocDependencies; + automatic logic [63:0] _instIds_T; + automatic logic _GEN_20 = _isAllocatedSlot_T_30 & ~(|tailPtr); + automatic logic _GEN_21 = _isAllocatedSlot_T_30 & tailPtr == 4'h1; + automatic logic _GEN_22 = _isAllocatedSlot_T_30 & tailPtr == 4'h2; + automatic logic _GEN_23 = _isAllocatedSlot_T_30 & tailPtr == 4'h3; + automatic logic _GEN_24 = _isAllocatedSlot_T_30 & tailPtr == 4'h4; + automatic logic _GEN_25 = _isAllocatedSlot_T_30 & tailPtr == 4'h5; + automatic logic _GEN_26 = _isAllocatedSlot_T_30 & tailPtr == 4'h6; + automatic logic _GEN_27 = _isAllocatedSlot_T_30 & tailPtr == 4'h7; + automatic logic _GEN_28 = _isAllocatedSlot_T_30 & tailPtr == 4'h8; + automatic logic _GEN_29 = _isAllocatedSlot_T_30 & tailPtr == 4'h9; + automatic logic _GEN_30 = _isAllocatedSlot_T_30 & tailPtr == 4'hA; + automatic logic _GEN_31 = _isAllocatedSlot_T_30 & tailPtr == 4'hB; + automatic logic _GEN_32 = _isAllocatedSlot_T_30 & tailPtr == 4'hC; + automatic logic _GEN_33 = _isAllocatedSlot_T_30 & tailPtr == 4'hD; + automatic logic _GEN_34 = _isAllocatedSlot_T_30 & tailPtr == 4'hE; + automatic logic _GEN_35 = _isAllocatedSlot_T_30 & (&tailPtr); + automatic logic [15:0] completedBitMask = + io_complete_valid ? 16'h1 << io_complete_bits : 16'h0; + automatic logic [3:0] _GEN_36; + automatic logic _GEN_37; + automatic logic [3:0] _GEN_38; + automatic logic _GEN_39; + automatic logic [3:0] _GEN_40; + automatic logic _GEN_41; + automatic logic [3:0] _GEN_42; + automatic logic _GEN_43; + automatic logic [3:0] _GEN_44; + automatic logic _GEN_45; + automatic logic [3:0] _GEN_46; + automatic logic _GEN_47; + automatic logic [3:0] _GEN_48; + automatic logic _GEN_49; + automatic logic [3:0] _GEN_50; + automatic logic _GEN_51; + automatic logic [3:0] _GEN_52; + automatic logic _GEN_53; + automatic logic [3:0] _GEN_54; + automatic logic _GEN_55; + automatic logic [3:0] _GEN_56; + automatic logic _GEN_57; + automatic logic [3:0] _GEN_58; + automatic logic _GEN_59; + automatic logic [3:0] _GEN_60; + automatic logic _GEN_61; + automatic logic [3:0] _GEN_62; + automatic logic _GEN_63; + automatic logic [3:0] _GEN_64; + automatic logic _GEN_65; + automatic logic [3:0] _GEN_66; + automatic logic _GEN_67 = + commitMask_15 & _entryIsConfig_15_T & robEntries_15_cmd_cmd_funct == 7'h20; + automatic logic [15:0] configEntryMask = + {entryIsConfig_15, + entryIsConfig_14, + entryIsConfig_13, + entryIsConfig_12, + entryIsConfig_11, + entryIsConfig_10, + entryIsConfig_9, + entryIsConfig_8, + entryIsConfig_7, + entryIsConfig_6, + entryIsConfig_5, + entryIsConfig_4, + entryIsConfig_3, + entryIsConfig_2, + entryIsConfig_1, + entryIsConfig_0}; + automatic logic isAllocatedSlot = _isAllocatedSlot_T_30 & ~(|tailPtr); + automatic logic [15:0] clearMask; + automatic logic isAllocatedSlot_1 = _isAllocatedSlot_T_30 & tailPtr == 4'h1; + automatic logic [15:0] clearMask_1; + automatic logic isAllocatedSlot_2 = _isAllocatedSlot_T_30 & tailPtr == 4'h2; + automatic logic [15:0] clearMask_2; + automatic logic isAllocatedSlot_3 = _isAllocatedSlot_T_30 & tailPtr == 4'h3; + automatic logic [15:0] clearMask_3; + automatic logic isAllocatedSlot_4 = _isAllocatedSlot_T_30 & tailPtr == 4'h4; + automatic logic [15:0] clearMask_4; + automatic logic isAllocatedSlot_5 = _isAllocatedSlot_T_30 & tailPtr == 4'h5; + automatic logic [15:0] clearMask_5; + automatic logic isAllocatedSlot_6 = _isAllocatedSlot_T_30 & tailPtr == 4'h6; + automatic logic [15:0] clearMask_6; + automatic logic isAllocatedSlot_7 = _isAllocatedSlot_T_30 & tailPtr == 4'h7; + automatic logic [15:0] clearMask_7; + automatic logic isAllocatedSlot_8 = _isAllocatedSlot_T_30 & tailPtr == 4'h8; + automatic logic [15:0] clearMask_8; + automatic logic isAllocatedSlot_9 = _isAllocatedSlot_T_30 & tailPtr == 4'h9; + automatic logic [15:0] clearMask_9; + automatic logic isAllocatedSlot_10 = _isAllocatedSlot_T_30 & tailPtr == 4'hA; + automatic logic [15:0] clearMask_10; + automatic logic isAllocatedSlot_11 = _isAllocatedSlot_T_30 & tailPtr == 4'hB; + automatic logic [15:0] clearMask_11; + automatic logic isAllocatedSlot_12 = _isAllocatedSlot_T_30 & tailPtr == 4'hC; + automatic logic [15:0] clearMask_12; + automatic logic isAllocatedSlot_13 = _isAllocatedSlot_T_30 & tailPtr == 4'hD; + automatic logic [15:0] clearMask_13; + automatic logic isAllocatedSlot_14 = _isAllocatedSlot_T_30 & tailPtr == 4'hE; + automatic logic [15:0] clearMask_14; + automatic logic isAllocatedSlot_15 = _isAllocatedSlot_T_30 & (&tailPtr); + automatic logic [15:0] clearMask_15; + allocDependencies = + {robValid_15 & ~robComplete_15 + & ((|(allocReadMask & entryRawWrites_15 | allocWriteMask & vbankMasks_15)) + | allocIsBall & robEntries_15_cmd_domain_id == 4'h3 + & robEntries_15_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_15 + & (allocIsConfig & entryIsConfig_15 | (allocIsConfig | entryIsConfig_15) + & (|(_configConflict_T_92 & vbankMasks_15))), + robValid_14 & ~robComplete_14 + & ((|(allocReadMask & entryRawWrites_14 | allocWriteMask & vbankMasks_14)) + | allocIsBall & robEntries_14_cmd_domain_id == 4'h3 + & robEntries_14_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_14 + & (allocIsConfig & entryIsConfig_14 | (allocIsConfig | entryIsConfig_14) + & (|(_configConflict_T_92 & vbankMasks_14))), + robValid_13 & ~robComplete_13 + & ((|(allocReadMask & entryRawWrites_13 | allocWriteMask & vbankMasks_13)) + | allocIsBall & robEntries_13_cmd_domain_id == 4'h3 + & robEntries_13_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_13 + & (allocIsConfig & entryIsConfig_13 | (allocIsConfig | entryIsConfig_13) + & (|(_configConflict_T_92 & vbankMasks_13))), + robValid_12 & ~robComplete_12 + & ((|(allocReadMask & entryRawWrites_12 | allocWriteMask & vbankMasks_12)) + | allocIsBall & robEntries_12_cmd_domain_id == 4'h3 + & robEntries_12_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_12 + & (allocIsConfig & entryIsConfig_12 | (allocIsConfig | entryIsConfig_12) + & (|(_configConflict_T_92 & vbankMasks_12))), + robValid_11 & ~robComplete_11 + & ((|(allocReadMask & entryRawWrites_11 | allocWriteMask & vbankMasks_11)) + | allocIsBall & robEntries_11_cmd_domain_id == 4'h3 + & robEntries_11_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_11 + & (allocIsConfig & entryIsConfig_11 | (allocIsConfig | entryIsConfig_11) + & (|(_configConflict_T_92 & vbankMasks_11))), + robValid_10 & ~robComplete_10 + & ((|(allocReadMask & entryRawWrites_10 | allocWriteMask & vbankMasks_10)) + | allocIsBall & robEntries_10_cmd_domain_id == 4'h3 + & robEntries_10_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_10 + & (allocIsConfig & entryIsConfig_10 | (allocIsConfig | entryIsConfig_10) + & (|(_configConflict_T_92 & vbankMasks_10))), + robValid_9 & ~robComplete_9 + & ((|(allocReadMask & entryRawWrites_9 | allocWriteMask & vbankMasks_9)) + | allocIsBall & robEntries_9_cmd_domain_id == 4'h3 + & robEntries_9_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_9 + & (allocIsConfig & entryIsConfig_9 | (allocIsConfig | entryIsConfig_9) + & (|(_configConflict_T_92 & vbankMasks_9))), + robValid_8 & ~robComplete_8 + & ((|(allocReadMask & entryRawWrites_8 | allocWriteMask & vbankMasks_8)) + | allocIsBall & robEntries_8_cmd_domain_id == 4'h3 + & robEntries_8_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_8 + & (allocIsConfig & entryIsConfig_8 | (allocIsConfig | entryIsConfig_8) + & (|(_configConflict_T_92 & vbankMasks_8))), + robValid_7 & ~robComplete_7 + & ((|(allocReadMask & entryRawWrites_7 | allocWriteMask & vbankMasks_7)) + | allocIsBall & robEntries_7_cmd_domain_id == 4'h3 + & robEntries_7_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_7 + & (allocIsConfig & entryIsConfig_7 | (allocIsConfig | entryIsConfig_7) + & (|(_configConflict_T_92 & vbankMasks_7))), + robValid_6 & ~robComplete_6 + & ((|(allocReadMask & entryRawWrites_6 | allocWriteMask & vbankMasks_6)) + | allocIsBall & robEntries_6_cmd_domain_id == 4'h3 + & robEntries_6_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_6 + & (allocIsConfig & entryIsConfig_6 | (allocIsConfig | entryIsConfig_6) + & (|(_configConflict_T_92 & vbankMasks_6))), + robValid_5 & ~robComplete_5 + & ((|(allocReadMask & entryRawWrites_5 | allocWriteMask & vbankMasks_5)) + | allocIsBall & robEntries_5_cmd_domain_id == 4'h3 + & robEntries_5_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_5 + & (allocIsConfig & entryIsConfig_5 | (allocIsConfig | entryIsConfig_5) + & (|(_configConflict_T_92 & vbankMasks_5))), + robValid_4 & ~robComplete_4 + & ((|(allocReadMask & entryRawWrites_4 | allocWriteMask & vbankMasks_4)) + | allocIsBall & robEntries_4_cmd_domain_id == 4'h3 + & robEntries_4_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_4 + & (allocIsConfig & entryIsConfig_4 | (allocIsConfig | entryIsConfig_4) + & (|(_configConflict_T_92 & vbankMasks_4))), + robValid_3 & ~robComplete_3 + & ((|(allocReadMask & entryRawWrites_3 | allocWriteMask & vbankMasks_3)) + | allocIsBall & robEntries_3_cmd_domain_id == 4'h3 + & robEntries_3_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_3 + & (allocIsConfig & entryIsConfig_3 | (allocIsConfig | entryIsConfig_3) + & (|(_configConflict_T_92 & vbankMasks_3))), + robValid_2 & ~robComplete_2 + & ((|(allocReadMask & entryRawWrites_2 | allocWriteMask & vbankMasks_2)) + | allocIsBall & robEntries_2_cmd_domain_id == 4'h3 + & robEntries_2_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_2 + & (allocIsConfig & entryIsConfig_2 | (allocIsConfig | entryIsConfig_2) + & (|(_configConflict_T_92 & vbankMasks_2))), + robValid_1 & ~robComplete_1 + & ((|(allocReadMask & entryRawWrites_1 | allocWriteMask & vbankMasks_1)) + | allocIsBall & robEntries_1_cmd_domain_id == 4'h3 + & robEntries_1_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_1 + & (allocIsConfig & entryIsConfig_1 | (allocIsConfig | entryIsConfig_1) + & (|(_configConflict_T_92 & vbankMasks_1))), + robValid_0 & ~robComplete_0 + & ((|(allocReadMask & entryRawWrites_0 | allocWriteMask & olderUseMask)) + | allocIsBall & robEntries_0_cmd_domain_id == 4'h3 + & robEntries_0_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_0 + & (allocIsConfig & entryIsConfig_0 | (allocIsConfig | entryIsConfig_0) + & (|(_configConflict_T_92 & olderUseMask)))}; + _instIds_T = (|io_alloc_bits_cmd_pc) ? nextInstId : 64'h0; + _GEN_36 = + robEntries_0_cmd_cmd_rs2Data[10] + ? (robEntries_0_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_0_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_37 = commitMask_0 & _entryIsConfig_0_T & robEntries_0_cmd_cmd_funct == 7'h20; + _GEN_38 = + robEntries_1_cmd_cmd_rs2Data[10] + ? (robEntries_1_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_1_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_39 = commitMask_1 & _entryIsConfig_1_T & robEntries_1_cmd_cmd_funct == 7'h20; + _GEN_40 = + robEntries_2_cmd_cmd_rs2Data[10] + ? (robEntries_2_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_2_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_41 = commitMask_2 & _entryIsConfig_2_T & robEntries_2_cmd_cmd_funct == 7'h20; + _GEN_42 = + robEntries_3_cmd_cmd_rs2Data[10] + ? (robEntries_3_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_3_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_43 = commitMask_3 & _entryIsConfig_3_T & robEntries_3_cmd_cmd_funct == 7'h20; + _GEN_44 = + robEntries_4_cmd_cmd_rs2Data[10] + ? (robEntries_4_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_4_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_45 = commitMask_4 & _entryIsConfig_4_T & robEntries_4_cmd_cmd_funct == 7'h20; + _GEN_46 = + robEntries_5_cmd_cmd_rs2Data[10] + ? (robEntries_5_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_5_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_47 = commitMask_5 & _entryIsConfig_5_T & robEntries_5_cmd_cmd_funct == 7'h20; + _GEN_48 = + robEntries_6_cmd_cmd_rs2Data[10] + ? (robEntries_6_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_6_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_49 = commitMask_6 & _entryIsConfig_6_T & robEntries_6_cmd_cmd_funct == 7'h20; + _GEN_50 = + robEntries_7_cmd_cmd_rs2Data[10] + ? (robEntries_7_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_7_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_51 = commitMask_7 & _entryIsConfig_7_T & robEntries_7_cmd_cmd_funct == 7'h20; + _GEN_52 = + robEntries_8_cmd_cmd_rs2Data[10] + ? (robEntries_8_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_8_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_53 = commitMask_8 & _entryIsConfig_8_T & robEntries_8_cmd_cmd_funct == 7'h20; + _GEN_54 = + robEntries_9_cmd_cmd_rs2Data[10] + ? (robEntries_9_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_9_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_55 = commitMask_9 & _entryIsConfig_9_T & robEntries_9_cmd_cmd_funct == 7'h20; + _GEN_56 = + robEntries_10_cmd_cmd_rs2Data[10] + ? (robEntries_10_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_10_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_57 = + commitMask_10 & _entryIsConfig_10_T & robEntries_10_cmd_cmd_funct == 7'h20; + _GEN_58 = + robEntries_11_cmd_cmd_rs2Data[10] + ? (robEntries_11_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_11_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_59 = + commitMask_11 & _entryIsConfig_11_T & robEntries_11_cmd_cmd_funct == 7'h20; + _GEN_60 = + robEntries_12_cmd_cmd_rs2Data[10] + ? (robEntries_12_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_12_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_61 = + commitMask_12 & _entryIsConfig_12_T & robEntries_12_cmd_cmd_funct == 7'h20; + _GEN_62 = + robEntries_13_cmd_cmd_rs2Data[10] + ? (robEntries_13_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_13_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_63 = + commitMask_13 & _entryIsConfig_13_T & robEntries_13_cmd_cmd_funct == 7'h20; + _GEN_64 = + robEntries_14_cmd_cmd_rs2Data[10] + ? (robEntries_14_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_14_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_65 = + commitMask_14 & _entryIsConfig_14_T & robEntries_14_cmd_cmd_funct == 7'h20; + _GEN_66 = + robEntries_15_cmd_cmd_rs2Data[10] + ? (robEntries_15_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_15_cmd_cmd_rs2Data[8:5]) + : 4'h0; + clearMask = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask | {16{isAllocatedSlot ? allocIsConfig : entryIsConfig_0}}); + clearMask_1 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask | {16{isAllocatedSlot_1 ? allocIsConfig : entryIsConfig_1}}); + clearMask_2 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask | {16{isAllocatedSlot_2 ? allocIsConfig : entryIsConfig_2}}); + clearMask_3 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask | {16{isAllocatedSlot_3 ? allocIsConfig : entryIsConfig_3}}); + clearMask_4 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask | {16{isAllocatedSlot_4 ? allocIsConfig : entryIsConfig_4}}); + clearMask_5 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask | {16{isAllocatedSlot_5 ? allocIsConfig : entryIsConfig_5}}); + clearMask_6 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask | {16{isAllocatedSlot_6 ? allocIsConfig : entryIsConfig_6}}); + clearMask_7 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask | {16{isAllocatedSlot_7 ? allocIsConfig : entryIsConfig_7}}); + clearMask_8 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask | {16{isAllocatedSlot_8 ? allocIsConfig : entryIsConfig_8}}); + clearMask_9 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask | {16{isAllocatedSlot_9 ? allocIsConfig : entryIsConfig_9}}); + clearMask_10 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask + | {16{isAllocatedSlot_10 ? allocIsConfig : entryIsConfig_10}}); + clearMask_11 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask + | {16{isAllocatedSlot_11 ? allocIsConfig : entryIsConfig_11}}); + clearMask_12 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask + | {16{isAllocatedSlot_12 ? allocIsConfig : entryIsConfig_12}}); + clearMask_13 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask + | {16{isAllocatedSlot_13 ? allocIsConfig : entryIsConfig_13}}); + clearMask_14 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask + | {16{isAllocatedSlot_14 ? allocIsConfig : entryIsConfig_14}}); + clearMask_15 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask + | {16{isAllocatedSlot_15 ? allocIsConfig : entryIsConfig_15}}); + if (_GEN_20) begin + robEntries_0_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_0_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_0_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_0_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_0_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_0_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_0_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_0_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_0_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_0_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_0_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_0_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_0_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_0_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_0_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_0_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_0_cmd_bankAccess_rd_bank_0_id <= io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_0_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_0_cmd_bankAccess_rd_bank_1_id <= io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_0_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_0_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_0_cmd_isFence <= io_alloc_bits_isFence; + robEntries_0_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_0_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_0_renamedBankAccess_rd_bank_0_id <= _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_0_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_0_renamedBankAccess_rd_bank_1_id <= _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_0_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_0_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_0_rob_id <= tailPtr; + instIds_0 <= _instIds_T; + end + if (_GEN_21) begin + robEntries_1_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_1_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_1_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_1_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_1_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_1_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_1_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_1_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_1_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_1_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_1_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_1_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_1_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_1_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_1_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_1_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_1_cmd_bankAccess_rd_bank_0_id <= io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_1_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_1_cmd_bankAccess_rd_bank_1_id <= io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_1_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_1_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_1_cmd_isFence <= io_alloc_bits_isFence; + robEntries_1_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_1_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_1_renamedBankAccess_rd_bank_0_id <= _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_1_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_1_renamedBankAccess_rd_bank_1_id <= _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_1_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_1_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_1_rob_id <= tailPtr; + instIds_1 <= _instIds_T; + end + if (_GEN_22) begin + robEntries_2_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_2_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_2_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_2_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_2_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_2_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_2_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_2_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_2_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_2_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_2_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_2_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_2_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_2_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_2_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_2_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_2_cmd_bankAccess_rd_bank_0_id <= io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_2_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_2_cmd_bankAccess_rd_bank_1_id <= io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_2_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_2_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_2_cmd_isFence <= io_alloc_bits_isFence; + robEntries_2_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_2_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_2_renamedBankAccess_rd_bank_0_id <= _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_2_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_2_renamedBankAccess_rd_bank_1_id <= _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_2_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_2_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_2_rob_id <= tailPtr; + instIds_2 <= _instIds_T; + end + if (_GEN_23) begin + robEntries_3_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_3_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_3_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_3_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_3_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_3_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_3_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_3_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_3_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_3_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_3_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_3_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_3_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_3_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_3_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_3_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_3_cmd_bankAccess_rd_bank_0_id <= io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_3_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_3_cmd_bankAccess_rd_bank_1_id <= io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_3_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_3_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_3_cmd_isFence <= io_alloc_bits_isFence; + robEntries_3_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_3_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_3_renamedBankAccess_rd_bank_0_id <= _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_3_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_3_renamedBankAccess_rd_bank_1_id <= _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_3_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_3_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_3_rob_id <= tailPtr; + instIds_3 <= _instIds_T; + end + if (_GEN_24) begin + robEntries_4_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_4_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_4_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_4_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_4_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_4_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_4_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_4_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_4_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_4_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_4_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_4_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_4_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_4_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_4_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_4_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_4_cmd_bankAccess_rd_bank_0_id <= io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_4_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_4_cmd_bankAccess_rd_bank_1_id <= io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_4_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_4_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_4_cmd_isFence <= io_alloc_bits_isFence; + robEntries_4_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_4_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_4_renamedBankAccess_rd_bank_0_id <= _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_4_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_4_renamedBankAccess_rd_bank_1_id <= _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_4_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_4_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_4_rob_id <= tailPtr; + instIds_4 <= _instIds_T; + end + if (_GEN_25) begin + robEntries_5_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_5_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_5_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_5_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_5_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_5_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_5_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_5_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_5_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_5_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_5_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_5_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_5_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_5_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_5_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_5_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_5_cmd_bankAccess_rd_bank_0_id <= io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_5_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_5_cmd_bankAccess_rd_bank_1_id <= io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_5_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_5_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_5_cmd_isFence <= io_alloc_bits_isFence; + robEntries_5_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_5_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_5_renamedBankAccess_rd_bank_0_id <= _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_5_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_5_renamedBankAccess_rd_bank_1_id <= _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_5_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_5_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_5_rob_id <= tailPtr; + instIds_5 <= _instIds_T; + end + if (_GEN_26) begin + robEntries_6_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_6_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_6_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_6_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_6_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_6_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_6_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_6_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_6_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_6_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_6_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_6_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_6_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_6_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_6_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_6_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_6_cmd_bankAccess_rd_bank_0_id <= io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_6_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_6_cmd_bankAccess_rd_bank_1_id <= io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_6_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_6_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_6_cmd_isFence <= io_alloc_bits_isFence; + robEntries_6_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_6_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_6_renamedBankAccess_rd_bank_0_id <= _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_6_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_6_renamedBankAccess_rd_bank_1_id <= _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_6_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_6_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_6_rob_id <= tailPtr; + instIds_6 <= _instIds_T; + end + if (_GEN_27) begin + robEntries_7_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_7_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_7_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_7_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_7_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_7_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_7_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_7_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_7_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_7_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_7_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_7_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_7_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_7_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_7_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_7_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_7_cmd_bankAccess_rd_bank_0_id <= io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_7_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_7_cmd_bankAccess_rd_bank_1_id <= io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_7_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_7_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_7_cmd_isFence <= io_alloc_bits_isFence; + robEntries_7_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_7_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_7_renamedBankAccess_rd_bank_0_id <= _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_7_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_7_renamedBankAccess_rd_bank_1_id <= _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_7_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_7_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_7_rob_id <= tailPtr; + instIds_7 <= _instIds_T; + end + if (_GEN_28) begin + robEntries_8_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_8_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_8_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_8_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_8_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_8_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_8_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_8_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_8_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_8_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_8_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_8_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_8_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_8_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_8_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_8_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_8_cmd_bankAccess_rd_bank_0_id <= io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_8_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_8_cmd_bankAccess_rd_bank_1_id <= io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_8_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_8_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_8_cmd_isFence <= io_alloc_bits_isFence; + robEntries_8_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_8_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_8_renamedBankAccess_rd_bank_0_id <= _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_8_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_8_renamedBankAccess_rd_bank_1_id <= _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_8_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_8_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_8_rob_id <= tailPtr; + instIds_8 <= _instIds_T; + end + if (_GEN_29) begin + robEntries_9_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_9_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_9_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_9_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_9_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_9_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_9_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_9_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_9_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_9_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_9_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_9_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_9_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_9_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_9_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_9_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_9_cmd_bankAccess_rd_bank_0_id <= io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_9_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_9_cmd_bankAccess_rd_bank_1_id <= io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_9_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_9_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_9_cmd_isFence <= io_alloc_bits_isFence; + robEntries_9_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_9_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_9_renamedBankAccess_rd_bank_0_id <= _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_9_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_9_renamedBankAccess_rd_bank_1_id <= _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_9_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_9_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_9_rob_id <= tailPtr; + instIds_9 <= _instIds_T; + end + if (_GEN_30) begin + robEntries_10_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_10_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_10_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_10_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_10_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_10_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_10_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_10_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_10_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_10_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_10_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_10_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_10_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_10_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_10_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_10_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_10_cmd_bankAccess_rd_bank_0_id <= + io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_10_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_10_cmd_bankAccess_rd_bank_1_id <= + io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_10_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_10_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_10_cmd_isFence <= io_alloc_bits_isFence; + robEntries_10_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_10_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_10_renamedBankAccess_rd_bank_0_id <= + _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_10_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_10_renamedBankAccess_rd_bank_1_id <= + _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_10_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_10_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_10_rob_id <= tailPtr; + instIds_10 <= _instIds_T; + end + if (_GEN_31) begin + robEntries_11_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_11_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_11_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_11_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_11_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_11_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_11_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_11_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_11_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_11_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_11_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_11_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_11_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_11_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_11_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_11_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_11_cmd_bankAccess_rd_bank_0_id <= + io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_11_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_11_cmd_bankAccess_rd_bank_1_id <= + io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_11_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_11_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_11_cmd_isFence <= io_alloc_bits_isFence; + robEntries_11_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_11_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_11_renamedBankAccess_rd_bank_0_id <= + _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_11_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_11_renamedBankAccess_rd_bank_1_id <= + _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_11_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_11_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_11_rob_id <= tailPtr; + instIds_11 <= _instIds_T; + end + if (_GEN_32) begin + robEntries_12_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_12_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_12_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_12_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_12_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_12_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_12_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_12_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_12_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_12_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_12_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_12_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_12_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_12_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_12_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_12_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_12_cmd_bankAccess_rd_bank_0_id <= + io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_12_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_12_cmd_bankAccess_rd_bank_1_id <= + io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_12_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_12_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_12_cmd_isFence <= io_alloc_bits_isFence; + robEntries_12_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_12_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_12_renamedBankAccess_rd_bank_0_id <= + _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_12_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_12_renamedBankAccess_rd_bank_1_id <= + _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_12_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_12_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_12_rob_id <= tailPtr; + instIds_12 <= _instIds_T; + end + if (_GEN_33) begin + robEntries_13_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_13_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_13_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_13_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_13_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_13_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_13_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_13_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_13_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_13_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_13_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_13_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_13_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_13_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_13_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_13_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_13_cmd_bankAccess_rd_bank_0_id <= + io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_13_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_13_cmd_bankAccess_rd_bank_1_id <= + io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_13_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_13_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_13_cmd_isFence <= io_alloc_bits_isFence; + robEntries_13_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_13_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_13_renamedBankAccess_rd_bank_0_id <= + _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_13_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_13_renamedBankAccess_rd_bank_1_id <= + _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_13_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_13_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_13_rob_id <= tailPtr; + instIds_13 <= _instIds_T; + end + if (_GEN_34) begin + robEntries_14_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_14_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_14_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_14_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_14_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_14_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_14_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_14_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_14_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_14_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_14_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_14_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_14_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_14_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_14_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_14_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_14_cmd_bankAccess_rd_bank_0_id <= + io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_14_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_14_cmd_bankAccess_rd_bank_1_id <= + io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_14_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_14_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_14_cmd_isFence <= io_alloc_bits_isFence; + robEntries_14_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_14_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_14_renamedBankAccess_rd_bank_0_id <= + _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_14_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_14_renamedBankAccess_rd_bank_1_id <= + _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_14_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_14_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_14_rob_id <= tailPtr; + instIds_14 <= _instIds_T; + end + if (_GEN_35) begin + robEntries_15_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_15_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_15_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_15_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_15_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_15_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_15_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_15_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_15_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_15_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_15_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_15_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_15_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_15_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_15_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_15_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_15_cmd_bankAccess_rd_bank_0_id <= + io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_15_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_15_cmd_bankAccess_rd_bank_1_id <= + io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_15_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_15_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_15_cmd_isFence <= io_alloc_bits_isFence; + robEntries_15_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_15_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_15_renamedBankAccess_rd_bank_0_id <= + _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_15_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_15_renamedBankAccess_rd_bank_1_id <= + _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_15_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_15_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_15_rob_id <= tailPtr; + instIds_15 <= _instIds_T; + end + robValid_0 <= ~commitMask_0 & (_GEN_20 | robValid_0); + robValid_1 <= ~commitMask_1 & (_GEN_21 | robValid_1); + robValid_2 <= ~commitMask_2 & (_GEN_22 | robValid_2); + robValid_3 <= ~commitMask_3 & (_GEN_23 | robValid_3); + robValid_4 <= ~commitMask_4 & (_GEN_24 | robValid_4); + robValid_5 <= ~commitMask_5 & (_GEN_25 | robValid_5); + robValid_6 <= ~commitMask_6 & (_GEN_26 | robValid_6); + robValid_7 <= ~commitMask_7 & (_GEN_27 | robValid_7); + robValid_8 <= ~commitMask_8 & (_GEN_28 | robValid_8); + robValid_9 <= ~commitMask_9 & (_GEN_29 | robValid_9); + robValid_10 <= ~commitMask_10 & (_GEN_30 | robValid_10); + robValid_11 <= ~commitMask_11 & (_GEN_31 | robValid_11); + robValid_12 <= ~commitMask_12 & (_GEN_32 | robValid_12); + robValid_13 <= ~commitMask_13 & (_GEN_33 | robValid_13); + robValid_14 <= ~commitMask_14 & (_GEN_34 | robValid_14); + robValid_15 <= ~commitMask_15 & (_GEN_35 | robValid_15); + robIssued_0 <= + ~commitMask_0 & (issueLoad & _actualIssuePtr_T == 4'h0 | ~_GEN_20 & robIssued_0); + robIssued_1 <= + ~commitMask_1 & (issueLoad & _actualIssuePtr_T == 4'h1 | ~_GEN_21 & robIssued_1); + robIssued_2 <= + ~commitMask_2 & (issueLoad & _actualIssuePtr_T == 4'h2 | ~_GEN_22 & robIssued_2); + robIssued_3 <= + ~commitMask_3 & (issueLoad & _actualIssuePtr_T == 4'h3 | ~_GEN_23 & robIssued_3); + robIssued_4 <= + ~commitMask_4 & (issueLoad & _actualIssuePtr_T == 4'h4 | ~_GEN_24 & robIssued_4); + robIssued_5 <= + ~commitMask_5 & (issueLoad & _actualIssuePtr_T == 4'h5 | ~_GEN_25 & robIssued_5); + robIssued_6 <= + ~commitMask_6 & (issueLoad & _actualIssuePtr_T == 4'h6 | ~_GEN_26 & robIssued_6); + robIssued_7 <= + ~commitMask_7 & (issueLoad & _actualIssuePtr_T == 4'h7 | ~_GEN_27 & robIssued_7); + robIssued_8 <= + ~commitMask_8 & (issueLoad & _actualIssuePtr_T == 4'h8 | ~_GEN_28 & robIssued_8); + robIssued_9 <= + ~commitMask_9 & (issueLoad & _actualIssuePtr_T == 4'h9 | ~_GEN_29 & robIssued_9); + robIssued_10 <= + ~commitMask_10 + & (issueLoad & _actualIssuePtr_T == 4'hA | ~_GEN_30 & robIssued_10); + robIssued_11 <= + ~commitMask_11 + & (issueLoad & _actualIssuePtr_T == 4'hB | ~_GEN_31 & robIssued_11); + robIssued_12 <= + ~commitMask_12 + & (issueLoad & _actualIssuePtr_T == 4'hC | ~_GEN_32 & robIssued_12); + robIssued_13 <= + ~commitMask_13 + & (issueLoad & _actualIssuePtr_T == 4'hD | ~_GEN_33 & robIssued_13); + robIssued_14 <= + ~commitMask_14 + & (issueLoad & _actualIssuePtr_T == 4'hE | ~_GEN_34 & robIssued_14); + robIssued_15 <= + ~commitMask_15 & (issueLoad & (&_actualIssuePtr_T) | ~_GEN_35 & robIssued_15); + robComplete_0 <= + ~commitMask_0 + & (io_complete_valid & io_complete_bits == 4'h0 | ~_GEN_20 & robComplete_0); + robComplete_1 <= + ~commitMask_1 + & (io_complete_valid & io_complete_bits == 4'h1 | ~_GEN_21 & robComplete_1); + robComplete_2 <= + ~commitMask_2 + & (io_complete_valid & io_complete_bits == 4'h2 | ~_GEN_22 & robComplete_2); + robComplete_3 <= + ~commitMask_3 + & (io_complete_valid & io_complete_bits == 4'h3 | ~_GEN_23 & robComplete_3); + robComplete_4 <= + ~commitMask_4 + & (io_complete_valid & io_complete_bits == 4'h4 | ~_GEN_24 & robComplete_4); + robComplete_5 <= + ~commitMask_5 + & (io_complete_valid & io_complete_bits == 4'h5 | ~_GEN_25 & robComplete_5); + robComplete_6 <= + ~commitMask_6 + & (io_complete_valid & io_complete_bits == 4'h6 | ~_GEN_26 & robComplete_6); + robComplete_7 <= + ~commitMask_7 + & (io_complete_valid & io_complete_bits == 4'h7 | ~_GEN_27 & robComplete_7); + robComplete_8 <= + ~commitMask_8 + & (io_complete_valid & io_complete_bits == 4'h8 | ~_GEN_28 & robComplete_8); + robComplete_9 <= + ~commitMask_9 + & (io_complete_valid & io_complete_bits == 4'h9 | ~_GEN_29 & robComplete_9); + robComplete_10 <= + ~commitMask_10 + & (io_complete_valid & io_complete_bits == 4'hA | ~_GEN_30 & robComplete_10); + robComplete_11 <= + ~commitMask_11 + & (io_complete_valid & io_complete_bits == 4'hB | ~_GEN_31 & robComplete_11); + robComplete_12 <= + ~commitMask_12 + & (io_complete_valid & io_complete_bits == 4'hC | ~_GEN_32 & robComplete_12); + robComplete_13 <= + ~commitMask_13 + & (io_complete_valid & io_complete_bits == 4'hD | ~_GEN_33 & robComplete_13); + robComplete_14 <= + ~commitMask_14 + & (io_complete_valid & io_complete_bits == 4'hE | ~_GEN_34 & robComplete_14); + robComplete_15 <= + ~commitMask_15 + & (io_complete_valid & (&io_complete_bits) | ~_GEN_35 & robComplete_15); + if (_GEN_3) + nextInstId <= nextInstId + 64'h1; + ptr <= + ptr + + {1'h0, + {1'h0, {1'h0, commitKeep_1} + {1'h0, commitKeep_2}} + + {1'h0, {1'h0, commitKeep_3} + {1'h0, commitKeep_4}}} + + {1'h0, + {1'h0, {1'h0, commitKeep_5} + {1'h0, commitKeep_6}} + + {1'h0, {1'h0, commitKeep_7} + {1'h0, commitKeep_8}}} + + {1'h0, + {1'h0, {1'h0, commitKeep_9} + {1'h0, commitScan_9}} + + {1'h0, {1'h0, commitKeep_11} + {1'h0, commitKeep_12}}} + + {1'h0, + {1'h0, {1'h0, commitKeep_13} + {1'h0, commitKeep_14}} + + {1'h0, {1'h0, commitKeep_15} + {1'h0, commitScan_15}}}; + if (_isAllocatedSlot_T_30) begin + if (&tailPtr) + tailPtr <= 4'h0; + else + tailPtr <= tailPtr + 4'h1; + end + issuedCount <= + issuedCount + {4'h0, issueLoad} + - {4'h0, io_complete_valid & _GEN_4[io_complete_bits]}; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_36; + if (_GEN_67 & (&(robEntries_15_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_66; + else if (_GEN_65 & (&(robEntries_14_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_64; + else if (_GEN_63 & (&(robEntries_13_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_62; + else if (_GEN_61 & (&(robEntries_12_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_60; + else if (_GEN_59 & (&(robEntries_11_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_58; + else if (_GEN_57 & (&(robEntries_10_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_56; + else if (_GEN_55 & (&(robEntries_9_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_54; + else if (_GEN_53 & (&(robEntries_8_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_52; + else if (_GEN_51 & (&(robEntries_7_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_50; + else if (_GEN_49 & (&(robEntries_6_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_48; + else if (_GEN_47 & (&(robEntries_5_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_46; + else if (_GEN_45 & (&(robEntries_4_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_44; + else if (_GEN_43 & (&(robEntries_3_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_42; + else if (_GEN_41 & (&(robEntries_2_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_40; + else if (_GEN_39 & (&(robEntries_1_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_38; + else if (_GEN_37 & (&(robEntries_0_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_36; + if (issueLoad | io_complete_valid) + vbankBusy <= + vbankBusy & ~(io_complete_valid ? _GEN_18[io_complete_bits] : 16'h0) + | (issueLoad ? _GEN_18[_actualIssuePtr_T] : 16'h0); + if (isAllocatedSlot) + dependencyMask_0 <= allocDependencies & ~clearMask; + else + dependencyMask_0 <= dependencyMask_0 & ~clearMask; + if (isAllocatedSlot_1) + dependencyMask_1 <= allocDependencies & ~clearMask_1; + else + dependencyMask_1 <= dependencyMask_1 & ~clearMask_1; + if (isAllocatedSlot_2) + dependencyMask_2 <= allocDependencies & ~clearMask_2; + else + dependencyMask_2 <= dependencyMask_2 & ~clearMask_2; + if (isAllocatedSlot_3) + dependencyMask_3 <= allocDependencies & ~clearMask_3; + else + dependencyMask_3 <= dependencyMask_3 & ~clearMask_3; + if (isAllocatedSlot_4) + dependencyMask_4 <= allocDependencies & ~clearMask_4; + else + dependencyMask_4 <= dependencyMask_4 & ~clearMask_4; + if (isAllocatedSlot_5) + dependencyMask_5 <= allocDependencies & ~clearMask_5; + else + dependencyMask_5 <= dependencyMask_5 & ~clearMask_5; + if (isAllocatedSlot_6) + dependencyMask_6 <= allocDependencies & ~clearMask_6; + else + dependencyMask_6 <= dependencyMask_6 & ~clearMask_6; + if (isAllocatedSlot_7) + dependencyMask_7 <= allocDependencies & ~clearMask_7; + else + dependencyMask_7 <= dependencyMask_7 & ~clearMask_7; + if (isAllocatedSlot_8) + dependencyMask_8 <= allocDependencies & ~clearMask_8; + else + dependencyMask_8 <= dependencyMask_8 & ~clearMask_8; + if (isAllocatedSlot_9) + dependencyMask_9 <= allocDependencies & ~clearMask_9; + else + dependencyMask_9 <= dependencyMask_9 & ~clearMask_9; + if (isAllocatedSlot_10) + dependencyMask_10 <= allocDependencies & ~clearMask_10; + else + dependencyMask_10 <= dependencyMask_10 & ~clearMask_10; + if (isAllocatedSlot_11) + dependencyMask_11 <= allocDependencies & ~clearMask_11; + else + dependencyMask_11 <= dependencyMask_11 & ~clearMask_11; + if (isAllocatedSlot_12) + dependencyMask_12 <= allocDependencies & ~clearMask_12; + else + dependencyMask_12 <= dependencyMask_12 & ~clearMask_12; + if (isAllocatedSlot_13) + dependencyMask_13 <= allocDependencies & ~clearMask_13; + else + dependencyMask_13 <= dependencyMask_13 & ~clearMask_13; + if (isAllocatedSlot_14) + dependencyMask_14 <= allocDependencies & ~clearMask_14; + else + dependencyMask_14 <= dependencyMask_14 & ~clearMask_14; + if (isAllocatedSlot_15) + dependencyMask_15 <= allocDependencies & ~clearMask_15; + else + dependencyMask_15 <= dependencyMask_15 & ~clearMask_15; + if (issueStageReady) + issueStageValid <= issuePtrValid; + if (issuePtrReady) + issuePtrValid <= issueLoad; + end + if (issueStageReady & issuePtrFire) begin + automatic logic [15:0] _GEN_68 = + {{robEntries_15_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_14_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_13_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_12_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_11_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_10_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_9_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_8_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_7_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_6_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_5_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_4_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_3_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_2_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_1_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_0_cmd_bankAccess_rd_bank_0_valid}}; + automatic logic issuePayload_cmd_bankAccess_rd_bank_0_valid = + _GEN_68[issuePtr]; + automatic logic [15:0][9:0] _GEN_69 = + {{robEntries_15_cmd_bankAccess_rd_bank_0_id}, + {robEntries_14_cmd_bankAccess_rd_bank_0_id}, + {robEntries_13_cmd_bankAccess_rd_bank_0_id}, + {robEntries_12_cmd_bankAccess_rd_bank_0_id}, + {robEntries_11_cmd_bankAccess_rd_bank_0_id}, + {robEntries_10_cmd_bankAccess_rd_bank_0_id}, + {robEntries_9_cmd_bankAccess_rd_bank_0_id}, + {robEntries_8_cmd_bankAccess_rd_bank_0_id}, + {robEntries_7_cmd_bankAccess_rd_bank_0_id}, + {robEntries_6_cmd_bankAccess_rd_bank_0_id}, + {robEntries_5_cmd_bankAccess_rd_bank_0_id}, + {robEntries_4_cmd_bankAccess_rd_bank_0_id}, + {robEntries_3_cmd_bankAccess_rd_bank_0_id}, + {robEntries_2_cmd_bankAccess_rd_bank_0_id}, + {robEntries_1_cmd_bankAccess_rd_bank_0_id}, + {robEntries_0_cmd_bankAccess_rd_bank_0_id}}; + automatic logic [9:0] issuePayload_cmd_bankAccess_rd_bank_0_id = + _GEN_69[issuePtr]; + automatic logic [15:0] _GEN_70 = + {{robEntries_15_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_14_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_13_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_12_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_11_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_10_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_9_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_8_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_7_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_6_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_5_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_4_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_3_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_2_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_1_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_0_cmd_bankAccess_rd_bank_1_valid}}; + automatic logic issuePayload_cmd_bankAccess_rd_bank_1_valid = + _GEN_70[issuePtr]; + automatic logic [15:0][9:0] _GEN_71 = + {{robEntries_15_cmd_bankAccess_rd_bank_1_id}, + {robEntries_14_cmd_bankAccess_rd_bank_1_id}, + {robEntries_13_cmd_bankAccess_rd_bank_1_id}, + {robEntries_12_cmd_bankAccess_rd_bank_1_id}, + {robEntries_11_cmd_bankAccess_rd_bank_1_id}, + {robEntries_10_cmd_bankAccess_rd_bank_1_id}, + {robEntries_9_cmd_bankAccess_rd_bank_1_id}, + {robEntries_8_cmd_bankAccess_rd_bank_1_id}, + {robEntries_7_cmd_bankAccess_rd_bank_1_id}, + {robEntries_6_cmd_bankAccess_rd_bank_1_id}, + {robEntries_5_cmd_bankAccess_rd_bank_1_id}, + {robEntries_4_cmd_bankAccess_rd_bank_1_id}, + {robEntries_3_cmd_bankAccess_rd_bank_1_id}, + {robEntries_2_cmd_bankAccess_rd_bank_1_id}, + {robEntries_1_cmd_bankAccess_rd_bank_1_id}, + {robEntries_0_cmd_bankAccess_rd_bank_1_id}}; + automatic logic [9:0] issuePayload_cmd_bankAccess_rd_bank_1_id = + _GEN_71[issuePtr]; + automatic logic [15:0] _GEN_72 = + {{robEntries_15_cmd_bankAccess_wr_bank_valid}, + {robEntries_14_cmd_bankAccess_wr_bank_valid}, + {robEntries_13_cmd_bankAccess_wr_bank_valid}, + {robEntries_12_cmd_bankAccess_wr_bank_valid}, + {robEntries_11_cmd_bankAccess_wr_bank_valid}, + {robEntries_10_cmd_bankAccess_wr_bank_valid}, + {robEntries_9_cmd_bankAccess_wr_bank_valid}, + {robEntries_8_cmd_bankAccess_wr_bank_valid}, + {robEntries_7_cmd_bankAccess_wr_bank_valid}, + {robEntries_6_cmd_bankAccess_wr_bank_valid}, + {robEntries_5_cmd_bankAccess_wr_bank_valid}, + {robEntries_4_cmd_bankAccess_wr_bank_valid}, + {robEntries_3_cmd_bankAccess_wr_bank_valid}, + {robEntries_2_cmd_bankAccess_wr_bank_valid}, + {robEntries_1_cmd_bankAccess_wr_bank_valid}, + {robEntries_0_cmd_bankAccess_wr_bank_valid}}; + automatic logic issuePayload_cmd_bankAccess_wr_bank_valid = + _GEN_72[issuePtr]; + automatic logic [15:0][9:0] _GEN_73 = + {{robEntries_15_cmd_bankAccess_wr_bank_id}, + {robEntries_14_cmd_bankAccess_wr_bank_id}, + {robEntries_13_cmd_bankAccess_wr_bank_id}, + {robEntries_12_cmd_bankAccess_wr_bank_id}, + {robEntries_11_cmd_bankAccess_wr_bank_id}, + {robEntries_10_cmd_bankAccess_wr_bank_id}, + {robEntries_9_cmd_bankAccess_wr_bank_id}, + {robEntries_8_cmd_bankAccess_wr_bank_id}, + {robEntries_7_cmd_bankAccess_wr_bank_id}, + {robEntries_6_cmd_bankAccess_wr_bank_id}, + {robEntries_5_cmd_bankAccess_wr_bank_id}, + {robEntries_4_cmd_bankAccess_wr_bank_id}, + {robEntries_3_cmd_bankAccess_wr_bank_id}, + {robEntries_2_cmd_bankAccess_wr_bank_id}, + {robEntries_1_cmd_bankAccess_wr_bank_id}, + {robEntries_0_cmd_bankAccess_wr_bank_id}}; + automatic logic [9:0] issuePayload_cmd_bankAccess_wr_bank_id = + _GEN_73[issuePtr]; + automatic logic [15:0][3:0] _GEN_74 = + {{bankCols_15}, + {bankCols_14}, + {bankCols_13}, + {bankCols_12}, + {bankCols_11}, + {bankCols_10}, + {bankCols_9}, + {bankCols_8}, + {bankCols_7}, + {bankCols_6}, + {bankCols_5}, + {bankCols_4}, + {bankCols_3}, + {bankCols_2}, + {bankCols_1}, + {bankCols_0}}; + automatic logic [15:0][4:0] _GEN_75 = + {{robEntries_15_cmd_ball_bid}, + {robEntries_14_cmd_ball_bid}, + {robEntries_13_cmd_ball_bid}, + {robEntries_12_cmd_ball_bid}, + {robEntries_11_cmd_ball_bid}, + {robEntries_10_cmd_ball_bid}, + {robEntries_9_cmd_ball_bid}, + {robEntries_8_cmd_ball_bid}, + {robEntries_7_cmd_ball_bid}, + {robEntries_6_cmd_ball_bid}, + {robEntries_5_cmd_ball_bid}, + {robEntries_4_cmd_ball_bid}, + {robEntries_3_cmd_ball_bid}, + {robEntries_2_cmd_ball_bid}, + {robEntries_1_cmd_ball_bid}, + {robEntries_0_cmd_ball_bid}}; + automatic logic [15:0][31:0] _GEN_76 = + {{robEntries_15_cmd_cmd_raw_inst}, + {robEntries_14_cmd_cmd_raw_inst}, + {robEntries_13_cmd_cmd_raw_inst}, + {robEntries_12_cmd_cmd_raw_inst}, + {robEntries_11_cmd_cmd_raw_inst}, + {robEntries_10_cmd_cmd_raw_inst}, + {robEntries_9_cmd_cmd_raw_inst}, + {robEntries_8_cmd_cmd_raw_inst}, + {robEntries_7_cmd_cmd_raw_inst}, + {robEntries_6_cmd_cmd_raw_inst}, + {robEntries_5_cmd_cmd_raw_inst}, + {robEntries_4_cmd_cmd_raw_inst}, + {robEntries_3_cmd_cmd_raw_inst}, + {robEntries_2_cmd_cmd_raw_inst}, + {robEntries_1_cmd_cmd_raw_inst}, + {robEntries_0_cmd_cmd_raw_inst}}; + automatic logic [15:0][2:0] _GEN_77 = + {{robEntries_15_cmd_cmd_funct3}, + {robEntries_14_cmd_cmd_funct3}, + {robEntries_13_cmd_cmd_funct3}, + {robEntries_12_cmd_cmd_funct3}, + {robEntries_11_cmd_cmd_funct3}, + {robEntries_10_cmd_cmd_funct3}, + {robEntries_9_cmd_cmd_funct3}, + {robEntries_8_cmd_cmd_funct3}, + {robEntries_7_cmd_cmd_funct3}, + {robEntries_6_cmd_cmd_funct3}, + {robEntries_5_cmd_cmd_funct3}, + {robEntries_4_cmd_cmd_funct3}, + {robEntries_3_cmd_cmd_funct3}, + {robEntries_2_cmd_cmd_funct3}, + {robEntries_1_cmd_cmd_funct3}, + {robEntries_0_cmd_cmd_funct3}}; + automatic logic [15:0][4:0] _GEN_78 = + {{robEntries_15_cmd_cmd_rs2}, + {robEntries_14_cmd_cmd_rs2}, + {robEntries_13_cmd_cmd_rs2}, + {robEntries_12_cmd_cmd_rs2}, + {robEntries_11_cmd_cmd_rs2}, + {robEntries_10_cmd_cmd_rs2}, + {robEntries_9_cmd_cmd_rs2}, + {robEntries_8_cmd_cmd_rs2}, + {robEntries_7_cmd_cmd_rs2}, + {robEntries_6_cmd_cmd_rs2}, + {robEntries_5_cmd_cmd_rs2}, + {robEntries_4_cmd_cmd_rs2}, + {robEntries_3_cmd_cmd_rs2}, + {robEntries_2_cmd_cmd_rs2}, + {robEntries_1_cmd_cmd_rs2}, + {robEntries_0_cmd_cmd_rs2}}; + automatic logic [15:0][4:0] _GEN_79 = + {{robEntries_15_cmd_cmd_rs1}, + {robEntries_14_cmd_cmd_rs1}, + {robEntries_13_cmd_cmd_rs1}, + {robEntries_12_cmd_cmd_rs1}, + {robEntries_11_cmd_cmd_rs1}, + {robEntries_10_cmd_cmd_rs1}, + {robEntries_9_cmd_cmd_rs1}, + {robEntries_8_cmd_cmd_rs1}, + {robEntries_7_cmd_cmd_rs1}, + {robEntries_6_cmd_cmd_rs1}, + {robEntries_5_cmd_cmd_rs1}, + {robEntries_4_cmd_cmd_rs1}, + {robEntries_3_cmd_cmd_rs1}, + {robEntries_2_cmd_cmd_rs1}, + {robEntries_1_cmd_cmd_rs1}, + {robEntries_0_cmd_cmd_rs1}}; + automatic logic [15:0] _GEN_80 = + {{robEntries_15_cmd_cmd_xd}, + {robEntries_14_cmd_cmd_xd}, + {robEntries_13_cmd_cmd_xd}, + {robEntries_12_cmd_cmd_xd}, + {robEntries_11_cmd_cmd_xd}, + {robEntries_10_cmd_cmd_xd}, + {robEntries_9_cmd_cmd_xd}, + {robEntries_8_cmd_cmd_xd}, + {robEntries_7_cmd_cmd_xd}, + {robEntries_6_cmd_cmd_xd}, + {robEntries_5_cmd_cmd_xd}, + {robEntries_4_cmd_cmd_xd}, + {robEntries_3_cmd_cmd_xd}, + {robEntries_2_cmd_cmd_xd}, + {robEntries_1_cmd_cmd_xd}, + {robEntries_0_cmd_cmd_xd}}; + automatic logic [15:0] _GEN_81 = + {{robEntries_15_cmd_cmd_xs1}, + {robEntries_14_cmd_cmd_xs1}, + {robEntries_13_cmd_cmd_xs1}, + {robEntries_12_cmd_cmd_xs1}, + {robEntries_11_cmd_cmd_xs1}, + {robEntries_10_cmd_cmd_xs1}, + {robEntries_9_cmd_cmd_xs1}, + {robEntries_8_cmd_cmd_xs1}, + {robEntries_7_cmd_cmd_xs1}, + {robEntries_6_cmd_cmd_xs1}, + {robEntries_5_cmd_cmd_xs1}, + {robEntries_4_cmd_cmd_xs1}, + {robEntries_3_cmd_cmd_xs1}, + {robEntries_2_cmd_cmd_xs1}, + {robEntries_1_cmd_cmd_xs1}, + {robEntries_0_cmd_cmd_xs1}}; + automatic logic [15:0] _GEN_82 = + {{robEntries_15_cmd_cmd_xs2}, + {robEntries_14_cmd_cmd_xs2}, + {robEntries_13_cmd_cmd_xs2}, + {robEntries_12_cmd_cmd_xs2}, + {robEntries_11_cmd_cmd_xs2}, + {robEntries_10_cmd_cmd_xs2}, + {robEntries_9_cmd_cmd_xs2}, + {robEntries_8_cmd_cmd_xs2}, + {robEntries_7_cmd_cmd_xs2}, + {robEntries_6_cmd_cmd_xs2}, + {robEntries_5_cmd_cmd_xs2}, + {robEntries_4_cmd_cmd_xs2}, + {robEntries_3_cmd_cmd_xs2}, + {robEntries_2_cmd_cmd_xs2}, + {robEntries_1_cmd_cmd_xs2}, + {robEntries_0_cmd_cmd_xs2}}; + automatic logic [15:0][4:0] _GEN_83 = + {{robEntries_15_cmd_cmd_rd}, + {robEntries_14_cmd_cmd_rd}, + {robEntries_13_cmd_cmd_rd}, + {robEntries_12_cmd_cmd_rd}, + {robEntries_11_cmd_cmd_rd}, + {robEntries_10_cmd_cmd_rd}, + {robEntries_9_cmd_cmd_rd}, + {robEntries_8_cmd_cmd_rd}, + {robEntries_7_cmd_cmd_rd}, + {robEntries_6_cmd_cmd_rd}, + {robEntries_5_cmd_cmd_rd}, + {robEntries_4_cmd_cmd_rd}, + {robEntries_3_cmd_cmd_rd}, + {robEntries_2_cmd_cmd_rd}, + {robEntries_1_cmd_cmd_rd}, + {robEntries_0_cmd_cmd_rd}}; + automatic logic [15:0][6:0] _GEN_84 = + {{robEntries_15_cmd_cmd_opcode}, + {robEntries_14_cmd_cmd_opcode}, + {robEntries_13_cmd_cmd_opcode}, + {robEntries_12_cmd_cmd_opcode}, + {robEntries_11_cmd_cmd_opcode}, + {robEntries_10_cmd_cmd_opcode}, + {robEntries_9_cmd_cmd_opcode}, + {robEntries_8_cmd_cmd_opcode}, + {robEntries_7_cmd_cmd_opcode}, + {robEntries_6_cmd_cmd_opcode}, + {robEntries_5_cmd_cmd_opcode}, + {robEntries_4_cmd_cmd_opcode}, + {robEntries_3_cmd_cmd_opcode}, + {robEntries_2_cmd_cmd_opcode}, + {robEntries_1_cmd_cmd_opcode}, + {robEntries_0_cmd_cmd_opcode}}; + automatic logic [15:0] _GEN_85 = + {{robEntries_15_cmd_isFence}, + {robEntries_14_cmd_isFence}, + {robEntries_13_cmd_isFence}, + {robEntries_12_cmd_isFence}, + {robEntries_11_cmd_isFence}, + {robEntries_10_cmd_isFence}, + {robEntries_9_cmd_isFence}, + {robEntries_8_cmd_isFence}, + {robEntries_7_cmd_isFence}, + {robEntries_6_cmd_isFence}, + {robEntries_5_cmd_isFence}, + {robEntries_4_cmd_isFence}, + {robEntries_3_cmd_isFence}, + {robEntries_2_cmd_isFence}, + {robEntries_1_cmd_isFence}, + {robEntries_0_cmd_isFence}}; + automatic logic [15:0] _GEN_86 = + {{robEntries_15_cmd_isBarrier}, + {robEntries_14_cmd_isBarrier}, + {robEntries_13_cmd_isBarrier}, + {robEntries_12_cmd_isBarrier}, + {robEntries_11_cmd_isBarrier}, + {robEntries_10_cmd_isBarrier}, + {robEntries_9_cmd_isBarrier}, + {robEntries_8_cmd_isBarrier}, + {robEntries_7_cmd_isBarrier}, + {robEntries_6_cmd_isBarrier}, + {robEntries_5_cmd_isBarrier}, + {robEntries_4_cmd_isBarrier}, + {robEntries_3_cmd_isBarrier}, + {robEntries_2_cmd_isBarrier}, + {robEntries_1_cmd_isBarrier}, + {robEntries_0_cmd_isBarrier}}; + issueStageEntry_cmd_domain_id <= _GEN_5[issuePtr]; + issueStageEntry_cmd_ball_bid <= _GEN_75[issuePtr]; + issueStageEntry_cmd_cmd_raw_inst <= _GEN_76[issuePtr]; + issueStageEntry_cmd_cmd_pc <= _GEN_6[issuePtr]; + issueStageEntry_cmd_cmd_funct <= _GEN_7[issuePtr]; + issueStageEntry_cmd_cmd_funct3 <= _GEN_77[issuePtr]; + issueStageEntry_cmd_cmd_rs2 <= _GEN_78[issuePtr]; + issueStageEntry_cmd_cmd_rs1 <= _GEN_79[issuePtr]; + issueStageEntry_cmd_cmd_xd <= _GEN_80[issuePtr]; + issueStageEntry_cmd_cmd_xs1 <= _GEN_81[issuePtr]; + issueStageEntry_cmd_cmd_xs2 <= _GEN_82[issuePtr]; + issueStageEntry_cmd_cmd_rd <= _GEN_83[issuePtr]; + issueStageEntry_cmd_cmd_opcode <= _GEN_84[issuePtr]; + issueStageEntry_cmd_cmd_rs1Data <= _robOperands_ext_R0_data[127:64]; + issueStageEntry_cmd_cmd_rs2Data <= _robOperands_ext_R0_data[63:0]; + issueStageEntry_cmd_bankAccess_rd_bank_0_valid <= + issuePayload_cmd_bankAccess_rd_bank_0_valid; + issueStageEntry_cmd_bankAccess_rd_bank_0_id <= + issuePayload_cmd_bankAccess_rd_bank_0_id; + issueStageEntry_cmd_bankAccess_rd_bank_1_valid <= + issuePayload_cmd_bankAccess_rd_bank_1_valid; + issueStageEntry_cmd_bankAccess_rd_bank_1_id <= + issuePayload_cmd_bankAccess_rd_bank_1_id; + issueStageEntry_cmd_bankAccess_wr_bank_valid <= + issuePayload_cmd_bankAccess_wr_bank_valid; + issueStageEntry_cmd_bankAccess_wr_bank_id <= issuePayload_cmd_bankAccess_wr_bank_id; + issueStageEntry_cmd_op1_col <= + issuePayload_cmd_bankAccess_rd_bank_0_valid + ? _GEN_74[issuePayload_cmd_bankAccess_rd_bank_0_id[3:0]] + : 4'h0; + issueStageEntry_cmd_op2_col <= + issuePayload_cmd_bankAccess_rd_bank_1_valid + ? _GEN_74[issuePayload_cmd_bankAccess_rd_bank_1_id[3:0]] + : 4'h0; + issueStageEntry_cmd_wr_col <= + issuePayload_cmd_bankAccess_wr_bank_valid + ? _GEN_74[issuePayload_cmd_bankAccess_wr_bank_id[3:0]] + : 4'h0; + issueStageEntry_cmd_isFence <= _GEN_85[issuePtr]; + issueStageEntry_cmd_isBarrier <= _GEN_86[issuePtr]; + issueStageEntry_renamedBankAccess_rd_bank_0_valid <= _GEN_13[issuePtr]; + issueStageEntry_renamedBankAccess_rd_bank_0_id <= _GEN_14[issuePtr]; + issueStageEntry_renamedBankAccess_rd_bank_1_valid <= _GEN_15[issuePtr]; + issueStageEntry_renamedBankAccess_rd_bank_1_id <= _GEN_16[issuePtr]; + issueStageEntry_renamedBankAccess_wr_bank_valid <= _GEN_10[issuePtr]; + issueStageEntry_renamedBankAccess_wr_bank_id <= _GEN_11[issuePtr]; + issueStageEntry_rob_id <= _GEN_19[issuePtr]; + end + if (issuePtrReady & issueLoad) + issuePtr <= _actualIssuePtr_T; + end // always @(posedge) + BankAliasTable bat ( + .clock (clock), + .reset (reset), + .io_alloc_valid (_isAllocatedSlot_T_30), + .io_alloc_rob_id (tailPtr), + .io_alloc_raw_rd_bank_0_valid (io_alloc_bits_bankAccess_rd_bank_0_valid), + .io_alloc_raw_rd_bank_0_id (io_alloc_bits_bankAccess_rd_bank_0_id), + .io_alloc_raw_rd_bank_1_valid (io_alloc_bits_bankAccess_rd_bank_1_valid), + .io_alloc_raw_rd_bank_1_id (io_alloc_bits_bankAccess_rd_bank_1_id), + .io_alloc_raw_wr_bank_valid (io_alloc_bits_bankAccess_wr_bank_valid), + .io_alloc_raw_wr_bank_id (io_alloc_bits_bankAccess_wr_bank_id), + .io_alloc_renamed_rd_bank_0_valid (_bat_io_alloc_renamed_rd_bank_0_valid), + .io_alloc_renamed_rd_bank_0_id (_bat_io_alloc_renamed_rd_bank_0_id), + .io_alloc_renamed_rd_bank_1_valid (_bat_io_alloc_renamed_rd_bank_1_valid), + .io_alloc_renamed_rd_bank_1_id (_bat_io_alloc_renamed_rd_bank_1_id), + .io_alloc_renamed_wr_bank_valid (_bat_io_alloc_renamed_wr_bank_valid), + .io_alloc_renamed_wr_bank_id (_bat_io_alloc_renamed_wr_bank_id), + .io_free_valid + (|{commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0}), + .io_free_mask_0 (commitMask_0), + .io_free_mask_1 (commitMask_1), + .io_free_mask_2 (commitMask_2), + .io_free_mask_3 (commitMask_3), + .io_free_mask_4 (commitMask_4), + .io_free_mask_5 (commitMask_5), + .io_free_mask_6 (commitMask_6), + .io_free_mask_7 (commitMask_7), + .io_free_mask_8 (commitMask_8), + .io_free_mask_9 (commitMask_9), + .io_free_mask_10 (commitMask_10), + .io_free_mask_11 (commitMask_11), + .io_free_mask_12 (commitMask_12), + .io_free_mask_13 (commitMask_13), + .io_free_mask_14 (commitMask_14), + .io_free_mask_15 (commitMask_15) + ); + BankScoreboard scoreboard ( + .clock (clock), + .reset (reset), + .alloc_valid + (_isAllocatedSlot_T_30 & io_alloc_bits_bankAccess_wr_bank_valid), + .alloc_bits_wr_bank_valid (_bat_io_alloc_renamed_wr_bank_valid), + .alloc_bits_wr_bank_id (_bat_io_alloc_renamed_wr_bank_id), + .complete_valid (io_complete_valid), + .complete_bits_wr_bank_valid (io_complete_valid & _GEN_10[io_complete_bits]), + .complete_bits_wr_bank_id (io_complete_valid ? _GEN_11[io_complete_bits] : 10'h0), + .queryVec_0_rd_bank_0_valid (_GEN_13[ptr]), + .queryVec_0_rd_bank_0_id (_GEN_14[ptr]), + .queryVec_0_rd_bank_1_valid (_GEN_15[ptr]), + .queryVec_0_rd_bank_1_id (_GEN_16[ptr]), + .queryVec_1_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1446]), + .queryVec_1_rd_bank_0_id (_GEN_14[_hits_ptr_T_1446]), + .queryVec_1_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1446]), + .queryVec_1_rd_bank_1_id (_GEN_16[_hits_ptr_T_1446]), + .queryVec_2_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1452]), + .queryVec_2_rd_bank_0_id (_GEN_14[_hits_ptr_T_1452]), + .queryVec_2_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1452]), + .queryVec_2_rd_bank_1_id (_GEN_16[_hits_ptr_T_1452]), + .queryVec_3_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1458]), + .queryVec_3_rd_bank_0_id (_GEN_14[_hits_ptr_T_1458]), + .queryVec_3_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1458]), + .queryVec_3_rd_bank_1_id (_GEN_16[_hits_ptr_T_1458]), + .queryVec_4_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1464]), + .queryVec_4_rd_bank_0_id (_GEN_14[_hits_ptr_T_1464]), + .queryVec_4_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1464]), + .queryVec_4_rd_bank_1_id (_GEN_16[_hits_ptr_T_1464]), + .queryVec_5_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1470]), + .queryVec_5_rd_bank_0_id (_GEN_14[_hits_ptr_T_1470]), + .queryVec_5_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1470]), + .queryVec_5_rd_bank_1_id (_GEN_16[_hits_ptr_T_1470]), + .queryVec_6_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1476]), + .queryVec_6_rd_bank_0_id (_GEN_14[_hits_ptr_T_1476]), + .queryVec_6_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1476]), + .queryVec_6_rd_bank_1_id (_GEN_16[_hits_ptr_T_1476]), + .queryVec_7_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1482]), + .queryVec_7_rd_bank_0_id (_GEN_14[_hits_ptr_T_1482]), + .queryVec_7_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1482]), + .queryVec_7_rd_bank_1_id (_GEN_16[_hits_ptr_T_1482]), + .queryVec_8_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1488]), + .queryVec_8_rd_bank_0_id (_GEN_14[_hits_ptr_T_1488]), + .queryVec_8_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1488]), + .queryVec_8_rd_bank_1_id (_GEN_16[_hits_ptr_T_1488]), + .queryVec_9_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1494]), + .queryVec_9_rd_bank_0_id (_GEN_14[_hits_ptr_T_1494]), + .queryVec_9_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1494]), + .queryVec_9_rd_bank_1_id (_GEN_16[_hits_ptr_T_1494]), + .queryVec_10_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1500]), + .queryVec_10_rd_bank_0_id (_GEN_14[_hits_ptr_T_1500]), + .queryVec_10_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1500]), + .queryVec_10_rd_bank_1_id (_GEN_16[_hits_ptr_T_1500]), + .queryVec_11_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1506]), + .queryVec_11_rd_bank_0_id (_GEN_14[_hits_ptr_T_1506]), + .queryVec_11_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1506]), + .queryVec_11_rd_bank_1_id (_GEN_16[_hits_ptr_T_1506]), + .queryVec_12_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1512]), + .queryVec_12_rd_bank_0_id (_GEN_14[_hits_ptr_T_1512]), + .queryVec_12_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1512]), + .queryVec_12_rd_bank_1_id (_GEN_16[_hits_ptr_T_1512]), + .queryVec_13_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1518]), + .queryVec_13_rd_bank_0_id (_GEN_14[_hits_ptr_T_1518]), + .queryVec_13_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1518]), + .queryVec_13_rd_bank_1_id (_GEN_16[_hits_ptr_T_1518]), + .queryVec_14_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1524]), + .queryVec_14_rd_bank_0_id (_GEN_14[_hits_ptr_T_1524]), + .queryVec_14_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1524]), + .queryVec_14_rd_bank_1_id (_GEN_16[_hits_ptr_T_1524]), + .queryVec_15_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1530]), + .queryVec_15_rd_bank_0_id (_GEN_14[_hits_ptr_T_1530]), + .queryVec_15_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1530]), + .queryVec_15_rd_bank_1_id (_GEN_16[_hits_ptr_T_1530]), + .hazardVec_0 (_scoreboard_hazardVec_0), + .hazardVec_1 (_scoreboard_hazardVec_1), + .hazardVec_2 (_scoreboard_hazardVec_2), + .hazardVec_3 (_scoreboard_hazardVec_3), + .hazardVec_4 (_scoreboard_hazardVec_4), + .hazardVec_5 (_scoreboard_hazardVec_5), + .hazardVec_6 (_scoreboard_hazardVec_6), + .hazardVec_7 (_scoreboard_hazardVec_7), + .hazardVec_8 (_scoreboard_hazardVec_8), + .hazardVec_9 (_scoreboard_hazardVec_9), + .hazardVec_10 (_scoreboard_hazardVec_10), + .hazardVec_11 (_scoreboard_hazardVec_11), + .hazardVec_12 (_scoreboard_hazardVec_12), + .hazardVec_13 (_scoreboard_hazardVec_13), + .hazardVec_14 (_scoreboard_hazardVec_14), + .hazardVec_15 (_scoreboard_hazardVec_15) + ); + ITraceDPI itraceAlloc ( + .clock (clock), + .reset (reset), + .is_issue ({6'h0, _isAllocatedSlot_T_30, 1'h0}), + .hart_id (64'h0), + .rob_id (_isAllocatedSlot_T_30 ? {28'h0, tailPtr} : 32'h0), + .inst_id (_GEN_3 ? nextInstId : 64'h0), + .domain_id (_isAllocatedSlot_T_30 ? {28'h0, io_alloc_bits_domain_id} : 32'h0), + .funct (_isAllocatedSlot_T_30 ? {25'h0, io_alloc_bits_cmd_funct} : 32'h0), + .pc (_isAllocatedSlot_T_30 ? io_alloc_bits_cmd_pc : 64'h0), + .rs1_data (_isAllocatedSlot_T_30 ? io_alloc_bits_cmd_rs1Data : 64'h0), + .rs2_data (_isAllocatedSlot_T_30 ? io_alloc_bits_cmd_rs2Data : 64'h0), + .enable (_isAllocatedSlot_T_30) + ); + ITraceDPI itraceIssue ( + .clock (clock), + .reset (reset), + .is_issue ({7'h0, issueLoad}), + .hart_id (64'h0), + .rob_id (issueLoad ? {28'h0, _GEN_19[_actualIssuePtr_T]} : 32'h0), + .inst_id (issueLoad ? _GEN_12[_actualIssuePtr_T] : 64'h0), + .domain_id (issueLoad ? {28'h0, _GEN_5[_actualIssuePtr_T]} : 32'h0), + .funct (issueLoad ? {25'h0, _GEN_7[_actualIssuePtr_T]} : 32'h0), + .pc (issueLoad ? _GEN_6[_actualIssuePtr_T] : 64'h0), + .rs1_data (issueLoad ? _GEN_8[_actualIssuePtr_T] : 64'h0), + .rs2_data (issueLoad ? _GEN_9[_actualIssuePtr_T] : 64'h0), + .enable (issueLoad) + ); + ITraceDPI itraceComp ( + .clock (clock), + .reset (reset), + .is_issue (8'h0), + .hart_id (64'h0), + .rob_id (io_complete_valid ? {28'h0, io_complete_bits} : 32'h0), + .inst_id (io_complete_valid ? _GEN_12[io_complete_bits] : 64'h0), + .domain_id (io_complete_valid ? {28'h0, _GEN_5[io_complete_bits]} : 32'h0), + .funct (io_complete_valid ? {25'h0, _GEN_7[io_complete_bits]} : 32'h0), + .pc (io_complete_valid ? _GEN_6[io_complete_bits] : 64'h0), + .rs1_data (io_complete_valid ? _GEN_8[io_complete_bits] : 64'h0), + .rs2_data (io_complete_valid ? _GEN_9[io_complete_bits] : 64'h0), + .enable (io_complete_valid) + ); + robOperands_16x128 robOperands_ext ( + .R0_addr (readAddress), + .R0_en (readEnable), + .R0_clk (clock), + .R0_data (_robOperands_ext_R0_data), + .W0_addr (tailPtr), + .W0_en (_isAllocatedSlot_T_30), + .W0_clk (clock), + .W0_data ({io_alloc_bits_cmd_rs1Data, io_alloc_bits_cmd_rs2Data}) + ); + assign io_alloc_ready = io_alloc_ready_0; + assign io_issue_valid = issueStageValid & ~io_subRobActive; + assign io_issue_bits_cmd_domain_id = issueStageEntry_cmd_domain_id; + assign io_issue_bits_cmd_ball_bid = issueStageEntry_cmd_ball_bid; + assign io_issue_bits_cmd_cmd_raw_inst = issueStageEntry_cmd_cmd_raw_inst; + assign io_issue_bits_cmd_cmd_pc = issueStageEntry_cmd_cmd_pc; + assign io_issue_bits_cmd_cmd_funct = issueStageEntry_cmd_cmd_funct; + assign io_issue_bits_cmd_cmd_funct3 = issueStageEntry_cmd_cmd_funct3; + assign io_issue_bits_cmd_cmd_rs2 = issueStageEntry_cmd_cmd_rs2; + assign io_issue_bits_cmd_cmd_rs1 = issueStageEntry_cmd_cmd_rs1; + assign io_issue_bits_cmd_cmd_xd = issueStageEntry_cmd_cmd_xd; + assign io_issue_bits_cmd_cmd_xs1 = issueStageEntry_cmd_cmd_xs1; + assign io_issue_bits_cmd_cmd_xs2 = issueStageEntry_cmd_cmd_xs2; + assign io_issue_bits_cmd_cmd_rd = issueStageEntry_cmd_cmd_rd; + assign io_issue_bits_cmd_cmd_opcode = issueStageEntry_cmd_cmd_opcode; + assign io_issue_bits_cmd_cmd_rs1Data = issueStageEntry_cmd_cmd_rs1Data; + assign io_issue_bits_cmd_cmd_rs2Data = issueStageEntry_cmd_cmd_rs2Data; + assign io_issue_bits_cmd_bankAccess_rd_bank_0_valid = + issueStageEntry_cmd_bankAccess_rd_bank_0_valid; + assign io_issue_bits_cmd_bankAccess_rd_bank_0_id = + issueStageEntry_cmd_bankAccess_rd_bank_0_id; + assign io_issue_bits_cmd_bankAccess_rd_bank_1_valid = + issueStageEntry_cmd_bankAccess_rd_bank_1_valid; + assign io_issue_bits_cmd_bankAccess_rd_bank_1_id = + issueStageEntry_cmd_bankAccess_rd_bank_1_id; + assign io_issue_bits_cmd_bankAccess_wr_bank_valid = + issueStageEntry_cmd_bankAccess_wr_bank_valid; + assign io_issue_bits_cmd_bankAccess_wr_bank_id = + issueStageEntry_cmd_bankAccess_wr_bank_id; + assign io_issue_bits_cmd_op1_col = issueStageEntry_cmd_op1_col; + assign io_issue_bits_cmd_op2_col = issueStageEntry_cmd_op2_col; + assign io_issue_bits_cmd_wr_col = issueStageEntry_cmd_wr_col; + assign io_issue_bits_cmd_isFence = issueStageEntry_cmd_isFence; + assign io_issue_bits_cmd_isBarrier = issueStageEntry_cmd_isBarrier; + assign io_issue_bits_renamedBankAccess_rd_bank_0_valid = + issueStageEntry_renamedBankAccess_rd_bank_0_valid; + assign io_issue_bits_renamedBankAccess_rd_bank_0_id = + issueStageEntry_renamedBankAccess_rd_bank_0_id; + assign io_issue_bits_renamedBankAccess_rd_bank_1_valid = + issueStageEntry_renamedBankAccess_rd_bank_1_valid; + assign io_issue_bits_renamedBankAccess_rd_bank_1_id = + issueStageEntry_renamedBankAccess_rd_bank_1_id; + assign io_issue_bits_renamedBankAccess_wr_bank_valid = + issueStageEntry_renamedBankAccess_wr_bank_valid; + assign io_issue_bits_renamedBankAccess_wr_bank_id = + issueStageEntry_renamedBankAccess_wr_bank_id; + assign io_issue_bits_rob_id = issueStageEntry_rob_id; + assign io_empty = _isFull_T & ~_GEN_0; + assign io_full = isFull; + assign io_head_ptr = ptr; + assign io_issued_count = issuedCount; + assign io_entry_valid_0 = robValid_0; + assign io_entry_valid_1 = robValid_1; + assign io_entry_valid_2 = robValid_2; + assign io_entry_valid_3 = robValid_3; + assign io_entry_valid_4 = robValid_4; + assign io_entry_valid_5 = robValid_5; + assign io_entry_valid_6 = robValid_6; + assign io_entry_valid_7 = robValid_7; + assign io_entry_valid_8 = robValid_8; + assign io_entry_valid_9 = robValid_9; + assign io_entry_valid_10 = robValid_10; + assign io_entry_valid_11 = robValid_11; + assign io_entry_valid_12 = robValid_12; + assign io_entry_valid_13 = robValid_13; + assign io_entry_valid_14 = robValid_14; + assign io_entry_valid_15 = robValid_15; + assign io_entry_complete_0 = robComplete_0; + assign io_entry_complete_1 = robComplete_1; + assign io_entry_complete_2 = robComplete_2; + assign io_entry_complete_3 = robComplete_3; + assign io_entry_complete_4 = robComplete_4; + assign io_entry_complete_5 = robComplete_5; + assign io_entry_complete_6 = robComplete_6; + assign io_entry_complete_7 = robComplete_7; + assign io_entry_complete_8 = robComplete_8; + assign io_entry_complete_9 = robComplete_9; + assign io_entry_complete_10 = robComplete_10; + assign io_entry_complete_11 = robComplete_11; + assign io_entry_complete_12 = robComplete_12; + assign io_entry_complete_13 = robComplete_13; + assign io_entry_complete_14 = robComplete_14; + assign io_entry_complete_15 = robComplete_15; + assign io_inst_ids_0 = instIds_0; + assign io_inst_ids_1 = instIds_1; + assign io_inst_ids_2 = instIds_2; + assign io_inst_ids_3 = instIds_3; + assign io_inst_ids_4 = instIds_4; + assign io_inst_ids_5 = instIds_5; + assign io_inst_ids_6 = instIds_6; + assign io_inst_ids_7 = instIds_7; + assign io_inst_ids_8 = instIds_8; + assign io_inst_ids_9 = instIds_9; + assign io_inst_ids_10 = instIds_10; + assign io_inst_ids_11 = instIds_11; + assign io_inst_ids_12 = instIds_12; + assign io_inst_ids_13 = instIds_13; + assign io_inst_ids_14 = instIds_14; + assign io_inst_ids_15 = instIds_15; +endmodule + +module GlobalROB_1( + input clock, + reset, + output io_alloc_ready, + input io_alloc_valid, + input [3:0] io_alloc_bits_domain_id, + input [4:0] io_alloc_bits_ball_bid, + input [31:0] io_alloc_bits_cmd_raw_inst, + input [63:0] io_alloc_bits_cmd_pc, + input [6:0] io_alloc_bits_cmd_funct, + input [2:0] io_alloc_bits_cmd_funct3, + input [4:0] io_alloc_bits_cmd_rs2, + io_alloc_bits_cmd_rs1, + input io_alloc_bits_cmd_xd, + io_alloc_bits_cmd_xs1, + io_alloc_bits_cmd_xs2, + input [4:0] io_alloc_bits_cmd_rd, + input [6:0] io_alloc_bits_cmd_opcode, + input [63:0] io_alloc_bits_cmd_rs1Data, + io_alloc_bits_cmd_rs2Data, + input io_alloc_bits_bankAccess_rd_bank_0_valid, + input [9:0] io_alloc_bits_bankAccess_rd_bank_0_id, + input io_alloc_bits_bankAccess_rd_bank_1_valid, + input [9:0] io_alloc_bits_bankAccess_rd_bank_1_id, + input io_alloc_bits_bankAccess_wr_bank_valid, + input [9:0] io_alloc_bits_bankAccess_wr_bank_id, + input io_alloc_bits_isFence, + io_alloc_bits_isBarrier, + io_issue_ready, + output io_issue_valid, + output [3:0] io_issue_bits_cmd_domain_id, + output [4:0] io_issue_bits_cmd_ball_bid, + output [31:0] io_issue_bits_cmd_cmd_raw_inst, + output [63:0] io_issue_bits_cmd_cmd_pc, + output [6:0] io_issue_bits_cmd_cmd_funct, + output [2:0] io_issue_bits_cmd_cmd_funct3, + output [4:0] io_issue_bits_cmd_cmd_rs2, + io_issue_bits_cmd_cmd_rs1, + output io_issue_bits_cmd_cmd_xd, + io_issue_bits_cmd_cmd_xs1, + io_issue_bits_cmd_cmd_xs2, + output [4:0] io_issue_bits_cmd_cmd_rd, + output [6:0] io_issue_bits_cmd_cmd_opcode, + output [63:0] io_issue_bits_cmd_cmd_rs1Data, + io_issue_bits_cmd_cmd_rs2Data, + output io_issue_bits_cmd_bankAccess_rd_bank_0_valid, + output [9:0] io_issue_bits_cmd_bankAccess_rd_bank_0_id, + output io_issue_bits_cmd_bankAccess_rd_bank_1_valid, + output [9:0] io_issue_bits_cmd_bankAccess_rd_bank_1_id, + output io_issue_bits_cmd_bankAccess_wr_bank_valid, + output [9:0] io_issue_bits_cmd_bankAccess_wr_bank_id, + output [3:0] io_issue_bits_cmd_op1_col, + io_issue_bits_cmd_op2_col, + io_issue_bits_cmd_wr_col, + output io_issue_bits_cmd_isFence, + io_issue_bits_cmd_isBarrier, + io_issue_bits_renamedBankAccess_rd_bank_0_valid, + output [9:0] io_issue_bits_renamedBankAccess_rd_bank_0_id, + output io_issue_bits_renamedBankAccess_rd_bank_1_valid, + output [9:0] io_issue_bits_renamedBankAccess_rd_bank_1_id, + output io_issue_bits_renamedBankAccess_wr_bank_valid, + output [9:0] io_issue_bits_renamedBankAccess_wr_bank_id, + output [3:0] io_issue_bits_rob_id, + input io_complete_valid, + input [3:0] io_complete_bits, + output io_empty, + io_full, + output [3:0] io_head_ptr, + output [4:0] io_issued_count, + output io_entry_valid_0, + io_entry_valid_1, + io_entry_valid_2, + io_entry_valid_3, + io_entry_valid_4, + io_entry_valid_5, + io_entry_valid_6, + io_entry_valid_7, + io_entry_valid_8, + io_entry_valid_9, + io_entry_valid_10, + io_entry_valid_11, + io_entry_valid_12, + io_entry_valid_13, + io_entry_valid_14, + io_entry_valid_15, + io_entry_complete_0, + io_entry_complete_1, + io_entry_complete_2, + io_entry_complete_3, + io_entry_complete_4, + io_entry_complete_5, + io_entry_complete_6, + io_entry_complete_7, + io_entry_complete_8, + io_entry_complete_9, + io_entry_complete_10, + io_entry_complete_11, + io_entry_complete_12, + io_entry_complete_13, + io_entry_complete_14, + io_entry_complete_15, + input io_subRobActive, + output [63:0] io_inst_ids_0, + io_inst_ids_1, + io_inst_ids_2, + io_inst_ids_3, + io_inst_ids_4, + io_inst_ids_5, + io_inst_ids_6, + io_inst_ids_7, + io_inst_ids_8, + io_inst_ids_9, + io_inst_ids_10, + io_inst_ids_11, + io_inst_ids_12, + io_inst_ids_13, + io_inst_ids_14, + io_inst_ids_15 +); + + wire commitMask_15; + wire commitMask_14; + wire commitMask_13; + wire commitMask_12; + wire commitMask_11; + wire commitMask_10; + wire commitMask_9; + wire commitMask_8; + wire commitMask_7; + wire commitMask_6; + wire commitMask_5; + wire commitMask_4; + wire commitMask_3; + wire commitMask_2; + wire commitMask_1; + wire commitMask_0; + wire _scoreboard_hazardVec_0; + wire _scoreboard_hazardVec_1; + wire _scoreboard_hazardVec_2; + wire _scoreboard_hazardVec_3; + wire _scoreboard_hazardVec_4; + wire _scoreboard_hazardVec_5; + wire _scoreboard_hazardVec_6; + wire _scoreboard_hazardVec_7; + wire _scoreboard_hazardVec_8; + wire _scoreboard_hazardVec_9; + wire _scoreboard_hazardVec_10; + wire _scoreboard_hazardVec_11; + wire _scoreboard_hazardVec_12; + wire _scoreboard_hazardVec_13; + wire _scoreboard_hazardVec_14; + wire _scoreboard_hazardVec_15; + wire _bat_io_alloc_renamed_rd_bank_0_valid; + wire [9:0] _bat_io_alloc_renamed_rd_bank_0_id; + wire _bat_io_alloc_renamed_rd_bank_1_valid; + wire [9:0] _bat_io_alloc_renamed_rd_bank_1_id; + wire _bat_io_alloc_renamed_wr_bank_valid; + wire [9:0] _bat_io_alloc_renamed_wr_bank_id; + reg [3:0] robEntries_0_cmd_domain_id; + reg [4:0] robEntries_0_cmd_ball_bid; + reg [31:0] robEntries_0_cmd_cmd_raw_inst; + reg [63:0] robEntries_0_cmd_cmd_pc; + reg [6:0] robEntries_0_cmd_cmd_funct; + reg [2:0] robEntries_0_cmd_cmd_funct3; + reg [4:0] robEntries_0_cmd_cmd_rs2; + reg [4:0] robEntries_0_cmd_cmd_rs1; + reg robEntries_0_cmd_cmd_xd; + reg robEntries_0_cmd_cmd_xs1; + reg robEntries_0_cmd_cmd_xs2; + reg [4:0] robEntries_0_cmd_cmd_rd; + reg [6:0] robEntries_0_cmd_cmd_opcode; + reg [63:0] robEntries_0_cmd_cmd_rs1Data; + reg [63:0] robEntries_0_cmd_cmd_rs2Data; + reg robEntries_0_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_0_cmd_bankAccess_rd_bank_0_id; + reg robEntries_0_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_0_cmd_bankAccess_rd_bank_1_id; + reg robEntries_0_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_0_cmd_bankAccess_wr_bank_id; + reg robEntries_0_cmd_isFence; + reg robEntries_0_cmd_isBarrier; + reg robEntries_0_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_0_renamedBankAccess_rd_bank_0_id; + reg robEntries_0_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_0_renamedBankAccess_rd_bank_1_id; + reg robEntries_0_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_0_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_0_rob_id; + reg [3:0] robEntries_1_cmd_domain_id; + reg [4:0] robEntries_1_cmd_ball_bid; + reg [31:0] robEntries_1_cmd_cmd_raw_inst; + reg [63:0] robEntries_1_cmd_cmd_pc; + reg [6:0] robEntries_1_cmd_cmd_funct; + reg [2:0] robEntries_1_cmd_cmd_funct3; + reg [4:0] robEntries_1_cmd_cmd_rs2; + reg [4:0] robEntries_1_cmd_cmd_rs1; + reg robEntries_1_cmd_cmd_xd; + reg robEntries_1_cmd_cmd_xs1; + reg robEntries_1_cmd_cmd_xs2; + reg [4:0] robEntries_1_cmd_cmd_rd; + reg [6:0] robEntries_1_cmd_cmd_opcode; + reg [63:0] robEntries_1_cmd_cmd_rs1Data; + reg [63:0] robEntries_1_cmd_cmd_rs2Data; + reg robEntries_1_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_1_cmd_bankAccess_rd_bank_0_id; + reg robEntries_1_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_1_cmd_bankAccess_rd_bank_1_id; + reg robEntries_1_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_1_cmd_bankAccess_wr_bank_id; + reg robEntries_1_cmd_isFence; + reg robEntries_1_cmd_isBarrier; + reg robEntries_1_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_1_renamedBankAccess_rd_bank_0_id; + reg robEntries_1_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_1_renamedBankAccess_rd_bank_1_id; + reg robEntries_1_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_1_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_1_rob_id; + reg [3:0] robEntries_2_cmd_domain_id; + reg [4:0] robEntries_2_cmd_ball_bid; + reg [31:0] robEntries_2_cmd_cmd_raw_inst; + reg [63:0] robEntries_2_cmd_cmd_pc; + reg [6:0] robEntries_2_cmd_cmd_funct; + reg [2:0] robEntries_2_cmd_cmd_funct3; + reg [4:0] robEntries_2_cmd_cmd_rs2; + reg [4:0] robEntries_2_cmd_cmd_rs1; + reg robEntries_2_cmd_cmd_xd; + reg robEntries_2_cmd_cmd_xs1; + reg robEntries_2_cmd_cmd_xs2; + reg [4:0] robEntries_2_cmd_cmd_rd; + reg [6:0] robEntries_2_cmd_cmd_opcode; + reg [63:0] robEntries_2_cmd_cmd_rs1Data; + reg [63:0] robEntries_2_cmd_cmd_rs2Data; + reg robEntries_2_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_2_cmd_bankAccess_rd_bank_0_id; + reg robEntries_2_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_2_cmd_bankAccess_rd_bank_1_id; + reg robEntries_2_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_2_cmd_bankAccess_wr_bank_id; + reg robEntries_2_cmd_isFence; + reg robEntries_2_cmd_isBarrier; + reg robEntries_2_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_2_renamedBankAccess_rd_bank_0_id; + reg robEntries_2_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_2_renamedBankAccess_rd_bank_1_id; + reg robEntries_2_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_2_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_2_rob_id; + reg [3:0] robEntries_3_cmd_domain_id; + reg [4:0] robEntries_3_cmd_ball_bid; + reg [31:0] robEntries_3_cmd_cmd_raw_inst; + reg [63:0] robEntries_3_cmd_cmd_pc; + reg [6:0] robEntries_3_cmd_cmd_funct; + reg [2:0] robEntries_3_cmd_cmd_funct3; + reg [4:0] robEntries_3_cmd_cmd_rs2; + reg [4:0] robEntries_3_cmd_cmd_rs1; + reg robEntries_3_cmd_cmd_xd; + reg robEntries_3_cmd_cmd_xs1; + reg robEntries_3_cmd_cmd_xs2; + reg [4:0] robEntries_3_cmd_cmd_rd; + reg [6:0] robEntries_3_cmd_cmd_opcode; + reg [63:0] robEntries_3_cmd_cmd_rs1Data; + reg [63:0] robEntries_3_cmd_cmd_rs2Data; + reg robEntries_3_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_3_cmd_bankAccess_rd_bank_0_id; + reg robEntries_3_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_3_cmd_bankAccess_rd_bank_1_id; + reg robEntries_3_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_3_cmd_bankAccess_wr_bank_id; + reg robEntries_3_cmd_isFence; + reg robEntries_3_cmd_isBarrier; + reg robEntries_3_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_3_renamedBankAccess_rd_bank_0_id; + reg robEntries_3_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_3_renamedBankAccess_rd_bank_1_id; + reg robEntries_3_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_3_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_3_rob_id; + reg [3:0] robEntries_4_cmd_domain_id; + reg [4:0] robEntries_4_cmd_ball_bid; + reg [31:0] robEntries_4_cmd_cmd_raw_inst; + reg [63:0] robEntries_4_cmd_cmd_pc; + reg [6:0] robEntries_4_cmd_cmd_funct; + reg [2:0] robEntries_4_cmd_cmd_funct3; + reg [4:0] robEntries_4_cmd_cmd_rs2; + reg [4:0] robEntries_4_cmd_cmd_rs1; + reg robEntries_4_cmd_cmd_xd; + reg robEntries_4_cmd_cmd_xs1; + reg robEntries_4_cmd_cmd_xs2; + reg [4:0] robEntries_4_cmd_cmd_rd; + reg [6:0] robEntries_4_cmd_cmd_opcode; + reg [63:0] robEntries_4_cmd_cmd_rs1Data; + reg [63:0] robEntries_4_cmd_cmd_rs2Data; + reg robEntries_4_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_4_cmd_bankAccess_rd_bank_0_id; + reg robEntries_4_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_4_cmd_bankAccess_rd_bank_1_id; + reg robEntries_4_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_4_cmd_bankAccess_wr_bank_id; + reg robEntries_4_cmd_isFence; + reg robEntries_4_cmd_isBarrier; + reg robEntries_4_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_4_renamedBankAccess_rd_bank_0_id; + reg robEntries_4_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_4_renamedBankAccess_rd_bank_1_id; + reg robEntries_4_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_4_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_4_rob_id; + reg [3:0] robEntries_5_cmd_domain_id; + reg [4:0] robEntries_5_cmd_ball_bid; + reg [31:0] robEntries_5_cmd_cmd_raw_inst; + reg [63:0] robEntries_5_cmd_cmd_pc; + reg [6:0] robEntries_5_cmd_cmd_funct; + reg [2:0] robEntries_5_cmd_cmd_funct3; + reg [4:0] robEntries_5_cmd_cmd_rs2; + reg [4:0] robEntries_5_cmd_cmd_rs1; + reg robEntries_5_cmd_cmd_xd; + reg robEntries_5_cmd_cmd_xs1; + reg robEntries_5_cmd_cmd_xs2; + reg [4:0] robEntries_5_cmd_cmd_rd; + reg [6:0] robEntries_5_cmd_cmd_opcode; + reg [63:0] robEntries_5_cmd_cmd_rs1Data; + reg [63:0] robEntries_5_cmd_cmd_rs2Data; + reg robEntries_5_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_5_cmd_bankAccess_rd_bank_0_id; + reg robEntries_5_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_5_cmd_bankAccess_rd_bank_1_id; + reg robEntries_5_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_5_cmd_bankAccess_wr_bank_id; + reg robEntries_5_cmd_isFence; + reg robEntries_5_cmd_isBarrier; + reg robEntries_5_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_5_renamedBankAccess_rd_bank_0_id; + reg robEntries_5_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_5_renamedBankAccess_rd_bank_1_id; + reg robEntries_5_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_5_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_5_rob_id; + reg [3:0] robEntries_6_cmd_domain_id; + reg [4:0] robEntries_6_cmd_ball_bid; + reg [31:0] robEntries_6_cmd_cmd_raw_inst; + reg [63:0] robEntries_6_cmd_cmd_pc; + reg [6:0] robEntries_6_cmd_cmd_funct; + reg [2:0] robEntries_6_cmd_cmd_funct3; + reg [4:0] robEntries_6_cmd_cmd_rs2; + reg [4:0] robEntries_6_cmd_cmd_rs1; + reg robEntries_6_cmd_cmd_xd; + reg robEntries_6_cmd_cmd_xs1; + reg robEntries_6_cmd_cmd_xs2; + reg [4:0] robEntries_6_cmd_cmd_rd; + reg [6:0] robEntries_6_cmd_cmd_opcode; + reg [63:0] robEntries_6_cmd_cmd_rs1Data; + reg [63:0] robEntries_6_cmd_cmd_rs2Data; + reg robEntries_6_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_6_cmd_bankAccess_rd_bank_0_id; + reg robEntries_6_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_6_cmd_bankAccess_rd_bank_1_id; + reg robEntries_6_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_6_cmd_bankAccess_wr_bank_id; + reg robEntries_6_cmd_isFence; + reg robEntries_6_cmd_isBarrier; + reg robEntries_6_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_6_renamedBankAccess_rd_bank_0_id; + reg robEntries_6_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_6_renamedBankAccess_rd_bank_1_id; + reg robEntries_6_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_6_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_6_rob_id; + reg [3:0] robEntries_7_cmd_domain_id; + reg [4:0] robEntries_7_cmd_ball_bid; + reg [31:0] robEntries_7_cmd_cmd_raw_inst; + reg [63:0] robEntries_7_cmd_cmd_pc; + reg [6:0] robEntries_7_cmd_cmd_funct; + reg [2:0] robEntries_7_cmd_cmd_funct3; + reg [4:0] robEntries_7_cmd_cmd_rs2; + reg [4:0] robEntries_7_cmd_cmd_rs1; + reg robEntries_7_cmd_cmd_xd; + reg robEntries_7_cmd_cmd_xs1; + reg robEntries_7_cmd_cmd_xs2; + reg [4:0] robEntries_7_cmd_cmd_rd; + reg [6:0] robEntries_7_cmd_cmd_opcode; + reg [63:0] robEntries_7_cmd_cmd_rs1Data; + reg [63:0] robEntries_7_cmd_cmd_rs2Data; + reg robEntries_7_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_7_cmd_bankAccess_rd_bank_0_id; + reg robEntries_7_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_7_cmd_bankAccess_rd_bank_1_id; + reg robEntries_7_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_7_cmd_bankAccess_wr_bank_id; + reg robEntries_7_cmd_isFence; + reg robEntries_7_cmd_isBarrier; + reg robEntries_7_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_7_renamedBankAccess_rd_bank_0_id; + reg robEntries_7_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_7_renamedBankAccess_rd_bank_1_id; + reg robEntries_7_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_7_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_7_rob_id; + reg [3:0] robEntries_8_cmd_domain_id; + reg [4:0] robEntries_8_cmd_ball_bid; + reg [31:0] robEntries_8_cmd_cmd_raw_inst; + reg [63:0] robEntries_8_cmd_cmd_pc; + reg [6:0] robEntries_8_cmd_cmd_funct; + reg [2:0] robEntries_8_cmd_cmd_funct3; + reg [4:0] robEntries_8_cmd_cmd_rs2; + reg [4:0] robEntries_8_cmd_cmd_rs1; + reg robEntries_8_cmd_cmd_xd; + reg robEntries_8_cmd_cmd_xs1; + reg robEntries_8_cmd_cmd_xs2; + reg [4:0] robEntries_8_cmd_cmd_rd; + reg [6:0] robEntries_8_cmd_cmd_opcode; + reg [63:0] robEntries_8_cmd_cmd_rs1Data; + reg [63:0] robEntries_8_cmd_cmd_rs2Data; + reg robEntries_8_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_8_cmd_bankAccess_rd_bank_0_id; + reg robEntries_8_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_8_cmd_bankAccess_rd_bank_1_id; + reg robEntries_8_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_8_cmd_bankAccess_wr_bank_id; + reg robEntries_8_cmd_isFence; + reg robEntries_8_cmd_isBarrier; + reg robEntries_8_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_8_renamedBankAccess_rd_bank_0_id; + reg robEntries_8_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_8_renamedBankAccess_rd_bank_1_id; + reg robEntries_8_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_8_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_8_rob_id; + reg [3:0] robEntries_9_cmd_domain_id; + reg [4:0] robEntries_9_cmd_ball_bid; + reg [31:0] robEntries_9_cmd_cmd_raw_inst; + reg [63:0] robEntries_9_cmd_cmd_pc; + reg [6:0] robEntries_9_cmd_cmd_funct; + reg [2:0] robEntries_9_cmd_cmd_funct3; + reg [4:0] robEntries_9_cmd_cmd_rs2; + reg [4:0] robEntries_9_cmd_cmd_rs1; + reg robEntries_9_cmd_cmd_xd; + reg robEntries_9_cmd_cmd_xs1; + reg robEntries_9_cmd_cmd_xs2; + reg [4:0] robEntries_9_cmd_cmd_rd; + reg [6:0] robEntries_9_cmd_cmd_opcode; + reg [63:0] robEntries_9_cmd_cmd_rs1Data; + reg [63:0] robEntries_9_cmd_cmd_rs2Data; + reg robEntries_9_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_9_cmd_bankAccess_rd_bank_0_id; + reg robEntries_9_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_9_cmd_bankAccess_rd_bank_1_id; + reg robEntries_9_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_9_cmd_bankAccess_wr_bank_id; + reg robEntries_9_cmd_isFence; + reg robEntries_9_cmd_isBarrier; + reg robEntries_9_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_9_renamedBankAccess_rd_bank_0_id; + reg robEntries_9_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_9_renamedBankAccess_rd_bank_1_id; + reg robEntries_9_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_9_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_9_rob_id; + reg [3:0] robEntries_10_cmd_domain_id; + reg [4:0] robEntries_10_cmd_ball_bid; + reg [31:0] robEntries_10_cmd_cmd_raw_inst; + reg [63:0] robEntries_10_cmd_cmd_pc; + reg [6:0] robEntries_10_cmd_cmd_funct; + reg [2:0] robEntries_10_cmd_cmd_funct3; + reg [4:0] robEntries_10_cmd_cmd_rs2; + reg [4:0] robEntries_10_cmd_cmd_rs1; + reg robEntries_10_cmd_cmd_xd; + reg robEntries_10_cmd_cmd_xs1; + reg robEntries_10_cmd_cmd_xs2; + reg [4:0] robEntries_10_cmd_cmd_rd; + reg [6:0] robEntries_10_cmd_cmd_opcode; + reg [63:0] robEntries_10_cmd_cmd_rs1Data; + reg [63:0] robEntries_10_cmd_cmd_rs2Data; + reg robEntries_10_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_10_cmd_bankAccess_rd_bank_0_id; + reg robEntries_10_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_10_cmd_bankAccess_rd_bank_1_id; + reg robEntries_10_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_10_cmd_bankAccess_wr_bank_id; + reg robEntries_10_cmd_isFence; + reg robEntries_10_cmd_isBarrier; + reg robEntries_10_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_10_renamedBankAccess_rd_bank_0_id; + reg robEntries_10_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_10_renamedBankAccess_rd_bank_1_id; + reg robEntries_10_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_10_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_10_rob_id; + reg [3:0] robEntries_11_cmd_domain_id; + reg [4:0] robEntries_11_cmd_ball_bid; + reg [31:0] robEntries_11_cmd_cmd_raw_inst; + reg [63:0] robEntries_11_cmd_cmd_pc; + reg [6:0] robEntries_11_cmd_cmd_funct; + reg [2:0] robEntries_11_cmd_cmd_funct3; + reg [4:0] robEntries_11_cmd_cmd_rs2; + reg [4:0] robEntries_11_cmd_cmd_rs1; + reg robEntries_11_cmd_cmd_xd; + reg robEntries_11_cmd_cmd_xs1; + reg robEntries_11_cmd_cmd_xs2; + reg [4:0] robEntries_11_cmd_cmd_rd; + reg [6:0] robEntries_11_cmd_cmd_opcode; + reg [63:0] robEntries_11_cmd_cmd_rs1Data; + reg [63:0] robEntries_11_cmd_cmd_rs2Data; + reg robEntries_11_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_11_cmd_bankAccess_rd_bank_0_id; + reg robEntries_11_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_11_cmd_bankAccess_rd_bank_1_id; + reg robEntries_11_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_11_cmd_bankAccess_wr_bank_id; + reg robEntries_11_cmd_isFence; + reg robEntries_11_cmd_isBarrier; + reg robEntries_11_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_11_renamedBankAccess_rd_bank_0_id; + reg robEntries_11_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_11_renamedBankAccess_rd_bank_1_id; + reg robEntries_11_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_11_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_11_rob_id; + reg [3:0] robEntries_12_cmd_domain_id; + reg [4:0] robEntries_12_cmd_ball_bid; + reg [31:0] robEntries_12_cmd_cmd_raw_inst; + reg [63:0] robEntries_12_cmd_cmd_pc; + reg [6:0] robEntries_12_cmd_cmd_funct; + reg [2:0] robEntries_12_cmd_cmd_funct3; + reg [4:0] robEntries_12_cmd_cmd_rs2; + reg [4:0] robEntries_12_cmd_cmd_rs1; + reg robEntries_12_cmd_cmd_xd; + reg robEntries_12_cmd_cmd_xs1; + reg robEntries_12_cmd_cmd_xs2; + reg [4:0] robEntries_12_cmd_cmd_rd; + reg [6:0] robEntries_12_cmd_cmd_opcode; + reg [63:0] robEntries_12_cmd_cmd_rs1Data; + reg [63:0] robEntries_12_cmd_cmd_rs2Data; + reg robEntries_12_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_12_cmd_bankAccess_rd_bank_0_id; + reg robEntries_12_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_12_cmd_bankAccess_rd_bank_1_id; + reg robEntries_12_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_12_cmd_bankAccess_wr_bank_id; + reg robEntries_12_cmd_isFence; + reg robEntries_12_cmd_isBarrier; + reg robEntries_12_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_12_renamedBankAccess_rd_bank_0_id; + reg robEntries_12_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_12_renamedBankAccess_rd_bank_1_id; + reg robEntries_12_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_12_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_12_rob_id; + reg [3:0] robEntries_13_cmd_domain_id; + reg [4:0] robEntries_13_cmd_ball_bid; + reg [31:0] robEntries_13_cmd_cmd_raw_inst; + reg [63:0] robEntries_13_cmd_cmd_pc; + reg [6:0] robEntries_13_cmd_cmd_funct; + reg [2:0] robEntries_13_cmd_cmd_funct3; + reg [4:0] robEntries_13_cmd_cmd_rs2; + reg [4:0] robEntries_13_cmd_cmd_rs1; + reg robEntries_13_cmd_cmd_xd; + reg robEntries_13_cmd_cmd_xs1; + reg robEntries_13_cmd_cmd_xs2; + reg [4:0] robEntries_13_cmd_cmd_rd; + reg [6:0] robEntries_13_cmd_cmd_opcode; + reg [63:0] robEntries_13_cmd_cmd_rs1Data; + reg [63:0] robEntries_13_cmd_cmd_rs2Data; + reg robEntries_13_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_13_cmd_bankAccess_rd_bank_0_id; + reg robEntries_13_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_13_cmd_bankAccess_rd_bank_1_id; + reg robEntries_13_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_13_cmd_bankAccess_wr_bank_id; + reg robEntries_13_cmd_isFence; + reg robEntries_13_cmd_isBarrier; + reg robEntries_13_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_13_renamedBankAccess_rd_bank_0_id; + reg robEntries_13_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_13_renamedBankAccess_rd_bank_1_id; + reg robEntries_13_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_13_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_13_rob_id; + reg [3:0] robEntries_14_cmd_domain_id; + reg [4:0] robEntries_14_cmd_ball_bid; + reg [31:0] robEntries_14_cmd_cmd_raw_inst; + reg [63:0] robEntries_14_cmd_cmd_pc; + reg [6:0] robEntries_14_cmd_cmd_funct; + reg [2:0] robEntries_14_cmd_cmd_funct3; + reg [4:0] robEntries_14_cmd_cmd_rs2; + reg [4:0] robEntries_14_cmd_cmd_rs1; + reg robEntries_14_cmd_cmd_xd; + reg robEntries_14_cmd_cmd_xs1; + reg robEntries_14_cmd_cmd_xs2; + reg [4:0] robEntries_14_cmd_cmd_rd; + reg [6:0] robEntries_14_cmd_cmd_opcode; + reg [63:0] robEntries_14_cmd_cmd_rs1Data; + reg [63:0] robEntries_14_cmd_cmd_rs2Data; + reg robEntries_14_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_14_cmd_bankAccess_rd_bank_0_id; + reg robEntries_14_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_14_cmd_bankAccess_rd_bank_1_id; + reg robEntries_14_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_14_cmd_bankAccess_wr_bank_id; + reg robEntries_14_cmd_isFence; + reg robEntries_14_cmd_isBarrier; + reg robEntries_14_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_14_renamedBankAccess_rd_bank_0_id; + reg robEntries_14_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_14_renamedBankAccess_rd_bank_1_id; + reg robEntries_14_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_14_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_14_rob_id; + reg [3:0] robEntries_15_cmd_domain_id; + reg [4:0] robEntries_15_cmd_ball_bid; + reg [31:0] robEntries_15_cmd_cmd_raw_inst; + reg [63:0] robEntries_15_cmd_cmd_pc; + reg [6:0] robEntries_15_cmd_cmd_funct; + reg [2:0] robEntries_15_cmd_cmd_funct3; + reg [4:0] robEntries_15_cmd_cmd_rs2; + reg [4:0] robEntries_15_cmd_cmd_rs1; + reg robEntries_15_cmd_cmd_xd; + reg robEntries_15_cmd_cmd_xs1; + reg robEntries_15_cmd_cmd_xs2; + reg [4:0] robEntries_15_cmd_cmd_rd; + reg [6:0] robEntries_15_cmd_cmd_opcode; + reg [63:0] robEntries_15_cmd_cmd_rs1Data; + reg [63:0] robEntries_15_cmd_cmd_rs2Data; + reg robEntries_15_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] robEntries_15_cmd_bankAccess_rd_bank_0_id; + reg robEntries_15_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] robEntries_15_cmd_bankAccess_rd_bank_1_id; + reg robEntries_15_cmd_bankAccess_wr_bank_valid; + reg [9:0] robEntries_15_cmd_bankAccess_wr_bank_id; + reg robEntries_15_cmd_isFence; + reg robEntries_15_cmd_isBarrier; + reg robEntries_15_renamedBankAccess_rd_bank_0_valid; + reg [9:0] robEntries_15_renamedBankAccess_rd_bank_0_id; + reg robEntries_15_renamedBankAccess_rd_bank_1_valid; + reg [9:0] robEntries_15_renamedBankAccess_rd_bank_1_id; + reg robEntries_15_renamedBankAccess_wr_bank_valid; + reg [9:0] robEntries_15_renamedBankAccess_wr_bank_id; + reg [3:0] robEntries_15_rob_id; + reg robValid_0; + reg robValid_1; + reg robValid_2; + reg robValid_3; + reg robValid_4; + reg robValid_5; + reg robValid_6; + reg robValid_7; + reg robValid_8; + reg robValid_9; + reg robValid_10; + reg robValid_11; + reg robValid_12; + reg robValid_13; + reg robValid_14; + reg robValid_15; + reg robIssued_0; + reg robIssued_1; + reg robIssued_2; + reg robIssued_3; + reg robIssued_4; + reg robIssued_5; + reg robIssued_6; + reg robIssued_7; + reg robIssued_8; + reg robIssued_9; + reg robIssued_10; + reg robIssued_11; + reg robIssued_12; + reg robIssued_13; + reg robIssued_14; + reg robIssued_15; + reg robComplete_0; + reg robComplete_1; + reg robComplete_2; + reg robComplete_3; + reg robComplete_4; + reg robComplete_5; + reg robComplete_6; + reg robComplete_7; + reg robComplete_8; + reg robComplete_9; + reg robComplete_10; + reg robComplete_11; + reg robComplete_12; + reg robComplete_13; + reg robComplete_14; + reg robComplete_15; + reg [63:0] instIds_0; + reg [63:0] instIds_1; + reg [63:0] instIds_2; + reg [63:0] instIds_3; + reg [63:0] instIds_4; + reg [63:0] instIds_5; + reg [63:0] instIds_6; + reg [63:0] instIds_7; + reg [63:0] instIds_8; + reg [63:0] instIds_9; + reg [63:0] instIds_10; + reg [63:0] instIds_11; + reg [63:0] instIds_12; + reg [63:0] instIds_13; + reg [63:0] instIds_14; + reg [63:0] instIds_15; + reg [63:0] nextInstId; + reg [3:0] ptr; + reg [3:0] tailPtr; + reg [4:0] issuedCount; + reg [3:0] bankCols_0; + reg [3:0] bankCols_1; + reg [3:0] bankCols_2; + reg [3:0] bankCols_3; + reg [3:0] bankCols_4; + reg [3:0] bankCols_5; + reg [3:0] bankCols_6; + reg [3:0] bankCols_7; + reg [3:0] bankCols_8; + reg [3:0] bankCols_9; + reg [3:0] bankCols_10; + reg [3:0] bankCols_11; + reg [3:0] bankCols_12; + reg [3:0] bankCols_13; + reg [3:0] bankCols_14; + reg [3:0] bankCols_15; + reg [15:0] vbankBusy; + reg [15:0] dependencyMask_0; + reg [15:0] dependencyMask_1; + reg [15:0] dependencyMask_2; + reg [15:0] dependencyMask_3; + reg [15:0] dependencyMask_4; + reg [15:0] dependencyMask_5; + reg [15:0] dependencyMask_6; + reg [15:0] dependencyMask_7; + reg [15:0] dependencyMask_8; + reg [15:0] dependencyMask_9; + reg [15:0] dependencyMask_10; + reg [15:0] dependencyMask_11; + reg [15:0] dependencyMask_12; + reg [15:0] dependencyMask_13; + reg [15:0] dependencyMask_14; + reg [15:0] dependencyMask_15; + wire _isFull_T = ptr == tailPtr; + wire [15:0] _GEN = + {{robValid_15}, + {robValid_14}, + {robValid_13}, + {robValid_12}, + {robValid_11}, + {robValid_10}, + {robValid_9}, + {robValid_8}, + {robValid_7}, + {robValid_6}, + {robValid_5}, + {robValid_4}, + {robValid_3}, + {robValid_2}, + {robValid_1}, + {robValid_0}}; + wire _GEN_0 = _GEN[ptr]; + wire isFull = _isFull_T & _GEN_0; + wire [15:0] _GEN_1 = + {{robComplete_15}, + {robComplete_14}, + {robComplete_13}, + {robComplete_12}, + {robComplete_11}, + {robComplete_10}, + {robComplete_9}, + {robComplete_8}, + {robComplete_7}, + {robComplete_6}, + {robComplete_5}, + {robComplete_4}, + {robComplete_3}, + {robComplete_2}, + {robComplete_1}, + {robComplete_0}}; + wire _GEN_2 = _GEN_1[ptr]; + wire commitKeep_1 = _GEN_0 & _GEN_2; + wire [3:0] _hits_ptr_T_1446 = ptr + 4'h1; + wire commitKeep_2 = + commitKeep_1 & _GEN[_hits_ptr_T_1446] & _GEN_1[_hits_ptr_T_1446]; + wire [3:0] _hits_ptr_T_1452 = ptr + 4'h2; + wire commitKeep_3 = + commitKeep_2 & _GEN[_hits_ptr_T_1452] & _GEN_1[_hits_ptr_T_1452]; + wire [3:0] _hits_ptr_T_1458 = ptr + 4'h3; + wire commitKeep_4 = + commitKeep_3 & _GEN[_hits_ptr_T_1458] & _GEN_1[_hits_ptr_T_1458]; + wire [3:0] _hits_ptr_T_1464 = ptr + 4'h4; + wire commitKeep_5 = + commitKeep_4 & _GEN[_hits_ptr_T_1464] & _GEN_1[_hits_ptr_T_1464]; + wire [3:0] _hits_ptr_T_1470 = ptr + 4'h5; + wire commitKeep_6 = + commitKeep_5 & _GEN[_hits_ptr_T_1470] & _GEN_1[_hits_ptr_T_1470]; + wire [3:0] _hits_ptr_T_1476 = ptr + 4'h6; + wire commitKeep_7 = + commitKeep_6 & _GEN[_hits_ptr_T_1476] & _GEN_1[_hits_ptr_T_1476]; + wire [3:0] _hits_ptr_T_1482 = ptr + 4'h7; + wire commitKeep_8 = + commitKeep_7 & _GEN[_hits_ptr_T_1482] & _GEN_1[_hits_ptr_T_1482]; + wire [3:0] _hits_ptr_T_1488 = ptr - 4'h8; + wire commitKeep_9 = + commitKeep_8 & _GEN[_hits_ptr_T_1488] & _GEN_1[_hits_ptr_T_1488]; + wire [3:0] _hits_ptr_T_1494 = ptr - 4'h7; + wire commitScan_9 = + commitKeep_9 & _GEN[_hits_ptr_T_1494] & _GEN_1[_hits_ptr_T_1494]; + wire [3:0] _hits_ptr_T_1500 = ptr - 4'h6; + wire commitKeep_11 = + commitScan_9 & _GEN[_hits_ptr_T_1500] & _GEN_1[_hits_ptr_T_1500]; + wire [3:0] _hits_ptr_T_1506 = ptr - 4'h5; + wire commitKeep_12 = + commitKeep_11 & _GEN[_hits_ptr_T_1506] & _GEN_1[_hits_ptr_T_1506]; + wire [3:0] _hits_ptr_T_1512 = ptr - 4'h4; + wire commitKeep_13 = + commitKeep_12 & _GEN[_hits_ptr_T_1512] & _GEN_1[_hits_ptr_T_1512]; + wire [3:0] _hits_ptr_T_1518 = ptr - 4'h3; + wire commitKeep_14 = + commitKeep_13 & _GEN[_hits_ptr_T_1518] & _GEN_1[_hits_ptr_T_1518]; + wire [3:0] _hits_ptr_T_1524 = ptr - 4'h2; + wire commitKeep_15 = + commitKeep_14 & _GEN[_hits_ptr_T_1524] & _GEN_1[_hits_ptr_T_1524]; + wire [3:0] _hits_ptr_T_1530 = ptr - 4'h1; + wire commitScan_15 = + commitKeep_15 & _GEN[_hits_ptr_T_1530] & _GEN_1[_hits_ptr_T_1530]; + wire [9:0] _tailAlias_T = {6'h0, tailPtr} + 10'h10; + wire io_alloc_ready_0 = + ~isFull + & {commitScan_15, + commitKeep_15, + commitKeep_14, + commitKeep_13, + commitKeep_12, + commitKeep_11, + commitScan_9, + commitKeep_9, + commitKeep_8, + commitKeep_7, + commitKeep_6, + commitKeep_5, + commitKeep_4, + commitKeep_3, + commitKeep_2, + commitKeep_1} == 16'h0 + & ~(robValid_15 & ~robComplete_15 + & (robEntries_15_renamedBankAccess_rd_bank_0_valid + & robEntries_15_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_15_renamedBankAccess_rd_bank_1_valid + & robEntries_15_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_15_renamedBankAccess_wr_bank_valid + & robEntries_15_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_14 + & ~robComplete_14 + & (robEntries_14_renamedBankAccess_rd_bank_0_valid + & robEntries_14_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_14_renamedBankAccess_rd_bank_1_valid + & robEntries_14_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_14_renamedBankAccess_wr_bank_valid + & robEntries_14_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_13 + & ~robComplete_13 + & (robEntries_13_renamedBankAccess_rd_bank_0_valid + & robEntries_13_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_13_renamedBankAccess_rd_bank_1_valid + & robEntries_13_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_13_renamedBankAccess_wr_bank_valid + & robEntries_13_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_12 + & ~robComplete_12 + & (robEntries_12_renamedBankAccess_rd_bank_0_valid + & robEntries_12_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_12_renamedBankAccess_rd_bank_1_valid + & robEntries_12_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_12_renamedBankAccess_wr_bank_valid + & robEntries_12_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_11 + & ~robComplete_11 + & (robEntries_11_renamedBankAccess_rd_bank_0_valid + & robEntries_11_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_11_renamedBankAccess_rd_bank_1_valid + & robEntries_11_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_11_renamedBankAccess_wr_bank_valid + & robEntries_11_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_10 + & ~robComplete_10 + & (robEntries_10_renamedBankAccess_rd_bank_0_valid + & robEntries_10_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_10_renamedBankAccess_rd_bank_1_valid + & robEntries_10_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_10_renamedBankAccess_wr_bank_valid + & robEntries_10_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_9 + & ~robComplete_9 + & (robEntries_9_renamedBankAccess_rd_bank_0_valid + & robEntries_9_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_9_renamedBankAccess_rd_bank_1_valid + & robEntries_9_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_9_renamedBankAccess_wr_bank_valid + & robEntries_9_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_8 + & ~robComplete_8 + & (robEntries_8_renamedBankAccess_rd_bank_0_valid + & robEntries_8_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_8_renamedBankAccess_rd_bank_1_valid + & robEntries_8_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_8_renamedBankAccess_wr_bank_valid + & robEntries_8_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_7 + & ~robComplete_7 + & (robEntries_7_renamedBankAccess_rd_bank_0_valid + & robEntries_7_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_7_renamedBankAccess_rd_bank_1_valid + & robEntries_7_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_7_renamedBankAccess_wr_bank_valid + & robEntries_7_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_6 + & ~robComplete_6 + & (robEntries_6_renamedBankAccess_rd_bank_0_valid + & robEntries_6_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_6_renamedBankAccess_rd_bank_1_valid + & robEntries_6_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_6_renamedBankAccess_wr_bank_valid + & robEntries_6_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_5 + & ~robComplete_5 + & (robEntries_5_renamedBankAccess_rd_bank_0_valid + & robEntries_5_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_5_renamedBankAccess_rd_bank_1_valid + & robEntries_5_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_5_renamedBankAccess_wr_bank_valid + & robEntries_5_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_4 + & ~robComplete_4 + & (robEntries_4_renamedBankAccess_rd_bank_0_valid + & robEntries_4_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_4_renamedBankAccess_rd_bank_1_valid + & robEntries_4_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_4_renamedBankAccess_wr_bank_valid + & robEntries_4_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_3 + & ~robComplete_3 + & (robEntries_3_renamedBankAccess_rd_bank_0_valid + & robEntries_3_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_3_renamedBankAccess_rd_bank_1_valid + & robEntries_3_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_3_renamedBankAccess_wr_bank_valid + & robEntries_3_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_2 + & ~robComplete_2 + & (robEntries_2_renamedBankAccess_rd_bank_0_valid + & robEntries_2_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_2_renamedBankAccess_rd_bank_1_valid + & robEntries_2_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_2_renamedBankAccess_wr_bank_valid + & robEntries_2_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_1 + & ~robComplete_1 + & (robEntries_1_renamedBankAccess_rd_bank_0_valid + & robEntries_1_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_1_renamedBankAccess_rd_bank_1_valid + & robEntries_1_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_1_renamedBankAccess_wr_bank_valid + & robEntries_1_renamedBankAccess_wr_bank_id == _tailAlias_T) | robValid_0 + & ~robComplete_0 + & (robEntries_0_renamedBankAccess_rd_bank_0_valid + & robEntries_0_renamedBankAccess_rd_bank_0_id == _tailAlias_T + | robEntries_0_renamedBankAccess_rd_bank_1_valid + & robEntries_0_renamedBankAccess_rd_bank_1_id == _tailAlias_T + | robEntries_0_renamedBankAccess_wr_bank_valid + & robEntries_0_renamedBankAccess_wr_bank_id == _tailAlias_T)); + wire _isAllocatedSlot_T_30 = io_alloc_ready_0 & io_alloc_valid; + wire [15:0] entryRawWrites_0 = + robEntries_0_cmd_bankAccess_wr_bank_valid + & robEntries_0_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_0_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_1 = + robEntries_1_cmd_bankAccess_wr_bank_valid + & robEntries_1_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_1_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_2 = + robEntries_2_cmd_bankAccess_wr_bank_valid + & robEntries_2_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_2_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_3 = + robEntries_3_cmd_bankAccess_wr_bank_valid + & robEntries_3_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_3_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_4 = + robEntries_4_cmd_bankAccess_wr_bank_valid + & robEntries_4_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_4_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_5 = + robEntries_5_cmd_bankAccess_wr_bank_valid + & robEntries_5_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_5_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_6 = + robEntries_6_cmd_bankAccess_wr_bank_valid + & robEntries_6_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_6_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_7 = + robEntries_7_cmd_bankAccess_wr_bank_valid + & robEntries_7_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_7_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_8 = + robEntries_8_cmd_bankAccess_wr_bank_valid + & robEntries_8_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_8_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_9 = + robEntries_9_cmd_bankAccess_wr_bank_valid + & robEntries_9_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_9_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_10 = + robEntries_10_cmd_bankAccess_wr_bank_valid + & robEntries_10_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_10_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_11 = + robEntries_11_cmd_bankAccess_wr_bank_valid + & robEntries_11_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_11_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_12 = + robEntries_12_cmd_bankAccess_wr_bank_valid + & robEntries_12_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_12_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_13 = + robEntries_13_cmd_bankAccess_wr_bank_valid + & robEntries_13_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_13_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_14 = + robEntries_14_cmd_bankAccess_wr_bank_valid + & robEntries_14_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_14_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] entryRawWrites_15 = + robEntries_15_cmd_bankAccess_wr_bank_valid + & robEntries_15_cmd_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << robEntries_15_cmd_bankAccess_wr_bank_id[3:0] + : 16'h0; + wire [15:0] olderUseMask = + (robEntries_0_cmd_bankAccess_rd_bank_0_valid + & robEntries_0_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_0_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_0_cmd_bankAccess_rd_bank_1_valid + & robEntries_0_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_0_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_0; + wire [15:0] vbankMasks_1 = + (robEntries_1_cmd_bankAccess_rd_bank_0_valid + & robEntries_1_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_1_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_1_cmd_bankAccess_rd_bank_1_valid + & robEntries_1_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_1_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_1; + wire [15:0] vbankMasks_2 = + (robEntries_2_cmd_bankAccess_rd_bank_0_valid + & robEntries_2_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_2_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_2_cmd_bankAccess_rd_bank_1_valid + & robEntries_2_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_2_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_2; + wire [15:0] vbankMasks_3 = + (robEntries_3_cmd_bankAccess_rd_bank_0_valid + & robEntries_3_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_3_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_3_cmd_bankAccess_rd_bank_1_valid + & robEntries_3_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_3_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_3; + wire [15:0] vbankMasks_4 = + (robEntries_4_cmd_bankAccess_rd_bank_0_valid + & robEntries_4_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_4_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_4_cmd_bankAccess_rd_bank_1_valid + & robEntries_4_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_4_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_4; + wire [15:0] vbankMasks_5 = + (robEntries_5_cmd_bankAccess_rd_bank_0_valid + & robEntries_5_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_5_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_5_cmd_bankAccess_rd_bank_1_valid + & robEntries_5_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_5_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_5; + wire [15:0] vbankMasks_6 = + (robEntries_6_cmd_bankAccess_rd_bank_0_valid + & robEntries_6_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_6_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_6_cmd_bankAccess_rd_bank_1_valid + & robEntries_6_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_6_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_6; + wire [15:0] vbankMasks_7 = + (robEntries_7_cmd_bankAccess_rd_bank_0_valid + & robEntries_7_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_7_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_7_cmd_bankAccess_rd_bank_1_valid + & robEntries_7_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_7_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_7; + wire [15:0] vbankMasks_8 = + (robEntries_8_cmd_bankAccess_rd_bank_0_valid + & robEntries_8_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_8_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_8_cmd_bankAccess_rd_bank_1_valid + & robEntries_8_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_8_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_8; + wire [15:0] vbankMasks_9 = + (robEntries_9_cmd_bankAccess_rd_bank_0_valid + & robEntries_9_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_9_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_9_cmd_bankAccess_rd_bank_1_valid + & robEntries_9_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_9_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_9; + wire [15:0] vbankMasks_10 = + (robEntries_10_cmd_bankAccess_rd_bank_0_valid + & robEntries_10_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_10_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_10_cmd_bankAccess_rd_bank_1_valid + & robEntries_10_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_10_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_10; + wire [15:0] vbankMasks_11 = + (robEntries_11_cmd_bankAccess_rd_bank_0_valid + & robEntries_11_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_11_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_11_cmd_bankAccess_rd_bank_1_valid + & robEntries_11_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_11_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_11; + wire [15:0] vbankMasks_12 = + (robEntries_12_cmd_bankAccess_rd_bank_0_valid + & robEntries_12_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_12_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_12_cmd_bankAccess_rd_bank_1_valid + & robEntries_12_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_12_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_12; + wire [15:0] vbankMasks_13 = + (robEntries_13_cmd_bankAccess_rd_bank_0_valid + & robEntries_13_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_13_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_13_cmd_bankAccess_rd_bank_1_valid + & robEntries_13_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_13_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_13; + wire [15:0] vbankMasks_14 = + (robEntries_14_cmd_bankAccess_rd_bank_0_valid + & robEntries_14_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_14_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_14_cmd_bankAccess_rd_bank_1_valid + & robEntries_14_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_14_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_14; + wire [15:0] vbankMasks_15 = + (robEntries_15_cmd_bankAccess_rd_bank_0_valid + & robEntries_15_cmd_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << robEntries_15_cmd_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (robEntries_15_cmd_bankAccess_rd_bank_1_valid + & robEntries_15_cmd_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << robEntries_15_cmd_bankAccess_rd_bank_1_id[3:0] + : 16'h0) | entryRawWrites_15; + wire _GEN_3 = _isAllocatedSlot_T_30 & (|io_alloc_bits_cmd_pc); + wire [15:0] _GEN_4 = + {{robIssued_15}, + {robIssued_14}, + {robIssued_13}, + {robIssued_12}, + {robIssued_11}, + {robIssued_10}, + {robIssued_9}, + {robIssued_8}, + {robIssued_7}, + {robIssued_6}, + {robIssued_5}, + {robIssued_4}, + {robIssued_3}, + {robIssued_2}, + {robIssued_1}, + {robIssued_0}}; + wire [15:0][3:0] _GEN_5 = + {{robEntries_15_cmd_domain_id}, + {robEntries_14_cmd_domain_id}, + {robEntries_13_cmd_domain_id}, + {robEntries_12_cmd_domain_id}, + {robEntries_11_cmd_domain_id}, + {robEntries_10_cmd_domain_id}, + {robEntries_9_cmd_domain_id}, + {robEntries_8_cmd_domain_id}, + {robEntries_7_cmd_domain_id}, + {robEntries_6_cmd_domain_id}, + {robEntries_5_cmd_domain_id}, + {robEntries_4_cmd_domain_id}, + {robEntries_3_cmd_domain_id}, + {robEntries_2_cmd_domain_id}, + {robEntries_1_cmd_domain_id}, + {robEntries_0_cmd_domain_id}}; + wire [15:0][63:0] _GEN_6 = + {{robEntries_15_cmd_cmd_pc}, + {robEntries_14_cmd_cmd_pc}, + {robEntries_13_cmd_cmd_pc}, + {robEntries_12_cmd_cmd_pc}, + {robEntries_11_cmd_cmd_pc}, + {robEntries_10_cmd_cmd_pc}, + {robEntries_9_cmd_cmd_pc}, + {robEntries_8_cmd_cmd_pc}, + {robEntries_7_cmd_cmd_pc}, + {robEntries_6_cmd_cmd_pc}, + {robEntries_5_cmd_cmd_pc}, + {robEntries_4_cmd_cmd_pc}, + {robEntries_3_cmd_cmd_pc}, + {robEntries_2_cmd_cmd_pc}, + {robEntries_1_cmd_cmd_pc}, + {robEntries_0_cmd_cmd_pc}}; + wire [15:0][6:0] _GEN_7 = + {{robEntries_15_cmd_cmd_funct}, + {robEntries_14_cmd_cmd_funct}, + {robEntries_13_cmd_cmd_funct}, + {robEntries_12_cmd_cmd_funct}, + {robEntries_11_cmd_cmd_funct}, + {robEntries_10_cmd_cmd_funct}, + {robEntries_9_cmd_cmd_funct}, + {robEntries_8_cmd_cmd_funct}, + {robEntries_7_cmd_cmd_funct}, + {robEntries_6_cmd_cmd_funct}, + {robEntries_5_cmd_cmd_funct}, + {robEntries_4_cmd_cmd_funct}, + {robEntries_3_cmd_cmd_funct}, + {robEntries_2_cmd_cmd_funct}, + {robEntries_1_cmd_cmd_funct}, + {robEntries_0_cmd_cmd_funct}}; + wire [15:0][63:0] _GEN_8 = + {{robEntries_15_cmd_cmd_rs1Data}, + {robEntries_14_cmd_cmd_rs1Data}, + {robEntries_13_cmd_cmd_rs1Data}, + {robEntries_12_cmd_cmd_rs1Data}, + {robEntries_11_cmd_cmd_rs1Data}, + {robEntries_10_cmd_cmd_rs1Data}, + {robEntries_9_cmd_cmd_rs1Data}, + {robEntries_8_cmd_cmd_rs1Data}, + {robEntries_7_cmd_cmd_rs1Data}, + {robEntries_6_cmd_cmd_rs1Data}, + {robEntries_5_cmd_cmd_rs1Data}, + {robEntries_4_cmd_cmd_rs1Data}, + {robEntries_3_cmd_cmd_rs1Data}, + {robEntries_2_cmd_cmd_rs1Data}, + {robEntries_1_cmd_cmd_rs1Data}, + {robEntries_0_cmd_cmd_rs1Data}}; + wire [15:0][63:0] _GEN_9 = + {{robEntries_15_cmd_cmd_rs2Data}, + {robEntries_14_cmd_cmd_rs2Data}, + {robEntries_13_cmd_cmd_rs2Data}, + {robEntries_12_cmd_cmd_rs2Data}, + {robEntries_11_cmd_cmd_rs2Data}, + {robEntries_10_cmd_cmd_rs2Data}, + {robEntries_9_cmd_cmd_rs2Data}, + {robEntries_8_cmd_cmd_rs2Data}, + {robEntries_7_cmd_cmd_rs2Data}, + {robEntries_6_cmd_cmd_rs2Data}, + {robEntries_5_cmd_cmd_rs2Data}, + {robEntries_4_cmd_cmd_rs2Data}, + {robEntries_3_cmd_cmd_rs2Data}, + {robEntries_2_cmd_cmd_rs2Data}, + {robEntries_1_cmd_cmd_rs2Data}, + {robEntries_0_cmd_cmd_rs2Data}}; + wire [15:0] _GEN_10 = + {{robEntries_15_renamedBankAccess_wr_bank_valid}, + {robEntries_14_renamedBankAccess_wr_bank_valid}, + {robEntries_13_renamedBankAccess_wr_bank_valid}, + {robEntries_12_renamedBankAccess_wr_bank_valid}, + {robEntries_11_renamedBankAccess_wr_bank_valid}, + {robEntries_10_renamedBankAccess_wr_bank_valid}, + {robEntries_9_renamedBankAccess_wr_bank_valid}, + {robEntries_8_renamedBankAccess_wr_bank_valid}, + {robEntries_7_renamedBankAccess_wr_bank_valid}, + {robEntries_6_renamedBankAccess_wr_bank_valid}, + {robEntries_5_renamedBankAccess_wr_bank_valid}, + {robEntries_4_renamedBankAccess_wr_bank_valid}, + {robEntries_3_renamedBankAccess_wr_bank_valid}, + {robEntries_2_renamedBankAccess_wr_bank_valid}, + {robEntries_1_renamedBankAccess_wr_bank_valid}, + {robEntries_0_renamedBankAccess_wr_bank_valid}}; + wire [15:0][9:0] _GEN_11 = + {{robEntries_15_renamedBankAccess_wr_bank_id}, + {robEntries_14_renamedBankAccess_wr_bank_id}, + {robEntries_13_renamedBankAccess_wr_bank_id}, + {robEntries_12_renamedBankAccess_wr_bank_id}, + {robEntries_11_renamedBankAccess_wr_bank_id}, + {robEntries_10_renamedBankAccess_wr_bank_id}, + {robEntries_9_renamedBankAccess_wr_bank_id}, + {robEntries_8_renamedBankAccess_wr_bank_id}, + {robEntries_7_renamedBankAccess_wr_bank_id}, + {robEntries_6_renamedBankAccess_wr_bank_id}, + {robEntries_5_renamedBankAccess_wr_bank_id}, + {robEntries_4_renamedBankAccess_wr_bank_id}, + {robEntries_3_renamedBankAccess_wr_bank_id}, + {robEntries_2_renamedBankAccess_wr_bank_id}, + {robEntries_1_renamedBankAccess_wr_bank_id}, + {robEntries_0_renamedBankAccess_wr_bank_id}}; + wire [15:0][63:0] _GEN_12 = + {{instIds_15}, + {instIds_14}, + {instIds_13}, + {instIds_12}, + {instIds_11}, + {instIds_10}, + {instIds_9}, + {instIds_8}, + {instIds_7}, + {instIds_6}, + {instIds_5}, + {instIds_4}, + {instIds_3}, + {instIds_2}, + {instIds_1}, + {instIds_0}}; + wire [15:0] _GEN_13 = + {{robEntries_15_renamedBankAccess_rd_bank_0_valid}, + {robEntries_14_renamedBankAccess_rd_bank_0_valid}, + {robEntries_13_renamedBankAccess_rd_bank_0_valid}, + {robEntries_12_renamedBankAccess_rd_bank_0_valid}, + {robEntries_11_renamedBankAccess_rd_bank_0_valid}, + {robEntries_10_renamedBankAccess_rd_bank_0_valid}, + {robEntries_9_renamedBankAccess_rd_bank_0_valid}, + {robEntries_8_renamedBankAccess_rd_bank_0_valid}, + {robEntries_7_renamedBankAccess_rd_bank_0_valid}, + {robEntries_6_renamedBankAccess_rd_bank_0_valid}, + {robEntries_5_renamedBankAccess_rd_bank_0_valid}, + {robEntries_4_renamedBankAccess_rd_bank_0_valid}, + {robEntries_3_renamedBankAccess_rd_bank_0_valid}, + {robEntries_2_renamedBankAccess_rd_bank_0_valid}, + {robEntries_1_renamedBankAccess_rd_bank_0_valid}, + {robEntries_0_renamedBankAccess_rd_bank_0_valid}}; + wire [15:0][9:0] _GEN_14 = + {{robEntries_15_renamedBankAccess_rd_bank_0_id}, + {robEntries_14_renamedBankAccess_rd_bank_0_id}, + {robEntries_13_renamedBankAccess_rd_bank_0_id}, + {robEntries_12_renamedBankAccess_rd_bank_0_id}, + {robEntries_11_renamedBankAccess_rd_bank_0_id}, + {robEntries_10_renamedBankAccess_rd_bank_0_id}, + {robEntries_9_renamedBankAccess_rd_bank_0_id}, + {robEntries_8_renamedBankAccess_rd_bank_0_id}, + {robEntries_7_renamedBankAccess_rd_bank_0_id}, + {robEntries_6_renamedBankAccess_rd_bank_0_id}, + {robEntries_5_renamedBankAccess_rd_bank_0_id}, + {robEntries_4_renamedBankAccess_rd_bank_0_id}, + {robEntries_3_renamedBankAccess_rd_bank_0_id}, + {robEntries_2_renamedBankAccess_rd_bank_0_id}, + {robEntries_1_renamedBankAccess_rd_bank_0_id}, + {robEntries_0_renamedBankAccess_rd_bank_0_id}}; + wire [15:0] _GEN_15 = + {{robEntries_15_renamedBankAccess_rd_bank_1_valid}, + {robEntries_14_renamedBankAccess_rd_bank_1_valid}, + {robEntries_13_renamedBankAccess_rd_bank_1_valid}, + {robEntries_12_renamedBankAccess_rd_bank_1_valid}, + {robEntries_11_renamedBankAccess_rd_bank_1_valid}, + {robEntries_10_renamedBankAccess_rd_bank_1_valid}, + {robEntries_9_renamedBankAccess_rd_bank_1_valid}, + {robEntries_8_renamedBankAccess_rd_bank_1_valid}, + {robEntries_7_renamedBankAccess_rd_bank_1_valid}, + {robEntries_6_renamedBankAccess_rd_bank_1_valid}, + {robEntries_5_renamedBankAccess_rd_bank_1_valid}, + {robEntries_4_renamedBankAccess_rd_bank_1_valid}, + {robEntries_3_renamedBankAccess_rd_bank_1_valid}, + {robEntries_2_renamedBankAccess_rd_bank_1_valid}, + {robEntries_1_renamedBankAccess_rd_bank_1_valid}, + {robEntries_0_renamedBankAccess_rd_bank_1_valid}}; + wire [15:0][9:0] _GEN_16 = + {{robEntries_15_renamedBankAccess_rd_bank_1_id}, + {robEntries_14_renamedBankAccess_rd_bank_1_id}, + {robEntries_13_renamedBankAccess_rd_bank_1_id}, + {robEntries_12_renamedBankAccess_rd_bank_1_id}, + {robEntries_11_renamedBankAccess_rd_bank_1_id}, + {robEntries_10_renamedBankAccess_rd_bank_1_id}, + {robEntries_9_renamedBankAccess_rd_bank_1_id}, + {robEntries_8_renamedBankAccess_rd_bank_1_id}, + {robEntries_7_renamedBankAccess_rd_bank_1_id}, + {robEntries_6_renamedBankAccess_rd_bank_1_id}, + {robEntries_5_renamedBankAccess_rd_bank_1_id}, + {robEntries_4_renamedBankAccess_rd_bank_1_id}, + {robEntries_3_renamedBankAccess_rd_bank_1_id}, + {robEntries_2_renamedBankAccess_rd_bank_1_id}, + {robEntries_1_renamedBankAccess_rd_bank_1_id}, + {robEntries_0_renamedBankAccess_rd_bank_1_id}}; + wire [15:0][15:0] _GEN_17 = + {{dependencyMask_15}, + {dependencyMask_14}, + {dependencyMask_13}, + {dependencyMask_12}, + {dependencyMask_11}, + {dependencyMask_10}, + {dependencyMask_9}, + {dependencyMask_8}, + {dependencyMask_7}, + {dependencyMask_6}, + {dependencyMask_5}, + {dependencyMask_4}, + {dependencyMask_3}, + {dependencyMask_2}, + {dependencyMask_1}, + {dependencyMask_0}}; + wire [15:0][15:0] _GEN_18 = + {{vbankMasks_15}, + {vbankMasks_14}, + {vbankMasks_13}, + {vbankMasks_12}, + {vbankMasks_11}, + {vbankMasks_10}, + {vbankMasks_9}, + {vbankMasks_8}, + {vbankMasks_7}, + {vbankMasks_6}, + {vbankMasks_5}, + {vbankMasks_4}, + {vbankMasks_3}, + {vbankMasks_2}, + {vbankMasks_1}, + {olderUseMask}}; + wire scanReady_0 = + _GEN_0 & ~_GEN_4[ptr] & ~_GEN_2 & ~_scoreboard_hazardVec_0 & _GEN_17[ptr] == 16'h0 + & (_GEN_18[ptr] & vbankBusy) == 16'h0; + wire scanReady_1 = + _GEN[_hits_ptr_T_1446] & ~_GEN_4[_hits_ptr_T_1446] & ~_GEN_1[_hits_ptr_T_1446] + & ~_scoreboard_hazardVec_1 & _GEN_17[_hits_ptr_T_1446] == 16'h0 + & (_GEN_18[_hits_ptr_T_1446] & vbankBusy) == 16'h0; + wire scanReady_2 = + _GEN[_hits_ptr_T_1452] & ~_GEN_4[_hits_ptr_T_1452] & ~_GEN_1[_hits_ptr_T_1452] + & ~_scoreboard_hazardVec_2 & _GEN_17[_hits_ptr_T_1452] == 16'h0 + & (_GEN_18[_hits_ptr_T_1452] & vbankBusy) == 16'h0; + wire scanReady_3 = + _GEN[_hits_ptr_T_1458] & ~_GEN_4[_hits_ptr_T_1458] & ~_GEN_1[_hits_ptr_T_1458] + & ~_scoreboard_hazardVec_3 & _GEN_17[_hits_ptr_T_1458] == 16'h0 + & (_GEN_18[_hits_ptr_T_1458] & vbankBusy) == 16'h0; + wire scanReady_4 = + _GEN[_hits_ptr_T_1464] & ~_GEN_4[_hits_ptr_T_1464] & ~_GEN_1[_hits_ptr_T_1464] + & ~_scoreboard_hazardVec_4 & _GEN_17[_hits_ptr_T_1464] == 16'h0 + & (_GEN_18[_hits_ptr_T_1464] & vbankBusy) == 16'h0; + wire scanReady_5 = + _GEN[_hits_ptr_T_1470] & ~_GEN_4[_hits_ptr_T_1470] & ~_GEN_1[_hits_ptr_T_1470] + & ~_scoreboard_hazardVec_5 & _GEN_17[_hits_ptr_T_1470] == 16'h0 + & (_GEN_18[_hits_ptr_T_1470] & vbankBusy) == 16'h0; + wire scanReady_6 = + _GEN[_hits_ptr_T_1476] & ~_GEN_4[_hits_ptr_T_1476] & ~_GEN_1[_hits_ptr_T_1476] + & ~_scoreboard_hazardVec_6 & _GEN_17[_hits_ptr_T_1476] == 16'h0 + & (_GEN_18[_hits_ptr_T_1476] & vbankBusy) == 16'h0; + wire scanReady_7 = + _GEN[_hits_ptr_T_1482] & ~_GEN_4[_hits_ptr_T_1482] & ~_GEN_1[_hits_ptr_T_1482] + & ~_scoreboard_hazardVec_7 & _GEN_17[_hits_ptr_T_1482] == 16'h0 + & (_GEN_18[_hits_ptr_T_1482] & vbankBusy) == 16'h0; + wire scanReady_8 = + _GEN[_hits_ptr_T_1488] & ~_GEN_4[_hits_ptr_T_1488] & ~_GEN_1[_hits_ptr_T_1488] + & ~_scoreboard_hazardVec_8 & _GEN_17[_hits_ptr_T_1488] == 16'h0 + & (_GEN_18[_hits_ptr_T_1488] & vbankBusy) == 16'h0; + wire scanReady_9 = + _GEN[_hits_ptr_T_1494] & ~_GEN_4[_hits_ptr_T_1494] & ~_GEN_1[_hits_ptr_T_1494] + & ~_scoreboard_hazardVec_9 & _GEN_17[_hits_ptr_T_1494] == 16'h0 + & (_GEN_18[_hits_ptr_T_1494] & vbankBusy) == 16'h0; + wire scanReady_10 = + _GEN[_hits_ptr_T_1500] & ~_GEN_4[_hits_ptr_T_1500] & ~_GEN_1[_hits_ptr_T_1500] + & ~_scoreboard_hazardVec_10 & _GEN_17[_hits_ptr_T_1500] == 16'h0 + & (_GEN_18[_hits_ptr_T_1500] & vbankBusy) == 16'h0; + wire scanReady_11 = + _GEN[_hits_ptr_T_1506] & ~_GEN_4[_hits_ptr_T_1506] & ~_GEN_1[_hits_ptr_T_1506] + & ~_scoreboard_hazardVec_11 & _GEN_17[_hits_ptr_T_1506] == 16'h0 + & (_GEN_18[_hits_ptr_T_1506] & vbankBusy) == 16'h0; + wire scanReady_12 = + _GEN[_hits_ptr_T_1512] & ~_GEN_4[_hits_ptr_T_1512] & ~_GEN_1[_hits_ptr_T_1512] + & ~_scoreboard_hazardVec_12 & _GEN_17[_hits_ptr_T_1512] == 16'h0 + & (_GEN_18[_hits_ptr_T_1512] & vbankBusy) == 16'h0; + wire scanReady_13 = + _GEN[_hits_ptr_T_1518] & ~_GEN_4[_hits_ptr_T_1518] & ~_GEN_1[_hits_ptr_T_1518] + & ~_scoreboard_hazardVec_13 & _GEN_17[_hits_ptr_T_1518] == 16'h0 + & (_GEN_18[_hits_ptr_T_1518] & vbankBusy) == 16'h0; + wire scanReady_14 = + _GEN[_hits_ptr_T_1524] & ~_GEN_4[_hits_ptr_T_1524] & ~_GEN_1[_hits_ptr_T_1524] + & ~_scoreboard_hazardVec_14 & _GEN_17[_hits_ptr_T_1524] == 16'h0 + & (_GEN_18[_hits_ptr_T_1524] & vbankBusy) == 16'h0; + wire [3:0] _actualIssuePtr_T = + ptr + + (scanReady_0 + ? 4'h0 + : scanReady_1 + ? 4'h1 + : scanReady_2 + ? 4'h2 + : scanReady_3 + ? 4'h3 + : scanReady_4 + ? 4'h4 + : scanReady_5 + ? 4'h5 + : scanReady_6 + ? 4'h6 + : scanReady_7 + ? 4'h7 + : scanReady_8 + ? 4'h8 + : scanReady_9 + ? 4'h9 + : scanReady_10 + ? 4'hA + : scanReady_11 + ? 4'hB + : scanReady_12 + ? 4'hC + : scanReady_13 + ? 4'hD + : {3'h7, ~scanReady_14}); + wire [15:0][3:0] _GEN_19 = + {{robEntries_15_rob_id}, + {robEntries_14_rob_id}, + {robEntries_13_rob_id}, + {robEntries_12_rob_id}, + {robEntries_11_rob_id}, + {robEntries_10_rob_id}, + {robEntries_9_rob_id}, + {robEntries_8_rob_id}, + {robEntries_7_rob_id}, + {robEntries_6_rob_id}, + {robEntries_5_rob_id}, + {robEntries_4_rob_id}, + {robEntries_3_rob_id}, + {robEntries_2_rob_id}, + {robEntries_1_rob_id}, + {robEntries_0_rob_id}}; + reg issueStageValid; + reg [3:0] issueStageEntry_cmd_domain_id; + reg [4:0] issueStageEntry_cmd_ball_bid; + reg [31:0] issueStageEntry_cmd_cmd_raw_inst; + reg [63:0] issueStageEntry_cmd_cmd_pc; + reg [6:0] issueStageEntry_cmd_cmd_funct; + reg [2:0] issueStageEntry_cmd_cmd_funct3; + reg [4:0] issueStageEntry_cmd_cmd_rs2; + reg [4:0] issueStageEntry_cmd_cmd_rs1; + reg issueStageEntry_cmd_cmd_xd; + reg issueStageEntry_cmd_cmd_xs1; + reg issueStageEntry_cmd_cmd_xs2; + reg [4:0] issueStageEntry_cmd_cmd_rd; + reg [6:0] issueStageEntry_cmd_cmd_opcode; + reg [63:0] issueStageEntry_cmd_cmd_rs1Data; + reg [63:0] issueStageEntry_cmd_cmd_rs2Data; + reg issueStageEntry_cmd_bankAccess_rd_bank_0_valid; + reg [9:0] issueStageEntry_cmd_bankAccess_rd_bank_0_id; + reg issueStageEntry_cmd_bankAccess_rd_bank_1_valid; + reg [9:0] issueStageEntry_cmd_bankAccess_rd_bank_1_id; + reg issueStageEntry_cmd_bankAccess_wr_bank_valid; + reg [9:0] issueStageEntry_cmd_bankAccess_wr_bank_id; + reg [3:0] issueStageEntry_cmd_op1_col; + reg [3:0] issueStageEntry_cmd_op2_col; + reg [3:0] issueStageEntry_cmd_wr_col; + reg issueStageEntry_cmd_isFence; + reg issueStageEntry_cmd_isBarrier; + reg issueStageEntry_renamedBankAccess_rd_bank_0_valid; + reg [9:0] issueStageEntry_renamedBankAccess_rd_bank_0_id; + reg issueStageEntry_renamedBankAccess_rd_bank_1_valid; + reg [9:0] issueStageEntry_renamedBankAccess_rd_bank_1_id; + reg issueStageEntry_renamedBankAccess_wr_bank_valid; + reg [9:0] issueStageEntry_renamedBankAccess_wr_bank_id; + reg [3:0] issueStageEntry_rob_id; + wire issueStageReady = + ~issueStageValid | issueStageValid & ~io_subRobActive & io_issue_ready; + reg issuePtrValid; + reg [3:0] issuePtr; + wire issuePtrFire = issuePtrValid & issueStageReady; + wire issuePtrReady = ~issuePtrValid | issuePtrFire; + wire issueLoad = + (|{_GEN[_hits_ptr_T_1530] & ~_GEN_4[_hits_ptr_T_1530] & ~_GEN_1[_hits_ptr_T_1530] + & ~_scoreboard_hazardVec_15 & _GEN_17[_hits_ptr_T_1530] == 16'h0 + & (_GEN_18[_hits_ptr_T_1530] & vbankBusy) == 16'h0, + scanReady_14, + scanReady_13, + scanReady_12, + scanReady_11, + scanReady_10, + scanReady_9, + scanReady_8, + scanReady_7, + scanReady_6, + scanReady_5, + scanReady_4, + scanReady_3, + scanReady_2, + scanReady_1, + scanReady_0}) & ~io_subRobActive & issuePtrReady; + assign commitMask_0 = + commitKeep_1 & ptr == 4'h0 | commitKeep_2 & _hits_ptr_T_1446 == 4'h0 | commitKeep_3 + & _hits_ptr_T_1452 == 4'h0 | commitKeep_4 & _hits_ptr_T_1458 == 4'h0 | commitKeep_5 + & _hits_ptr_T_1464 == 4'h0 | commitKeep_6 & _hits_ptr_T_1470 == 4'h0 | commitKeep_7 + & _hits_ptr_T_1476 == 4'h0 | commitKeep_8 & _hits_ptr_T_1482 == 4'h0 | commitKeep_9 + & _hits_ptr_T_1488 == 4'h0 | commitScan_9 & _hits_ptr_T_1494 == 4'h0 | commitKeep_11 + & _hits_ptr_T_1500 == 4'h0 | commitKeep_12 & _hits_ptr_T_1506 == 4'h0 | commitKeep_13 + & _hits_ptr_T_1512 == 4'h0 | commitKeep_14 & _hits_ptr_T_1518 == 4'h0 | commitKeep_15 + & _hits_ptr_T_1524 == 4'h0 | commitScan_15 & _hits_ptr_T_1530 == 4'h0; + assign commitMask_1 = + commitKeep_1 & ptr == 4'h1 | commitKeep_2 & _hits_ptr_T_1446 == 4'h1 | commitKeep_3 + & _hits_ptr_T_1452 == 4'h1 | commitKeep_4 & _hits_ptr_T_1458 == 4'h1 | commitKeep_5 + & _hits_ptr_T_1464 == 4'h1 | commitKeep_6 & _hits_ptr_T_1470 == 4'h1 | commitKeep_7 + & _hits_ptr_T_1476 == 4'h1 | commitKeep_8 & _hits_ptr_T_1482 == 4'h1 | commitKeep_9 + & _hits_ptr_T_1488 == 4'h1 | commitScan_9 & _hits_ptr_T_1494 == 4'h1 | commitKeep_11 + & _hits_ptr_T_1500 == 4'h1 | commitKeep_12 & _hits_ptr_T_1506 == 4'h1 | commitKeep_13 + & _hits_ptr_T_1512 == 4'h1 | commitKeep_14 & _hits_ptr_T_1518 == 4'h1 | commitKeep_15 + & _hits_ptr_T_1524 == 4'h1 | commitScan_15 & _hits_ptr_T_1530 == 4'h1; + assign commitMask_2 = + commitKeep_1 & ptr == 4'h2 | commitKeep_2 & _hits_ptr_T_1446 == 4'h2 | commitKeep_3 + & _hits_ptr_T_1452 == 4'h2 | commitKeep_4 & _hits_ptr_T_1458 == 4'h2 | commitKeep_5 + & _hits_ptr_T_1464 == 4'h2 | commitKeep_6 & _hits_ptr_T_1470 == 4'h2 | commitKeep_7 + & _hits_ptr_T_1476 == 4'h2 | commitKeep_8 & _hits_ptr_T_1482 == 4'h2 | commitKeep_9 + & _hits_ptr_T_1488 == 4'h2 | commitScan_9 & _hits_ptr_T_1494 == 4'h2 | commitKeep_11 + & _hits_ptr_T_1500 == 4'h2 | commitKeep_12 & _hits_ptr_T_1506 == 4'h2 | commitKeep_13 + & _hits_ptr_T_1512 == 4'h2 | commitKeep_14 & _hits_ptr_T_1518 == 4'h2 | commitKeep_15 + & _hits_ptr_T_1524 == 4'h2 | commitScan_15 & _hits_ptr_T_1530 == 4'h2; + assign commitMask_3 = + commitKeep_1 & ptr == 4'h3 | commitKeep_2 & _hits_ptr_T_1446 == 4'h3 | commitKeep_3 + & _hits_ptr_T_1452 == 4'h3 | commitKeep_4 & _hits_ptr_T_1458 == 4'h3 | commitKeep_5 + & _hits_ptr_T_1464 == 4'h3 | commitKeep_6 & _hits_ptr_T_1470 == 4'h3 | commitKeep_7 + & _hits_ptr_T_1476 == 4'h3 | commitKeep_8 & _hits_ptr_T_1482 == 4'h3 | commitKeep_9 + & _hits_ptr_T_1488 == 4'h3 | commitScan_9 & _hits_ptr_T_1494 == 4'h3 | commitKeep_11 + & _hits_ptr_T_1500 == 4'h3 | commitKeep_12 & _hits_ptr_T_1506 == 4'h3 | commitKeep_13 + & _hits_ptr_T_1512 == 4'h3 | commitKeep_14 & _hits_ptr_T_1518 == 4'h3 | commitKeep_15 + & _hits_ptr_T_1524 == 4'h3 | commitScan_15 & _hits_ptr_T_1530 == 4'h3; + assign commitMask_4 = + commitKeep_1 & ptr == 4'h4 | commitKeep_2 & _hits_ptr_T_1446 == 4'h4 | commitKeep_3 + & _hits_ptr_T_1452 == 4'h4 | commitKeep_4 & _hits_ptr_T_1458 == 4'h4 | commitKeep_5 + & _hits_ptr_T_1464 == 4'h4 | commitKeep_6 & _hits_ptr_T_1470 == 4'h4 | commitKeep_7 + & _hits_ptr_T_1476 == 4'h4 | commitKeep_8 & _hits_ptr_T_1482 == 4'h4 | commitKeep_9 + & _hits_ptr_T_1488 == 4'h4 | commitScan_9 & _hits_ptr_T_1494 == 4'h4 | commitKeep_11 + & _hits_ptr_T_1500 == 4'h4 | commitKeep_12 & _hits_ptr_T_1506 == 4'h4 | commitKeep_13 + & _hits_ptr_T_1512 == 4'h4 | commitKeep_14 & _hits_ptr_T_1518 == 4'h4 | commitKeep_15 + & _hits_ptr_T_1524 == 4'h4 | commitScan_15 & _hits_ptr_T_1530 == 4'h4; + assign commitMask_5 = + commitKeep_1 & ptr == 4'h5 | commitKeep_2 & _hits_ptr_T_1446 == 4'h5 | commitKeep_3 + & _hits_ptr_T_1452 == 4'h5 | commitKeep_4 & _hits_ptr_T_1458 == 4'h5 | commitKeep_5 + & _hits_ptr_T_1464 == 4'h5 | commitKeep_6 & _hits_ptr_T_1470 == 4'h5 | commitKeep_7 + & _hits_ptr_T_1476 == 4'h5 | commitKeep_8 & _hits_ptr_T_1482 == 4'h5 | commitKeep_9 + & _hits_ptr_T_1488 == 4'h5 | commitScan_9 & _hits_ptr_T_1494 == 4'h5 | commitKeep_11 + & _hits_ptr_T_1500 == 4'h5 | commitKeep_12 & _hits_ptr_T_1506 == 4'h5 | commitKeep_13 + & _hits_ptr_T_1512 == 4'h5 | commitKeep_14 & _hits_ptr_T_1518 == 4'h5 | commitKeep_15 + & _hits_ptr_T_1524 == 4'h5 | commitScan_15 & _hits_ptr_T_1530 == 4'h5; + assign commitMask_6 = + commitKeep_1 & ptr == 4'h6 | commitKeep_2 & _hits_ptr_T_1446 == 4'h6 | commitKeep_3 + & _hits_ptr_T_1452 == 4'h6 | commitKeep_4 & _hits_ptr_T_1458 == 4'h6 | commitKeep_5 + & _hits_ptr_T_1464 == 4'h6 | commitKeep_6 & _hits_ptr_T_1470 == 4'h6 | commitKeep_7 + & _hits_ptr_T_1476 == 4'h6 | commitKeep_8 & _hits_ptr_T_1482 == 4'h6 | commitKeep_9 + & _hits_ptr_T_1488 == 4'h6 | commitScan_9 & _hits_ptr_T_1494 == 4'h6 | commitKeep_11 + & _hits_ptr_T_1500 == 4'h6 | commitKeep_12 & _hits_ptr_T_1506 == 4'h6 | commitKeep_13 + & _hits_ptr_T_1512 == 4'h6 | commitKeep_14 & _hits_ptr_T_1518 == 4'h6 | commitKeep_15 + & _hits_ptr_T_1524 == 4'h6 | commitScan_15 & _hits_ptr_T_1530 == 4'h6; + assign commitMask_7 = + commitKeep_1 & ptr == 4'h7 | commitKeep_2 & _hits_ptr_T_1446 == 4'h7 | commitKeep_3 + & _hits_ptr_T_1452 == 4'h7 | commitKeep_4 & _hits_ptr_T_1458 == 4'h7 | commitKeep_5 + & _hits_ptr_T_1464 == 4'h7 | commitKeep_6 & _hits_ptr_T_1470 == 4'h7 | commitKeep_7 + & _hits_ptr_T_1476 == 4'h7 | commitKeep_8 & _hits_ptr_T_1482 == 4'h7 | commitKeep_9 + & _hits_ptr_T_1488 == 4'h7 | commitScan_9 & _hits_ptr_T_1494 == 4'h7 | commitKeep_11 + & _hits_ptr_T_1500 == 4'h7 | commitKeep_12 & _hits_ptr_T_1506 == 4'h7 | commitKeep_13 + & _hits_ptr_T_1512 == 4'h7 | commitKeep_14 & _hits_ptr_T_1518 == 4'h7 | commitKeep_15 + & _hits_ptr_T_1524 == 4'h7 | commitScan_15 & _hits_ptr_T_1530 == 4'h7; + assign commitMask_8 = + commitKeep_1 & ptr == 4'h8 | commitKeep_2 & _hits_ptr_T_1446 == 4'h8 | commitKeep_3 + & _hits_ptr_T_1452 == 4'h8 | commitKeep_4 & _hits_ptr_T_1458 == 4'h8 | commitKeep_5 + & _hits_ptr_T_1464 == 4'h8 | commitKeep_6 & _hits_ptr_T_1470 == 4'h8 | commitKeep_7 + & _hits_ptr_T_1476 == 4'h8 | commitKeep_8 & _hits_ptr_T_1482 == 4'h8 | commitKeep_9 + & _hits_ptr_T_1488 == 4'h8 | commitScan_9 & _hits_ptr_T_1494 == 4'h8 | commitKeep_11 + & _hits_ptr_T_1500 == 4'h8 | commitKeep_12 & _hits_ptr_T_1506 == 4'h8 | commitKeep_13 + & _hits_ptr_T_1512 == 4'h8 | commitKeep_14 & _hits_ptr_T_1518 == 4'h8 | commitKeep_15 + & _hits_ptr_T_1524 == 4'h8 | commitScan_15 & _hits_ptr_T_1530 == 4'h8; + assign commitMask_9 = + commitKeep_1 & ptr == 4'h9 | commitKeep_2 & _hits_ptr_T_1446 == 4'h9 | commitKeep_3 + & _hits_ptr_T_1452 == 4'h9 | commitKeep_4 & _hits_ptr_T_1458 == 4'h9 | commitKeep_5 + & _hits_ptr_T_1464 == 4'h9 | commitKeep_6 & _hits_ptr_T_1470 == 4'h9 | commitKeep_7 + & _hits_ptr_T_1476 == 4'h9 | commitKeep_8 & _hits_ptr_T_1482 == 4'h9 | commitKeep_9 + & _hits_ptr_T_1488 == 4'h9 | commitScan_9 & _hits_ptr_T_1494 == 4'h9 | commitKeep_11 + & _hits_ptr_T_1500 == 4'h9 | commitKeep_12 & _hits_ptr_T_1506 == 4'h9 | commitKeep_13 + & _hits_ptr_T_1512 == 4'h9 | commitKeep_14 & _hits_ptr_T_1518 == 4'h9 | commitKeep_15 + & _hits_ptr_T_1524 == 4'h9 | commitScan_15 & _hits_ptr_T_1530 == 4'h9; + assign commitMask_10 = + commitKeep_1 & ptr == 4'hA | commitKeep_2 & _hits_ptr_T_1446 == 4'hA | commitKeep_3 + & _hits_ptr_T_1452 == 4'hA | commitKeep_4 & _hits_ptr_T_1458 == 4'hA | commitKeep_5 + & _hits_ptr_T_1464 == 4'hA | commitKeep_6 & _hits_ptr_T_1470 == 4'hA | commitKeep_7 + & _hits_ptr_T_1476 == 4'hA | commitKeep_8 & _hits_ptr_T_1482 == 4'hA | commitKeep_9 + & _hits_ptr_T_1488 == 4'hA | commitScan_9 & _hits_ptr_T_1494 == 4'hA | commitKeep_11 + & _hits_ptr_T_1500 == 4'hA | commitKeep_12 & _hits_ptr_T_1506 == 4'hA | commitKeep_13 + & _hits_ptr_T_1512 == 4'hA | commitKeep_14 & _hits_ptr_T_1518 == 4'hA | commitKeep_15 + & _hits_ptr_T_1524 == 4'hA | commitScan_15 & _hits_ptr_T_1530 == 4'hA; + assign commitMask_11 = + commitKeep_1 & ptr == 4'hB | commitKeep_2 & _hits_ptr_T_1446 == 4'hB | commitKeep_3 + & _hits_ptr_T_1452 == 4'hB | commitKeep_4 & _hits_ptr_T_1458 == 4'hB | commitKeep_5 + & _hits_ptr_T_1464 == 4'hB | commitKeep_6 & _hits_ptr_T_1470 == 4'hB | commitKeep_7 + & _hits_ptr_T_1476 == 4'hB | commitKeep_8 & _hits_ptr_T_1482 == 4'hB | commitKeep_9 + & _hits_ptr_T_1488 == 4'hB | commitScan_9 & _hits_ptr_T_1494 == 4'hB | commitKeep_11 + & _hits_ptr_T_1500 == 4'hB | commitKeep_12 & _hits_ptr_T_1506 == 4'hB | commitKeep_13 + & _hits_ptr_T_1512 == 4'hB | commitKeep_14 & _hits_ptr_T_1518 == 4'hB | commitKeep_15 + & _hits_ptr_T_1524 == 4'hB | commitScan_15 & _hits_ptr_T_1530 == 4'hB; + assign commitMask_12 = + commitKeep_1 & ptr == 4'hC | commitKeep_2 & _hits_ptr_T_1446 == 4'hC | commitKeep_3 + & _hits_ptr_T_1452 == 4'hC | commitKeep_4 & _hits_ptr_T_1458 == 4'hC | commitKeep_5 + & _hits_ptr_T_1464 == 4'hC | commitKeep_6 & _hits_ptr_T_1470 == 4'hC | commitKeep_7 + & _hits_ptr_T_1476 == 4'hC | commitKeep_8 & _hits_ptr_T_1482 == 4'hC | commitKeep_9 + & _hits_ptr_T_1488 == 4'hC | commitScan_9 & _hits_ptr_T_1494 == 4'hC | commitKeep_11 + & _hits_ptr_T_1500 == 4'hC | commitKeep_12 & _hits_ptr_T_1506 == 4'hC | commitKeep_13 + & _hits_ptr_T_1512 == 4'hC | commitKeep_14 & _hits_ptr_T_1518 == 4'hC | commitKeep_15 + & _hits_ptr_T_1524 == 4'hC | commitScan_15 & _hits_ptr_T_1530 == 4'hC; + assign commitMask_13 = + commitKeep_1 & ptr == 4'hD | commitKeep_2 & _hits_ptr_T_1446 == 4'hD | commitKeep_3 + & _hits_ptr_T_1452 == 4'hD | commitKeep_4 & _hits_ptr_T_1458 == 4'hD | commitKeep_5 + & _hits_ptr_T_1464 == 4'hD | commitKeep_6 & _hits_ptr_T_1470 == 4'hD | commitKeep_7 + & _hits_ptr_T_1476 == 4'hD | commitKeep_8 & _hits_ptr_T_1482 == 4'hD | commitKeep_9 + & _hits_ptr_T_1488 == 4'hD | commitScan_9 & _hits_ptr_T_1494 == 4'hD | commitKeep_11 + & _hits_ptr_T_1500 == 4'hD | commitKeep_12 & _hits_ptr_T_1506 == 4'hD | commitKeep_13 + & _hits_ptr_T_1512 == 4'hD | commitKeep_14 & _hits_ptr_T_1518 == 4'hD | commitKeep_15 + & _hits_ptr_T_1524 == 4'hD | commitScan_15 & _hits_ptr_T_1530 == 4'hD; + assign commitMask_14 = + commitKeep_1 & ptr == 4'hE | commitKeep_2 & _hits_ptr_T_1446 == 4'hE | commitKeep_3 + & _hits_ptr_T_1452 == 4'hE | commitKeep_4 & _hits_ptr_T_1458 == 4'hE | commitKeep_5 + & _hits_ptr_T_1464 == 4'hE | commitKeep_6 & _hits_ptr_T_1470 == 4'hE | commitKeep_7 + & _hits_ptr_T_1476 == 4'hE | commitKeep_8 & _hits_ptr_T_1482 == 4'hE | commitKeep_9 + & _hits_ptr_T_1488 == 4'hE | commitScan_9 & _hits_ptr_T_1494 == 4'hE | commitKeep_11 + & _hits_ptr_T_1500 == 4'hE | commitKeep_12 & _hits_ptr_T_1506 == 4'hE | commitKeep_13 + & _hits_ptr_T_1512 == 4'hE | commitKeep_14 & _hits_ptr_T_1518 == 4'hE | commitKeep_15 + & _hits_ptr_T_1524 == 4'hE | commitScan_15 & _hits_ptr_T_1530 == 4'hE; + assign commitMask_15 = + commitKeep_1 & (&ptr) | commitKeep_2 & (&_hits_ptr_T_1446) | commitKeep_3 + & (&_hits_ptr_T_1452) | commitKeep_4 & (&_hits_ptr_T_1458) | commitKeep_5 + & (&_hits_ptr_T_1464) | commitKeep_6 & (&_hits_ptr_T_1470) | commitKeep_7 + & (&_hits_ptr_T_1476) | commitKeep_8 & (&_hits_ptr_T_1482) | commitKeep_9 + & (&_hits_ptr_T_1488) | commitScan_9 & (&_hits_ptr_T_1494) | commitKeep_11 + & (&_hits_ptr_T_1500) | commitKeep_12 & (&_hits_ptr_T_1506) | commitKeep_13 + & (&_hits_ptr_T_1512) | commitKeep_14 & (&_hits_ptr_T_1518) | commitKeep_15 + & (&_hits_ptr_T_1524) | commitScan_15 & (&_hits_ptr_T_1530); + always @(posedge clock) begin + if (reset) begin + robEntries_0_cmd_domain_id <= 4'h0; + robEntries_0_cmd_ball_bid <= 5'h0; + robEntries_0_cmd_cmd_raw_inst <= 32'h0; + robEntries_0_cmd_cmd_pc <= 64'h0; + robEntries_0_cmd_cmd_funct <= 7'h0; + robEntries_0_cmd_cmd_funct3 <= 3'h0; + robEntries_0_cmd_cmd_rs2 <= 5'h0; + robEntries_0_cmd_cmd_rs1 <= 5'h0; + robEntries_0_cmd_cmd_xd <= 1'h0; + robEntries_0_cmd_cmd_xs1 <= 1'h0; + robEntries_0_cmd_cmd_xs2 <= 1'h0; + robEntries_0_cmd_cmd_rd <= 5'h0; + robEntries_0_cmd_cmd_opcode <= 7'h0; + robEntries_0_cmd_cmd_rs1Data <= 64'h0; + robEntries_0_cmd_cmd_rs2Data <= 64'h0; + robEntries_0_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_0_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_0_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_0_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_0_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_0_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_0_cmd_isFence <= 1'h0; + robEntries_0_cmd_isBarrier <= 1'h0; + robEntries_0_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_0_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_0_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_0_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_0_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_0_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_0_rob_id <= 4'h0; + robEntries_1_cmd_domain_id <= 4'h0; + robEntries_1_cmd_ball_bid <= 5'h0; + robEntries_1_cmd_cmd_raw_inst <= 32'h0; + robEntries_1_cmd_cmd_pc <= 64'h0; + robEntries_1_cmd_cmd_funct <= 7'h0; + robEntries_1_cmd_cmd_funct3 <= 3'h0; + robEntries_1_cmd_cmd_rs2 <= 5'h0; + robEntries_1_cmd_cmd_rs1 <= 5'h0; + robEntries_1_cmd_cmd_xd <= 1'h0; + robEntries_1_cmd_cmd_xs1 <= 1'h0; + robEntries_1_cmd_cmd_xs2 <= 1'h0; + robEntries_1_cmd_cmd_rd <= 5'h0; + robEntries_1_cmd_cmd_opcode <= 7'h0; + robEntries_1_cmd_cmd_rs1Data <= 64'h0; + robEntries_1_cmd_cmd_rs2Data <= 64'h0; + robEntries_1_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_1_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_1_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_1_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_1_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_1_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_1_cmd_isFence <= 1'h0; + robEntries_1_cmd_isBarrier <= 1'h0; + robEntries_1_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_1_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_1_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_1_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_1_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_1_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_1_rob_id <= 4'h0; + robEntries_2_cmd_domain_id <= 4'h0; + robEntries_2_cmd_ball_bid <= 5'h0; + robEntries_2_cmd_cmd_raw_inst <= 32'h0; + robEntries_2_cmd_cmd_pc <= 64'h0; + robEntries_2_cmd_cmd_funct <= 7'h0; + robEntries_2_cmd_cmd_funct3 <= 3'h0; + robEntries_2_cmd_cmd_rs2 <= 5'h0; + robEntries_2_cmd_cmd_rs1 <= 5'h0; + robEntries_2_cmd_cmd_xd <= 1'h0; + robEntries_2_cmd_cmd_xs1 <= 1'h0; + robEntries_2_cmd_cmd_xs2 <= 1'h0; + robEntries_2_cmd_cmd_rd <= 5'h0; + robEntries_2_cmd_cmd_opcode <= 7'h0; + robEntries_2_cmd_cmd_rs1Data <= 64'h0; + robEntries_2_cmd_cmd_rs2Data <= 64'h0; + robEntries_2_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_2_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_2_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_2_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_2_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_2_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_2_cmd_isFence <= 1'h0; + robEntries_2_cmd_isBarrier <= 1'h0; + robEntries_2_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_2_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_2_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_2_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_2_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_2_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_2_rob_id <= 4'h0; + robEntries_3_cmd_domain_id <= 4'h0; + robEntries_3_cmd_ball_bid <= 5'h0; + robEntries_3_cmd_cmd_raw_inst <= 32'h0; + robEntries_3_cmd_cmd_pc <= 64'h0; + robEntries_3_cmd_cmd_funct <= 7'h0; + robEntries_3_cmd_cmd_funct3 <= 3'h0; + robEntries_3_cmd_cmd_rs2 <= 5'h0; + robEntries_3_cmd_cmd_rs1 <= 5'h0; + robEntries_3_cmd_cmd_xd <= 1'h0; + robEntries_3_cmd_cmd_xs1 <= 1'h0; + robEntries_3_cmd_cmd_xs2 <= 1'h0; + robEntries_3_cmd_cmd_rd <= 5'h0; + robEntries_3_cmd_cmd_opcode <= 7'h0; + robEntries_3_cmd_cmd_rs1Data <= 64'h0; + robEntries_3_cmd_cmd_rs2Data <= 64'h0; + robEntries_3_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_3_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_3_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_3_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_3_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_3_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_3_cmd_isFence <= 1'h0; + robEntries_3_cmd_isBarrier <= 1'h0; + robEntries_3_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_3_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_3_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_3_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_3_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_3_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_3_rob_id <= 4'h0; + robEntries_4_cmd_domain_id <= 4'h0; + robEntries_4_cmd_ball_bid <= 5'h0; + robEntries_4_cmd_cmd_raw_inst <= 32'h0; + robEntries_4_cmd_cmd_pc <= 64'h0; + robEntries_4_cmd_cmd_funct <= 7'h0; + robEntries_4_cmd_cmd_funct3 <= 3'h0; + robEntries_4_cmd_cmd_rs2 <= 5'h0; + robEntries_4_cmd_cmd_rs1 <= 5'h0; + robEntries_4_cmd_cmd_xd <= 1'h0; + robEntries_4_cmd_cmd_xs1 <= 1'h0; + robEntries_4_cmd_cmd_xs2 <= 1'h0; + robEntries_4_cmd_cmd_rd <= 5'h0; + robEntries_4_cmd_cmd_opcode <= 7'h0; + robEntries_4_cmd_cmd_rs1Data <= 64'h0; + robEntries_4_cmd_cmd_rs2Data <= 64'h0; + robEntries_4_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_4_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_4_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_4_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_4_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_4_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_4_cmd_isFence <= 1'h0; + robEntries_4_cmd_isBarrier <= 1'h0; + robEntries_4_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_4_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_4_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_4_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_4_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_4_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_4_rob_id <= 4'h0; + robEntries_5_cmd_domain_id <= 4'h0; + robEntries_5_cmd_ball_bid <= 5'h0; + robEntries_5_cmd_cmd_raw_inst <= 32'h0; + robEntries_5_cmd_cmd_pc <= 64'h0; + robEntries_5_cmd_cmd_funct <= 7'h0; + robEntries_5_cmd_cmd_funct3 <= 3'h0; + robEntries_5_cmd_cmd_rs2 <= 5'h0; + robEntries_5_cmd_cmd_rs1 <= 5'h0; + robEntries_5_cmd_cmd_xd <= 1'h0; + robEntries_5_cmd_cmd_xs1 <= 1'h0; + robEntries_5_cmd_cmd_xs2 <= 1'h0; + robEntries_5_cmd_cmd_rd <= 5'h0; + robEntries_5_cmd_cmd_opcode <= 7'h0; + robEntries_5_cmd_cmd_rs1Data <= 64'h0; + robEntries_5_cmd_cmd_rs2Data <= 64'h0; + robEntries_5_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_5_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_5_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_5_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_5_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_5_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_5_cmd_isFence <= 1'h0; + robEntries_5_cmd_isBarrier <= 1'h0; + robEntries_5_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_5_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_5_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_5_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_5_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_5_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_5_rob_id <= 4'h0; + robEntries_6_cmd_domain_id <= 4'h0; + robEntries_6_cmd_ball_bid <= 5'h0; + robEntries_6_cmd_cmd_raw_inst <= 32'h0; + robEntries_6_cmd_cmd_pc <= 64'h0; + robEntries_6_cmd_cmd_funct <= 7'h0; + robEntries_6_cmd_cmd_funct3 <= 3'h0; + robEntries_6_cmd_cmd_rs2 <= 5'h0; + robEntries_6_cmd_cmd_rs1 <= 5'h0; + robEntries_6_cmd_cmd_xd <= 1'h0; + robEntries_6_cmd_cmd_xs1 <= 1'h0; + robEntries_6_cmd_cmd_xs2 <= 1'h0; + robEntries_6_cmd_cmd_rd <= 5'h0; + robEntries_6_cmd_cmd_opcode <= 7'h0; + robEntries_6_cmd_cmd_rs1Data <= 64'h0; + robEntries_6_cmd_cmd_rs2Data <= 64'h0; + robEntries_6_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_6_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_6_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_6_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_6_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_6_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_6_cmd_isFence <= 1'h0; + robEntries_6_cmd_isBarrier <= 1'h0; + robEntries_6_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_6_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_6_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_6_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_6_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_6_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_6_rob_id <= 4'h0; + robEntries_7_cmd_domain_id <= 4'h0; + robEntries_7_cmd_ball_bid <= 5'h0; + robEntries_7_cmd_cmd_raw_inst <= 32'h0; + robEntries_7_cmd_cmd_pc <= 64'h0; + robEntries_7_cmd_cmd_funct <= 7'h0; + robEntries_7_cmd_cmd_funct3 <= 3'h0; + robEntries_7_cmd_cmd_rs2 <= 5'h0; + robEntries_7_cmd_cmd_rs1 <= 5'h0; + robEntries_7_cmd_cmd_xd <= 1'h0; + robEntries_7_cmd_cmd_xs1 <= 1'h0; + robEntries_7_cmd_cmd_xs2 <= 1'h0; + robEntries_7_cmd_cmd_rd <= 5'h0; + robEntries_7_cmd_cmd_opcode <= 7'h0; + robEntries_7_cmd_cmd_rs1Data <= 64'h0; + robEntries_7_cmd_cmd_rs2Data <= 64'h0; + robEntries_7_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_7_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_7_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_7_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_7_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_7_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_7_cmd_isFence <= 1'h0; + robEntries_7_cmd_isBarrier <= 1'h0; + robEntries_7_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_7_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_7_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_7_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_7_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_7_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_7_rob_id <= 4'h0; + robEntries_8_cmd_domain_id <= 4'h0; + robEntries_8_cmd_ball_bid <= 5'h0; + robEntries_8_cmd_cmd_raw_inst <= 32'h0; + robEntries_8_cmd_cmd_pc <= 64'h0; + robEntries_8_cmd_cmd_funct <= 7'h0; + robEntries_8_cmd_cmd_funct3 <= 3'h0; + robEntries_8_cmd_cmd_rs2 <= 5'h0; + robEntries_8_cmd_cmd_rs1 <= 5'h0; + robEntries_8_cmd_cmd_xd <= 1'h0; + robEntries_8_cmd_cmd_xs1 <= 1'h0; + robEntries_8_cmd_cmd_xs2 <= 1'h0; + robEntries_8_cmd_cmd_rd <= 5'h0; + robEntries_8_cmd_cmd_opcode <= 7'h0; + robEntries_8_cmd_cmd_rs1Data <= 64'h0; + robEntries_8_cmd_cmd_rs2Data <= 64'h0; + robEntries_8_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_8_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_8_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_8_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_8_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_8_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_8_cmd_isFence <= 1'h0; + robEntries_8_cmd_isBarrier <= 1'h0; + robEntries_8_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_8_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_8_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_8_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_8_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_8_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_8_rob_id <= 4'h0; + robEntries_9_cmd_domain_id <= 4'h0; + robEntries_9_cmd_ball_bid <= 5'h0; + robEntries_9_cmd_cmd_raw_inst <= 32'h0; + robEntries_9_cmd_cmd_pc <= 64'h0; + robEntries_9_cmd_cmd_funct <= 7'h0; + robEntries_9_cmd_cmd_funct3 <= 3'h0; + robEntries_9_cmd_cmd_rs2 <= 5'h0; + robEntries_9_cmd_cmd_rs1 <= 5'h0; + robEntries_9_cmd_cmd_xd <= 1'h0; + robEntries_9_cmd_cmd_xs1 <= 1'h0; + robEntries_9_cmd_cmd_xs2 <= 1'h0; + robEntries_9_cmd_cmd_rd <= 5'h0; + robEntries_9_cmd_cmd_opcode <= 7'h0; + robEntries_9_cmd_cmd_rs1Data <= 64'h0; + robEntries_9_cmd_cmd_rs2Data <= 64'h0; + robEntries_9_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_9_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_9_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_9_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_9_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_9_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_9_cmd_isFence <= 1'h0; + robEntries_9_cmd_isBarrier <= 1'h0; + robEntries_9_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_9_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_9_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_9_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_9_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_9_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_9_rob_id <= 4'h0; + robEntries_10_cmd_domain_id <= 4'h0; + robEntries_10_cmd_ball_bid <= 5'h0; + robEntries_10_cmd_cmd_raw_inst <= 32'h0; + robEntries_10_cmd_cmd_pc <= 64'h0; + robEntries_10_cmd_cmd_funct <= 7'h0; + robEntries_10_cmd_cmd_funct3 <= 3'h0; + robEntries_10_cmd_cmd_rs2 <= 5'h0; + robEntries_10_cmd_cmd_rs1 <= 5'h0; + robEntries_10_cmd_cmd_xd <= 1'h0; + robEntries_10_cmd_cmd_xs1 <= 1'h0; + robEntries_10_cmd_cmd_xs2 <= 1'h0; + robEntries_10_cmd_cmd_rd <= 5'h0; + robEntries_10_cmd_cmd_opcode <= 7'h0; + robEntries_10_cmd_cmd_rs1Data <= 64'h0; + robEntries_10_cmd_cmd_rs2Data <= 64'h0; + robEntries_10_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_10_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_10_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_10_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_10_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_10_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_10_cmd_isFence <= 1'h0; + robEntries_10_cmd_isBarrier <= 1'h0; + robEntries_10_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_10_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_10_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_10_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_10_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_10_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_10_rob_id <= 4'h0; + robEntries_11_cmd_domain_id <= 4'h0; + robEntries_11_cmd_ball_bid <= 5'h0; + robEntries_11_cmd_cmd_raw_inst <= 32'h0; + robEntries_11_cmd_cmd_pc <= 64'h0; + robEntries_11_cmd_cmd_funct <= 7'h0; + robEntries_11_cmd_cmd_funct3 <= 3'h0; + robEntries_11_cmd_cmd_rs2 <= 5'h0; + robEntries_11_cmd_cmd_rs1 <= 5'h0; + robEntries_11_cmd_cmd_xd <= 1'h0; + robEntries_11_cmd_cmd_xs1 <= 1'h0; + robEntries_11_cmd_cmd_xs2 <= 1'h0; + robEntries_11_cmd_cmd_rd <= 5'h0; + robEntries_11_cmd_cmd_opcode <= 7'h0; + robEntries_11_cmd_cmd_rs1Data <= 64'h0; + robEntries_11_cmd_cmd_rs2Data <= 64'h0; + robEntries_11_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_11_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_11_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_11_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_11_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_11_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_11_cmd_isFence <= 1'h0; + robEntries_11_cmd_isBarrier <= 1'h0; + robEntries_11_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_11_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_11_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_11_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_11_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_11_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_11_rob_id <= 4'h0; + robEntries_12_cmd_domain_id <= 4'h0; + robEntries_12_cmd_ball_bid <= 5'h0; + robEntries_12_cmd_cmd_raw_inst <= 32'h0; + robEntries_12_cmd_cmd_pc <= 64'h0; + robEntries_12_cmd_cmd_funct <= 7'h0; + robEntries_12_cmd_cmd_funct3 <= 3'h0; + robEntries_12_cmd_cmd_rs2 <= 5'h0; + robEntries_12_cmd_cmd_rs1 <= 5'h0; + robEntries_12_cmd_cmd_xd <= 1'h0; + robEntries_12_cmd_cmd_xs1 <= 1'h0; + robEntries_12_cmd_cmd_xs2 <= 1'h0; + robEntries_12_cmd_cmd_rd <= 5'h0; + robEntries_12_cmd_cmd_opcode <= 7'h0; + robEntries_12_cmd_cmd_rs1Data <= 64'h0; + robEntries_12_cmd_cmd_rs2Data <= 64'h0; + robEntries_12_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_12_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_12_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_12_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_12_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_12_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_12_cmd_isFence <= 1'h0; + robEntries_12_cmd_isBarrier <= 1'h0; + robEntries_12_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_12_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_12_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_12_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_12_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_12_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_12_rob_id <= 4'h0; + robEntries_13_cmd_domain_id <= 4'h0; + robEntries_13_cmd_ball_bid <= 5'h0; + robEntries_13_cmd_cmd_raw_inst <= 32'h0; + robEntries_13_cmd_cmd_pc <= 64'h0; + robEntries_13_cmd_cmd_funct <= 7'h0; + robEntries_13_cmd_cmd_funct3 <= 3'h0; + robEntries_13_cmd_cmd_rs2 <= 5'h0; + robEntries_13_cmd_cmd_rs1 <= 5'h0; + robEntries_13_cmd_cmd_xd <= 1'h0; + robEntries_13_cmd_cmd_xs1 <= 1'h0; + robEntries_13_cmd_cmd_xs2 <= 1'h0; + robEntries_13_cmd_cmd_rd <= 5'h0; + robEntries_13_cmd_cmd_opcode <= 7'h0; + robEntries_13_cmd_cmd_rs1Data <= 64'h0; + robEntries_13_cmd_cmd_rs2Data <= 64'h0; + robEntries_13_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_13_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_13_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_13_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_13_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_13_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_13_cmd_isFence <= 1'h0; + robEntries_13_cmd_isBarrier <= 1'h0; + robEntries_13_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_13_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_13_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_13_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_13_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_13_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_13_rob_id <= 4'h0; + robEntries_14_cmd_domain_id <= 4'h0; + robEntries_14_cmd_ball_bid <= 5'h0; + robEntries_14_cmd_cmd_raw_inst <= 32'h0; + robEntries_14_cmd_cmd_pc <= 64'h0; + robEntries_14_cmd_cmd_funct <= 7'h0; + robEntries_14_cmd_cmd_funct3 <= 3'h0; + robEntries_14_cmd_cmd_rs2 <= 5'h0; + robEntries_14_cmd_cmd_rs1 <= 5'h0; + robEntries_14_cmd_cmd_xd <= 1'h0; + robEntries_14_cmd_cmd_xs1 <= 1'h0; + robEntries_14_cmd_cmd_xs2 <= 1'h0; + robEntries_14_cmd_cmd_rd <= 5'h0; + robEntries_14_cmd_cmd_opcode <= 7'h0; + robEntries_14_cmd_cmd_rs1Data <= 64'h0; + robEntries_14_cmd_cmd_rs2Data <= 64'h0; + robEntries_14_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_14_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_14_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_14_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_14_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_14_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_14_cmd_isFence <= 1'h0; + robEntries_14_cmd_isBarrier <= 1'h0; + robEntries_14_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_14_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_14_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_14_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_14_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_14_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_14_rob_id <= 4'h0; + robEntries_15_cmd_domain_id <= 4'h0; + robEntries_15_cmd_ball_bid <= 5'h0; + robEntries_15_cmd_cmd_raw_inst <= 32'h0; + robEntries_15_cmd_cmd_pc <= 64'h0; + robEntries_15_cmd_cmd_funct <= 7'h0; + robEntries_15_cmd_cmd_funct3 <= 3'h0; + robEntries_15_cmd_cmd_rs2 <= 5'h0; + robEntries_15_cmd_cmd_rs1 <= 5'h0; + robEntries_15_cmd_cmd_xd <= 1'h0; + robEntries_15_cmd_cmd_xs1 <= 1'h0; + robEntries_15_cmd_cmd_xs2 <= 1'h0; + robEntries_15_cmd_cmd_rd <= 5'h0; + robEntries_15_cmd_cmd_opcode <= 7'h0; + robEntries_15_cmd_cmd_rs1Data <= 64'h0; + robEntries_15_cmd_cmd_rs2Data <= 64'h0; + robEntries_15_cmd_bankAccess_rd_bank_0_valid <= 1'h0; + robEntries_15_cmd_bankAccess_rd_bank_0_id <= 10'h0; + robEntries_15_cmd_bankAccess_rd_bank_1_valid <= 1'h0; + robEntries_15_cmd_bankAccess_rd_bank_1_id <= 10'h0; + robEntries_15_cmd_bankAccess_wr_bank_valid <= 1'h0; + robEntries_15_cmd_bankAccess_wr_bank_id <= 10'h0; + robEntries_15_cmd_isFence <= 1'h0; + robEntries_15_cmd_isBarrier <= 1'h0; + robEntries_15_renamedBankAccess_rd_bank_0_valid <= 1'h0; + robEntries_15_renamedBankAccess_rd_bank_0_id <= 10'h0; + robEntries_15_renamedBankAccess_rd_bank_1_valid <= 1'h0; + robEntries_15_renamedBankAccess_rd_bank_1_id <= 10'h0; + robEntries_15_renamedBankAccess_wr_bank_valid <= 1'h0; + robEntries_15_renamedBankAccess_wr_bank_id <= 10'h0; + robEntries_15_rob_id <= 4'h0; + robValid_0 <= 1'h0; + robValid_1 <= 1'h0; + robValid_2 <= 1'h0; + robValid_3 <= 1'h0; + robValid_4 <= 1'h0; + robValid_5 <= 1'h0; + robValid_6 <= 1'h0; + robValid_7 <= 1'h0; + robValid_8 <= 1'h0; + robValid_9 <= 1'h0; + robValid_10 <= 1'h0; + robValid_11 <= 1'h0; + robValid_12 <= 1'h0; + robValid_13 <= 1'h0; + robValid_14 <= 1'h0; + robValid_15 <= 1'h0; + robIssued_0 <= 1'h0; + robIssued_1 <= 1'h0; + robIssued_2 <= 1'h0; + robIssued_3 <= 1'h0; + robIssued_4 <= 1'h0; + robIssued_5 <= 1'h0; + robIssued_6 <= 1'h0; + robIssued_7 <= 1'h0; + robIssued_8 <= 1'h0; + robIssued_9 <= 1'h0; + robIssued_10 <= 1'h0; + robIssued_11 <= 1'h0; + robIssued_12 <= 1'h0; + robIssued_13 <= 1'h0; + robIssued_14 <= 1'h0; + robIssued_15 <= 1'h0; + robComplete_0 <= 1'h0; + robComplete_1 <= 1'h0; + robComplete_2 <= 1'h0; + robComplete_3 <= 1'h0; + robComplete_4 <= 1'h0; + robComplete_5 <= 1'h0; + robComplete_6 <= 1'h0; + robComplete_7 <= 1'h0; + robComplete_8 <= 1'h0; + robComplete_9 <= 1'h0; + robComplete_10 <= 1'h0; + robComplete_11 <= 1'h0; + robComplete_12 <= 1'h0; + robComplete_13 <= 1'h0; + robComplete_14 <= 1'h0; + robComplete_15 <= 1'h0; + instIds_0 <= 64'h0; + instIds_1 <= 64'h0; + instIds_2 <= 64'h0; + instIds_3 <= 64'h0; + instIds_4 <= 64'h0; + instIds_5 <= 64'h0; + instIds_6 <= 64'h0; + instIds_7 <= 64'h0; + instIds_8 <= 64'h0; + instIds_9 <= 64'h0; + instIds_10 <= 64'h0; + instIds_11 <= 64'h0; + instIds_12 <= 64'h0; + instIds_13 <= 64'h0; + instIds_14 <= 64'h0; + instIds_15 <= 64'h0; + nextInstId <= 64'h1; + ptr <= 4'h0; + tailPtr <= 4'h0; + issuedCount <= 5'h0; + bankCols_0 <= 4'h0; + bankCols_1 <= 4'h0; + bankCols_2 <= 4'h0; + bankCols_3 <= 4'h0; + bankCols_4 <= 4'h0; + bankCols_5 <= 4'h0; + bankCols_6 <= 4'h0; + bankCols_7 <= 4'h0; + bankCols_8 <= 4'h0; + bankCols_9 <= 4'h0; + bankCols_10 <= 4'h0; + bankCols_11 <= 4'h0; + bankCols_12 <= 4'h0; + bankCols_13 <= 4'h0; + bankCols_14 <= 4'h0; + bankCols_15 <= 4'h0; + vbankBusy <= 16'h0; + dependencyMask_0 <= 16'h0; + dependencyMask_1 <= 16'h0; + dependencyMask_2 <= 16'h0; + dependencyMask_3 <= 16'h0; + dependencyMask_4 <= 16'h0; + dependencyMask_5 <= 16'h0; + dependencyMask_6 <= 16'h0; + dependencyMask_7 <= 16'h0; + dependencyMask_8 <= 16'h0; + dependencyMask_9 <= 16'h0; + dependencyMask_10 <= 16'h0; + dependencyMask_11 <= 16'h0; + dependencyMask_12 <= 16'h0; + dependencyMask_13 <= 16'h0; + dependencyMask_14 <= 16'h0; + dependencyMask_15 <= 16'h0; + issueStageValid <= 1'h0; + issuePtrValid <= 1'h0; + end + else begin + automatic logic _entryIsConfig_0_T = robEntries_0_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_0 = + _entryIsConfig_0_T & robEntries_0_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_1_T = robEntries_1_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_1 = + _entryIsConfig_1_T & robEntries_1_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_2_T = robEntries_2_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_2 = + _entryIsConfig_2_T & robEntries_2_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_3_T = robEntries_3_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_3 = + _entryIsConfig_3_T & robEntries_3_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_4_T = robEntries_4_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_4 = + _entryIsConfig_4_T & robEntries_4_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_5_T = robEntries_5_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_5 = + _entryIsConfig_5_T & robEntries_5_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_6_T = robEntries_6_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_6 = + _entryIsConfig_6_T & robEntries_6_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_7_T = robEntries_7_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_7 = + _entryIsConfig_7_T & robEntries_7_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_8_T = robEntries_8_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_8 = + _entryIsConfig_8_T & robEntries_8_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_9_T = robEntries_9_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_9 = + _entryIsConfig_9_T & robEntries_9_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_10_T = robEntries_10_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_10 = + _entryIsConfig_10_T & robEntries_10_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_11_T = robEntries_11_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_11 = + _entryIsConfig_11_T & robEntries_11_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_12_T = robEntries_12_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_12 = + _entryIsConfig_12_T & robEntries_12_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_13_T = robEntries_13_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_13 = + _entryIsConfig_13_T & robEntries_13_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_14_T = robEntries_14_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_14 = + _entryIsConfig_14_T & robEntries_14_cmd_cmd_funct == 7'h20; + automatic logic _entryIsConfig_15_T = robEntries_15_cmd_domain_id == 4'h1; + automatic logic entryIsConfig_15 = + _entryIsConfig_15_T & robEntries_15_cmd_cmd_funct == 7'h20; + automatic logic [15:0] allocReadMask = + (io_alloc_bits_bankAccess_rd_bank_0_valid + & io_alloc_bits_bankAccess_rd_bank_0_id < 10'h10 + ? 16'h1 << io_alloc_bits_bankAccess_rd_bank_0_id[3:0] + : 16'h0) + | (io_alloc_bits_bankAccess_rd_bank_1_valid + & io_alloc_bits_bankAccess_rd_bank_1_id < 10'h10 + ? 16'h1 << io_alloc_bits_bankAccess_rd_bank_1_id[3:0] + : 16'h0); + automatic logic [15:0] allocWriteMask = + io_alloc_bits_bankAccess_wr_bank_valid + & io_alloc_bits_bankAccess_wr_bank_id < 10'h10 + ? 16'h1 << io_alloc_bits_bankAccess_wr_bank_id[3:0] + : 16'h0; + automatic logic allocIsConfig = + io_alloc_bits_domain_id == 4'h1 & io_alloc_bits_cmd_funct == 7'h20; + automatic logic allocIsBall = io_alloc_bits_domain_id == 4'h3; + automatic logic [15:0] _configConflict_T_92 = allocReadMask | allocWriteMask; + automatic logic [15:0] allocDependencies; + automatic logic [63:0] _instIds_T; + automatic logic _GEN_20 = _isAllocatedSlot_T_30 & ~(|tailPtr); + automatic logic _GEN_21 = _isAllocatedSlot_T_30 & tailPtr == 4'h1; + automatic logic _GEN_22 = _isAllocatedSlot_T_30 & tailPtr == 4'h2; + automatic logic _GEN_23 = _isAllocatedSlot_T_30 & tailPtr == 4'h3; + automatic logic _GEN_24 = _isAllocatedSlot_T_30 & tailPtr == 4'h4; + automatic logic _GEN_25 = _isAllocatedSlot_T_30 & tailPtr == 4'h5; + automatic logic _GEN_26 = _isAllocatedSlot_T_30 & tailPtr == 4'h6; + automatic logic _GEN_27 = _isAllocatedSlot_T_30 & tailPtr == 4'h7; + automatic logic _GEN_28 = _isAllocatedSlot_T_30 & tailPtr == 4'h8; + automatic logic _GEN_29 = _isAllocatedSlot_T_30 & tailPtr == 4'h9; + automatic logic _GEN_30 = _isAllocatedSlot_T_30 & tailPtr == 4'hA; + automatic logic _GEN_31 = _isAllocatedSlot_T_30 & tailPtr == 4'hB; + automatic logic _GEN_32 = _isAllocatedSlot_T_30 & tailPtr == 4'hC; + automatic logic _GEN_33 = _isAllocatedSlot_T_30 & tailPtr == 4'hD; + automatic logic _GEN_34 = _isAllocatedSlot_T_30 & tailPtr == 4'hE; + automatic logic _GEN_35 = _isAllocatedSlot_T_30 & (&tailPtr); + automatic logic [15:0] completedBitMask = + io_complete_valid ? 16'h1 << io_complete_bits : 16'h0; + automatic logic [3:0] _GEN_36; + automatic logic _GEN_37; + automatic logic [3:0] _GEN_38; + automatic logic _GEN_39; + automatic logic [3:0] _GEN_40; + automatic logic _GEN_41; + automatic logic [3:0] _GEN_42; + automatic logic _GEN_43; + automatic logic [3:0] _GEN_44; + automatic logic _GEN_45; + automatic logic [3:0] _GEN_46; + automatic logic _GEN_47; + automatic logic [3:0] _GEN_48; + automatic logic _GEN_49; + automatic logic [3:0] _GEN_50; + automatic logic _GEN_51; + automatic logic [3:0] _GEN_52; + automatic logic _GEN_53; + automatic logic [3:0] _GEN_54; + automatic logic _GEN_55; + automatic logic [3:0] _GEN_56; + automatic logic _GEN_57; + automatic logic [3:0] _GEN_58; + automatic logic _GEN_59; + automatic logic [3:0] _GEN_60; + automatic logic _GEN_61; + automatic logic [3:0] _GEN_62; + automatic logic _GEN_63; + automatic logic [3:0] _GEN_64; + automatic logic _GEN_65; + automatic logic [3:0] _GEN_66; + automatic logic _GEN_67 = + commitMask_15 & _entryIsConfig_15_T & robEntries_15_cmd_cmd_funct == 7'h20; + automatic logic [15:0] configEntryMask = + {entryIsConfig_15, + entryIsConfig_14, + entryIsConfig_13, + entryIsConfig_12, + entryIsConfig_11, + entryIsConfig_10, + entryIsConfig_9, + entryIsConfig_8, + entryIsConfig_7, + entryIsConfig_6, + entryIsConfig_5, + entryIsConfig_4, + entryIsConfig_3, + entryIsConfig_2, + entryIsConfig_1, + entryIsConfig_0}; + automatic logic isAllocatedSlot = _isAllocatedSlot_T_30 & ~(|tailPtr); + automatic logic [15:0] clearMask; + automatic logic isAllocatedSlot_1 = _isAllocatedSlot_T_30 & tailPtr == 4'h1; + automatic logic [15:0] clearMask_1; + automatic logic isAllocatedSlot_2 = _isAllocatedSlot_T_30 & tailPtr == 4'h2; + automatic logic [15:0] clearMask_2; + automatic logic isAllocatedSlot_3 = _isAllocatedSlot_T_30 & tailPtr == 4'h3; + automatic logic [15:0] clearMask_3; + automatic logic isAllocatedSlot_4 = _isAllocatedSlot_T_30 & tailPtr == 4'h4; + automatic logic [15:0] clearMask_4; + automatic logic isAllocatedSlot_5 = _isAllocatedSlot_T_30 & tailPtr == 4'h5; + automatic logic [15:0] clearMask_5; + automatic logic isAllocatedSlot_6 = _isAllocatedSlot_T_30 & tailPtr == 4'h6; + automatic logic [15:0] clearMask_6; + automatic logic isAllocatedSlot_7 = _isAllocatedSlot_T_30 & tailPtr == 4'h7; + automatic logic [15:0] clearMask_7; + automatic logic isAllocatedSlot_8 = _isAllocatedSlot_T_30 & tailPtr == 4'h8; + automatic logic [15:0] clearMask_8; + automatic logic isAllocatedSlot_9 = _isAllocatedSlot_T_30 & tailPtr == 4'h9; + automatic logic [15:0] clearMask_9; + automatic logic isAllocatedSlot_10 = _isAllocatedSlot_T_30 & tailPtr == 4'hA; + automatic logic [15:0] clearMask_10; + automatic logic isAllocatedSlot_11 = _isAllocatedSlot_T_30 & tailPtr == 4'hB; + automatic logic [15:0] clearMask_11; + automatic logic isAllocatedSlot_12 = _isAllocatedSlot_T_30 & tailPtr == 4'hC; + automatic logic [15:0] clearMask_12; + automatic logic isAllocatedSlot_13 = _isAllocatedSlot_T_30 & tailPtr == 4'hD; + automatic logic [15:0] clearMask_13; + automatic logic isAllocatedSlot_14 = _isAllocatedSlot_T_30 & tailPtr == 4'hE; + automatic logic [15:0] clearMask_14; + automatic logic isAllocatedSlot_15 = _isAllocatedSlot_T_30 & (&tailPtr); + automatic logic [15:0] clearMask_15; + allocDependencies = + {robValid_15 & ~robComplete_15 + & ((|(allocReadMask & entryRawWrites_15 | allocWriteMask & vbankMasks_15)) + | allocIsBall & robEntries_15_cmd_domain_id == 4'h3 + & robEntries_15_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_15 + & (allocIsConfig & entryIsConfig_15 | (allocIsConfig | entryIsConfig_15) + & (|(_configConflict_T_92 & vbankMasks_15))), + robValid_14 & ~robComplete_14 + & ((|(allocReadMask & entryRawWrites_14 | allocWriteMask & vbankMasks_14)) + | allocIsBall & robEntries_14_cmd_domain_id == 4'h3 + & robEntries_14_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_14 + & (allocIsConfig & entryIsConfig_14 | (allocIsConfig | entryIsConfig_14) + & (|(_configConflict_T_92 & vbankMasks_14))), + robValid_13 & ~robComplete_13 + & ((|(allocReadMask & entryRawWrites_13 | allocWriteMask & vbankMasks_13)) + | allocIsBall & robEntries_13_cmd_domain_id == 4'h3 + & robEntries_13_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_13 + & (allocIsConfig & entryIsConfig_13 | (allocIsConfig | entryIsConfig_13) + & (|(_configConflict_T_92 & vbankMasks_13))), + robValid_12 & ~robComplete_12 + & ((|(allocReadMask & entryRawWrites_12 | allocWriteMask & vbankMasks_12)) + | allocIsBall & robEntries_12_cmd_domain_id == 4'h3 + & robEntries_12_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_12 + & (allocIsConfig & entryIsConfig_12 | (allocIsConfig | entryIsConfig_12) + & (|(_configConflict_T_92 & vbankMasks_12))), + robValid_11 & ~robComplete_11 + & ((|(allocReadMask & entryRawWrites_11 | allocWriteMask & vbankMasks_11)) + | allocIsBall & robEntries_11_cmd_domain_id == 4'h3 + & robEntries_11_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_11 + & (allocIsConfig & entryIsConfig_11 | (allocIsConfig | entryIsConfig_11) + & (|(_configConflict_T_92 & vbankMasks_11))), + robValid_10 & ~robComplete_10 + & ((|(allocReadMask & entryRawWrites_10 | allocWriteMask & vbankMasks_10)) + | allocIsBall & robEntries_10_cmd_domain_id == 4'h3 + & robEntries_10_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_10 + & (allocIsConfig & entryIsConfig_10 | (allocIsConfig | entryIsConfig_10) + & (|(_configConflict_T_92 & vbankMasks_10))), + robValid_9 & ~robComplete_9 + & ((|(allocReadMask & entryRawWrites_9 | allocWriteMask & vbankMasks_9)) + | allocIsBall & robEntries_9_cmd_domain_id == 4'h3 + & robEntries_9_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_9 + & (allocIsConfig & entryIsConfig_9 | (allocIsConfig | entryIsConfig_9) + & (|(_configConflict_T_92 & vbankMasks_9))), + robValid_8 & ~robComplete_8 + & ((|(allocReadMask & entryRawWrites_8 | allocWriteMask & vbankMasks_8)) + | allocIsBall & robEntries_8_cmd_domain_id == 4'h3 + & robEntries_8_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_8 + & (allocIsConfig & entryIsConfig_8 | (allocIsConfig | entryIsConfig_8) + & (|(_configConflict_T_92 & vbankMasks_8))), + robValid_7 & ~robComplete_7 + & ((|(allocReadMask & entryRawWrites_7 | allocWriteMask & vbankMasks_7)) + | allocIsBall & robEntries_7_cmd_domain_id == 4'h3 + & robEntries_7_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_7 + & (allocIsConfig & entryIsConfig_7 | (allocIsConfig | entryIsConfig_7) + & (|(_configConflict_T_92 & vbankMasks_7))), + robValid_6 & ~robComplete_6 + & ((|(allocReadMask & entryRawWrites_6 | allocWriteMask & vbankMasks_6)) + | allocIsBall & robEntries_6_cmd_domain_id == 4'h3 + & robEntries_6_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_6 + & (allocIsConfig & entryIsConfig_6 | (allocIsConfig | entryIsConfig_6) + & (|(_configConflict_T_92 & vbankMasks_6))), + robValid_5 & ~robComplete_5 + & ((|(allocReadMask & entryRawWrites_5 | allocWriteMask & vbankMasks_5)) + | allocIsBall & robEntries_5_cmd_domain_id == 4'h3 + & robEntries_5_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_5 + & (allocIsConfig & entryIsConfig_5 | (allocIsConfig | entryIsConfig_5) + & (|(_configConflict_T_92 & vbankMasks_5))), + robValid_4 & ~robComplete_4 + & ((|(allocReadMask & entryRawWrites_4 | allocWriteMask & vbankMasks_4)) + | allocIsBall & robEntries_4_cmd_domain_id == 4'h3 + & robEntries_4_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_4 + & (allocIsConfig & entryIsConfig_4 | (allocIsConfig | entryIsConfig_4) + & (|(_configConflict_T_92 & vbankMasks_4))), + robValid_3 & ~robComplete_3 + & ((|(allocReadMask & entryRawWrites_3 | allocWriteMask & vbankMasks_3)) + | allocIsBall & robEntries_3_cmd_domain_id == 4'h3 + & robEntries_3_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_3 + & (allocIsConfig & entryIsConfig_3 | (allocIsConfig | entryIsConfig_3) + & (|(_configConflict_T_92 & vbankMasks_3))), + robValid_2 & ~robComplete_2 + & ((|(allocReadMask & entryRawWrites_2 | allocWriteMask & vbankMasks_2)) + | allocIsBall & robEntries_2_cmd_domain_id == 4'h3 + & robEntries_2_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_2 + & (allocIsConfig & entryIsConfig_2 | (allocIsConfig | entryIsConfig_2) + & (|(_configConflict_T_92 & vbankMasks_2))), + robValid_1 & ~robComplete_1 + & ((|(allocReadMask & entryRawWrites_1 | allocWriteMask & vbankMasks_1)) + | allocIsBall & robEntries_1_cmd_domain_id == 4'h3 + & robEntries_1_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_1 + & (allocIsConfig & entryIsConfig_1 | (allocIsConfig | entryIsConfig_1) + & (|(_configConflict_T_92 & vbankMasks_1))), + robValid_0 & ~robComplete_0 + & ((|(allocReadMask & entryRawWrites_0 | allocWriteMask & olderUseMask)) + | allocIsBall & robEntries_0_cmd_domain_id == 4'h3 + & robEntries_0_cmd_ball_bid == io_alloc_bits_ball_bid) | robValid_0 + & (allocIsConfig & entryIsConfig_0 | (allocIsConfig | entryIsConfig_0) + & (|(_configConflict_T_92 & olderUseMask)))}; + _instIds_T = (|io_alloc_bits_cmd_pc) ? nextInstId : 64'h0; + _GEN_36 = + robEntries_0_cmd_cmd_rs2Data[10] + ? (robEntries_0_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_0_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_37 = commitMask_0 & _entryIsConfig_0_T & robEntries_0_cmd_cmd_funct == 7'h20; + _GEN_38 = + robEntries_1_cmd_cmd_rs2Data[10] + ? (robEntries_1_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_1_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_39 = commitMask_1 & _entryIsConfig_1_T & robEntries_1_cmd_cmd_funct == 7'h20; + _GEN_40 = + robEntries_2_cmd_cmd_rs2Data[10] + ? (robEntries_2_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_2_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_41 = commitMask_2 & _entryIsConfig_2_T & robEntries_2_cmd_cmd_funct == 7'h20; + _GEN_42 = + robEntries_3_cmd_cmd_rs2Data[10] + ? (robEntries_3_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_3_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_43 = commitMask_3 & _entryIsConfig_3_T & robEntries_3_cmd_cmd_funct == 7'h20; + _GEN_44 = + robEntries_4_cmd_cmd_rs2Data[10] + ? (robEntries_4_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_4_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_45 = commitMask_4 & _entryIsConfig_4_T & robEntries_4_cmd_cmd_funct == 7'h20; + _GEN_46 = + robEntries_5_cmd_cmd_rs2Data[10] + ? (robEntries_5_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_5_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_47 = commitMask_5 & _entryIsConfig_5_T & robEntries_5_cmd_cmd_funct == 7'h20; + _GEN_48 = + robEntries_6_cmd_cmd_rs2Data[10] + ? (robEntries_6_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_6_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_49 = commitMask_6 & _entryIsConfig_6_T & robEntries_6_cmd_cmd_funct == 7'h20; + _GEN_50 = + robEntries_7_cmd_cmd_rs2Data[10] + ? (robEntries_7_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_7_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_51 = commitMask_7 & _entryIsConfig_7_T & robEntries_7_cmd_cmd_funct == 7'h20; + _GEN_52 = + robEntries_8_cmd_cmd_rs2Data[10] + ? (robEntries_8_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_8_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_53 = commitMask_8 & _entryIsConfig_8_T & robEntries_8_cmd_cmd_funct == 7'h20; + _GEN_54 = + robEntries_9_cmd_cmd_rs2Data[10] + ? (robEntries_9_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_9_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_55 = commitMask_9 & _entryIsConfig_9_T & robEntries_9_cmd_cmd_funct == 7'h20; + _GEN_56 = + robEntries_10_cmd_cmd_rs2Data[10] + ? (robEntries_10_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_10_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_57 = + commitMask_10 & _entryIsConfig_10_T & robEntries_10_cmd_cmd_funct == 7'h20; + _GEN_58 = + robEntries_11_cmd_cmd_rs2Data[10] + ? (robEntries_11_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_11_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_59 = + commitMask_11 & _entryIsConfig_11_T & robEntries_11_cmd_cmd_funct == 7'h20; + _GEN_60 = + robEntries_12_cmd_cmd_rs2Data[10] + ? (robEntries_12_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_12_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_61 = + commitMask_12 & _entryIsConfig_12_T & robEntries_12_cmd_cmd_funct == 7'h20; + _GEN_62 = + robEntries_13_cmd_cmd_rs2Data[10] + ? (robEntries_13_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_13_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_63 = + commitMask_13 & _entryIsConfig_13_T & robEntries_13_cmd_cmd_funct == 7'h20; + _GEN_64 = + robEntries_14_cmd_cmd_rs2Data[10] + ? (robEntries_14_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_14_cmd_cmd_rs2Data[8:5]) + : 4'h0; + _GEN_65 = + commitMask_14 & _entryIsConfig_14_T & robEntries_14_cmd_cmd_funct == 7'h20; + _GEN_66 = + robEntries_15_cmd_cmd_rs2Data[10] + ? (robEntries_15_cmd_cmd_rs2Data[9:5] == 5'h0 + ? 4'h8 + : robEntries_15_cmd_cmd_rs2Data[8:5]) + : 4'h0; + clearMask = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask | {16{isAllocatedSlot ? allocIsConfig : entryIsConfig_0}}); + clearMask_1 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask | {16{isAllocatedSlot_1 ? allocIsConfig : entryIsConfig_1}}); + clearMask_2 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask | {16{isAllocatedSlot_2 ? allocIsConfig : entryIsConfig_2}}); + clearMask_3 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask | {16{isAllocatedSlot_3 ? allocIsConfig : entryIsConfig_3}}); + clearMask_4 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask | {16{isAllocatedSlot_4 ? allocIsConfig : entryIsConfig_4}}); + clearMask_5 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask | {16{isAllocatedSlot_5 ? allocIsConfig : entryIsConfig_5}}); + clearMask_6 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask | {16{isAllocatedSlot_6 ? allocIsConfig : entryIsConfig_6}}); + clearMask_7 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask | {16{isAllocatedSlot_7 ? allocIsConfig : entryIsConfig_7}}); + clearMask_8 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask | {16{isAllocatedSlot_8 ? allocIsConfig : entryIsConfig_8}}); + clearMask_9 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask | {16{isAllocatedSlot_9 ? allocIsConfig : entryIsConfig_9}}); + clearMask_10 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask + | {16{isAllocatedSlot_10 ? allocIsConfig : entryIsConfig_10}}); + clearMask_11 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask + | {16{isAllocatedSlot_11 ? allocIsConfig : entryIsConfig_11}}); + clearMask_12 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask + | {16{isAllocatedSlot_12 ? allocIsConfig : entryIsConfig_12}}); + clearMask_13 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask + | {16{isAllocatedSlot_13 ? allocIsConfig : entryIsConfig_13}}); + clearMask_14 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask + | {16{isAllocatedSlot_14 ? allocIsConfig : entryIsConfig_14}}); + clearMask_15 = + {commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0} | completedBitMask + & ~(configEntryMask + | {16{isAllocatedSlot_15 ? allocIsConfig : entryIsConfig_15}}); + if (_GEN_20) begin + robEntries_0_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_0_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_0_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_0_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_0_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_0_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_0_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_0_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_0_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_0_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_0_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_0_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_0_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_0_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_0_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_0_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_0_cmd_bankAccess_rd_bank_0_id <= io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_0_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_0_cmd_bankAccess_rd_bank_1_id <= io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_0_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_0_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_0_cmd_isFence <= io_alloc_bits_isFence; + robEntries_0_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_0_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_0_renamedBankAccess_rd_bank_0_id <= _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_0_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_0_renamedBankAccess_rd_bank_1_id <= _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_0_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_0_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_0_rob_id <= tailPtr; + instIds_0 <= _instIds_T; + end + if (_GEN_21) begin + robEntries_1_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_1_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_1_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_1_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_1_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_1_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_1_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_1_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_1_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_1_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_1_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_1_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_1_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_1_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_1_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_1_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_1_cmd_bankAccess_rd_bank_0_id <= io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_1_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_1_cmd_bankAccess_rd_bank_1_id <= io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_1_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_1_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_1_cmd_isFence <= io_alloc_bits_isFence; + robEntries_1_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_1_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_1_renamedBankAccess_rd_bank_0_id <= _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_1_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_1_renamedBankAccess_rd_bank_1_id <= _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_1_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_1_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_1_rob_id <= tailPtr; + instIds_1 <= _instIds_T; + end + if (_GEN_22) begin + robEntries_2_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_2_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_2_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_2_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_2_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_2_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_2_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_2_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_2_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_2_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_2_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_2_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_2_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_2_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_2_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_2_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_2_cmd_bankAccess_rd_bank_0_id <= io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_2_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_2_cmd_bankAccess_rd_bank_1_id <= io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_2_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_2_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_2_cmd_isFence <= io_alloc_bits_isFence; + robEntries_2_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_2_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_2_renamedBankAccess_rd_bank_0_id <= _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_2_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_2_renamedBankAccess_rd_bank_1_id <= _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_2_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_2_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_2_rob_id <= tailPtr; + instIds_2 <= _instIds_T; + end + if (_GEN_23) begin + robEntries_3_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_3_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_3_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_3_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_3_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_3_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_3_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_3_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_3_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_3_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_3_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_3_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_3_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_3_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_3_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_3_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_3_cmd_bankAccess_rd_bank_0_id <= io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_3_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_3_cmd_bankAccess_rd_bank_1_id <= io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_3_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_3_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_3_cmd_isFence <= io_alloc_bits_isFence; + robEntries_3_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_3_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_3_renamedBankAccess_rd_bank_0_id <= _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_3_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_3_renamedBankAccess_rd_bank_1_id <= _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_3_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_3_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_3_rob_id <= tailPtr; + instIds_3 <= _instIds_T; + end + if (_GEN_24) begin + robEntries_4_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_4_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_4_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_4_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_4_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_4_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_4_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_4_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_4_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_4_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_4_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_4_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_4_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_4_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_4_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_4_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_4_cmd_bankAccess_rd_bank_0_id <= io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_4_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_4_cmd_bankAccess_rd_bank_1_id <= io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_4_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_4_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_4_cmd_isFence <= io_alloc_bits_isFence; + robEntries_4_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_4_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_4_renamedBankAccess_rd_bank_0_id <= _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_4_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_4_renamedBankAccess_rd_bank_1_id <= _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_4_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_4_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_4_rob_id <= tailPtr; + instIds_4 <= _instIds_T; + end + if (_GEN_25) begin + robEntries_5_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_5_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_5_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_5_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_5_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_5_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_5_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_5_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_5_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_5_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_5_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_5_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_5_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_5_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_5_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_5_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_5_cmd_bankAccess_rd_bank_0_id <= io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_5_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_5_cmd_bankAccess_rd_bank_1_id <= io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_5_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_5_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_5_cmd_isFence <= io_alloc_bits_isFence; + robEntries_5_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_5_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_5_renamedBankAccess_rd_bank_0_id <= _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_5_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_5_renamedBankAccess_rd_bank_1_id <= _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_5_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_5_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_5_rob_id <= tailPtr; + instIds_5 <= _instIds_T; + end + if (_GEN_26) begin + robEntries_6_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_6_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_6_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_6_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_6_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_6_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_6_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_6_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_6_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_6_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_6_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_6_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_6_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_6_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_6_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_6_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_6_cmd_bankAccess_rd_bank_0_id <= io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_6_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_6_cmd_bankAccess_rd_bank_1_id <= io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_6_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_6_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_6_cmd_isFence <= io_alloc_bits_isFence; + robEntries_6_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_6_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_6_renamedBankAccess_rd_bank_0_id <= _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_6_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_6_renamedBankAccess_rd_bank_1_id <= _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_6_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_6_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_6_rob_id <= tailPtr; + instIds_6 <= _instIds_T; + end + if (_GEN_27) begin + robEntries_7_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_7_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_7_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_7_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_7_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_7_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_7_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_7_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_7_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_7_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_7_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_7_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_7_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_7_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_7_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_7_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_7_cmd_bankAccess_rd_bank_0_id <= io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_7_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_7_cmd_bankAccess_rd_bank_1_id <= io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_7_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_7_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_7_cmd_isFence <= io_alloc_bits_isFence; + robEntries_7_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_7_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_7_renamedBankAccess_rd_bank_0_id <= _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_7_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_7_renamedBankAccess_rd_bank_1_id <= _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_7_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_7_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_7_rob_id <= tailPtr; + instIds_7 <= _instIds_T; + end + if (_GEN_28) begin + robEntries_8_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_8_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_8_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_8_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_8_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_8_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_8_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_8_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_8_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_8_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_8_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_8_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_8_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_8_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_8_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_8_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_8_cmd_bankAccess_rd_bank_0_id <= io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_8_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_8_cmd_bankAccess_rd_bank_1_id <= io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_8_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_8_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_8_cmd_isFence <= io_alloc_bits_isFence; + robEntries_8_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_8_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_8_renamedBankAccess_rd_bank_0_id <= _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_8_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_8_renamedBankAccess_rd_bank_1_id <= _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_8_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_8_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_8_rob_id <= tailPtr; + instIds_8 <= _instIds_T; + end + if (_GEN_29) begin + robEntries_9_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_9_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_9_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_9_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_9_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_9_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_9_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_9_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_9_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_9_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_9_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_9_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_9_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_9_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_9_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_9_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_9_cmd_bankAccess_rd_bank_0_id <= io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_9_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_9_cmd_bankAccess_rd_bank_1_id <= io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_9_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_9_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_9_cmd_isFence <= io_alloc_bits_isFence; + robEntries_9_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_9_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_9_renamedBankAccess_rd_bank_0_id <= _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_9_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_9_renamedBankAccess_rd_bank_1_id <= _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_9_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_9_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_9_rob_id <= tailPtr; + instIds_9 <= _instIds_T; + end + if (_GEN_30) begin + robEntries_10_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_10_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_10_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_10_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_10_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_10_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_10_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_10_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_10_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_10_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_10_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_10_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_10_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_10_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_10_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_10_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_10_cmd_bankAccess_rd_bank_0_id <= + io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_10_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_10_cmd_bankAccess_rd_bank_1_id <= + io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_10_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_10_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_10_cmd_isFence <= io_alloc_bits_isFence; + robEntries_10_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_10_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_10_renamedBankAccess_rd_bank_0_id <= + _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_10_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_10_renamedBankAccess_rd_bank_1_id <= + _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_10_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_10_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_10_rob_id <= tailPtr; + instIds_10 <= _instIds_T; + end + if (_GEN_31) begin + robEntries_11_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_11_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_11_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_11_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_11_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_11_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_11_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_11_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_11_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_11_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_11_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_11_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_11_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_11_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_11_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_11_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_11_cmd_bankAccess_rd_bank_0_id <= + io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_11_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_11_cmd_bankAccess_rd_bank_1_id <= + io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_11_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_11_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_11_cmd_isFence <= io_alloc_bits_isFence; + robEntries_11_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_11_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_11_renamedBankAccess_rd_bank_0_id <= + _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_11_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_11_renamedBankAccess_rd_bank_1_id <= + _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_11_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_11_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_11_rob_id <= tailPtr; + instIds_11 <= _instIds_T; + end + if (_GEN_32) begin + robEntries_12_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_12_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_12_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_12_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_12_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_12_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_12_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_12_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_12_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_12_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_12_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_12_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_12_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_12_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_12_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_12_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_12_cmd_bankAccess_rd_bank_0_id <= + io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_12_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_12_cmd_bankAccess_rd_bank_1_id <= + io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_12_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_12_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_12_cmd_isFence <= io_alloc_bits_isFence; + robEntries_12_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_12_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_12_renamedBankAccess_rd_bank_0_id <= + _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_12_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_12_renamedBankAccess_rd_bank_1_id <= + _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_12_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_12_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_12_rob_id <= tailPtr; + instIds_12 <= _instIds_T; + end + if (_GEN_33) begin + robEntries_13_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_13_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_13_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_13_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_13_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_13_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_13_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_13_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_13_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_13_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_13_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_13_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_13_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_13_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_13_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_13_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_13_cmd_bankAccess_rd_bank_0_id <= + io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_13_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_13_cmd_bankAccess_rd_bank_1_id <= + io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_13_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_13_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_13_cmd_isFence <= io_alloc_bits_isFence; + robEntries_13_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_13_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_13_renamedBankAccess_rd_bank_0_id <= + _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_13_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_13_renamedBankAccess_rd_bank_1_id <= + _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_13_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_13_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_13_rob_id <= tailPtr; + instIds_13 <= _instIds_T; + end + if (_GEN_34) begin + robEntries_14_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_14_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_14_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_14_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_14_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_14_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_14_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_14_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_14_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_14_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_14_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_14_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_14_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_14_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_14_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_14_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_14_cmd_bankAccess_rd_bank_0_id <= + io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_14_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_14_cmd_bankAccess_rd_bank_1_id <= + io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_14_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_14_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_14_cmd_isFence <= io_alloc_bits_isFence; + robEntries_14_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_14_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_14_renamedBankAccess_rd_bank_0_id <= + _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_14_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_14_renamedBankAccess_rd_bank_1_id <= + _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_14_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_14_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_14_rob_id <= tailPtr; + instIds_14 <= _instIds_T; + end + if (_GEN_35) begin + robEntries_15_cmd_domain_id <= io_alloc_bits_domain_id; + robEntries_15_cmd_ball_bid <= io_alloc_bits_ball_bid; + robEntries_15_cmd_cmd_raw_inst <= io_alloc_bits_cmd_raw_inst; + robEntries_15_cmd_cmd_pc <= io_alloc_bits_cmd_pc; + robEntries_15_cmd_cmd_funct <= io_alloc_bits_cmd_funct; + robEntries_15_cmd_cmd_funct3 <= io_alloc_bits_cmd_funct3; + robEntries_15_cmd_cmd_rs2 <= io_alloc_bits_cmd_rs2; + robEntries_15_cmd_cmd_rs1 <= io_alloc_bits_cmd_rs1; + robEntries_15_cmd_cmd_xd <= io_alloc_bits_cmd_xd; + robEntries_15_cmd_cmd_xs1 <= io_alloc_bits_cmd_xs1; + robEntries_15_cmd_cmd_xs2 <= io_alloc_bits_cmd_xs2; + robEntries_15_cmd_cmd_rd <= io_alloc_bits_cmd_rd; + robEntries_15_cmd_cmd_opcode <= io_alloc_bits_cmd_opcode; + robEntries_15_cmd_cmd_rs1Data <= io_alloc_bits_cmd_rs1Data; + robEntries_15_cmd_cmd_rs2Data <= io_alloc_bits_cmd_rs2Data; + robEntries_15_cmd_bankAccess_rd_bank_0_valid <= + io_alloc_bits_bankAccess_rd_bank_0_valid; + robEntries_15_cmd_bankAccess_rd_bank_0_id <= + io_alloc_bits_bankAccess_rd_bank_0_id; + robEntries_15_cmd_bankAccess_rd_bank_1_valid <= + io_alloc_bits_bankAccess_rd_bank_1_valid; + robEntries_15_cmd_bankAccess_rd_bank_1_id <= + io_alloc_bits_bankAccess_rd_bank_1_id; + robEntries_15_cmd_bankAccess_wr_bank_valid <= + io_alloc_bits_bankAccess_wr_bank_valid; + robEntries_15_cmd_bankAccess_wr_bank_id <= io_alloc_bits_bankAccess_wr_bank_id; + robEntries_15_cmd_isFence <= io_alloc_bits_isFence; + robEntries_15_cmd_isBarrier <= io_alloc_bits_isBarrier; + robEntries_15_renamedBankAccess_rd_bank_0_valid <= + _bat_io_alloc_renamed_rd_bank_0_valid; + robEntries_15_renamedBankAccess_rd_bank_0_id <= + _bat_io_alloc_renamed_rd_bank_0_id; + robEntries_15_renamedBankAccess_rd_bank_1_valid <= + _bat_io_alloc_renamed_rd_bank_1_valid; + robEntries_15_renamedBankAccess_rd_bank_1_id <= + _bat_io_alloc_renamed_rd_bank_1_id; + robEntries_15_renamedBankAccess_wr_bank_valid <= + _bat_io_alloc_renamed_wr_bank_valid; + robEntries_15_renamedBankAccess_wr_bank_id <= _bat_io_alloc_renamed_wr_bank_id; + robEntries_15_rob_id <= tailPtr; + instIds_15 <= _instIds_T; + end + robValid_0 <= ~commitMask_0 & (_GEN_20 | robValid_0); + robValid_1 <= ~commitMask_1 & (_GEN_21 | robValid_1); + robValid_2 <= ~commitMask_2 & (_GEN_22 | robValid_2); + robValid_3 <= ~commitMask_3 & (_GEN_23 | robValid_3); + robValid_4 <= ~commitMask_4 & (_GEN_24 | robValid_4); + robValid_5 <= ~commitMask_5 & (_GEN_25 | robValid_5); + robValid_6 <= ~commitMask_6 & (_GEN_26 | robValid_6); + robValid_7 <= ~commitMask_7 & (_GEN_27 | robValid_7); + robValid_8 <= ~commitMask_8 & (_GEN_28 | robValid_8); + robValid_9 <= ~commitMask_9 & (_GEN_29 | robValid_9); + robValid_10 <= ~commitMask_10 & (_GEN_30 | robValid_10); + robValid_11 <= ~commitMask_11 & (_GEN_31 | robValid_11); + robValid_12 <= ~commitMask_12 & (_GEN_32 | robValid_12); + robValid_13 <= ~commitMask_13 & (_GEN_33 | robValid_13); + robValid_14 <= ~commitMask_14 & (_GEN_34 | robValid_14); + robValid_15 <= ~commitMask_15 & (_GEN_35 | robValid_15); + robIssued_0 <= + ~commitMask_0 & (issueLoad & _actualIssuePtr_T == 4'h0 | ~_GEN_20 & robIssued_0); + robIssued_1 <= + ~commitMask_1 & (issueLoad & _actualIssuePtr_T == 4'h1 | ~_GEN_21 & robIssued_1); + robIssued_2 <= + ~commitMask_2 & (issueLoad & _actualIssuePtr_T == 4'h2 | ~_GEN_22 & robIssued_2); + robIssued_3 <= + ~commitMask_3 & (issueLoad & _actualIssuePtr_T == 4'h3 | ~_GEN_23 & robIssued_3); + robIssued_4 <= + ~commitMask_4 & (issueLoad & _actualIssuePtr_T == 4'h4 | ~_GEN_24 & robIssued_4); + robIssued_5 <= + ~commitMask_5 & (issueLoad & _actualIssuePtr_T == 4'h5 | ~_GEN_25 & robIssued_5); + robIssued_6 <= + ~commitMask_6 & (issueLoad & _actualIssuePtr_T == 4'h6 | ~_GEN_26 & robIssued_6); + robIssued_7 <= + ~commitMask_7 & (issueLoad & _actualIssuePtr_T == 4'h7 | ~_GEN_27 & robIssued_7); + robIssued_8 <= + ~commitMask_8 & (issueLoad & _actualIssuePtr_T == 4'h8 | ~_GEN_28 & robIssued_8); + robIssued_9 <= + ~commitMask_9 & (issueLoad & _actualIssuePtr_T == 4'h9 | ~_GEN_29 & robIssued_9); + robIssued_10 <= + ~commitMask_10 + & (issueLoad & _actualIssuePtr_T == 4'hA | ~_GEN_30 & robIssued_10); + robIssued_11 <= + ~commitMask_11 + & (issueLoad & _actualIssuePtr_T == 4'hB | ~_GEN_31 & robIssued_11); + robIssued_12 <= + ~commitMask_12 + & (issueLoad & _actualIssuePtr_T == 4'hC | ~_GEN_32 & robIssued_12); + robIssued_13 <= + ~commitMask_13 + & (issueLoad & _actualIssuePtr_T == 4'hD | ~_GEN_33 & robIssued_13); + robIssued_14 <= + ~commitMask_14 + & (issueLoad & _actualIssuePtr_T == 4'hE | ~_GEN_34 & robIssued_14); + robIssued_15 <= + ~commitMask_15 & (issueLoad & (&_actualIssuePtr_T) | ~_GEN_35 & robIssued_15); + robComplete_0 <= + ~commitMask_0 + & (io_complete_valid & io_complete_bits == 4'h0 | ~_GEN_20 & robComplete_0); + robComplete_1 <= + ~commitMask_1 + & (io_complete_valid & io_complete_bits == 4'h1 | ~_GEN_21 & robComplete_1); + robComplete_2 <= + ~commitMask_2 + & (io_complete_valid & io_complete_bits == 4'h2 | ~_GEN_22 & robComplete_2); + robComplete_3 <= + ~commitMask_3 + & (io_complete_valid & io_complete_bits == 4'h3 | ~_GEN_23 & robComplete_3); + robComplete_4 <= + ~commitMask_4 + & (io_complete_valid & io_complete_bits == 4'h4 | ~_GEN_24 & robComplete_4); + robComplete_5 <= + ~commitMask_5 + & (io_complete_valid & io_complete_bits == 4'h5 | ~_GEN_25 & robComplete_5); + robComplete_6 <= + ~commitMask_6 + & (io_complete_valid & io_complete_bits == 4'h6 | ~_GEN_26 & robComplete_6); + robComplete_7 <= + ~commitMask_7 + & (io_complete_valid & io_complete_bits == 4'h7 | ~_GEN_27 & robComplete_7); + robComplete_8 <= + ~commitMask_8 + & (io_complete_valid & io_complete_bits == 4'h8 | ~_GEN_28 & robComplete_8); + robComplete_9 <= + ~commitMask_9 + & (io_complete_valid & io_complete_bits == 4'h9 | ~_GEN_29 & robComplete_9); + robComplete_10 <= + ~commitMask_10 + & (io_complete_valid & io_complete_bits == 4'hA | ~_GEN_30 & robComplete_10); + robComplete_11 <= + ~commitMask_11 + & (io_complete_valid & io_complete_bits == 4'hB | ~_GEN_31 & robComplete_11); + robComplete_12 <= + ~commitMask_12 + & (io_complete_valid & io_complete_bits == 4'hC | ~_GEN_32 & robComplete_12); + robComplete_13 <= + ~commitMask_13 + & (io_complete_valid & io_complete_bits == 4'hD | ~_GEN_33 & robComplete_13); + robComplete_14 <= + ~commitMask_14 + & (io_complete_valid & io_complete_bits == 4'hE | ~_GEN_34 & robComplete_14); + robComplete_15 <= + ~commitMask_15 + & (io_complete_valid & (&io_complete_bits) | ~_GEN_35 & robComplete_15); + if (_GEN_3) + nextInstId <= nextInstId + 64'h1; + ptr <= + ptr + + {1'h0, + {1'h0, {1'h0, commitKeep_1} + {1'h0, commitKeep_2}} + + {1'h0, {1'h0, commitKeep_3} + {1'h0, commitKeep_4}}} + + {1'h0, + {1'h0, {1'h0, commitKeep_5} + {1'h0, commitKeep_6}} + + {1'h0, {1'h0, commitKeep_7} + {1'h0, commitKeep_8}}} + + {1'h0, + {1'h0, {1'h0, commitKeep_9} + {1'h0, commitScan_9}} + + {1'h0, {1'h0, commitKeep_11} + {1'h0, commitKeep_12}}} + + {1'h0, + {1'h0, {1'h0, commitKeep_13} + {1'h0, commitKeep_14}} + + {1'h0, {1'h0, commitKeep_15} + {1'h0, commitScan_15}}}; + if (_isAllocatedSlot_T_30) begin + if (&tailPtr) + tailPtr <= 4'h0; + else + tailPtr <= tailPtr + 4'h1; + end + issuedCount <= + issuedCount + {4'h0, issueLoad} + - {4'h0, io_complete_valid & _GEN_4[io_complete_bits]}; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'h0) + bankCols_0 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'h1) + bankCols_1 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'h2) + bankCols_2 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'h3) + bankCols_3 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'h4) + bankCols_4 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'h5) + bankCols_5 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'h6) + bankCols_6 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'h7) + bankCols_7 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'h8) + bankCols_8 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'h9) + bankCols_9 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'hA) + bankCols_10 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'hB) + bankCols_11 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'hC) + bankCols_12 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'hD) + bankCols_13 <= _GEN_36; + if (_GEN_67 & robEntries_15_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_66; + else if (_GEN_65 & robEntries_14_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_64; + else if (_GEN_63 & robEntries_13_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_62; + else if (_GEN_61 & robEntries_12_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_60; + else if (_GEN_59 & robEntries_11_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_58; + else if (_GEN_57 & robEntries_10_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_56; + else if (_GEN_55 & robEntries_9_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_54; + else if (_GEN_53 & robEntries_8_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_52; + else if (_GEN_51 & robEntries_7_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_50; + else if (_GEN_49 & robEntries_6_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_48; + else if (_GEN_47 & robEntries_5_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_46; + else if (_GEN_45 & robEntries_4_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_44; + else if (_GEN_43 & robEntries_3_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_42; + else if (_GEN_41 & robEntries_2_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_40; + else if (_GEN_39 & robEntries_1_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_38; + else if (_GEN_37 & robEntries_0_cmd_bankAccess_wr_bank_id[3:0] == 4'hE) + bankCols_14 <= _GEN_36; + if (_GEN_67 & (&(robEntries_15_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_66; + else if (_GEN_65 & (&(robEntries_14_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_64; + else if (_GEN_63 & (&(robEntries_13_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_62; + else if (_GEN_61 & (&(robEntries_12_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_60; + else if (_GEN_59 & (&(robEntries_11_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_58; + else if (_GEN_57 & (&(robEntries_10_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_56; + else if (_GEN_55 & (&(robEntries_9_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_54; + else if (_GEN_53 & (&(robEntries_8_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_52; + else if (_GEN_51 & (&(robEntries_7_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_50; + else if (_GEN_49 & (&(robEntries_6_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_48; + else if (_GEN_47 & (&(robEntries_5_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_46; + else if (_GEN_45 & (&(robEntries_4_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_44; + else if (_GEN_43 & (&(robEntries_3_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_42; + else if (_GEN_41 & (&(robEntries_2_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_40; + else if (_GEN_39 & (&(robEntries_1_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_38; + else if (_GEN_37 & (&(robEntries_0_cmd_bankAccess_wr_bank_id[3:0]))) + bankCols_15 <= _GEN_36; + if (issueLoad | io_complete_valid) + vbankBusy <= + vbankBusy & ~(io_complete_valid ? _GEN_18[io_complete_bits] : 16'h0) + | (issueLoad ? _GEN_18[_actualIssuePtr_T] : 16'h0); + if (isAllocatedSlot) + dependencyMask_0 <= allocDependencies & ~clearMask; + else + dependencyMask_0 <= dependencyMask_0 & ~clearMask; + if (isAllocatedSlot_1) + dependencyMask_1 <= allocDependencies & ~clearMask_1; + else + dependencyMask_1 <= dependencyMask_1 & ~clearMask_1; + if (isAllocatedSlot_2) + dependencyMask_2 <= allocDependencies & ~clearMask_2; + else + dependencyMask_2 <= dependencyMask_2 & ~clearMask_2; + if (isAllocatedSlot_3) + dependencyMask_3 <= allocDependencies & ~clearMask_3; + else + dependencyMask_3 <= dependencyMask_3 & ~clearMask_3; + if (isAllocatedSlot_4) + dependencyMask_4 <= allocDependencies & ~clearMask_4; + else + dependencyMask_4 <= dependencyMask_4 & ~clearMask_4; + if (isAllocatedSlot_5) + dependencyMask_5 <= allocDependencies & ~clearMask_5; + else + dependencyMask_5 <= dependencyMask_5 & ~clearMask_5; + if (isAllocatedSlot_6) + dependencyMask_6 <= allocDependencies & ~clearMask_6; + else + dependencyMask_6 <= dependencyMask_6 & ~clearMask_6; + if (isAllocatedSlot_7) + dependencyMask_7 <= allocDependencies & ~clearMask_7; + else + dependencyMask_7 <= dependencyMask_7 & ~clearMask_7; + if (isAllocatedSlot_8) + dependencyMask_8 <= allocDependencies & ~clearMask_8; + else + dependencyMask_8 <= dependencyMask_8 & ~clearMask_8; + if (isAllocatedSlot_9) + dependencyMask_9 <= allocDependencies & ~clearMask_9; + else + dependencyMask_9 <= dependencyMask_9 & ~clearMask_9; + if (isAllocatedSlot_10) + dependencyMask_10 <= allocDependencies & ~clearMask_10; + else + dependencyMask_10 <= dependencyMask_10 & ~clearMask_10; + if (isAllocatedSlot_11) + dependencyMask_11 <= allocDependencies & ~clearMask_11; + else + dependencyMask_11 <= dependencyMask_11 & ~clearMask_11; + if (isAllocatedSlot_12) + dependencyMask_12 <= allocDependencies & ~clearMask_12; + else + dependencyMask_12 <= dependencyMask_12 & ~clearMask_12; + if (isAllocatedSlot_13) + dependencyMask_13 <= allocDependencies & ~clearMask_13; + else + dependencyMask_13 <= dependencyMask_13 & ~clearMask_13; + if (isAllocatedSlot_14) + dependencyMask_14 <= allocDependencies & ~clearMask_14; + else + dependencyMask_14 <= dependencyMask_14 & ~clearMask_14; + if (isAllocatedSlot_15) + dependencyMask_15 <= allocDependencies & ~clearMask_15; + else + dependencyMask_15 <= dependencyMask_15 & ~clearMask_15; + if (issueStageReady) + issueStageValid <= issuePtrValid; + if (issuePtrReady) + issuePtrValid <= issueLoad; + end + if (issueStageReady & issuePtrFire) begin + automatic logic [15:0] _GEN_68 = + {{robEntries_15_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_14_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_13_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_12_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_11_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_10_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_9_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_8_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_7_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_6_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_5_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_4_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_3_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_2_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_1_cmd_bankAccess_rd_bank_0_valid}, + {robEntries_0_cmd_bankAccess_rd_bank_0_valid}}; + automatic logic issuePayload_cmd_bankAccess_rd_bank_0_valid = + _GEN_68[issuePtr]; + automatic logic [15:0][9:0] _GEN_69 = + {{robEntries_15_cmd_bankAccess_rd_bank_0_id}, + {robEntries_14_cmd_bankAccess_rd_bank_0_id}, + {robEntries_13_cmd_bankAccess_rd_bank_0_id}, + {robEntries_12_cmd_bankAccess_rd_bank_0_id}, + {robEntries_11_cmd_bankAccess_rd_bank_0_id}, + {robEntries_10_cmd_bankAccess_rd_bank_0_id}, + {robEntries_9_cmd_bankAccess_rd_bank_0_id}, + {robEntries_8_cmd_bankAccess_rd_bank_0_id}, + {robEntries_7_cmd_bankAccess_rd_bank_0_id}, + {robEntries_6_cmd_bankAccess_rd_bank_0_id}, + {robEntries_5_cmd_bankAccess_rd_bank_0_id}, + {robEntries_4_cmd_bankAccess_rd_bank_0_id}, + {robEntries_3_cmd_bankAccess_rd_bank_0_id}, + {robEntries_2_cmd_bankAccess_rd_bank_0_id}, + {robEntries_1_cmd_bankAccess_rd_bank_0_id}, + {robEntries_0_cmd_bankAccess_rd_bank_0_id}}; + automatic logic [9:0] issuePayload_cmd_bankAccess_rd_bank_0_id = + _GEN_69[issuePtr]; + automatic logic [15:0] _GEN_70 = + {{robEntries_15_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_14_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_13_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_12_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_11_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_10_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_9_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_8_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_7_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_6_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_5_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_4_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_3_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_2_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_1_cmd_bankAccess_rd_bank_1_valid}, + {robEntries_0_cmd_bankAccess_rd_bank_1_valid}}; + automatic logic issuePayload_cmd_bankAccess_rd_bank_1_valid = + _GEN_70[issuePtr]; + automatic logic [15:0][9:0] _GEN_71 = + {{robEntries_15_cmd_bankAccess_rd_bank_1_id}, + {robEntries_14_cmd_bankAccess_rd_bank_1_id}, + {robEntries_13_cmd_bankAccess_rd_bank_1_id}, + {robEntries_12_cmd_bankAccess_rd_bank_1_id}, + {robEntries_11_cmd_bankAccess_rd_bank_1_id}, + {robEntries_10_cmd_bankAccess_rd_bank_1_id}, + {robEntries_9_cmd_bankAccess_rd_bank_1_id}, + {robEntries_8_cmd_bankAccess_rd_bank_1_id}, + {robEntries_7_cmd_bankAccess_rd_bank_1_id}, + {robEntries_6_cmd_bankAccess_rd_bank_1_id}, + {robEntries_5_cmd_bankAccess_rd_bank_1_id}, + {robEntries_4_cmd_bankAccess_rd_bank_1_id}, + {robEntries_3_cmd_bankAccess_rd_bank_1_id}, + {robEntries_2_cmd_bankAccess_rd_bank_1_id}, + {robEntries_1_cmd_bankAccess_rd_bank_1_id}, + {robEntries_0_cmd_bankAccess_rd_bank_1_id}}; + automatic logic [9:0] issuePayload_cmd_bankAccess_rd_bank_1_id = + _GEN_71[issuePtr]; + automatic logic [15:0] _GEN_72 = + {{robEntries_15_cmd_bankAccess_wr_bank_valid}, + {robEntries_14_cmd_bankAccess_wr_bank_valid}, + {robEntries_13_cmd_bankAccess_wr_bank_valid}, + {robEntries_12_cmd_bankAccess_wr_bank_valid}, + {robEntries_11_cmd_bankAccess_wr_bank_valid}, + {robEntries_10_cmd_bankAccess_wr_bank_valid}, + {robEntries_9_cmd_bankAccess_wr_bank_valid}, + {robEntries_8_cmd_bankAccess_wr_bank_valid}, + {robEntries_7_cmd_bankAccess_wr_bank_valid}, + {robEntries_6_cmd_bankAccess_wr_bank_valid}, + {robEntries_5_cmd_bankAccess_wr_bank_valid}, + {robEntries_4_cmd_bankAccess_wr_bank_valid}, + {robEntries_3_cmd_bankAccess_wr_bank_valid}, + {robEntries_2_cmd_bankAccess_wr_bank_valid}, + {robEntries_1_cmd_bankAccess_wr_bank_valid}, + {robEntries_0_cmd_bankAccess_wr_bank_valid}}; + automatic logic issuePayload_cmd_bankAccess_wr_bank_valid = + _GEN_72[issuePtr]; + automatic logic [15:0][9:0] _GEN_73 = + {{robEntries_15_cmd_bankAccess_wr_bank_id}, + {robEntries_14_cmd_bankAccess_wr_bank_id}, + {robEntries_13_cmd_bankAccess_wr_bank_id}, + {robEntries_12_cmd_bankAccess_wr_bank_id}, + {robEntries_11_cmd_bankAccess_wr_bank_id}, + {robEntries_10_cmd_bankAccess_wr_bank_id}, + {robEntries_9_cmd_bankAccess_wr_bank_id}, + {robEntries_8_cmd_bankAccess_wr_bank_id}, + {robEntries_7_cmd_bankAccess_wr_bank_id}, + {robEntries_6_cmd_bankAccess_wr_bank_id}, + {robEntries_5_cmd_bankAccess_wr_bank_id}, + {robEntries_4_cmd_bankAccess_wr_bank_id}, + {robEntries_3_cmd_bankAccess_wr_bank_id}, + {robEntries_2_cmd_bankAccess_wr_bank_id}, + {robEntries_1_cmd_bankAccess_wr_bank_id}, + {robEntries_0_cmd_bankAccess_wr_bank_id}}; + automatic logic [9:0] issuePayload_cmd_bankAccess_wr_bank_id = + _GEN_73[issuePtr]; + automatic logic [15:0][3:0] _GEN_74 = + {{bankCols_15}, + {bankCols_14}, + {bankCols_13}, + {bankCols_12}, + {bankCols_11}, + {bankCols_10}, + {bankCols_9}, + {bankCols_8}, + {bankCols_7}, + {bankCols_6}, + {bankCols_5}, + {bankCols_4}, + {bankCols_3}, + {bankCols_2}, + {bankCols_1}, + {bankCols_0}}; + automatic logic [15:0][4:0] _GEN_75 = + {{robEntries_15_cmd_ball_bid}, + {robEntries_14_cmd_ball_bid}, + {robEntries_13_cmd_ball_bid}, + {robEntries_12_cmd_ball_bid}, + {robEntries_11_cmd_ball_bid}, + {robEntries_10_cmd_ball_bid}, + {robEntries_9_cmd_ball_bid}, + {robEntries_8_cmd_ball_bid}, + {robEntries_7_cmd_ball_bid}, + {robEntries_6_cmd_ball_bid}, + {robEntries_5_cmd_ball_bid}, + {robEntries_4_cmd_ball_bid}, + {robEntries_3_cmd_ball_bid}, + {robEntries_2_cmd_ball_bid}, + {robEntries_1_cmd_ball_bid}, + {robEntries_0_cmd_ball_bid}}; + automatic logic [15:0][31:0] _GEN_76 = + {{robEntries_15_cmd_cmd_raw_inst}, + {robEntries_14_cmd_cmd_raw_inst}, + {robEntries_13_cmd_cmd_raw_inst}, + {robEntries_12_cmd_cmd_raw_inst}, + {robEntries_11_cmd_cmd_raw_inst}, + {robEntries_10_cmd_cmd_raw_inst}, + {robEntries_9_cmd_cmd_raw_inst}, + {robEntries_8_cmd_cmd_raw_inst}, + {robEntries_7_cmd_cmd_raw_inst}, + {robEntries_6_cmd_cmd_raw_inst}, + {robEntries_5_cmd_cmd_raw_inst}, + {robEntries_4_cmd_cmd_raw_inst}, + {robEntries_3_cmd_cmd_raw_inst}, + {robEntries_2_cmd_cmd_raw_inst}, + {robEntries_1_cmd_cmd_raw_inst}, + {robEntries_0_cmd_cmd_raw_inst}}; + automatic logic [15:0][2:0] _GEN_77 = + {{robEntries_15_cmd_cmd_funct3}, + {robEntries_14_cmd_cmd_funct3}, + {robEntries_13_cmd_cmd_funct3}, + {robEntries_12_cmd_cmd_funct3}, + {robEntries_11_cmd_cmd_funct3}, + {robEntries_10_cmd_cmd_funct3}, + {robEntries_9_cmd_cmd_funct3}, + {robEntries_8_cmd_cmd_funct3}, + {robEntries_7_cmd_cmd_funct3}, + {robEntries_6_cmd_cmd_funct3}, + {robEntries_5_cmd_cmd_funct3}, + {robEntries_4_cmd_cmd_funct3}, + {robEntries_3_cmd_cmd_funct3}, + {robEntries_2_cmd_cmd_funct3}, + {robEntries_1_cmd_cmd_funct3}, + {robEntries_0_cmd_cmd_funct3}}; + automatic logic [15:0][4:0] _GEN_78 = + {{robEntries_15_cmd_cmd_rs2}, + {robEntries_14_cmd_cmd_rs2}, + {robEntries_13_cmd_cmd_rs2}, + {robEntries_12_cmd_cmd_rs2}, + {robEntries_11_cmd_cmd_rs2}, + {robEntries_10_cmd_cmd_rs2}, + {robEntries_9_cmd_cmd_rs2}, + {robEntries_8_cmd_cmd_rs2}, + {robEntries_7_cmd_cmd_rs2}, + {robEntries_6_cmd_cmd_rs2}, + {robEntries_5_cmd_cmd_rs2}, + {robEntries_4_cmd_cmd_rs2}, + {robEntries_3_cmd_cmd_rs2}, + {robEntries_2_cmd_cmd_rs2}, + {robEntries_1_cmd_cmd_rs2}, + {robEntries_0_cmd_cmd_rs2}}; + automatic logic [15:0][4:0] _GEN_79 = + {{robEntries_15_cmd_cmd_rs1}, + {robEntries_14_cmd_cmd_rs1}, + {robEntries_13_cmd_cmd_rs1}, + {robEntries_12_cmd_cmd_rs1}, + {robEntries_11_cmd_cmd_rs1}, + {robEntries_10_cmd_cmd_rs1}, + {robEntries_9_cmd_cmd_rs1}, + {robEntries_8_cmd_cmd_rs1}, + {robEntries_7_cmd_cmd_rs1}, + {robEntries_6_cmd_cmd_rs1}, + {robEntries_5_cmd_cmd_rs1}, + {robEntries_4_cmd_cmd_rs1}, + {robEntries_3_cmd_cmd_rs1}, + {robEntries_2_cmd_cmd_rs1}, + {robEntries_1_cmd_cmd_rs1}, + {robEntries_0_cmd_cmd_rs1}}; + automatic logic [15:0] _GEN_80 = + {{robEntries_15_cmd_cmd_xd}, + {robEntries_14_cmd_cmd_xd}, + {robEntries_13_cmd_cmd_xd}, + {robEntries_12_cmd_cmd_xd}, + {robEntries_11_cmd_cmd_xd}, + {robEntries_10_cmd_cmd_xd}, + {robEntries_9_cmd_cmd_xd}, + {robEntries_8_cmd_cmd_xd}, + {robEntries_7_cmd_cmd_xd}, + {robEntries_6_cmd_cmd_xd}, + {robEntries_5_cmd_cmd_xd}, + {robEntries_4_cmd_cmd_xd}, + {robEntries_3_cmd_cmd_xd}, + {robEntries_2_cmd_cmd_xd}, + {robEntries_1_cmd_cmd_xd}, + {robEntries_0_cmd_cmd_xd}}; + automatic logic [15:0] _GEN_81 = + {{robEntries_15_cmd_cmd_xs1}, + {robEntries_14_cmd_cmd_xs1}, + {robEntries_13_cmd_cmd_xs1}, + {robEntries_12_cmd_cmd_xs1}, + {robEntries_11_cmd_cmd_xs1}, + {robEntries_10_cmd_cmd_xs1}, + {robEntries_9_cmd_cmd_xs1}, + {robEntries_8_cmd_cmd_xs1}, + {robEntries_7_cmd_cmd_xs1}, + {robEntries_6_cmd_cmd_xs1}, + {robEntries_5_cmd_cmd_xs1}, + {robEntries_4_cmd_cmd_xs1}, + {robEntries_3_cmd_cmd_xs1}, + {robEntries_2_cmd_cmd_xs1}, + {robEntries_1_cmd_cmd_xs1}, + {robEntries_0_cmd_cmd_xs1}}; + automatic logic [15:0] _GEN_82 = + {{robEntries_15_cmd_cmd_xs2}, + {robEntries_14_cmd_cmd_xs2}, + {robEntries_13_cmd_cmd_xs2}, + {robEntries_12_cmd_cmd_xs2}, + {robEntries_11_cmd_cmd_xs2}, + {robEntries_10_cmd_cmd_xs2}, + {robEntries_9_cmd_cmd_xs2}, + {robEntries_8_cmd_cmd_xs2}, + {robEntries_7_cmd_cmd_xs2}, + {robEntries_6_cmd_cmd_xs2}, + {robEntries_5_cmd_cmd_xs2}, + {robEntries_4_cmd_cmd_xs2}, + {robEntries_3_cmd_cmd_xs2}, + {robEntries_2_cmd_cmd_xs2}, + {robEntries_1_cmd_cmd_xs2}, + {robEntries_0_cmd_cmd_xs2}}; + automatic logic [15:0][4:0] _GEN_83 = + {{robEntries_15_cmd_cmd_rd}, + {robEntries_14_cmd_cmd_rd}, + {robEntries_13_cmd_cmd_rd}, + {robEntries_12_cmd_cmd_rd}, + {robEntries_11_cmd_cmd_rd}, + {robEntries_10_cmd_cmd_rd}, + {robEntries_9_cmd_cmd_rd}, + {robEntries_8_cmd_cmd_rd}, + {robEntries_7_cmd_cmd_rd}, + {robEntries_6_cmd_cmd_rd}, + {robEntries_5_cmd_cmd_rd}, + {robEntries_4_cmd_cmd_rd}, + {robEntries_3_cmd_cmd_rd}, + {robEntries_2_cmd_cmd_rd}, + {robEntries_1_cmd_cmd_rd}, + {robEntries_0_cmd_cmd_rd}}; + automatic logic [15:0][6:0] _GEN_84 = + {{robEntries_15_cmd_cmd_opcode}, + {robEntries_14_cmd_cmd_opcode}, + {robEntries_13_cmd_cmd_opcode}, + {robEntries_12_cmd_cmd_opcode}, + {robEntries_11_cmd_cmd_opcode}, + {robEntries_10_cmd_cmd_opcode}, + {robEntries_9_cmd_cmd_opcode}, + {robEntries_8_cmd_cmd_opcode}, + {robEntries_7_cmd_cmd_opcode}, + {robEntries_6_cmd_cmd_opcode}, + {robEntries_5_cmd_cmd_opcode}, + {robEntries_4_cmd_cmd_opcode}, + {robEntries_3_cmd_cmd_opcode}, + {robEntries_2_cmd_cmd_opcode}, + {robEntries_1_cmd_cmd_opcode}, + {robEntries_0_cmd_cmd_opcode}}; + automatic logic [15:0] _GEN_85 = + {{robEntries_15_cmd_isFence}, + {robEntries_14_cmd_isFence}, + {robEntries_13_cmd_isFence}, + {robEntries_12_cmd_isFence}, + {robEntries_11_cmd_isFence}, + {robEntries_10_cmd_isFence}, + {robEntries_9_cmd_isFence}, + {robEntries_8_cmd_isFence}, + {robEntries_7_cmd_isFence}, + {robEntries_6_cmd_isFence}, + {robEntries_5_cmd_isFence}, + {robEntries_4_cmd_isFence}, + {robEntries_3_cmd_isFence}, + {robEntries_2_cmd_isFence}, + {robEntries_1_cmd_isFence}, + {robEntries_0_cmd_isFence}}; + automatic logic [15:0] _GEN_86 = + {{robEntries_15_cmd_isBarrier}, + {robEntries_14_cmd_isBarrier}, + {robEntries_13_cmd_isBarrier}, + {robEntries_12_cmd_isBarrier}, + {robEntries_11_cmd_isBarrier}, + {robEntries_10_cmd_isBarrier}, + {robEntries_9_cmd_isBarrier}, + {robEntries_8_cmd_isBarrier}, + {robEntries_7_cmd_isBarrier}, + {robEntries_6_cmd_isBarrier}, + {robEntries_5_cmd_isBarrier}, + {robEntries_4_cmd_isBarrier}, + {robEntries_3_cmd_isBarrier}, + {robEntries_2_cmd_isBarrier}, + {robEntries_1_cmd_isBarrier}, + {robEntries_0_cmd_isBarrier}}; + issueStageEntry_cmd_domain_id <= _GEN_5[issuePtr]; + issueStageEntry_cmd_ball_bid <= _GEN_75[issuePtr]; + issueStageEntry_cmd_cmd_raw_inst <= _GEN_76[issuePtr]; + issueStageEntry_cmd_cmd_pc <= _GEN_6[issuePtr]; + issueStageEntry_cmd_cmd_funct <= _GEN_7[issuePtr]; + issueStageEntry_cmd_cmd_funct3 <= _GEN_77[issuePtr]; + issueStageEntry_cmd_cmd_rs2 <= _GEN_78[issuePtr]; + issueStageEntry_cmd_cmd_rs1 <= _GEN_79[issuePtr]; + issueStageEntry_cmd_cmd_xd <= _GEN_80[issuePtr]; + issueStageEntry_cmd_cmd_xs1 <= _GEN_81[issuePtr]; + issueStageEntry_cmd_cmd_xs2 <= _GEN_82[issuePtr]; + issueStageEntry_cmd_cmd_rd <= _GEN_83[issuePtr]; + issueStageEntry_cmd_cmd_opcode <= _GEN_84[issuePtr]; + issueStageEntry_cmd_cmd_rs1Data <= _GEN_8[issuePtr]; + issueStageEntry_cmd_cmd_rs2Data <= _GEN_9[issuePtr]; + issueStageEntry_cmd_bankAccess_rd_bank_0_valid <= + issuePayload_cmd_bankAccess_rd_bank_0_valid; + issueStageEntry_cmd_bankAccess_rd_bank_0_id <= + issuePayload_cmd_bankAccess_rd_bank_0_id; + issueStageEntry_cmd_bankAccess_rd_bank_1_valid <= + issuePayload_cmd_bankAccess_rd_bank_1_valid; + issueStageEntry_cmd_bankAccess_rd_bank_1_id <= + issuePayload_cmd_bankAccess_rd_bank_1_id; + issueStageEntry_cmd_bankAccess_wr_bank_valid <= + issuePayload_cmd_bankAccess_wr_bank_valid; + issueStageEntry_cmd_bankAccess_wr_bank_id <= issuePayload_cmd_bankAccess_wr_bank_id; + issueStageEntry_cmd_op1_col <= + issuePayload_cmd_bankAccess_rd_bank_0_valid + ? _GEN_74[issuePayload_cmd_bankAccess_rd_bank_0_id[3:0]] + : 4'h0; + issueStageEntry_cmd_op2_col <= + issuePayload_cmd_bankAccess_rd_bank_1_valid + ? _GEN_74[issuePayload_cmd_bankAccess_rd_bank_1_id[3:0]] + : 4'h0; + issueStageEntry_cmd_wr_col <= + issuePayload_cmd_bankAccess_wr_bank_valid + ? _GEN_74[issuePayload_cmd_bankAccess_wr_bank_id[3:0]] + : 4'h0; + issueStageEntry_cmd_isFence <= _GEN_85[issuePtr]; + issueStageEntry_cmd_isBarrier <= _GEN_86[issuePtr]; + issueStageEntry_renamedBankAccess_rd_bank_0_valid <= _GEN_13[issuePtr]; + issueStageEntry_renamedBankAccess_rd_bank_0_id <= _GEN_14[issuePtr]; + issueStageEntry_renamedBankAccess_rd_bank_1_valid <= _GEN_15[issuePtr]; + issueStageEntry_renamedBankAccess_rd_bank_1_id <= _GEN_16[issuePtr]; + issueStageEntry_renamedBankAccess_wr_bank_valid <= _GEN_10[issuePtr]; + issueStageEntry_renamedBankAccess_wr_bank_id <= _GEN_11[issuePtr]; + issueStageEntry_rob_id <= _GEN_19[issuePtr]; + end + if (issuePtrReady & issueLoad) + issuePtr <= _actualIssuePtr_T; + end // always @(posedge) + BankAliasTable bat ( + .clock (clock), + .reset (reset), + .io_alloc_valid (_isAllocatedSlot_T_30), + .io_alloc_rob_id (tailPtr), + .io_alloc_raw_rd_bank_0_valid (io_alloc_bits_bankAccess_rd_bank_0_valid), + .io_alloc_raw_rd_bank_0_id (io_alloc_bits_bankAccess_rd_bank_0_id), + .io_alloc_raw_rd_bank_1_valid (io_alloc_bits_bankAccess_rd_bank_1_valid), + .io_alloc_raw_rd_bank_1_id (io_alloc_bits_bankAccess_rd_bank_1_id), + .io_alloc_raw_wr_bank_valid (io_alloc_bits_bankAccess_wr_bank_valid), + .io_alloc_raw_wr_bank_id (io_alloc_bits_bankAccess_wr_bank_id), + .io_alloc_renamed_rd_bank_0_valid (_bat_io_alloc_renamed_rd_bank_0_valid), + .io_alloc_renamed_rd_bank_0_id (_bat_io_alloc_renamed_rd_bank_0_id), + .io_alloc_renamed_rd_bank_1_valid (_bat_io_alloc_renamed_rd_bank_1_valid), + .io_alloc_renamed_rd_bank_1_id (_bat_io_alloc_renamed_rd_bank_1_id), + .io_alloc_renamed_wr_bank_valid (_bat_io_alloc_renamed_wr_bank_valid), + .io_alloc_renamed_wr_bank_id (_bat_io_alloc_renamed_wr_bank_id), + .io_free_valid + (|{commitMask_15, + commitMask_14, + commitMask_13, + commitMask_12, + commitMask_11, + commitMask_10, + commitMask_9, + commitMask_8, + commitMask_7, + commitMask_6, + commitMask_5, + commitMask_4, + commitMask_3, + commitMask_2, + commitMask_1, + commitMask_0}), + .io_free_mask_0 (commitMask_0), + .io_free_mask_1 (commitMask_1), + .io_free_mask_2 (commitMask_2), + .io_free_mask_3 (commitMask_3), + .io_free_mask_4 (commitMask_4), + .io_free_mask_5 (commitMask_5), + .io_free_mask_6 (commitMask_6), + .io_free_mask_7 (commitMask_7), + .io_free_mask_8 (commitMask_8), + .io_free_mask_9 (commitMask_9), + .io_free_mask_10 (commitMask_10), + .io_free_mask_11 (commitMask_11), + .io_free_mask_12 (commitMask_12), + .io_free_mask_13 (commitMask_13), + .io_free_mask_14 (commitMask_14), + .io_free_mask_15 (commitMask_15) + ); + BankScoreboard scoreboard ( + .clock (clock), + .reset (reset), + .alloc_valid + (_isAllocatedSlot_T_30 & io_alloc_bits_bankAccess_wr_bank_valid), + .alloc_bits_wr_bank_valid (_bat_io_alloc_renamed_wr_bank_valid), + .alloc_bits_wr_bank_id (_bat_io_alloc_renamed_wr_bank_id), + .complete_valid (io_complete_valid), + .complete_bits_wr_bank_valid (io_complete_valid & _GEN_10[io_complete_bits]), + .complete_bits_wr_bank_id (io_complete_valid ? _GEN_11[io_complete_bits] : 10'h0), + .queryVec_0_rd_bank_0_valid (_GEN_13[ptr]), + .queryVec_0_rd_bank_0_id (_GEN_14[ptr]), + .queryVec_0_rd_bank_1_valid (_GEN_15[ptr]), + .queryVec_0_rd_bank_1_id (_GEN_16[ptr]), + .queryVec_1_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1446]), + .queryVec_1_rd_bank_0_id (_GEN_14[_hits_ptr_T_1446]), + .queryVec_1_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1446]), + .queryVec_1_rd_bank_1_id (_GEN_16[_hits_ptr_T_1446]), + .queryVec_2_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1452]), + .queryVec_2_rd_bank_0_id (_GEN_14[_hits_ptr_T_1452]), + .queryVec_2_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1452]), + .queryVec_2_rd_bank_1_id (_GEN_16[_hits_ptr_T_1452]), + .queryVec_3_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1458]), + .queryVec_3_rd_bank_0_id (_GEN_14[_hits_ptr_T_1458]), + .queryVec_3_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1458]), + .queryVec_3_rd_bank_1_id (_GEN_16[_hits_ptr_T_1458]), + .queryVec_4_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1464]), + .queryVec_4_rd_bank_0_id (_GEN_14[_hits_ptr_T_1464]), + .queryVec_4_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1464]), + .queryVec_4_rd_bank_1_id (_GEN_16[_hits_ptr_T_1464]), + .queryVec_5_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1470]), + .queryVec_5_rd_bank_0_id (_GEN_14[_hits_ptr_T_1470]), + .queryVec_5_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1470]), + .queryVec_5_rd_bank_1_id (_GEN_16[_hits_ptr_T_1470]), + .queryVec_6_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1476]), + .queryVec_6_rd_bank_0_id (_GEN_14[_hits_ptr_T_1476]), + .queryVec_6_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1476]), + .queryVec_6_rd_bank_1_id (_GEN_16[_hits_ptr_T_1476]), + .queryVec_7_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1482]), + .queryVec_7_rd_bank_0_id (_GEN_14[_hits_ptr_T_1482]), + .queryVec_7_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1482]), + .queryVec_7_rd_bank_1_id (_GEN_16[_hits_ptr_T_1482]), + .queryVec_8_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1488]), + .queryVec_8_rd_bank_0_id (_GEN_14[_hits_ptr_T_1488]), + .queryVec_8_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1488]), + .queryVec_8_rd_bank_1_id (_GEN_16[_hits_ptr_T_1488]), + .queryVec_9_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1494]), + .queryVec_9_rd_bank_0_id (_GEN_14[_hits_ptr_T_1494]), + .queryVec_9_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1494]), + .queryVec_9_rd_bank_1_id (_GEN_16[_hits_ptr_T_1494]), + .queryVec_10_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1500]), + .queryVec_10_rd_bank_0_id (_GEN_14[_hits_ptr_T_1500]), + .queryVec_10_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1500]), + .queryVec_10_rd_bank_1_id (_GEN_16[_hits_ptr_T_1500]), + .queryVec_11_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1506]), + .queryVec_11_rd_bank_0_id (_GEN_14[_hits_ptr_T_1506]), + .queryVec_11_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1506]), + .queryVec_11_rd_bank_1_id (_GEN_16[_hits_ptr_T_1506]), + .queryVec_12_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1512]), + .queryVec_12_rd_bank_0_id (_GEN_14[_hits_ptr_T_1512]), + .queryVec_12_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1512]), + .queryVec_12_rd_bank_1_id (_GEN_16[_hits_ptr_T_1512]), + .queryVec_13_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1518]), + .queryVec_13_rd_bank_0_id (_GEN_14[_hits_ptr_T_1518]), + .queryVec_13_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1518]), + .queryVec_13_rd_bank_1_id (_GEN_16[_hits_ptr_T_1518]), + .queryVec_14_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1524]), + .queryVec_14_rd_bank_0_id (_GEN_14[_hits_ptr_T_1524]), + .queryVec_14_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1524]), + .queryVec_14_rd_bank_1_id (_GEN_16[_hits_ptr_T_1524]), + .queryVec_15_rd_bank_0_valid (_GEN_13[_hits_ptr_T_1530]), + .queryVec_15_rd_bank_0_id (_GEN_14[_hits_ptr_T_1530]), + .queryVec_15_rd_bank_1_valid (_GEN_15[_hits_ptr_T_1530]), + .queryVec_15_rd_bank_1_id (_GEN_16[_hits_ptr_T_1530]), + .hazardVec_0 (_scoreboard_hazardVec_0), + .hazardVec_1 (_scoreboard_hazardVec_1), + .hazardVec_2 (_scoreboard_hazardVec_2), + .hazardVec_3 (_scoreboard_hazardVec_3), + .hazardVec_4 (_scoreboard_hazardVec_4), + .hazardVec_5 (_scoreboard_hazardVec_5), + .hazardVec_6 (_scoreboard_hazardVec_6), + .hazardVec_7 (_scoreboard_hazardVec_7), + .hazardVec_8 (_scoreboard_hazardVec_8), + .hazardVec_9 (_scoreboard_hazardVec_9), + .hazardVec_10 (_scoreboard_hazardVec_10), + .hazardVec_11 (_scoreboard_hazardVec_11), + .hazardVec_12 (_scoreboard_hazardVec_12), + .hazardVec_13 (_scoreboard_hazardVec_13), + .hazardVec_14 (_scoreboard_hazardVec_14), + .hazardVec_15 (_scoreboard_hazardVec_15) + ); + ITraceDPI itraceAlloc ( + .clock (clock), + .reset (reset), + .is_issue ({6'h0, _isAllocatedSlot_T_30, 1'h0}), + .hart_id (64'h0), + .rob_id (_isAllocatedSlot_T_30 ? {28'h0, tailPtr} : 32'h0), + .inst_id (_GEN_3 ? nextInstId : 64'h0), + .domain_id (_isAllocatedSlot_T_30 ? {28'h0, io_alloc_bits_domain_id} : 32'h0), + .funct (_isAllocatedSlot_T_30 ? {25'h0, io_alloc_bits_cmd_funct} : 32'h0), + .pc (_isAllocatedSlot_T_30 ? io_alloc_bits_cmd_pc : 64'h0), + .rs1_data (_isAllocatedSlot_T_30 ? io_alloc_bits_cmd_rs1Data : 64'h0), + .rs2_data (_isAllocatedSlot_T_30 ? io_alloc_bits_cmd_rs2Data : 64'h0), + .enable (_isAllocatedSlot_T_30) + ); + ITraceDPI itraceIssue ( + .clock (clock), + .reset (reset), + .is_issue ({7'h0, issueLoad}), + .hart_id (64'h0), + .rob_id (issueLoad ? {28'h0, _GEN_19[_actualIssuePtr_T]} : 32'h0), + .inst_id (issueLoad ? _GEN_12[_actualIssuePtr_T] : 64'h0), + .domain_id (issueLoad ? {28'h0, _GEN_5[_actualIssuePtr_T]} : 32'h0), + .funct (issueLoad ? {25'h0, _GEN_7[_actualIssuePtr_T]} : 32'h0), + .pc (issueLoad ? _GEN_6[_actualIssuePtr_T] : 64'h0), + .rs1_data (issueLoad ? _GEN_8[_actualIssuePtr_T] : 64'h0), + .rs2_data (issueLoad ? _GEN_9[_actualIssuePtr_T] : 64'h0), + .enable (issueLoad) + ); + ITraceDPI itraceComp ( + .clock (clock), + .reset (reset), + .is_issue (8'h0), + .hart_id (64'h0), + .rob_id (io_complete_valid ? {28'h0, io_complete_bits} : 32'h0), + .inst_id (io_complete_valid ? _GEN_12[io_complete_bits] : 64'h0), + .domain_id (io_complete_valid ? {28'h0, _GEN_5[io_complete_bits]} : 32'h0), + .funct (io_complete_valid ? {25'h0, _GEN_7[io_complete_bits]} : 32'h0), + .pc (io_complete_valid ? _GEN_6[io_complete_bits] : 64'h0), + .rs1_data (io_complete_valid ? _GEN_8[io_complete_bits] : 64'h0), + .rs2_data (io_complete_valid ? _GEN_9[io_complete_bits] : 64'h0), + .enable (io_complete_valid) + ); + assign io_alloc_ready = io_alloc_ready_0; + assign io_issue_valid = issueStageValid & ~io_subRobActive; + assign io_issue_bits_cmd_domain_id = issueStageEntry_cmd_domain_id; + assign io_issue_bits_cmd_ball_bid = issueStageEntry_cmd_ball_bid; + assign io_issue_bits_cmd_cmd_raw_inst = issueStageEntry_cmd_cmd_raw_inst; + assign io_issue_bits_cmd_cmd_pc = issueStageEntry_cmd_cmd_pc; + assign io_issue_bits_cmd_cmd_funct = issueStageEntry_cmd_cmd_funct; + assign io_issue_bits_cmd_cmd_funct3 = issueStageEntry_cmd_cmd_funct3; + assign io_issue_bits_cmd_cmd_rs2 = issueStageEntry_cmd_cmd_rs2; + assign io_issue_bits_cmd_cmd_rs1 = issueStageEntry_cmd_cmd_rs1; + assign io_issue_bits_cmd_cmd_xd = issueStageEntry_cmd_cmd_xd; + assign io_issue_bits_cmd_cmd_xs1 = issueStageEntry_cmd_cmd_xs1; + assign io_issue_bits_cmd_cmd_xs2 = issueStageEntry_cmd_cmd_xs2; + assign io_issue_bits_cmd_cmd_rd = issueStageEntry_cmd_cmd_rd; + assign io_issue_bits_cmd_cmd_opcode = issueStageEntry_cmd_cmd_opcode; + assign io_issue_bits_cmd_cmd_rs1Data = issueStageEntry_cmd_cmd_rs1Data; + assign io_issue_bits_cmd_cmd_rs2Data = issueStageEntry_cmd_cmd_rs2Data; + assign io_issue_bits_cmd_bankAccess_rd_bank_0_valid = + issueStageEntry_cmd_bankAccess_rd_bank_0_valid; + assign io_issue_bits_cmd_bankAccess_rd_bank_0_id = + issueStageEntry_cmd_bankAccess_rd_bank_0_id; + assign io_issue_bits_cmd_bankAccess_rd_bank_1_valid = + issueStageEntry_cmd_bankAccess_rd_bank_1_valid; + assign io_issue_bits_cmd_bankAccess_rd_bank_1_id = + issueStageEntry_cmd_bankAccess_rd_bank_1_id; + assign io_issue_bits_cmd_bankAccess_wr_bank_valid = + issueStageEntry_cmd_bankAccess_wr_bank_valid; + assign io_issue_bits_cmd_bankAccess_wr_bank_id = + issueStageEntry_cmd_bankAccess_wr_bank_id; + assign io_issue_bits_cmd_op1_col = issueStageEntry_cmd_op1_col; + assign io_issue_bits_cmd_op2_col = issueStageEntry_cmd_op2_col; + assign io_issue_bits_cmd_wr_col = issueStageEntry_cmd_wr_col; + assign io_issue_bits_cmd_isFence = issueStageEntry_cmd_isFence; + assign io_issue_bits_cmd_isBarrier = issueStageEntry_cmd_isBarrier; + assign io_issue_bits_renamedBankAccess_rd_bank_0_valid = + issueStageEntry_renamedBankAccess_rd_bank_0_valid; + assign io_issue_bits_renamedBankAccess_rd_bank_0_id = + issueStageEntry_renamedBankAccess_rd_bank_0_id; + assign io_issue_bits_renamedBankAccess_rd_bank_1_valid = + issueStageEntry_renamedBankAccess_rd_bank_1_valid; + assign io_issue_bits_renamedBankAccess_rd_bank_1_id = + issueStageEntry_renamedBankAccess_rd_bank_1_id; + assign io_issue_bits_renamedBankAccess_wr_bank_valid = + issueStageEntry_renamedBankAccess_wr_bank_valid; + assign io_issue_bits_renamedBankAccess_wr_bank_id = + issueStageEntry_renamedBankAccess_wr_bank_id; + assign io_issue_bits_rob_id = issueStageEntry_rob_id; + assign io_empty = _isFull_T & ~_GEN_0; + assign io_full = isFull; + assign io_head_ptr = ptr; + assign io_issued_count = issuedCount; + assign io_entry_valid_0 = robValid_0; + assign io_entry_valid_1 = robValid_1; + assign io_entry_valid_2 = robValid_2; + assign io_entry_valid_3 = robValid_3; + assign io_entry_valid_4 = robValid_4; + assign io_entry_valid_5 = robValid_5; + assign io_entry_valid_6 = robValid_6; + assign io_entry_valid_7 = robValid_7; + assign io_entry_valid_8 = robValid_8; + assign io_entry_valid_9 = robValid_9; + assign io_entry_valid_10 = robValid_10; + assign io_entry_valid_11 = robValid_11; + assign io_entry_valid_12 = robValid_12; + assign io_entry_valid_13 = robValid_13; + assign io_entry_valid_14 = robValid_14; + assign io_entry_valid_15 = robValid_15; + assign io_entry_complete_0 = robComplete_0; + assign io_entry_complete_1 = robComplete_1; + assign io_entry_complete_2 = robComplete_2; + assign io_entry_complete_3 = robComplete_3; + assign io_entry_complete_4 = robComplete_4; + assign io_entry_complete_5 = robComplete_5; + assign io_entry_complete_6 = robComplete_6; + assign io_entry_complete_7 = robComplete_7; + assign io_entry_complete_8 = robComplete_8; + assign io_entry_complete_9 = robComplete_9; + assign io_entry_complete_10 = robComplete_10; + assign io_entry_complete_11 = robComplete_11; + assign io_entry_complete_12 = robComplete_12; + assign io_entry_complete_13 = robComplete_13; + assign io_entry_complete_14 = robComplete_14; + assign io_entry_complete_15 = robComplete_15; + assign io_inst_ids_0 = instIds_0; + assign io_inst_ids_1 = instIds_1; + assign io_inst_ids_2 = instIds_2; + assign io_inst_ids_3 = instIds_3; + assign io_inst_ids_4 = instIds_4; + assign io_inst_ids_5 = instIds_5; + assign io_inst_ids_6 = instIds_6; + assign io_inst_ids_7 = instIds_7; + assign io_inst_ids_8 = instIds_8; + assign io_inst_ids_9 = instIds_9; + assign io_inst_ids_10 = instIds_10; + assign io_inst_ids_11 = instIds_11; + assign io_inst_ids_12 = instIds_12; + assign io_inst_ids_13 = instIds_13; + assign io_inst_ids_14 = instIds_14; + assign io_inst_ids_15 = instIds_15; +endmodule + +// VCS coverage exclude_file +module ram_2x303( + input R0_addr, + R0_en, + R0_clk, + output [302:0] R0_data, + input W0_addr, + W0_en, + W0_clk, + input [302:0] W0_data +); + + reg [302:0] Memory[0:1]; + always @(posedge W0_clk) begin + if (W0_en & 1'h1) + Memory[W0_addr] <= W0_data; + end // always @(posedge) + assign R0_data = R0_en ? Memory[R0_addr] : 303'bx; +endmodule + +module Queue2_PostGDCmd( + input clock, + reset, + io_enq_valid, + input [3:0] io_enq_bits_domain_id, + input [31:0] io_enq_bits_cmd_raw_inst, + input [63:0] io_enq_bits_cmd_pc, + input [6:0] io_enq_bits_cmd_funct, + input [63:0] io_enq_bits_cmd_rs1Data, + io_enq_bits_cmd_rs2Data, + input io_enq_bits_bankAccess_rd_bank_0_valid, + input [9:0] io_enq_bits_bankAccess_rd_bank_0_id, + input io_enq_bits_bankAccess_rd_bank_1_valid, + input [9:0] io_enq_bits_bankAccess_rd_bank_1_id, + input io_enq_bits_bankAccess_wr_bank_valid, + input [9:0] io_enq_bits_bankAccess_wr_bank_id, + input io_deq_ready, + output io_deq_valid, + output [3:0] io_deq_bits_domain_id, + output [4:0] io_deq_bits_ball_bid, + output [31:0] io_deq_bits_cmd_raw_inst, + output [63:0] io_deq_bits_cmd_pc, + output [6:0] io_deq_bits_cmd_funct, + output [2:0] io_deq_bits_cmd_funct3, + output [4:0] io_deq_bits_cmd_rs2, + io_deq_bits_cmd_rs1, + output io_deq_bits_cmd_xd, + io_deq_bits_cmd_xs1, + io_deq_bits_cmd_xs2, + output [4:0] io_deq_bits_cmd_rd, + output [6:0] io_deq_bits_cmd_opcode, + output [63:0] io_deq_bits_cmd_rs1Data, + io_deq_bits_cmd_rs2Data, + output io_deq_bits_bankAccess_rd_bank_0_valid, + output [9:0] io_deq_bits_bankAccess_rd_bank_0_id, + output io_deq_bits_bankAccess_rd_bank_1_valid, + output [9:0] io_deq_bits_bankAccess_rd_bank_1_id, + output io_deq_bits_bankAccess_wr_bank_valid, + output [9:0] io_deq_bits_bankAccess_wr_bank_id, + output io_deq_bits_isFence, + io_deq_bits_isBarrier +); + + wire io_enq_ready; + wire [302:0] _ram_ext_R0_data; + reg wrap; + reg wrap_1; + reg maybe_full; + wire ptr_match = wrap == wrap_1; + wire empty = ptr_match & ~maybe_full; + wire do_enq = io_enq_ready & io_enq_valid; + assign io_enq_ready = ~(ptr_match & maybe_full); + always @(posedge clock) begin + if (reset) begin + wrap <= 1'h0; + wrap_1 <= 1'h0; + maybe_full <= 1'h0; + end + else begin + automatic logic do_deq = io_deq_ready & ~empty; + if (do_enq) + wrap <= wrap - 1'h1; + if (do_deq) + wrap_1 <= wrap_1 - 1'h1; + if (~(do_enq == do_deq)) + maybe_full <= do_enq; + end + end // always @(posedge) + ram_2x303 ram_ext ( + .R0_addr (wrap_1), + .R0_en (1'h1), + .R0_clk (clock), + .R0_data (_ram_ext_R0_data), + .W0_addr (wrap), + .W0_en (do_enq), + .W0_clk (clock), + .W0_data + ({2'h0, + io_enq_bits_bankAccess_wr_bank_id, + io_enq_bits_bankAccess_wr_bank_valid, + io_enq_bits_bankAccess_rd_bank_1_id, + io_enq_bits_bankAccess_rd_bank_1_valid, + io_enq_bits_bankAccess_rd_bank_0_id, + io_enq_bits_bankAccess_rd_bank_0_valid, + io_enq_bits_cmd_rs2Data, + io_enq_bits_cmd_rs1Data, + 28'h0, + io_enq_bits_cmd_funct, + io_enq_bits_cmd_pc, + io_enq_bits_cmd_raw_inst, + 5'h0, + io_enq_bits_domain_id}) + ); + assign io_deq_valid = ~empty; + assign io_deq_bits_domain_id = _ram_ext_R0_data[3:0]; + assign io_deq_bits_ball_bid = _ram_ext_R0_data[8:4]; + assign io_deq_bits_cmd_raw_inst = _ram_ext_R0_data[40:9]; + assign io_deq_bits_cmd_pc = _ram_ext_R0_data[104:41]; + assign io_deq_bits_cmd_funct = _ram_ext_R0_data[111:105]; + assign io_deq_bits_cmd_funct3 = _ram_ext_R0_data[114:112]; + assign io_deq_bits_cmd_rs2 = _ram_ext_R0_data[119:115]; + assign io_deq_bits_cmd_rs1 = _ram_ext_R0_data[124:120]; + assign io_deq_bits_cmd_xd = _ram_ext_R0_data[125]; + assign io_deq_bits_cmd_xs1 = _ram_ext_R0_data[126]; + assign io_deq_bits_cmd_xs2 = _ram_ext_R0_data[127]; + assign io_deq_bits_cmd_rd = _ram_ext_R0_data[132:128]; + assign io_deq_bits_cmd_opcode = _ram_ext_R0_data[139:133]; + assign io_deq_bits_cmd_rs1Data = _ram_ext_R0_data[203:140]; + assign io_deq_bits_cmd_rs2Data = _ram_ext_R0_data[267:204]; + assign io_deq_bits_bankAccess_rd_bank_0_valid = _ram_ext_R0_data[268]; + assign io_deq_bits_bankAccess_rd_bank_0_id = _ram_ext_R0_data[278:269]; + assign io_deq_bits_bankAccess_rd_bank_1_valid = _ram_ext_R0_data[279]; + assign io_deq_bits_bankAccess_rd_bank_1_id = _ram_ext_R0_data[289:280]; + assign io_deq_bits_bankAccess_wr_bank_valid = _ram_ext_R0_data[290]; + assign io_deq_bits_bankAccess_wr_bank_id = _ram_ext_R0_data[300:291]; + assign io_deq_bits_isFence = _ram_ext_R0_data[301]; + assign io_deq_bits_isBarrier = _ram_ext_R0_data[302]; +endmodule + +// VCS coverage exclude_file +module ram_16x4( + input [3:0] R0_addr, + input R0_en, + R0_clk, + output [3:0] R0_data, + input [3:0] W0_addr, + input W0_en, + W0_clk, + input [3:0] W0_data +); + + reg [3:0] Memory[0:15]; + always @(posedge W0_clk) begin + if (W0_en & 1'h1) + Memory[W0_addr] <= W0_data; + end // always @(posedge) + assign R0_data = R0_en ? Memory[R0_addr] : 4'bx; +endmodule + +module Queue16_UInt4( + input clock, + reset, + output io_enq_ready, + input io_enq_valid, + input [3:0] io_enq_bits, + input io_deq_ready, + output io_deq_valid, + output [3:0] io_deq_bits +); + + reg [3:0] enq_ptr_value; + reg [3:0] deq_ptr_value; + reg maybe_full; + wire ptr_match = enq_ptr_value == deq_ptr_value; + wire empty = ptr_match & ~maybe_full; + wire full = ptr_match & maybe_full; + wire do_enq = ~full & io_enq_valid; + always @(posedge clock) begin + if (reset) begin + enq_ptr_value <= 4'h0; + deq_ptr_value <= 4'h0; + maybe_full <= 1'h0; + end + else begin + automatic logic do_deq = io_deq_ready & ~empty; + if (do_enq) + enq_ptr_value <= enq_ptr_value + 4'h1; + if (do_deq) + deq_ptr_value <= deq_ptr_value + 4'h1; + if (~(do_enq == do_deq)) + maybe_full <= do_enq; + end + end // always @(posedge) + ram_16x4 ram_ext ( + .R0_addr (deq_ptr_value), + .R0_en (1'h1), + .R0_clk (clock), + .R0_data (io_deq_bits), + .W0_addr (enq_ptr_value), + .W0_en (do_enq), + .W0_clk (clock), + .W0_data (io_enq_bits) + ); + assign io_enq_ready = ~full; + assign io_deq_valid = ~empty; +endmodule + +module GlobalRobCheck( + input clock, + reset, + input [31:0] seed, + output passed +); + + wire _completions_io_enq_ready; + wire _completions_io_deq_valid; + wire [3:0] _completions_io_deq_bits; + wire _source_io_deq_valid; + wire [3:0] _source_io_deq_bits_domain_id; + wire [4:0] _source_io_deq_bits_ball_bid; + wire [31:0] _source_io_deq_bits_cmd_raw_inst; + wire [63:0] _source_io_deq_bits_cmd_pc; + wire [6:0] _source_io_deq_bits_cmd_funct; + wire [2:0] _source_io_deq_bits_cmd_funct3; + wire [4:0] _source_io_deq_bits_cmd_rs2; + wire [4:0] _source_io_deq_bits_cmd_rs1; + wire _source_io_deq_bits_cmd_xd; + wire _source_io_deq_bits_cmd_xs1; + wire _source_io_deq_bits_cmd_xs2; + wire [4:0] _source_io_deq_bits_cmd_rd; + wire [6:0] _source_io_deq_bits_cmd_opcode; + wire [63:0] _source_io_deq_bits_cmd_rs1Data; + wire [63:0] _source_io_deq_bits_cmd_rs2Data; + wire _source_io_deq_bits_bankAccess_rd_bank_0_valid; + wire [9:0] _source_io_deq_bits_bankAccess_rd_bank_0_id; + wire _source_io_deq_bits_bankAccess_rd_bank_1_valid; + wire [9:0] _source_io_deq_bits_bankAccess_rd_bank_1_id; + wire _source_io_deq_bits_bankAccess_wr_bank_valid; + wire [9:0] _source_io_deq_bits_bankAccess_wr_bank_id; + wire _source_io_deq_bits_isFence; + wire _source_io_deq_bits_isBarrier; + wire _reference_io_alloc_ready; + wire _reference_io_issue_valid; + wire [3:0] _reference_io_issue_bits_cmd_domain_id; + wire [4:0] _reference_io_issue_bits_cmd_ball_bid; + wire [31:0] _reference_io_issue_bits_cmd_cmd_raw_inst; + wire [63:0] _reference_io_issue_bits_cmd_cmd_pc; + wire [6:0] _reference_io_issue_bits_cmd_cmd_funct; + wire [2:0] _reference_io_issue_bits_cmd_cmd_funct3; + wire [4:0] _reference_io_issue_bits_cmd_cmd_rs2; + wire [4:0] _reference_io_issue_bits_cmd_cmd_rs1; + wire _reference_io_issue_bits_cmd_cmd_xd; + wire _reference_io_issue_bits_cmd_cmd_xs1; + wire _reference_io_issue_bits_cmd_cmd_xs2; + wire [4:0] _reference_io_issue_bits_cmd_cmd_rd; + wire [6:0] _reference_io_issue_bits_cmd_cmd_opcode; + wire [63:0] _reference_io_issue_bits_cmd_cmd_rs1Data; + wire [63:0] _reference_io_issue_bits_cmd_cmd_rs2Data; + wire _reference_io_issue_bits_cmd_bankAccess_rd_bank_0_valid; + wire [9:0] _reference_io_issue_bits_cmd_bankAccess_rd_bank_0_id; + wire _reference_io_issue_bits_cmd_bankAccess_rd_bank_1_valid; + wire [9:0] _reference_io_issue_bits_cmd_bankAccess_rd_bank_1_id; + wire _reference_io_issue_bits_cmd_bankAccess_wr_bank_valid; + wire [9:0] _reference_io_issue_bits_cmd_bankAccess_wr_bank_id; + wire [3:0] _reference_io_issue_bits_cmd_op1_col; + wire [3:0] _reference_io_issue_bits_cmd_op2_col; + wire [3:0] _reference_io_issue_bits_cmd_wr_col; + wire _reference_io_issue_bits_cmd_isFence; + wire _reference_io_issue_bits_cmd_isBarrier; + wire _reference_io_issue_bits_renamedBankAccess_rd_bank_0_valid; + wire [9:0] _reference_io_issue_bits_renamedBankAccess_rd_bank_0_id; + wire _reference_io_issue_bits_renamedBankAccess_rd_bank_1_valid; + wire [9:0] _reference_io_issue_bits_renamedBankAccess_rd_bank_1_id; + wire _reference_io_issue_bits_renamedBankAccess_wr_bank_valid; + wire [9:0] _reference_io_issue_bits_renamedBankAccess_wr_bank_id; + wire [3:0] _reference_io_issue_bits_rob_id; + wire _reference_io_empty; + wire _reference_io_full; + wire [3:0] _reference_io_head_ptr; + wire [4:0] _reference_io_issued_count; + wire _reference_io_entry_valid_0; + wire _reference_io_entry_valid_1; + wire _reference_io_entry_valid_2; + wire _reference_io_entry_valid_3; + wire _reference_io_entry_valid_4; + wire _reference_io_entry_valid_5; + wire _reference_io_entry_valid_6; + wire _reference_io_entry_valid_7; + wire _reference_io_entry_valid_8; + wire _reference_io_entry_valid_9; + wire _reference_io_entry_valid_10; + wire _reference_io_entry_valid_11; + wire _reference_io_entry_valid_12; + wire _reference_io_entry_valid_13; + wire _reference_io_entry_valid_14; + wire _reference_io_entry_valid_15; + wire _reference_io_entry_complete_0; + wire _reference_io_entry_complete_1; + wire _reference_io_entry_complete_2; + wire _reference_io_entry_complete_3; + wire _reference_io_entry_complete_4; + wire _reference_io_entry_complete_5; + wire _reference_io_entry_complete_6; + wire _reference_io_entry_complete_7; + wire _reference_io_entry_complete_8; + wire _reference_io_entry_complete_9; + wire _reference_io_entry_complete_10; + wire _reference_io_entry_complete_11; + wire _reference_io_entry_complete_12; + wire _reference_io_entry_complete_13; + wire _reference_io_entry_complete_14; + wire _reference_io_entry_complete_15; + wire [63:0] _reference_io_inst_ids_0; + wire [63:0] _reference_io_inst_ids_1; + wire [63:0] _reference_io_inst_ids_2; + wire [63:0] _reference_io_inst_ids_3; + wire [63:0] _reference_io_inst_ids_4; + wire [63:0] _reference_io_inst_ids_5; + wire [63:0] _reference_io_inst_ids_6; + wire [63:0] _reference_io_inst_ids_7; + wire [63:0] _reference_io_inst_ids_8; + wire [63:0] _reference_io_inst_ids_9; + wire [63:0] _reference_io_inst_ids_10; + wire [63:0] _reference_io_inst_ids_11; + wire [63:0] _reference_io_inst_ids_12; + wire [63:0] _reference_io_inst_ids_13; + wire [63:0] _reference_io_inst_ids_14; + wire [63:0] _reference_io_inst_ids_15; + wire _dut_io_alloc_ready; + wire _dut_io_issue_valid; + wire [3:0] _dut_io_issue_bits_cmd_domain_id; + wire [4:0] _dut_io_issue_bits_cmd_ball_bid; + wire [31:0] _dut_io_issue_bits_cmd_cmd_raw_inst; + wire [63:0] _dut_io_issue_bits_cmd_cmd_pc; + wire [6:0] _dut_io_issue_bits_cmd_cmd_funct; + wire [2:0] _dut_io_issue_bits_cmd_cmd_funct3; + wire [4:0] _dut_io_issue_bits_cmd_cmd_rs2; + wire [4:0] _dut_io_issue_bits_cmd_cmd_rs1; + wire _dut_io_issue_bits_cmd_cmd_xd; + wire _dut_io_issue_bits_cmd_cmd_xs1; + wire _dut_io_issue_bits_cmd_cmd_xs2; + wire [4:0] _dut_io_issue_bits_cmd_cmd_rd; + wire [6:0] _dut_io_issue_bits_cmd_cmd_opcode; + wire [63:0] _dut_io_issue_bits_cmd_cmd_rs1Data; + wire [63:0] _dut_io_issue_bits_cmd_cmd_rs2Data; + wire _dut_io_issue_bits_cmd_bankAccess_rd_bank_0_valid; + wire [9:0] _dut_io_issue_bits_cmd_bankAccess_rd_bank_0_id; + wire _dut_io_issue_bits_cmd_bankAccess_rd_bank_1_valid; + wire [9:0] _dut_io_issue_bits_cmd_bankAccess_rd_bank_1_id; + wire _dut_io_issue_bits_cmd_bankAccess_wr_bank_valid; + wire [9:0] _dut_io_issue_bits_cmd_bankAccess_wr_bank_id; + wire [3:0] _dut_io_issue_bits_cmd_op1_col; + wire [3:0] _dut_io_issue_bits_cmd_op2_col; + wire [3:0] _dut_io_issue_bits_cmd_wr_col; + wire _dut_io_issue_bits_cmd_isFence; + wire _dut_io_issue_bits_cmd_isBarrier; + wire _dut_io_issue_bits_renamedBankAccess_rd_bank_0_valid; + wire [9:0] _dut_io_issue_bits_renamedBankAccess_rd_bank_0_id; + wire _dut_io_issue_bits_renamedBankAccess_rd_bank_1_valid; + wire [9:0] _dut_io_issue_bits_renamedBankAccess_rd_bank_1_id; + wire _dut_io_issue_bits_renamedBankAccess_wr_bank_valid; + wire [9:0] _dut_io_issue_bits_renamedBankAccess_wr_bank_id; + wire [3:0] _dut_io_issue_bits_rob_id; + wire _dut_io_empty; + wire _dut_io_full; + wire [3:0] _dut_io_head_ptr; + wire [4:0] _dut_io_issued_count; + wire _dut_io_entry_valid_0; + wire _dut_io_entry_valid_1; + wire _dut_io_entry_valid_2; + wire _dut_io_entry_valid_3; + wire _dut_io_entry_valid_4; + wire _dut_io_entry_valid_5; + wire _dut_io_entry_valid_6; + wire _dut_io_entry_valid_7; + wire _dut_io_entry_valid_8; + wire _dut_io_entry_valid_9; + wire _dut_io_entry_valid_10; + wire _dut_io_entry_valid_11; + wire _dut_io_entry_valid_12; + wire _dut_io_entry_valid_13; + wire _dut_io_entry_valid_14; + wire _dut_io_entry_valid_15; + wire _dut_io_entry_complete_0; + wire _dut_io_entry_complete_1; + wire _dut_io_entry_complete_2; + wire _dut_io_entry_complete_3; + wire _dut_io_entry_complete_4; + wire _dut_io_entry_complete_5; + wire _dut_io_entry_complete_6; + wire _dut_io_entry_complete_7; + wire _dut_io_entry_complete_8; + wire _dut_io_entry_complete_9; + wire _dut_io_entry_complete_10; + wire _dut_io_entry_complete_11; + wire _dut_io_entry_complete_12; + wire _dut_io_entry_complete_13; + wire _dut_io_entry_complete_14; + wire _dut_io_entry_complete_15; + wire [63:0] _dut_io_inst_ids_0; + wire [63:0] _dut_io_inst_ids_1; + wire [63:0] _dut_io_inst_ids_2; + wire [63:0] _dut_io_inst_ids_3; + wire [63:0] _dut_io_inst_ids_4; + wire [63:0] _dut_io_inst_ids_5; + wire [63:0] _dut_io_inst_ids_6; + wire [63:0] _dut_io_inst_ids_7; + wire [63:0] _dut_io_inst_ids_8; + wire [63:0] _dut_io_inst_ids_9; + wire [63:0] _dut_io_inst_ids_10; + wire [63:0] _dut_io_inst_ids_11; + wire [63:0] _dut_io_inst_ids_12; + wire [63:0] _dut_io_inst_ids_13; + wire [63:0] _dut_io_inst_ids_14; + wire [63:0] _dut_io_inst_ids_15; + reg [15:0] cycle; + reg [31:0] random; + wire active = cycle[9:6] == 4'hD; + wire ready = _completions_io_enq_ready & random[7] & cycle[8:5] != 4'h7; + wire _completions_io_enq_valid_T = ready & _dut_io_issue_valid; + wire _dut_io_complete_valid_T_1 = _completions_io_deq_valid & random[4]; + reg [15:0] allocated; + reg [15:0] issued; + reg [15:0] completed; + reg sawFull; + reg sawStall; + reg [31:0] expected_0_raw_inst; + reg [63:0] expected_0_pc; + reg [6:0] expected_0_funct; + reg [2:0] expected_0_funct3; + reg [4:0] expected_0_rs2; + reg [4:0] expected_0_rs1; + reg expected_0_xd; + reg expected_0_xs1; + reg expected_0_xs2; + reg [4:0] expected_0_rd; + reg [6:0] expected_0_opcode; + reg [63:0] expected_0_rs1Data; + reg [63:0] expected_0_rs2Data; + reg [31:0] expected_1_raw_inst; + reg [63:0] expected_1_pc; + reg [6:0] expected_1_funct; + reg [2:0] expected_1_funct3; + reg [4:0] expected_1_rs2; + reg [4:0] expected_1_rs1; + reg expected_1_xd; + reg expected_1_xs1; + reg expected_1_xs2; + reg [4:0] expected_1_rd; + reg [6:0] expected_1_opcode; + reg [63:0] expected_1_rs1Data; + reg [63:0] expected_1_rs2Data; + reg [31:0] expected_2_raw_inst; + reg [63:0] expected_2_pc; + reg [6:0] expected_2_funct; + reg [2:0] expected_2_funct3; + reg [4:0] expected_2_rs2; + reg [4:0] expected_2_rs1; + reg expected_2_xd; + reg expected_2_xs1; + reg expected_2_xs2; + reg [4:0] expected_2_rd; + reg [6:0] expected_2_opcode; + reg [63:0] expected_2_rs1Data; + reg [63:0] expected_2_rs2Data; + reg [31:0] expected_3_raw_inst; + reg [63:0] expected_3_pc; + reg [6:0] expected_3_funct; + reg [2:0] expected_3_funct3; + reg [4:0] expected_3_rs2; + reg [4:0] expected_3_rs1; + reg expected_3_xd; + reg expected_3_xs1; + reg expected_3_xs2; + reg [4:0] expected_3_rd; + reg [6:0] expected_3_opcode; + reg [63:0] expected_3_rs1Data; + reg [63:0] expected_3_rs2Data; + reg [31:0] expected_4_raw_inst; + reg [63:0] expected_4_pc; + reg [6:0] expected_4_funct; + reg [2:0] expected_4_funct3; + reg [4:0] expected_4_rs2; + reg [4:0] expected_4_rs1; + reg expected_4_xd; + reg expected_4_xs1; + reg expected_4_xs2; + reg [4:0] expected_4_rd; + reg [6:0] expected_4_opcode; + reg [63:0] expected_4_rs1Data; + reg [63:0] expected_4_rs2Data; + reg [31:0] expected_5_raw_inst; + reg [63:0] expected_5_pc; + reg [6:0] expected_5_funct; + reg [2:0] expected_5_funct3; + reg [4:0] expected_5_rs2; + reg [4:0] expected_5_rs1; + reg expected_5_xd; + reg expected_5_xs1; + reg expected_5_xs2; + reg [4:0] expected_5_rd; + reg [6:0] expected_5_opcode; + reg [63:0] expected_5_rs1Data; + reg [63:0] expected_5_rs2Data; + reg [31:0] expected_6_raw_inst; + reg [63:0] expected_6_pc; + reg [6:0] expected_6_funct; + reg [2:0] expected_6_funct3; + reg [4:0] expected_6_rs2; + reg [4:0] expected_6_rs1; + reg expected_6_xd; + reg expected_6_xs1; + reg expected_6_xs2; + reg [4:0] expected_6_rd; + reg [6:0] expected_6_opcode; + reg [63:0] expected_6_rs1Data; + reg [63:0] expected_6_rs2Data; + reg [31:0] expected_7_raw_inst; + reg [63:0] expected_7_pc; + reg [6:0] expected_7_funct; + reg [2:0] expected_7_funct3; + reg [4:0] expected_7_rs2; + reg [4:0] expected_7_rs1; + reg expected_7_xd; + reg expected_7_xs1; + reg expected_7_xs2; + reg [4:0] expected_7_rd; + reg [6:0] expected_7_opcode; + reg [63:0] expected_7_rs1Data; + reg [63:0] expected_7_rs2Data; + reg [31:0] expected_8_raw_inst; + reg [63:0] expected_8_pc; + reg [6:0] expected_8_funct; + reg [2:0] expected_8_funct3; + reg [4:0] expected_8_rs2; + reg [4:0] expected_8_rs1; + reg expected_8_xd; + reg expected_8_xs1; + reg expected_8_xs2; + reg [4:0] expected_8_rd; + reg [6:0] expected_8_opcode; + reg [63:0] expected_8_rs1Data; + reg [63:0] expected_8_rs2Data; + reg [31:0] expected_9_raw_inst; + reg [63:0] expected_9_pc; + reg [6:0] expected_9_funct; + reg [2:0] expected_9_funct3; + reg [4:0] expected_9_rs2; + reg [4:0] expected_9_rs1; + reg expected_9_xd; + reg expected_9_xs1; + reg expected_9_xs2; + reg [4:0] expected_9_rd; + reg [6:0] expected_9_opcode; + reg [63:0] expected_9_rs1Data; + reg [63:0] expected_9_rs2Data; + reg [31:0] expected_10_raw_inst; + reg [63:0] expected_10_pc; + reg [6:0] expected_10_funct; + reg [2:0] expected_10_funct3; + reg [4:0] expected_10_rs2; + reg [4:0] expected_10_rs1; + reg expected_10_xd; + reg expected_10_xs1; + reg expected_10_xs2; + reg [4:0] expected_10_rd; + reg [6:0] expected_10_opcode; + reg [63:0] expected_10_rs1Data; + reg [63:0] expected_10_rs2Data; + reg [31:0] expected_11_raw_inst; + reg [63:0] expected_11_pc; + reg [6:0] expected_11_funct; + reg [2:0] expected_11_funct3; + reg [4:0] expected_11_rs2; + reg [4:0] expected_11_rs1; + reg expected_11_xd; + reg expected_11_xs1; + reg expected_11_xs2; + reg [4:0] expected_11_rd; + reg [6:0] expected_11_opcode; + reg [63:0] expected_11_rs1Data; + reg [63:0] expected_11_rs2Data; + reg [31:0] expected_12_raw_inst; + reg [63:0] expected_12_pc; + reg [6:0] expected_12_funct; + reg [2:0] expected_12_funct3; + reg [4:0] expected_12_rs2; + reg [4:0] expected_12_rs1; + reg expected_12_xd; + reg expected_12_xs1; + reg expected_12_xs2; + reg [4:0] expected_12_rd; + reg [6:0] expected_12_opcode; + reg [63:0] expected_12_rs1Data; + reg [63:0] expected_12_rs2Data; + reg [31:0] expected_13_raw_inst; + reg [63:0] expected_13_pc; + reg [6:0] expected_13_funct; + reg [2:0] expected_13_funct3; + reg [4:0] expected_13_rs2; + reg [4:0] expected_13_rs1; + reg expected_13_xd; + reg expected_13_xs1; + reg expected_13_xs2; + reg [4:0] expected_13_rd; + reg [6:0] expected_13_opcode; + reg [63:0] expected_13_rs1Data; + reg [63:0] expected_13_rs2Data; + reg [31:0] expected_14_raw_inst; + reg [63:0] expected_14_pc; + reg [6:0] expected_14_funct; + reg [2:0] expected_14_funct3; + reg [4:0] expected_14_rs2; + reg [4:0] expected_14_rs1; + reg expected_14_xd; + reg expected_14_xs1; + reg expected_14_xs2; + reg [4:0] expected_14_rd; + reg [6:0] expected_14_opcode; + reg [63:0] expected_14_rs1Data; + reg [63:0] expected_14_rs2Data; + reg [31:0] expected_15_raw_inst; + reg [63:0] expected_15_pc; + reg [6:0] expected_15_funct; + reg [2:0] expected_15_funct3; + reg [4:0] expected_15_rs2; + reg [4:0] expected_15_rs1; + reg expected_15_xd; + reg expected_15_xs1; + reg expected_15_xs2; + reg [4:0] expected_15_rd; + reg [6:0] expected_15_opcode; + reg [63:0] expected_15_rs1Data; + reg [63:0] expected_15_rs2Data; + reg [3:0] allocationSlot; + wire _passed_output = + cycle > 16'h138D & ~_source_io_deq_valid & _dut_io_empty & ~_completions_io_deq_valid; + `ifndef SYNTHESIS + always @(posedge clock) begin + automatic logic _GEN = _passed_output & ~reset; + automatic logic [15:0][63:0] _GEN_0 = + {{expected_15_rs2Data}, + {expected_14_rs2Data}, + {expected_13_rs2Data}, + {expected_12_rs2Data}, + {expected_11_rs2Data}, + {expected_10_rs2Data}, + {expected_9_rs2Data}, + {expected_8_rs2Data}, + {expected_7_rs2Data}, + {expected_6_rs2Data}, + {expected_5_rs2Data}, + {expected_4_rs2Data}, + {expected_3_rs2Data}, + {expected_2_rs2Data}, + {expected_1_rs2Data}, + {expected_0_rs2Data}}; + automatic logic [15:0][63:0] _GEN_1 = + {{expected_15_rs1Data}, + {expected_14_rs1Data}, + {expected_13_rs1Data}, + {expected_12_rs1Data}, + {expected_11_rs1Data}, + {expected_10_rs1Data}, + {expected_9_rs1Data}, + {expected_8_rs1Data}, + {expected_7_rs1Data}, + {expected_6_rs1Data}, + {expected_5_rs1Data}, + {expected_4_rs1Data}, + {expected_3_rs1Data}, + {expected_2_rs1Data}, + {expected_1_rs1Data}, + {expected_0_rs1Data}}; + automatic logic [15:0][6:0] _GEN_2 = + {{expected_15_opcode}, + {expected_14_opcode}, + {expected_13_opcode}, + {expected_12_opcode}, + {expected_11_opcode}, + {expected_10_opcode}, + {expected_9_opcode}, + {expected_8_opcode}, + {expected_7_opcode}, + {expected_6_opcode}, + {expected_5_opcode}, + {expected_4_opcode}, + {expected_3_opcode}, + {expected_2_opcode}, + {expected_1_opcode}, + {expected_0_opcode}}; + automatic logic [15:0][4:0] _GEN_3 = + {{expected_15_rd}, + {expected_14_rd}, + {expected_13_rd}, + {expected_12_rd}, + {expected_11_rd}, + {expected_10_rd}, + {expected_9_rd}, + {expected_8_rd}, + {expected_7_rd}, + {expected_6_rd}, + {expected_5_rd}, + {expected_4_rd}, + {expected_3_rd}, + {expected_2_rd}, + {expected_1_rd}, + {expected_0_rd}}; + automatic logic [15:0] _GEN_4 = + {{expected_15_xs2}, + {expected_14_xs2}, + {expected_13_xs2}, + {expected_12_xs2}, + {expected_11_xs2}, + {expected_10_xs2}, + {expected_9_xs2}, + {expected_8_xs2}, + {expected_7_xs2}, + {expected_6_xs2}, + {expected_5_xs2}, + {expected_4_xs2}, + {expected_3_xs2}, + {expected_2_xs2}, + {expected_1_xs2}, + {expected_0_xs2}}; + automatic logic [15:0] _GEN_5 = + {{expected_15_xs1}, + {expected_14_xs1}, + {expected_13_xs1}, + {expected_12_xs1}, + {expected_11_xs1}, + {expected_10_xs1}, + {expected_9_xs1}, + {expected_8_xs1}, + {expected_7_xs1}, + {expected_6_xs1}, + {expected_5_xs1}, + {expected_4_xs1}, + {expected_3_xs1}, + {expected_2_xs1}, + {expected_1_xs1}, + {expected_0_xs1}}; + automatic logic [15:0] _GEN_6 = + {{expected_15_xd}, + {expected_14_xd}, + {expected_13_xd}, + {expected_12_xd}, + {expected_11_xd}, + {expected_10_xd}, + {expected_9_xd}, + {expected_8_xd}, + {expected_7_xd}, + {expected_6_xd}, + {expected_5_xd}, + {expected_4_xd}, + {expected_3_xd}, + {expected_2_xd}, + {expected_1_xd}, + {expected_0_xd}}; + automatic logic [15:0][4:0] _GEN_7 = + {{expected_15_rs1}, + {expected_14_rs1}, + {expected_13_rs1}, + {expected_12_rs1}, + {expected_11_rs1}, + {expected_10_rs1}, + {expected_9_rs1}, + {expected_8_rs1}, + {expected_7_rs1}, + {expected_6_rs1}, + {expected_5_rs1}, + {expected_4_rs1}, + {expected_3_rs1}, + {expected_2_rs1}, + {expected_1_rs1}, + {expected_0_rs1}}; + automatic logic [15:0][4:0] _GEN_8 = + {{expected_15_rs2}, + {expected_14_rs2}, + {expected_13_rs2}, + {expected_12_rs2}, + {expected_11_rs2}, + {expected_10_rs2}, + {expected_9_rs2}, + {expected_8_rs2}, + {expected_7_rs2}, + {expected_6_rs2}, + {expected_5_rs2}, + {expected_4_rs2}, + {expected_3_rs2}, + {expected_2_rs2}, + {expected_1_rs2}, + {expected_0_rs2}}; + automatic logic [15:0][2:0] _GEN_9 = + {{expected_15_funct3}, + {expected_14_funct3}, + {expected_13_funct3}, + {expected_12_funct3}, + {expected_11_funct3}, + {expected_10_funct3}, + {expected_9_funct3}, + {expected_8_funct3}, + {expected_7_funct3}, + {expected_6_funct3}, + {expected_5_funct3}, + {expected_4_funct3}, + {expected_3_funct3}, + {expected_2_funct3}, + {expected_1_funct3}, + {expected_0_funct3}}; + automatic logic [15:0][6:0] _GEN_10 = + {{expected_15_funct}, + {expected_14_funct}, + {expected_13_funct}, + {expected_12_funct}, + {expected_11_funct}, + {expected_10_funct}, + {expected_9_funct}, + {expected_8_funct}, + {expected_7_funct}, + {expected_6_funct}, + {expected_5_funct}, + {expected_4_funct}, + {expected_3_funct}, + {expected_2_funct}, + {expected_1_funct}, + {expected_0_funct}}; + automatic logic [15:0][63:0] _GEN_11 = + {{expected_15_pc}, + {expected_14_pc}, + {expected_13_pc}, + {expected_12_pc}, + {expected_11_pc}, + {expected_10_pc}, + {expected_9_pc}, + {expected_8_pc}, + {expected_7_pc}, + {expected_6_pc}, + {expected_5_pc}, + {expected_4_pc}, + {expected_3_pc}, + {expected_2_pc}, + {expected_1_pc}, + {expected_0_pc}}; + automatic logic [15:0][31:0] _GEN_12 = + {{expected_15_raw_inst}, + {expected_14_raw_inst}, + {expected_13_raw_inst}, + {expected_12_raw_inst}, + {expected_11_raw_inst}, + {expected_10_raw_inst}, + {expected_9_raw_inst}, + {expected_8_raw_inst}, + {expected_7_raw_inst}, + {expected_6_raw_inst}, + {expected_5_raw_inst}, + {expected_4_raw_inst}, + {expected_3_raw_inst}, + {expected_2_raw_inst}, + {expected_1_raw_inst}, + {expected_0_raw_inst}}; + if (~reset & cycle > 16'h2327) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: GlobalROB drain timeout\n at EmitGlobalRobCheck.scala:21 assert(cycle < 9000.U, \"GlobalROB drain timeout\")\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & _dut_io_alloc_ready != _reference_io_alloc_ready) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: ROB allocation timing mismatch\n at EmitGlobalRobCheck.scala:65 assert(dut.io.alloc.ready === reference.io.alloc.ready, \"ROB allocation timing mismatch\")\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & _dut_io_issue_valid != _reference_io_issue_valid) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: ROB issue timing mismatch\n at EmitGlobalRobCheck.scala:67 assert(dut.io.issue.valid === reference.io.issue.valid, \"ROB issue timing mismatch\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_dut_io_issue_valid & ~reset + & {_dut_io_issue_bits_cmd_domain_id, + _dut_io_issue_bits_cmd_ball_bid, + _dut_io_issue_bits_cmd_cmd_raw_inst, + _dut_io_issue_bits_cmd_cmd_pc, + _dut_io_issue_bits_cmd_cmd_funct, + _dut_io_issue_bits_cmd_cmd_funct3, + _dut_io_issue_bits_cmd_cmd_rs2, + _dut_io_issue_bits_cmd_cmd_rs1, + _dut_io_issue_bits_cmd_cmd_xd, + _dut_io_issue_bits_cmd_cmd_xs1, + _dut_io_issue_bits_cmd_cmd_xs2, + _dut_io_issue_bits_cmd_cmd_rd, + _dut_io_issue_bits_cmd_cmd_opcode, + _dut_io_issue_bits_cmd_cmd_rs1Data, + _dut_io_issue_bits_cmd_cmd_rs2Data, + _dut_io_issue_bits_cmd_bankAccess_rd_bank_0_valid, + _dut_io_issue_bits_cmd_bankAccess_rd_bank_0_id, + _dut_io_issue_bits_cmd_bankAccess_rd_bank_1_valid, + _dut_io_issue_bits_cmd_bankAccess_rd_bank_1_id, + _dut_io_issue_bits_cmd_bankAccess_wr_bank_valid, + _dut_io_issue_bits_cmd_bankAccess_wr_bank_id, + _dut_io_issue_bits_cmd_op1_col, + _dut_io_issue_bits_cmd_op2_col, + _dut_io_issue_bits_cmd_wr_col, + _dut_io_issue_bits_cmd_isFence, + _dut_io_issue_bits_cmd_isBarrier, + _dut_io_issue_bits_renamedBankAccess_rd_bank_0_valid, + _dut_io_issue_bits_renamedBankAccess_rd_bank_0_id, + _dut_io_issue_bits_renamedBankAccess_rd_bank_1_valid, + _dut_io_issue_bits_renamedBankAccess_rd_bank_1_id, + _dut_io_issue_bits_renamedBankAccess_wr_bank_valid, + _dut_io_issue_bits_renamedBankAccess_wr_bank_id, + _dut_io_issue_bits_rob_id} != {_reference_io_issue_bits_cmd_domain_id, + _reference_io_issue_bits_cmd_ball_bid, + _reference_io_issue_bits_cmd_cmd_raw_inst, + _reference_io_issue_bits_cmd_cmd_pc, + _reference_io_issue_bits_cmd_cmd_funct, + _reference_io_issue_bits_cmd_cmd_funct3, + _reference_io_issue_bits_cmd_cmd_rs2, + _reference_io_issue_bits_cmd_cmd_rs1, + _reference_io_issue_bits_cmd_cmd_xd, + _reference_io_issue_bits_cmd_cmd_xs1, + _reference_io_issue_bits_cmd_cmd_xs2, + _reference_io_issue_bits_cmd_cmd_rd, + _reference_io_issue_bits_cmd_cmd_opcode, + _reference_io_issue_bits_cmd_cmd_rs1Data, + _reference_io_issue_bits_cmd_cmd_rs2Data, + _reference_io_issue_bits_cmd_bankAccess_rd_bank_0_valid, + _reference_io_issue_bits_cmd_bankAccess_rd_bank_0_id, + _reference_io_issue_bits_cmd_bankAccess_rd_bank_1_valid, + _reference_io_issue_bits_cmd_bankAccess_rd_bank_1_id, + _reference_io_issue_bits_cmd_bankAccess_wr_bank_valid, + _reference_io_issue_bits_cmd_bankAccess_wr_bank_id, + _reference_io_issue_bits_cmd_op1_col, + _reference_io_issue_bits_cmd_op2_col, + _reference_io_issue_bits_cmd_wr_col, + _reference_io_issue_bits_cmd_isFence, + _reference_io_issue_bits_cmd_isBarrier, + _reference_io_issue_bits_renamedBankAccess_rd_bank_0_valid, + _reference_io_issue_bits_renamedBankAccess_rd_bank_0_id, + _reference_io_issue_bits_renamedBankAccess_rd_bank_1_valid, + _reference_io_issue_bits_renamedBankAccess_rd_bank_1_id, + _reference_io_issue_bits_renamedBankAccess_wr_bank_valid, + _reference_io_issue_bits_renamedBankAccess_wr_bank_id, + _reference_io_issue_bits_rob_id}) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: ROB issue payload mismatch\n at EmitGlobalRobCheck.scala:69 assert(dut.io.issue.bits.asUInt === reference.io.issue.bits.asUInt, \"ROB issue payload mismatch\")\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset + & ~(_dut_io_empty == _reference_io_empty + & _dut_io_full == _reference_io_full)) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitGlobalRobCheck.scala:71 assert(dut.io.empty === reference.io.empty && dut.io.full === reference.io.full)\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & _dut_io_head_ptr != _reference_io_head_ptr) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitGlobalRobCheck.scala:72 assert(dut.io.head_ptr === reference.io.head_ptr)\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & _dut_io_issued_count != _reference_io_issued_count) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitGlobalRobCheck.scala:73 assert(dut.io.issued_count === reference.io.issued_count)\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset + & {_dut_io_entry_valid_15, + _dut_io_entry_valid_14, + _dut_io_entry_valid_13, + _dut_io_entry_valid_12, + _dut_io_entry_valid_11, + _dut_io_entry_valid_10, + _dut_io_entry_valid_9, + _dut_io_entry_valid_8, + _dut_io_entry_valid_7, + _dut_io_entry_valid_6, + _dut_io_entry_valid_5, + _dut_io_entry_valid_4, + _dut_io_entry_valid_3, + _dut_io_entry_valid_2, + _dut_io_entry_valid_1, + _dut_io_entry_valid_0} != {_reference_io_entry_valid_15, + _reference_io_entry_valid_14, + _reference_io_entry_valid_13, + _reference_io_entry_valid_12, + _reference_io_entry_valid_11, + _reference_io_entry_valid_10, + _reference_io_entry_valid_9, + _reference_io_entry_valid_8, + _reference_io_entry_valid_7, + _reference_io_entry_valid_6, + _reference_io_entry_valid_5, + _reference_io_entry_valid_4, + _reference_io_entry_valid_3, + _reference_io_entry_valid_2, + _reference_io_entry_valid_1, + _reference_io_entry_valid_0}) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitGlobalRobCheck.scala:74 assert(dut.io.entry_valid.asUInt === reference.io.entry_valid.asUInt)\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset + & {_dut_io_entry_complete_15, + _dut_io_entry_complete_14, + _dut_io_entry_complete_13, + _dut_io_entry_complete_12, + _dut_io_entry_complete_11, + _dut_io_entry_complete_10, + _dut_io_entry_complete_9, + _dut_io_entry_complete_8, + _dut_io_entry_complete_7, + _dut_io_entry_complete_6, + _dut_io_entry_complete_5, + _dut_io_entry_complete_4, + _dut_io_entry_complete_3, + _dut_io_entry_complete_2, + _dut_io_entry_complete_1, + _dut_io_entry_complete_0} != {_reference_io_entry_complete_15, + _reference_io_entry_complete_14, + _reference_io_entry_complete_13, + _reference_io_entry_complete_12, + _reference_io_entry_complete_11, + _reference_io_entry_complete_10, + _reference_io_entry_complete_9, + _reference_io_entry_complete_8, + _reference_io_entry_complete_7, + _reference_io_entry_complete_6, + _reference_io_entry_complete_5, + _reference_io_entry_complete_4, + _reference_io_entry_complete_3, + _reference_io_entry_complete_2, + _reference_io_entry_complete_1, + _reference_io_entry_complete_0}) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitGlobalRobCheck.scala:75 assert(dut.io.entry_complete.asUInt === reference.io.entry_complete.asUInt)\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset + & {_dut_io_inst_ids_15, + _dut_io_inst_ids_14, + _dut_io_inst_ids_13, + _dut_io_inst_ids_12, + _dut_io_inst_ids_11, + _dut_io_inst_ids_10, + _dut_io_inst_ids_9, + _dut_io_inst_ids_8, + _dut_io_inst_ids_7, + _dut_io_inst_ids_6, + _dut_io_inst_ids_5, + _dut_io_inst_ids_4, + _dut_io_inst_ids_3, + _dut_io_inst_ids_2, + _dut_io_inst_ids_1, + _dut_io_inst_ids_0} != {_reference_io_inst_ids_15, + _reference_io_inst_ids_14, + _reference_io_inst_ids_13, + _reference_io_inst_ids_12, + _reference_io_inst_ids_11, + _reference_io_inst_ids_10, + _reference_io_inst_ids_9, + _reference_io_inst_ids_8, + _reference_io_inst_ids_7, + _reference_io_inst_ids_6, + _reference_io_inst_ids_5, + _reference_io_inst_ids_4, + _reference_io_inst_ids_3, + _reference_io_inst_ids_2, + _reference_io_inst_ids_1, + _reference_io_inst_ids_0}) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitGlobalRobCheck.scala:76 assert(dut.io.inst_ids.asUInt === reference.io.inst_ids.asUInt)\n"); + if (`STOP_COND_) + $fatal; + end + if (_completions_io_enq_valid_T & ~reset + & {_dut_io_issue_bits_cmd_cmd_raw_inst, + _dut_io_issue_bits_cmd_cmd_pc, + _dut_io_issue_bits_cmd_cmd_funct, + _dut_io_issue_bits_cmd_cmd_funct3, + _dut_io_issue_bits_cmd_cmd_rs2, + _dut_io_issue_bits_cmd_cmd_rs1, + _dut_io_issue_bits_cmd_cmd_xd, + _dut_io_issue_bits_cmd_cmd_xs1, + _dut_io_issue_bits_cmd_cmd_xs2, + _dut_io_issue_bits_cmd_cmd_rd, + _dut_io_issue_bits_cmd_cmd_opcode, + _dut_io_issue_bits_cmd_cmd_rs1Data, + _dut_io_issue_bits_cmd_cmd_rs2Data} != {_GEN_12[_dut_io_issue_bits_rob_id], + _GEN_11[_dut_io_issue_bits_rob_id], + _GEN_10[_dut_io_issue_bits_rob_id], + _GEN_9[_dut_io_issue_bits_rob_id], + _GEN_8[_dut_io_issue_bits_rob_id], + _GEN_7[_dut_io_issue_bits_rob_id], + _GEN_6[_dut_io_issue_bits_rob_id], + _GEN_5[_dut_io_issue_bits_rob_id], + _GEN_4[_dut_io_issue_bits_rob_id], + _GEN_3[_dut_io_issue_bits_rob_id], + _GEN_2[_dut_io_issue_bits_rob_id], + _GEN_1[_dut_io_issue_bits_rob_id], + _GEN_0[_dut_io_issue_bits_rob_id]}) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: ROB changed accepted command operands\n at EmitGlobalRobCheck.scala:93 assert(dut.io.issue.bits.cmd.cmd.asUInt === expected(dut.io.issue.bits.rob_id).asUInt,\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN & ~(allocated == issued & issued == completed & allocated > 16'h40)) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitGlobalRobCheck.scala:101 assert(allocated === issued && issued === completed && allocated > 64.U)\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN & ~(sawFull & sawStall)) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: Missing ROB full/stall coverage\n at EmitGlobalRobCheck.scala:102 assert(sawFull && sawStall, \"Missing ROB full/stall coverage\")\n"); + if (`STOP_COND_) + $fatal; + end + end // always @(posedge) + `endif // not def SYNTHESIS + always @(posedge clock) begin + automatic logic _GEN_13; + _GEN_13 = _dut_io_alloc_ready & _source_io_deq_valid; + if (reset) begin + cycle <= 16'h0; + random <= seed; + allocated <= 16'h0; + issued <= 16'h0; + completed <= 16'h0; + sawFull <= 1'h0; + sawStall <= 1'h0; + allocationSlot <= 4'h0; + end + else begin + cycle <= cycle + 16'h1; + random <= {random[30:0], random[31] ^ random[21] ^ random[1] ^ random[0]}; + if (_GEN_13) begin + allocated <= allocated + 16'h1; + if (&allocationSlot) + allocationSlot <= 4'h0; + else + allocationSlot <= allocationSlot + 4'h1; + end + if (_completions_io_enq_valid_T) + issued <= issued + 16'h1; + if (_dut_io_complete_valid_T_1) + completed <= completed + 16'h1; + sawFull <= _dut_io_full | sawFull; + sawStall <= _dut_io_issue_valid & ~ready | sawStall; + end + if (_GEN_13 & allocationSlot == 4'h0) begin + expected_0_raw_inst <= _source_io_deq_bits_cmd_raw_inst; + expected_0_pc <= _source_io_deq_bits_cmd_pc; + expected_0_funct <= _source_io_deq_bits_cmd_funct; + expected_0_funct3 <= _source_io_deq_bits_cmd_funct3; + expected_0_rs2 <= _source_io_deq_bits_cmd_rs2; + expected_0_rs1 <= _source_io_deq_bits_cmd_rs1; + expected_0_xd <= _source_io_deq_bits_cmd_xd; + expected_0_xs1 <= _source_io_deq_bits_cmd_xs1; + expected_0_xs2 <= _source_io_deq_bits_cmd_xs2; + expected_0_rd <= _source_io_deq_bits_cmd_rd; + expected_0_opcode <= _source_io_deq_bits_cmd_opcode; + expected_0_rs1Data <= _source_io_deq_bits_cmd_rs1Data; + expected_0_rs2Data <= _source_io_deq_bits_cmd_rs2Data; + end + if (_GEN_13 & allocationSlot == 4'h1) begin + expected_1_raw_inst <= _source_io_deq_bits_cmd_raw_inst; + expected_1_pc <= _source_io_deq_bits_cmd_pc; + expected_1_funct <= _source_io_deq_bits_cmd_funct; + expected_1_funct3 <= _source_io_deq_bits_cmd_funct3; + expected_1_rs2 <= _source_io_deq_bits_cmd_rs2; + expected_1_rs1 <= _source_io_deq_bits_cmd_rs1; + expected_1_xd <= _source_io_deq_bits_cmd_xd; + expected_1_xs1 <= _source_io_deq_bits_cmd_xs1; + expected_1_xs2 <= _source_io_deq_bits_cmd_xs2; + expected_1_rd <= _source_io_deq_bits_cmd_rd; + expected_1_opcode <= _source_io_deq_bits_cmd_opcode; + expected_1_rs1Data <= _source_io_deq_bits_cmd_rs1Data; + expected_1_rs2Data <= _source_io_deq_bits_cmd_rs2Data; + end + if (_GEN_13 & allocationSlot == 4'h2) begin + expected_2_raw_inst <= _source_io_deq_bits_cmd_raw_inst; + expected_2_pc <= _source_io_deq_bits_cmd_pc; + expected_2_funct <= _source_io_deq_bits_cmd_funct; + expected_2_funct3 <= _source_io_deq_bits_cmd_funct3; + expected_2_rs2 <= _source_io_deq_bits_cmd_rs2; + expected_2_rs1 <= _source_io_deq_bits_cmd_rs1; + expected_2_xd <= _source_io_deq_bits_cmd_xd; + expected_2_xs1 <= _source_io_deq_bits_cmd_xs1; + expected_2_xs2 <= _source_io_deq_bits_cmd_xs2; + expected_2_rd <= _source_io_deq_bits_cmd_rd; + expected_2_opcode <= _source_io_deq_bits_cmd_opcode; + expected_2_rs1Data <= _source_io_deq_bits_cmd_rs1Data; + expected_2_rs2Data <= _source_io_deq_bits_cmd_rs2Data; + end + if (_GEN_13 & allocationSlot == 4'h3) begin + expected_3_raw_inst <= _source_io_deq_bits_cmd_raw_inst; + expected_3_pc <= _source_io_deq_bits_cmd_pc; + expected_3_funct <= _source_io_deq_bits_cmd_funct; + expected_3_funct3 <= _source_io_deq_bits_cmd_funct3; + expected_3_rs2 <= _source_io_deq_bits_cmd_rs2; + expected_3_rs1 <= _source_io_deq_bits_cmd_rs1; + expected_3_xd <= _source_io_deq_bits_cmd_xd; + expected_3_xs1 <= _source_io_deq_bits_cmd_xs1; + expected_3_xs2 <= _source_io_deq_bits_cmd_xs2; + expected_3_rd <= _source_io_deq_bits_cmd_rd; + expected_3_opcode <= _source_io_deq_bits_cmd_opcode; + expected_3_rs1Data <= _source_io_deq_bits_cmd_rs1Data; + expected_3_rs2Data <= _source_io_deq_bits_cmd_rs2Data; + end + if (_GEN_13 & allocationSlot == 4'h4) begin + expected_4_raw_inst <= _source_io_deq_bits_cmd_raw_inst; + expected_4_pc <= _source_io_deq_bits_cmd_pc; + expected_4_funct <= _source_io_deq_bits_cmd_funct; + expected_4_funct3 <= _source_io_deq_bits_cmd_funct3; + expected_4_rs2 <= _source_io_deq_bits_cmd_rs2; + expected_4_rs1 <= _source_io_deq_bits_cmd_rs1; + expected_4_xd <= _source_io_deq_bits_cmd_xd; + expected_4_xs1 <= _source_io_deq_bits_cmd_xs1; + expected_4_xs2 <= _source_io_deq_bits_cmd_xs2; + expected_4_rd <= _source_io_deq_bits_cmd_rd; + expected_4_opcode <= _source_io_deq_bits_cmd_opcode; + expected_4_rs1Data <= _source_io_deq_bits_cmd_rs1Data; + expected_4_rs2Data <= _source_io_deq_bits_cmd_rs2Data; + end + if (_GEN_13 & allocationSlot == 4'h5) begin + expected_5_raw_inst <= _source_io_deq_bits_cmd_raw_inst; + expected_5_pc <= _source_io_deq_bits_cmd_pc; + expected_5_funct <= _source_io_deq_bits_cmd_funct; + expected_5_funct3 <= _source_io_deq_bits_cmd_funct3; + expected_5_rs2 <= _source_io_deq_bits_cmd_rs2; + expected_5_rs1 <= _source_io_deq_bits_cmd_rs1; + expected_5_xd <= _source_io_deq_bits_cmd_xd; + expected_5_xs1 <= _source_io_deq_bits_cmd_xs1; + expected_5_xs2 <= _source_io_deq_bits_cmd_xs2; + expected_5_rd <= _source_io_deq_bits_cmd_rd; + expected_5_opcode <= _source_io_deq_bits_cmd_opcode; + expected_5_rs1Data <= _source_io_deq_bits_cmd_rs1Data; + expected_5_rs2Data <= _source_io_deq_bits_cmd_rs2Data; + end + if (_GEN_13 & allocationSlot == 4'h6) begin + expected_6_raw_inst <= _source_io_deq_bits_cmd_raw_inst; + expected_6_pc <= _source_io_deq_bits_cmd_pc; + expected_6_funct <= _source_io_deq_bits_cmd_funct; + expected_6_funct3 <= _source_io_deq_bits_cmd_funct3; + expected_6_rs2 <= _source_io_deq_bits_cmd_rs2; + expected_6_rs1 <= _source_io_deq_bits_cmd_rs1; + expected_6_xd <= _source_io_deq_bits_cmd_xd; + expected_6_xs1 <= _source_io_deq_bits_cmd_xs1; + expected_6_xs2 <= _source_io_deq_bits_cmd_xs2; + expected_6_rd <= _source_io_deq_bits_cmd_rd; + expected_6_opcode <= _source_io_deq_bits_cmd_opcode; + expected_6_rs1Data <= _source_io_deq_bits_cmd_rs1Data; + expected_6_rs2Data <= _source_io_deq_bits_cmd_rs2Data; + end + if (_GEN_13 & allocationSlot == 4'h7) begin + expected_7_raw_inst <= _source_io_deq_bits_cmd_raw_inst; + expected_7_pc <= _source_io_deq_bits_cmd_pc; + expected_7_funct <= _source_io_deq_bits_cmd_funct; + expected_7_funct3 <= _source_io_deq_bits_cmd_funct3; + expected_7_rs2 <= _source_io_deq_bits_cmd_rs2; + expected_7_rs1 <= _source_io_deq_bits_cmd_rs1; + expected_7_xd <= _source_io_deq_bits_cmd_xd; + expected_7_xs1 <= _source_io_deq_bits_cmd_xs1; + expected_7_xs2 <= _source_io_deq_bits_cmd_xs2; + expected_7_rd <= _source_io_deq_bits_cmd_rd; + expected_7_opcode <= _source_io_deq_bits_cmd_opcode; + expected_7_rs1Data <= _source_io_deq_bits_cmd_rs1Data; + expected_7_rs2Data <= _source_io_deq_bits_cmd_rs2Data; + end + if (_GEN_13 & allocationSlot == 4'h8) begin + expected_8_raw_inst <= _source_io_deq_bits_cmd_raw_inst; + expected_8_pc <= _source_io_deq_bits_cmd_pc; + expected_8_funct <= _source_io_deq_bits_cmd_funct; + expected_8_funct3 <= _source_io_deq_bits_cmd_funct3; + expected_8_rs2 <= _source_io_deq_bits_cmd_rs2; + expected_8_rs1 <= _source_io_deq_bits_cmd_rs1; + expected_8_xd <= _source_io_deq_bits_cmd_xd; + expected_8_xs1 <= _source_io_deq_bits_cmd_xs1; + expected_8_xs2 <= _source_io_deq_bits_cmd_xs2; + expected_8_rd <= _source_io_deq_bits_cmd_rd; + expected_8_opcode <= _source_io_deq_bits_cmd_opcode; + expected_8_rs1Data <= _source_io_deq_bits_cmd_rs1Data; + expected_8_rs2Data <= _source_io_deq_bits_cmd_rs2Data; + end + if (_GEN_13 & allocationSlot == 4'h9) begin + expected_9_raw_inst <= _source_io_deq_bits_cmd_raw_inst; + expected_9_pc <= _source_io_deq_bits_cmd_pc; + expected_9_funct <= _source_io_deq_bits_cmd_funct; + expected_9_funct3 <= _source_io_deq_bits_cmd_funct3; + expected_9_rs2 <= _source_io_deq_bits_cmd_rs2; + expected_9_rs1 <= _source_io_deq_bits_cmd_rs1; + expected_9_xd <= _source_io_deq_bits_cmd_xd; + expected_9_xs1 <= _source_io_deq_bits_cmd_xs1; + expected_9_xs2 <= _source_io_deq_bits_cmd_xs2; + expected_9_rd <= _source_io_deq_bits_cmd_rd; + expected_9_opcode <= _source_io_deq_bits_cmd_opcode; + expected_9_rs1Data <= _source_io_deq_bits_cmd_rs1Data; + expected_9_rs2Data <= _source_io_deq_bits_cmd_rs2Data; + end + if (_GEN_13 & allocationSlot == 4'hA) begin + expected_10_raw_inst <= _source_io_deq_bits_cmd_raw_inst; + expected_10_pc <= _source_io_deq_bits_cmd_pc; + expected_10_funct <= _source_io_deq_bits_cmd_funct; + expected_10_funct3 <= _source_io_deq_bits_cmd_funct3; + expected_10_rs2 <= _source_io_deq_bits_cmd_rs2; + expected_10_rs1 <= _source_io_deq_bits_cmd_rs1; + expected_10_xd <= _source_io_deq_bits_cmd_xd; + expected_10_xs1 <= _source_io_deq_bits_cmd_xs1; + expected_10_xs2 <= _source_io_deq_bits_cmd_xs2; + expected_10_rd <= _source_io_deq_bits_cmd_rd; + expected_10_opcode <= _source_io_deq_bits_cmd_opcode; + expected_10_rs1Data <= _source_io_deq_bits_cmd_rs1Data; + expected_10_rs2Data <= _source_io_deq_bits_cmd_rs2Data; + end + if (_GEN_13 & allocationSlot == 4'hB) begin + expected_11_raw_inst <= _source_io_deq_bits_cmd_raw_inst; + expected_11_pc <= _source_io_deq_bits_cmd_pc; + expected_11_funct <= _source_io_deq_bits_cmd_funct; + expected_11_funct3 <= _source_io_deq_bits_cmd_funct3; + expected_11_rs2 <= _source_io_deq_bits_cmd_rs2; + expected_11_rs1 <= _source_io_deq_bits_cmd_rs1; + expected_11_xd <= _source_io_deq_bits_cmd_xd; + expected_11_xs1 <= _source_io_deq_bits_cmd_xs1; + expected_11_xs2 <= _source_io_deq_bits_cmd_xs2; + expected_11_rd <= _source_io_deq_bits_cmd_rd; + expected_11_opcode <= _source_io_deq_bits_cmd_opcode; + expected_11_rs1Data <= _source_io_deq_bits_cmd_rs1Data; + expected_11_rs2Data <= _source_io_deq_bits_cmd_rs2Data; + end + if (_GEN_13 & allocationSlot == 4'hC) begin + expected_12_raw_inst <= _source_io_deq_bits_cmd_raw_inst; + expected_12_pc <= _source_io_deq_bits_cmd_pc; + expected_12_funct <= _source_io_deq_bits_cmd_funct; + expected_12_funct3 <= _source_io_deq_bits_cmd_funct3; + expected_12_rs2 <= _source_io_deq_bits_cmd_rs2; + expected_12_rs1 <= _source_io_deq_bits_cmd_rs1; + expected_12_xd <= _source_io_deq_bits_cmd_xd; + expected_12_xs1 <= _source_io_deq_bits_cmd_xs1; + expected_12_xs2 <= _source_io_deq_bits_cmd_xs2; + expected_12_rd <= _source_io_deq_bits_cmd_rd; + expected_12_opcode <= _source_io_deq_bits_cmd_opcode; + expected_12_rs1Data <= _source_io_deq_bits_cmd_rs1Data; + expected_12_rs2Data <= _source_io_deq_bits_cmd_rs2Data; + end + if (_GEN_13 & allocationSlot == 4'hD) begin + expected_13_raw_inst <= _source_io_deq_bits_cmd_raw_inst; + expected_13_pc <= _source_io_deq_bits_cmd_pc; + expected_13_funct <= _source_io_deq_bits_cmd_funct; + expected_13_funct3 <= _source_io_deq_bits_cmd_funct3; + expected_13_rs2 <= _source_io_deq_bits_cmd_rs2; + expected_13_rs1 <= _source_io_deq_bits_cmd_rs1; + expected_13_xd <= _source_io_deq_bits_cmd_xd; + expected_13_xs1 <= _source_io_deq_bits_cmd_xs1; + expected_13_xs2 <= _source_io_deq_bits_cmd_xs2; + expected_13_rd <= _source_io_deq_bits_cmd_rd; + expected_13_opcode <= _source_io_deq_bits_cmd_opcode; + expected_13_rs1Data <= _source_io_deq_bits_cmd_rs1Data; + expected_13_rs2Data <= _source_io_deq_bits_cmd_rs2Data; + end + if (_GEN_13 & allocationSlot == 4'hE) begin + expected_14_raw_inst <= _source_io_deq_bits_cmd_raw_inst; + expected_14_pc <= _source_io_deq_bits_cmd_pc; + expected_14_funct <= _source_io_deq_bits_cmd_funct; + expected_14_funct3 <= _source_io_deq_bits_cmd_funct3; + expected_14_rs2 <= _source_io_deq_bits_cmd_rs2; + expected_14_rs1 <= _source_io_deq_bits_cmd_rs1; + expected_14_xd <= _source_io_deq_bits_cmd_xd; + expected_14_xs1 <= _source_io_deq_bits_cmd_xs1; + expected_14_xs2 <= _source_io_deq_bits_cmd_xs2; + expected_14_rd <= _source_io_deq_bits_cmd_rd; + expected_14_opcode <= _source_io_deq_bits_cmd_opcode; + expected_14_rs1Data <= _source_io_deq_bits_cmd_rs1Data; + expected_14_rs2Data <= _source_io_deq_bits_cmd_rs2Data; + end + if (_GEN_13 & (&allocationSlot)) begin + expected_15_raw_inst <= _source_io_deq_bits_cmd_raw_inst; + expected_15_pc <= _source_io_deq_bits_cmd_pc; + expected_15_funct <= _source_io_deq_bits_cmd_funct; + expected_15_funct3 <= _source_io_deq_bits_cmd_funct3; + expected_15_rs2 <= _source_io_deq_bits_cmd_rs2; + expected_15_rs1 <= _source_io_deq_bits_cmd_rs1; + expected_15_xd <= _source_io_deq_bits_cmd_xd; + expected_15_xs1 <= _source_io_deq_bits_cmd_xs1; + expected_15_xs2 <= _source_io_deq_bits_cmd_xs2; + expected_15_rd <= _source_io_deq_bits_cmd_rd; + expected_15_opcode <= _source_io_deq_bits_cmd_opcode; + expected_15_rs1Data <= _source_io_deq_bits_cmd_rs1Data; + expected_15_rs2Data <= _source_io_deq_bits_cmd_rs2Data; + end + end // always @(posedge) + GlobalROB dut ( + .clock (clock), + .reset (reset), + .io_alloc_ready (_dut_io_alloc_ready), + .io_alloc_valid (_source_io_deq_valid), + .io_alloc_bits_domain_id (_source_io_deq_bits_domain_id), + .io_alloc_bits_ball_bid (_source_io_deq_bits_ball_bid), + .io_alloc_bits_cmd_raw_inst (_source_io_deq_bits_cmd_raw_inst), + .io_alloc_bits_cmd_pc (_source_io_deq_bits_cmd_pc), + .io_alloc_bits_cmd_funct (_source_io_deq_bits_cmd_funct), + .io_alloc_bits_cmd_funct3 (_source_io_deq_bits_cmd_funct3), + .io_alloc_bits_cmd_rs2 (_source_io_deq_bits_cmd_rs2), + .io_alloc_bits_cmd_rs1 (_source_io_deq_bits_cmd_rs1), + .io_alloc_bits_cmd_xd (_source_io_deq_bits_cmd_xd), + .io_alloc_bits_cmd_xs1 (_source_io_deq_bits_cmd_xs1), + .io_alloc_bits_cmd_xs2 (_source_io_deq_bits_cmd_xs2), + .io_alloc_bits_cmd_rd (_source_io_deq_bits_cmd_rd), + .io_alloc_bits_cmd_opcode (_source_io_deq_bits_cmd_opcode), + .io_alloc_bits_cmd_rs1Data (_source_io_deq_bits_cmd_rs1Data), + .io_alloc_bits_cmd_rs2Data (_source_io_deq_bits_cmd_rs2Data), + .io_alloc_bits_bankAccess_rd_bank_0_valid + (_source_io_deq_bits_bankAccess_rd_bank_0_valid), + .io_alloc_bits_bankAccess_rd_bank_0_id + (_source_io_deq_bits_bankAccess_rd_bank_0_id), + .io_alloc_bits_bankAccess_rd_bank_1_valid + (_source_io_deq_bits_bankAccess_rd_bank_1_valid), + .io_alloc_bits_bankAccess_rd_bank_1_id + (_source_io_deq_bits_bankAccess_rd_bank_1_id), + .io_alloc_bits_bankAccess_wr_bank_valid + (_source_io_deq_bits_bankAccess_wr_bank_valid), + .io_alloc_bits_bankAccess_wr_bank_id + (_source_io_deq_bits_bankAccess_wr_bank_id), + .io_alloc_bits_isFence (_source_io_deq_bits_isFence), + .io_alloc_bits_isBarrier (_source_io_deq_bits_isBarrier), + .io_issue_ready (ready), + .io_issue_valid (_dut_io_issue_valid), + .io_issue_bits_cmd_domain_id (_dut_io_issue_bits_cmd_domain_id), + .io_issue_bits_cmd_ball_bid (_dut_io_issue_bits_cmd_ball_bid), + .io_issue_bits_cmd_cmd_raw_inst + (_dut_io_issue_bits_cmd_cmd_raw_inst), + .io_issue_bits_cmd_cmd_pc (_dut_io_issue_bits_cmd_cmd_pc), + .io_issue_bits_cmd_cmd_funct (_dut_io_issue_bits_cmd_cmd_funct), + .io_issue_bits_cmd_cmd_funct3 (_dut_io_issue_bits_cmd_cmd_funct3), + .io_issue_bits_cmd_cmd_rs2 (_dut_io_issue_bits_cmd_cmd_rs2), + .io_issue_bits_cmd_cmd_rs1 (_dut_io_issue_bits_cmd_cmd_rs1), + .io_issue_bits_cmd_cmd_xd (_dut_io_issue_bits_cmd_cmd_xd), + .io_issue_bits_cmd_cmd_xs1 (_dut_io_issue_bits_cmd_cmd_xs1), + .io_issue_bits_cmd_cmd_xs2 (_dut_io_issue_bits_cmd_cmd_xs2), + .io_issue_bits_cmd_cmd_rd (_dut_io_issue_bits_cmd_cmd_rd), + .io_issue_bits_cmd_cmd_opcode (_dut_io_issue_bits_cmd_cmd_opcode), + .io_issue_bits_cmd_cmd_rs1Data (_dut_io_issue_bits_cmd_cmd_rs1Data), + .io_issue_bits_cmd_cmd_rs2Data (_dut_io_issue_bits_cmd_cmd_rs2Data), + .io_issue_bits_cmd_bankAccess_rd_bank_0_valid + (_dut_io_issue_bits_cmd_bankAccess_rd_bank_0_valid), + .io_issue_bits_cmd_bankAccess_rd_bank_0_id + (_dut_io_issue_bits_cmd_bankAccess_rd_bank_0_id), + .io_issue_bits_cmd_bankAccess_rd_bank_1_valid + (_dut_io_issue_bits_cmd_bankAccess_rd_bank_1_valid), + .io_issue_bits_cmd_bankAccess_rd_bank_1_id + (_dut_io_issue_bits_cmd_bankAccess_rd_bank_1_id), + .io_issue_bits_cmd_bankAccess_wr_bank_valid + (_dut_io_issue_bits_cmd_bankAccess_wr_bank_valid), + .io_issue_bits_cmd_bankAccess_wr_bank_id + (_dut_io_issue_bits_cmd_bankAccess_wr_bank_id), + .io_issue_bits_cmd_op1_col (_dut_io_issue_bits_cmd_op1_col), + .io_issue_bits_cmd_op2_col (_dut_io_issue_bits_cmd_op2_col), + .io_issue_bits_cmd_wr_col (_dut_io_issue_bits_cmd_wr_col), + .io_issue_bits_cmd_isFence (_dut_io_issue_bits_cmd_isFence), + .io_issue_bits_cmd_isBarrier (_dut_io_issue_bits_cmd_isBarrier), + .io_issue_bits_renamedBankAccess_rd_bank_0_valid + (_dut_io_issue_bits_renamedBankAccess_rd_bank_0_valid), + .io_issue_bits_renamedBankAccess_rd_bank_0_id + (_dut_io_issue_bits_renamedBankAccess_rd_bank_0_id), + .io_issue_bits_renamedBankAccess_rd_bank_1_valid + (_dut_io_issue_bits_renamedBankAccess_rd_bank_1_valid), + .io_issue_bits_renamedBankAccess_rd_bank_1_id + (_dut_io_issue_bits_renamedBankAccess_rd_bank_1_id), + .io_issue_bits_renamedBankAccess_wr_bank_valid + (_dut_io_issue_bits_renamedBankAccess_wr_bank_valid), + .io_issue_bits_renamedBankAccess_wr_bank_id + (_dut_io_issue_bits_renamedBankAccess_wr_bank_id), + .io_issue_bits_rob_id (_dut_io_issue_bits_rob_id), + .io_complete_valid (_dut_io_complete_valid_T_1), + .io_complete_bits (_completions_io_deq_bits), + .io_empty (_dut_io_empty), + .io_full (_dut_io_full), + .io_head_ptr (_dut_io_head_ptr), + .io_issued_count (_dut_io_issued_count), + .io_entry_valid_0 (_dut_io_entry_valid_0), + .io_entry_valid_1 (_dut_io_entry_valid_1), + .io_entry_valid_2 (_dut_io_entry_valid_2), + .io_entry_valid_3 (_dut_io_entry_valid_3), + .io_entry_valid_4 (_dut_io_entry_valid_4), + .io_entry_valid_5 (_dut_io_entry_valid_5), + .io_entry_valid_6 (_dut_io_entry_valid_6), + .io_entry_valid_7 (_dut_io_entry_valid_7), + .io_entry_valid_8 (_dut_io_entry_valid_8), + .io_entry_valid_9 (_dut_io_entry_valid_9), + .io_entry_valid_10 (_dut_io_entry_valid_10), + .io_entry_valid_11 (_dut_io_entry_valid_11), + .io_entry_valid_12 (_dut_io_entry_valid_12), + .io_entry_valid_13 (_dut_io_entry_valid_13), + .io_entry_valid_14 (_dut_io_entry_valid_14), + .io_entry_valid_15 (_dut_io_entry_valid_15), + .io_entry_complete_0 (_dut_io_entry_complete_0), + .io_entry_complete_1 (_dut_io_entry_complete_1), + .io_entry_complete_2 (_dut_io_entry_complete_2), + .io_entry_complete_3 (_dut_io_entry_complete_3), + .io_entry_complete_4 (_dut_io_entry_complete_4), + .io_entry_complete_5 (_dut_io_entry_complete_5), + .io_entry_complete_6 (_dut_io_entry_complete_6), + .io_entry_complete_7 (_dut_io_entry_complete_7), + .io_entry_complete_8 (_dut_io_entry_complete_8), + .io_entry_complete_9 (_dut_io_entry_complete_9), + .io_entry_complete_10 (_dut_io_entry_complete_10), + .io_entry_complete_11 (_dut_io_entry_complete_11), + .io_entry_complete_12 (_dut_io_entry_complete_12), + .io_entry_complete_13 (_dut_io_entry_complete_13), + .io_entry_complete_14 (_dut_io_entry_complete_14), + .io_entry_complete_15 (_dut_io_entry_complete_15), + .io_subRobActive (active), + .io_inst_ids_0 (_dut_io_inst_ids_0), + .io_inst_ids_1 (_dut_io_inst_ids_1), + .io_inst_ids_2 (_dut_io_inst_ids_2), + .io_inst_ids_3 (_dut_io_inst_ids_3), + .io_inst_ids_4 (_dut_io_inst_ids_4), + .io_inst_ids_5 (_dut_io_inst_ids_5), + .io_inst_ids_6 (_dut_io_inst_ids_6), + .io_inst_ids_7 (_dut_io_inst_ids_7), + .io_inst_ids_8 (_dut_io_inst_ids_8), + .io_inst_ids_9 (_dut_io_inst_ids_9), + .io_inst_ids_10 (_dut_io_inst_ids_10), + .io_inst_ids_11 (_dut_io_inst_ids_11), + .io_inst_ids_12 (_dut_io_inst_ids_12), + .io_inst_ids_13 (_dut_io_inst_ids_13), + .io_inst_ids_14 (_dut_io_inst_ids_14), + .io_inst_ids_15 (_dut_io_inst_ids_15) + ); + GlobalROB_1 reference ( + .clock (clock), + .reset (reset), + .io_alloc_ready (_reference_io_alloc_ready), + .io_alloc_valid (_source_io_deq_valid), + .io_alloc_bits_domain_id (_source_io_deq_bits_domain_id), + .io_alloc_bits_ball_bid (_source_io_deq_bits_ball_bid), + .io_alloc_bits_cmd_raw_inst (_source_io_deq_bits_cmd_raw_inst), + .io_alloc_bits_cmd_pc (_source_io_deq_bits_cmd_pc), + .io_alloc_bits_cmd_funct (_source_io_deq_bits_cmd_funct), + .io_alloc_bits_cmd_funct3 (_source_io_deq_bits_cmd_funct3), + .io_alloc_bits_cmd_rs2 (_source_io_deq_bits_cmd_rs2), + .io_alloc_bits_cmd_rs1 (_source_io_deq_bits_cmd_rs1), + .io_alloc_bits_cmd_xd (_source_io_deq_bits_cmd_xd), + .io_alloc_bits_cmd_xs1 (_source_io_deq_bits_cmd_xs1), + .io_alloc_bits_cmd_xs2 (_source_io_deq_bits_cmd_xs2), + .io_alloc_bits_cmd_rd (_source_io_deq_bits_cmd_rd), + .io_alloc_bits_cmd_opcode (_source_io_deq_bits_cmd_opcode), + .io_alloc_bits_cmd_rs1Data (_source_io_deq_bits_cmd_rs1Data), + .io_alloc_bits_cmd_rs2Data (_source_io_deq_bits_cmd_rs2Data), + .io_alloc_bits_bankAccess_rd_bank_0_valid + (_source_io_deq_bits_bankAccess_rd_bank_0_valid), + .io_alloc_bits_bankAccess_rd_bank_0_id + (_source_io_deq_bits_bankAccess_rd_bank_0_id), + .io_alloc_bits_bankAccess_rd_bank_1_valid + (_source_io_deq_bits_bankAccess_rd_bank_1_valid), + .io_alloc_bits_bankAccess_rd_bank_1_id + (_source_io_deq_bits_bankAccess_rd_bank_1_id), + .io_alloc_bits_bankAccess_wr_bank_valid + (_source_io_deq_bits_bankAccess_wr_bank_valid), + .io_alloc_bits_bankAccess_wr_bank_id + (_source_io_deq_bits_bankAccess_wr_bank_id), + .io_alloc_bits_isFence (_source_io_deq_bits_isFence), + .io_alloc_bits_isBarrier (_source_io_deq_bits_isBarrier), + .io_issue_ready (ready), + .io_issue_valid (_reference_io_issue_valid), + .io_issue_bits_cmd_domain_id + (_reference_io_issue_bits_cmd_domain_id), + .io_issue_bits_cmd_ball_bid + (_reference_io_issue_bits_cmd_ball_bid), + .io_issue_bits_cmd_cmd_raw_inst + (_reference_io_issue_bits_cmd_cmd_raw_inst), + .io_issue_bits_cmd_cmd_pc + (_reference_io_issue_bits_cmd_cmd_pc), + .io_issue_bits_cmd_cmd_funct + (_reference_io_issue_bits_cmd_cmd_funct), + .io_issue_bits_cmd_cmd_funct3 + (_reference_io_issue_bits_cmd_cmd_funct3), + .io_issue_bits_cmd_cmd_rs2 + (_reference_io_issue_bits_cmd_cmd_rs2), + .io_issue_bits_cmd_cmd_rs1 + (_reference_io_issue_bits_cmd_cmd_rs1), + .io_issue_bits_cmd_cmd_xd + (_reference_io_issue_bits_cmd_cmd_xd), + .io_issue_bits_cmd_cmd_xs1 + (_reference_io_issue_bits_cmd_cmd_xs1), + .io_issue_bits_cmd_cmd_xs2 + (_reference_io_issue_bits_cmd_cmd_xs2), + .io_issue_bits_cmd_cmd_rd + (_reference_io_issue_bits_cmd_cmd_rd), + .io_issue_bits_cmd_cmd_opcode + (_reference_io_issue_bits_cmd_cmd_opcode), + .io_issue_bits_cmd_cmd_rs1Data + (_reference_io_issue_bits_cmd_cmd_rs1Data), + .io_issue_bits_cmd_cmd_rs2Data + (_reference_io_issue_bits_cmd_cmd_rs2Data), + .io_issue_bits_cmd_bankAccess_rd_bank_0_valid + (_reference_io_issue_bits_cmd_bankAccess_rd_bank_0_valid), + .io_issue_bits_cmd_bankAccess_rd_bank_0_id + (_reference_io_issue_bits_cmd_bankAccess_rd_bank_0_id), + .io_issue_bits_cmd_bankAccess_rd_bank_1_valid + (_reference_io_issue_bits_cmd_bankAccess_rd_bank_1_valid), + .io_issue_bits_cmd_bankAccess_rd_bank_1_id + (_reference_io_issue_bits_cmd_bankAccess_rd_bank_1_id), + .io_issue_bits_cmd_bankAccess_wr_bank_valid + (_reference_io_issue_bits_cmd_bankAccess_wr_bank_valid), + .io_issue_bits_cmd_bankAccess_wr_bank_id + (_reference_io_issue_bits_cmd_bankAccess_wr_bank_id), + .io_issue_bits_cmd_op1_col + (_reference_io_issue_bits_cmd_op1_col), + .io_issue_bits_cmd_op2_col + (_reference_io_issue_bits_cmd_op2_col), + .io_issue_bits_cmd_wr_col + (_reference_io_issue_bits_cmd_wr_col), + .io_issue_bits_cmd_isFence + (_reference_io_issue_bits_cmd_isFence), + .io_issue_bits_cmd_isBarrier + (_reference_io_issue_bits_cmd_isBarrier), + .io_issue_bits_renamedBankAccess_rd_bank_0_valid + (_reference_io_issue_bits_renamedBankAccess_rd_bank_0_valid), + .io_issue_bits_renamedBankAccess_rd_bank_0_id + (_reference_io_issue_bits_renamedBankAccess_rd_bank_0_id), + .io_issue_bits_renamedBankAccess_rd_bank_1_valid + (_reference_io_issue_bits_renamedBankAccess_rd_bank_1_valid), + .io_issue_bits_renamedBankAccess_rd_bank_1_id + (_reference_io_issue_bits_renamedBankAccess_rd_bank_1_id), + .io_issue_bits_renamedBankAccess_wr_bank_valid + (_reference_io_issue_bits_renamedBankAccess_wr_bank_valid), + .io_issue_bits_renamedBankAccess_wr_bank_id + (_reference_io_issue_bits_renamedBankAccess_wr_bank_id), + .io_issue_bits_rob_id (_reference_io_issue_bits_rob_id), + .io_complete_valid (_dut_io_complete_valid_T_1), + .io_complete_bits (_completions_io_deq_bits), + .io_empty (_reference_io_empty), + .io_full (_reference_io_full), + .io_head_ptr (_reference_io_head_ptr), + .io_issued_count (_reference_io_issued_count), + .io_entry_valid_0 (_reference_io_entry_valid_0), + .io_entry_valid_1 (_reference_io_entry_valid_1), + .io_entry_valid_2 (_reference_io_entry_valid_2), + .io_entry_valid_3 (_reference_io_entry_valid_3), + .io_entry_valid_4 (_reference_io_entry_valid_4), + .io_entry_valid_5 (_reference_io_entry_valid_5), + .io_entry_valid_6 (_reference_io_entry_valid_6), + .io_entry_valid_7 (_reference_io_entry_valid_7), + .io_entry_valid_8 (_reference_io_entry_valid_8), + .io_entry_valid_9 (_reference_io_entry_valid_9), + .io_entry_valid_10 (_reference_io_entry_valid_10), + .io_entry_valid_11 (_reference_io_entry_valid_11), + .io_entry_valid_12 (_reference_io_entry_valid_12), + .io_entry_valid_13 (_reference_io_entry_valid_13), + .io_entry_valid_14 (_reference_io_entry_valid_14), + .io_entry_valid_15 (_reference_io_entry_valid_15), + .io_entry_complete_0 (_reference_io_entry_complete_0), + .io_entry_complete_1 (_reference_io_entry_complete_1), + .io_entry_complete_2 (_reference_io_entry_complete_2), + .io_entry_complete_3 (_reference_io_entry_complete_3), + .io_entry_complete_4 (_reference_io_entry_complete_4), + .io_entry_complete_5 (_reference_io_entry_complete_5), + .io_entry_complete_6 (_reference_io_entry_complete_6), + .io_entry_complete_7 (_reference_io_entry_complete_7), + .io_entry_complete_8 (_reference_io_entry_complete_8), + .io_entry_complete_9 (_reference_io_entry_complete_9), + .io_entry_complete_10 (_reference_io_entry_complete_10), + .io_entry_complete_11 (_reference_io_entry_complete_11), + .io_entry_complete_12 (_reference_io_entry_complete_12), + .io_entry_complete_13 (_reference_io_entry_complete_13), + .io_entry_complete_14 (_reference_io_entry_complete_14), + .io_entry_complete_15 (_reference_io_entry_complete_15), + .io_subRobActive (active), + .io_inst_ids_0 (_reference_io_inst_ids_0), + .io_inst_ids_1 (_reference_io_inst_ids_1), + .io_inst_ids_2 (_reference_io_inst_ids_2), + .io_inst_ids_3 (_reference_io_inst_ids_3), + .io_inst_ids_4 (_reference_io_inst_ids_4), + .io_inst_ids_5 (_reference_io_inst_ids_5), + .io_inst_ids_6 (_reference_io_inst_ids_6), + .io_inst_ids_7 (_reference_io_inst_ids_7), + .io_inst_ids_8 (_reference_io_inst_ids_8), + .io_inst_ids_9 (_reference_io_inst_ids_9), + .io_inst_ids_10 (_reference_io_inst_ids_10), + .io_inst_ids_11 (_reference_io_inst_ids_11), + .io_inst_ids_12 (_reference_io_inst_ids_12), + .io_inst_ids_13 (_reference_io_inst_ids_13), + .io_inst_ids_14 (_reference_io_inst_ids_14), + .io_inst_ids_15 (_reference_io_inst_ids_15) + ); + Queue2_PostGDCmd source ( + .clock (clock), + .reset (reset), + .io_enq_valid (cycle < 16'h1388 & random[0]), + .io_enq_bits_domain_id + ({2'h0, ~(~(|(random[5:2])) | random[2]), 1'h1}), + .io_enq_bits_cmd_raw_inst (random), + .io_enq_bits_cmd_pc ({random, ~random}), + .io_enq_bits_cmd_funct + ((|(random[5:2])) ? (random[3] ? 7'h35 : 7'h42) : 7'h20), + .io_enq_bits_cmd_rs1Data + ({random, random[31], random[30:0] ^ 31'h597BDF03}), + .io_enq_bits_cmd_rs2Data + ((|(random[5:2])) + ? {~random, random[31:30], random[29:0] ^ 30'h26AC048E} + : {random, 25'h8, random[1:0], 5'h0}), + .io_enq_bits_bankAccess_rd_bank_0_valid ((|(random[5:2])) & random[8]), + .io_enq_bits_bankAccess_rd_bank_0_id ({6'h0, random[14:11]}), + .io_enq_bits_bankAccess_rd_bank_1_valid ((|(random[5:2])) & random[9]), + .io_enq_bits_bankAccess_rd_bank_1_id ({6'h0, random[18:15]}), + .io_enq_bits_bankAccess_wr_bank_valid (~(|(random[5:2])) | random[10]), + .io_enq_bits_bankAccess_wr_bank_id ({6'h0, random[22:19]}), + .io_deq_ready (_dut_io_alloc_ready), + .io_deq_valid (_source_io_deq_valid), + .io_deq_bits_domain_id (_source_io_deq_bits_domain_id), + .io_deq_bits_ball_bid (_source_io_deq_bits_ball_bid), + .io_deq_bits_cmd_raw_inst (_source_io_deq_bits_cmd_raw_inst), + .io_deq_bits_cmd_pc (_source_io_deq_bits_cmd_pc), + .io_deq_bits_cmd_funct (_source_io_deq_bits_cmd_funct), + .io_deq_bits_cmd_funct3 (_source_io_deq_bits_cmd_funct3), + .io_deq_bits_cmd_rs2 (_source_io_deq_bits_cmd_rs2), + .io_deq_bits_cmd_rs1 (_source_io_deq_bits_cmd_rs1), + .io_deq_bits_cmd_xd (_source_io_deq_bits_cmd_xd), + .io_deq_bits_cmd_xs1 (_source_io_deq_bits_cmd_xs1), + .io_deq_bits_cmd_xs2 (_source_io_deq_bits_cmd_xs2), + .io_deq_bits_cmd_rd (_source_io_deq_bits_cmd_rd), + .io_deq_bits_cmd_opcode (_source_io_deq_bits_cmd_opcode), + .io_deq_bits_cmd_rs1Data (_source_io_deq_bits_cmd_rs1Data), + .io_deq_bits_cmd_rs2Data (_source_io_deq_bits_cmd_rs2Data), + .io_deq_bits_bankAccess_rd_bank_0_valid + (_source_io_deq_bits_bankAccess_rd_bank_0_valid), + .io_deq_bits_bankAccess_rd_bank_0_id (_source_io_deq_bits_bankAccess_rd_bank_0_id), + .io_deq_bits_bankAccess_rd_bank_1_valid + (_source_io_deq_bits_bankAccess_rd_bank_1_valid), + .io_deq_bits_bankAccess_rd_bank_1_id (_source_io_deq_bits_bankAccess_rd_bank_1_id), + .io_deq_bits_bankAccess_wr_bank_valid + (_source_io_deq_bits_bankAccess_wr_bank_valid), + .io_deq_bits_bankAccess_wr_bank_id (_source_io_deq_bits_bankAccess_wr_bank_id), + .io_deq_bits_isFence (_source_io_deq_bits_isFence), + .io_deq_bits_isBarrier (_source_io_deq_bits_isBarrier) + ); + Queue16_UInt4 completions ( + .clock (clock), + .reset (reset), + .io_enq_ready (_completions_io_enq_ready), + .io_enq_valid (_completions_io_enq_valid_T), + .io_enq_bits (_dut_io_issue_bits_rob_id), + .io_deq_ready (random[4]), + .io_deq_valid (_completions_io_deq_valid), + .io_deq_bits (_completions_io_deq_bits) + ); + assign passed = _passed_output; +endmodule + + +// ----- 8< ----- FILE "./ITraceDPI.v" ----- 8< ----- + + +module ITraceDPI( + input clock, + input reset, + input [7:0] is_issue, + input [63:0] hart_id, + input [31:0] rob_id, + input [63:0] inst_id, + input [31:0] domain_id, + input [31:0] funct, + input [63:0] pc, + input [63:0] rs1_data, + input [63:0] rs2_data, + input enable +); +`ifndef BUCKYBALL_DISABLE_DPI +`ifndef BUCKYBALL_DISABLE_TRACE_DPI +`ifndef BUCKYBALL_DISABLE_ITRACE_DPI + + import "DPI-C" context function void dpi_itrace( + input int unsigned is_issue, + input int unsigned hart_id_lo, + input int unsigned hart_id_hi, + input int unsigned rob_id, + input int unsigned inst_id_lo, + input int unsigned inst_id_hi, + input int unsigned domain_id, + input int unsigned funct, + input int unsigned pc_lo, + input int unsigned pc_hi, + input int unsigned rs1_data_lo, + input int unsigned rs1_data_hi, + input int unsigned rs2_data_lo, + input int unsigned rs2_data_hi + ); + reg [7:0] is_issue_reg; + reg [63:0] hart_id_reg; + reg [31:0] rob_id_reg; + reg [63:0] inst_id_reg; + reg [31:0] domain_id_reg; + reg [31:0] funct_reg; + reg [63:0] pc_reg; + reg [63:0] rs1_data_reg; + reg [63:0] rs2_data_reg; + reg valid_reg; + + always @(posedge clock) begin + if (reset) begin + valid_reg <= 1'b0; + end else begin + if (valid_reg) begin + dpi_itrace(is_issue_reg, hart_id_reg[31:0], hart_id_reg[63:32], rob_id_reg, inst_id_reg[31:0], inst_id_reg[63:32], domain_id_reg, funct_reg, pc_reg[31:0], pc_reg[63:32], rs1_data_reg[31:0], rs1_data_reg[63:32], rs2_data_reg[31:0], rs2_data_reg[63:32]); + end + + valid_reg <= enable; + if (enable) begin + is_issue_reg <= is_issue; + hart_id_reg <= hart_id; + rob_id_reg <= rob_id; + inst_id_reg <= inst_id; + domain_id_reg <= domain_id; + funct_reg <= funct; + pc_reg <= pc; + rs1_data_reg <= rs1_data; + rs2_data_reg <= rs2_data; + end + end + end +`endif +`endif +`endif + +endmodule + + +// ----- 8< ----- FILE "firrtl_black_box_resource_files.f" ----- 8< ----- + +ITraceDPI.v diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/globalrob-check/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/globalrob-check/RESULT.json new file mode 100644 index 0000000..b5daff2 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/globalrob-check/RESULT.json @@ -0,0 +1,15 @@ +{ + "result": "PASS", + "cycle_equivalence": true, + "coverage": [ + "accepted operand integrity", + "ROB full", + "pointer wrap", + "issue backpressure", + "SubROB ownership stall", + "mid-flight resets", + "concurrent allocation/issue/completion", + "complete drain" + ], + "rtl_sha256": "e44723e3396d7e6421b9fae96a5d7b0b12ad0b4d55cc15128f21d7e048296fd0" +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/globalrob-check/compile.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/globalrob-check/compile.log new file mode 100644 index 0000000..b51b2dd --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/globalrob-check/compile.log @@ -0,0 +1,93 @@ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/globalrob-check/GlobalRobCheck.sim.sv:22:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 22 | module BankAliasTable( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/tb_globalrob.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ + ... For warning description see https://verilator.org/warn/TIMESCALEMOD?v=5.050 + ... Use "/* verilator lint_off TIMESCALEMOD */" and lint_on around source to disable this message. +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/globalrob-check/GlobalRobCheck.sim.sv:1346:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 1346 | module BankScoreboard( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/tb_globalrob.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/globalrob-check/GlobalRobCheck.sim.sv:1722:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 1722 | module robOperands_16x128( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/tb_globalrob.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/globalrob-check/GlobalRobCheck.sim.sv:1747:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 1747 | module GlobalROB( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/tb_globalrob.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/globalrob-check/GlobalRobCheck.sim.sv:6809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6809 | module GlobalROB_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/tb_globalrob.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/globalrob-check/GlobalRobCheck.sim.sv:11849:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +11849 | module ram_2x303( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/tb_globalrob.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/globalrob-check/GlobalRobCheck.sim.sv:11868:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +11868 | module Queue2_PostGDCmd( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/tb_globalrob.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/globalrob-check/GlobalRobCheck.sim.sv:11988:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +11988 | module ram_16x4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/tb_globalrob.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/globalrob-check/GlobalRobCheck.sim.sv:12007:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12007 | module Queue16_UInt4( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/tb_globalrob.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/globalrob-check/GlobalRobCheck.sim.sv:12055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12055 | module GlobalRobCheck( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/tb_globalrob.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/globalrob-check/GlobalRobCheck.sim.sv:13609:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13609 | module ITraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/tb_globalrob.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +make: Entering directory '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/globalrob-check/obj' +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_timing.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_timing.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_threads.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_threads.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb__pch.h -o Vtb__pch.h.fast.gch +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb__pch.h -o Vtb__pch.h.slow.gch +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__0.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__1.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__2.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb_BankAliasTable__0.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb_BankAliasTable__1.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb__main.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__1__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb_BankAliasTable__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb_BankAliasTable__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb__Syms__Slow.cpp +g++ verilated.o verilated_timing.o verilated_threads.o Vtb__ALL.a -pthread -lpthread -latomic -o Vtb +rm Vtb__ALL.verilator_deplist.tmp +make: Leaving directory '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/globalrob-check/obj' +- V e r i l a t i o n R e p o r t: Verilator 5.050 2026-07-01 rev v5.050 +- Verilator: Built from 1.311 MB sources in 13 modules, into 4.922 MB in 13 C++ files needing 0.004 MB +- Verilator: Walltime 10.706 s (elab=0.052, cvt=0.438, bld=10.114); cpu 0.659 s on 4 threads; allocated 453.211 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/globalrob-check/elaboration.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/globalrob-check/elaboration.log new file mode 100644 index 0000000..baa98c5 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/globalrob-check/elaboration.log @@ -0,0 +1,593 @@ +[info] welcome to sbt 1.12.11 (N/A Java 17.0.20) +[info] loading project definition from /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/project +[info] loading settings for project root from build.sbt... +[info] set current project to toy-arty-a7-linux (in build file:/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/) +[info] compiling 1 Scala source to /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/cde/target/scala-2.13/classes ... +[info] compiling 1 Scala source to /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/rocket-chip/macros/target/scala-2.13/classes ... +[info] compiling 7 Scala sources to /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/firesim-compile/target/scala-2.13/classes ... +[info] done compiling +[info] done compiling +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/firesim/sim/midas/targetutils/src/main/scala/midas/InstrumentationPredication.scala:7:8: Importing from firrtl is deprecated as of Chisel's 3.6.0 release. +[warn] import firrtl.annotations.{ReferenceTarget, SingleTargetAnnotation} +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/firesim/sim/midas/targetutils/src/main/scala/midas/annotations.scala:24:8: Importing from firrtl is deprecated as of Chisel's 3.6.0 release. +[warn] import firrtl.RenameMap +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/firesim/sim/midas/targetutils/src/main/scala/midas/annotations.scala:25:8: Importing from firrtl is deprecated as of Chisel's 3.6.0 release. +[warn] import firrtl.annotations.{ +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/firesim/sim/midas/targetutils/src/main/scala/midas/xdc/RAMStyleHint.scala:6:8: Importing from firrtl is deprecated as of Chisel's 3.6.0 release. +[warn] import firrtl.annotations.ReferenceTarget +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/firesim/sim/midas/targetutils/src/main/scala/midas/xdc/XDCAnnotation.scala:7:8: Importing from firrtl is deprecated as of Chisel's 3.6.0 release. +[warn] import firrtl.RenameMap +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/firesim/sim/midas/targetutils/src/main/scala/midas/xdc/XDCAnnotation.scala:8:8: Importing from firrtl is deprecated as of Chisel's 3.6.0 release. +[warn] import firrtl.annotations.{Annotation, HasSerializationHints, NoTargetAnnotation, ReferenceTarget} +[warn] ^ +[info] compiling 36 Scala sources to /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/diplomacy/diplomacy/target/scala-2.13/classes ... +[info] compiling 20 Scala sources to /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/hardfloat/hardfloat/target/scala-2.13/classes ... +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/firesim/sim/midas/targetutils/src/main/scala/midas/InstrumentationPredication.scala:51:5: method apply in object annotate is deprecated (since Chisel 6.7.0): Avoid custom annotations. If you must use annotations, use annotate.apply method that takes Data +[warn] annotate(new ChiselAnnotation { def toFirrtl = GlobalResetCondition(condition.toTarget) }) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/firesim/sim/midas/targetutils/src/main/scala/midas/InstrumentationPredication.scala:51:18: trait ChiselAnnotation in package experimental is deprecated (since Chisel 6.7.0): Avoid custom annotations. If you must use annotations, use annotate.apply method that takes Data +[warn] annotate(new ChiselAnnotation { def toFirrtl = GlobalResetCondition(condition.toTarget) }) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/firesim/sim/midas/targetutils/src/main/scala/midas/InstrumentationPredication.scala:59:42: method apply in object annotate is deprecated (since Chisel 6.7.0): Avoid custom annotations. If you must use annotations, use annotate.apply method that takes Data +[warn] def sink(target: chisel3.Bool): Unit = annotate(new ChiselAnnotation { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/firesim/sim/midas/targetutils/src/main/scala/midas/InstrumentationPredication.scala:59:55: trait ChiselAnnotation in package experimental is deprecated (since Chisel 6.7.0): Avoid custom annotations. If you must use annotations, use annotate.apply method that takes Data +[warn] def sink(target: chisel3.Bool): Unit = annotate(new ChiselAnnotation { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/firesim/sim/midas/targetutils/src/main/scala/midas/annotations.scala:38:54: trait ChiselAnnotation in package experimental is deprecated (since Chisel 6.7.0): Avoid custom annotations. If you must use annotations, use annotate.apply method that takes Data +[warn] case class FpgaDebugAnnotation(target: Data) extends ChiselAnnotation { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/firesim/sim/midas/targetutils/src/main/scala/midas/annotations.scala:49:24: method apply in object annotate is deprecated (since Chisel 6.7.0): Avoid custom annotations. If you must use annotations, use annotate.apply method that takes Data +[warn] targets.map({ t => annotate(FpgaDebugAnnotation(t)) }) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/firesim/sim/midas/targetutils/src/main/scala/midas/annotations.scala:90:5: method apply in object annotate is deprecated (since Chisel 6.7.0): Avoid custom annotations. If you must use annotations, use annotate.apply method that takes Data +[warn] annotate(new ChiselAnnotation { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/firesim/sim/midas/targetutils/src/main/scala/midas/annotations.scala:90:18: trait ChiselAnnotation in package experimental is deprecated (since Chisel 6.7.0): Avoid custom annotations. If you must use annotations, use annotate.apply method that takes Data +[warn] annotate(new ChiselAnnotation { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/firesim/sim/midas/targetutils/src/main/scala/midas/annotations.scala:146:60: trait ChiselAnnotation in package experimental is deprecated (since Chisel 6.7.0): Avoid custom annotations. If you must use annotations, use annotate.apply method that takes Data +[warn] case class FAMEModelAnnotation(target: BaseModule) extends ChiselAnnotation { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/firesim/sim/midas/targetutils/src/main/scala/midas/annotations.scala:163:76: trait ChiselAnnotation in package experimental is deprecated (since Chisel 6.7.0): Avoid custom annotations. If you must use annotations, use annotate.apply method that takes Data +[warn] case class EnableModelMultiThreadingAnnotation(target: BaseModule) extends ChiselAnnotation { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/firesim/sim/midas/targetutils/src/main/scala/midas/annotations.scala:182:70: trait ChiselAnnotation in package experimental is deprecated (since Chisel 6.7.0): Avoid custom annotations. If you must use annotations, use annotate.apply method that takes Data +[warn] case class MemModelAnnotation[T <: Data](target: MemBase[T]) extends ChiselAnnotation { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/firesim/sim/midas/targetutils/src/main/scala/midas/annotations.scala:195:40: trait ChiselAnnotation in package experimental is deprecated (since Chisel 6.7.0): Avoid custom annotations. If you must use annotations, use annotate.apply method that takes Data +[warn] def apply(target: (String, String)): ChiselAnnotation = +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/firesim/sim/midas/targetutils/src/main/scala/midas/annotations.scala:196:9: trait ChiselAnnotation in package experimental is deprecated (since Chisel 6.7.0): Avoid custom annotations. If you must use annotations, use annotate.apply method that takes Data +[warn] new ChiselAnnotation { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/firesim/sim/midas/targetutils/src/main/scala/midas/annotations.scala:248:75: trait ChiselAnnotation in package experimental is deprecated (since Chisel 6.7.0): Avoid custom annotations. If you must use annotations, use annotate.apply method that takes Data +[warn] case class AutoCounterCoverModuleAnnotation(target: ModuleTarget) extends ChiselAnnotation { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/firesim/sim/midas/targetutils/src/main/scala/midas/annotations.scala:264:5: method apply in object annotate is deprecated (since Chisel 6.7.0): Avoid custom annotations. If you must use annotations, use annotate.apply method that takes Data +[warn] annotate(new ChiselAnnotation { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/firesim/sim/midas/targetutils/src/main/scala/midas/annotations.scala:264:18: trait ChiselAnnotation in package experimental is deprecated (since Chisel 6.7.0): Avoid custom annotations. If you must use annotations, use annotate.apply method that takes Data +[warn] annotate(new ChiselAnnotation { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/firesim/sim/midas/targetutils/src/main/scala/midas/annotations.scala:337:5: method apply in object annotate is deprecated (since Chisel 6.7.0): Avoid custom annotations. If you must use annotations, use annotate.apply method that takes Data +[warn] annotate(new ChiselAnnotation { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/firesim/sim/midas/targetutils/src/main/scala/midas/annotations.scala:337:18: trait ChiselAnnotation in package experimental is deprecated (since Chisel 6.7.0): Avoid custom annotations. If you must use annotations, use annotate.apply method that takes Data +[warn] annotate(new ChiselAnnotation { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/firesim/sim/midas/targetutils/src/main/scala/midas/annotations.scala:400:5: method apply in object annotate is deprecated (since Chisel 6.7.0): Avoid custom annotations. If you must use annotations, use annotate.apply method that takes Data +[warn] annotate(new ChiselAnnotation { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/firesim/sim/midas/targetutils/src/main/scala/midas/annotations.scala:400:18: trait ChiselAnnotation in package experimental is deprecated (since Chisel 6.7.0): Avoid custom annotations. If you must use annotations, use annotate.apply method that takes Data +[warn] annotate(new ChiselAnnotation { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/firesim/sim/midas/targetutils/src/main/scala/midas/annotations.scala:462:5: method apply in object annotate is deprecated (since Chisel 6.7.0): Avoid custom annotations. If you must use annotations, use annotate.apply method that takes Data +[warn] annotate(new ChiselAnnotation { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/firesim/sim/midas/targetutils/src/main/scala/midas/annotations.scala:462:18: trait ChiselAnnotation in package experimental is deprecated (since Chisel 6.7.0): Avoid custom annotations. If you must use annotations, use annotate.apply method that takes Data +[warn] annotate(new ChiselAnnotation { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/firesim/sim/midas/targetutils/src/main/scala/midas/annotations.scala:510:5: method apply in object annotate is deprecated (since Chisel 6.7.0): Avoid custom annotations. If you must use annotations, use annotate.apply method that takes Data +[warn] annotate(new ChiselAnnotation { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/firesim/sim/midas/targetutils/src/main/scala/midas/annotations.scala:510:18: trait ChiselAnnotation in package experimental is deprecated (since Chisel 6.7.0): Avoid custom annotations. If you must use annotations, use annotate.apply method that takes Data +[warn] annotate(new ChiselAnnotation { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/firesim/sim/midas/targetutils/src/main/scala/midas/xdc/QSFPPortLocHint.scala:23:26: method apply in object annotate is deprecated (since Chisel 6.7.0): Avoid custom annotations. If you must use annotations, use annotate.apply method that takes Data +[warn] chisel3.experimental.annotate(new ChiselAnnotation { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/firesim/sim/midas/targetutils/src/main/scala/midas/xdc/QSFPPortLocHint.scala:23:39: trait ChiselAnnotation in package experimental is deprecated (since Chisel 6.7.0): Avoid custom annotations. If you must use annotations, use annotate.apply method that takes Data +[warn] chisel3.experimental.annotate(new ChiselAnnotation { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/firesim/sim/midas/targetutils/src/main/scala/midas/xdc/RAMStyleHint.scala:51:26: method apply in object annotate is deprecated (since Chisel 6.7.0): Avoid custom annotations. If you must use annotations, use annotate.apply method that takes Data +[warn] chisel3.experimental.annotate(new ChiselAnnotation { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/firesim/sim/midas/targetutils/src/main/scala/midas/xdc/RAMStyleHint.scala:51:39: trait ChiselAnnotation in package experimental is deprecated (since Chisel 6.7.0): Avoid custom annotations. If you must use annotations, use annotate.apply method that takes Data +[warn] chisel3.experimental.annotate(new ChiselAnnotation { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/firesim/sim/midas/targetutils/src/main/scala/midas/xdc/XDCAnnotation.scala:89:26: method apply in object annotate is deprecated (since Chisel 6.7.0): Avoid custom annotations. If you must use annotations, use annotate.apply method that takes Data +[warn] chisel3.experimental.annotate(new ChiselAnnotation { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/firesim/sim/midas/targetutils/src/main/scala/midas/xdc/XDCAnnotation.scala:89:39: trait ChiselAnnotation in package experimental is deprecated (since Chisel 6.7.0): Avoid custom annotations. If you must use annotations, use annotate.apply method that takes Data +[warn] chisel3.experimental.annotate(new ChiselAnnotation { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/firesim/sim/midas/targetutils/src/main/scala/midas/xdc/XDCAnnotation.scala:105:26: method apply in object annotate is deprecated (since Chisel 6.7.0): Avoid custom annotations. If you must use annotations, use annotate.apply method that takes Data +[warn] chisel3.experimental.annotate(new ChiselAnnotation { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/firesim/sim/midas/targetutils/src/main/scala/midas/xdc/XDCAnnotation.scala:105:39: trait ChiselAnnotation in package experimental is deprecated (since Chisel 6.7.0): Avoid custom annotations. If you must use annotations, use annotate.apply method that takes Data +[warn] chisel3.experimental.annotate(new ChiselAnnotation { +[warn] ^ +[warn] 38 warnings found +[info] done compiling +[info] done compiling +[info] done compiling +[info] compiling 324 Scala sources to /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/rocket-chip/target/scala-2.13/classes ... +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/rocket-chip/src/main/scala/diplomacy/Main.scala:6:8: Importing from firrtl is deprecated as of Chisel's 3.6.0 release. +[warn] import firrtl.AnnotationSeq +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/rocket-chip/src/main/scala/diplomacy/Main.scala:7:8: Importing from firrtl is deprecated as of Chisel's 3.6.0 release. +[warn] import firrtl.options.TargetDirAnnotation +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/rocket-chip/src/main/scala/diplomacy/Main.scala:40:14: class MaybeInjectingPhase in package phases is deprecated (since 6.6.0): injecting aspects are being removed in Chisel 7 +[warn] ) { case (annos, phase) => phase.transform(annos) } +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/rocket-chip/src/main/scala/tilelink/Monitor.scala:860:11: method legalizeADSourceOld in class TLMonitor is deprecated: Use legalizeADSource instead if possible +[warn] legalizeADSourceOld(bundle, edge) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/rocket-chip/src/main/scala/util/SynchronizerReg.scala:127:52: class SyncResetSynchronizerShiftReg in package util is deprecated (since rocket-chip 1.2): SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type. +[warn] if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) +[warn] ^ +[warn] 5 warnings found +[info] done compiling +[info] compiling 21 Scala sources to /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/inclusive-cache/target/scala-2.13/classes ... +[info] compiling 56 Scala sources to /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini-compile/target/scala-2.13/classes ... +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/inclusive-cache/design/craft/inclusivecache/src/MSHR.scala:343:83: procedure syntax is deprecated: instead, add `: Unit =` to explicitly declare `eviction`'s return type [quickfixable] +[warn] def eviction(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/inclusive-cache/design/craft/inclusivecache/src/MSHR.scala:356:101: procedure syntax is deprecated: instead, add `: Unit =` to explicitly declare `transition`'s return type [quickfixable] +[warn] def transition(from: CacheState, to: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/inclusive-cache/design/craft/inclusivecache/src/MSHR.scala:513:81: procedure syntax is deprecated: instead, add `: Unit =` to explicitly declare `bypass`'s return type [quickfixable] +[warn] def bypass(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/Arithmetic.scala:54:27: Implicit definition should have explicit type (inferred gemmini.ArithmeticOps[chisel3.UInt]) [quickfixable] +[warn] override implicit def cast(self: UInt) = new ArithmeticOps(self) { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/Arithmetic.scala:91:27: Implicit definition should have explicit type (inferred gemmini.ArithmeticOps[chisel3.SInt]) [quickfixable] +[warn] override implicit def cast(self: SInt) = new ArithmeticOps(self) { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/Arithmetic.scala:531:27: Implicit definition should have explicit type (inferred gemmini.ArithmeticOps[gemmini.DummySInt]) [quickfixable] +[warn] override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/Arithmetic.scala:28:16: implicit conversion method cast should be enabled +[warn] by making the implicit value scala.language.implicitConversions visible. +[warn] This can be achieved by adding the import clause 'import scala.language.implicitConversions' +[warn] or by setting the compiler option -language:implicitConversions. +[warn] See the Scaladoc for value scala.language.implicitConversions for a discussion +[warn] why the feature should be explicitly enabled. +[warn] implicit def cast(t: T): ArithmeticOps[T] +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/Arithmetic.scala:331:27: implicit conversion method cast should be enabled +[warn] by making the implicit value scala.language.implicitConversions visible. +[warn] override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/Controller.scala:173:16: Implicit definition should have explicit type (inferred freechips.rocketchip.tilelink.TLEdgeOut) [quickfixable] +[warn] implicit val edge = outer.spad.id_node.edges.out.head +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/inclusive-cache/design/craft/inclusivecache/src/Configs.scala:54:29: method apply in class View is deprecated (since CDE 0.1): up(XYZ, site) is no longer necessary; remove the superfluous site argument +[warn] case InclusiveCacheKey => up(InclusiveCacheKey, site).copy(schedulerBypass = enable) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/inclusive-cache/design/craft/inclusivecache/src/Configs.scala:58:29: method apply in class View is deprecated (since CDE 0.1): up(XYZ, site) is no longer necessary; remove the superfluous site argument +[warn] case InclusiveCacheKey => up(InclusiveCacheKey, site).copy(dirReg = enable) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/inclusive-cache/design/craft/inclusivecache/src/Configs.scala:73:67: method apply in class View is deprecated (since CDE 0.1): up(XYZ, site) is no longer necessary; remove the superfluous site argument +[warn] sets = (capacityKB * 1024)/(site(CacheBlockBytes) * nWays * up(SubsystemBankedCoherenceKey, site).nBanks), +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/inclusive-cache/design/craft/inclusivecache/src/Configs.scala:82:39: method apply in class View is deprecated (since CDE 0.1): up(XYZ, site) is no longer necessary; remove the superfluous site argument +[warn] case SubsystemBankedCoherenceKey => up(SubsystemBankedCoherenceKey, site).copy(coherenceManager = { context => +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/inclusive-cache/design/craft/inclusivecache/src/Configs.scala:110:14: value LazyModule in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] val l2 = LazyModule(new InclusiveCache( +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/inclusive-cache/design/craft/inclusivecache/src/Configs.scala:136:18: value LazyModule in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] val filter = LazyModule(new TLFilter(cfilter = skipMMIO)) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/inclusive-cache/design/craft/inclusivecache/src/Configs.scala:139:16: value LazyModule in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] val cork = LazyModule(new TLCacheCork) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/inclusive-cache/design/craft/inclusivecache/src/Configs.scala:153:30: value LazyModule in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] val physicalFilter = LazyModule(new PhysicalFilter(fp.copy(controlBeatBytes = cbus.beatBytes))) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/inclusive-cache/design/craft/inclusivecache/src/Configs.scala:155:39: value LazyScope in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] physicalFilter.controlNode := LazyScope("physical_filter_xing", "TLPhysicalFilterCtrlCrossing") { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/inclusive-cache/design/craft/inclusivecache/src/Configs.scala:162:21: value LazyScope in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] _.ctrlnode := LazyScope("l2_ctrl_xing", "TLL2CtrlCrossing") { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/inclusive-cache/design/craft/inclusivecache/src/Control.scala:30:126: type LazyModule in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] class InclusiveCacheControl(outer: InclusiveCache, control: InclusiveCacheControlParameters)(implicit p: Parameters) extends LazyModule()(p) { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/inclusive-cache/design/craft/inclusivecache/src/Control.scala:38:22: type LazyModuleImp in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] class Impl extends LazyModuleImp(this) { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/inclusive-cache/design/craft/inclusivecache/src/InclusiveCache.scala:35:13: type LazyModule in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] extends LazyModule +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/inclusive-cache/design/craft/inclusivecache/src/InclusiveCache.scala:41:21: type ResourceBindings in package diplomacy is deprecated (since rocketchip 2.0.0): Use freechips.rocketchip.resources.ResourceBindings +[warn] var resourcesOpt: Option[ResourceBindings] = None +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/inclusive-cache/design/craft/inclusivecache/src/InclusiveCache.scala:43:15: type SimpleDevice in package diplomacy is deprecated (since rocketchip 2.0.0): Use freechips.rocketchip.resources.SimpleDevice +[warn] val device: SimpleDevice = new SimpleDevice("cache-controller", Seq("sifive,inclusivecache0", "cache")) { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/inclusive-cache/design/craft/inclusivecache/src/InclusiveCache.scala:43:34: type SimpleDevice in package diplomacy is deprecated (since rocketchip 2.0.0): Use freechips.rocketchip.resources.SimpleDevice +[warn] val device: SimpleDevice = new SimpleDevice("cache-controller", Seq("sifive,inclusivecache0", "cache")) { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/inclusive-cache/design/craft/inclusivecache/src/InclusiveCache.scala:44:29: value ResourceInt in package diplomacy is deprecated (since rocketchip 2.0.0): Use freechips.rocketchip.resources.ResourceInt +[warn] def ofInt(x: Int) = Seq(ResourceInt(BigInt(x))) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/inclusive-cache/design/craft/inclusivecache/src/InclusiveCache.scala:46:38: type ResourceBindings in package diplomacy is deprecated (since rocketchip 2.0.0): Use freechips.rocketchip.resources.ResourceBindings +[warn] override def describe(resources: ResourceBindings): Description = { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/inclusive-cache/design/craft/inclusivecache/src/InclusiveCache.scala:46:57: type Description in package diplomacy is deprecated (since rocketchip 2.0.0): Use freechips.rocketchip.resources.Description +[warn] override def describe(resources: ResourceBindings): Description = { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/inclusive-cache/design/craft/inclusivecache/src/InclusiveCache.scala:57:22: type ResourceValue in package diplomacy is deprecated (since rocketchip 2.0.0): Use freechips.rocketchip.resources.ResourceValue +[warn] val nextlevel: Option[(String, Seq[ResourceValue])] = +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/inclusive-cache/design/craft/inclusivecache/src/InclusiveCache.scala:61:53: value ResourceReference in package diplomacy is deprecated (since rocketchip 2.0.0): Use freechips.rocketchip.resources.ResourceReference +[warn] Some("next-level-cache" -> outer.map(l => ResourceReference(l)).toList) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/inclusive-cache/design/craft/inclusivecache/src/InclusiveCache.scala:71:7: value Description in package diplomacy is deprecated (since rocketchip 2.0.0): Use freechips.rocketchip.resources.Description +[warn] Description(name, mapping ++ extra ++ nextlevel) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/inclusive-cache/design/craft/inclusivecache/src/InclusiveCache.scala:76:24: method apply in object TLClientPortParameters is deprecated: Use TLMasterPortParameters.v1 instead of TLClientPortParameters +[warn] clientFn = { _ => TLClientPortParameters(Seq(TLClientParameters( +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/inclusive-cache/design/craft/inclusivecache/src/InclusiveCache.scala:76:51: method apply in object TLClientParameters is deprecated: Use TLMasterParameters.v1 instead of TLClientParameters +[warn] clientFn = { _ => TLClientPortParameters(Seq(TLClientParameters( +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/inclusive-cache/design/craft/inclusivecache/src/InclusiveCache.scala:81:24: method apply in object TLManagerPortParameters is deprecated: Use TLSlavePortParameters.v1 instead of TLManagerPortParameters +[warn] managerFn = { m => TLManagerPortParameters( +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/inclusive-cache/design/craft/inclusivecache/src/InclusiveCache.scala:84:30: value Resource in package diplomacy is deprecated (since rocketchip 2.0.0): Use freechips.rocketchip.resources.Resource +[warn] resources = Resource(device, "caches") +: m.resources, +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/inclusive-cache/design/craft/inclusivecache/src/InclusiveCache.scala:82:42: method copy in class TLSlaveParameters is deprecated: Use v1copy instead of copy +[warn] managers = m.managers.map { m => m.copy( +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/inclusive-cache/design/craft/inclusivecache/src/InclusiveCache.scala:103:33: value LazyModule in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] Seq.tabulate(nCtrls) { i => LazyModule(new InclusiveCacheControl(this, +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/inclusive-cache/design/craft/inclusivecache/src/InclusiveCache.scala:108:22: type LazyModuleImp in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] class Impl extends LazyModuleImp(this) { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/inclusive-cache/design/craft/inclusivecache/src/Parameters.scala:56:48: type ValName in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e)) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/inclusive-cache/design/craft/inclusivecache/src/Parameters.scala:56:59: value LazyModule in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e)) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/inclusive-cache/design/craft/inclusivecache/src/Parameters.scala:239:14: method copyArrayToImmutableIndexedSeq in class LowPriorityImplicits2 is deprecated (since 2.13.0): implicit conversions from Array to immutable.IndexedSeq are implemented by copying; use `toIndexedSeq` explicitly if you want to copy, or use the more efficient non-copying ArraySeq.unsafeWrapArray +[warn] Cat(bits.reverse) +[warn] ^ +[warn] 35 warnings found +[info] done compiling +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/patches/gemmini/Mesh.scala:86:46: method zipped in class Ops is deprecated (since 2.13.0): Use xs.lazyZip(ys).lazyZip(zs) +[warn] (tile.io.in_control, in_ctrl, valid).zipped.foreach { case (tile_ctrl, ctrl, v) => +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/Configs.scala:261:21: value LazyModule in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] val gemmini = LazyModule(new Gemmini(gemminiConfig)) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/Configs.scala:276:21: value LazyModule in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] val gemmini = LazyModule(new Gemmini(gemminiConfig)) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/Configs.scala:288:21: value LazyModule in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] val gemmini = LazyModule(new Gemmini(gemminiConfig)) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/Configs.scala:300:21: value LazyModule in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] val gemmini = LazyModule(new Gemmini(gemminiConfig)) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/Configs.scala:314:21: value LazyModule in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] int_gemmini = LazyModule(new Gemmini(GemminiConfigs.chipConfig.copy( +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/Configs.scala:323:20: value LazyModule in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] fp_gemmini = LazyModule(new Gemmini(GemminiFPConfigs.BF16DefaultConfig.copy( +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/Configs.scala:339:7: value InModuleBody in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] InModuleBody { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/ConfigsFP.scala:146:37: type ValName in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] implicit val v = implicitly[ValName] +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/ConfigsFP.scala:147:9: value LazyModule in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] LazyModule(new Gemmini(GemminiFPConfigs.FP32DefaultConfig)) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/ConfigsFP.scala:158:21: value LazyModule in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] val gemmini = LazyModule(new Gemmini(gemminiConfig)) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/ConfigsFP.scala:170:37: type ValName in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] implicit val v = implicitly[ValName] +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/ConfigsFP.scala:171:9: value LazyModule in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] LazyModule(new Gemmini(GemminiFPConfigs.FP16DefaultConfig)) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/ConfigsFP.scala:181:37: type ValName in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] implicit val v = implicitly[ValName] +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/ConfigsFP.scala:182:9: value LazyModule in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] LazyModule(new Gemmini(GemminiFPConfigs.BF16DefaultConfig)) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/ConfigsFP.scala:191:35: type ValName in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] implicit val v = implicitly[ValName] +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/ConfigsFP.scala:192:21: value LazyModule in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] val gemmini = LazyModule(new Gemmini(GemminiFPConfigs.BF16DefaultConfig.copy( +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/ConfigsFP.scala:206:37: type ValName in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] implicit val v = implicitly[ValName] +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/ConfigsFP.scala:207:9: value LazyModule in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] LazyModule(new Gemmini(GemminiFPConfigs.BF16Default8Config)) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/Controller.scala:35:14: value LazyModule in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] val spad = LazyModule(new Scratchpad(config)) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/Controller.scala:380:82: method zipped in class Ops is deprecated (since 2.13.0): Use xs.lazyZip(ys).lazyZip(zs) +[warn] (ex_controller.io.srams.read, im2col.io.sram_reads, spad.module.io.srams.read).zipped.foreach { case (ex_read, im2col_read, spad_read) => +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/CustomConfigs.scala:73:21: value LazyModule in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] val gemmini = LazyModule(new Gemmini(gemminiConfig)) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/DMA.scala:55:52: type LazyModule in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] (implicit p: Parameters) extends LazyModule { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/DMA.scala:56:14: value LazyModule in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] val core = LazyModule(new StreamReaderCore(config, nXacts, beatBits, maxBytes, spadWidth, accWidth, aligned_to, spad_rows, acc_rows, meshRows, use_tlb_register_filter, use_firesim_simulation_counters)) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/DMA.scala:60:22: type LazyModuleImp in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] class Impl extends LazyModuleImp(this) { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/DMA.scala:129:67: type LazyModule in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] (implicit p: Parameters) extends LazyModule { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/DMA.scala:130:61: method apply in object TLClientParameters is deprecated: Use TLMasterParameters.v1 instead of TLClientParameters +[warn] val node = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters( +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/DMA.scala:138:22: type LazyModuleImp in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] class Impl extends LazyModuleImp(this) with HasCoreParameters with MemoryOpConstants { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/DMA.scala:332:16: method apply in object SynthesizePrintf is deprecated (since FireSim 1.14): This method will be removed. Annotate the printf statement directly +[warn] printf(SynthesizePrintf("RDMA bytes rec: %d\n", total_bytes_read)) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/DMA.scala:354:52: type LazyModule in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] (implicit p: Parameters) extends LazyModule { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/DMA.scala:355:61: method apply in object TLClientParameters is deprecated: Use TLMasterParameters.v1 instead of TLClientParameters +[warn] val node = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters( +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/DMA.scala:363:22: type LazyModuleImp in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] class Impl extends LazyModuleImp(this) with HasCoreParameters with MemoryOpConstants { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/DMA.scala:649:16: method apply in object SynthesizePrintf is deprecated (since FireSim 1.14): This method will be removed. Annotate the printf statement directly +[warn] printf(SynthesizePrintf("WDMA bytes sent: %d\n", total_bytes_sent)) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/DMA.scala:650:16: method apply in object SynthesizePrintf is deprecated (since FireSim 1.14): This method will be removed. Annotate the printf statement directly +[warn] printf(SynthesizePrintf("WDMA total latency: %d\n", total_latency)) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/DSEConfigs.scala:121:37: type ValName in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] implicit val v = implicitly[ValName] +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/DSEConfigs.scala:122:9: value LazyModule in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] LazyModule(new Gemmini(DSEConfigs.baseConfig)) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/DSEConfigs.scala:132:37: type ValName in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] implicit val v = implicitly[ValName] +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/DSEConfigs.scala:133:9: value LazyModule in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] LazyModule(new Gemmini(DSEConfigs.wsOnlyConfig)) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/DSEConfigs.scala:143:37: type ValName in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] implicit val v = implicitly[ValName] +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/DSEConfigs.scala:144:9: value LazyModule in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] LazyModule(new Gemmini(DSEConfigs.bothDataflowsConfig)) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/DSEConfigs.scala:154:37: type ValName in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] implicit val v = implicitly[ValName] +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/DSEConfigs.scala:155:9: value LazyModule in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] LazyModule(new Gemmini(DSEConfigs.highBitwidthConfig)) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/DSEConfigs.scala:165:37: type ValName in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] implicit val v = implicitly[ValName] +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/DSEConfigs.scala:166:9: value LazyModule in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] LazyModule(new Gemmini(DSEConfigs.largerDimConfig)) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/DSEConfigs.scala:176:37: type ValName in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] implicit val v = implicitly[ValName] +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/DSEConfigs.scala:177:9: value LazyModule in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] LazyModule(new Gemmini(DSEConfigs.fullyCombinationalConfig)) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/DSEConfigs.scala:187:37: type ValName in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] implicit val v = implicitly[ValName] +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/DSEConfigs.scala:188:9: value LazyModule in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] LazyModule(new Gemmini(DSEConfigs.moreMemoryConfig)) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/DSEConfigs.scala:198:37: type ValName in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] implicit val v = implicitly[ValName] +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/DSEConfigs.scala:199:9: value LazyModule in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] LazyModule(new Gemmini(DSEConfigs.moreBanksConfig)) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/DSEConfigs.scala:209:37: type ValName in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] implicit val v = implicitly[ValName] +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/DSEConfigs.scala:210:9: value LazyModule in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] LazyModule(new Gemmini(DSEConfigs.narrowerBusConfig)) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/DSEConfigs.scala:220:35: type ValName in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] implicit val v = implicitly[ValName] +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/DSEConfigs.scala:221:7: value LazyModule in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] LazyModule(new Gemmini(DSEConfigs.pnr16Config)) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/DSEConfigs.scala:231:35: type ValName in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] implicit val v = implicitly[ValName] +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/DSEConfigs.scala:232:7: value LazyModule in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] LazyModule(new Gemmini(DSEConfigs.pnr32Config)) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/DSEConfigs.scala:242:37: type ValName in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] implicit val v = implicitly[ValName] +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/DSEConfigs.scala:243:9: value LazyModule in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] LazyModule(new Gemmini(DSEConfigs.baseConfig)) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/Pipeline.scala:29:49: method zipped in class Ops is deprecated (since 2.13.0): Use xs.lazyZip(ys).lazyZip(zs) +[warn] (stalling.init, stalling.tail, valids.init).zipped.foreach { case (s1, s2, v1) => +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/Pipeline.scala:39:34: method zipped in class Ops is deprecated (since 2.13.0): Use xs.lazyZip(ys) +[warn] (valids.init, stalling.tail).zipped.foreach { case (v1, s2) => +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/Pipeline.scala:48:32: method zipped in class Ops is deprecated (since 2.13.0): Use xs.lazyZip(ys) +[warn] (valids.tail, valids.init).zipped.foreach { case (v2, v1) => +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/ReservationStation.scala:585:14: method apply in object SynthesizePrintf is deprecated (since FireSim 1.14): This method will be removed. Annotate the printf statement directly +[warn] printf(SynthesizePrintf("Utilization: %d\n", utilization)) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/ReservationStation.scala:586:14: method apply in object SynthesizePrintf is deprecated (since FireSim 1.14): This method will be removed. Annotate the printf statement directly +[warn] printf(SynthesizePrintf("Utilization ld q (incomplete): %d\n", utilization_ld_q_unissued)) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/ReservationStation.scala:587:14: method apply in object SynthesizePrintf is deprecated (since FireSim 1.14): This method will be removed. Annotate the printf statement directly +[warn] printf(SynthesizePrintf("Utilization st q (incomplete): %d\n", utilization_st_q_unissued)) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/ReservationStation.scala:588:14: method apply in object SynthesizePrintf is deprecated (since FireSim 1.14): This method will be removed. Annotate the printf statement directly +[warn] printf(SynthesizePrintf("Utilization ex q (incomplete): %d\n", utilization_ex_q_unissued)) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/ReservationStation.scala:589:14: method apply in object SynthesizePrintf is deprecated (since FireSim 1.14): This method will be removed. Annotate the printf statement directly +[warn] printf(SynthesizePrintf("Utilization ld q: %d\n", utilization_ld_q)) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/ReservationStation.scala:590:14: method apply in object SynthesizePrintf is deprecated (since FireSim 1.14): This method will be removed. Annotate the printf statement directly +[warn] printf(SynthesizePrintf("Utilization st q: %d\n", utilization_st_q)) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/ReservationStation.scala:591:14: method apply in object SynthesizePrintf is deprecated (since FireSim 1.14): This method will be removed. Annotate the printf statement directly +[warn] printf(SynthesizePrintf("Utilization ex q: %d\n", utilization_ex_q)) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/Scratchpad.scala:192:57: type LazyModule in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] (implicit p: Parameters, ev: Arithmetic[T]) extends LazyModule { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/Scratchpad.scala:208:16: value LazyModule in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] val reader = LazyModule(new StreamReader(config, max_in_flight_mem_reqs, dataBits, maxBytes, spad_w, acc_w, aligned_to, +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/Scratchpad.scala:211:16: value LazyModule in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] val writer = LazyModule(new StreamWriter(max_in_flight_mem_reqs, dataBits, maxBytes, +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/Scratchpad.scala:214:56: value LazyModule in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] val spad_writer = Option.when(config.use_tl_ext_mem)(LazyModule(new StreamWriter(max_in_flight_mem_reqs, dataBits, maxBytes, +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/Scratchpad.scala:227:22: type LazyModuleImp in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] class Impl extends LazyModuleImp(this) with HasCoreParameters { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/XactTracker.scala:106:14: method apply in object SynthesizePrintf is deprecated (since FireSim 1.14): This method will be removed. Annotate the printf statement directly +[warn] printf(SynthesizePrintf("RDMA total latency: %d\n", total_latency)) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/thirdparty/gemmini/src/main/scala/gemmini/VectorScalarMultiplier.scala:135:32: unreachable code +[warn] case b: Bool => 1.U(1.W) +[warn] ^ +[warn] 81 warnings found +[info] done compiling +[info] compiling 213 Scala sources to /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/target/scala-2.13/classes ... +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/upstream/arch/src/main/scala/framework/gpdomain/sequencer/decoder/T1DecodePattern.scala:38:43: Auto-application to `()` is deprecated. Supply the empty argument list `()` explicitly to invoke method apply, +[warn] or remove the empty argument list from its definition (Java-defined methods are exempt). +[warn] In Scala 3, an unapplied method like this will be eta-expanded into a function. [quickfixable] +[warn] val attributes = IO(Output(Property[Seq[AnyClassType]])) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/upstream/arch/src/main/scala/framework/gpdomain/sequencer/decoder/T1DecodePattern.scala:40:42: Auto-application to `()` is deprecated. Supply the empty argument list `()` explicitly to invoke method apply, +[warn] or remove the empty argument list from its definition (Java-defined methods are exempt). +[warn] In Scala 3, an unapplied method like this will be eta-expanded into a function. [quickfixable] +[warn] val attributesIn = IO(Input(Property[Seq[AnyClassType]])) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/upstream/arch/src/main/scala/framework/gpdomain/sequencer/decoder/TableGenerator.scala:22:16: implicit conversion method bool2str should be enabled +[warn] by making the implicit value scala.language.implicitConversions visible. +[warn] This can be achieved by adding the import clause 'import scala.language.implicitConversions' +[warn] or by setting the compiler option -language:implicitConversions. +[warn] See the Scaladoc for value scala.language.implicitConversions for a discussion +[warn] why the feature should be explicitly enabled. +[warn] implicit def bool2str(b: Boolean): String = if (b) "b1" else "b0" +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/src/main/scala/ToyLinuxConfig.scala:72:24: method apply in class View is deprecated (since CDE 0.1): up(XYZ, site) is no longer necessary; remove the superfluous site argument +[warn] case SystemBusKey => up(SystemBusKey, site).copy(beatBytes = 16, dtsFrequency = Some(BigInt(50000000))) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/src/main/scala/ToyLinuxConfig.scala:73:24: method apply in class View is deprecated (since CDE 0.1): up(XYZ, site) is no longer necessary; remove the superfluous site argument +[warn] case MemoryBusKey => up(MemoryBusKey, site).copy(beatBytes = 16, dtsFrequency = Some(BigInt(50000000))) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/src/main/scala/ToyLinuxConfig.scala:74:27: method apply in class View is deprecated (since CDE 0.1): up(XYZ, site) is no longer necessary; remove the superfluous site argument +[warn] case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = Some(BigInt(50000000))) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/src/main/scala/ToyLinuxConfig.scala:75:25: method apply in class View is deprecated (since CDE 0.1): up(XYZ, site) is no longer necessary; remove the superfluous site argument +[warn] case ControlBusKey => up(ControlBusKey, site).copy(dtsFrequency = Some(BigInt(50000000))) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/src/main/scala/ToyLinuxConfig.scala:76:23: method apply in class View is deprecated (since CDE 0.1): up(XYZ, site) is no longer necessary; remove the superfluous site argument +[warn] case FrontBusKey => up(FrontBusKey, site).copy(dtsFrequency = Some(BigInt(50000000))) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/src/main/scala/ToyLinuxConfig.scala:78:37: method apply in class View is deprecated (since CDE 0.1): up(XYZ, site) is no longer necessary; remove the superfluous site argument +[warn] case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site).map { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/src/main/scala/ToyLinuxConfig.scala:116:5: method apply in class View is deprecated (since CDE 0.1): up(XYZ, site) is no longer necessary; remove the superfluous site argument +[warn] up(TilesLocated(InSubsystem), site).map { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/src/main/scala/ToyLinuxConfig.scala:135:17: method apply in class View is deprecated (since CDE 0.1): up(XYZ, site) is no longer necessary; remove the superfluous site argument +[warn] val cache = up(InclusiveCacheKey, site) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/src/main/scala/ToyLinuxConfig.scala:138:37: method apply in class View is deprecated (since CDE 0.1): up(XYZ, site) is no longer necessary; remove the superfluous site argument +[warn] case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site).map { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/src/main/scala/ToyLinuxConfig.scala:171:37: method apply in class View is deprecated (since CDE 0.1): up(XYZ, site) is no longer necessary; remove the superfluous site argument +[warn] case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site).map { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/upstream/arch/src/main/scala/framework/builtin/pipeline/Pipeline.scala:30:49: method zipped in class Ops is deprecated (since 2.13.0): Use xs.lazyZip(ys).lazyZip(zs) +[warn] (stalling.init, stalling.tail, valids.init).zipped.foreach { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/upstream/arch/src/main/scala/framework/builtin/pipeline/Pipeline.scala:41:34: method zipped in class Ops is deprecated (since 2.13.0): Use xs.lazyZip(ys) +[warn] (valids.init, stalling.tail).zipped.foreach { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/upstream/arch/src/main/scala/framework/builtin/pipeline/Pipeline.scala:51:32: method zipped in class Ops is deprecated (since 2.13.0): Use xs.lazyZip(ys) +[warn] (valids.tail, valids.init).zipped.foreach { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/upstream/arch/src/main/scala/framework/gpdomain/sequencer/decoder/TableGenerator.scala:13:35: type Traversable in package scala is deprecated (since 2.13.0): Use Iterable instead of Traversable +[warn] implicit class CrossAble[X](xs: Traversable[X]) { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/upstream/arch/src/main/scala/framework/gpdomain/sequencer/decoder/TableGenerator.scala:15:22: type Traversable in package scala is deprecated (since 2.13.0): Use Iterable instead of Traversable +[warn] def cross[Y](ys: Traversable[Y]): Traversable[(X, Y)] = for { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/upstream/arch/src/main/scala/framework/gpdomain/sequencer/decoder/TableGenerator.scala:15:39: type Traversable in package scala is deprecated (since 2.13.0): Use Iterable instead of Traversable +[warn] def cross[Y](ys: Traversable[Y]): Traversable[(X, Y)] = for { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/upstream/arch/src/main/scala/framework/system/tile/BBTile.scala:175:85: method apply in object TLClientParameters is deprecated: Use TLMasterParameters.v1 instead of TLClientParameters +[warn] if (bbPerCore(i).isDefined) Some(TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters( +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/upstream/arch/src/main/scala/framework/system/tile/BBTile.scala:183:85: method apply in object TLClientParameters is deprecated: Use TLMasterParameters.v1 instead of TLClientParameters +[warn] if (bbPerCore(i).isDefined) Some(TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters( +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/upstream/arch/src/main/scala/framework/system/tile/BBTile.scala:305:3: method DisableMonitors in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] DisableMonitors(implicit p => tlSlaveXbar.node :*= slaveNode) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/upstream/arch/src/main/scala/framework/system/tile/Configs.scala:59:40: method apply in class View is deprecated (since CDE 0.1): up(XYZ, site) is no longer necessary; remove the superfluous site argument +[warn] val prev = up(TilesLocated(`location`), site) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/upstream/arch/src/main/scala/framework/system/tile/Configs.scala:110:40: method apply in class View is deprecated (since CDE 0.1): up(XYZ, site) is no longer necessary; remove the superfluous site argument +[warn] val prev = up(TilesLocated(`location`), site) +[warn] ^ +[warn] 24 warnings found +[info] done compiling +[info] running fpga.arty.linux.EmitGlobalRobCheck +[success] Total time: 59 s, completed Oct 13, 2026, 12:56:44 AM diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/globalrob-check/simulation.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/globalrob-check/simulation.log new file mode 100644 index 0000000..10926fb --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/globalrob-check/simulation.log @@ -0,0 +1,5 @@ +PASS GLOBALROB RAM/register cycle comparison, payloads, wrap, stalls, resets cycles=8029 +- /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/tb_globalrob.sv:25: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 80us; walltime 0.032 s; speed 2.475 ms/s +- Verilator: cpu 0.032 s on 1 threads; allocated 7 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/loop-stress/simulation/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/loop-stress/simulation/RESULT.json new file mode 100644 index 0000000..acd0a0f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/loop-stress/simulation/RESULT.json @@ -0,0 +1,10 @@ +{ + "result": "PASS", + "test_label": "whole Toy 40 alternating multi tile OS WS loops", + "core_rtl_sha256": "31e7e07f94d08208dbb564edf9546240df26ff834935bfb646b71b541d875fb9", + "test_binary_sha256": "bbe9646dc565ac9ac1188c6b3d53d24b1b37985ee158ee2ac918df04c3267ce2", + "cycles_including_boot": 652682, + "memory_read_bursts": 3498, + "memory_write_bursts": 5766, + "linux_boot_tested": false +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/loop-stress/simulation/simulation.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/loop-stress/simulation/simulation.log new file mode 100644 index 0000000..7c0b282 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/loop-stress/simulation/simulation.log @@ -0,0 +1,7 @@ +CPU status = 00000000600d600d +PASS whole Toy 40 alternating multi tile OS WS loops +- /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:88: Verilog $finish +MEASURE cycles=652682 memory_reads=3498 memory_writes=5766 +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 7ms; walltime 4.818 s; speed 1.355 ms/s +- Verilator: cpu 4.817 s on 1 threads; allocated 8 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/loop-stress/simulation/smoke.bin b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/loop-stress/simulation/smoke.bin new file mode 100644 index 0000000..d985179 Binary files /dev/null and b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/loop-stress/simulation/smoke.bin differ diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/loop-stress/simulation/smoke.disasm b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/loop-stress/simulation/smoke.disasm new file mode 100644 index 0000000..54de83c --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/loop-stress/simulation/smoke.disasm @@ -0,0 +1,337 @@ + +/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/smoke.elf: file format elf64-littleriscv + + +Disassembly of section .text: + +0000000080000000 <_start>: + 80000000: 00002137 lui sp,0x2 + 80000004: 0011011b addiw sp,sp,1 # 2001 <_start-0x7fffdfff> + 80000008: 01211113 slli sp,sp,0x12 + 8000000c: ff010113 addi sp,sp,-16 + 80000010: 00000297 auipc t0,0x0 + 80000014: 04c28293 addi t0,t0,76 # 8000005c + 80000018: 30529073 csrw mtvec,t0 + 8000001c: 30401073 csrw mie,zero + 80000020: 30201073 csrw medeleg,zero + 80000024: 0001e2b7 lui t0,0x1e + 80000028: 3002a073 csrs mstatus,t0 + 8000002c: 00000097 auipc ra,0x0 + 80000030: 050080e7 jalr 80(ra) # 8000007c
+ 80000034: 600002b7 lui t0,0x60000 + 80000038: 600d6337 lui t1,0x600d6 + 8000003c: 00d3031b addiw t1,t1,13 # 600d600d <_start-0x1ff29ff3> + 80000040: 00050a63 beqz a0,80000054 + 80000044: 00001337 lui t1,0x1 + 80000048: bad3031b addiw t1,t1,-1107 # bad <_start-0x7ffff453> + 8000004c: 01431313 slli t1,t1,0x14 + 80000050: 00a36333 or t1,t1,a0 + +0000000080000054 : + 80000054: 0062b023 sd t1,0(t0) # 60000000 <_start-0x20000000> + 80000058: 0000006f j 80000058 + +000000008000005c : + 8000005c: 342023f3 csrr t2,mcause + 80000060: 600002b7 lui t0,0x60000 + 80000064: 000bb337 lui t1,0xbb + 80000068: d0f3031b addiw t1,t1,-753 # bad0f <_start-0x7ff452f1> + 8000006c: 00c31313 slli t1,t1,0xc + 80000070: 00736333 or t1,t1,t2 + 80000074: 0062b023 sd t1,0(t0) # 60000000 <_start-0x20000000> + 80000078: 0000006f j 80000078 + +000000008000007c
: + 8000007c: 715d addi sp,sp,-80 + 8000007e: e062 sd s8,0(sp) + 80000080: 38e39537 lui a0,0x38e39 + 80000084: 00001c17 auipc s8,0x1 + 80000088: c7cc0c13 addi s8,s8,-900 # 80000d00 + 8000008c: e0a2 sd s0,64(sp) + 8000008e: e486 sd ra,72(sp) + 80000090: fc26 sd s1,56(sp) + 80000092: f84a sd s2,48(sp) + 80000094: f44e sd s3,40(sp) + 80000096: f052 sd s4,32(sp) + 80000098: ec56 sd s5,24(sp) + 8000009a: e85a sd s6,16(sp) + 8000009c: e45e sd s7,8(sp) + 8000009e: 0880 addi s0,sp,80 + 800000a0: 8862 mv a6,s8 + 800000a2: e3950513 addi a0,a0,-455 # 38e38e39 <_start-0x471c71c7> + 800000a6: 02800593 li a1,40 + 800000aa: 04000893 li a7,64 + 800000ae: fd85869b addiw a3,a1,-40 + 800000b2: 8642 mv a2,a6 + 800000b4: 02069713 slli a4,a3,0x20 + 800000b8: 9301 srli a4,a4,0x20 + 800000ba: 02a70733 mul a4,a4,a0 + 800000be: 0605 addi a2,a2,1 + 800000c0: 9305 srli a4,a4,0x21 + 800000c2: 0037179b slliw a5,a4,0x3 + 800000c6: 9fb9 addw a5,a5,a4 + 800000c8: 40f687bb subw a5,a3,a5 + 800000cc: 37f1 addiw a5,a5,-4 + 800000ce: fef60fa3 sb a5,-1(a2) + 800000d2: 2695 addiw a3,a3,5 + 800000d4: feb690e3 bne a3,a1,800000b4 + 800000d8: 0036859b addiw a1,a3,3 + 800000dc: 0821 addi a6,a6,8 + 800000de: fd1598e3 bne a1,a7,800000ae + 800000e2: 2e8ba537 lui a0,0x2e8ba + 800000e6: 2e950513 addi a0,a0,745 # 2e8ba2e9 <_start-0x51745d17> + 800000ea: 00001b97 auipc s7,0x1 + 800000ee: b16b8b93 addi s7,s7,-1258 # 80000c00 + 800000f2: 00001597 auipc a1,0x1 + 800000f6: b2e58593 addi a1,a1,-1234 # 80000c20 + 800000fa: 4801 li a6,0 + 800000fc: 03800893 li a7,56 + 80000100: fe058613 addi a2,a1,-32 + 80000104: 86c2 mv a3,a6 + 80000106: 02a68733 mul a4,a3,a0 + 8000010a: 41f6d79b sraiw a5,a3,0x1f + 8000010e: 0605 addi a2,a2,1 + 80000110: 9705 srai a4,a4,0x21 + 80000112: 9f1d subw a4,a4,a5 + 80000114: 0017179b slliw a5,a4,0x1 + 80000118: 9fb9 addw a5,a5,a4 + 8000011a: 0027979b slliw a5,a5,0x2 + 8000011e: 9f99 subw a5,a5,a4 + 80000120: 40f687bb subw a5,a3,a5 + 80000124: 37ed addiw a5,a5,-5 + 80000126: fef60fa3 sb a5,-1(a2) + 8000012a: 2689 addiw a3,a3,2 + 8000012c: fcb61de3 bne a2,a1,80000106 + 80000130: 281d addiw a6,a6,7 + 80000132: 02060593 addi a1,a2,32 + 80000136: fd1815e3 bne a6,a7,80000100 + 8000013a: 47a1 li a5,8 + 8000013c: 86be mv a3,a5 + 8000013e: 02000713 li a4,32 + 80000142: 00000617 auipc a2,0x0 + 80000146: 2be60613 addi a2,a2,702 # 80000400 + 8000014a: 00001597 auipc a1,0x1 + 8000014e: ab658593 addi a1,a1,-1354 # 80000c00 + 80000152: 00001517 auipc a0,0x1 + 80000156: bae50513 addi a0,a0,-1106 # 80000d00 + 8000015a: 00000097 auipc ra,0x0 + 8000015e: 180080e7 jalr 384(ra) # 800002da + 80000162: 57fd li a5,-1 + 80000164: 4905 li s2,1 + 80000166: 040019b7 lui s3,0x4001 + 8000016a: 83e5 srli a5,a5,0x19 + 8000016c: 4a85 li s5,1 + 8000016e: 00000b17 auipc s6,0x0 + 80000172: 692b0b13 addi s6,s6,1682 # 80000800 + 80000176: 099a slli s3,s3,0x6 + 80000178: 1916 slli s2,s2,0x25 + 8000017a: 40200a37 lui s4,0x40200 + 8000017e: 99d6 add s3,s3,s5 + 80000180: 00fc7c33 and s8,s8,a5 + 80000184: 00fbfbb3 and s7,s7,a5 + 80000188: 00fb7b33 and s6,s6,a5 + 8000018c: 0921 addi s2,s2,8 + 8000018e: 1a9e slli s5,s5,0x27 + 80000190: 400a0a13 addi s4,s4,1024 # 40200400 <_start-0x3fdffc00> + 80000194: 4481 li s1,0 + 80000196: a019 j 8000019c + 80000198: 08f48a63 beq s1,a5,8000022c + 8000019c: 02000613 li a2,32 + 800001a0: 45a1 li a1,8 + 800001a2: 00000517 auipc a0,0x0 + 800001a6: 65e50513 addi a0,a0,1630 # 80000800 + 800001aa: 00000097 auipc ra,0x0 + 800001ae: 112080e7 jalr 274(ra) # 800002bc + 800001b2: 0014f713 andi a4,s1,1 + 800001b6: 0712 slli a4,a4,0x4 + 800001b8: 4781 li a5,0 + 800001ba: 04e7b07b .insn 4, 0x04e7b07b + 800001be: a137b07b .insn 4, 0xa137b07b + 800001c2: a387b07b .insn 4, 0xa387b07b + 800001c6: a577b07b .insn 4, 0xa577b07b + 800001ca: 4701 li a4,0 + 800001cc: a6e7b07b .insn 4, 0xa6e7b07b + 800001d0: a967b07b .insn 4, 0xa967b07b + 800001d4: ab27b07b .insn 4, 0xab27b07b + 800001d8: ad57b07b .insn 4, 0xad57b07b + 800001dc: af47b07b .insn 4, 0xaf47b07b + 800001e0: 00f7b07b .insn 4, 0x00f7b07b + 800001e4: 0330000f fence rw,rw + 800001e8: 0000100f fence.i + 800001ec: 02000693 li a3,32 + 800001f0: 4621 li a2,8 + 800001f2: 00000597 auipc a1,0x0 + 800001f6: 20e58593 addi a1,a1,526 # 80000400 + 800001fa: 00000517 auipc a0,0x0 + 800001fe: 60650513 addi a0,a0,1542 # 80000800 + 80000202: 00000097 auipc ra,0x0 + 80000206: 074080e7 jalr 116(ra) # 80000276 + 8000020a: 02800793 li a5,40 + 8000020e: 2485 addiw s1,s1,1 + 80000210: f541 bnez a0,80000198 + 80000212: 60a6 ld ra,72(sp) + 80000214: 6406 ld s0,64(sp) + 80000216: 7942 ld s2,48(sp) + 80000218: 79a2 ld s3,40(sp) + 8000021a: 7a02 ld s4,32(sp) + 8000021c: 6ae2 ld s5,24(sp) + 8000021e: 6b42 ld s6,16(sp) + 80000220: 6ba2 ld s7,8(sp) + 80000222: 6c02 ld s8,0(sp) + 80000224: 8526 mv a0,s1 + 80000226: 74e2 ld s1,56(sp) + 80000228: 6161 addi sp,sp,80 + 8000022a: 8082 ret + 8000022c: 4481 li s1,0 + 8000022e: b7d5 j 80000212 + +0000000080000230 : + 80000230: 715d addi sp,sp,-80 + 80000232: e022 sd s0,0(sp) + 80000234: e406 sd ra,8(sp) + 80000236: 0800 addi s0,sp,16 + 80000238: e40c sd a1,8(s0) + 8000023a: 60a2 ld ra,8(sp) + 8000023c: e810 sd a2,16(s0) + 8000023e: ec14 sd a3,24(s0) + 80000240: f018 sd a4,32(s0) + 80000242: f41c sd a5,40(s0) + 80000244: 03043823 sd a6,48(s0) + 80000248: 03143c23 sd a7,56(s0) + 8000024c: 6402 ld s0,0(sp) + 8000024e: 4501 li a0,0 + 80000250: 6161 addi sp,sp,80 + 80000252: 8082 ret + +0000000080000254 : + 80000254: 1141 addi sp,sp,-16 + 80000256: e022 sd s0,0(sp) + 80000258: e406 sd ra,8(sp) + 8000025a: 0800 addi s0,sp,16 + 8000025c: 00c50733 add a4,a0,a2 + 80000260: c619 beqz a2,8000026e + 80000262: 87aa mv a5,a0 + 80000264: 00b78023 sb a1,0(a5) + 80000268: 0785 addi a5,a5,1 + 8000026a: fee79de3 bne a5,a4,80000264 + 8000026e: 60a2 ld ra,8(sp) + 80000270: 6402 ld s0,0(sp) + 80000272: 0141 addi sp,sp,16 + 80000274: 8082 ret + +0000000080000276 : + 80000276: 02d6073b mulw a4,a2,a3 + 8000027a: 02e05f63 blez a4,800002b8 + 8000027e: 87ae mv a5,a1 + 80000280: 4581 li a1,0 + 80000282: a021 j 8000028a + 80000284: 2585 addiw a1,a1,1 + 80000286: 02e58963 beq a1,a4,800002b8 + 8000028a: 4114 lw a3,0(a0) + 8000028c: 4390 lw a2,0(a5) + 8000028e: 0511 addi a0,a0,4 + 80000290: 0791 addi a5,a5,4 + 80000292: fec689e3 beq a3,a2,80000284 + 80000296: 1141 addi sp,sp,-16 + 80000298: e022 sd s0,0(sp) + 8000029a: e406 sd ra,8(sp) + 8000029c: 0800 addi s0,sp,16 + 8000029e: 00000517 auipc a0,0x0 + 800002a2: 11250513 addi a0,a0,274 # 800003b0 + 800002a6: 00000097 auipc ra,0x0 + 800002aa: f8a080e7 jalr -118(ra) # 80000230 + 800002ae: 60a2 ld ra,8(sp) + 800002b0: 6402 ld s0,0(sp) + 800002b2: 4501 li a0,0 + 800002b4: 0141 addi sp,sp,16 + 800002b6: 8082 ret + 800002b8: 4505 li a0,1 + 800002ba: 8082 ret + +00000000800002bc : + 800002bc: 02c5863b mulw a2,a1,a2 + 800002c0: 1141 addi sp,sp,-16 + 800002c2: e022 sd s0,0(sp) + 800002c4: e406 sd ra,8(sp) + 800002c6: 0800 addi s0,sp,16 + 800002c8: 6402 ld s0,0(sp) + 800002ca: 60a2 ld ra,8(sp) + 800002cc: 4581 li a1,0 + 800002ce: 060a slli a2,a2,0x2 + 800002d0: 0141 addi sp,sp,16 + 800002d2: 00000317 auipc t1,0x0 + 800002d6: f8230067 jr -126(t1) # 80000254 + +00000000800002da : + 800002da: 02e6883b mulw a6,a3,a4 + 800002de: 715d addi sp,sp,-80 + 800002e0: e0a2 sd s0,64(sp) + 800002e2: fc26 sd s1,56(sp) + 800002e4: 0880 addi s0,sp,80 + 800002e6: f84a sd s2,48(sp) + 800002e8: f44e sd s3,40(sp) + 800002ea: e486 sd ra,72(sp) + 800002ec: 84b2 mv s1,a2 + 800002ee: 89aa mv s3,a0 + 800002f0: 892e mv s2,a1 + 800002f2: 8532 mv a0,a2 + 800002f4: 4581 li a1,0 + 800002f6: 00281613 slli a2,a6,0x2 + 800002fa: fcd43023 sd a3,-64(s0) + 800002fe: fae43c23 sd a4,-72(s0) + 80000302: fcf43423 sd a5,-56(s0) + 80000306: 00000097 auipc ra,0x0 + 8000030a: f4e080e7 jalr -178(ra) # 80000254 + 8000030e: fc043683 ld a3,-64(s0) + 80000312: 02d05c63 blez a3,8000034a + 80000316: fc843783 ld a5,-56(s0) + 8000031a: fb843703 ld a4,-72(s0) + 8000031e: f052 sd s4,32(sp) + 80000320: 4f01 li t5,0 + 80000322: 4281 li t0,0 + 80000324: 4381 li t2,0 + 80000326: 00f98a33 add s4,s3,a5 + 8000032a: 02e05763 blez a4,80000358 + 8000032e: 4e81 li t4,0 + 80000330: 02f04e63 bgtz a5,8000036c + 80000334: 0e85 addi t4,t4,1 + 80000336: feee9de3 bne t4,a4,80000330 + 8000033a: 2385 addiw t2,t2,1 + 8000033c: 00f282bb addw t0,t0,a5 + 80000340: 00ef0f3b addw t5,t5,a4 + 80000344: fe7695e3 bne a3,t2,8000032e + 80000348: 7a02 ld s4,32(sp) + 8000034a: 60a6 ld ra,72(sp) + 8000034c: 6406 ld s0,64(sp) + 8000034e: 74e2 ld s1,56(sp) + 80000350: 7942 ld s2,48(sp) + 80000352: 79a2 ld s3,40(sp) + 80000354: 6161 addi sp,sp,80 + 80000356: 8082 ret + 80000358: 2385 addiw t2,t2,1 + 8000035a: 00f282bb addw t0,t0,a5 + 8000035e: 00ef0f3b addw t5,t5,a4 + 80000362: fe7683e3 beq a3,t2,80000348 + 80000366: fce044e3 bgtz a4,8000032e + 8000036a: b7fd j 80000358 + 8000036c: 8376 mv t1,t4 + 8000036e: 00598fb3 add t6,s3,t0 + 80000372: 005a0e33 add t3,s4,t0 + 80000376: 01e3033b addw t1,t1,t5 + 8000037a: 030a slli t1,t1,0x2 + 8000037c: 9326 add t1,t1,s1 + 8000037e: 00032803 lw a6,0(t1) + 80000382: 867e mv a2,t6 + 80000384: 01d90533 add a0,s2,t4 + 80000388: 00060583 lb a1,0(a2) + 8000038c: 00050883 lb a7,0(a0) + 80000390: 0605 addi a2,a2,1 + 80000392: 953a add a0,a0,a4 + 80000394: 031585bb mulw a1,a1,a7 + 80000398: 0105883b addw a6,a1,a6 + 8000039c: 01032023 sw a6,0(t1) + 800003a0: fece14e3 bne t3,a2,80000388 + 800003a4: 0e85 addi t4,t4,1 + 800003a6: fbd709e3 beq a4,t4,80000358 + 800003aa: 8376 mv t1,t4 + 800003ac: b7e9 j 80000376 diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/loop-stress/simulation/smoke.elf b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/loop-stress/simulation/smoke.elf new file mode 100644 index 0000000..6555746 Binary files /dev/null and b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/loop-stress/simulation/smoke.elf differ diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/loop-stress/simulation/smoke.hex b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/loop-stress/simulation/smoke.hex new file mode 100644 index 0000000..504292e --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/loop-stress/simulation/smoke.hex @@ -0,0 +1,987 @@ +37 +21 +00 +00 +1b +01 +11 +00 +13 +11 +21 +01 +13 +01 +01 +ff +97 +02 +00 +00 +93 +82 +c2 +04 +73 +90 +52 +30 +73 +10 +40 +30 +73 +10 +20 +30 +b7 +e2 +01 +00 +73 +a0 +02 +30 +97 +00 +00 +00 +e7 +80 +00 +05 +b7 +02 +00 +60 +37 +63 +0d +60 +1b +03 +d3 +00 +63 +0a +05 +00 +37 +13 +00 +00 +1b +03 +d3 +ba +13 +13 +43 +01 +33 +63 +a3 +00 +23 +b0 +62 +00 +6f +00 +00 +00 +f3 +23 +20 +34 +b7 +02 +00 +60 +37 +b3 +0b +00 +1b +03 +f3 +d0 +13 +13 +c3 +00 +33 +63 +73 +00 +23 +b0 +62 +00 +6f +00 +00 +00 +5d +71 +62 +e0 +37 +95 +e3 +38 +17 +1c +00 +00 +13 +0c +cc +c7 +a2 +e0 +86 +e4 +26 +fc +4a +f8 +4e +f4 +52 +f0 +56 +ec +5a +e8 +5e +e4 +80 +08 +62 +88 +13 +05 +95 +e3 +93 +05 +80 +02 +93 +08 +00 +04 +9b +86 +85 +fd +42 +86 +13 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+fe +85 +0e +e3 +09 +d7 +fb +76 +83 +e9 +b7 +00 +00 +4d +69 +73 +6d +61 +74 +63 +68 +20 +61 +74 +20 +69 +6e +64 +65 +78 +20 +25 +64 +3a +20 +65 +78 +70 +65 +63 +74 +65 +64 +20 +25 +64 +2c +20 +67 +6f +74 +20 +25 +64 +0a +00 \ No newline at end of file diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/loop-stress/simulation/tb_cpu.sv b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/loop-stress/simulation/tb_cpu.sv new file mode 100644 index 0000000..3ad5256 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/loop-stress/simulation/tb_cpu.sv @@ -0,0 +1,153 @@ +`timescale 1ns/1ps +module tb; + reg clock=0; + reg reset=0; + reg interrupt=0; + wire memory_aw_ready; + wire memory_aw_valid; + wire [3:0] memory_aw_bits_id; + wire [31:0] memory_aw_bits_addr; + wire [7:0] memory_aw_bits_len; + wire [2:0] memory_aw_bits_size; + wire [1:0] memory_aw_bits_burst; + wire memory_aw_bits_lock; + wire [3:0] memory_aw_bits_cache; + wire [2:0] memory_aw_bits_prot; + wire [3:0] memory_aw_bits_qos; + wire memory_w_ready; + wire memory_w_valid; + wire [127:0] memory_w_bits_data; + wire [15:0] memory_w_bits_strb; + wire memory_w_bits_last; + wire memory_b_ready; + wire memory_b_valid; + wire [3:0] memory_b_bits_id; + wire [1:0] memory_b_bits_resp; + wire memory_ar_ready; + wire memory_ar_valid; + wire [3:0] memory_ar_bits_id; + wire [31:0] memory_ar_bits_addr; + wire [7:0] memory_ar_bits_len; + wire [2:0] memory_ar_bits_size; + wire [1:0] memory_ar_bits_burst; + wire memory_ar_bits_lock; + wire [3:0] memory_ar_bits_cache; + wire [2:0] memory_ar_bits_prot; + wire [3:0] memory_ar_bits_qos; + wire memory_r_ready; + wire memory_r_valid; + wire [3:0] memory_r_bits_id; + wire [127:0] memory_r_bits_data; + wire [1:0] memory_r_bits_resp; + wire memory_r_bits_last; + wire peripherals_aw_ready; + wire peripherals_aw_valid; + wire [1:0] peripherals_aw_bits_id; + wire [30:0] peripherals_aw_bits_addr; + wire [7:0] peripherals_aw_bits_len; + wire [2:0] peripherals_aw_bits_size; + wire [1:0] peripherals_aw_bits_burst; + wire peripherals_aw_bits_lock; + wire [3:0] peripherals_aw_bits_cache; + wire [2:0] peripherals_aw_bits_prot; + wire [3:0] peripherals_aw_bits_qos; + wire peripherals_w_ready; + wire peripherals_w_valid; + wire [63:0] peripherals_w_bits_data; + wire [7:0] peripherals_w_bits_strb; + wire peripherals_w_bits_last; + wire peripherals_b_ready; + wire peripherals_b_valid; + wire [1:0] peripherals_b_bits_id; + wire [1:0] peripherals_b_bits_resp; + wire peripherals_ar_ready; + wire peripherals_ar_valid; + wire [1:0] peripherals_ar_bits_id; + wire [30:0] peripherals_ar_bits_addr; + wire [7:0] peripherals_ar_bits_len; + wire [2:0] peripherals_ar_bits_size; + wire [1:0] peripherals_ar_bits_burst; + wire peripherals_ar_bits_lock; + wire [3:0] peripherals_ar_bits_cache; + wire [2:0] peripherals_ar_bits_prot; + wire [3:0] peripherals_ar_bits_qos; + wire peripherals_r_ready; + wire peripherals_r_valid; + wire [1:0] peripherals_r_bits_id; + wire [63:0] peripherals_r_bits_data; + wire [1:0] peripherals_r_bits_resp; + wire peripherals_r_bits_last; + ToyLinuxChip dut(.*); + integer cycle_count=0; + always @(posedge clock) if (!reset) cycle_count<=cycle_count+1; + always #5 clock=~clock; + initial begin reset=1; repeat(20) @(negedge clock); reset=0; end + initial begin repeat(5000000) @(posedge clock); $fatal(1,"CPU timeout"); end + axi_smoke_memory #(.DATA_BITS(128), .ID_BITS(4), .ADDR_BITS(32), .BASE(32'h80000000), .CAPACITY(262144), .IMAGE("smoke.hex")) memory_model ( + .clock(clock), + .reset(reset), + .aw_ready(memory_aw_ready), + .aw_valid(memory_aw_valid), + .aw_bits_id(memory_aw_bits_id), + .aw_bits_addr(memory_aw_bits_addr), + .aw_bits_len(memory_aw_bits_len), + .aw_bits_size(memory_aw_bits_size), + .aw_bits_burst(memory_aw_bits_burst), + .w_ready(memory_w_ready), + .w_valid(memory_w_valid), + .w_bits_data(memory_w_bits_data), + .w_bits_strb(memory_w_bits_strb), + .w_bits_last(memory_w_bits_last), + .b_ready(memory_b_ready), + .b_valid(memory_b_valid), + .b_bits_id(memory_b_bits_id), + .b_bits_resp(memory_b_bits_resp), + .ar_ready(memory_ar_ready), + .ar_valid(memory_ar_valid), + .ar_bits_id(memory_ar_bits_id), + .ar_bits_addr(memory_ar_bits_addr), + .ar_bits_len(memory_ar_bits_len), + .ar_bits_size(memory_ar_bits_size), + .ar_bits_burst(memory_ar_bits_burst), + .r_ready(memory_r_ready), + .r_valid(memory_r_valid), + .r_bits_id(memory_r_bits_id), + .r_bits_data(memory_r_bits_data), + .r_bits_resp(memory_r_bits_resp), + .r_bits_last(memory_r_bits_last) + ); + axi_smoke_memory #(.DATA_BITS(64), .ID_BITS(2), .ADDR_BITS(31), .BASE(32'h60000000), .CAPACITY(4096), .MONITOR(1), .TEST_LABEL("whole Toy 40 alternating multi tile OS WS loops")) peripherals_model ( + .clock(clock), + .reset(reset), + .aw_ready(peripherals_aw_ready), + .aw_valid(peripherals_aw_valid), + .aw_bits_id(peripherals_aw_bits_id), + .aw_bits_addr(peripherals_aw_bits_addr), + .aw_bits_len(peripherals_aw_bits_len), + .aw_bits_size(peripherals_aw_bits_size), + .aw_bits_burst(peripherals_aw_bits_burst), + .w_ready(peripherals_w_ready), + .w_valid(peripherals_w_valid), + .w_bits_data(peripherals_w_bits_data), + .w_bits_strb(peripherals_w_bits_strb), + .w_bits_last(peripherals_w_bits_last), + .b_ready(peripherals_b_ready), + .b_valid(peripherals_b_valid), + .b_bits_id(peripherals_b_bits_id), + .b_bits_resp(peripherals_b_bits_resp), + .ar_ready(peripherals_ar_ready), + .ar_valid(peripherals_ar_valid), + .ar_bits_id(peripherals_ar_bits_id), + .ar_bits_addr(peripherals_ar_bits_addr), + .ar_bits_len(peripherals_ar_bits_len), + .ar_bits_size(peripherals_ar_bits_size), + .ar_bits_burst(peripherals_ar_bits_burst), + .r_ready(peripherals_r_ready), + .r_valid(peripherals_r_valid), + .r_bits_id(peripherals_r_bits_id), + .r_bits_data(peripherals_r_bits_data), + .r_bits_resp(peripherals_r_bits_resp), + .r_bits_last(peripherals_r_bits_last) + ); + final $display("MEASURE cycles=%0d memory_reads=%0d memory_writes=%0d", cycle_count, memory_model.read_bursts, memory_model.write_bursts); +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/loop-stress/simulation/verilator-build.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/loop-stress/simulation/verilator-build.log new file mode 100644 index 0000000..94f0c39 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/loop-stress/simulation/verilator-build.log @@ -0,0 +1,2123 @@ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 31 | module NonSyncResetSynchronizerPrimitiveShiftReg_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ + ... For warning description see https://verilator.org/warn/TIMESCALEMOD?v=5.050 + ... Use "/* verilator lint_off TIMESCALEMOD */" and lint_on around source to disable this message. +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:48:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 48 | module SynchronizerShiftReg_w1_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:61:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 61 | module IntSyncAsyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:74:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 74 | module AsyncResetRegVec_w1_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 103 | module IntSyncCrossingSource_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:118:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 118 | module FixedClockBroadcast_3( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:139:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 139 | module TLMonitor( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:987:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 987 | module TLMonitor_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:2434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 2434 | module TLXbar_sbus_i2_o3_a32d128s3k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:3195:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3195 | module TLMonitor_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4151 | module Repeater_TLBundleA_a28d128s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4218 | module TLWidthWidget16( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4386 | module TLInterconnectCoupler_sbus_to_bus_named_cbus( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4478:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4478 | module ram_2x58( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4497:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4497 | module Queue2_AXI4BundleAW( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4581:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4581 | module ram_2x73( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4600:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4600 | module Queue2_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4657:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4657 | module ram_2x4( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4676:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4676 | module Queue2_AXI4BundleB( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4729:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4729 | module Queue2_AXI4BundleAR( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4813:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4813 | module ram_2x69( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4832:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4832 | module Queue2_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4891:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4891 | module AXI4Buffer( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5067:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5067 | module ram_2x8( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5086:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5086 | module Queue2_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5143:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5143 | module Queue1_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5178 | module AXI4UserYanker( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5540:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5540 | module ram_8x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5559:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5559 | module Queue8_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5631 | module AXI4Deinterleaver( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:6073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6073 | module AXI4IdIndexer( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:6219:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6219 | module TLMonitor_3( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7048:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7048 | module Queue1_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7082:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7082 | module Queue1_AXI4BundleARW( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7148:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7148 | module TLToAXI4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7529:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7529 | module TLMonitor_4( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8396:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8396 | module Repeater_TLBundleA_a31d128s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8463 | module TLWidthWidget16_2( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8623:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8623 | module TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:9400:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 9400 | module SystemBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10050 | module FixedClockBroadcast_4( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10073 | module TLMonitor_5( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10975:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10975 | module TLXbar_cbus_out_i1_o4_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:11288:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +11288 | module TLMonitor_6( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12202:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12202 | module ram_2x114( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12221 | module Queue2_TLBundleA_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12301 | module ram_2x79( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12320:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12320 | module Queue2_TLBundleD_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12399:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12399 | module TLBuffer_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12534:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12534 | module TLMonitor_7( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:13449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13449 | module TLAtomicAutomata_cbus( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:13973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13973 | module TLMonitor_8( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14799 | module Queue1_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14846:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14846 | module TLError( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14953 | module TLMonitor_9( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15857 | module ram_2x100( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15876:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15876 | module Queue2_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15955:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15955 | module Queue2_TLBundleD_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16028 | module TLBuffer_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16155 | module ErrorDeviceWrapper( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16258 | module TLMonitor_10( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17017:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17017 | module Repeater_TLBundleA_a26d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17081:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17081 | module TLFragmenter_CLINT( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17261:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17261 | module TLInterconnectCoupler_cbus_to_clint( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17336:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17336 | module TLMonitor_11( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18106:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18106 | module Repeater_TLBundleA_a28d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18170:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18170 | module TLFragmenter_PLIC( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18350 | module TLInterconnectCoupler_cbus_to_plic( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18425:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18425 | module TLMonitor_12( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19040 | module Repeater_TLBundleA_a17d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19104:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19104 | module TLFragmenter_bootrom( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19263:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19263 | module TLInterconnectCoupler_cbus_to_bootrom( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19330:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19330 | module PeripheryBus_cbus( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19882 | module TLMonitor_13( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20610:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20610 | module ProbePicker( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20688:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20688 | module ram_2x10( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20707:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20707 | module Queue2_BundleMap_6( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20764:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20764 | module AXI4UserYanker_1( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:21713:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21713 | module AXI4IdIndexer_1( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:21859:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21859 | module TLMonitor_14( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22587:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22587 | module Queue1_AXI4BundleW_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22621 | module Queue1_AXI4BundleARW_1( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22687:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22687 | module TLToAXI4_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:23555:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +23555 | module TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:24031:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24031 | module MemoryBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:24349:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24349 | module TLMonitor_15( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25732:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25732 | module BroadcastFilter( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25756:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25756 | module ram_4x144( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25775:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25775 | module Queue4_TLBroadcastData( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25828:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25828 | module TLBroadcastTracker( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25964:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25964 | module TLBroadcastTracker_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:26100:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26100 | module TLBroadcast( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:26686:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26686 | module TLMonitor_16( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27414 | module BankBinder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27491:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27491 | module CoherenceManagerWrapper( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27669:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27669 | module TLMonitor_17( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29229:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29229 | module TLMonitor_18( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29635:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29635 | module TLXbar_MasterXbar_BBTile_i2_o1_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29898 | module IntXbar_i4_o1( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29918:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29918 | module WritebackUnit( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30014:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30014 | module ProbeUnit( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30154:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30154 | module Arbiter1_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30168:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30168 | module Arbiter1_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30191 | module Arbiter1_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30214 | module Arbiter1_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30249:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30249 | module Arbiter1_Bool( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30258 | module ram_16x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30277:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30277 | module Queue16_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30360:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30360 | module Queue1_TLBundleE_a32d128s1k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30388:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30388 | module MSHR( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30835:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30835 | module Arbiter1_HellaCacheResp( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30879:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30879 | module IOMSHR( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31790:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31790 | module sdq_17x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31809 | module MSHRFile( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32350 | module OptimizationBarrier_TLBEntryData( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32406:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32406 | module PMPChecker_s3( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32691:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32691 | module PMAChecker( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32731:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32731 | module DTLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:35923:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35923 | module L1MetadataArray( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:35990:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35990 | module Arbiter5_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36023:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36023 | module Arbiter2_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36055 | module DataArray( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36151 | module Arbiter4_L1DataReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36180:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36180 | module Arbiter2_L1DataWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36206:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36206 | module AMOALU( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36248:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36248 | module MaxPeriodFibonacciLFSR( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36342:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36342 | module Arbiter2_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36377:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36377 | module NonBlockingDCache( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:37660:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37660 | module ICache( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:37914:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37914 | module ShiftQueue( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:38054:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38054 | module PMPChecker_s2( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:38215:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38215 | module ITLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:41129:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41129 | module Frontend( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:41494:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41494 | module TLMonitor_19( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:42301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +42301 | module TLMonitor_20( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43108:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43108 | module TLXbar_i2_o1_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43343 | module TLMonitor_21( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43851:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43851 | module ram_2x116( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43870:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43870 | module Queue2_TLBundleA_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43947:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43947 | module ram_2x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43966:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43966 | module Queue2_TLBundleD_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44045:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44045 | module TLBuffer_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44158:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44158 | module TLMonitor_22( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44783 | module TLBuffer_a32d64s1k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44892:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44892 | module TLMonitor_23( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:45699:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45699 | module Repeater_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:45766:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45766 | module TLWidthWidget8_4( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46074:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46074 | module TLMonitor_24( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46882 | module ram_2x117( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46901:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46901 | module Queue2_TLBundleA_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46981:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46981 | module ram_2x78( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47000:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47000 | module Queue2_TLBundleD_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47079:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47079 | module TLBuffer_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47214 | module HellaCacheArbiter( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47381 | module Arbiter3_Valid_PTWReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47419:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47419 | module OptimizationBarrier_UInt( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47427 | module OptimizationBarrier_PTE( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47459 | module PTW( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:48434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +48434 | module FPUDecoder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49794:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49794 | module CompareRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49824:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49824 | module RecFNToIN_e11_s53_i64( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49873:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49873 | module RecFNToIN_e11_s53_i32( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49912:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49912 | module FPToInt( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50375:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50375 | module RoundAnyRawFNToRecFN_ie7_is64_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50410:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50410 | module PipelinedINToRecFN( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50513:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50513 | module RoundAnyRawFNToRecFN_ie7_is64_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50539 | module PipelinedINToRecFN_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50614 | module RoundAnyRawFNToRecFN_ie7_is64_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50642:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50642 | module PipelinedINToRecFN_2( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50717 | module IntToFP( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51072:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51072 | module RoundAnyRawFNToRecFN_ie11_is53_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51199:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51199 | module RecFNToRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51221 | module RoundAnyRawFNToRecFN_ie11_is53_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51321:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51321 | module RecFNToRecFN_1( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51343 | module FPToFP( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51469:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51469 | module MulAddRecFNToRaw_preMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51569 | module MulAddRecFNToRaw_postMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51822:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51822 | module RoundAnyRawFNToRecFN_ie11_is55_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51953 | module RoundAnyRawFNToRecFN_ie11_is55_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52060:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52060 | module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52194:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52194 | module SharedMulAddRecFNPipe( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52551:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52551 | module FPUSharedFMAPipe( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52682:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52682 | module DivSqrtRawFN_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52852:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52852 | module DivSqrtRecFMToRaw_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52907:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52907 | module RoundAnyRawFNToRecFN_ie5_is13_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53039:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53039 | module RoundRawFNToRecFN_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53068:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53068 | module DivSqrtRecFM_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53128:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53128 | module DivSqrtRawFN_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53297:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53297 | module DivSqrtRecFMToRaw_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53352:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53352 | module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53456:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53456 | module RoundRawFNToRecFN_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53485:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53485 | module DivSqrtRecFM_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53545:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53545 | module DivSqrtRawFN_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53715:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53715 | module DivSqrtRecFMToRaw_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53770:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53770 | module RoundRawFNToRecFN_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53799 | module DivSqrtRecFM_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53860:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53860 | module regfile_32x65( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53905:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53905 | module FPU( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:54820:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +54820 | module RVCExpander( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:55183:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55183 | module IBuf( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:55307:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55307 | module CSRFile( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:57223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57223 | module RocketALU( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:57809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57809 | module MulDiv( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:58107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58107 | module Arbiter3_LLWB( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:58125:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58125 | module rf_31x64( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:58149:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58149 | module RocketBB( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62838:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62838 | module GlobalDecoder( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62928:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62928 | module BankAliasTable( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:64252:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64252 | module BankScoreboard( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:64627:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64627 | module GlobalROB( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68674:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68674 | module Arbiter3_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68717 | module ram_16x4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68736:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68736 | module Queue16_UInt4( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68782:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68782 | module SubROB( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:69357:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69357 | module Arbiter1_SubRobRow( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:69722:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69722 | module GlobalScheduler( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:70973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +70973 | module BootRom( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:71013:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71013 | module Frontend_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:71637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71637 | module PE( + | ^~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:71656:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71656 | module AlwaysOutTransposer( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72411:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72411 | module MacUnit( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72426:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72426 | module PE_64( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72524:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72524 | module Tile( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72571:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72571 | module Mesh( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76050 | module TagQueue( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76191 | module ram_6x7( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76210:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76210 | module Queue6_TagWithIdAndTotalRows( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76271:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76271 | module MeshWithDelays( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77318:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77318 | module ram_data_8x64( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77337 | module Queue8_SramReadResp( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77385:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77385 | module GemminiExCtrl( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79354:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79354 | module LoopMatmulUnroller( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79637 | module LoopConvAddrGen( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79690:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79690 | module LoopConvUnroller( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:80113:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80113 | module LoopCmdEncoder( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:80402:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80402 | module Arbiter2_LoopCmd( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:80598:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80598 | module GemminiBall( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:81783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81783 | module RRArbiter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:81857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81857 | module CmdRouter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:81985:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81985 | module BallCyclePMC( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:82095:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82095 | module BBus( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:82898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82898 | module BallDomainDecoder( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83028 | module ram_4x281( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83047:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83047 | module Queue4_BallReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83178 | module Arbiter1_BallRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83198:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83198 | module BallReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83328:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83328 | module BallDomain( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84141:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84141 | module MemDomainDecoder( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84300:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84300 | module ram_4x158( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84319:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84319 | module Queue4_MemReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84421:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84421 | module Arbiter3_MemRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84463 | module MemReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84631 | module MemLoader( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84869:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84869 | module MemStorer( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85122:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85122 | module MemCyclePMC( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85241:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85241 | module TLB( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85621 | module RRArbiter_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85649:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85649 | module BBTLBCluster( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85777 | module StreamReader( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86142:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86142 | module StreamWriter( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86223 | module ZeroLineGenerator( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86264:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86264 | module MemConfiger( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86433:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86433 | module RRArbiter_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86465:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86465 | module MemGroupQueryArbiter( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86543:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86543 | module MemFrontend( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87160 | module MemMidend( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87621 | module SramBank( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87672:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87672 | module AccPipe( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87781 | module PrivateMemBackend( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:90777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +90777 | module MemBackend( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:91055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91055 | module MemDomain( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:91973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91973 | module Queue1_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92008:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92008 | module GpDomain( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92040 | module ram_8x21( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92059 | module Queue8_BuckyballAccelerator_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92123:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92123 | module BuckyballAccelerator( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93569 | module Queue3_UInt2( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93614 | module SimpleHellaCacheIFReplayQueue( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93667:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93667 | module Arbiter2_HellaCacheReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93678:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93678 | module SimpleHellaCacheIF( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93768:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93768 | module BarrierUnit( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93785:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93785 | module BBTile( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:95579:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +95579 | module TLMonitor_25( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:96427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +96427 | module TLMonitor_26( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98184:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98184 | module ram_2x189( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98203:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98203 | module Queue2_TLBundleA_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98283:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98283 | module ram_2x142( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98302:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98302 | module Queue2_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98381 | module Queue2_TLBundleA_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98459 | module Queue2_TLBundleD_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98539 | module ram_2x60( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98558:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98558 | module Queue2_TLBundleB_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98622:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98622 | module ram_2x173( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98641:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98641 | module Queue2_TLBundleC_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98716:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98716 | module ram_sink_2x1( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98735:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98735 | module Queue2_TLBundleE_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98781 | module TLBuffer_a32d128s2k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99162:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99162 | module IntSyncSyncCrossingSink_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99173:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99173 | module IntSyncSyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99181:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99181 | module TilePRCIDomain( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99589:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99589 | module BundleBridgeNexus_UInt1_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99597:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99597 | module TLMonitor_27( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100216:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100216 | module CLINT( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100337 | module AsyncResetRegVec_w2_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100366:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100366 | module IntSyncCrossingSource_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100386 | module CLINTClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100449 | module TLMonitor_28( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101080:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101080 | module LevelGateway( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101099:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101099 | module PLICFanIn( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101111:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101111 | module Queue1_RegMapperInput_i23_m8( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101160 | module TLPLIC( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101389:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101389 | module PLICClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101452:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101452 | module TLMonitor_29( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101973 | module TLROM( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:102530:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102530 | module bootromClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:102569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102569 | module ToyLinuxSystem( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103817:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103817 | module ToyLinuxChip( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103984:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103984 | module tag_array( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104007:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104007 | module array_0_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104034:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104034 | module array_0_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104059 | module array_2_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104084:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104084 | module array_2_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104109:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104109 | module bbtile_icache_tag_array( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104132:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104132 | module bbtile_icache_data_arrays_0( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104155 | module bbtile_icache_data_arrays_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104176:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104176 | module bbtile_icache_data_arrays_2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104197:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104197 | module bbtile_icache_data_arrays_3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104218 | module robOperands( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104243:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104243 | module sram( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104268:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104268 | module mem( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104301 | module plusarg_reader #( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104326:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104326 | module ITraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104404:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104404 | module FpgaDspMac(input [7:0] a, b, input [19:0] c, output [19:0] y); + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104414 | module PMCTraceDPI( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104464:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104464 | module MemPMCTraceDPI( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104514:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104514 | module MTraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:1:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 1 | module tag_array_ext( input [4:0] RW0_addr, + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 19 | module array_0_0_ext( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:37:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 37 | module bbtile_icache_tag_array_ext( input [5:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:55:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 55 | module bbtile_icache_data_arrays_0_ext( input [7:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:73:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 73 | module robOperands_ext( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:90:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 90 | module sram_ext( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 107 | module mem_ext( input [9:0] RW0_addr, + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:3:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3 | module axi_smoke_memory #( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:52:20: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'addr' generates 31 bits. + : ... note: In instance 'tb.peripherals_model' + 52 | offset=(addr & ~(LANES-1))-BASE; + | ^ + ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=5.050 + ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:78:28: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'write_addr' generates 31 bits. + : ... note: In instance 'tb.peripherals_model' + 78 | offset=(write_addr & ~(LANES-1))-BASE; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:86:26: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'h600d600d' generates 64 bits. + : ... note: In instance 'tb.memory_model' + 86 | if (w_bits_data==64'h600d600d) begin + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:91:66: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff' generates 64 bits. + : ... note: In instance 'tb.memory_model' + 91 | $fatal(1,"CPU smoke failed at stage %0d",w_bits_data & 64'hffff); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:90:28: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff0000' generates 64 bits. + : ... note: In instance 'tb.memory_model' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:90:43: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'hbad00000' generates 64 bits. + : ... note: In instance 'tb.memory_model' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^~ +make: Entering directory '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/obj' +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_timing.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_timing.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_threads.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_threads.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb__pch.h -o Vtb__pch.h.fast.gch +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb__pch.h -o Vtb__pch.h.slow.gch +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__0.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__1.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__2.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__3.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__4.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__5.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__6.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__7.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__8.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__9.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb__main.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb__ConstPool__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__1__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__2__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__3__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb__Syms__Slow.cpp +g++ verilated.o verilated_timing.o verilated_threads.o Vtb__ALL.a -pthread -lpthread -latomic -o Vtb +rm Vtb__ALL.verilator_deplist.tmp +make: Leaving directory '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/loop-stress/simulation/obj' +- V e r i l a t i o n R e p o r t: Verilator 5.050 2026-07-01 rev v5.050 +- Verilator: Built from 15.468 MB sources in 346 modules, into 23.746 MB in 19 C++ files needing 0.019 MB +- Verilator: Walltime 12.980 s (elab=0.523, cvt=3.179, bld=8.691); cpu 4.550 s on 8 threads; allocated 561.762 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/mmio-old-counterexample/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/mmio-old-counterexample/RESULT.json new file mode 100644 index 0000000..bfa8512 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/mmio-old-counterexample/RESULT.json @@ -0,0 +1,6 @@ +{ + "result": "FAILED", + "physical_hardware_tested": false, + "error_type": "CalledProcessError", + "error": "Command '['/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/obj/Vtb_mmio_error']' returned non-zero exit status 1." +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/mmio-old-counterexample/compile.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/mmio-old-counterexample/compile.log new file mode 100644 index 0000000..f9db9d3 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/mmio-old-counterexample/compile.log @@ -0,0 +1,2201 @@ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 31 | module NonSyncResetSynchronizerPrimitiveShiftReg_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ + ... For warning description see https://verilator.org/warn/TIMESCALEMOD?v=5.050 + ... Use "/* verilator lint_off TIMESCALEMOD */" and lint_on around source to disable this message. +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:48:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 48 | module SynchronizerShiftReg_w1_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:61:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 61 | module IntSyncAsyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:74:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 74 | module AsyncResetRegVec_w1_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 103 | module IntSyncCrossingSource_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:118:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 118 | module FixedClockBroadcast_3( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:139:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 139 | module TLMonitor( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:987:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 987 | module TLMonitor_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:2434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 2434 | module TLXbar_sbus_i2_o3_a32d128s3k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:3195:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3195 | module TLMonitor_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4151 | module Repeater_TLBundleA_a28d128s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4218 | module TLWidthWidget16( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4386 | module TLInterconnectCoupler_sbus_to_bus_named_cbus( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4478:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4478 | module ram_2x58( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4497:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4497 | module Queue2_AXI4BundleAW( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4581:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4581 | module ram_2x73( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4600:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4600 | module Queue2_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4657:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4657 | module ram_2x4( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4676:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4676 | module Queue2_AXI4BundleB( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4729:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4729 | module Queue2_AXI4BundleAR( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4813:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4813 | module ram_2x69( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4832:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4832 | module Queue2_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4891:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4891 | module AXI4Buffer( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5067:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5067 | module ram_2x8( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5086:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5086 | module Queue2_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5143:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5143 | module Queue1_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5178 | module AXI4UserYanker( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5540:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5540 | module ram_8x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5559:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5559 | module Queue8_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5631 | module AXI4Deinterleaver( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:6073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6073 | module AXI4IdIndexer( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:6219:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6219 | module TLMonitor_3( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7048:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7048 | module Queue1_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7082:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7082 | module Queue1_AXI4BundleARW( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7148:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7148 | module TLToAXI4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7529:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7529 | module TLMonitor_4( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8396:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8396 | module Repeater_TLBundleA_a31d128s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8463 | module TLWidthWidget16_2( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8623:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8623 | module TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:9400:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 9400 | module SystemBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10050 | module FixedClockBroadcast_4( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10073 | module TLMonitor_5( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10975:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10975 | module TLXbar_cbus_out_i1_o4_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:11288:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +11288 | module TLMonitor_6( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12202:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12202 | module ram_2x114( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12221 | module Queue2_TLBundleA_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12301 | module ram_2x79( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12320:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12320 | module Queue2_TLBundleD_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12399:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12399 | module TLBuffer_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12534:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12534 | module TLMonitor_7( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:13449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13449 | module TLAtomicAutomata_cbus( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:13973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13973 | module TLMonitor_8( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14799 | module Queue1_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14846:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14846 | module TLError( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14953 | module TLMonitor_9( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15857 | module ram_2x100( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15876:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15876 | module Queue2_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15955:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15955 | module Queue2_TLBundleD_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16028 | module TLBuffer_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16155 | module ErrorDeviceWrapper( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16258 | module TLMonitor_10( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17017:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17017 | module Repeater_TLBundleA_a26d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17081:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17081 | module TLFragmenter_CLINT( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17261:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17261 | module TLInterconnectCoupler_cbus_to_clint( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17336:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17336 | module TLMonitor_11( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18106:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18106 | module Repeater_TLBundleA_a28d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18170:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18170 | module TLFragmenter_PLIC( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18350 | module TLInterconnectCoupler_cbus_to_plic( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18425:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18425 | module TLMonitor_12( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19040 | module Repeater_TLBundleA_a17d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19104:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19104 | module TLFragmenter_bootrom( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19263:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19263 | module TLInterconnectCoupler_cbus_to_bootrom( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19330:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19330 | module PeripheryBus_cbus( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19882 | module TLMonitor_13( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20610:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20610 | module ProbePicker( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20688:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20688 | module ram_2x10( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20707:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20707 | module Queue2_BundleMap_6( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20764:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20764 | module AXI4UserYanker_1( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:21713:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21713 | module AXI4IdIndexer_1( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:21859:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21859 | module TLMonitor_14( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22587:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22587 | module Queue1_AXI4BundleW_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22621 | module Queue1_AXI4BundleARW_1( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22687:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22687 | module TLToAXI4_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:23555:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +23555 | module TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:24031:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24031 | module MemoryBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:24349:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24349 | module TLMonitor_15( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25732:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25732 | module BroadcastFilter( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25756:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25756 | module ram_4x144( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25775:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25775 | module Queue4_TLBroadcastData( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25828:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25828 | module TLBroadcastTracker( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25964:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25964 | module TLBroadcastTracker_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:26100:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26100 | module TLBroadcast( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:26686:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26686 | module TLMonitor_16( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27414 | module BankBinder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27491:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27491 | module CoherenceManagerWrapper( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27669:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27669 | module TLMonitor_17( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29229:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29229 | module TLMonitor_18( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29635:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29635 | module TLXbar_MasterXbar_BBTile_i2_o1_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29898 | module IntXbar_i4_o1( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29918:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29918 | module WritebackUnit( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30014:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30014 | module ProbeUnit( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30154:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30154 | module Arbiter1_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30168:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30168 | module Arbiter1_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30191 | module Arbiter1_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30214 | module Arbiter1_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30249:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30249 | module Arbiter1_Bool( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30258 | module ram_16x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30277:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30277 | module Queue16_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30360:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30360 | module Queue1_TLBundleE_a32d128s1k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30388:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30388 | module MSHR( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30835:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30835 | module Arbiter1_HellaCacheResp( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30879:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30879 | module IOMSHR( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31790:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31790 | module sdq_17x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31809 | module MSHRFile( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32350 | module OptimizationBarrier_TLBEntryData( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32406:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32406 | module PMPChecker_s3( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32691:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32691 | module PMAChecker( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32731:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32731 | module DTLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:35923:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35923 | module L1MetadataArray( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:35990:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35990 | module Arbiter5_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36023:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36023 | module Arbiter2_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36055 | module DataArray( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36151 | module Arbiter4_L1DataReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36180:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36180 | module Arbiter2_L1DataWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36206:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36206 | module AMOALU( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36248:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36248 | module MaxPeriodFibonacciLFSR( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36342:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36342 | module Arbiter2_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36377:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36377 | module NonBlockingDCache( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:37660:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37660 | module ICache( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:37914:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37914 | module ShiftQueue( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:38054:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38054 | module PMPChecker_s2( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:38215:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38215 | module ITLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:41129:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41129 | module Frontend( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:41494:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41494 | module TLMonitor_19( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:42301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +42301 | module TLMonitor_20( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43108:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43108 | module TLXbar_i2_o1_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43343 | module TLMonitor_21( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43851:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43851 | module ram_2x116( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43870:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43870 | module Queue2_TLBundleA_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43947:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43947 | module ram_2x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43966:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43966 | module Queue2_TLBundleD_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44045:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44045 | module TLBuffer_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44158:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44158 | module TLMonitor_22( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44783 | module TLBuffer_a32d64s1k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44892:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44892 | module TLMonitor_23( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:45699:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45699 | module Repeater_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:45766:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45766 | module TLWidthWidget8_4( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46074:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46074 | module TLMonitor_24( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46882 | module ram_2x117( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46901:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46901 | module Queue2_TLBundleA_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46981:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46981 | module ram_2x78( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47000:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47000 | module Queue2_TLBundleD_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47079:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47079 | module TLBuffer_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47214 | module HellaCacheArbiter( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47381 | module Arbiter3_Valid_PTWReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47419:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47419 | module OptimizationBarrier_UInt( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47427 | module OptimizationBarrier_PTE( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47459 | module PTW( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:48434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +48434 | module FPUDecoder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49794:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49794 | module CompareRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49824:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49824 | module RecFNToIN_e11_s53_i64( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49873:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49873 | module RecFNToIN_e11_s53_i32( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49912:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49912 | module FPToInt( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50375:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50375 | module RoundAnyRawFNToRecFN_ie7_is64_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50410:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50410 | module PipelinedINToRecFN( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50513:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50513 | module RoundAnyRawFNToRecFN_ie7_is64_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50539 | module PipelinedINToRecFN_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50614 | module RoundAnyRawFNToRecFN_ie7_is64_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50642:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50642 | module PipelinedINToRecFN_2( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50717 | module IntToFP( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51072:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51072 | module RoundAnyRawFNToRecFN_ie11_is53_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51199:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51199 | module RecFNToRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51221 | module RoundAnyRawFNToRecFN_ie11_is53_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51321:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51321 | module RecFNToRecFN_1( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51343 | module FPToFP( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51469:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51469 | module MulAddRecFNToRaw_preMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51569 | module MulAddRecFNToRaw_postMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51822:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51822 | module RoundAnyRawFNToRecFN_ie11_is55_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51953 | module RoundAnyRawFNToRecFN_ie11_is55_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52060:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52060 | module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52194:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52194 | module SharedMulAddRecFNPipe( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52551:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52551 | module FPUSharedFMAPipe( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52682:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52682 | module DivSqrtRawFN_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52852:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52852 | module DivSqrtRecFMToRaw_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52907:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52907 | module RoundAnyRawFNToRecFN_ie5_is13_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53039:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53039 | module RoundRawFNToRecFN_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53068:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53068 | module DivSqrtRecFM_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53128:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53128 | module DivSqrtRawFN_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53297:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53297 | module DivSqrtRecFMToRaw_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53352:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53352 | module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53456:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53456 | module RoundRawFNToRecFN_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53485:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53485 | module DivSqrtRecFM_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53545:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53545 | module DivSqrtRawFN_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53715:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53715 | module DivSqrtRecFMToRaw_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53770:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53770 | module RoundRawFNToRecFN_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53799 | module DivSqrtRecFM_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53860:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53860 | module regfile_32x65( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53905:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53905 | module FPU( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:54820:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +54820 | module RVCExpander( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:55183:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55183 | module IBuf( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:55307:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55307 | module CSRFile( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:57223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57223 | module RocketALU( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:57809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57809 | module MulDiv( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:58107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58107 | module Arbiter3_LLWB( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:58125:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58125 | module rf_31x64( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:58149:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58149 | module RocketBB( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62838:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62838 | module GlobalDecoder( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62928:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62928 | module BankAliasTable( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:64252:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64252 | module BankScoreboard( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:64627:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64627 | module GlobalROB( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68674:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68674 | module Arbiter3_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68717 | module ram_16x4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68736:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68736 | module Queue16_UInt4( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68782:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68782 | module SubROB( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:69357:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69357 | module Arbiter1_SubRobRow( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:69722:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69722 | module GlobalScheduler( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:70973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +70973 | module BootRom( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:71013:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71013 | module Frontend_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:71637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71637 | module PE( + | ^~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:71656:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71656 | module AlwaysOutTransposer( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72411:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72411 | module MacUnit( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72426:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72426 | module PE_64( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72524:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72524 | module Tile( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72571:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72571 | module Mesh( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76050 | module TagQueue( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76191 | module ram_6x7( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76210:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76210 | module Queue6_TagWithIdAndTotalRows( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76271:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76271 | module MeshWithDelays( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77318:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77318 | module ram_data_8x64( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77337 | module Queue8_SramReadResp( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77385:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77385 | module GemminiExCtrl( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79354:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79354 | module LoopMatmulUnroller( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79637 | module LoopConvAddrGen( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79690:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79690 | module LoopConvUnroller( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:80113:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80113 | module LoopCmdEncoder( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:80402:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80402 | module Arbiter2_LoopCmd( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:80598:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80598 | module GemminiBall( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:81783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81783 | module RRArbiter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:81857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81857 | module CmdRouter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:81985:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81985 | module BallCyclePMC( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:82095:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82095 | module BBus( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:82898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82898 | module BallDomainDecoder( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83028 | module ram_4x281( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83047:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83047 | module Queue4_BallReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83178 | module Arbiter1_BallRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83198:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83198 | module BallReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83328:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83328 | module BallDomain( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84141:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84141 | module MemDomainDecoder( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84300:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84300 | module ram_4x158( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84319:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84319 | module Queue4_MemReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84421:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84421 | module Arbiter3_MemRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84463 | module MemReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84631 | module MemLoader( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84869:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84869 | module MemStorer( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85122:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85122 | module MemCyclePMC( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85241:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85241 | module TLB( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85621 | module RRArbiter_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85649:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85649 | module BBTLBCluster( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85777 | module StreamReader( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86142:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86142 | module StreamWriter( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86223 | module ZeroLineGenerator( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86264:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86264 | module MemConfiger( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86433:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86433 | module RRArbiter_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86465:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86465 | module MemGroupQueryArbiter( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86543:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86543 | module MemFrontend( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87160 | module MemMidend( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87621 | module SramBank( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87672:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87672 | module AccPipe( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87781 | module PrivateMemBackend( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:90777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +90777 | module MemBackend( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:91055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91055 | module MemDomain( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:91973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91973 | module Queue1_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92008:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92008 | module GpDomain( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92040 | module ram_8x21( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92059 | module Queue8_BuckyballAccelerator_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92123:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92123 | module BuckyballAccelerator( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93569 | module Queue3_UInt2( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93614 | module SimpleHellaCacheIFReplayQueue( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93667:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93667 | module Arbiter2_HellaCacheReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93678:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93678 | module SimpleHellaCacheIF( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93768:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93768 | module BarrierUnit( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93785:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93785 | module BBTile( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:95579:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +95579 | module TLMonitor_25( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:96427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +96427 | module TLMonitor_26( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98184:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98184 | module ram_2x189( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98203:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98203 | module Queue2_TLBundleA_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98283:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98283 | module ram_2x142( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98302:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98302 | module Queue2_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98381 | module Queue2_TLBundleA_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98459 | module Queue2_TLBundleD_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98539 | module ram_2x60( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98558:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98558 | module Queue2_TLBundleB_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98622:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98622 | module ram_2x173( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98641:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98641 | module Queue2_TLBundleC_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98716:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98716 | module ram_sink_2x1( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98735:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98735 | module Queue2_TLBundleE_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98781 | module TLBuffer_a32d128s2k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99162:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99162 | module IntSyncSyncCrossingSink_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99173:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99173 | module IntSyncSyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99181:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99181 | module TilePRCIDomain( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99589:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99589 | module BundleBridgeNexus_UInt1_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99597:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99597 | module TLMonitor_27( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100216:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100216 | module CLINT( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100337 | module AsyncResetRegVec_w2_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100366:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100366 | module IntSyncCrossingSource_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100386 | module CLINTClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100449 | module TLMonitor_28( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101080:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101080 | module LevelGateway( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101099:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101099 | module PLICFanIn( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101111:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101111 | module Queue1_RegMapperInput_i23_m8( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101160 | module TLPLIC( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101389:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101389 | module PLICClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101452:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101452 | module TLMonitor_29( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101973 | module TLROM( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:102530:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102530 | module bootromClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:102569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102569 | module ToyLinuxSystem( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103817:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103817 | module ToyLinuxChip( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103984:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103984 | module tag_array( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104007:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104007 | module array_0_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104034:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104034 | module array_0_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104059 | module array_2_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104084:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104084 | module array_2_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104109:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104109 | module bbtile_icache_tag_array( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104132:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104132 | module bbtile_icache_data_arrays_0( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104155 | module bbtile_icache_data_arrays_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104176:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104176 | module bbtile_icache_data_arrays_2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104197:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104197 | module bbtile_icache_data_arrays_3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104218 | module robOperands( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104243:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104243 | module sram( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104268:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104268 | module mem( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104301 | module plusarg_reader #( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104326:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104326 | module ITraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104404:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104404 | module FpgaDspMac(input [7:0] a, b, input [19:0] c, output [19:0] y); + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104414 | module PMCTraceDPI( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104464:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104464 | module MemPMCTraceDPI( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104514:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104514 | module MTraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:1:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 1 | module tag_array_ext( input [4:0] RW0_addr, + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 19 | module array_0_0_ext( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:37:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 37 | module bbtile_icache_tag_array_ext( input [5:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:55:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 55 | module bbtile_icache_data_arrays_0_ext( input [7:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:73:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 73 | module robOperands_ext( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:90:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 90 | module sram_ext( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 107 | module mem_ext( input [9:0] RW0_addr, + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:3:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3 | module axi_smoke_memory #( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:2:8: ... Location of module with timescale + 2 | module tb_mmio_error; + | ^~~~~~~~~~~~~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_tx.sv:27:15: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_mmio_error.platform.transmitter' + 27 | count <= DIVISOR - 1; + | ^~ + ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=5.050 + ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_tx.sv:32:13: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_mmio_error.platform.transmitter' + 32 | count <= DIVISOR - 1; + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_rx.sv:23:55: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_mmio_error.platform.receiver' + 23 | IDLE: if (!rx_sync) begin state <= START; count <= DIVISOR/2 - 1; end + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_rx.sv:26:57: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_mmio_error.platform.receiver' + 26 | else begin state <= DATA; bit_index <= 0; count <= DIVISOR - 1; end + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/uart_rx.sv:29:46: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_mmio_error.platform.receiver' + 29 | shift[bit_index] <= rx_sync; count <= DIVISOR - 1; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:32:43: Operator ADD expects 33 bits on the RHS, but RHS's VARREF 'length' generates 16 bits. + : ... note: In instance 'tb_mmio_error.platform.loader' + 32 | wire [32:0] end_address = {1'b0,address}+length; + | ^ + ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=5.050 + ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:35:38: Operator ADD expects 32 bits on the RHS, but RHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_mmio_error.platform.loader' + 35 | wire [31:0] byte_address = address + cursor; + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:67:32: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's SHIFTR generates 32 bits. + : ... note: In instance 'tb_mmio_error.platform.loader' + 67 | 11,12,13,14:tx_data=RAM_BYTES >> ((reply_index-11)*8); + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:68:32: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's SHIFTR generates 32 bits. + : ... note: In instance 'tb_mmio_error.platform.loader' + 68 | 15,16,17,18:tx_data=CLOCK_HZ >> ((reply_index-15)*8); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:73:28: Operator EQ expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_mmio_error.platform.loader' + 73 | else if(reply_index==7+reply_length) tx_data=crc[7:0]; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:64:23: Operator LT expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_mmio_error.platform.loader' + 64 | if(reply_index<7+reply_length) begin + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:119:20: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_mmio_error.platform.loader' + 119 | if(cursor+1==length) state<=CRC0; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:144:25: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_mmio_error.platform.loader' + 144 | else if(cursor+1==length) begin image_loaded<=1;state<=REPLY;end + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:152:20: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_mmio_error.platform.loader' + 152 | if(cursor+1==length) state<=REPLY; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:157:43: Operator LT expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_mmio_error.platform.loader' + 157 | if(reply_index>=2 && reply_index<7+reply_length) crc<=crc_next(crc,tx_data); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:158:25: Operator EQ expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_mmio_error.platform.loader' + 158 | if(reply_index==8+reply_length) state<=DRAIN; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/board/ddr_uart_loader.sv:87:37: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'timeout_count' generates 22 bits. + : ... note: In instance 'tb_mmio_error.platform.loader' + 87 | if((receiving && timeout_count==RX_TIMEOUT-1) || (receiving && rx_error)) begin + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:52:20: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'addr' generates 28 bits. + : ... note: In instance 'tb_mmio_error.memory' + 52 | offset=(addr & ~(LANES-1))-BASE; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:78:28: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'write_addr' generates 28 bits. + : ... note: In instance 'tb_mmio_error.memory' + 78 | offset=(write_addr & ~(LANES-1))-BASE; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:86:26: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'h600d600d' generates 64 bits. + : ... note: In instance 'tb_mmio_error.memory' + 86 | if (w_bits_data==64'h600d600d) begin + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:91:66: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff' generates 64 bits. + : ... note: In instance 'tb_mmio_error.memory' + 91 | $fatal(1,"CPU smoke failed at stage %0d",w_bits_data & 64'hffff); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:90:28: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff0000' generates 64 bits. + : ... note: In instance 'tb_mmio_error.memory' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:90:43: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'hbad00000' generates 64 bits. + : ... note: In instance 'tb_mmio_error.memory' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^~ +%Warning-WIDTHEXPAND: evidence/2026-10-12/pr10-review/old-platform.sv:406:33: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's REDOR generates 1 bits. + : ... note: In instance 'tb_mmio_error.platform' + 406 | assign peripherals_b_bits_resp=|scu_bresp; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:99:12: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's SEL generates 16 bits. + : ... note: In instance 'tb_mmio_error' + 99 | traps=exit_code[15:0];$display("MMIO_SYNCHRONOUS_TRAPS %0d",traps); + | ^ +make: Entering directory '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/obj' +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_timing.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_timing.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_threads.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_threads.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb_mmio_error__pch.h -o Vtb_mmio_error__pch.h.fast.gch +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb_mmio_error__pch.h -o Vtb_mmio_error__pch.h.slow.gch +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_mmio_error__pch.h.fast -c Vtb_mmio_error.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_mmio_error__pch.h.fast -c Vtb_mmio_error___024root__0.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_mmio_error__pch.h.fast -c Vtb_mmio_error___024root__1.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_mmio_error__pch.h.fast -c Vtb_mmio_error___024root__2.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_mmio_error__pch.h.fast -c Vtb_mmio_error___024root__3.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_mmio_error__pch.h.fast -c Vtb_mmio_error___024root__4.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_mmio_error__pch.h.fast -c Vtb_mmio_error___024root__5.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_mmio_error__pch.h.fast -c Vtb_mmio_error___024root__6.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_mmio_error__pch.h.fast -c Vtb_mmio_error___024root__7.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_mmio_error__pch.h.fast -c Vtb_mmio_error___024root__8.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_mmio_error__pch.h.fast -c Vtb_mmio_error___024root__9.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_mmio_error__pch.h.fast -c Vtb_mmio_error__main.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_mmio_error__pch.h.slow -c Vtb_mmio_error__ConstPool__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_mmio_error__pch.h.slow -c Vtb_mmio_error___024root__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_mmio_error__pch.h.slow -c Vtb_mmio_error___024root__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_mmio_error__pch.h.slow -c Vtb_mmio_error___024root__1__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_mmio_error__pch.h.slow -c Vtb_mmio_error___024root__2__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_mmio_error__pch.h.slow -c Vtb_mmio_error___024root__3__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_mmio_error__pch.h.slow -c Vtb_mmio_error__Syms__Slow.cpp +g++ verilated.o verilated_timing.o verilated_threads.o Vtb_mmio_error__ALL.a -pthread -lpthread -latomic -o Vtb_mmio_error +rm Vtb_mmio_error__ALL.verilator_deplist.tmp +make: Leaving directory '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/obj' +- V e r i l a t i o n R e p o r t: Verilator 5.050 2026-07-01 rev v5.050 +- Verilator: Built from 46.551 MB sources in 354 modules, into 26.554 MB in 19 C++ files needing 0.019 MB +- Verilator: Walltime 18.180 s (elab=0.558, cvt=3.500, bld=13.519); cpu 4.957 s on 4 threads; allocated 557.465 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/mmio-old-counterexample/fault.bin b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/mmio-old-counterexample/fault.bin new file mode 100644 index 0000000..adb2d4a Binary files /dev/null and b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/mmio-old-counterexample/fault.bin differ diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/mmio-old-counterexample/fault.elf b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/mmio-old-counterexample/fault.elf new file mode 100644 index 0000000..4bd5381 Binary files /dev/null and b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/mmio-old-counterexample/fault.elf differ diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/mmio-old-counterexample/fault.hex b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/mmio-old-counterexample/fault.hex new file mode 100644 index 0000000..c3dc26c --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/mmio-old-counterexample/fault.hex @@ -0,0 +1,164 @@ +97 +02 +00 +00 +93 +82 +02 +05 +73 +90 +52 +30 +73 +10 +20 +30 +73 +10 +40 +30 +93 +04 +00 +00 +b7 +02 +03 +60 +23 +b0 +02 +00 +0f +00 +f0 +0f +03 +b3 +02 +00 +0f +00 +f0 +0f +b7 +02 +00 +60 +37 +03 +00 +74 +33 +63 +93 +00 +23 +b0 +62 +00 +b7 +02 +00 +60 +37 +63 +0d +60 +1b +03 +d3 +00 +23 +b0 +62 +00 +6f +00 +00 +00 +73 +25 +20 +34 +13 +06 +50 +00 +63 +06 +c5 +00 +13 +06 +70 +00 +63 +14 +c5 +02 +f3 +25 +30 +34 +63 +86 +05 +00 +37 +06 +03 +60 +63 +9c +c5 +00 +93 +84 +14 +00 +73 +25 +10 +34 +13 +05 +45 +00 +73 +10 +15 +34 +73 +00 +20 +30 +b7 +02 +00 +60 +37 +13 +00 +00 +1b +03 +d3 +ba +13 +13 +43 +01 +13 +03 +73 +00 +23 +b0 +62 +00 +6f +00 +00 +00 diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/mmio-old-counterexample/simulation.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/mmio-old-counterexample/simulation.log new file mode 100644 index 0000000..f8ee005 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/mmio-old-counterexample/simulation.log @@ -0,0 +1,3 @@ +[1535000] %Fatal: tb_mmio_error.sv:106: Assertion failed in tb_mmio_error: CPU did not receive SLVERR +%Error: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/board-mmio-error/tb_mmio_error.sv:106: Verilog $stop +Aborting... diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/mmio-old-counterexample/tb_mmio_error.sv b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/mmio-old-counterexample/tb_mmio_error.sv new file mode 100644 index 0000000..61e125f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/mmio-old-counterexample/tb_mmio_error.sv @@ -0,0 +1,115 @@ +`timescale 1ns/1ps +module tb_mmio_error; + reg clk=0;always #5 clk=~clk; + reg reset=1,uart_rx_in=1; + wire uart_tx_out; + wire cpu_run; + wire exited; + wire loader_error; + wire [31:0] exit_code; + wire [3:0] ddr_awid; + wire [27:0] ddr_awaddr; + wire [7:0] ddr_awlen; + wire [2:0] ddr_awsize; + wire [1:0] ddr_awburst; + wire ddr_awvalid; + wire ddr_awready; + wire [127:0] ddr_wdata; + wire [15:0] ddr_wstrb; + wire ddr_wlast; + wire ddr_wvalid; + wire ddr_wready; + wire [3:0] ddr_bid; + wire [1:0] ddr_bresp; + wire ddr_bvalid; + wire ddr_bready; + wire [3:0] ddr_arid; + wire [27:0] ddr_araddr; + wire [7:0] ddr_arlen; + wire [2:0] ddr_arsize; + wire [1:0] ddr_arburst; + wire ddr_arvalid; + wire ddr_arready; + wire [3:0] ddr_rid; + wire [127:0] ddr_rdata; + wire [1:0] ddr_rresp; + wire ddr_rlast; + wire ddr_rvalid; + wire ddr_rready; + wire flash_miso; + wire flash_recovery; + wire flash_mosi; + wire flash_sck; + wire flash_cs_n; + toy_a7_platform platform(.*); + initial begin + repeat(10) @(negedge clk); force platform.loader.cpu_run=1;reset=0;end + integer cycles=0; + always @(posedge clk) if(!reset) begin + cycles<=cycles+1; + if(platform.memory_aw_valid && platform.memory_aw_bits_lock) $fatal(1,"Unexpected AXI exclusive write"); + if(platform.memory_ar_valid && platform.memory_ar_bits_lock) $fatal(1,"Unexpected AXI exclusive read"); + if(ddr_awvalid && ddr_awready && (ddr_awsize!=4 || ddr_awlen!=0)) $fatal(1,"Narrow DDR write"); + if(ddr_arvalid && ddr_arready && (ddr_arsize!=4 || ddr_arlen!=0)) $fatal(1,"Narrow DDR read"); + if(exited && (exit_code & 32'hffff0000)==32'hbad00000) $fatal(1,"CPU oracle failed stage=%h",exit_code); + if(exited && exit_code==32'h600d600d) begin + if(bad_b!=1 || bad_r!=1) $fatal(1,"Fault did not traverse AXI/SCU"); + $display("PASS MMIO_ERROR CPU AXI/SCU response delivery cycles=%0d",cycles);$finish;end + if(cycles>4000000) $fatal(1,"Board CPU watchdog"); + end + axi_smoke_memory #(.ADDR_BITS(28),.BASE(0),.CAPACITY(262144),.IMAGE("fault.hex")) memory ( + .clock(clk), + .reset(reset), + .aw_bits_id(ddr_awid), + .aw_bits_addr(ddr_awaddr), + .aw_bits_len(ddr_awlen), + .aw_bits_size(ddr_awsize), + .aw_bits_burst(ddr_awburst), + .aw_valid(ddr_awvalid), + .aw_ready(ddr_awready), + .w_bits_data(ddr_wdata), + .w_bits_strb(ddr_wstrb), + .w_bits_last(ddr_wlast), + .w_valid(ddr_wvalid), + .w_ready(ddr_wready), + .b_bits_id(ddr_bid), + .b_bits_resp(ddr_bresp), + .b_valid(ddr_bvalid), + .b_ready(ddr_bready), + .ar_bits_id(ddr_arid), + .ar_bits_addr(ddr_araddr), + .ar_bits_len(ddr_arlen), + .ar_bits_size(ddr_arsize), + .ar_bits_burst(ddr_arburst), + .ar_valid(ddr_arvalid), + .ar_ready(ddr_arready), + .r_bits_id(ddr_rid), + .r_bits_data(ddr_rdata), + .r_bits_resp(ddr_rresp), + .r_bits_last(ddr_rlast), + .r_valid(ddr_rvalid), + .r_ready(ddr_rready) + ); + + reg bad_write=0,bad_read=0; + integer bad_b=0,bad_r=0; + integer traps=-1; + always @(posedge clk) if(!reset) begin + if(exited && exit_code[31:16]==16'h7400 && traps<0) begin + traps=exit_code[15:0];$display("MMIO_SYNCHRONOUS_TRAPS %0d",traps); + end + if(platform.peripherals_aw_valid && platform.peripherals_aw_ready) + bad_write<=platform.peripherals_aw_bits_addr==31'h60030000; + if(platform.peripherals_ar_valid && platform.peripherals_ar_ready) + bad_read<=platform.peripherals_ar_bits_addr==31'h60030000; + if(platform.peripherals_b_valid && platform.peripherals_b_ready && bad_write) begin + if(platform.chip.peripherals_b_bits_resp!==2'b10) $fatal(1,"CPU did not receive SLVERR"); + bad_b<=bad_b+1;bad_write<=0; + end + if(platform.peripherals_r_valid && platform.peripherals_r_ready && bad_read) begin + if(platform.chip.peripherals_r_bits_resp!==2'b10) $fatal(1,"CPU did not receive read error"); + bad_r<=bad_r+1;bad_read<=0; + end + end + +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/pe-checks/cycles-test.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/pe-checks/cycles-test.log new file mode 100644 index 0000000..637bc58 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/pe-checks/cycles-test.log @@ -0,0 +1,5 @@ +PASS original/LUT/DSP PE: 91115 valid-cycle comparisons +- /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/tb_pe.sv:53: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 1ms; walltime 0.146 s; speed 7.247 ms/s +- Verilator: cpu 0.146 s on 1 threads; allocated 6 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/pe-checks/quantizer-proof.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/pe-checks/quantizer-proof.log new file mode 100644 index 0000000..c3d5b30 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/pe-checks/quantizer-proof.log @@ -0,0 +1,218 @@ + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2026 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.67+post (git sha1 v0.67, Release, GNU /nix/store/adcz0m6qq2flmshdf0zz2xwjr5zbq1gr-gcc-wrapper-15.3.0/bin/g++ 15.3.0) + +-- Running command `read_verilog -sv /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/quantizer/QuantizerEquivalence_rtl.sv; prep -top QuantizerEquivalence -flatten; sat -prove equal 1 -verify -show-inputs -show-outputs' -- + +1. Executing Verilog-2005 frontend: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/quantizer/QuantizerEquivalence_rtl.sv +Parsing SystemVerilog input from `/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/quantizer/QuantizerEquivalence_rtl.sv' to AST representation. +Generating RTLIL representation for module `\QuantizerEquivalence'. +Successfully finished Verilog frontend. + +2. Executing PREP pass. + +2.1. Executing HIERARCHY pass (managing design hierarchy). + +2.1.1. Analyzing design hierarchy.. +Top module: \QuantizerEquivalence + +2.1.2. Analyzing design hierarchy.. +Top module: \QuantizerEquivalence +Removed 0 unused modules. + +2.2. Executing PROC pass (convert processes to netlists). + +2.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +2.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Removed a total of 0 dead cases. + +2.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 0 assignments to connections. + +2.2.4. Executing PROC_INIT pass (extract init attributes). + +2.2.5. Executing PROC_ARST pass (detect async resets in processes). + +2.2.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + +2.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). + +2.2.8. Executing PROC_DLATCH pass (convert process syncs to latches). + +2.2.9. Executing PROC_DFF pass (convert process syncs to FFs). + +2.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +2.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +2.2.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module QuantizerEquivalence. + +2.3. Executing FLATTEN pass (flatten design). + +2.4. Executing FUTURE pass. + +2.5. Executing OPT_EXPR pass (perform const folding). +Optimizing module QuantizerEquivalence. + +2.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \QuantizerEquivalence.. +Removed 0 unused cells and 12 unused wires. + + +2.7. Executing CHECK pass (checking for obvious problems). +Checking module QuantizerEquivalence... +Found and reported 0 problems. + +2.8. Executing OPT pass (performing simple optimizations). + +2.8.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module QuantizerEquivalence. + +2.8.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\QuantizerEquivalence'. +Computing hashes of 35 cells of `\QuantizerEquivalence'. +Finding duplicate cells in `\QuantizerEquivalence'. +Removed a total of 0 cells. + +2.8.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \QuantizerEquivalence.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +2.8.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \QuantizerEquivalence. +Performed a total of 0 changes. + +2.8.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\QuantizerEquivalence'. +Computing hashes of 35 cells of `\QuantizerEquivalence'. +Finding duplicate cells in `\QuantizerEquivalence'. +Removed a total of 0 cells. + +2.8.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \QuantizerEquivalence.. + +2.8.7. Executing OPT_EXPR pass (perform const folding). +Optimizing module QuantizerEquivalence. + +2.8.8. Finished fast OPT passes. (There is nothing left to do.) + +2.9. Executing WREDUCE pass (reducing word size of cells). +Removed top 4 bits (of 5) from port B of cell QuantizerEquivalence.$sub$/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/quantizer/QuantizerEquivalence_rtl.sv:11$1 ($sub). +Removed top 12 bits (of 32) from port A of cell QuantizerEquivalence.$sshr$/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/quantizer/QuantizerEquivalence_rtl.sv:12$2 ($sshr). +Removed top 27 bits (of 32) from port B of cell QuantizerEquivalence.$sshr$/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/quantizer/QuantizerEquivalence_rtl.sv:12$2 ($sshr). +Removed top 31 bits (of 32) from port Y of cell QuantizerEquivalence.$sshr$/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/quantizer/QuantizerEquivalence_rtl.sv:12$2 ($sshr). +Removed top 12 bits (of 32) from port A of cell QuantizerEquivalence.$sshr$/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/quantizer/QuantizerEquivalence_rtl.sv:13$3 ($sshr). +Removed top 3 bits (of 5) from port B of cell QuantizerEquivalence.$lt$/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/quantizer/QuantizerEquivalence_rtl.sv:18$6 ($lt). +Removed top 31 bits (of 32) from port A of cell QuantizerEquivalence.$shl$/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/quantizer/QuantizerEquivalence_rtl.sv:18$7 ($shl). +Removed top 27 bits (of 32) from port B of cell QuantizerEquivalence.$shl$/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/quantizer/QuantizerEquivalence_rtl.sv:18$7 ($shl). +Removed top 31 bits (of 32) from port B of cell QuantizerEquivalence.$sub$/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/quantizer/QuantizerEquivalence_rtl.sv:18$8 ($sub). +Removed top 31 bits (of 32) from port B of cell QuantizerEquivalence.$add$/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/quantizer/QuantizerEquivalence_rtl.sv:15$14 ($add). +Removed top 12 bits (of 32) from port B of cell QuantizerEquivalence.$gt$/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/quantizer/QuantizerEquivalence_rtl.sv:21$15 ($gt). +Removed top 12 bits (of 32) from port B of cell QuantizerEquivalence.$lt$/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/quantizer/QuantizerEquivalence_rtl.sv:23$16 ($lt). +Removed top 1 bits (of 22) from mux cell QuantizerEquivalence.$ternary$/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/quantizer/QuantizerEquivalence_rtl.sv:24$19 ($mux). +Removed top 1 bits (of 22) from mux cell QuantizerEquivalence.$ternary$/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/quantizer/QuantizerEquivalence_rtl.sv:26$22 ($mux). +Removed top 1 bits (of 22) from mux cell QuantizerEquivalence.$ternary$/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/quantizer/QuantizerEquivalence_rtl.sv:30$25 ($mux). +Removed top 1 bits (of 22) from mux cell QuantizerEquivalence.$ternary$/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/quantizer/QuantizerEquivalence_rtl.sv:34$28 ($mux). +Removed top 1 bits (of 22) from mux cell QuantizerEquivalence.$ternary$/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/quantizer/QuantizerEquivalence_rtl.sv:38$31 ($mux). +Removed top 19 bits (of 20) from port B of cell QuantizerEquivalence.$add$/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/quantizer/QuantizerEquivalence_rtl.sv:44$34 ($add). +Removed top 31 bits (of 32) from wire QuantizerEquivalence._reference_point_five_T_3. +Removed top 27 bits (of 32) from wire QuantizerEquivalence._GEN_0. + +2.10. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \QuantizerEquivalence.. +Removed 0 unused cells and 2 unused wires. + + +2.11. Executing MEMORY_COLLECT pass (generating $mem cells). + +2.12. Executing OPT pass (performing simple optimizations). + +2.12.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module QuantizerEquivalence. + +2.12.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\QuantizerEquivalence'. +Computing hashes of 35 cells of `\QuantizerEquivalence'. +Finding duplicate cells in `\QuantizerEquivalence'. +Removed a total of 0 cells. + +2.12.3. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \QuantizerEquivalence.. + +2.12.4. Finished fast OPT passes. + +2.13. Executing SORT pass. + +2.14. Printing statistics. + +=== QuantizerEquivalence === + + +----------Local Count, excluding submodules. + | + 40 wires + 484 wire bits + 17 public wires + 318 public wire bits + 5 ports + 66 port bits + 35 cells + 2 $add + 4 $and + 1 $eq + 1 $gt + 2 $lt + 8 $mux + 6 $or + 6 $reduce_or + 1 $shl + 2 $sshr + 2 $sub + +2.15. Executing CHECK pass (checking for obvious problems). +Checking module QuantizerEquivalence... +Found and reported 0 problems. + +3. Executing SAT pass (solving SAT problems in the circuit). +Using SAT solver `minisat`. + +Setting up SAT problem: +Final constraint equation: { } = { } +Imported 35 cells to SAT database. +Import proof-constraint: \equal = 1'1 +Final proof equation: \equal = 1'1 +Import show expression: \amount +Import show expression: \value +Import show expression: \actual +Import show expression: \equal +Import show expression: \reference + +Solving problem with 3686 variables and 10252 clauses.. +SAT proof finished - no model found: SUCCESS! + + /$$$$$$ /$$$$$$$$ /$$$$$$$ + /$$__ $$ | $$_____/ | $$__ $$ + | $$ \ $$ | $$ | $$ \ $$ + | $$ | $$ | $$$$$ | $$ | $$ + | $$ | $$ | $$__/ | $$ | $$ + | $$/$$ $$ | $$ | $$ | $$ + | $$$$$$/ /$$| $$$$$$$$ /$$| $$$$$$$//$$ + \____ $$$|__/|________/|__/|_______/|__/ + \__/ + +End of script. Logfile hash: 1760e1ba6f, time: 0.07s, user: 0.05s, system: 0.01s, MEM: 33.04 MB peak +Yosys 0.67+post (git sha1 v0.67, Release, GNU /nix/store/adcz0m6qq2flmshdf0zz2xwjr5zbq1gr-gcc-wrapper-15.3.0/bin/g++ 15.3.0) +Time spent: 79% 1x sat (0 sec), 4% 4x opt_clean (0 sec), ... diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/pe-checks/tb_pe.sv b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/pe-checks/tb_pe.sv new file mode 100644 index 0000000..9b6fb8b --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/pe-checks/tb_pe.sv @@ -0,0 +1,56 @@ + +`timescale 1ns/1ps +module tb; + reg clock=0; + always #5 clock=~clock; + reg reset=0; + reg [7:0] in_a=0; + reg [19:0] in_b=0, in_d=0; + reg control_dataflow=0, control_propagate=0; + reg [4:0] control_shift=0; + reg [1:0] id=0; + reg last=0, valid=1; + wire equal; + integer checked=0; + integer seed=57201; + PeCycleEquivalence dut(.*); + task step(input bit df, input bit prop, input integer shift, + input integer a, input integer b, input integer d, + input bit v, input bit check); + begin + @(negedge clock); + control_dataflow=df; control_propagate=prop; control_shift=shift; + in_a=a; in_b=b; in_d=d; valid=v; + id=$random(seed); last=$random(seed); + #1; + if (check && v) begin + if (equal !== 1'b1) begin + $display("PE mismatch df=%0d prop=%0d shift=%0d",df,prop,shift); + $fatal(1,"a=%0d b=%0d d=%0d cycle=%0d",a,b,d,checked); + end + checked=checked+1; + end + @(posedge clock); #1; + end + endtask + initial begin + // Initialize both original accumulator registers through legal loading. + step(0,1,0,0,0,0,1,0); + step(0,0,0,0,0,0,1,0); + for (integer shift=0; shift<32; shift=shift+1) + for (integer df=0; df<2; df=df+1) + for (integer p=0; p<2; p=p+1) + for (integer n=0; n<16; n=n+1) begin + step(df,p,shift,(n&1)?-128:127,(n&2)?-524288:524287, + (n&4)?-524288:524287,1,1); + step(df,!p,shift,(n&1)?-1:1,(n&2)?-3:3,(n&4)?-1:1,1,1); + step(df,p,shift,0,0,0,0,1); + end + for (integer n=0; n<100000; n=n+1) + step($random(seed)&1,$random(seed)&1,$random(seed)&31, + $random(seed),$random(seed),$random(seed),($random(seed)&7)!=0,1); + $display("PASS original/LUT/DSP PE: %0d valid-cycle comparisons",checked); + $finish; + end + initial begin #2000000; $fatal(1,"PE test timeout"); end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/pe-checks/verilator-build.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/pe-checks/verilator-build.log new file mode 100644 index 0000000..afe43ef --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/pe-checks/verilator-build.log @@ -0,0 +1,140 @@ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/cycles/PeCycleEquivalence_rtl.sv:2:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 2 | module ReferenceMacUnit( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/tb_pe.sv:3:8: ... Location of module with timescale + 3 | module tb; + | ^~ + ... For warning description see https://verilator.org/warn/TIMESCALEMOD?v=5.050 + ... Use "/* verilator lint_off TIMESCALEMOD */" and lint_on around source to disable this message. +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/cycles/PeCycleEquivalence_rtl.sv:13:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 13 | module ReferencePE( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/tb_pe.sv:3:8: ... Location of module with timescale + 3 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/cycles/PeCycleEquivalence_rtl.sv:115:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 115 | module MacUnit( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/tb_pe.sv:3:8: ... Location of module with timescale + 3 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/cycles/PeCycleEquivalence_rtl.sv:126:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 126 | module PE( + | ^~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/tb_pe.sv:3:8: ... Location of module with timescale + 3 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/cycles/PeCycleEquivalence_rtl.sv:226:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 226 | module MacUnit_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/tb_pe.sv:3:8: ... Location of module with timescale + 3 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/cycles/PeCycleEquivalence_rtl.sv:241:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 241 | module PE_1( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/tb_pe.sv:3:8: ... Location of module with timescale + 3 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/cycles/PeCycleEquivalence_rtl.sv:339:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 339 | module PeCycleEquivalence( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/tb_pe.sv:3:8: ... Location of module with timescale + 3 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/cycles/PeCycleEquivalence_rtl.sv:477:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 477 | module FpgaDspMac(input [7:0] a, b, input [19:0] c, output [19:0] y); + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/tb_pe.sv:3:8: ... Location of module with timescale + 3 | module tb; + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/tb_pe.sv:22:65: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'shift' generates 32 bits. + : ... note: In instance 'tb' + 22 | control_dataflow=df; control_propagate=prop; control_shift=shift; + | ^ + ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=5.050 + ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/tb_pe.sv:23:11: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'a' generates 32 bits. + : ... note: In instance 'tb' + 23 | in_a=a; in_b=b; in_d=d; valid=v; + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/tb_pe.sv:23:19: Operator ASSIGN expects 20 bits on the Assign RHS, but Assign RHS's VARREF 'b' generates 32 bits. + : ... note: In instance 'tb' + 23 | in_a=a; in_b=b; in_d=d; valid=v; + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/tb_pe.sv:23:27: Operator ASSIGN expects 20 bits on the Assign RHS, but Assign RHS's VARREF 'd' generates 32 bits. + : ... note: In instance 'tb' + 23 | in_a=a; in_b=b; in_d=d; valid=v; + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/tb_pe.sv:24:9: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS's RAND generates 32 bits. + : ... note: In instance 'tb' + 24 | id=$random(seed); last=$random(seed); + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/tb_pe.sv:24:29: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's RAND generates 32 bits. + : ... note: In instance 'tb' + 24 | id=$random(seed); last=$random(seed); + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/tb_pe.sv:44:34: Logical operator COND expects 1 bit on the Conditional Test, but Conditional Test's AND generates 32 bits. + : ... note: In instance 'tb' + 44 | step(df,p,shift,(n&1)?-128:127,(n&2)?-524288:524287, + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/tb_pe.sv:44:49: Logical operator COND expects 1 bit on the Conditional Test, but Conditional Test's AND generates 32 bits. + : ... note: In instance 'tb' + 44 | step(df,p,shift,(n&1)?-128:127,(n&2)?-524288:524287, + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/tb_pe.sv:45:23: Logical operator COND expects 1 bit on the Conditional Test, but Conditional Test's AND generates 32 bits. + : ... note: In instance 'tb' + 45 | (n&4)?-524288:524287,1,1); + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/tb_pe.sv:44:13: Operator TASKREF 'step' expects 1 bits on the Function Argument, but Function Argument's VARREF 'df' generates 32 bits. + : ... note: In instance 'tb' + 44 | step(df,p,shift,(n&1)?-128:127,(n&2)?-524288:524287, + | ^~~~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/tb_pe.sv:44:13: Operator TASKREF 'step' expects 1 bits on the Function Argument, but Function Argument's VARREF 'p' generates 32 bits. + : ... note: In instance 'tb' + 44 | step(df,p,shift,(n&1)?-128:127,(n&2)?-524288:524287, + | ^~~~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/tb_pe.sv:46:21: Logical operator LOGNOT expects 1 bit on the LHS, but LHS's VARREF 'p' generates 32 bits. + : ... note: In instance 'tb' + 46 | step(df,!p,shift,(n&1)?-1:1,(n&2)?-3:3,(n&4)?-1:1,1,1); + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/tb_pe.sv:46:35: Logical operator COND expects 1 bit on the Conditional Test, but Conditional Test's AND generates 32 bits. + : ... note: In instance 'tb' + 46 | step(df,!p,shift,(n&1)?-1:1,(n&2)?-3:3,(n&4)?-1:1,1,1); + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/tb_pe.sv:46:46: Logical operator COND expects 1 bit on the Conditional Test, but Conditional Test's AND generates 32 bits. + : ... note: In instance 'tb' + 46 | step(df,!p,shift,(n&1)?-1:1,(n&2)?-3:3,(n&4)?-1:1,1,1); + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/tb_pe.sv:46:57: Logical operator COND expects 1 bit on the Conditional Test, but Conditional Test's AND generates 32 bits. + : ... note: In instance 'tb' + 46 | step(df,!p,shift,(n&1)?-1:1,(n&2)?-3:3,(n&4)?-1:1,1,1); + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/tb_pe.sv:46:13: Operator TASKREF 'step' expects 1 bits on the Function Argument, but Function Argument's VARREF 'df' generates 32 bits. + : ... note: In instance 'tb' + 46 | step(df,!p,shift,(n&1)?-1:1,(n&2)?-3:3,(n&4)?-1:1,1,1); + | ^~~~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/tb_pe.sv:47:13: Operator TASKREF 'step' expects 1 bits on the Function Argument, but Function Argument's VARREF 'df' generates 32 bits. + : ... note: In instance 'tb' + 47 | step(df,p,shift,0,0,0,0,1); + | ^~~~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/tb_pe.sv:47:13: Operator TASKREF 'step' expects 1 bits on the Function Argument, but Function Argument's VARREF 'p' generates 32 bits. + : ... note: In instance 'tb' + 47 | step(df,p,shift,0,0,0,0,1); + | ^~~~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/tb_pe.sv:50:7: Operator TASKREF 'step' expects 1 bits on the Function Argument, but Function Argument's AND generates 32 bits. + : ... note: In instance 'tb' + 50 | step($random(seed)&1,$random(seed)&1,$random(seed)&31, + | ^~~~ +make: Entering directory '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/obj' +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_timing.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_timing.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_threads.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_threads.cpp +python3 /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vtb.cpp Vtb___024root__0.cpp Vtb__main.cpp Vtb___024root__Slow.cpp Vtb___024root__0__Slow.cpp Vtb__Syms__Slow.cpp > Vtb__ALL.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o Vtb__ALL.o Vtb__ALL.cpp +g++ verilated.o verilated_timing.o verilated_threads.o Vtb__ALL.a -pthread -lpthread -latomic -o Vtb +rm Vtb__ALL.verilator_deplist.tmp +make: Leaving directory '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/pe-checks/obj' +- V e r i l a t i o n R e p o r t: Verilator 5.050 2026-07-01 rev v5.050 +- Verilator: Built from 0.091 MB sources in 10 modules, into 0.135 MB in 6 C++ files needing 0.001 MB +- Verilator: Walltime 3.402 s (elab=0.004, cvt=0.019, bld=3.368); cpu 0.041 s on 8 threads; allocated 360.035 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/RESULT.json new file mode 100644 index 0000000..aeac5b4 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/RESULT.json @@ -0,0 +1,106 @@ +{ + "result": "PASS_OFFLINE_TCL_CONTRACTS", + "physical_hardware_tested": false, + "cases": [ + { + "script": "program_arty.tcl", + "fault": "none", + "result": "PASS" + }, + { + "script": "program_arty.tcl", + "fault": "device_error", + "result": "PASS" + }, + { + "script": "program_arty.tcl", + "fault": "done_low", + "result": "PASS" + }, + { + "script": "program_arty.tcl", + "fault": "eos_low", + "result": "PASS" + }, + { + "script": "program_arty.tcl", + "fault": "crc_error", + "result": "PASS" + }, + { + "script": "backup_flash.tcl", + "fault": "none", + "result": "PASS" + }, + { + "script": "backup_flash.tcl", + "fault": "device_error", + "result": "PASS" + }, + { + "script": "backup_flash.tcl", + "fault": "done_low", + "result": "PASS" + }, + { + "script": "backup_flash.tcl", + "fault": "eos_low", + "result": "PASS" + }, + { + "script": "backup_flash.tcl", + "fault": "crc_error", + "result": "PASS" + }, + { + "script": "backup_flash.tcl", + "fault": "readback_error", + "result": "PASS" + }, + { + "script": "backup_flash.tcl", + "fault": "short_backup", + "result": "PASS" + }, + { + "script": "program_flash.tcl", + "fault": "none", + "result": "PASS" + }, + { + "script": "program_flash.tcl", + "fault": "device_error", + "result": "PASS" + }, + { + "script": "program_flash.tcl", + "fault": "done_low", + "result": "PASS" + }, + { + "script": "program_flash.tcl", + "fault": "eos_low", + "result": "PASS" + }, + { + "script": "program_flash.tcl", + "fault": "crc_error", + "result": "PASS" + }, + { + "script": "program_flash.tcl", + "fault": "readback_error", + "result": "PASS" + }, + { + "script": "program_flash.tcl", + "fault": "short_backup", + "result": "PASS" + }, + { + "script": "program_flash.tcl", + "fault": "cfgmem_error", + "result": "PASS" + } + ] +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/backup_flash.tcl-crc_error.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/backup_flash.tcl-crc_error.log new file mode 100644 index 0000000..fca1bae --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/backup_flash.tcl-crc_error.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device +MOCK_FAILURE SPI bridge configuration status rejected diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/backup_flash.tcl-device_error.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/backup_flash.tcl-device_error.log new file mode 100644 index 0000000..30ac2d8 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/backup_flash.tcl-device_error.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device +MOCK_FAILURE SPI bridge programming failed: injected programming exception diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/backup_flash.tcl-done_low.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/backup_flash.tcl-done_low.log new file mode 100644 index 0000000..fca1bae --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/backup_flash.tcl-done_low.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device +MOCK_FAILURE SPI bridge configuration status rejected diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/backup_flash.tcl-eos_low.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/backup_flash.tcl-eos_low.log new file mode 100644 index 0000000..fca1bae --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/backup_flash.tcl-eos_low.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device +MOCK_FAILURE SPI bridge configuration status rejected diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/backup_flash.tcl-none.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/backup_flash.tcl-none.log new file mode 100644 index 0000000..8bcb587 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/backup_flash.tcl-none.log @@ -0,0 +1,3 @@ +PASS FLASH_BACKUP: mt25ql128-spi-x1_x2_x4 /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/programming-check/tmpojanmxcc/backup.bin bytes=16777216 +MOCK_EVENTS program_device readback +MOCK_SUCCESS diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/backup_flash.tcl-readback_error.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/backup_flash.tcl-readback_error.log new file mode 100644 index 0000000..450c391 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/backup_flash.tcl-readback_error.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device readback +MOCK_FAILURE Flash readback failed: injected readback exception diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/backup_flash.tcl-short_backup.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/backup_flash.tcl-short_backup.log new file mode 100644 index 0000000..20502f0 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/backup_flash.tcl-short_backup.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device readback +MOCK_FAILURE Incomplete Flash backup diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/program_arty.tcl-crc_error.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/program_arty.tcl-crc_error.log new file mode 100644 index 0000000..728e8ba --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/program_arty.tcl-crc_error.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device +MOCK_FAILURE JTAG configuration status rejected: expected DONE/EOS high and CRC error clear diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/program_arty.tcl-device_error.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/program_arty.tcl-device_error.log new file mode 100644 index 0000000..a98384b --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/program_arty.tcl-device_error.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device +MOCK_FAILURE JTAG programming failed: injected programming exception diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/program_arty.tcl-done_low.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/program_arty.tcl-done_low.log new file mode 100644 index 0000000..728e8ba --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/program_arty.tcl-done_low.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device +MOCK_FAILURE JTAG configuration status rejected: expected DONE/EOS high and CRC error clear diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/program_arty.tcl-eos_low.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/program_arty.tcl-eos_low.log new file mode 100644 index 0000000..728e8ba --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/program_arty.tcl-eos_low.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device +MOCK_FAILURE JTAG configuration status rejected: expected DONE/EOS high and CRC error clear diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/program_arty.tcl-none.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/program_arty.tcl-none.log new file mode 100644 index 0000000..87ce668 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/program_arty.tcl-none.log @@ -0,0 +1,3 @@ +ARTY_JTAG_PROGRAMMED: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/programming-check/tmpas361gke/input.bit +MOCK_EVENTS program_device +MOCK_SUCCESS diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/program_flash.tcl-cfgmem_error.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/program_flash.tcl-cfgmem_error.log new file mode 100644 index 0000000..176a81a --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/program_flash.tcl-cfgmem_error.log @@ -0,0 +1,3 @@ +PASS FLASH_BACKUP: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/programming-check/tmp6_8c85ze/backup.bin bytes=16777216 +MOCK_EVENTS program_device readback program_flash +MOCK_FAILURE Flash program/verify failed: injected Flash verify exception diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/program_flash.tcl-crc_error.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/program_flash.tcl-crc_error.log new file mode 100644 index 0000000..e18af32 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/program_flash.tcl-crc_error.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device +MOCK_FAILURE SPI bridge configuration status rejected; Flash programming cancelled diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/program_flash.tcl-device_error.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/program_flash.tcl-device_error.log new file mode 100644 index 0000000..30ac2d8 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/program_flash.tcl-device_error.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device +MOCK_FAILURE SPI bridge programming failed: injected programming exception diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/program_flash.tcl-done_low.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/program_flash.tcl-done_low.log new file mode 100644 index 0000000..e18af32 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/program_flash.tcl-done_low.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device +MOCK_FAILURE SPI bridge configuration status rejected; Flash programming cancelled diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/program_flash.tcl-eos_low.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/program_flash.tcl-eos_low.log new file mode 100644 index 0000000..e18af32 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/program_flash.tcl-eos_low.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device +MOCK_FAILURE SPI bridge configuration status rejected; Flash programming cancelled diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/program_flash.tcl-none.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/program_flash.tcl-none.log new file mode 100644 index 0000000..4e57041 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/program_flash.tcl-none.log @@ -0,0 +1,5 @@ +PASS FLASH_BACKUP: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/programming-check/tmpp5h7sv79/backup.bin bytes=16777216 +PASS FLASH_PROGRAM_VERIFY: mt25ql128-spi-x1_x2_x4 /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/programming-check/tmpp5h7sv79/input.bit +FLASH_BOOT_CONFIG_STATUS DONE=1 EOS=1 CRC=0 +MOCK_EVENTS program_device readback program_flash boot +MOCK_SUCCESS diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/program_flash.tcl-readback_error.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/program_flash.tcl-readback_error.log new file mode 100644 index 0000000..8cc9ec4 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/program_flash.tcl-readback_error.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device readback +MOCK_FAILURE Flash backup failed; programming cancelled: injected readback exception diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/program_flash.tcl-short_backup.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/program_flash.tcl-short_backup.log new file mode 100644 index 0000000..2541aca --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/programming-check/program_flash.tcl-short_backup.log @@ -0,0 +1,2 @@ +MOCK_EVENTS program_device readback +MOCK_FAILURE Incomplete backup; programming cancelled diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/routing-check/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/routing-check/RESULT.json new file mode 100644 index 0000000..bf31dfd --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/routing-check/RESULT.json @@ -0,0 +1,15 @@ +{ + "result": "PASS", + "transactions": 512, + "coverage": [ + "two Gemmini reads", + "four Gemmini writes", + "concurrent DMA requests", + "request stalls", + "response stalls", + "backend route look-ahead", + "opposite-direction request arriving during pending route", + "Ball release with responses pending" + ], + "rtl_sha256": "0393da410194867126ec59332fe94a8882895852cd2685e086ce0fa56ec0b2ca" +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/routing-check/RoutingCheck.sv b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/routing-check/RoutingCheck.sv new file mode 100644 index 0000000..c54eed3 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/routing-check/RoutingCheck.sv @@ -0,0 +1,1751 @@ +// Generated by CIRCT firtool-1.62.1 +// Standard header to adapt well known macros for prints and assertions. + +// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. +`ifndef ASSERT_VERBOSE_COND_ + `ifdef ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) + `else // ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ 1 + `endif // ASSERT_VERBOSE_COND +`endif // not def ASSERT_VERBOSE_COND_ + +// Users can define 'STOP_COND' to add an extra gate to stop conditions. +`ifndef STOP_COND_ + `ifdef STOP_COND + `define STOP_COND_ (`STOP_COND) + `else // STOP_COND + `define STOP_COND_ 1 + `endif // STOP_COND +`endif // not def STOP_COND_ + +module MemMidend( + input clock, + reset, + output io_bankRead_0_bankRead_io_req_ready, + input io_bankRead_0_bankRead_io_req_valid, + input [9:0] io_bankRead_0_bankRead_io_req_bits_addr, + input io_bankRead_0_bankRead_io_resp_ready, + output io_bankRead_0_bankRead_io_resp_valid, + output [63:0] io_bankRead_0_bankRead_io_resp_bits_data, + output io_bankRead_1_bankRead_io_req_ready, + input io_bankRead_1_bankRead_io_req_valid, + input [9:0] io_bankRead_1_bankRead_io_req_bits_addr, + input io_bankRead_1_bankRead_io_resp_ready, + output io_bankRead_1_bankRead_io_resp_valid, + output [63:0] io_bankRead_1_bankRead_io_resp_bits_data, + output io_bankRead_2_bankRead_io_req_ready, + input io_bankRead_2_bankRead_io_req_valid, + input [9:0] io_bankRead_2_bankRead_io_req_bits_addr, + input io_bankRead_2_bankRead_io_resp_ready, + output io_bankRead_2_bankRead_io_resp_valid, + output [63:0] io_bankRead_2_bankRead_io_resp_bits_data, + output io_bankWrite_0_bankWrite_io_req_ready, + input io_bankWrite_0_bankWrite_io_req_valid, + input [9:0] io_bankWrite_0_bankWrite_io_req_bits_addr, + input [63:0] io_bankWrite_0_bankWrite_io_req_bits_data, + input io_bankWrite_0_bankWrite_io_resp_ready, + output io_bankWrite_0_bankWrite_io_resp_valid, + io_bankWrite_0_bankWrite_io_resp_bits_ok, + io_bankWrite_1_bankWrite_io_req_ready, + input io_bankWrite_1_bankWrite_io_req_valid, + input [9:0] io_bankWrite_1_bankWrite_io_req_bits_addr, + input [63:0] io_bankWrite_1_bankWrite_io_req_bits_data, + input io_bankWrite_1_bankWrite_io_resp_ready, + output io_bankWrite_1_bankWrite_io_resp_valid, + io_bankWrite_1_bankWrite_io_resp_bits_ok, + io_bankWrite_2_bankWrite_io_req_ready, + input io_bankWrite_2_bankWrite_io_req_valid, + input [9:0] io_bankWrite_2_bankWrite_io_req_bits_addr, + input [63:0] io_bankWrite_2_bankWrite_io_req_bits_data, + input io_bankWrite_2_bankWrite_io_resp_ready, + output io_bankWrite_2_bankWrite_io_resp_valid, + io_bankWrite_2_bankWrite_io_resp_bits_ok, + io_bankWrite_3_bankWrite_io_req_ready, + input io_bankWrite_3_bankWrite_io_req_valid, + input [9:0] io_bankWrite_3_bankWrite_io_req_bits_addr, + input [63:0] io_bankWrite_3_bankWrite_io_req_bits_data, + input io_bankWrite_3_bankWrite_io_resp_ready, + output io_bankWrite_3_bankWrite_io_resp_valid, + io_bankWrite_3_bankWrite_io_resp_bits_ok, + io_bankWrite_4_bankWrite_io_req_ready, + input io_bankWrite_4_bankWrite_io_req_valid, + input [9:0] io_bankWrite_4_bankWrite_io_req_bits_addr, + input [63:0] io_bankWrite_4_bankWrite_io_req_bits_data, + input io_bankWrite_4_bankWrite_io_resp_ready, + output io_bankWrite_4_bankWrite_io_resp_valid, + io_bankWrite_4_bankWrite_io_resp_bits_ok, + input io_ballChannelActive_0, + io_mem_req_0_read_req_ready, + output io_mem_req_0_read_req_valid, + output [9:0] io_mem_req_0_read_req_bits_addr, + output io_mem_req_0_read_resp_ready, + input io_mem_req_0_read_resp_valid, + input [63:0] io_mem_req_0_read_resp_bits_data, + input io_mem_req_1_read_req_ready, + output io_mem_req_1_read_req_valid, + output [9:0] io_mem_req_1_read_req_bits_addr, + output io_mem_req_1_read_resp_ready, + input io_mem_req_1_read_resp_valid, + input [63:0] io_mem_req_1_read_resp_bits_data, + input io_mem_req_2_write_req_ready, + output io_mem_req_2_write_req_valid, + output [9:0] io_mem_req_2_write_req_bits_addr, + output [63:0] io_mem_req_2_write_req_bits_data, + output io_mem_req_2_write_resp_ready, + input io_mem_req_2_write_resp_valid, + io_mem_req_2_write_resp_bits_ok, + io_mem_req_3_write_req_ready, + output io_mem_req_3_write_req_valid, + output [9:0] io_mem_req_3_write_req_bits_addr, + output [63:0] io_mem_req_3_write_req_bits_data, + output io_mem_req_3_write_resp_ready, + input io_mem_req_3_write_resp_valid, + io_mem_req_3_write_resp_bits_ok, + io_mem_req_4_write_req_ready, + output io_mem_req_4_write_req_valid, + output [9:0] io_mem_req_4_write_req_bits_addr, + output [63:0] io_mem_req_4_write_req_bits_data, + output io_mem_req_4_write_resp_ready, + input io_mem_req_4_write_resp_valid, + io_mem_req_4_write_resp_bits_ok, + io_mem_req_5_write_req_ready, + output io_mem_req_5_write_req_valid, + output [9:0] io_mem_req_5_write_req_bits_addr, + output [63:0] io_mem_req_5_write_req_bits_data, + output io_mem_req_5_write_resp_ready, + input io_mem_req_5_write_resp_valid, + io_mem_req_5_write_resp_bits_ok, + io_mem_req_6_write_req_ready, + output io_mem_req_6_write_req_valid, + output [9:0] io_mem_req_6_write_req_bits_addr, + output [63:0] io_mem_req_6_write_req_bits_data, + output io_mem_req_6_write_resp_ready, + input io_mem_req_6_write_resp_valid, + io_mem_req_6_write_resp_bits_ok, + io_mem_req_6_read_req_ready, + output io_mem_req_6_read_req_valid, + output [9:0] io_mem_req_6_read_req_bits_addr, + output io_mem_req_6_read_resp_ready, + input io_mem_req_6_read_resp_valid, + input [63:0] io_mem_req_6_read_resp_bits_data, + output [3:0] io_mem_req_6_bank_id, + io_mem_req_6_rob_id, + output [63:0] io_mem_req_6_inst_id +); + + wire [15:0][63:0] _GEN = + '{64'h73, + 64'h72, + 64'h71, + 64'h70, + 64'h6F, + 64'h6E, + 64'h6D, + 64'h6C, + 64'h6B, + 64'h6A, + 64'h69, + 64'h68, + 64'h67, + 64'h66, + 64'h65, + 64'h64}; + reg pending; + reg accepted; + reg writeSelected; + reg [3:0] bank; + reg [3:0] rob; + wire io_mem_req_6_read_req_valid_0 = + pending & ~accepted & ~writeSelected & io_bankRead_2_bankRead_io_req_valid; + wire io_mem_req_6_write_req_valid_0 = + pending & ~accepted & writeSelected & io_bankWrite_4_bankWrite_io_req_valid; + wire _GEN_0 = io_mem_req_6_read_req_ready & io_mem_req_6_read_req_valid_0; + wire _GEN_1 = + io_mem_req_6_write_req_ready & io_mem_req_6_write_req_valid_0; + `ifndef SYNTHESIS + always @(posedge clock) begin + if (~reset & _GEN_0 & _GEN_1) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at MemMidend.scala:131 assert(!(dma.read.req.fire && dma.write.req.fire))\n"); + if (`STOP_COND_) + $fatal; + end + end // always @(posedge) + `endif // not def SYNTHESIS + always @(posedge clock) begin + automatic logic _GEN_2; + _GEN_2 = + ~pending + & (io_bankRead_2_bankRead_io_req_valid | io_bankWrite_4_bankWrite_io_req_valid); + if (reset) begin + pending <= 1'h0; + accepted <= 1'h0; + writeSelected <= 1'h0; + end + else begin + pending <= + ~(io_bankRead_2_bankRead_io_resp_ready & io_mem_req_6_read_resp_valid + | io_bankWrite_4_bankWrite_io_resp_ready & io_mem_req_6_write_resp_valid) + & (_GEN_2 | pending); + accepted <= _GEN_0 | _GEN_1 | ~_GEN_2 & accepted; + if (_GEN_2) + writeSelected <= io_bankWrite_4_bankWrite_io_req_valid; + end + if (_GEN_2) begin + bank <= {3'h3, io_bankWrite_4_bankWrite_io_req_valid}; + rob <= {2'h0, ~io_bankWrite_4_bankWrite_io_req_valid, 1'h0}; + end + end // always @(posedge) + assign io_bankRead_0_bankRead_io_req_ready = + io_mem_req_0_read_req_ready & io_ballChannelActive_0; + assign io_bankRead_0_bankRead_io_resp_valid = io_mem_req_0_read_resp_valid; + assign io_bankRead_0_bankRead_io_resp_bits_data = io_mem_req_0_read_resp_bits_data; + assign io_bankRead_1_bankRead_io_req_ready = + io_mem_req_1_read_req_ready & io_ballChannelActive_0; + assign io_bankRead_1_bankRead_io_resp_valid = io_mem_req_1_read_resp_valid; + assign io_bankRead_1_bankRead_io_resp_bits_data = io_mem_req_1_read_resp_bits_data; + assign io_bankRead_2_bankRead_io_req_ready = + pending & ~accepted & ~writeSelected & io_mem_req_6_read_req_ready; + assign io_bankRead_2_bankRead_io_resp_valid = io_mem_req_6_read_resp_valid; + assign io_bankRead_2_bankRead_io_resp_bits_data = io_mem_req_6_read_resp_bits_data; + assign io_bankWrite_0_bankWrite_io_req_ready = + io_mem_req_2_write_req_ready & io_ballChannelActive_0; + assign io_bankWrite_0_bankWrite_io_resp_valid = io_mem_req_2_write_resp_valid; + assign io_bankWrite_0_bankWrite_io_resp_bits_ok = io_mem_req_2_write_resp_bits_ok; + assign io_bankWrite_1_bankWrite_io_req_ready = + io_mem_req_3_write_req_ready & io_ballChannelActive_0; + assign io_bankWrite_1_bankWrite_io_resp_valid = io_mem_req_3_write_resp_valid; + assign io_bankWrite_1_bankWrite_io_resp_bits_ok = io_mem_req_3_write_resp_bits_ok; + assign io_bankWrite_2_bankWrite_io_req_ready = + io_mem_req_4_write_req_ready & io_ballChannelActive_0; + assign io_bankWrite_2_bankWrite_io_resp_valid = io_mem_req_4_write_resp_valid; + assign io_bankWrite_2_bankWrite_io_resp_bits_ok = io_mem_req_4_write_resp_bits_ok; + assign io_bankWrite_3_bankWrite_io_req_ready = + io_mem_req_5_write_req_ready & io_ballChannelActive_0; + assign io_bankWrite_3_bankWrite_io_resp_valid = io_mem_req_5_write_resp_valid; + assign io_bankWrite_3_bankWrite_io_resp_bits_ok = io_mem_req_5_write_resp_bits_ok; + assign io_bankWrite_4_bankWrite_io_req_ready = + pending & ~accepted & writeSelected & io_mem_req_6_write_req_ready; + assign io_bankWrite_4_bankWrite_io_resp_valid = io_mem_req_6_write_resp_valid; + assign io_bankWrite_4_bankWrite_io_resp_bits_ok = io_mem_req_6_write_resp_bits_ok; + assign io_mem_req_0_read_req_valid = + io_bankRead_0_bankRead_io_req_valid & io_ballChannelActive_0; + assign io_mem_req_0_read_req_bits_addr = io_bankRead_0_bankRead_io_req_bits_addr; + assign io_mem_req_0_read_resp_ready = io_bankRead_0_bankRead_io_resp_ready; + assign io_mem_req_1_read_req_valid = + io_bankRead_1_bankRead_io_req_valid & io_ballChannelActive_0; + assign io_mem_req_1_read_req_bits_addr = io_bankRead_1_bankRead_io_req_bits_addr; + assign io_mem_req_1_read_resp_ready = io_bankRead_1_bankRead_io_resp_ready; + assign io_mem_req_2_write_req_valid = + io_bankWrite_0_bankWrite_io_req_valid & io_ballChannelActive_0; + assign io_mem_req_2_write_req_bits_addr = io_bankWrite_0_bankWrite_io_req_bits_addr; + assign io_mem_req_2_write_req_bits_data = io_bankWrite_0_bankWrite_io_req_bits_data; + assign io_mem_req_2_write_resp_ready = io_bankWrite_0_bankWrite_io_resp_ready; + assign io_mem_req_3_write_req_valid = + io_bankWrite_1_bankWrite_io_req_valid & io_ballChannelActive_0; + assign io_mem_req_3_write_req_bits_addr = io_bankWrite_1_bankWrite_io_req_bits_addr; + assign io_mem_req_3_write_req_bits_data = io_bankWrite_1_bankWrite_io_req_bits_data; + assign io_mem_req_3_write_resp_ready = io_bankWrite_1_bankWrite_io_resp_ready; + assign io_mem_req_4_write_req_valid = + io_bankWrite_2_bankWrite_io_req_valid & io_ballChannelActive_0; + assign io_mem_req_4_write_req_bits_addr = io_bankWrite_2_bankWrite_io_req_bits_addr; + assign io_mem_req_4_write_req_bits_data = io_bankWrite_2_bankWrite_io_req_bits_data; + assign io_mem_req_4_write_resp_ready = io_bankWrite_2_bankWrite_io_resp_ready; + assign io_mem_req_5_write_req_valid = + io_bankWrite_3_bankWrite_io_req_valid & io_ballChannelActive_0; + assign io_mem_req_5_write_req_bits_addr = io_bankWrite_3_bankWrite_io_req_bits_addr; + assign io_mem_req_5_write_req_bits_data = io_bankWrite_3_bankWrite_io_req_bits_data; + assign io_mem_req_5_write_resp_ready = io_bankWrite_3_bankWrite_io_resp_ready; + assign io_mem_req_6_write_req_valid = io_mem_req_6_write_req_valid_0; + assign io_mem_req_6_write_req_bits_addr = io_bankWrite_4_bankWrite_io_req_bits_addr; + assign io_mem_req_6_write_req_bits_data = io_bankWrite_4_bankWrite_io_req_bits_data; + assign io_mem_req_6_write_resp_ready = io_bankWrite_4_bankWrite_io_resp_ready; + assign io_mem_req_6_read_req_valid = io_mem_req_6_read_req_valid_0; + assign io_mem_req_6_read_req_bits_addr = io_bankRead_2_bankRead_io_req_bits_addr; + assign io_mem_req_6_read_resp_ready = io_bankRead_2_bankRead_io_resp_ready; + assign io_mem_req_6_bank_id = bank; + assign io_mem_req_6_rob_id = rob; + assign io_mem_req_6_inst_id = _GEN[rob]; +endmodule + +module AccPipe( + input clock, + reset, + io_sramRead_req_ready, + output io_sramRead_req_valid, + output [9:0] io_sramRead_req_bits_addr, + output io_sramRead_resp_ready, + input io_sramRead_resp_valid, + input [63:0] io_sramRead_resp_bits_data, + input io_sramWrite_req_ready, + output io_sramWrite_req_valid, + output [9:0] io_sramWrite_req_bits_addr, + output io_sramWrite_req_bits_mask_0, + io_sramWrite_req_bits_mask_1, + io_sramWrite_req_bits_mask_2, + io_sramWrite_req_bits_mask_3, + io_sramWrite_req_bits_mask_4, + io_sramWrite_req_bits_mask_5, + io_sramWrite_req_bits_mask_6, + io_sramWrite_req_bits_mask_7, + output [63:0] io_sramWrite_req_bits_data, + output io_sramWrite_resp_ready, + input io_sramWrite_resp_valid, + output io_mem_req_write_req_ready, + input io_mem_req_write_req_valid, + input [9:0] io_mem_req_write_req_bits_addr, + input io_mem_req_write_req_bits_mask_0, + io_mem_req_write_req_bits_mask_1, + io_mem_req_write_req_bits_mask_2, + io_mem_req_write_req_bits_mask_3, + io_mem_req_write_req_bits_mask_4, + io_mem_req_write_req_bits_mask_5, + io_mem_req_write_req_bits_mask_6, + io_mem_req_write_req_bits_mask_7, + input [63:0] io_mem_req_write_req_bits_data, + input io_mem_req_write_resp_ready, + output io_mem_req_write_resp_valid, + io_mem_req_write_resp_bits_ok, + io_mem_req_read_req_ready, + input io_mem_req_read_req_valid, + input [9:0] io_mem_req_read_req_bits_addr, + input io_mem_req_read_resp_ready, + output io_mem_req_read_resp_valid, + output [63:0] io_mem_req_read_resp_bits_data, + output io_busy +); + + reg rd_hold; + reg [63:0] rd_data_reg; + reg wr_hold; + reg wr_ok_reg; + reg busy_reg; + wire canStart = ~busy_reg & ~rd_hold & ~wr_hold; + wire io_mem_req_read_req_ready_0 = + canStart & ~io_mem_req_write_req_valid & io_sramRead_req_ready; + wire io_mem_req_write_req_ready_0 = canStart & io_sramWrite_req_ready; + always @(posedge clock) begin + if (reset) begin + rd_hold <= 1'h0; + rd_data_reg <= 64'h0; + wr_hold <= 1'h0; + wr_ok_reg <= 1'h0; + busy_reg <= 1'h0; + end + else begin + automatic logic _GEN = rd_hold & io_mem_req_read_resp_ready; + automatic logic _GEN_0 = ~rd_hold & io_sramRead_resp_valid; + automatic logic _GEN_1 = wr_hold & io_mem_req_write_resp_ready; + automatic logic _GEN_2 = ~wr_hold & io_sramWrite_resp_valid; + rd_hold <= ~_GEN & (_GEN_0 | rd_hold); + if (_GEN | ~_GEN_0) begin + end + else + rd_data_reg <= io_sramRead_resp_bits_data; + wr_hold <= ~_GEN_1 & (_GEN_2 | wr_hold); + wr_ok_reg <= ~_GEN_1 & _GEN_2 | wr_ok_reg; + busy_reg <= + ~(io_mem_req_read_resp_ready & rd_hold | io_mem_req_write_resp_ready & wr_hold) + & (io_mem_req_read_req_ready_0 & io_mem_req_read_req_valid + | io_mem_req_write_req_ready_0 & io_mem_req_write_req_valid | busy_reg); + end + end // always @(posedge) + assign io_sramRead_req_valid = + canStart & ~io_mem_req_write_req_valid & io_mem_req_read_req_valid; + assign io_sramRead_req_bits_addr = io_mem_req_read_req_bits_addr; + assign io_sramRead_resp_ready = ~rd_hold; + assign io_sramWrite_req_valid = canStart & io_mem_req_write_req_valid; + assign io_sramWrite_req_bits_addr = io_mem_req_write_req_bits_addr; + assign io_sramWrite_req_bits_mask_0 = io_mem_req_write_req_bits_mask_0; + assign io_sramWrite_req_bits_mask_1 = io_mem_req_write_req_bits_mask_1; + assign io_sramWrite_req_bits_mask_2 = io_mem_req_write_req_bits_mask_2; + assign io_sramWrite_req_bits_mask_3 = io_mem_req_write_req_bits_mask_3; + assign io_sramWrite_req_bits_mask_4 = io_mem_req_write_req_bits_mask_4; + assign io_sramWrite_req_bits_mask_5 = io_mem_req_write_req_bits_mask_5; + assign io_sramWrite_req_bits_mask_6 = io_mem_req_write_req_bits_mask_6; + assign io_sramWrite_req_bits_mask_7 = io_mem_req_write_req_bits_mask_7; + assign io_sramWrite_req_bits_data = io_mem_req_write_req_bits_data; + assign io_sramWrite_resp_ready = ~wr_hold; + assign io_mem_req_write_req_ready = io_mem_req_write_req_ready_0; + assign io_mem_req_write_resp_valid = wr_hold; + assign io_mem_req_write_resp_bits_ok = wr_ok_reg; + assign io_mem_req_read_req_ready = io_mem_req_read_req_ready_0; + assign io_mem_req_read_resp_valid = rd_hold; + assign io_mem_req_read_resp_bits_data = rd_data_reg; + assign io_busy = busy_reg; +endmodule + +module RoutingCheck( + input clock, + reset, + output passed +); + + wire _writeSent_3_6; + wire _writeSent_2_6; + wire _writeSent_1_6; + wire _writeSent_0_6; + wire _readSent_2_6; + wire _readSent_1_6; + wire _readSent_0_6; + wire _pipe_6_io_sramRead_req_valid; + wire [9:0] _pipe_6_io_sramRead_req_bits_addr; + wire _pipe_6_io_sramRead_resp_ready; + wire _pipe_6_io_sramWrite_req_valid; + wire [9:0] _pipe_6_io_sramWrite_req_bits_addr; + wire _pipe_6_io_sramWrite_req_bits_mask_0; + wire _pipe_6_io_sramWrite_req_bits_mask_1; + wire _pipe_6_io_sramWrite_req_bits_mask_2; + wire _pipe_6_io_sramWrite_req_bits_mask_3; + wire _pipe_6_io_sramWrite_req_bits_mask_4; + wire _pipe_6_io_sramWrite_req_bits_mask_5; + wire _pipe_6_io_sramWrite_req_bits_mask_6; + wire _pipe_6_io_sramWrite_req_bits_mask_7; + wire [63:0] _pipe_6_io_sramWrite_req_bits_data; + wire _pipe_6_io_sramWrite_resp_ready; + wire _pipe_6_io_mem_req_write_req_ready; + wire _pipe_6_io_mem_req_write_resp_valid; + wire _pipe_6_io_mem_req_write_resp_bits_ok; + wire _pipe_6_io_mem_req_read_req_ready; + wire _pipe_6_io_mem_req_read_resp_valid; + wire [63:0] _pipe_6_io_mem_req_read_resp_bits_data; + wire _pipe_6_io_busy; + wire _pipe_5_io_sramRead_req_valid; + wire [9:0] _pipe_5_io_sramRead_req_bits_addr; + wire _pipe_5_io_sramRead_resp_ready; + wire _pipe_5_io_sramWrite_req_valid; + wire [9:0] _pipe_5_io_sramWrite_req_bits_addr; + wire _pipe_5_io_sramWrite_req_bits_mask_0; + wire _pipe_5_io_sramWrite_req_bits_mask_1; + wire _pipe_5_io_sramWrite_req_bits_mask_2; + wire _pipe_5_io_sramWrite_req_bits_mask_3; + wire _pipe_5_io_sramWrite_req_bits_mask_4; + wire _pipe_5_io_sramWrite_req_bits_mask_5; + wire _pipe_5_io_sramWrite_req_bits_mask_6; + wire _pipe_5_io_sramWrite_req_bits_mask_7; + wire [63:0] _pipe_5_io_sramWrite_req_bits_data; + wire _pipe_5_io_sramWrite_resp_ready; + wire _pipe_5_io_mem_req_write_req_ready; + wire _pipe_5_io_mem_req_write_resp_valid; + wire _pipe_5_io_mem_req_write_resp_bits_ok; + wire _pipe_5_io_busy; + wire _pipe_4_io_sramRead_req_valid; + wire [9:0] _pipe_4_io_sramRead_req_bits_addr; + wire _pipe_4_io_sramRead_resp_ready; + wire _pipe_4_io_sramWrite_req_valid; + wire [9:0] _pipe_4_io_sramWrite_req_bits_addr; + wire _pipe_4_io_sramWrite_req_bits_mask_0; + wire _pipe_4_io_sramWrite_req_bits_mask_1; + wire _pipe_4_io_sramWrite_req_bits_mask_2; + wire _pipe_4_io_sramWrite_req_bits_mask_3; + wire _pipe_4_io_sramWrite_req_bits_mask_4; + wire _pipe_4_io_sramWrite_req_bits_mask_5; + wire _pipe_4_io_sramWrite_req_bits_mask_6; + wire _pipe_4_io_sramWrite_req_bits_mask_7; + wire [63:0] _pipe_4_io_sramWrite_req_bits_data; + wire _pipe_4_io_sramWrite_resp_ready; + wire _pipe_4_io_mem_req_write_req_ready; + wire _pipe_4_io_mem_req_write_resp_valid; + wire _pipe_4_io_mem_req_write_resp_bits_ok; + wire _pipe_4_io_busy; + wire _pipe_3_io_sramRead_req_valid; + wire [9:0] _pipe_3_io_sramRead_req_bits_addr; + wire _pipe_3_io_sramRead_resp_ready; + wire _pipe_3_io_sramWrite_req_valid; + wire [9:0] _pipe_3_io_sramWrite_req_bits_addr; + wire _pipe_3_io_sramWrite_req_bits_mask_0; + wire _pipe_3_io_sramWrite_req_bits_mask_1; + wire _pipe_3_io_sramWrite_req_bits_mask_2; + wire _pipe_3_io_sramWrite_req_bits_mask_3; + wire _pipe_3_io_sramWrite_req_bits_mask_4; + wire _pipe_3_io_sramWrite_req_bits_mask_5; + wire _pipe_3_io_sramWrite_req_bits_mask_6; + wire _pipe_3_io_sramWrite_req_bits_mask_7; + wire [63:0] _pipe_3_io_sramWrite_req_bits_data; + wire _pipe_3_io_sramWrite_resp_ready; + wire _pipe_3_io_mem_req_write_req_ready; + wire _pipe_3_io_mem_req_write_resp_valid; + wire _pipe_3_io_mem_req_write_resp_bits_ok; + wire _pipe_3_io_busy; + wire _pipe_2_io_sramRead_req_valid; + wire [9:0] _pipe_2_io_sramRead_req_bits_addr; + wire _pipe_2_io_sramRead_resp_ready; + wire _pipe_2_io_sramWrite_req_valid; + wire [9:0] _pipe_2_io_sramWrite_req_bits_addr; + wire _pipe_2_io_sramWrite_req_bits_mask_0; + wire _pipe_2_io_sramWrite_req_bits_mask_1; + wire _pipe_2_io_sramWrite_req_bits_mask_2; + wire _pipe_2_io_sramWrite_req_bits_mask_3; + wire _pipe_2_io_sramWrite_req_bits_mask_4; + wire _pipe_2_io_sramWrite_req_bits_mask_5; + wire _pipe_2_io_sramWrite_req_bits_mask_6; + wire _pipe_2_io_sramWrite_req_bits_mask_7; + wire [63:0] _pipe_2_io_sramWrite_req_bits_data; + wire _pipe_2_io_sramWrite_resp_ready; + wire _pipe_2_io_mem_req_write_req_ready; + wire _pipe_2_io_mem_req_write_resp_valid; + wire _pipe_2_io_mem_req_write_resp_bits_ok; + wire _pipe_2_io_busy; + wire _pipe_1_io_sramRead_req_valid; + wire [9:0] _pipe_1_io_sramRead_req_bits_addr; + wire _pipe_1_io_sramRead_resp_ready; + wire _pipe_1_io_sramWrite_req_valid; + wire [9:0] _pipe_1_io_sramWrite_req_bits_addr; + wire _pipe_1_io_sramWrite_req_bits_mask_0; + wire _pipe_1_io_sramWrite_req_bits_mask_1; + wire _pipe_1_io_sramWrite_req_bits_mask_2; + wire _pipe_1_io_sramWrite_req_bits_mask_3; + wire _pipe_1_io_sramWrite_req_bits_mask_4; + wire _pipe_1_io_sramWrite_req_bits_mask_5; + wire _pipe_1_io_sramWrite_req_bits_mask_6; + wire _pipe_1_io_sramWrite_req_bits_mask_7; + wire [63:0] _pipe_1_io_sramWrite_req_bits_data; + wire _pipe_1_io_sramWrite_resp_ready; + wire _pipe_1_io_mem_req_read_req_ready; + wire _pipe_1_io_mem_req_read_resp_valid; + wire [63:0] _pipe_1_io_mem_req_read_resp_bits_data; + wire _pipe_1_io_busy; + wire _pipe_io_sramRead_req_valid; + wire [9:0] _pipe_io_sramRead_req_bits_addr; + wire _pipe_io_sramRead_resp_ready; + wire _pipe_io_sramWrite_req_valid; + wire [9:0] _pipe_io_sramWrite_req_bits_addr; + wire _pipe_io_sramWrite_req_bits_mask_0; + wire _pipe_io_sramWrite_req_bits_mask_1; + wire _pipe_io_sramWrite_req_bits_mask_2; + wire _pipe_io_sramWrite_req_bits_mask_3; + wire _pipe_io_sramWrite_req_bits_mask_4; + wire _pipe_io_sramWrite_req_bits_mask_5; + wire _pipe_io_sramWrite_req_bits_mask_6; + wire _pipe_io_sramWrite_req_bits_mask_7; + wire [63:0] _pipe_io_sramWrite_req_bits_data; + wire _pipe_io_sramWrite_resp_ready; + wire _pipe_io_mem_req_read_req_ready; + wire _pipe_io_mem_req_read_resp_valid; + wire [63:0] _pipe_io_mem_req_read_resp_bits_data; + wire _pipe_io_busy; + wire _midend_io_bankRead_0_bankRead_io_req_ready; + wire _midend_io_bankRead_0_bankRead_io_resp_valid; + wire [63:0] _midend_io_bankRead_0_bankRead_io_resp_bits_data; + wire _midend_io_bankRead_1_bankRead_io_req_ready; + wire _midend_io_bankRead_1_bankRead_io_resp_valid; + wire [63:0] _midend_io_bankRead_1_bankRead_io_resp_bits_data; + wire _midend_io_bankRead_2_bankRead_io_req_ready; + wire _midend_io_bankRead_2_bankRead_io_resp_valid; + wire [63:0] _midend_io_bankRead_2_bankRead_io_resp_bits_data; + wire _midend_io_bankWrite_0_bankWrite_io_req_ready; + wire _midend_io_bankWrite_0_bankWrite_io_resp_valid; + wire _midend_io_bankWrite_0_bankWrite_io_resp_bits_ok; + wire _midend_io_bankWrite_1_bankWrite_io_req_ready; + wire _midend_io_bankWrite_1_bankWrite_io_resp_valid; + wire _midend_io_bankWrite_1_bankWrite_io_resp_bits_ok; + wire _midend_io_bankWrite_2_bankWrite_io_req_ready; + wire _midend_io_bankWrite_2_bankWrite_io_resp_valid; + wire _midend_io_bankWrite_2_bankWrite_io_resp_bits_ok; + wire _midend_io_bankWrite_3_bankWrite_io_req_ready; + wire _midend_io_bankWrite_3_bankWrite_io_resp_valid; + wire _midend_io_bankWrite_3_bankWrite_io_resp_bits_ok; + wire _midend_io_bankWrite_4_bankWrite_io_req_ready; + wire _midend_io_bankWrite_4_bankWrite_io_resp_valid; + wire _midend_io_bankWrite_4_bankWrite_io_resp_bits_ok; + wire _midend_io_mem_req_0_read_req_valid; + wire [9:0] _midend_io_mem_req_0_read_req_bits_addr; + wire _midend_io_mem_req_0_read_resp_ready; + wire _midend_io_mem_req_1_read_req_valid; + wire [9:0] _midend_io_mem_req_1_read_req_bits_addr; + wire _midend_io_mem_req_1_read_resp_ready; + wire _midend_io_mem_req_2_write_req_valid; + wire [9:0] _midend_io_mem_req_2_write_req_bits_addr; + wire [63:0] _midend_io_mem_req_2_write_req_bits_data; + wire _midend_io_mem_req_2_write_resp_ready; + wire _midend_io_mem_req_3_write_req_valid; + wire [9:0] _midend_io_mem_req_3_write_req_bits_addr; + wire [63:0] _midend_io_mem_req_3_write_req_bits_data; + wire _midend_io_mem_req_3_write_resp_ready; + wire _midend_io_mem_req_4_write_req_valid; + wire [9:0] _midend_io_mem_req_4_write_req_bits_addr; + wire [63:0] _midend_io_mem_req_4_write_req_bits_data; + wire _midend_io_mem_req_4_write_resp_ready; + wire _midend_io_mem_req_5_write_req_valid; + wire [9:0] _midend_io_mem_req_5_write_req_bits_addr; + wire [63:0] _midend_io_mem_req_5_write_req_bits_data; + wire _midend_io_mem_req_5_write_resp_ready; + wire _midend_io_mem_req_6_write_req_valid; + wire [9:0] _midend_io_mem_req_6_write_req_bits_addr; + wire [63:0] _midend_io_mem_req_6_write_req_bits_data; + wire _midend_io_mem_req_6_write_resp_ready; + wire _midend_io_mem_req_6_read_req_valid; + wire [9:0] _midend_io_mem_req_6_read_req_bits_addr; + wire _midend_io_mem_req_6_read_resp_ready; + wire [3:0] _midend_io_mem_req_6_bank_id; + wire [3:0] _midend_io_mem_req_6_rob_id; + wire [63:0] _midend_io_mem_req_6_inst_id; + reg [15:0] cycle; + reg [6:0] readSent_0; + reg [6:0] readSent_1; + reg [6:0] readSent_2; + reg [6:0] readSeen_0; + reg [6:0] readSeen_1; + reg [6:0] readSeen_2; + reg [6:0] writeSent_0; + reg [6:0] writeSent_1; + reg [6:0] writeSent_2; + reg [6:0] writeSent_3; + reg [6:0] writeSent_4; + reg [6:0] writeSeen_0; + reg [6:0] writeSeen_1; + reg [6:0] writeSeen_2; + reg [6:0] writeSeen_3; + reg [6:0] writeSeen_4; + assign _readSent_0_6 = readSent_0[6]; + wire _GEN = cycle[1] & _midend_io_bankRead_0_bankRead_io_resp_valid; + assign _readSent_1_6 = readSent_1[6]; + wire _GEN_0 = cycle[2] & _midend_io_bankRead_1_bankRead_io_resp_valid; + assign _readSent_2_6 = readSent_2[6]; + wire _GEN_1 = cycle[3] & _midend_io_bankRead_2_bankRead_io_resp_valid; + assign _writeSent_0_6 = writeSent_0[6]; + wire _GEN_2 = cycle[2] & _midend_io_bankWrite_0_bankWrite_io_resp_valid; + assign _writeSent_1_6 = writeSent_1[6]; + wire _GEN_3 = cycle[3] & _midend_io_bankWrite_1_bankWrite_io_resp_valid; + assign _writeSent_2_6 = writeSent_2[6]; + wire _GEN_4 = cycle[4] & _midend_io_bankWrite_2_bankWrite_io_resp_valid; + assign _writeSent_3_6 = writeSent_3[6]; + wire _GEN_5 = cycle[0] & _midend_io_bankWrite_3_bankWrite_io_resp_valid; + wire _midend_io_bankWrite_4_bankWrite_io_req_valid_T_2 = + ~(writeSent_4[6]) & (|cycle); + wire _GEN_6 = cycle[1] & _midend_io_bankWrite_4_bankWrite_io_resp_valid; + reg readPending; + reg writePending; + reg [63:0] readData; + reg routePending; + wire _pipe_io_sramRead_req_ready_T_5 = + routePending & ~readPending & ~writePending & cycle[0]; + wire _pipe_io_sramWrite_req_ready_T_5 = + routePending & ~readPending & ~writePending & cycle[1]; + wire _pipe_io_sramRead_resp_valid_T_1 = readPending & cycle[3]; + wire _pipe_io_sramWrite_resp_valid_T_1 = writePending & cycle[4]; + wire _GEN_7 = _pipe_io_sramRead_req_ready_T_5 & _pipe_io_sramRead_req_valid; + wire _GEN_8 = _pipe_io_sramWrite_req_ready_T_5 & _pipe_io_sramWrite_req_valid; + reg readPending_1; + reg writePending_1; + reg [63:0] readData_1; + reg routePending_1; + wire _pipe_io_sramRead_req_ready_T_11 = + routePending_1 & ~readPending_1 & ~writePending_1 & cycle[1]; + wire _pipe_io_sramWrite_req_ready_T_11 = + routePending_1 & ~readPending_1 & ~writePending_1 & cycle[2]; + wire _pipe_io_sramRead_resp_valid_T_3 = readPending_1 & cycle[4]; + wire _pipe_io_sramWrite_resp_valid_T_3 = writePending_1 & cycle[0]; + wire _GEN_9 = _pipe_io_sramRead_req_ready_T_11 & _pipe_1_io_sramRead_req_valid; + wire _GEN_10 = + _pipe_io_sramWrite_req_ready_T_11 & _pipe_1_io_sramWrite_req_valid; + reg readPending_2; + reg writePending_2; + reg [63:0] readData_2; + reg routePending_2; + wire _pipe_io_sramRead_req_ready_T_17 = + routePending_2 & ~readPending_2 & ~writePending_2 & cycle[2]; + wire _pipe_io_sramWrite_req_ready_T_17 = + routePending_2 & ~readPending_2 & ~writePending_2 & cycle[3]; + wire _pipe_io_sramRead_resp_valid_T_5 = readPending_2 & cycle[0]; + wire _pipe_io_sramWrite_resp_valid_T_5 = writePending_2 & cycle[1]; + wire _GEN_11 = _pipe_io_sramRead_req_ready_T_17 & _pipe_2_io_sramRead_req_valid; + wire _GEN_12 = + _pipe_io_sramWrite_req_ready_T_17 & _pipe_2_io_sramWrite_req_valid; + reg readPending_3; + reg writePending_3; + reg [63:0] readData_3; + reg routePending_3; + wire _pipe_io_sramRead_req_ready_T_23 = + routePending_3 & ~readPending_3 & ~writePending_3 & cycle[3]; + wire _pipe_io_sramWrite_req_ready_T_23 = + routePending_3 & ~readPending_3 & ~writePending_3 & cycle[4]; + wire _pipe_io_sramRead_resp_valid_T_7 = readPending_3 & cycle[1]; + wire _pipe_io_sramWrite_resp_valid_T_7 = writePending_3 & cycle[2]; + wire _GEN_13 = _pipe_io_sramRead_req_ready_T_23 & _pipe_3_io_sramRead_req_valid; + wire _GEN_14 = + _pipe_io_sramWrite_req_ready_T_23 & _pipe_3_io_sramWrite_req_valid; + reg readPending_4; + reg writePending_4; + reg [63:0] readData_4; + reg routePending_4; + wire _pipe_io_sramRead_req_ready_T_29 = + routePending_4 & ~readPending_4 & ~writePending_4 & cycle[4]; + wire _pipe_io_sramWrite_req_ready_T_29 = + routePending_4 & ~readPending_4 & ~writePending_4 & cycle[0]; + wire _pipe_io_sramRead_resp_valid_T_9 = readPending_4 & cycle[2]; + wire _pipe_io_sramWrite_resp_valid_T_9 = writePending_4 & cycle[3]; + wire _GEN_15 = _pipe_io_sramRead_req_ready_T_29 & _pipe_4_io_sramRead_req_valid; + wire _GEN_16 = + _pipe_io_sramWrite_req_ready_T_29 & _pipe_4_io_sramWrite_req_valid; + reg readPending_5; + reg writePending_5; + reg [63:0] readData_5; + reg routePending_5; + wire _pipe_io_sramRead_req_ready_T_35 = + routePending_5 & ~readPending_5 & ~writePending_5 & cycle[0]; + wire _pipe_io_sramWrite_req_ready_T_35 = + routePending_5 & ~readPending_5 & ~writePending_5 & cycle[1]; + wire _pipe_io_sramRead_resp_valid_T_11 = readPending_5 & cycle[3]; + wire _pipe_io_sramWrite_resp_valid_T_11 = writePending_5 & cycle[4]; + wire _GEN_17 = _pipe_io_sramRead_req_ready_T_35 & _pipe_5_io_sramRead_req_valid; + wire _GEN_18 = + _pipe_io_sramWrite_req_ready_T_35 & _pipe_5_io_sramWrite_req_valid; + reg readPending_6; + reg writePending_6; + reg [63:0] readData_6; + reg routePending_6; + reg [3:0] routeBank_6; + wire _pipe_io_sramRead_req_ready_T_41 = + routePending_6 & ~readPending_6 & ~writePending_6 & cycle[1]; + wire _pipe_io_sramWrite_req_ready_T_41 = + routePending_6 & ~readPending_6 & ~writePending_6 & cycle[2]; + wire _pipe_io_sramRead_resp_valid_T_13 = readPending_6 & cycle[4]; + wire _pipe_io_sramWrite_resp_valid_T_13 = writePending_6 & cycle[0]; + wire _GEN_19 = _pipe_io_sramRead_req_ready_T_41 & _pipe_6_io_sramRead_req_valid; + wire _GEN_20 = + _pipe_io_sramWrite_req_ready_T_41 & _pipe_6_io_sramWrite_req_valid; + `ifndef SYNTHESIS + always @(posedge clock) begin + automatic logic _GEN_21 = _GEN_8 & ~reset; + automatic logic _GEN_22 = _GEN_10 & ~reset; + automatic logic _GEN_23 = _GEN_12 & ~reset; + automatic logic _GEN_24 = _GEN_14 & ~reset; + automatic logic _GEN_25 = _GEN_16 & ~reset; + automatic logic _GEN_26 = _GEN_18 & ~reset; + automatic logic _GEN_27 = _GEN_19 & ~reset; + automatic logic _GEN_28 = _midend_io_mem_req_6_bank_id != routeBank_6; + automatic logic _GEN_29 = _GEN_20 & ~reset; + if (~reset & cycle > 16'h4E1F) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: Routing regression timeout\n at EmitRoutingCheck.scala:17 assert(cycle < 20000.U, \"Routing regression timeout\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN & ~reset + & _midend_io_bankRead_0_bankRead_io_resp_bits_data != {57'h0, readSeen_0}) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: Read response lost or misrouted\n at EmitRoutingCheck.scala:42 assert(source.bankRead.io.resp.bits.data ===\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_0 & ~reset + & _midend_io_bankRead_1_bankRead_io_resp_bits_data != {47'h0, + {10'h0, readSeen_1} + - 17'h10000}) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: Read response lost or misrouted\n at EmitRoutingCheck.scala:42 assert(source.bankRead.io.resp.bits.data ===\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_1 & ~reset + & _midend_io_bankRead_2_bankRead_io_resp_bits_data != {45'h0, + {12'h0, readSeen_2} + - 19'h20000}) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: Read response lost or misrouted\n at EmitRoutingCheck.scala:42 assert(source.bankRead.io.resp.bits.data ===\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_2 & ~reset & ~_midend_io_bankWrite_0_bankWrite_io_resp_bits_ok) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: Write response lost or misrouted\n at EmitRoutingCheck.scala:63 assert(source.bankWrite.io.resp.bits.ok, \"Write response lost or misrouted\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_3 & ~reset & ~_midend_io_bankWrite_1_bankWrite_io_resp_bits_ok) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: Write response lost or misrouted\n at EmitRoutingCheck.scala:63 assert(source.bankWrite.io.resp.bits.ok, \"Write response lost or misrouted\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_4 & ~reset & ~_midend_io_bankWrite_2_bankWrite_io_resp_bits_ok) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: Write response lost or misrouted\n at EmitRoutingCheck.scala:63 assert(source.bankWrite.io.resp.bits.ok, \"Write response lost or misrouted\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_5 & ~reset & ~_midend_io_bankWrite_3_bankWrite_io_resp_bits_ok) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: Write response lost or misrouted\n at EmitRoutingCheck.scala:63 assert(source.bankWrite.io.resp.bits.ok, \"Write response lost or misrouted\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_6 & ~reset & ~_midend_io_bankWrite_4_bankWrite_io_resp_bits_ok) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: Write response lost or misrouted\n at EmitRoutingCheck.scala:63 assert(source.bankWrite.io.resp.bits.ok, \"Write response lost or misrouted\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_21 + & _pipe_io_sramWrite_req_bits_data != {54'h0, + _pipe_io_sramWrite_req_bits_addr}) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitRoutingCheck.scala:103 assert(pipe.io.sramWrite.req.bits.data ===\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_21 + & {_pipe_io_sramWrite_req_bits_mask_7, + _pipe_io_sramWrite_req_bits_mask_6, + _pipe_io_sramWrite_req_bits_mask_5, + _pipe_io_sramWrite_req_bits_mask_4, + _pipe_io_sramWrite_req_bits_mask_3, + _pipe_io_sramWrite_req_bits_mask_2, + _pipe_io_sramWrite_req_bits_mask_1, + _pipe_io_sramWrite_req_bits_mask_0} != 8'hFF) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitRoutingCheck.scala:105 assert(pipe.io.sramWrite.req.bits.mask.asUInt.andR)\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & _GEN_7 & _GEN_8) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitRoutingCheck.scala:113 assert(!(pipe.io.sramRead.req.fire && pipe.io.sramWrite.req.fire))\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_22 + & _pipe_1_io_sramWrite_req_bits_data != {47'h0, + {7'h0, + _pipe_1_io_sramWrite_req_bits_addr} + - 17'h10000}) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitRoutingCheck.scala:103 assert(pipe.io.sramWrite.req.bits.data ===\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_22 + & {_pipe_1_io_sramWrite_req_bits_mask_7, + _pipe_1_io_sramWrite_req_bits_mask_6, + _pipe_1_io_sramWrite_req_bits_mask_5, + _pipe_1_io_sramWrite_req_bits_mask_4, + _pipe_1_io_sramWrite_req_bits_mask_3, + _pipe_1_io_sramWrite_req_bits_mask_2, + _pipe_1_io_sramWrite_req_bits_mask_1, + _pipe_1_io_sramWrite_req_bits_mask_0} != 8'hFF) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitRoutingCheck.scala:105 assert(pipe.io.sramWrite.req.bits.mask.asUInt.andR)\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_22) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitRoutingCheck.scala:108 assert(request.rob_id === (port %%%% 4).U)\n"); + if (`STOP_COND_) + $fatal; + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitRoutingCheck.scala:109 assert(request.inst_id === (100 + port %%%% 4).U)\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & _GEN_9 & _GEN_10) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitRoutingCheck.scala:113 assert(!(pipe.io.sramRead.req.fire && pipe.io.sramWrite.req.fire))\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_11 & ~reset) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitRoutingCheck.scala:93 assert(request.bank_id === (if (channel < 2) channel else 6).U)\n"); + if (`STOP_COND_) + $fatal; + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitRoutingCheck.scala:95 assert(request.rob_id === (if (channel < 2) channel else 2).U)\n"); + if (`STOP_COND_) + $fatal; + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitRoutingCheck.scala:96 assert(request.inst_id === (if (channel < 2) 100 + channel else 102).U)\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_23 + & _pipe_2_io_sramWrite_req_bits_data != {46'h0, + {8'h0, + _pipe_2_io_sramWrite_req_bits_addr} + - 18'h20000}) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitRoutingCheck.scala:103 assert(pipe.io.sramWrite.req.bits.data ===\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_23 + & {_pipe_2_io_sramWrite_req_bits_mask_7, + _pipe_2_io_sramWrite_req_bits_mask_6, + _pipe_2_io_sramWrite_req_bits_mask_5, + _pipe_2_io_sramWrite_req_bits_mask_4, + _pipe_2_io_sramWrite_req_bits_mask_3, + _pipe_2_io_sramWrite_req_bits_mask_2, + _pipe_2_io_sramWrite_req_bits_mask_1, + _pipe_2_io_sramWrite_req_bits_mask_0} != 8'hFF) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitRoutingCheck.scala:105 assert(pipe.io.sramWrite.req.bits.mask.asUInt.andR)\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & _GEN_11 & _GEN_12) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitRoutingCheck.scala:113 assert(!(pipe.io.sramRead.req.fire && pipe.io.sramWrite.req.fire))\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_13 & ~reset) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitRoutingCheck.scala:93 assert(request.bank_id === (if (channel < 2) channel else 6).U)\n"); + if (`STOP_COND_) + $fatal; + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitRoutingCheck.scala:94 assert(request.group_id === 0.U)\n"); + if (`STOP_COND_) + $fatal; + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitRoutingCheck.scala:95 assert(request.rob_id === (if (channel < 2) channel else 2).U)\n"); + if (`STOP_COND_) + $fatal; + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitRoutingCheck.scala:96 assert(request.inst_id === (if (channel < 2) 100 + channel else 102).U)\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_24 + & _pipe_3_io_sramWrite_req_bits_data != {46'h0, + {8'h0, + _pipe_3_io_sramWrite_req_bits_addr} + - 18'h10000}) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitRoutingCheck.scala:103 assert(pipe.io.sramWrite.req.bits.data ===\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_24 + & {_pipe_3_io_sramWrite_req_bits_mask_7, + _pipe_3_io_sramWrite_req_bits_mask_6, + _pipe_3_io_sramWrite_req_bits_mask_5, + _pipe_3_io_sramWrite_req_bits_mask_4, + _pipe_3_io_sramWrite_req_bits_mask_3, + _pipe_3_io_sramWrite_req_bits_mask_2, + _pipe_3_io_sramWrite_req_bits_mask_1, + _pipe_3_io_sramWrite_req_bits_mask_0} != 8'hFF) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitRoutingCheck.scala:105 assert(pipe.io.sramWrite.req.bits.mask.asUInt.andR)\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & _GEN_13 & _GEN_14) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitRoutingCheck.scala:113 assert(!(pipe.io.sramRead.req.fire && pipe.io.sramWrite.req.fire))\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_15 & ~reset) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitRoutingCheck.scala:93 assert(request.bank_id === (if (channel < 2) channel else 6).U)\n"); + if (`STOP_COND_) + $fatal; + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitRoutingCheck.scala:94 assert(request.group_id === 0.U)\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_25 + & _pipe_4_io_sramWrite_req_bits_data != {45'h0, + {9'h0, + _pipe_4_io_sramWrite_req_bits_addr} + - 19'h40000}) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitRoutingCheck.scala:103 assert(pipe.io.sramWrite.req.bits.data ===\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_25 + & {_pipe_4_io_sramWrite_req_bits_mask_7, + _pipe_4_io_sramWrite_req_bits_mask_6, + _pipe_4_io_sramWrite_req_bits_mask_5, + _pipe_4_io_sramWrite_req_bits_mask_4, + _pipe_4_io_sramWrite_req_bits_mask_3, + _pipe_4_io_sramWrite_req_bits_mask_2, + _pipe_4_io_sramWrite_req_bits_mask_1, + _pipe_4_io_sramWrite_req_bits_mask_0} != 8'hFF) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitRoutingCheck.scala:105 assert(pipe.io.sramWrite.req.bits.mask.asUInt.andR)\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & _GEN_15 & _GEN_16) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitRoutingCheck.scala:113 assert(!(pipe.io.sramRead.req.fire && pipe.io.sramWrite.req.fire))\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_17 & ~reset) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitRoutingCheck.scala:93 assert(request.bank_id === (if (channel < 2) channel else 6).U)\n"); + if (`STOP_COND_) + $fatal; + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitRoutingCheck.scala:94 assert(request.group_id === 0.U)\n"); + if (`STOP_COND_) + $fatal; + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitRoutingCheck.scala:95 assert(request.rob_id === (if (channel < 2) channel else 2).U)\n"); + if (`STOP_COND_) + $fatal; + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitRoutingCheck.scala:96 assert(request.inst_id === (if (channel < 2) 100 + channel else 102).U)\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_26 + & _pipe_5_io_sramWrite_req_bits_data != {45'h0, + {9'h0, + _pipe_5_io_sramWrite_req_bits_addr} + - 19'h30000}) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitRoutingCheck.scala:103 assert(pipe.io.sramWrite.req.bits.data ===\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_26 + & {_pipe_5_io_sramWrite_req_bits_mask_7, + _pipe_5_io_sramWrite_req_bits_mask_6, + _pipe_5_io_sramWrite_req_bits_mask_5, + _pipe_5_io_sramWrite_req_bits_mask_4, + _pipe_5_io_sramWrite_req_bits_mask_3, + _pipe_5_io_sramWrite_req_bits_mask_2, + _pipe_5_io_sramWrite_req_bits_mask_1, + _pipe_5_io_sramWrite_req_bits_mask_0} != 8'hFF) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitRoutingCheck.scala:105 assert(pipe.io.sramWrite.req.bits.mask.asUInt.andR)\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & _GEN_17 & _GEN_18) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitRoutingCheck.scala:113 assert(!(pipe.io.sramRead.req.fire && pipe.io.sramWrite.req.fire))\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_27 & _GEN_28) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: Route metadata changed before SRAM acceptance\n at EmitRoutingCheck.scala:92 assert(request.bank_id === routeBank, \"Route metadata changed before SRAM acceptance\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_27 & _midend_io_mem_req_6_bank_id != 4'h6) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitRoutingCheck.scala:93 assert(request.bank_id === (if (channel < 2) channel else 6).U)\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_27 & _midend_io_mem_req_6_rob_id != 4'h2) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitRoutingCheck.scala:95 assert(request.rob_id === (if (channel < 2) channel else 2).U)\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_27 & _midend_io_mem_req_6_inst_id != 64'h66) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitRoutingCheck.scala:96 assert(request.inst_id === (if (channel < 2) 100 + channel else 102).U)\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_29 & _GEN_28) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: Write replaced a pending read route\n at EmitRoutingCheck.scala:100 assert(request.bank_id === routeBank, \"Write replaced a pending read route\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_29 & _midend_io_mem_req_6_bank_id != 4'h7) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: Wrong write bank metadata\n at EmitRoutingCheck.scala:102 assert(request.bank_id === bank.U, \"Wrong write bank metadata\")\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_29 + & _pipe_6_io_sramWrite_req_bits_data != {45'h0, + {9'h0, + _pipe_6_io_sramWrite_req_bits_addr} + - 19'h10000}) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitRoutingCheck.scala:103 assert(pipe.io.sramWrite.req.bits.data ===\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_29 + & {_pipe_6_io_sramWrite_req_bits_mask_7, + _pipe_6_io_sramWrite_req_bits_mask_6, + _pipe_6_io_sramWrite_req_bits_mask_5, + _pipe_6_io_sramWrite_req_bits_mask_4, + _pipe_6_io_sramWrite_req_bits_mask_3, + _pipe_6_io_sramWrite_req_bits_mask_2, + _pipe_6_io_sramWrite_req_bits_mask_1, + _pipe_6_io_sramWrite_req_bits_mask_0} != 8'hFF) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitRoutingCheck.scala:105 assert(pipe.io.sramWrite.req.bits.mask.asUInt.andR)\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_29 & (|_midend_io_mem_req_6_rob_id)) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitRoutingCheck.scala:108 assert(request.rob_id === (port %%%% 4).U)\n"); + if (`STOP_COND_) + $fatal; + end + if (_GEN_29 & _midend_io_mem_req_6_inst_id != 64'h64) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitRoutingCheck.scala:109 assert(request.inst_id === (100 + port %%%% 4).U)\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & _GEN_19 & _GEN_20) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed\n at EmitRoutingCheck.scala:113 assert(!(pipe.io.sramRead.req.fire && pipe.io.sramWrite.req.fire))\n"); + if (`STOP_COND_) + $fatal; + end + end // always @(posedge) + `endif // not def SYNTHESIS + always @(posedge clock) begin + automatic logic _GEN_30; + _GEN_30 = + ~routePending_6 & ~_pipe_6_io_busy + & (_midend_io_mem_req_6_read_req_valid | _midend_io_mem_req_6_write_req_valid); + if (reset) begin + cycle <= 16'h0; + readSent_0 <= 7'h0; + readSent_1 <= 7'h0; + readSent_2 <= 7'h0; + readSeen_0 <= 7'h0; + readSeen_1 <= 7'h0; + readSeen_2 <= 7'h0; + writeSent_0 <= 7'h0; + writeSent_1 <= 7'h0; + writeSent_2 <= 7'h0; + writeSent_3 <= 7'h0; + writeSent_4 <= 7'h0; + writeSeen_0 <= 7'h0; + writeSeen_1 <= 7'h0; + writeSeen_2 <= 7'h0; + writeSeen_3 <= 7'h0; + writeSeen_4 <= 7'h0; + readPending <= 1'h0; + writePending <= 1'h0; + routePending <= 1'h0; + readPending_1 <= 1'h0; + writePending_1 <= 1'h0; + routePending_1 <= 1'h0; + readPending_2 <= 1'h0; + writePending_2 <= 1'h0; + routePending_2 <= 1'h0; + readPending_3 <= 1'h0; + writePending_3 <= 1'h0; + routePending_3 <= 1'h0; + readPending_4 <= 1'h0; + writePending_4 <= 1'h0; + routePending_4 <= 1'h0; + readPending_5 <= 1'h0; + writePending_5 <= 1'h0; + routePending_5 <= 1'h0; + readPending_6 <= 1'h0; + writePending_6 <= 1'h0; + routePending_6 <= 1'h0; + end + else begin + cycle <= cycle + 16'h1; + if (_midend_io_bankRead_0_bankRead_io_req_ready & ~_readSent_0_6) + readSent_0 <= readSent_0 + 7'h1; + if (_midend_io_bankRead_1_bankRead_io_req_ready & ~_readSent_1_6) + readSent_1 <= readSent_1 + 7'h1; + if (_midend_io_bankRead_2_bankRead_io_req_ready & ~_readSent_2_6) + readSent_2 <= readSent_2 + 7'h1; + if (_GEN) + readSeen_0 <= readSeen_0 + 7'h1; + if (_GEN_0) + readSeen_1 <= readSeen_1 + 7'h1; + if (_GEN_1) + readSeen_2 <= readSeen_2 + 7'h1; + if (_midend_io_bankWrite_0_bankWrite_io_req_ready & ~_writeSent_0_6) + writeSent_0 <= writeSent_0 + 7'h1; + if (_midend_io_bankWrite_1_bankWrite_io_req_ready & ~_writeSent_1_6) + writeSent_1 <= writeSent_1 + 7'h1; + if (_midend_io_bankWrite_2_bankWrite_io_req_ready & ~_writeSent_2_6) + writeSent_2 <= writeSent_2 + 7'h1; + if (_midend_io_bankWrite_3_bankWrite_io_req_ready & ~_writeSent_3_6) + writeSent_3 <= writeSent_3 + 7'h1; + if (_midend_io_bankWrite_4_bankWrite_io_req_ready + & _midend_io_bankWrite_4_bankWrite_io_req_valid_T_2) + writeSent_4 <= writeSent_4 + 7'h1; + if (_GEN_2) + writeSeen_0 <= writeSeen_0 + 7'h1; + if (_GEN_3) + writeSeen_1 <= writeSeen_1 + 7'h1; + if (_GEN_4) + writeSeen_2 <= writeSeen_2 + 7'h1; + if (_GEN_5) + writeSeen_3 <= writeSeen_3 + 7'h1; + if (_GEN_6) + writeSeen_4 <= writeSeen_4 + 7'h1; + readPending <= + ~(_pipe_io_sramRead_resp_ready & _pipe_io_sramRead_resp_valid_T_1) + & (_GEN_7 | readPending); + writePending <= + ~(_pipe_io_sramWrite_resp_ready & _pipe_io_sramWrite_resp_valid_T_1) + & (_GEN_8 | writePending); + routePending <= + ~(_pipe_io_mem_req_read_req_ready & _midend_io_mem_req_0_read_req_valid) + & (~routePending & ~_pipe_io_busy & _midend_io_mem_req_0_read_req_valid + | routePending); + readPending_1 <= + ~(_pipe_1_io_sramRead_resp_ready & _pipe_io_sramRead_resp_valid_T_3) + & (_GEN_9 | readPending_1); + writePending_1 <= + ~(_pipe_1_io_sramWrite_resp_ready & _pipe_io_sramWrite_resp_valid_T_3) + & (_GEN_10 | writePending_1); + routePending_1 <= + ~(_pipe_1_io_mem_req_read_req_ready & _midend_io_mem_req_1_read_req_valid) + & (~routePending_1 & ~_pipe_1_io_busy & _midend_io_mem_req_1_read_req_valid + | routePending_1); + readPending_2 <= + ~(_pipe_2_io_sramRead_resp_ready & _pipe_io_sramRead_resp_valid_T_5) + & (_GEN_11 | readPending_2); + writePending_2 <= + ~(_pipe_2_io_sramWrite_resp_ready & _pipe_io_sramWrite_resp_valid_T_5) + & (_GEN_12 | writePending_2); + routePending_2 <= + ~(_pipe_2_io_mem_req_write_req_ready & _midend_io_mem_req_2_write_req_valid) + & (~routePending_2 & ~_pipe_2_io_busy & _midend_io_mem_req_2_write_req_valid + | routePending_2); + readPending_3 <= + ~(_pipe_3_io_sramRead_resp_ready & _pipe_io_sramRead_resp_valid_T_7) + & (_GEN_13 | readPending_3); + writePending_3 <= + ~(_pipe_3_io_sramWrite_resp_ready & _pipe_io_sramWrite_resp_valid_T_7) + & (_GEN_14 | writePending_3); + routePending_3 <= + ~(_pipe_3_io_mem_req_write_req_ready & _midend_io_mem_req_3_write_req_valid) + & (~routePending_3 & ~_pipe_3_io_busy & _midend_io_mem_req_3_write_req_valid + | routePending_3); + readPending_4 <= + ~(_pipe_4_io_sramRead_resp_ready & _pipe_io_sramRead_resp_valid_T_9) + & (_GEN_15 | readPending_4); + writePending_4 <= + ~(_pipe_4_io_sramWrite_resp_ready & _pipe_io_sramWrite_resp_valid_T_9) + & (_GEN_16 | writePending_4); + routePending_4 <= + ~(_pipe_4_io_mem_req_write_req_ready & _midend_io_mem_req_4_write_req_valid) + & (~routePending_4 & ~_pipe_4_io_busy & _midend_io_mem_req_4_write_req_valid + | routePending_4); + readPending_5 <= + ~(_pipe_5_io_sramRead_resp_ready & _pipe_io_sramRead_resp_valid_T_11) + & (_GEN_17 | readPending_5); + writePending_5 <= + ~(_pipe_5_io_sramWrite_resp_ready & _pipe_io_sramWrite_resp_valid_T_11) + & (_GEN_18 | writePending_5); + routePending_5 <= + ~(_pipe_5_io_mem_req_write_req_ready & _midend_io_mem_req_5_write_req_valid) + & (~routePending_5 & ~_pipe_5_io_busy & _midend_io_mem_req_5_write_req_valid + | routePending_5); + readPending_6 <= + ~(_pipe_6_io_sramRead_resp_ready & _pipe_io_sramRead_resp_valid_T_13) + & (_GEN_19 | readPending_6); + writePending_6 <= + ~(_pipe_6_io_sramWrite_resp_ready & _pipe_io_sramWrite_resp_valid_T_13) + & (_GEN_20 | writePending_6); + routePending_6 <= + ~(_pipe_6_io_mem_req_read_req_ready & _midend_io_mem_req_6_read_req_valid + | _pipe_6_io_mem_req_write_req_ready & _midend_io_mem_req_6_write_req_valid) + & (_GEN_30 | routePending_6); + end + if (_GEN_7) + readData <= {54'h0, _pipe_io_sramRead_req_bits_addr}; + if (_GEN_9) + readData_1 <= {44'h0, {10'h0, _pipe_1_io_sramRead_req_bits_addr} + 20'h10000}; + if (_GEN_11) + readData_2 <= {44'h0, {10'h0, _pipe_2_io_sramRead_req_bits_addr} + 20'h20000}; + if (_GEN_13) + readData_3 <= {44'h0, {10'h0, _pipe_3_io_sramRead_req_bits_addr} + 20'h30000}; + if (_GEN_15) + readData_4 <= {44'h0, {10'h0, _pipe_4_io_sramRead_req_bits_addr} + 20'h40000}; + if (_GEN_17) + readData_5 <= {44'h0, {10'h0, _pipe_5_io_sramRead_req_bits_addr} + 20'h50000}; + if (_GEN_19) + readData_6 <= + {44'h0, {10'h0, _pipe_6_io_sramRead_req_bits_addr} + {routeBank_6, 16'h0}}; + if (_GEN_30) + routeBank_6 <= _midend_io_mem_req_6_bank_id; + end // always @(posedge) + MemMidend midend ( + .clock (clock), + .reset (reset), + .io_bankRead_0_bankRead_io_req_ready + (_midend_io_bankRead_0_bankRead_io_req_ready), + .io_bankRead_0_bankRead_io_req_valid (~_readSent_0_6), + .io_bankRead_0_bankRead_io_req_bits_addr ({3'h0, readSent_0}), + .io_bankRead_0_bankRead_io_resp_ready (cycle[1]), + .io_bankRead_0_bankRead_io_resp_valid + (_midend_io_bankRead_0_bankRead_io_resp_valid), + .io_bankRead_0_bankRead_io_resp_bits_data + (_midend_io_bankRead_0_bankRead_io_resp_bits_data), + .io_bankRead_1_bankRead_io_req_ready + (_midend_io_bankRead_1_bankRead_io_req_ready), + .io_bankRead_1_bankRead_io_req_valid (~_readSent_1_6), + .io_bankRead_1_bankRead_io_req_bits_addr ({3'h0, readSent_1}), + .io_bankRead_1_bankRead_io_resp_ready (cycle[2]), + .io_bankRead_1_bankRead_io_resp_valid + (_midend_io_bankRead_1_bankRead_io_resp_valid), + .io_bankRead_1_bankRead_io_resp_bits_data + (_midend_io_bankRead_1_bankRead_io_resp_bits_data), + .io_bankRead_2_bankRead_io_req_ready + (_midend_io_bankRead_2_bankRead_io_req_ready), + .io_bankRead_2_bankRead_io_req_valid (~_readSent_2_6), + .io_bankRead_2_bankRead_io_req_bits_addr ({3'h0, readSent_2}), + .io_bankRead_2_bankRead_io_resp_ready (cycle[3]), + .io_bankRead_2_bankRead_io_resp_valid + (_midend_io_bankRead_2_bankRead_io_resp_valid), + .io_bankRead_2_bankRead_io_resp_bits_data + (_midend_io_bankRead_2_bankRead_io_resp_bits_data), + .io_bankWrite_0_bankWrite_io_req_ready + (_midend_io_bankWrite_0_bankWrite_io_req_ready), + .io_bankWrite_0_bankWrite_io_req_valid (~_writeSent_0_6), + .io_bankWrite_0_bankWrite_io_req_bits_addr ({3'h0, writeSent_0}), + .io_bankWrite_0_bankWrite_io_req_bits_data + ({46'h0, {11'h0, writeSent_0} - 18'h20000}), + .io_bankWrite_0_bankWrite_io_resp_ready (cycle[2]), + .io_bankWrite_0_bankWrite_io_resp_valid + (_midend_io_bankWrite_0_bankWrite_io_resp_valid), + .io_bankWrite_0_bankWrite_io_resp_bits_ok + (_midend_io_bankWrite_0_bankWrite_io_resp_bits_ok), + .io_bankWrite_1_bankWrite_io_req_ready + (_midend_io_bankWrite_1_bankWrite_io_req_ready), + .io_bankWrite_1_bankWrite_io_req_valid (~_writeSent_1_6), + .io_bankWrite_1_bankWrite_io_req_bits_addr ({3'h0, writeSent_1}), + .io_bankWrite_1_bankWrite_io_req_bits_data + ({46'h0, {11'h0, writeSent_1} - 18'h10000}), + .io_bankWrite_1_bankWrite_io_resp_ready (cycle[3]), + .io_bankWrite_1_bankWrite_io_resp_valid + (_midend_io_bankWrite_1_bankWrite_io_resp_valid), + .io_bankWrite_1_bankWrite_io_resp_bits_ok + (_midend_io_bankWrite_1_bankWrite_io_resp_bits_ok), + .io_bankWrite_2_bankWrite_io_req_ready + (_midend_io_bankWrite_2_bankWrite_io_req_ready), + .io_bankWrite_2_bankWrite_io_req_valid (~_writeSent_2_6), + .io_bankWrite_2_bankWrite_io_req_bits_addr ({3'h0, writeSent_2}), + .io_bankWrite_2_bankWrite_io_req_bits_data + ({45'h0, {12'h0, writeSent_2} - 19'h40000}), + .io_bankWrite_2_bankWrite_io_resp_ready (cycle[4]), + .io_bankWrite_2_bankWrite_io_resp_valid + (_midend_io_bankWrite_2_bankWrite_io_resp_valid), + .io_bankWrite_2_bankWrite_io_resp_bits_ok + (_midend_io_bankWrite_2_bankWrite_io_resp_bits_ok), + .io_bankWrite_3_bankWrite_io_req_ready + (_midend_io_bankWrite_3_bankWrite_io_req_ready), + .io_bankWrite_3_bankWrite_io_req_valid (~_writeSent_3_6), + .io_bankWrite_3_bankWrite_io_req_bits_addr ({3'h0, writeSent_3}), + .io_bankWrite_3_bankWrite_io_req_bits_data + ({45'h0, {12'h0, writeSent_3} - 19'h30000}), + .io_bankWrite_3_bankWrite_io_resp_ready (cycle[0]), + .io_bankWrite_3_bankWrite_io_resp_valid + (_midend_io_bankWrite_3_bankWrite_io_resp_valid), + .io_bankWrite_3_bankWrite_io_resp_bits_ok + (_midend_io_bankWrite_3_bankWrite_io_resp_bits_ok), + .io_bankWrite_4_bankWrite_io_req_ready + (_midend_io_bankWrite_4_bankWrite_io_req_ready), + .io_bankWrite_4_bankWrite_io_req_valid + (_midend_io_bankWrite_4_bankWrite_io_req_valid_T_2), + .io_bankWrite_4_bankWrite_io_req_bits_addr ({3'h0, writeSent_4}), + .io_bankWrite_4_bankWrite_io_req_bits_data + ({45'h0, {12'h0, writeSent_4} - 19'h10000}), + .io_bankWrite_4_bankWrite_io_resp_ready (cycle[1]), + .io_bankWrite_4_bankWrite_io_resp_valid + (_midend_io_bankWrite_4_bankWrite_io_resp_valid), + .io_bankWrite_4_bankWrite_io_resp_bits_ok + (_midend_io_bankWrite_4_bankWrite_io_resp_bits_ok), + .io_ballChannelActive_0 + (~(readSent_0 == 7'h40 & readSent_1 == 7'h40 & writeSent_0 == 7'h40 + & writeSent_1 == 7'h40 & writeSent_2 == 7'h40 & writeSent_3 == 7'h40)), + .io_mem_req_0_read_req_ready (_pipe_io_mem_req_read_req_ready), + .io_mem_req_0_read_req_valid (_midend_io_mem_req_0_read_req_valid), + .io_mem_req_0_read_req_bits_addr (_midend_io_mem_req_0_read_req_bits_addr), + .io_mem_req_0_read_resp_ready (_midend_io_mem_req_0_read_resp_ready), + .io_mem_req_0_read_resp_valid (_pipe_io_mem_req_read_resp_valid), + .io_mem_req_0_read_resp_bits_data (_pipe_io_mem_req_read_resp_bits_data), + .io_mem_req_1_read_req_ready (_pipe_1_io_mem_req_read_req_ready), + .io_mem_req_1_read_req_valid (_midend_io_mem_req_1_read_req_valid), + .io_mem_req_1_read_req_bits_addr (_midend_io_mem_req_1_read_req_bits_addr), + .io_mem_req_1_read_resp_ready (_midend_io_mem_req_1_read_resp_ready), + .io_mem_req_1_read_resp_valid (_pipe_1_io_mem_req_read_resp_valid), + .io_mem_req_1_read_resp_bits_data (_pipe_1_io_mem_req_read_resp_bits_data), + .io_mem_req_2_write_req_ready (_pipe_2_io_mem_req_write_req_ready), + .io_mem_req_2_write_req_valid (_midend_io_mem_req_2_write_req_valid), + .io_mem_req_2_write_req_bits_addr (_midend_io_mem_req_2_write_req_bits_addr), + .io_mem_req_2_write_req_bits_data (_midend_io_mem_req_2_write_req_bits_data), + .io_mem_req_2_write_resp_ready (_midend_io_mem_req_2_write_resp_ready), + .io_mem_req_2_write_resp_valid (_pipe_2_io_mem_req_write_resp_valid), + .io_mem_req_2_write_resp_bits_ok (_pipe_2_io_mem_req_write_resp_bits_ok), + .io_mem_req_3_write_req_ready (_pipe_3_io_mem_req_write_req_ready), + .io_mem_req_3_write_req_valid (_midend_io_mem_req_3_write_req_valid), + .io_mem_req_3_write_req_bits_addr (_midend_io_mem_req_3_write_req_bits_addr), + .io_mem_req_3_write_req_bits_data (_midend_io_mem_req_3_write_req_bits_data), + .io_mem_req_3_write_resp_ready (_midend_io_mem_req_3_write_resp_ready), + .io_mem_req_3_write_resp_valid (_pipe_3_io_mem_req_write_resp_valid), + .io_mem_req_3_write_resp_bits_ok (_pipe_3_io_mem_req_write_resp_bits_ok), + .io_mem_req_4_write_req_ready (_pipe_4_io_mem_req_write_req_ready), + .io_mem_req_4_write_req_valid (_midend_io_mem_req_4_write_req_valid), + .io_mem_req_4_write_req_bits_addr (_midend_io_mem_req_4_write_req_bits_addr), + .io_mem_req_4_write_req_bits_data (_midend_io_mem_req_4_write_req_bits_data), + .io_mem_req_4_write_resp_ready (_midend_io_mem_req_4_write_resp_ready), + .io_mem_req_4_write_resp_valid (_pipe_4_io_mem_req_write_resp_valid), + .io_mem_req_4_write_resp_bits_ok (_pipe_4_io_mem_req_write_resp_bits_ok), + .io_mem_req_5_write_req_ready (_pipe_5_io_mem_req_write_req_ready), + .io_mem_req_5_write_req_valid (_midend_io_mem_req_5_write_req_valid), + .io_mem_req_5_write_req_bits_addr (_midend_io_mem_req_5_write_req_bits_addr), + .io_mem_req_5_write_req_bits_data (_midend_io_mem_req_5_write_req_bits_data), + .io_mem_req_5_write_resp_ready (_midend_io_mem_req_5_write_resp_ready), + .io_mem_req_5_write_resp_valid (_pipe_5_io_mem_req_write_resp_valid), + .io_mem_req_5_write_resp_bits_ok (_pipe_5_io_mem_req_write_resp_bits_ok), + .io_mem_req_6_write_req_ready (_pipe_6_io_mem_req_write_req_ready), + .io_mem_req_6_write_req_valid (_midend_io_mem_req_6_write_req_valid), + .io_mem_req_6_write_req_bits_addr (_midend_io_mem_req_6_write_req_bits_addr), + .io_mem_req_6_write_req_bits_data (_midend_io_mem_req_6_write_req_bits_data), + .io_mem_req_6_write_resp_ready (_midend_io_mem_req_6_write_resp_ready), + .io_mem_req_6_write_resp_valid (_pipe_6_io_mem_req_write_resp_valid), + .io_mem_req_6_write_resp_bits_ok (_pipe_6_io_mem_req_write_resp_bits_ok), + .io_mem_req_6_read_req_ready (_pipe_6_io_mem_req_read_req_ready), + .io_mem_req_6_read_req_valid (_midend_io_mem_req_6_read_req_valid), + .io_mem_req_6_read_req_bits_addr (_midend_io_mem_req_6_read_req_bits_addr), + .io_mem_req_6_read_resp_ready (_midend_io_mem_req_6_read_resp_ready), + .io_mem_req_6_read_resp_valid (_pipe_6_io_mem_req_read_resp_valid), + .io_mem_req_6_read_resp_bits_data (_pipe_6_io_mem_req_read_resp_bits_data), + .io_mem_req_6_bank_id (_midend_io_mem_req_6_bank_id), + .io_mem_req_6_rob_id (_midend_io_mem_req_6_rob_id), + .io_mem_req_6_inst_id (_midend_io_mem_req_6_inst_id) + ); + AccPipe pipe ( + .clock (clock), + .reset (reset), + .io_sramRead_req_ready (_pipe_io_sramRead_req_ready_T_5), + .io_sramRead_req_valid (_pipe_io_sramRead_req_valid), + .io_sramRead_req_bits_addr (_pipe_io_sramRead_req_bits_addr), + .io_sramRead_resp_ready (_pipe_io_sramRead_resp_ready), + .io_sramRead_resp_valid (_pipe_io_sramRead_resp_valid_T_1), + .io_sramRead_resp_bits_data (readData), + .io_sramWrite_req_ready (_pipe_io_sramWrite_req_ready_T_5), + .io_sramWrite_req_valid (_pipe_io_sramWrite_req_valid), + .io_sramWrite_req_bits_addr (_pipe_io_sramWrite_req_bits_addr), + .io_sramWrite_req_bits_mask_0 (_pipe_io_sramWrite_req_bits_mask_0), + .io_sramWrite_req_bits_mask_1 (_pipe_io_sramWrite_req_bits_mask_1), + .io_sramWrite_req_bits_mask_2 (_pipe_io_sramWrite_req_bits_mask_2), + .io_sramWrite_req_bits_mask_3 (_pipe_io_sramWrite_req_bits_mask_3), + .io_sramWrite_req_bits_mask_4 (_pipe_io_sramWrite_req_bits_mask_4), + .io_sramWrite_req_bits_mask_5 (_pipe_io_sramWrite_req_bits_mask_5), + .io_sramWrite_req_bits_mask_6 (_pipe_io_sramWrite_req_bits_mask_6), + .io_sramWrite_req_bits_mask_7 (_pipe_io_sramWrite_req_bits_mask_7), + .io_sramWrite_req_bits_data (_pipe_io_sramWrite_req_bits_data), + .io_sramWrite_resp_ready (_pipe_io_sramWrite_resp_ready), + .io_sramWrite_resp_valid (_pipe_io_sramWrite_resp_valid_T_1), + .io_mem_req_write_req_ready (/* unused */), + .io_mem_req_write_req_valid (1'h0), + .io_mem_req_write_req_bits_addr (10'h0), + .io_mem_req_write_req_bits_mask_0 (1'h0), + .io_mem_req_write_req_bits_mask_1 (1'h0), + .io_mem_req_write_req_bits_mask_2 (1'h0), + .io_mem_req_write_req_bits_mask_3 (1'h0), + .io_mem_req_write_req_bits_mask_4 (1'h0), + .io_mem_req_write_req_bits_mask_5 (1'h0), + .io_mem_req_write_req_bits_mask_6 (1'h0), + .io_mem_req_write_req_bits_mask_7 (1'h0), + .io_mem_req_write_req_bits_data (64'h0), + .io_mem_req_write_resp_ready (1'h0), + .io_mem_req_write_resp_valid (/* unused */), + .io_mem_req_write_resp_bits_ok (/* unused */), + .io_mem_req_read_req_ready (_pipe_io_mem_req_read_req_ready), + .io_mem_req_read_req_valid (_midend_io_mem_req_0_read_req_valid), + .io_mem_req_read_req_bits_addr (_midend_io_mem_req_0_read_req_bits_addr), + .io_mem_req_read_resp_ready (_midend_io_mem_req_0_read_resp_ready), + .io_mem_req_read_resp_valid (_pipe_io_mem_req_read_resp_valid), + .io_mem_req_read_resp_bits_data (_pipe_io_mem_req_read_resp_bits_data), + .io_busy (_pipe_io_busy) + ); + AccPipe pipe_1 ( + .clock (clock), + .reset (reset), + .io_sramRead_req_ready (_pipe_io_sramRead_req_ready_T_11), + .io_sramRead_req_valid (_pipe_1_io_sramRead_req_valid), + .io_sramRead_req_bits_addr (_pipe_1_io_sramRead_req_bits_addr), + .io_sramRead_resp_ready (_pipe_1_io_sramRead_resp_ready), + .io_sramRead_resp_valid (_pipe_io_sramRead_resp_valid_T_3), + .io_sramRead_resp_bits_data (readData_1), + .io_sramWrite_req_ready (_pipe_io_sramWrite_req_ready_T_11), + .io_sramWrite_req_valid (_pipe_1_io_sramWrite_req_valid), + .io_sramWrite_req_bits_addr (_pipe_1_io_sramWrite_req_bits_addr), + .io_sramWrite_req_bits_mask_0 (_pipe_1_io_sramWrite_req_bits_mask_0), + .io_sramWrite_req_bits_mask_1 (_pipe_1_io_sramWrite_req_bits_mask_1), + .io_sramWrite_req_bits_mask_2 (_pipe_1_io_sramWrite_req_bits_mask_2), + .io_sramWrite_req_bits_mask_3 (_pipe_1_io_sramWrite_req_bits_mask_3), + .io_sramWrite_req_bits_mask_4 (_pipe_1_io_sramWrite_req_bits_mask_4), + .io_sramWrite_req_bits_mask_5 (_pipe_1_io_sramWrite_req_bits_mask_5), + .io_sramWrite_req_bits_mask_6 (_pipe_1_io_sramWrite_req_bits_mask_6), + .io_sramWrite_req_bits_mask_7 (_pipe_1_io_sramWrite_req_bits_mask_7), + .io_sramWrite_req_bits_data (_pipe_1_io_sramWrite_req_bits_data), + .io_sramWrite_resp_ready (_pipe_1_io_sramWrite_resp_ready), + .io_sramWrite_resp_valid (_pipe_io_sramWrite_resp_valid_T_3), + .io_mem_req_write_req_ready (/* unused */), + .io_mem_req_write_req_valid (1'h0), + .io_mem_req_write_req_bits_addr (10'h0), + .io_mem_req_write_req_bits_mask_0 (1'h0), + .io_mem_req_write_req_bits_mask_1 (1'h0), + .io_mem_req_write_req_bits_mask_2 (1'h0), + .io_mem_req_write_req_bits_mask_3 (1'h0), + .io_mem_req_write_req_bits_mask_4 (1'h0), + .io_mem_req_write_req_bits_mask_5 (1'h0), + .io_mem_req_write_req_bits_mask_6 (1'h0), + .io_mem_req_write_req_bits_mask_7 (1'h0), + .io_mem_req_write_req_bits_data (64'h0), + .io_mem_req_write_resp_ready (1'h0), + .io_mem_req_write_resp_valid (/* unused */), + .io_mem_req_write_resp_bits_ok (/* unused */), + .io_mem_req_read_req_ready (_pipe_1_io_mem_req_read_req_ready), + .io_mem_req_read_req_valid (_midend_io_mem_req_1_read_req_valid), + .io_mem_req_read_req_bits_addr (_midend_io_mem_req_1_read_req_bits_addr), + .io_mem_req_read_resp_ready (_midend_io_mem_req_1_read_resp_ready), + .io_mem_req_read_resp_valid (_pipe_1_io_mem_req_read_resp_valid), + .io_mem_req_read_resp_bits_data (_pipe_1_io_mem_req_read_resp_bits_data), + .io_busy (_pipe_1_io_busy) + ); + AccPipe pipe_2 ( + .clock (clock), + .reset (reset), + .io_sramRead_req_ready (_pipe_io_sramRead_req_ready_T_17), + .io_sramRead_req_valid (_pipe_2_io_sramRead_req_valid), + .io_sramRead_req_bits_addr (_pipe_2_io_sramRead_req_bits_addr), + .io_sramRead_resp_ready (_pipe_2_io_sramRead_resp_ready), + .io_sramRead_resp_valid (_pipe_io_sramRead_resp_valid_T_5), + .io_sramRead_resp_bits_data (readData_2), + .io_sramWrite_req_ready (_pipe_io_sramWrite_req_ready_T_17), + .io_sramWrite_req_valid (_pipe_2_io_sramWrite_req_valid), + .io_sramWrite_req_bits_addr (_pipe_2_io_sramWrite_req_bits_addr), + .io_sramWrite_req_bits_mask_0 (_pipe_2_io_sramWrite_req_bits_mask_0), + .io_sramWrite_req_bits_mask_1 (_pipe_2_io_sramWrite_req_bits_mask_1), + .io_sramWrite_req_bits_mask_2 (_pipe_2_io_sramWrite_req_bits_mask_2), + .io_sramWrite_req_bits_mask_3 (_pipe_2_io_sramWrite_req_bits_mask_3), + .io_sramWrite_req_bits_mask_4 (_pipe_2_io_sramWrite_req_bits_mask_4), + .io_sramWrite_req_bits_mask_5 (_pipe_2_io_sramWrite_req_bits_mask_5), + .io_sramWrite_req_bits_mask_6 (_pipe_2_io_sramWrite_req_bits_mask_6), + .io_sramWrite_req_bits_mask_7 (_pipe_2_io_sramWrite_req_bits_mask_7), + .io_sramWrite_req_bits_data (_pipe_2_io_sramWrite_req_bits_data), + .io_sramWrite_resp_ready (_pipe_2_io_sramWrite_resp_ready), + .io_sramWrite_resp_valid (_pipe_io_sramWrite_resp_valid_T_5), + .io_mem_req_write_req_ready (_pipe_2_io_mem_req_write_req_ready), + .io_mem_req_write_req_valid (_midend_io_mem_req_2_write_req_valid), + .io_mem_req_write_req_bits_addr (_midend_io_mem_req_2_write_req_bits_addr), + .io_mem_req_write_req_bits_mask_0 (1'h1), + .io_mem_req_write_req_bits_mask_1 (1'h1), + .io_mem_req_write_req_bits_mask_2 (1'h1), + .io_mem_req_write_req_bits_mask_3 (1'h1), + .io_mem_req_write_req_bits_mask_4 (1'h1), + .io_mem_req_write_req_bits_mask_5 (1'h1), + .io_mem_req_write_req_bits_mask_6 (1'h1), + .io_mem_req_write_req_bits_mask_7 (1'h1), + .io_mem_req_write_req_bits_data (_midend_io_mem_req_2_write_req_bits_data), + .io_mem_req_write_resp_ready (_midend_io_mem_req_2_write_resp_ready), + .io_mem_req_write_resp_valid (_pipe_2_io_mem_req_write_resp_valid), + .io_mem_req_write_resp_bits_ok (_pipe_2_io_mem_req_write_resp_bits_ok), + .io_mem_req_read_req_ready (/* unused */), + .io_mem_req_read_req_valid (1'h0), + .io_mem_req_read_req_bits_addr (10'h0), + .io_mem_req_read_resp_ready (1'h0), + .io_mem_req_read_resp_valid (/* unused */), + .io_mem_req_read_resp_bits_data (/* unused */), + .io_busy (_pipe_2_io_busy) + ); + AccPipe pipe_3 ( + .clock (clock), + .reset (reset), + .io_sramRead_req_ready (_pipe_io_sramRead_req_ready_T_23), + .io_sramRead_req_valid (_pipe_3_io_sramRead_req_valid), + .io_sramRead_req_bits_addr (_pipe_3_io_sramRead_req_bits_addr), + .io_sramRead_resp_ready (_pipe_3_io_sramRead_resp_ready), + .io_sramRead_resp_valid (_pipe_io_sramRead_resp_valid_T_7), + .io_sramRead_resp_bits_data (readData_3), + .io_sramWrite_req_ready (_pipe_io_sramWrite_req_ready_T_23), + .io_sramWrite_req_valid (_pipe_3_io_sramWrite_req_valid), + .io_sramWrite_req_bits_addr (_pipe_3_io_sramWrite_req_bits_addr), + .io_sramWrite_req_bits_mask_0 (_pipe_3_io_sramWrite_req_bits_mask_0), + .io_sramWrite_req_bits_mask_1 (_pipe_3_io_sramWrite_req_bits_mask_1), + .io_sramWrite_req_bits_mask_2 (_pipe_3_io_sramWrite_req_bits_mask_2), + .io_sramWrite_req_bits_mask_3 (_pipe_3_io_sramWrite_req_bits_mask_3), + .io_sramWrite_req_bits_mask_4 (_pipe_3_io_sramWrite_req_bits_mask_4), + .io_sramWrite_req_bits_mask_5 (_pipe_3_io_sramWrite_req_bits_mask_5), + .io_sramWrite_req_bits_mask_6 (_pipe_3_io_sramWrite_req_bits_mask_6), + .io_sramWrite_req_bits_mask_7 (_pipe_3_io_sramWrite_req_bits_mask_7), + .io_sramWrite_req_bits_data (_pipe_3_io_sramWrite_req_bits_data), + .io_sramWrite_resp_ready (_pipe_3_io_sramWrite_resp_ready), + .io_sramWrite_resp_valid (_pipe_io_sramWrite_resp_valid_T_7), + .io_mem_req_write_req_ready (_pipe_3_io_mem_req_write_req_ready), + .io_mem_req_write_req_valid (_midend_io_mem_req_3_write_req_valid), + .io_mem_req_write_req_bits_addr (_midend_io_mem_req_3_write_req_bits_addr), + .io_mem_req_write_req_bits_mask_0 (1'h1), + .io_mem_req_write_req_bits_mask_1 (1'h1), + .io_mem_req_write_req_bits_mask_2 (1'h1), + .io_mem_req_write_req_bits_mask_3 (1'h1), + .io_mem_req_write_req_bits_mask_4 (1'h1), + .io_mem_req_write_req_bits_mask_5 (1'h1), + .io_mem_req_write_req_bits_mask_6 (1'h1), + .io_mem_req_write_req_bits_mask_7 (1'h1), + .io_mem_req_write_req_bits_data (_midend_io_mem_req_3_write_req_bits_data), + .io_mem_req_write_resp_ready (_midend_io_mem_req_3_write_resp_ready), + .io_mem_req_write_resp_valid (_pipe_3_io_mem_req_write_resp_valid), + .io_mem_req_write_resp_bits_ok (_pipe_3_io_mem_req_write_resp_bits_ok), + .io_mem_req_read_req_ready (/* unused */), + .io_mem_req_read_req_valid (1'h0), + .io_mem_req_read_req_bits_addr (10'h0), + .io_mem_req_read_resp_ready (1'h0), + .io_mem_req_read_resp_valid (/* unused */), + .io_mem_req_read_resp_bits_data (/* unused */), + .io_busy (_pipe_3_io_busy) + ); + AccPipe pipe_4 ( + .clock (clock), + .reset (reset), + .io_sramRead_req_ready (_pipe_io_sramRead_req_ready_T_29), + .io_sramRead_req_valid (_pipe_4_io_sramRead_req_valid), + .io_sramRead_req_bits_addr (_pipe_4_io_sramRead_req_bits_addr), + .io_sramRead_resp_ready (_pipe_4_io_sramRead_resp_ready), + .io_sramRead_resp_valid (_pipe_io_sramRead_resp_valid_T_9), + .io_sramRead_resp_bits_data (readData_4), + .io_sramWrite_req_ready (_pipe_io_sramWrite_req_ready_T_29), + .io_sramWrite_req_valid (_pipe_4_io_sramWrite_req_valid), + .io_sramWrite_req_bits_addr (_pipe_4_io_sramWrite_req_bits_addr), + .io_sramWrite_req_bits_mask_0 (_pipe_4_io_sramWrite_req_bits_mask_0), + .io_sramWrite_req_bits_mask_1 (_pipe_4_io_sramWrite_req_bits_mask_1), + .io_sramWrite_req_bits_mask_2 (_pipe_4_io_sramWrite_req_bits_mask_2), + .io_sramWrite_req_bits_mask_3 (_pipe_4_io_sramWrite_req_bits_mask_3), + .io_sramWrite_req_bits_mask_4 (_pipe_4_io_sramWrite_req_bits_mask_4), + .io_sramWrite_req_bits_mask_5 (_pipe_4_io_sramWrite_req_bits_mask_5), + .io_sramWrite_req_bits_mask_6 (_pipe_4_io_sramWrite_req_bits_mask_6), + .io_sramWrite_req_bits_mask_7 (_pipe_4_io_sramWrite_req_bits_mask_7), + .io_sramWrite_req_bits_data (_pipe_4_io_sramWrite_req_bits_data), + .io_sramWrite_resp_ready (_pipe_4_io_sramWrite_resp_ready), + .io_sramWrite_resp_valid (_pipe_io_sramWrite_resp_valid_T_9), + .io_mem_req_write_req_ready (_pipe_4_io_mem_req_write_req_ready), + .io_mem_req_write_req_valid (_midend_io_mem_req_4_write_req_valid), + .io_mem_req_write_req_bits_addr (_midend_io_mem_req_4_write_req_bits_addr), + .io_mem_req_write_req_bits_mask_0 (1'h1), + .io_mem_req_write_req_bits_mask_1 (1'h1), + .io_mem_req_write_req_bits_mask_2 (1'h1), + .io_mem_req_write_req_bits_mask_3 (1'h1), + .io_mem_req_write_req_bits_mask_4 (1'h1), + .io_mem_req_write_req_bits_mask_5 (1'h1), + .io_mem_req_write_req_bits_mask_6 (1'h1), + .io_mem_req_write_req_bits_mask_7 (1'h1), + .io_mem_req_write_req_bits_data (_midend_io_mem_req_4_write_req_bits_data), + .io_mem_req_write_resp_ready (_midend_io_mem_req_4_write_resp_ready), + .io_mem_req_write_resp_valid (_pipe_4_io_mem_req_write_resp_valid), + .io_mem_req_write_resp_bits_ok (_pipe_4_io_mem_req_write_resp_bits_ok), + .io_mem_req_read_req_ready (/* unused */), + .io_mem_req_read_req_valid (1'h0), + .io_mem_req_read_req_bits_addr (10'h0), + .io_mem_req_read_resp_ready (1'h0), + .io_mem_req_read_resp_valid (/* unused */), + .io_mem_req_read_resp_bits_data (/* unused */), + .io_busy (_pipe_4_io_busy) + ); + AccPipe pipe_5 ( + .clock (clock), + .reset (reset), + .io_sramRead_req_ready (_pipe_io_sramRead_req_ready_T_35), + .io_sramRead_req_valid (_pipe_5_io_sramRead_req_valid), + .io_sramRead_req_bits_addr (_pipe_5_io_sramRead_req_bits_addr), + .io_sramRead_resp_ready (_pipe_5_io_sramRead_resp_ready), + .io_sramRead_resp_valid (_pipe_io_sramRead_resp_valid_T_11), + .io_sramRead_resp_bits_data (readData_5), + .io_sramWrite_req_ready (_pipe_io_sramWrite_req_ready_T_35), + .io_sramWrite_req_valid (_pipe_5_io_sramWrite_req_valid), + .io_sramWrite_req_bits_addr (_pipe_5_io_sramWrite_req_bits_addr), + .io_sramWrite_req_bits_mask_0 (_pipe_5_io_sramWrite_req_bits_mask_0), + .io_sramWrite_req_bits_mask_1 (_pipe_5_io_sramWrite_req_bits_mask_1), + .io_sramWrite_req_bits_mask_2 (_pipe_5_io_sramWrite_req_bits_mask_2), + .io_sramWrite_req_bits_mask_3 (_pipe_5_io_sramWrite_req_bits_mask_3), + .io_sramWrite_req_bits_mask_4 (_pipe_5_io_sramWrite_req_bits_mask_4), + .io_sramWrite_req_bits_mask_5 (_pipe_5_io_sramWrite_req_bits_mask_5), + .io_sramWrite_req_bits_mask_6 (_pipe_5_io_sramWrite_req_bits_mask_6), + .io_sramWrite_req_bits_mask_7 (_pipe_5_io_sramWrite_req_bits_mask_7), + .io_sramWrite_req_bits_data (_pipe_5_io_sramWrite_req_bits_data), + .io_sramWrite_resp_ready (_pipe_5_io_sramWrite_resp_ready), + .io_sramWrite_resp_valid (_pipe_io_sramWrite_resp_valid_T_11), + .io_mem_req_write_req_ready (_pipe_5_io_mem_req_write_req_ready), + .io_mem_req_write_req_valid (_midend_io_mem_req_5_write_req_valid), + .io_mem_req_write_req_bits_addr (_midend_io_mem_req_5_write_req_bits_addr), + .io_mem_req_write_req_bits_mask_0 (1'h1), + .io_mem_req_write_req_bits_mask_1 (1'h1), + .io_mem_req_write_req_bits_mask_2 (1'h1), + .io_mem_req_write_req_bits_mask_3 (1'h1), + .io_mem_req_write_req_bits_mask_4 (1'h1), + .io_mem_req_write_req_bits_mask_5 (1'h1), + .io_mem_req_write_req_bits_mask_6 (1'h1), + .io_mem_req_write_req_bits_mask_7 (1'h1), + .io_mem_req_write_req_bits_data (_midend_io_mem_req_5_write_req_bits_data), + .io_mem_req_write_resp_ready (_midend_io_mem_req_5_write_resp_ready), + .io_mem_req_write_resp_valid (_pipe_5_io_mem_req_write_resp_valid), + .io_mem_req_write_resp_bits_ok (_pipe_5_io_mem_req_write_resp_bits_ok), + .io_mem_req_read_req_ready (/* unused */), + .io_mem_req_read_req_valid (1'h0), + .io_mem_req_read_req_bits_addr (10'h0), + .io_mem_req_read_resp_ready (1'h0), + .io_mem_req_read_resp_valid (/* unused */), + .io_mem_req_read_resp_bits_data (/* unused */), + .io_busy (_pipe_5_io_busy) + ); + AccPipe pipe_6 ( + .clock (clock), + .reset (reset), + .io_sramRead_req_ready (_pipe_io_sramRead_req_ready_T_41), + .io_sramRead_req_valid (_pipe_6_io_sramRead_req_valid), + .io_sramRead_req_bits_addr (_pipe_6_io_sramRead_req_bits_addr), + .io_sramRead_resp_ready (_pipe_6_io_sramRead_resp_ready), + .io_sramRead_resp_valid (_pipe_io_sramRead_resp_valid_T_13), + .io_sramRead_resp_bits_data (readData_6), + .io_sramWrite_req_ready (_pipe_io_sramWrite_req_ready_T_41), + .io_sramWrite_req_valid (_pipe_6_io_sramWrite_req_valid), + .io_sramWrite_req_bits_addr (_pipe_6_io_sramWrite_req_bits_addr), + .io_sramWrite_req_bits_mask_0 (_pipe_6_io_sramWrite_req_bits_mask_0), + .io_sramWrite_req_bits_mask_1 (_pipe_6_io_sramWrite_req_bits_mask_1), + .io_sramWrite_req_bits_mask_2 (_pipe_6_io_sramWrite_req_bits_mask_2), + .io_sramWrite_req_bits_mask_3 (_pipe_6_io_sramWrite_req_bits_mask_3), + .io_sramWrite_req_bits_mask_4 (_pipe_6_io_sramWrite_req_bits_mask_4), + .io_sramWrite_req_bits_mask_5 (_pipe_6_io_sramWrite_req_bits_mask_5), + .io_sramWrite_req_bits_mask_6 (_pipe_6_io_sramWrite_req_bits_mask_6), + .io_sramWrite_req_bits_mask_7 (_pipe_6_io_sramWrite_req_bits_mask_7), + .io_sramWrite_req_bits_data (_pipe_6_io_sramWrite_req_bits_data), + .io_sramWrite_resp_ready (_pipe_6_io_sramWrite_resp_ready), + .io_sramWrite_resp_valid (_pipe_io_sramWrite_resp_valid_T_13), + .io_mem_req_write_req_ready (_pipe_6_io_mem_req_write_req_ready), + .io_mem_req_write_req_valid (_midend_io_mem_req_6_write_req_valid), + .io_mem_req_write_req_bits_addr (_midend_io_mem_req_6_write_req_bits_addr), + .io_mem_req_write_req_bits_mask_0 (1'h1), + .io_mem_req_write_req_bits_mask_1 (1'h1), + .io_mem_req_write_req_bits_mask_2 (1'h1), + .io_mem_req_write_req_bits_mask_3 (1'h1), + .io_mem_req_write_req_bits_mask_4 (1'h1), + .io_mem_req_write_req_bits_mask_5 (1'h1), + .io_mem_req_write_req_bits_mask_6 (1'h1), + .io_mem_req_write_req_bits_mask_7 (1'h1), + .io_mem_req_write_req_bits_data (_midend_io_mem_req_6_write_req_bits_data), + .io_mem_req_write_resp_ready (_midend_io_mem_req_6_write_resp_ready), + .io_mem_req_write_resp_valid (_pipe_6_io_mem_req_write_resp_valid), + .io_mem_req_write_resp_bits_ok (_pipe_6_io_mem_req_write_resp_bits_ok), + .io_mem_req_read_req_ready (_pipe_6_io_mem_req_read_req_ready), + .io_mem_req_read_req_valid (_midend_io_mem_req_6_read_req_valid), + .io_mem_req_read_req_bits_addr (_midend_io_mem_req_6_read_req_bits_addr), + .io_mem_req_read_resp_ready (_midend_io_mem_req_6_read_resp_ready), + .io_mem_req_read_resp_valid (_pipe_6_io_mem_req_read_resp_valid), + .io_mem_req_read_resp_bits_data (_pipe_6_io_mem_req_read_resp_bits_data), + .io_busy (_pipe_6_io_busy) + ); + assign passed = + readSeen_0 == 7'h40 & readSeen_1 == 7'h40 & readSeen_2 == 7'h40 & writeSeen_0 == 7'h40 + & writeSeen_1 == 7'h40 & writeSeen_2 == 7'h40 & writeSeen_3 == 7'h40 + & writeSeen_4 == 7'h40; +endmodule + diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/routing-check/simulation.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/routing-check/simulation.log new file mode 100644 index 0000000..3136540 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/routing-check/simulation.log @@ -0,0 +1,5 @@ +PASS fixed routing: 512 transactions, DMA arbitration, stalls +- /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/routing-check/tb.sv:12: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 15us; walltime 0.001 s; speed 12.635 ms/s +- Verilator: cpu 0.001 s on 1 threads; allocated 6 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/routing-check/tb.sv b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/routing-check/tb.sv new file mode 100644 index 0000000..260c5c5 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/routing-check/tb.sv @@ -0,0 +1,18 @@ +`timescale 1ns/1ps +module tb; + reg clock=0, reset=1; + wire passed; + RoutingCheck dut(.*); + always #5 clock=~clock; + initial begin + repeat(10) @(negedge clock); + reset=0; + wait(passed); + $display("PASS fixed routing: 512 transactions, DMA arbitration, stalls"); + $finish; + end + initial begin + repeat(20000) @(posedge clock); + $fatal(1, "Routing check timeout"); + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/runner-status-check/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/runner-status-check/RESULT.json new file mode 100644 index 0000000..487476f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/runner-status-check/RESULT.json @@ -0,0 +1,28 @@ +{ + "result": "PASS_RUNNER_FAILURE_STATUS", + "baseline_ref": null, + "physical_hardware_tested": false, + "cases": [ + { + "script": "check_board.py", + "source_sha256": "2c6cb06f301bfc4b98f66d21e5f34d7627a73b490ee60e385185bfaf2377711b", + "exit_code": 1, + "observed_result": "FAILED", + "result": "PASS" + }, + { + "script": "check_programming_scripts.py", + "source_sha256": "8bd486cc7b0dbb960984a6dadc1bd97eb5a2b393abbe55e9d99077817dbc02a5", + "exit_code": 1, + "observed_result": "FAILED", + "result": "PASS" + }, + { + "script": "check_flash_guards.py", + "source_sha256": "76bba3666d73a87aa698fa714933244f59dbdaa2260cb742462ad71505a10a5b", + "exit_code": 1, + "observed_result": "FAILED", + "result": "PASS" + } + ] +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/runner-status-check/check_board.py.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/runner-status-check/check_board.py.log new file mode 100644 index 0000000..53c0b23 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/runner-status-check/check_board.py.log @@ -0,0 +1,10 @@ +Traceback (most recent call last): + File "/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/runner-status-check/tmpgiugwnkk/scripts/check_board.py", line 77, in + run_check(main, OUT) + File "/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/runner-status-check/tmpgiugwnkk/scripts/offline_check.py", line 19, in run_check + main() + File "/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/runner-status-check/tmpgiugwnkk/scripts/check_board.py", line 28, in main + raise ValueError("CPU port fixture differs from its manifest") +ValueError: CPU port fixture differs from its manifest + +OBSERVED_RESULT {"result": "FAILED", "physical_hardware_tested": false, "error_type": "ValueError", "error": "CPU port fixture differs from its manifest"} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/runner-status-check/check_flash_guards.py.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/runner-status-check/check_flash_guards.py.log new file mode 100644 index 0000000..f9a6149 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/runner-status-check/check_flash_guards.py.log @@ -0,0 +1,12 @@ +Traceback (most recent call last): + File "/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/runner-status-check/tmpliwrp981/scripts/check_flash_guards.py", line 48, in + run_check(main, ROOT / "build/flash-guard-check") + File "/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/runner-status-check/tmpliwrp981/scripts/offline_check.py", line 19, in run_check + main() + File "/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/runner-status-check/tmpliwrp981/scripts/check_flash_guards.py", line 38, in main + result.check_returncode() + File "/usr/lib/python3.12/subprocess.py", line 502, in check_returncode + raise CalledProcessError(self.returncode, self.args, self.stdout, +subprocess.CalledProcessError: Command '['/usr/bin/python3', '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/runner-status-check/tmpliwrp981/tests/flash_guard_probe.py', '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/runner-status-check/tmpliwrp981/host/flash.py', '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/runner-status-check/tmpliwrp981/build/flash-guard-check/tmp0jxst5tj/chip.bit', '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/runner-status-check/tmpliwrp981/build/flash-guard-check/tmp0jxst5tj/payload.bin', '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/runner-status-check/tmpliwrp981/build/flash-guard-check/tmp0jxst5tj/image.mcs', '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/runner-status-check/tmpliwrp981/build/flash-guard-check/tmp0jxst5tj/run', 'accept']' returned non-zero exit status 1. + +OBSERVED_RESULT {"result": "FAILED", "physical_hardware_tested": false, "error_type": "CalledProcessError", "error": "Command '['/usr/bin/python3', '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/runner-status-check/tmpliwrp981/tests/flash_guard_probe.py', '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/runner-status-check/tmpliwrp981/host/flash.py', '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/runner-status-check/tmpliwrp981/build/flash-guard-check/tmp0jxst5tj/chip.bit', '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/runner-status-check/tmpliwrp981/build/flash-guard-check/tmp0jxst5tj/payload.bin', '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/runner-status-check/tmpliwrp981/build/flash-guard-check/tmp0jxst5tj/image.mcs', '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/runner-status-check/tmpliwrp981/build/flash-guard-check/tmp0jxst5tj/run', 'accept']' returned non-zero exit status 1."} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/runner-status-check/check_programming_scripts.py.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/runner-status-check/check_programming_scripts.py.log new file mode 100644 index 0000000..45d0eae --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/runner-status-check/check_programming_scripts.py.log @@ -0,0 +1,14 @@ +Traceback (most recent call last): + File "/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/runner-status-check/tmpdb8x_wmb/scripts/check_programming_scripts.py", line 57, in + run_check(main, ROOT / "build/programming-check") + File "/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/runner-status-check/tmpdb8x_wmb/scripts/offline_check.py", line 19, in run_check + main() + File "/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/runner-status-check/tmpdb8x_wmb/scripts/check_programming_scripts.py", line 41, in main + raise ValueError(f"Documented success return rejected: {script}: {transcript}") +ValueError: Documented success return rejected: program_arty.tcl: Traceback (most recent call last): + File "/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/runner-status-check/tmpdb8x_wmb/tests/mock_programming.tcl", line 1, in + raise RuntimeError('INJECTED_CHECK_FAILURE') +RuntimeError: INJECTED_CHECK_FAILURE + + +OBSERVED_RESULT {"result": "FAILED", "physical_hardware_tested": false, "error_type": "ValueError", "error": "Documented success return rejected: program_arty.tcl: Traceback (most recent call last):\n File \"/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/runner-status-check/tmpdb8x_wmb/tests/mock_programming.tcl\", line 1, in \n raise RuntimeError('INJECTED_CHECK_FAILURE')\nRuntimeError: INJECTED_CHECK_FAILURE\n"} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/ws-round-edges/simulation/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/ws-round-edges/simulation/RESULT.json new file mode 100644 index 0000000..928b5cb --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/ws-round-edges/simulation/RESULT.json @@ -0,0 +1,10 @@ +{ + "result": "PASS", + "test_label": "whole Toy 64 OS WS RNE edge cases 4096 results", + "core_rtl_sha256": "31e7e07f94d08208dbb564edf9546240df26ff834935bfb646b71b541d875fb9", + "test_binary_sha256": "fbf5f1205e364accf5cdd7973cadefc8529947d3c236e65cb384cb9e41b29462", + "cycles_including_boot": 979581, + "memory_read_bursts": 3347, + "memory_write_bursts": 2496, + "linux_boot_tested": false +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/ws-round-edges/simulation/simulation.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/ws-round-edges/simulation/simulation.log new file mode 100644 index 0000000..f9a4e33 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/ws-round-edges/simulation/simulation.log @@ -0,0 +1,7 @@ +CPU status = 00000000600d600d +PASS whole Toy 64 OS WS RNE edge cases 4096 results +- /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:88: Verilog $finish +MEASURE cycles=979581 memory_reads=3347 memory_writes=2496 +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 10ms; walltime 7.903 s; speed 1.239 ms/s +- Verilator: cpu 7.902 s on 1 threads; allocated 8 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/ws-round-edges/simulation/smoke.bin b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/ws-round-edges/simulation/smoke.bin new file mode 100644 index 0000000..d2c9203 Binary files /dev/null and b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/ws-round-edges/simulation/smoke.bin differ diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/ws-round-edges/simulation/smoke.disasm b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/ws-round-edges/simulation/smoke.disasm new file mode 100644 index 0000000..a3e65d2 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/ws-round-edges/simulation/smoke.disasm @@ -0,0 +1,395 @@ + +/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/smoke.elf: file format elf64-littleriscv + + +Disassembly of section .text: + +0000000080000000 <_start>: + 80000000: 00002137 lui sp,0x2 + 80000004: 0011011b addiw sp,sp,1 # 2001 <_start-0x7fffdfff> + 80000008: 01211113 slli sp,sp,0x12 + 8000000c: ff010113 addi sp,sp,-16 + 80000010: 00000297 auipc t0,0x0 + 80000014: 04c28293 addi t0,t0,76 # 8000005c + 80000018: 30529073 csrw mtvec,t0 + 8000001c: 30401073 csrw mie,zero + 80000020: 30201073 csrw medeleg,zero + 80000024: 0001e2b7 lui t0,0x1e + 80000028: 3002a073 csrs mstatus,t0 + 8000002c: 00000097 auipc ra,0x0 + 80000030: 050080e7 jalr 80(ra) # 8000007c
+ 80000034: 600002b7 lui t0,0x60000 + 80000038: 600d6337 lui t1,0x600d6 + 8000003c: 00d3031b addiw t1,t1,13 # 600d600d <_start-0x1ff29ff3> + 80000040: 00050a63 beqz a0,80000054 + 80000044: 00001337 lui t1,0x1 + 80000048: bad3031b addiw t1,t1,-1107 # bad <_start-0x7ffff453> + 8000004c: 01431313 slli t1,t1,0x14 + 80000050: 00a36333 or t1,t1,a0 + +0000000080000054 : + 80000054: 0062b023 sd t1,0(t0) # 60000000 <_start-0x20000000> + 80000058: 0000006f j 80000058 + +000000008000005c : + 8000005c: 342023f3 csrr t2,mcause + 80000060: 600002b7 lui t0,0x60000 + 80000064: 000bb337 lui t1,0xbb + 80000068: d0f3031b addiw t1,t1,-753 # bad0f <_start-0x7ff452f1> + 8000006c: 00c31313 slli t1,t1,0xc + 80000070: 00736333 or t1,t1,t2 + 80000074: 0062b023 sd t1,0(t0) # 60000000 <_start-0x20000000> + 80000078: 0000006f j 80000078 + +000000008000007c
: + 8000007c: 7131 addi sp,sp,-192 + 8000007e: f922 sd s0,176(sp) + 80000080: e556 sd s5,136(sp) + 80000082: 0180 addi s0,sp,192 + 80000084: 57fd li a5,-1 + 80000086: fd06 sd ra,184(sp) + 80000088: f526 sd s1,168(sp) + 8000008a: f14a sd s2,160(sp) + 8000008c: ed4e sd s3,152(sp) + 8000008e: e952 sd s4,144(sp) + 80000090: e15a sd s6,128(sp) + 80000092: fcde sd s7,120(sp) + 80000094: f8e2 sd s8,112(sp) + 80000096: f4e6 sd s9,104(sp) + 80000098: f0ea sd s10,96(sp) + 8000009a: ecee sd s11,88(sp) + 8000009c: 0197d713 srli a4,a5,0x19 + 800000a0: 00000797 auipc a5,0x0 + 800000a4: 5e078793 addi a5,a5,1504 # 80000680 + 800000a8: 8ff9 and a5,a5,a4 + 800000aa: f8e43423 sd a4,-120(s0) + 800000ae: 4705 li a4,1 + 800000b0: 171e slli a4,a4,0x27 + 800000b2: 8fd9 or a5,a5,a4 + 800000b4: f4f43423 sd a5,-184(s0) + 800000b8: f6043c23 sd zero,-136(s0) + 800000bc: 00000a97 auipc s5,0x0 + 800000c0: 454a8a93 addi s5,s5,1108 # 80000510 + 800000c4: 51eb8d37 lui s10,0x51eb8 + 800000c8: 51fd0d13 addi s10,s10,1311 # 51eb851f <_start-0x2e147ae1> + 800000cc: 4c81 li s9,0 + 800000ce: 00000d97 auipc s11,0x0 + 800000d2: 3dad8d93 addi s11,s11,986 # 800004a8 + 800000d6: 4b81 li s7,0 + 800000d8: 8656 mv a2,s5 + 800000da: fffc8793 addi a5,s9,-1 + 800000de: 0017b793 seqz a5,a5 + 800000e2: 92492c37 lui s8,0x92492 + 800000e6: f8f43023 sd a5,-128(s0) + 800000ea: 493c0c13 addi s8,s8,1171 # ffffffff92492493 + 800000ee: 4681 li a3,0 + 800000f0: f8043703 ld a4,-128(s0) + 800000f4: 00000a17 auipc s4,0x0 + 800000f8: 54ca0a13 addi s4,s4,1356 # 80000640 + 800000fc: 00000817 auipc a6,0x0 + 80000100: 44480813 addi a6,a6,1092 # 80000540 + 80000104: 00000997 auipc s3,0x0 + 80000108: 5bc98993 addi s3,s3,1468 # 800006c0 + 8000010c: 12345fb7 lui t6,0x12345 + 80000110: 8f52 mv t5,s4 + 80000112: 8ac2 mv s5,a6 + 80000114: 894e mv s2,s3 + 80000116: 678f8f93 addi t6,t6,1656 # 12345678 <_start-0x6dcba988> + 8000011a: 00d774b3 and s1,a4,a3 + 8000011e: 00000e97 auipc t4,0x0 + 80000122: 562e8e93 addi t4,t4,1378 # 80000680 + 80000126: 4e01 li t3,0 + 80000128: 438d li t2,3 + 8000012a: f8000b13 li s6,-128 + 8000012e: 42a1 li t0,8 + 80000130: f6d43823 sd a3,-144(s0) + 80000134: f7343423 sd s3,-152(s0) + 80000138: f7043023 sd a6,-160(s0) + 8000013c: f5443c23 sd s4,-168(s0) + 80000140: 003e181b slliw a6,t3,0x3 + 80000144: 89ca mv s3,s2 + 80000146: 8356 mv t1,s5 + 80000148: 4701 li a4,0 + 8000014a: a0ad j 800001b4 + 8000014c: 4501 li a0,0 + 8000014e: 091e0863 beq t3,a7,800001de + 80000152: 03a585b3 mul a1,a1,s10 + 80000156: 00a98023 sb a0,0(s3) + 8000015a: 4881 li a7,0 + 8000015c: 918d srli a1,a1,0x23 + 8000015e: 0015951b slliw a0,a1,0x1 + 80000162: 9d2d addw a0,a0,a1 + 80000164: 0035151b slliw a0,a0,0x3 + 80000168: 9d2d addw a0,a0,a1 + 8000016a: 9f89 subw a5,a5,a0 + 8000016c: 078a slli a5,a5,0x2 + 8000016e: 97ee add a5,a5,s11 + 80000170: 439c lw a5,0(a5) + 80000172: c08d beqz s1,80000194 + 80000174: 038805b3 mul a1,a6,s8 + 80000178: 9181 srli a1,a1,0x20 + 8000017a: 00b805bb addw a1,a6,a1 + 8000017e: 4025d59b sraiw a1,a1,0x2 + 80000182: 414585bb subw a1,a1,s4 + 80000186: 0035989b slliw a7,a1,0x3 + 8000018a: 40b888bb subw a7,a7,a1 + 8000018e: 411808bb subw a7,a6,a7 + 80000192: 38f5 addiw a7,a7,-3 + 80000194: 00ee85b3 add a1,t4,a4 + 80000198: 00f58023 sb a5,0(a1) + 8000019c: 00ef07b3 add a5,t5,a4 + 800001a0: 01f32023 sw t6,0(t1) + 800001a4: 01178023 sb a7,0(a5) + 800001a8: 0705 addi a4,a4,1 + 800001aa: 0311 addi t1,t1,4 + 800001ac: 2805 addiw a6,a6,1 + 800001ae: 0985 addi s3,s3,1 + 800001b0: 06570263 beq a4,t0,80000214 + 800001b4: 017807bb addw a5,a6,s7 + 800001b8: 02079593 slli a1,a5,0x20 + 800001bc: 9181 srli a1,a1,0x20 + 800001be: 41f85a1b sraiw s4,a6,0x1f + 800001c2: 0007089b sext.w a7,a4 + 800001c6: f87c93e3 bne s9,t2,8000014c + 800001ca: 03f71593 slli a1,a4,0x3f + 800001ce: 43f5d793 srai a5,a1,0x3f + 800001d2: 01698023 sb s6,0(s3) + 800001d6: f807c793 xori a5,a5,-128 + 800001da: 4881 li a7,0 + 800001dc: bf65 j 80000194 + 800001de: 4889 li a7,2 + 800001e0: 4505 li a0,1 + 800001e2: f71c98e3 bne s9,a7,80000152 + 800001e6: 00e8079b addiw a5,a6,14 + 800001ea: 02079513 slli a0,a5,0x20 + 800001ee: 9101 srli a0,a0,0x20 + 800001f0: 03a50533 mul a0,a0,s10 + 800001f4: 4591 li a1,4 + 800001f6: 00b98023 sb a1,0(s3) + 800001fa: 4881 li a7,0 + 800001fc: 910d srli a0,a0,0x23 + 800001fe: 0015159b slliw a1,a0,0x1 + 80000202: 9da9 addw a1,a1,a0 + 80000204: 0035959b slliw a1,a1,0x3 + 80000208: 9da9 addw a1,a1,a0 + 8000020a: 9f8d subw a5,a5,a1 + 8000020c: 078a slli a5,a5,0x2 + 8000020e: 97ee add a5,a5,s11 + 80000210: 439c lw a5,0(a5) + 80000212: b749 j 80000194 + 80000214: 2e05 addiw t3,t3,1 + 80000216: 0ea1 addi t4,t4,8 + 80000218: 0f21 addi t5,t5,8 + 8000021a: 020a8a93 addi s5,s5,32 + 8000021e: 0921 addi s2,s2,8 + 80000220: f2ee10e3 bne t3,a4,80000140 + 80000224: f7043783 ld a5,-144(s0) + 80000228: 4585 li a1,1 + 8000022a: 4501 li a0,0 + 8000022c: f6843983 ld s3,-152(s0) + 80000230: f5843a03 ld s4,-168(s0) + 80000234: f4f43823 sd a5,-176(s0) + 80000238: f6d43423 sd a3,-152(s0) + 8000023c: f6c43823 sd a2,-144(s0) + 80000240: 00000097 auipc ra,0x0 + 80000244: 22e080e7 jalr 558(ra) # 8000046e + 80000248: 4701 li a4,0 + 8000024a: 42100493 li s1,1057 + 8000024e: 4097307b .insn 4, 0x4097307b + 80000252: 4585 li a1,1 + 80000254: 852e mv a0,a1 + 80000256: 00000097 auipc ra,0x0 + 8000025a: 218080e7 jalr 536(ra) # 8000046e + 8000025e: 4905 li s2,1 + 80000260: 4099307b .insn 4, 0x4099307b + 80000264: 4509 li a0,2 + 80000266: 85ca mv a1,s2 + 80000268: 00000097 auipc ra,0x0 + 8000026c: 206080e7 jalr 518(ra) # 8000046e + 80000270: 4709 li a4,2 + 80000272: 4097307b .insn 4, 0x4097307b + 80000276: 4591 li a1,4 + 80000278: 450d li a0,3 + 8000027a: 00000097 auipc ra,0x0 + 8000027e: 1f4080e7 jalr 500(ra) # 8000046e + 80000282: 470d li a4,3 + 80000284: 48100593 li a1,1153 + 80000288: 40b7307b .insn 4, 0x40b7307b + 8000028c: 0000100f fence.i + 80000290: f4843783 ld a5,-184(s0) + 80000294: 02191713 slli a4,s2,0x21 + 80000298: 42f7307b .insn 4, 0x42f7307b + 8000029c: 0000100f fence.i + 800002a0: f8843783 ld a5,-120(s0) + 800002a4: 02791693 slli a3,s2,0x27 + 800002a8: 02001737 lui a4,0x2001 + 800002ac: 00f9f5b3 and a1,s3,a5 + 800002b0: 8dd5 or a1,a1,a3 + 800002b2: 0722 slli a4,a4,0x8 + 800002b4: 42b7307b .insn 4, 0x42b7307b + 800002b8: 0000100f fence.i + 800002bc: 01001737 lui a4,0x1001 + 800002c0: 00fa75b3 and a1,s4,a5 + 800002c4: 8dd5 or a1,a1,a3 + 800002c6: 0726 slli a4,a4,0x9 + 800002c8: 42b7307b .insn 4, 0x42b7307b + 800002cc: f7043603 ld a2,-144(s0) + 800002d0: f6843683 ld a3,-152(s0) + 800002d4: 4501 li a0,0 + 800002d6: 4218 lw a4,0(a2) + 800002d8: 00469593 slli a1,a3,0x4 + 800002dc: 02071893 slli a7,a4,0x20 + 800002e0: 0178d713 srli a4,a7,0x17 + 800002e4: 8f4d or a4,a4,a1 + 800002e6: 04e5307b .insn 4, 0x04e5307b + 800002ea: f5043783 ld a5,-176(s0) + 800002ee: 02003737 lui a4,0x2003 + 800002f2: 0722 slli a4,a4,0x8 + 800002f4: 0127c7b3 xor a5,a5,s2 + 800002f8: 2781 sext.w a5,a5 + 800002fa: 8fd9 or a5,a5,a4 + 800002fc: 6b27b07b .insn 4, 0x6b27b07b + 80000300: f6043803 ld a6,-160(s0) + 80000304: 012707b3 add a5,a4,s2 + 80000308: ca81 beqz a3,80000318 + 8000030a: 002007b7 lui a5,0x200 + 8000030e: 30178793 addi a5,a5,769 # 200301 <_start-0x7fdffcff> + 80000312: 07b2 slli a5,a5,0xc + 80000314: 80178793 addi a5,a5,-2047 + 80000318: 4709 li a4,2 + 8000031a: 84e7b07b .insn 4, 0x84e7b07b + 8000031e: 0000100f fence.i + 80000322: f8843703 ld a4,-120(s0) + 80000326: 4585 li a1,1 + 80000328: 4785 li a5,1 + 8000032a: 00e87733 and a4,a6,a4 + 8000032e: 02759513 slli a0,a1,0x27 + 80000332: 1786 slli a5,a5,0x21 + 80000334: 8f49 or a4,a4,a0 + 80000336: 078d addi a5,a5,3 + 80000338: 20e7b07b .insn 4, 0x20e7b07b + 8000033c: 4781 li a5,0 + 8000033e: 00f7b07b .insn 4, 0x00f7b07b + 80000342: 0330000f fence rw,rw + 80000346: 0000100f fence.i + 8000034a: 00062e83 lw t4,0(a2) + 8000034e: 4781 li a5,0 + 80000350: 4fa1 li t6,8 + 80000352: 01d59f33 sll t5,a1,t4 + 80000356: ffff0293 addi t0,t5,-1 + 8000035a: 04000393 li t2,64 + 8000035e: 00000e17 auipc t3,0x0 + 80000362: 362e0e13 addi t3,t3,866 # 800006c0 + 80000366: 84c2 mv s1,a6 + 80000368: 4301 li t1,0 + 8000036a: 006a0733 add a4,s4,t1 + 8000036e: 00070883 lb a7,0(a4) # 2003000 <_start-0x7dffd000> + 80000372: fc0e0593 addi a1,t3,-64 + 80000376: 854e mv a0,s3 + 80000378: 00050703 lb a4,0(a0) + 8000037c: 00058903 lb s2,0(a1) + 80000380: 05a1 addi a1,a1,8 + 80000382: 0505 addi a0,a0,1 + 80000384: 0327073b mulw a4,a4,s2 + 80000388: 0117073b addw a4,a4,a7 + 8000038c: 88ba mv a7,a4 + 8000038e: ffc595e3 bne a1,t3,80000378 + 80000392: 4088 lw a0,0(s1) + 80000394: 020e8763 beqz t4,800003c2 + 80000398: 41f7589b sraiw a7,a4,0x1f + 8000039c: 011745b3 xor a1,a4,a7 + 800003a0: 411585bb subw a1,a1,a7 + 800003a4: 1582 slli a1,a1,0x20 + 800003a6: 9181 srli a1,a1,0x20 + 800003a8: 00b2f8b3 and a7,t0,a1 + 800003ac: 0886 slli a7,a7,0x1 + 800003ae: 41d5d5b3 sra a1,a1,t4 + 800003b2: 0b1f4c63 blt t5,a7,8000046a + 800003b6: 0b1f0663 beq t5,a7,80000462 + 800003ba: 0005889b sext.w a7,a1 + 800003be: 06074b63 bltz a4,80000434 + 800003c2: 07151d63 bne a0,a7,8000043c + 800003c6: 0305 addi t1,t1,1 + 800003c8: 0491 addi s1,s1,4 + 800003ca: 0e05 addi t3,t3,1 + 800003cc: f9f31fe3 bne t1,t6,8000036a + 800003d0: 07a1 addi a5,a5,8 + 800003d2: 09a1 addi s3,s3,8 + 800003d4: 02080813 addi a6,a6,32 + 800003d8: 0a21 addi s4,s4,8 + 800003da: f87792e3 bne a5,t2,8000035e + 800003de: 4481 li s1,0 + 800003e0: 4911 li s2,4 + 800003e2: 89b6 mv s3,a3 + 800003e4: 8a32 mv s4,a2 + 800003e6: 4585 li a1,1 + 800003e8: 0004851b sext.w a0,s1 + 800003ec: 00000097 auipc ra,0x0 + 800003f0: 082080e7 jalr 130(ra) # 8000046e + 800003f4: 4781 li a5,0 + 800003f6: 40f4b07b .insn 4, 0x40f4b07b + 800003fa: 0485 addi s1,s1,1 + 800003fc: ff2495e3 bne s1,s2,800003e6 + 80000400: f7843683 ld a3,-136(s0) + 80000404: 00198713 addi a4,s3,1 + 80000408: 4789 li a5,2 + 8000040a: 2685 addiw a3,a3,1 + 8000040c: f6d43c23 sd a3,-136(s0) + 80000410: 8652 mv a2,s4 + 80000412: 4685 li a3,1 + 80000414: ccf71ee3 bne a4,a5,800000f0 + 80000418: 2c85 addiw s9,s9,1 + 8000041a: 2b9d addiw s7,s7,7 + 8000041c: ca9c9fe3 bne s9,s1,800000da + 80000420: 004a0a93 addi s5,s4,4 + 80000424: 00000797 auipc a5,0x0 + 80000428: 10c78793 addi a5,a5,268 # 80000530 + 8000042c: c8fa9ce3 bne s5,a5,800000c4 + 80000430: 4501 li a0,0 + 80000432: a809 j 80000444 + 80000434: 40b008bb negw a7,a1 + 80000438: f91507e3 beq a0,a7,800003c6 + 8000043c: f7843783 ld a5,-136(s0) + 80000440: 0017851b addiw a0,a5,1 + 80000444: 70ea ld ra,184(sp) + 80000446: 744a ld s0,176(sp) + 80000448: 74aa ld s1,168(sp) + 8000044a: 790a ld s2,160(sp) + 8000044c: 69ea ld s3,152(sp) + 8000044e: 6a4a ld s4,144(sp) + 80000450: 6aaa ld s5,136(sp) + 80000452: 6b0a ld s6,128(sp) + 80000454: 7be6 ld s7,120(sp) + 80000456: 7c46 ld s8,112(sp) + 80000458: 7ca6 ld s9,104(sp) + 8000045a: 7d06 ld s10,96(sp) + 8000045c: 6de6 ld s11,88(sp) + 8000045e: 6129 addi sp,sp,192 + 80000460: 8082 ret + 80000462: 0015f893 andi a7,a1,1 + 80000466: f4088ae3 beqz a7,800003ba + 8000046a: 0585 addi a1,a1,1 + 8000046c: b7b9 j 800003ba + +000000008000046e : + 8000046e: 1141 addi sp,sp,-16 + 80000470: e022 sd s0,0(sp) + 80000472: e406 sd ra,8(sp) + 80000474: 0800 addi s0,sp,16 + 80000476: 47bd li a5,15 + 80000478: 00a7fa63 bgeu a5,a0,8000048c + 8000047c: 00000717 auipc a4,0x0 + 80000480: 0b473703 ld a4,180(a4) # 80000530 + 80000484: 600007b7 lui a5,0x60000 + 80000488: e398 sd a4,0(a5) + 8000048a: a001 j 8000048a + 8000048c: 02051793 slli a5,a0,0x20 + 80000490: 60a2 ld ra,8(sp) + 80000492: 6402 ld s0,0(sp) + 80000494: 01e7d513 srli a0,a5,0x1e + 80000498: 00000797 auipc a5,0x0 + 8000049c: 26878793 addi a5,a5,616 # 80000700 + 800004a0: 97aa add a5,a5,a0 + 800004a2: c38c sw a1,0(a5) + 800004a4: 0141 addi sp,sp,16 + 800004a6: 8082 ret diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/ws-round-edges/simulation/smoke.elf b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/ws-round-edges/simulation/smoke.elf new file mode 100644 index 0000000..3b092d8 Binary files /dev/null and b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/ws-round-edges/simulation/smoke.elf differ diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/ws-round-edges/simulation/smoke.hex b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/ws-round-edges/simulation/smoke.hex new file mode 100644 index 0000000..bfdf5b9 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/ws-round-edges/simulation/smoke.hex @@ -0,0 +1,1336 @@ +37 +21 +00 +00 +1b +01 +11 +00 +13 +11 +21 +01 +13 +01 +01 +ff +97 +02 +00 +00 +93 +82 +c2 +04 +73 +90 +52 +30 +73 +10 +40 +30 +73 +10 +20 +30 +b7 +e2 +01 +00 +73 +a0 +02 +30 +97 +00 +00 +00 +e7 +80 +00 +05 +b7 +02 +00 +60 +37 +63 +0d +60 +1b +03 +d3 +00 +63 +0a +05 +00 +37 +13 +00 +00 +1b +03 +d3 +ba +13 +13 +43 +01 +33 +63 +a3 +00 +23 +b0 +62 +00 +6f +00 +00 +00 +f3 +23 +20 +34 +b7 +02 +00 +60 +37 +b3 +0b +00 +1b +03 +f3 +d0 +13 +13 +c3 +00 +33 +63 +73 +00 +23 +b0 +62 +00 +6f +00 +00 +00 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+15 +00 +e3 +8a +08 +f4 +85 +05 +b9 +b7 +41 +11 +22 +e0 +06 +e4 +00 +08 +bd +47 +63 +fa +a7 +00 +17 +07 +00 +00 +03 +37 +47 +0b +b7 +07 +00 +60 +98 +e3 +01 +a0 +93 +17 +05 +02 +a2 +60 +02 +64 +13 +d5 +e7 +01 +97 +07 +00 +00 +93 +87 +87 +26 +aa +97 +8c +c3 +41 +01 +82 +80 +d7 +ff +ff +ff +d8 +ff +ff +ff +d9 +ff +ff +ff +e7 +ff +ff +ff +e8 +ff +ff +ff +e9 +ff +ff +ff +f7 +ff +ff +ff +f8 +ff +ff +ff +f9 +ff +ff +ff +fd +ff +ff +ff +fe +ff +ff +ff +ff +ff +ff +ff +00 +00 +00 +00 +01 +00 +00 +00 +02 +00 +00 +00 +03 +00 +00 +00 +07 +00 +00 +00 +08 +00 +00 +00 +09 +00 +00 +00 +17 +00 +00 +00 +18 +00 +00 +00 +19 +00 +00 +00 +27 +00 +00 +00 +28 +00 +00 +00 +29 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +01 +00 +00 +00 +02 +00 +00 +00 +04 +00 +00 +00 +08 +00 +00 +00 +13 +00 +00 +00 +14 +00 +00 +00 +1f +00 +00 +00 +01 +ee +d0 +ba +00 +00 +00 +00 \ No newline at end of file diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/ws-round-edges/simulation/tb_cpu.sv b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/ws-round-edges/simulation/tb_cpu.sv new file mode 100644 index 0000000..6a5e8de --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/ws-round-edges/simulation/tb_cpu.sv @@ -0,0 +1,153 @@ +`timescale 1ns/1ps +module tb; + reg clock=0; + reg reset=0; + reg interrupt=0; + wire memory_aw_ready; + wire memory_aw_valid; + wire [3:0] memory_aw_bits_id; + wire [31:0] memory_aw_bits_addr; + wire [7:0] memory_aw_bits_len; + wire [2:0] memory_aw_bits_size; + wire [1:0] memory_aw_bits_burst; + wire memory_aw_bits_lock; + wire [3:0] memory_aw_bits_cache; + wire [2:0] memory_aw_bits_prot; + wire [3:0] memory_aw_bits_qos; + wire memory_w_ready; + wire memory_w_valid; + wire [127:0] memory_w_bits_data; + wire [15:0] memory_w_bits_strb; + wire memory_w_bits_last; + wire memory_b_ready; + wire memory_b_valid; + wire [3:0] memory_b_bits_id; + wire [1:0] memory_b_bits_resp; + wire memory_ar_ready; + wire memory_ar_valid; + wire [3:0] memory_ar_bits_id; + wire [31:0] memory_ar_bits_addr; + wire [7:0] memory_ar_bits_len; + wire [2:0] memory_ar_bits_size; + wire [1:0] memory_ar_bits_burst; + wire memory_ar_bits_lock; + wire [3:0] memory_ar_bits_cache; + wire [2:0] memory_ar_bits_prot; + wire [3:0] memory_ar_bits_qos; + wire memory_r_ready; + wire memory_r_valid; + wire [3:0] memory_r_bits_id; + wire [127:0] memory_r_bits_data; + wire [1:0] memory_r_bits_resp; + wire memory_r_bits_last; + wire peripherals_aw_ready; + wire peripherals_aw_valid; + wire [1:0] peripherals_aw_bits_id; + wire [30:0] peripherals_aw_bits_addr; + wire [7:0] peripherals_aw_bits_len; + wire [2:0] peripherals_aw_bits_size; + wire [1:0] peripherals_aw_bits_burst; + wire peripherals_aw_bits_lock; + wire [3:0] peripherals_aw_bits_cache; + wire [2:0] peripherals_aw_bits_prot; + wire [3:0] peripherals_aw_bits_qos; + wire peripherals_w_ready; + wire peripherals_w_valid; + wire [63:0] peripherals_w_bits_data; + wire [7:0] peripherals_w_bits_strb; + wire peripherals_w_bits_last; + wire peripherals_b_ready; + wire peripherals_b_valid; + wire [1:0] peripherals_b_bits_id; + wire [1:0] peripherals_b_bits_resp; + wire peripherals_ar_ready; + wire peripherals_ar_valid; + wire [1:0] peripherals_ar_bits_id; + wire [30:0] peripherals_ar_bits_addr; + wire [7:0] peripherals_ar_bits_len; + wire [2:0] peripherals_ar_bits_size; + wire [1:0] peripherals_ar_bits_burst; + wire peripherals_ar_bits_lock; + wire [3:0] peripherals_ar_bits_cache; + wire [2:0] peripherals_ar_bits_prot; + wire [3:0] peripherals_ar_bits_qos; + wire peripherals_r_ready; + wire peripherals_r_valid; + wire [1:0] peripherals_r_bits_id; + wire [63:0] peripherals_r_bits_data; + wire [1:0] peripherals_r_bits_resp; + wire peripherals_r_bits_last; + ToyLinuxChip dut(.*); + integer cycle_count=0; + always @(posedge clock) if (!reset) cycle_count<=cycle_count+1; + always #5 clock=~clock; + initial begin reset=1; repeat(20) @(negedge clock); reset=0; end + initial begin repeat(5000000) @(posedge clock); $fatal(1,"CPU timeout"); end + axi_smoke_memory #(.DATA_BITS(128), .ID_BITS(4), .ADDR_BITS(32), .BASE(32'h80000000), .CAPACITY(262144), .IMAGE("smoke.hex")) memory_model ( + .clock(clock), + .reset(reset), + .aw_ready(memory_aw_ready), + .aw_valid(memory_aw_valid), + .aw_bits_id(memory_aw_bits_id), + .aw_bits_addr(memory_aw_bits_addr), + .aw_bits_len(memory_aw_bits_len), + .aw_bits_size(memory_aw_bits_size), + .aw_bits_burst(memory_aw_bits_burst), + .w_ready(memory_w_ready), + .w_valid(memory_w_valid), + .w_bits_data(memory_w_bits_data), + .w_bits_strb(memory_w_bits_strb), + .w_bits_last(memory_w_bits_last), + .b_ready(memory_b_ready), + .b_valid(memory_b_valid), + .b_bits_id(memory_b_bits_id), + .b_bits_resp(memory_b_bits_resp), + .ar_ready(memory_ar_ready), + .ar_valid(memory_ar_valid), + .ar_bits_id(memory_ar_bits_id), + .ar_bits_addr(memory_ar_bits_addr), + .ar_bits_len(memory_ar_bits_len), + .ar_bits_size(memory_ar_bits_size), + .ar_bits_burst(memory_ar_bits_burst), + .r_ready(memory_r_ready), + .r_valid(memory_r_valid), + .r_bits_id(memory_r_bits_id), + .r_bits_data(memory_r_bits_data), + .r_bits_resp(memory_r_bits_resp), + .r_bits_last(memory_r_bits_last) + ); + axi_smoke_memory #(.DATA_BITS(64), .ID_BITS(2), .ADDR_BITS(31), .BASE(32'h60000000), .CAPACITY(4096), .MONITOR(1), .TEST_LABEL("whole Toy 64 OS WS RNE edge cases 4096 results")) peripherals_model ( + .clock(clock), + .reset(reset), + .aw_ready(peripherals_aw_ready), + .aw_valid(peripherals_aw_valid), + .aw_bits_id(peripherals_aw_bits_id), + .aw_bits_addr(peripherals_aw_bits_addr), + .aw_bits_len(peripherals_aw_bits_len), + .aw_bits_size(peripherals_aw_bits_size), + .aw_bits_burst(peripherals_aw_bits_burst), + .w_ready(peripherals_w_ready), + .w_valid(peripherals_w_valid), + .w_bits_data(peripherals_w_bits_data), + .w_bits_strb(peripherals_w_bits_strb), + .w_bits_last(peripherals_w_bits_last), + .b_ready(peripherals_b_ready), + .b_valid(peripherals_b_valid), + .b_bits_id(peripherals_b_bits_id), + .b_bits_resp(peripherals_b_bits_resp), + .ar_ready(peripherals_ar_ready), + .ar_valid(peripherals_ar_valid), + .ar_bits_id(peripherals_ar_bits_id), + .ar_bits_addr(peripherals_ar_bits_addr), + .ar_bits_len(peripherals_ar_bits_len), + .ar_bits_size(peripherals_ar_bits_size), + .ar_bits_burst(peripherals_ar_bits_burst), + .r_ready(peripherals_r_ready), + .r_valid(peripherals_r_valid), + .r_bits_id(peripherals_r_bits_id), + .r_bits_data(peripherals_r_bits_data), + .r_bits_resp(peripherals_r_bits_resp), + .r_bits_last(peripherals_r_bits_last) + ); + final $display("MEASURE cycles=%0d memory_reads=%0d memory_writes=%0d", cycle_count, memory_model.read_bursts, memory_model.write_bursts); +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/ws-round-edges/simulation/verilator-build.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/ws-round-edges/simulation/verilator-build.log new file mode 100644 index 0000000..0942b52 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/ws-round-edges/simulation/verilator-build.log @@ -0,0 +1,2123 @@ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 31 | module NonSyncResetSynchronizerPrimitiveShiftReg_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ + ... For warning description see https://verilator.org/warn/TIMESCALEMOD?v=5.050 + ... Use "/* verilator lint_off TIMESCALEMOD */" and lint_on around source to disable this message. +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:48:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 48 | module SynchronizerShiftReg_w1_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:61:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 61 | module IntSyncAsyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:74:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 74 | module AsyncResetRegVec_w1_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 103 | module IntSyncCrossingSource_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:118:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 118 | module FixedClockBroadcast_3( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:139:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 139 | module TLMonitor( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:987:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 987 | module TLMonitor_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:2434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 2434 | module TLXbar_sbus_i2_o3_a32d128s3k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:3195:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3195 | module TLMonitor_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4151 | module Repeater_TLBundleA_a28d128s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4218 | module TLWidthWidget16( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4386 | module TLInterconnectCoupler_sbus_to_bus_named_cbus( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4478:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4478 | module ram_2x58( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4497:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4497 | module Queue2_AXI4BundleAW( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4581:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4581 | module ram_2x73( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4600:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4600 | module Queue2_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4657:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4657 | module ram_2x4( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4676:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4676 | module Queue2_AXI4BundleB( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4729:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4729 | module Queue2_AXI4BundleAR( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4813:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4813 | module ram_2x69( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4832:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4832 | module Queue2_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4891:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4891 | module AXI4Buffer( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5067:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5067 | module ram_2x8( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5086:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5086 | module Queue2_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5143:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5143 | module Queue1_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5178 | module AXI4UserYanker( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5540:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5540 | module ram_8x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5559:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5559 | module Queue8_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5631 | module AXI4Deinterleaver( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:6073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6073 | module AXI4IdIndexer( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:6219:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6219 | module TLMonitor_3( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7048:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7048 | module Queue1_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7082:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7082 | module Queue1_AXI4BundleARW( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7148:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7148 | module TLToAXI4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7529:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7529 | module TLMonitor_4( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8396:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8396 | module Repeater_TLBundleA_a31d128s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8463 | module TLWidthWidget16_2( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8623:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8623 | module TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:9400:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 9400 | module SystemBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10050 | module FixedClockBroadcast_4( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10073 | module TLMonitor_5( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10975:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10975 | module TLXbar_cbus_out_i1_o4_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:11288:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +11288 | module TLMonitor_6( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12202:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12202 | module ram_2x114( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12221 | module Queue2_TLBundleA_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12301 | module ram_2x79( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12320:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12320 | module Queue2_TLBundleD_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12399:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12399 | module TLBuffer_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12534:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12534 | module TLMonitor_7( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:13449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13449 | module TLAtomicAutomata_cbus( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:13973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13973 | module TLMonitor_8( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14799 | module Queue1_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14846:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14846 | module TLError( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14953 | module TLMonitor_9( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15857 | module ram_2x100( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15876:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15876 | module Queue2_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15955:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15955 | module Queue2_TLBundleD_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16028 | module TLBuffer_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16155 | module ErrorDeviceWrapper( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16258 | module TLMonitor_10( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17017:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17017 | module Repeater_TLBundleA_a26d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17081:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17081 | module TLFragmenter_CLINT( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17261:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17261 | module TLInterconnectCoupler_cbus_to_clint( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17336:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17336 | module TLMonitor_11( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18106:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18106 | module Repeater_TLBundleA_a28d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18170:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18170 | module TLFragmenter_PLIC( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18350 | module TLInterconnectCoupler_cbus_to_plic( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18425:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18425 | module TLMonitor_12( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19040 | module Repeater_TLBundleA_a17d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19104:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19104 | module TLFragmenter_bootrom( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19263:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19263 | module TLInterconnectCoupler_cbus_to_bootrom( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19330:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19330 | module PeripheryBus_cbus( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19882 | module TLMonitor_13( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20610:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20610 | module ProbePicker( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20688:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20688 | module ram_2x10( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20707:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20707 | module Queue2_BundleMap_6( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20764:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20764 | module AXI4UserYanker_1( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:21713:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21713 | module AXI4IdIndexer_1( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:21859:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21859 | module TLMonitor_14( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22587:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22587 | module Queue1_AXI4BundleW_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22621 | module Queue1_AXI4BundleARW_1( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22687:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22687 | module TLToAXI4_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:23555:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +23555 | module TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:24031:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24031 | module MemoryBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:24349:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24349 | module TLMonitor_15( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25732:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25732 | module BroadcastFilter( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25756:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25756 | module ram_4x144( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25775:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25775 | module Queue4_TLBroadcastData( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25828:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25828 | module TLBroadcastTracker( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25964:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25964 | module TLBroadcastTracker_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:26100:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26100 | module TLBroadcast( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:26686:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26686 | module TLMonitor_16( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27414 | module BankBinder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27491:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27491 | module CoherenceManagerWrapper( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27669:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27669 | module TLMonitor_17( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29229:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29229 | module TLMonitor_18( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29635:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29635 | module TLXbar_MasterXbar_BBTile_i2_o1_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29898 | module IntXbar_i4_o1( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29918:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29918 | module WritebackUnit( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30014:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30014 | module ProbeUnit( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30154:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30154 | module Arbiter1_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30168:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30168 | module Arbiter1_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30191 | module Arbiter1_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30214 | module Arbiter1_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30249:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30249 | module Arbiter1_Bool( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30258 | module ram_16x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30277:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30277 | module Queue16_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30360:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30360 | module Queue1_TLBundleE_a32d128s1k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30388:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30388 | module MSHR( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30835:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30835 | module Arbiter1_HellaCacheResp( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30879:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30879 | module IOMSHR( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31790:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31790 | module sdq_17x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31809 | module MSHRFile( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32350 | module OptimizationBarrier_TLBEntryData( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32406:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32406 | module PMPChecker_s3( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32691:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32691 | module PMAChecker( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32731:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32731 | module DTLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:35923:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35923 | module L1MetadataArray( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:35990:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35990 | module Arbiter5_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36023:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36023 | module Arbiter2_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36055 | module DataArray( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36151 | module Arbiter4_L1DataReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36180:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36180 | module Arbiter2_L1DataWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36206:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36206 | module AMOALU( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36248:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36248 | module MaxPeriodFibonacciLFSR( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36342:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36342 | module Arbiter2_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36377:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36377 | module NonBlockingDCache( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:37660:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37660 | module ICache( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:37914:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37914 | module ShiftQueue( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:38054:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38054 | module PMPChecker_s2( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:38215:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38215 | module ITLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:41129:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41129 | module Frontend( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:41494:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41494 | module TLMonitor_19( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:42301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +42301 | module TLMonitor_20( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43108:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43108 | module TLXbar_i2_o1_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43343 | module TLMonitor_21( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43851:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43851 | module ram_2x116( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43870:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43870 | module Queue2_TLBundleA_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43947:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43947 | module ram_2x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43966:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43966 | module Queue2_TLBundleD_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44045:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44045 | module TLBuffer_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44158:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44158 | module TLMonitor_22( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44783 | module TLBuffer_a32d64s1k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44892:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44892 | module TLMonitor_23( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:45699:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45699 | module Repeater_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:45766:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45766 | module TLWidthWidget8_4( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46074:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46074 | module TLMonitor_24( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46882 | module ram_2x117( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46901:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46901 | module Queue2_TLBundleA_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46981:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46981 | module ram_2x78( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47000:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47000 | module Queue2_TLBundleD_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47079:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47079 | module TLBuffer_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47214 | module HellaCacheArbiter( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47381 | module Arbiter3_Valid_PTWReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47419:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47419 | module OptimizationBarrier_UInt( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47427 | module OptimizationBarrier_PTE( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47459 | module PTW( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:48434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +48434 | module FPUDecoder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49794:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49794 | module CompareRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49824:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49824 | module RecFNToIN_e11_s53_i64( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49873:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49873 | module RecFNToIN_e11_s53_i32( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49912:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49912 | module FPToInt( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50375:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50375 | module RoundAnyRawFNToRecFN_ie7_is64_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50410:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50410 | module PipelinedINToRecFN( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50513:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50513 | module RoundAnyRawFNToRecFN_ie7_is64_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50539 | module PipelinedINToRecFN_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50614 | module RoundAnyRawFNToRecFN_ie7_is64_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50642:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50642 | module PipelinedINToRecFN_2( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50717 | module IntToFP( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51072:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51072 | module RoundAnyRawFNToRecFN_ie11_is53_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51199:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51199 | module RecFNToRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51221 | module RoundAnyRawFNToRecFN_ie11_is53_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51321:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51321 | module RecFNToRecFN_1( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51343 | module FPToFP( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51469:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51469 | module MulAddRecFNToRaw_preMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51569 | module MulAddRecFNToRaw_postMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51822:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51822 | module RoundAnyRawFNToRecFN_ie11_is55_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51953 | module RoundAnyRawFNToRecFN_ie11_is55_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52060:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52060 | module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52194:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52194 | module SharedMulAddRecFNPipe( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52551:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52551 | module FPUSharedFMAPipe( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52682:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52682 | module DivSqrtRawFN_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52852:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52852 | module DivSqrtRecFMToRaw_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52907:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52907 | module RoundAnyRawFNToRecFN_ie5_is13_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53039:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53039 | module RoundRawFNToRecFN_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53068:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53068 | module DivSqrtRecFM_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53128:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53128 | module DivSqrtRawFN_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53297:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53297 | module DivSqrtRecFMToRaw_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53352:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53352 | module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53456:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53456 | module RoundRawFNToRecFN_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53485:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53485 | module DivSqrtRecFM_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53545:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53545 | module DivSqrtRawFN_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53715:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53715 | module DivSqrtRecFMToRaw_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53770:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53770 | module RoundRawFNToRecFN_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53799 | module DivSqrtRecFM_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53860:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53860 | module regfile_32x65( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53905:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53905 | module FPU( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:54820:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +54820 | module RVCExpander( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:55183:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55183 | module IBuf( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:55307:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55307 | module CSRFile( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:57223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57223 | module RocketALU( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:57809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57809 | module MulDiv( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:58107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58107 | module Arbiter3_LLWB( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:58125:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58125 | module rf_31x64( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:58149:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58149 | module RocketBB( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62838:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62838 | module GlobalDecoder( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62928:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62928 | module BankAliasTable( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:64252:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64252 | module BankScoreboard( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:64627:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64627 | module GlobalROB( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68674:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68674 | module Arbiter3_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68717 | module ram_16x4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68736:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68736 | module Queue16_UInt4( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68782:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68782 | module SubROB( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:69357:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69357 | module Arbiter1_SubRobRow( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:69722:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69722 | module GlobalScheduler( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:70973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +70973 | module BootRom( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:71013:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71013 | module Frontend_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:71637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71637 | module PE( + | ^~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:71656:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71656 | module AlwaysOutTransposer( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72411:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72411 | module MacUnit( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72426:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72426 | module PE_64( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72524:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72524 | module Tile( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72571:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72571 | module Mesh( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76050 | module TagQueue( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76191 | module ram_6x7( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76210:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76210 | module Queue6_TagWithIdAndTotalRows( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76271:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76271 | module MeshWithDelays( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77318:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77318 | module ram_data_8x64( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77337 | module Queue8_SramReadResp( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77385:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77385 | module GemminiExCtrl( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79354:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79354 | module LoopMatmulUnroller( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79637 | module LoopConvAddrGen( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79690:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79690 | module LoopConvUnroller( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:80113:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80113 | module LoopCmdEncoder( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:80402:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80402 | module Arbiter2_LoopCmd( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:80598:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80598 | module GemminiBall( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:81783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81783 | module RRArbiter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:81857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81857 | module CmdRouter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:81985:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81985 | module BallCyclePMC( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:82095:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82095 | module BBus( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:82898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82898 | module BallDomainDecoder( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83028 | module ram_4x281( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83047:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83047 | module Queue4_BallReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83178 | module Arbiter1_BallRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83198:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83198 | module BallReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83328:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83328 | module BallDomain( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84141:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84141 | module MemDomainDecoder( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84300:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84300 | module ram_4x158( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84319:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84319 | module Queue4_MemReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84421:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84421 | module Arbiter3_MemRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84463 | module MemReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84631 | module MemLoader( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84869:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84869 | module MemStorer( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85122:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85122 | module MemCyclePMC( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85241:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85241 | module TLB( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85621 | module RRArbiter_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85649:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85649 | module BBTLBCluster( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85777 | module StreamReader( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86142:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86142 | module StreamWriter( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86223 | module ZeroLineGenerator( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86264:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86264 | module MemConfiger( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86433:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86433 | module RRArbiter_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86465:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86465 | module MemGroupQueryArbiter( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86543:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86543 | module MemFrontend( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87160 | module MemMidend( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87621 | module SramBank( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87672:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87672 | module AccPipe( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87781 | module PrivateMemBackend( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:90777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +90777 | module MemBackend( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:91055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91055 | module MemDomain( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:91973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91973 | module Queue1_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92008:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92008 | module GpDomain( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92040 | module ram_8x21( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92059 | module Queue8_BuckyballAccelerator_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92123:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92123 | module BuckyballAccelerator( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93569 | module Queue3_UInt2( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93614 | module SimpleHellaCacheIFReplayQueue( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93667:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93667 | module Arbiter2_HellaCacheReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93678:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93678 | module SimpleHellaCacheIF( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93768:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93768 | module BarrierUnit( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93785:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93785 | module BBTile( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:95579:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +95579 | module TLMonitor_25( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:96427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +96427 | module TLMonitor_26( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98184:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98184 | module ram_2x189( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98203:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98203 | module Queue2_TLBundleA_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98283:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98283 | module ram_2x142( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98302:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98302 | module Queue2_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98381 | module Queue2_TLBundleA_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98459 | module Queue2_TLBundleD_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98539 | module ram_2x60( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98558:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98558 | module Queue2_TLBundleB_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98622:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98622 | module ram_2x173( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98641:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98641 | module Queue2_TLBundleC_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98716:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98716 | module ram_sink_2x1( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98735:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98735 | module Queue2_TLBundleE_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98781 | module TLBuffer_a32d128s2k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99162:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99162 | module IntSyncSyncCrossingSink_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99173:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99173 | module IntSyncSyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99181:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99181 | module TilePRCIDomain( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99589:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99589 | module BundleBridgeNexus_UInt1_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99597:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99597 | module TLMonitor_27( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100216:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100216 | module CLINT( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100337 | module AsyncResetRegVec_w2_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100366:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100366 | module IntSyncCrossingSource_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100386 | module CLINTClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100449 | module TLMonitor_28( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101080:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101080 | module LevelGateway( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101099:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101099 | module PLICFanIn( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101111:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101111 | module Queue1_RegMapperInput_i23_m8( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101160 | module TLPLIC( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101389:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101389 | module PLICClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101452:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101452 | module TLMonitor_29( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101973 | module TLROM( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:102530:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102530 | module bootromClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:102569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102569 | module ToyLinuxSystem( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103817:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103817 | module ToyLinuxChip( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103984:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103984 | module tag_array( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104007:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104007 | module array_0_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104034:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104034 | module array_0_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104059 | module array_2_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104084:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104084 | module array_2_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104109:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104109 | module bbtile_icache_tag_array( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104132:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104132 | module bbtile_icache_data_arrays_0( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104155 | module bbtile_icache_data_arrays_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104176:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104176 | module bbtile_icache_data_arrays_2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104197:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104197 | module bbtile_icache_data_arrays_3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104218 | module robOperands( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104243:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104243 | module sram( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104268:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104268 | module mem( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104301 | module plusarg_reader #( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104326:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104326 | module ITraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104404:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104404 | module FpgaDspMac(input [7:0] a, b, input [19:0] c, output [19:0] y); + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104414 | module PMCTraceDPI( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104464:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104464 | module MemPMCTraceDPI( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104514:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104514 | module MTraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:1:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 1 | module tag_array_ext( input [4:0] RW0_addr, + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 19 | module array_0_0_ext( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:37:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 37 | module bbtile_icache_tag_array_ext( input [5:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:55:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 55 | module bbtile_icache_data_arrays_0_ext( input [7:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:73:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 73 | module robOperands_ext( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:90:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 90 | module sram_ext( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 107 | module mem_ext( input [9:0] RW0_addr, + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:3:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3 | module axi_smoke_memory #( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:52:20: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'addr' generates 31 bits. + : ... note: In instance 'tb.peripherals_model' + 52 | offset=(addr & ~(LANES-1))-BASE; + | ^ + ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=5.050 + ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:78:28: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'write_addr' generates 31 bits. + : ... note: In instance 'tb.peripherals_model' + 78 | offset=(write_addr & ~(LANES-1))-BASE; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:86:26: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'h600d600d' generates 64 bits. + : ... note: In instance 'tb.memory_model' + 86 | if (w_bits_data==64'h600d600d) begin + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:91:66: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff' generates 64 bits. + : ... note: In instance 'tb.memory_model' + 91 | $fatal(1,"CPU smoke failed at stage %0d",w_bits_data & 64'hffff); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:90:28: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff0000' generates 64 bits. + : ... note: In instance 'tb.memory_model' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:90:43: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'hbad00000' generates 64 bits. + : ... note: In instance 'tb.memory_model' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^~ +make: Entering directory '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/obj' +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_timing.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_timing.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_threads.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_threads.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb__pch.h -o Vtb__pch.h.fast.gch +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb__pch.h -o Vtb__pch.h.slow.gch +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb__ConstPool__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__1__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__2__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__3__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb__Syms__Slow.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__0.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__1.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__2.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__3.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__4.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__5.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__6.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__7.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__8.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__9.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb__main.cpp +g++ verilated.o verilated_timing.o verilated_threads.o Vtb__ALL.a -pthread -lpthread -latomic -o Vtb +rm Vtb__ALL.verilator_deplist.tmp +make: Leaving directory '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-round-edges/simulation/obj' +- V e r i l a t i o n R e p o r t: Verilator 5.050 2026-07-01 rev v5.050 +- Verilator: Built from 15.468 MB sources in 346 modules, into 23.746 MB in 19 C++ files needing 0.019 MB +- Verilator: Walltime 15.019 s (elab=0.606, cvt=3.444, bld=10.267); cpu 5.037 s on 8 threads; allocated 433.789 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/ws-shift-edges/simulation/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/ws-shift-edges/simulation/RESULT.json new file mode 100644 index 0000000..71655c1 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/ws-shift-edges/simulation/RESULT.json @@ -0,0 +1,10 @@ +{ + "result": "PASS", + "test_label": "whole Toy 64 OS WS RNE edge cases 4096 results", + "core_rtl_sha256": "31e7e07f94d08208dbb564edf9546240df26ff834935bfb646b71b541d875fb9", + "test_binary_sha256": "07898e3c5d7e61a41c9d655944fef67a4e3b2a085fa6d59e20fedc70fc13f308", + "cycles_including_boot": 978208, + "memory_read_bursts": 3219, + "memory_write_bursts": 2496, + "linux_boot_tested": false +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/ws-shift-edges/simulation/simulation.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/ws-shift-edges/simulation/simulation.log new file mode 100644 index 0000000..3becb10 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/ws-shift-edges/simulation/simulation.log @@ -0,0 +1,7 @@ +CPU status = 00000000600d600d +PASS whole Toy 64 OS WS RNE edge cases 4096 results +- /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:88: Verilog $finish +MEASURE cycles=978208 memory_reads=3219 memory_writes=2496 +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 10ms; walltime 7.258 s; speed 1.348 ms/s +- Verilator: cpu 7.257 s on 1 threads; allocated 8 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/ws-shift-edges/simulation/smoke.bin b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/ws-shift-edges/simulation/smoke.bin new file mode 100644 index 0000000..8b1fe75 Binary files /dev/null and b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/ws-shift-edges/simulation/smoke.bin differ diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/ws-shift-edges/simulation/smoke.disasm b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/ws-shift-edges/simulation/smoke.disasm new file mode 100644 index 0000000..dac24b7 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/ws-shift-edges/simulation/smoke.disasm @@ -0,0 +1,348 @@ + +/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/smoke.elf: file format elf64-littleriscv + + +Disassembly of section .text: + +0000000080000000 <_start>: + 80000000: 00002137 lui sp,0x2 + 80000004: 0011011b addiw sp,sp,1 # 2001 <_start-0x7fffdfff> + 80000008: 01211113 slli sp,sp,0x12 + 8000000c: ff010113 addi sp,sp,-16 + 80000010: 00000297 auipc t0,0x0 + 80000014: 04c28293 addi t0,t0,76 # 8000005c + 80000018: 30529073 csrw mtvec,t0 + 8000001c: 30401073 csrw mie,zero + 80000020: 30201073 csrw medeleg,zero + 80000024: 0001e2b7 lui t0,0x1e + 80000028: 3002a073 csrs mstatus,t0 + 8000002c: 00000097 auipc ra,0x0 + 80000030: 050080e7 jalr 80(ra) # 8000007c
+ 80000034: 600002b7 lui t0,0x60000 + 80000038: 600d6337 lui t1,0x600d6 + 8000003c: 00d3031b addiw t1,t1,13 # 600d600d <_start-0x1ff29ff3> + 80000040: 00050a63 beqz a0,80000054 + 80000044: 00001337 lui t1,0x1 + 80000048: bad3031b addiw t1,t1,-1107 # bad <_start-0x7ffff453> + 8000004c: 01431313 slli t1,t1,0x14 + 80000050: 00a36333 or t1,t1,a0 + +0000000080000054 : + 80000054: 0062b023 sd t1,0(t0) # 60000000 <_start-0x20000000> + 80000058: 0000006f j 80000058 + +000000008000005c : + 8000005c: 342023f3 csrr t2,mcause + 80000060: 600002b7 lui t0,0x60000 + 80000064: 000bb337 lui t1,0xbb + 80000068: d0f3031b addiw t1,t1,-753 # bad0f <_start-0x7ff452f1> + 8000006c: 00c31313 slli t1,t1,0xc + 80000070: 00736333 or t1,t1,t2 + 80000074: 0062b023 sd t1,0(t0) # 60000000 <_start-0x20000000> + 80000078: 0000006f j 80000078 + +000000008000007c
: + 8000007c: 7171 addi sp,sp,-176 + 8000007e: 57fd li a5,-1 + 80000080: 0197d713 srli a4,a5,0x19 + 80000084: ed26 sd s1,152(sp) + 80000086: 00000797 auipc a5,0x0 + 8000008a: 57a78793 addi a5,a5,1402 # 80000600 + 8000008e: 4485 li s1,1 + 80000090: f122 sd s0,160(sp) + 80000092: f0e2 sd s8,96(sp) + 80000094: 1900 addi s0,sp,176 + 80000096: e8ea sd s10,80(sp) + 80000098: f506 sd ra,168(sp) + 8000009a: e94a sd s2,144(sp) + 8000009c: e54e sd s3,136(sp) + 8000009e: e152 sd s4,128(sp) + 800000a0: fcd6 sd s5,120(sp) + 800000a2: f8da sd s6,112(sp) + 800000a4: f4de sd s7,104(sp) + 800000a6: ece6 sd s9,88(sp) + 800000a8: e4ee sd s11,72(sp) + 800000aa: 8ff9 and a5,a5,a4 + 800000ac: 02749c13 slli s8,s1,0x27 + 800000b0: 0187e7b3 or a5,a5,s8 + 800000b4: f4f43c23 sd a5,-168(s0) + 800000b8: 00000797 auipc a5,0x0 + 800000bc: 3d878793 addi a5,a5,984 # 80000490 + 800000c0: f8e43023 sd a4,-128(s0) + 800000c4: f8f43423 sd a5,-120(s0) + 800000c8: f6043823 sd zero,-144(s0) + 800000cc: 00000d17 auipc s10,0x0 + 800000d0: 35cd0d13 addi s10,s10,860 # 80000428 + 800000d4: 51eb8937 lui s2,0x51eb8 + 800000d8: 51f90913 addi s2,s2,1311 # 51eb851f <_start-0x2e147ae1> + 800000dc: 4c81 li s9,0 + 800000de: 4b09 li s6,2 + 800000e0: 003c979b slliw a5,s9,0x3 + 800000e4: 4b81 li s7,0 + 800000e6: f6f43c23 sd a5,-136(s0) + 800000ea: f7843783 ld a5,-136(s0) + 800000ee: 00000997 auipc s3,0x0 + 800000f2: 55298993 addi s3,s3,1362 # 80000640 + 800000f6: 00000a17 auipc s4,0x0 + 800000fa: 4caa0a13 addi s4,s4,1226 # 800005c0 + 800000fe: 00000a97 auipc s5,0x0 + 80000102: 3c2a8a93 addi s5,s5,962 # 800004c0 + 80000106: 12345f37 lui t5,0x12345 + 8000010a: 8e52 mv t3,s4 + 8000010c: 8856 mv a6,s5 + 8000010e: 854e mv a0,s3 + 80000110: 678f0f13 addi t5,t5,1656 # 12345678 <_start-0x6dcba988> + 80000114: 4197833b subw t1,a5,s9 + 80000118: 00000897 auipc a7,0x0 + 8000011c: 4e888893 addi a7,a7,1256 # 80000600 + 80000120: 4e81 li t4,0 + 80000122: 428d li t0,3 + 80000124: f8000393 li t2,-128 + 80000128: 4fa1 li t6,8 + 8000012a: f7743423 sd s7,-152(s0) + 8000012e: f7343023 sd s3,-160(s0) + 80000132: 85aa mv a1,a0 + 80000134: 8642 mv a2,a6 + 80000136: 4701 li a4,0 + 80000138: a0a9 j 80000182 + 8000013a: 032686b3 mul a3,a3,s2 + 8000013e: 4d81 li s11,0 + 80000140: 073e8363 beq t4,s3,800001a6 + 80000144: 928d srli a3,a3,0x23 + 80000146: 0016999b slliw s3,a3,0x1 + 8000014a: 00d989bb addw s3,s3,a3 + 8000014e: 0039999b slliw s3,s3,0x3 + 80000152: 00d989bb addw s3,s3,a3 + 80000156: 413787bb subw a5,a5,s3 + 8000015a: 078a slli a5,a5,0x2 + 8000015c: 97ea add a5,a5,s10 + 8000015e: 439c lw a5,0(a5) + 80000160: 01b58023 sb s11,0(a1) + 80000164: 00e886b3 add a3,a7,a4 + 80000168: 00f68023 sb a5,0(a3) + 8000016c: 00ee07b3 add a5,t3,a4 + 80000170: 01e62023 sw t5,0(a2) + 80000174: 00078023 sb zero,0(a5) + 80000178: 0705 addi a4,a4,1 + 8000017a: 0611 addi a2,a2,4 + 8000017c: 0585 addi a1,a1,1 + 8000017e: 03f70963 beq a4,t6,800001b0 + 80000182: 0007099b sext.w s3,a4 + 80000186: 006987bb addw a5,s3,t1 + 8000018a: 02079693 slli a3,a5,0x20 + 8000018e: 9281 srli a3,a3,0x20 + 80000190: fa5c95e3 bne s9,t0,8000013a + 80000194: 03f71693 slli a3,a4,0x3f + 80000198: 43f6d793 srai a5,a3,0x3f + 8000019c: 00758023 sb t2,0(a1) + 800001a0: f807c793 xori a5,a5,-128 + 800001a4: b7c1 j 80000164 + 800001a6: 4d91 li s11,4 + 800001a8: f96c8ee3 beq s9,s6,80000144 + 800001ac: 4d85 li s11,1 + 800001ae: bf59 j 80000144 + 800001b0: 2e85 addiw t4,t4,1 + 800001b2: 08a1 addi a7,a7,8 + 800001b4: 0e21 addi t3,t3,8 + 800001b6: 2321 addiw t1,t1,8 + 800001b8: 02080813 addi a6,a6,32 + 800001bc: 0521 addi a0,a0,8 + 800001be: f6ee9ae3 bne t4,a4,80000132 + 800001c2: 4585 li a1,1 + 800001c4: 4501 li a0,0 + 800001c6: f6043983 ld s3,-160(s0) + 800001ca: 00000097 auipc ra,0x0 + 800001ce: 220080e7 jalr 544(ra) # 800003ea + 800001d2: 4701 li a4,0 + 800001d4: 42100d93 li s11,1057 + 800001d8: 41b7307b .insn 4, 0x41b7307b + 800001dc: 4585 li a1,1 + 800001de: 852e mv a0,a1 + 800001e0: 00000097 auipc ra,0x0 + 800001e4: 20a080e7 jalr 522(ra) # 800003ea + 800001e8: 41b4b07b .insn 4, 0x41b4b07b + 800001ec: 4585 li a1,1 + 800001ee: 4509 li a0,2 + 800001f0: 00000097 auipc ra,0x0 + 800001f4: 1fa080e7 jalr 506(ra) # 800003ea + 800001f8: 4709 li a4,2 + 800001fa: 41b7307b .insn 4, 0x41b7307b + 800001fe: 4591 li a1,4 + 80000200: 450d li a0,3 + 80000202: 00000097 auipc ra,0x0 + 80000206: 1e8080e7 jalr 488(ra) # 800003ea + 8000020a: 478d li a5,3 + 8000020c: 48100713 li a4,1153 + 80000210: 40e7b07b .insn 4, 0x40e7b07b + 80000214: 0000100f fence.i + 80000218: f5843703 ld a4,-168(s0) + 8000021c: 02149793 slli a5,s1,0x21 + 80000220: 42e7b07b .insn 4, 0x42e7b07b + 80000224: 0000100f fence.i + 80000228: f8043683 ld a3,-128(s0) + 8000022c: 020017b7 lui a5,0x2001 + 80000230: 07a2 slli a5,a5,0x8 + 80000232: 00d9f733 and a4,s3,a3 + 80000236: 01876733 or a4,a4,s8 + 8000023a: 42e7b07b .insn 4, 0x42e7b07b + 8000023e: 0000100f fence.i + 80000242: 010017b7 lui a5,0x1001 + 80000246: 00da7733 and a4,s4,a3 + 8000024a: 01876733 or a4,a4,s8 + 8000024e: 07a6 slli a5,a5,0x9 + 80000250: 42e7b07b .insn 4, 0x42e7b07b + 80000254: f8843783 ld a5,-120(s0) + 80000258: 004b9713 slli a4,s7,0x4 + 8000025c: 4601 li a2,0 + 8000025e: 439c lw a5,0(a5) + 80000260: 02079593 slli a1,a5,0x20 + 80000264: 0175d793 srli a5,a1,0x17 + 80000268: 8fd9 or a5,a5,a4 + 8000026a: 04f6307b .insn 4, 0x04f6307b + 8000026e: f6843683 ld a3,-152(s0) + 80000272: 02003737 lui a4,0x2003 + 80000276: 0722 slli a4,a4,0x8 + 80000278: 0016c793 xori a5,a3,1 + 8000027c: 2781 sext.w a5,a5 + 8000027e: 8fd9 or a5,a5,a4 + 80000280: 6a97b07b .insn 4, 0x6a97b07b + 80000284: 00170793 addi a5,a4,1 # 2003001 <_start-0x7dffcfff> + 80000288: 000b8963 beqz s7,8000029a + 8000028c: 002007b7 lui a5,0x200 + 80000290: 30178793 addi a5,a5,769 # 200301 <_start-0x7fdffcff> + 80000294: 07b2 slli a5,a5,0xc + 80000296: 80178793 addi a5,a5,-2047 + 8000029a: 4709 li a4,2 + 8000029c: 84e7b07b .insn 4, 0x84e7b07b + 800002a0: 0000100f fence.i + 800002a4: f8043703 ld a4,-128(s0) + 800002a8: 4785 li a5,1 + 800002aa: 1786 slli a5,a5,0x21 + 800002ac: 00eaf733 and a4,s5,a4 + 800002b0: 01876733 or a4,a4,s8 + 800002b4: 078d addi a5,a5,3 + 800002b6: 20e7b07b .insn 4, 0x20e7b07b + 800002ba: 4781 li a5,0 + 800002bc: 00f7b07b .insn 4, 0x00f7b07b + 800002c0: 0330000f fence rw,rw + 800002c4: 0000100f fence.i + 800002c8: f8843783 ld a5,-120(s0) + 800002cc: 4e21 li t3,8 + 800002ce: 04000f13 li t5,64 + 800002d2: 0007a883 lw a7,0(a5) + 800002d6: 4781 li a5,0 + 800002d8: 01149333 sll t1,s1,a7 + 800002dc: fff30e93 addi t4,t1,-1 + 800002e0: 00000817 auipc a6,0x0 + 800002e4: 36080813 addi a6,a6,864 # 80000640 + 800002e8: 8fd6 mv t6,s5 + 800002ea: 4501 li a0,0 + 800002ec: 00aa0733 add a4,s4,a0 + 800002f0: 00070583 lb a1,0(a4) + 800002f4: fc080693 addi a3,a6,-64 + 800002f8: 864e mv a2,s3 + 800002fa: 00060703 lb a4,0(a2) + 800002fe: 00068283 lb t0,0(a3) + 80000302: 06a1 addi a3,a3,8 + 80000304: 0605 addi a2,a2,1 + 80000306: 0257073b mulw a4,a4,t0 + 8000030a: 9f2d addw a4,a4,a1 + 8000030c: 85ba mv a1,a4 + 8000030e: ff0696e3 bne a3,a6,800002fa + 80000312: 000fa603 lw a2,0(t6) + 80000316: 02088663 beqz a7,80000342 + 8000031a: 41f7559b sraiw a1,a4,0x1f + 8000031e: 00b746b3 xor a3,a4,a1 + 80000322: 9e8d subw a3,a3,a1 + 80000324: 1682 slli a3,a3,0x20 + 80000326: 9281 srli a3,a3,0x20 + 80000328: 00def5b3 and a1,t4,a3 + 8000032c: 0586 slli a1,a1,0x1 + 8000032e: 4116d6b3 sra a3,a3,a7 + 80000332: 0ab34a63 blt t1,a1,800003e6 + 80000336: 0ab30563 beq t1,a1,800003e0 + 8000033a: 0006859b sext.w a1,a3 + 8000033e: 06074a63 bltz a4,800003b2 + 80000342: 06b61c63 bne a2,a1,800003ba + 80000346: 0505 addi a0,a0,1 + 80000348: 0f91 addi t6,t6,4 + 8000034a: 0805 addi a6,a6,1 + 8000034c: fbc510e3 bne a0,t3,800002ec + 80000350: 07a1 addi a5,a5,8 + 80000352: 09a1 addi s3,s3,8 + 80000354: 020a8a93 addi s5,s5,32 + 80000358: 0a21 addi s4,s4,8 + 8000035a: f9e793e3 bne a5,t5,800002e0 + 8000035e: 4981 li s3,0 + 80000360: 4a11 li s4,4 + 80000362: 4585 li a1,1 + 80000364: 0009851b sext.w a0,s3 + 80000368: 00000097 auipc ra,0x0 + 8000036c: 082080e7 jalr 130(ra) # 800003ea + 80000370: 4781 li a5,0 + 80000372: 40f9b07b .insn 4, 0x40f9b07b + 80000376: 0985 addi s3,s3,1 + 80000378: ff4995e3 bne s3,s4,80000362 + 8000037c: f7043683 ld a3,-144(s0) + 80000380: 001b8713 addi a4,s7,1 + 80000384: 4789 li a5,2 + 80000386: 2685 addiw a3,a3,1 + 80000388: f6d43823 sd a3,-144(s0) + 8000038c: 4b85 li s7,1 + 8000038e: d4f71ee3 bne a4,a5,800000ea + 80000392: 2c85 addiw s9,s9,1 + 80000394: d53c96e3 bne s9,s3,800000e0 + 80000398: f8843783 ld a5,-120(s0) + 8000039c: 00000717 auipc a4,0x0 + 800003a0: 11470713 addi a4,a4,276 # 800004b0 + 800003a4: 0791 addi a5,a5,4 + 800003a6: f8f43423 sd a5,-120(s0) + 800003aa: d2e795e3 bne a5,a4,800000d4 + 800003ae: 4501 li a0,0 + 800003b0: a809 j 800003c2 + 800003b2: 40d005bb negw a1,a3 + 800003b6: f8b608e3 beq a2,a1,80000346 + 800003ba: f7043783 ld a5,-144(s0) + 800003be: 0017851b addiw a0,a5,1 + 800003c2: 70aa ld ra,168(sp) + 800003c4: 740a ld s0,160(sp) + 800003c6: 64ea ld s1,152(sp) + 800003c8: 694a ld s2,144(sp) + 800003ca: 69aa ld s3,136(sp) + 800003cc: 6a0a ld s4,128(sp) + 800003ce: 7ae6 ld s5,120(sp) + 800003d0: 7b46 ld s6,112(sp) + 800003d2: 7ba6 ld s7,104(sp) + 800003d4: 7c06 ld s8,96(sp) + 800003d6: 6ce6 ld s9,88(sp) + 800003d8: 6d46 ld s10,80(sp) + 800003da: 6da6 ld s11,72(sp) + 800003dc: 614d addi sp,sp,176 + 800003de: 8082 ret + 800003e0: 0016f593 andi a1,a3,1 + 800003e4: d9b9 beqz a1,8000033a + 800003e6: 0685 addi a3,a3,1 + 800003e8: bf89 j 8000033a + +00000000800003ea : + 800003ea: 1141 addi sp,sp,-16 + 800003ec: e022 sd s0,0(sp) + 800003ee: e406 sd ra,8(sp) + 800003f0: 0800 addi s0,sp,16 + 800003f2: 47bd li a5,15 + 800003f4: 00a7fa63 bgeu a5,a0,80000408 + 800003f8: 00000717 auipc a4,0x0 + 800003fc: 0b873703 ld a4,184(a4) # 800004b0 + 80000400: 600007b7 lui a5,0x60000 + 80000404: e398 sd a4,0(a5) + 80000406: a001 j 80000406 + 80000408: 02051793 slli a5,a0,0x20 + 8000040c: 60a2 ld ra,8(sp) + 8000040e: 6402 ld s0,0(sp) + 80000410: 01e7d513 srli a0,a5,0x1e + 80000414: 00000797 auipc a5,0x0 + 80000418: 26c78793 addi a5,a5,620 # 80000680 + 8000041c: 97aa add a5,a5,a0 + 8000041e: c38c sw a1,0(a5) + 80000420: 0141 addi sp,sp,16 + 80000422: 8082 ret diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/ws-shift-edges/simulation/smoke.elf b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/ws-shift-edges/simulation/smoke.elf new file mode 100644 index 0000000..bff5cc1 Binary files /dev/null and b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/ws-shift-edges/simulation/smoke.elf differ diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/ws-shift-edges/simulation/smoke.hex b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/ws-shift-edges/simulation/smoke.hex new file mode 100644 index 0000000..0687153 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/ws-shift-edges/simulation/smoke.hex @@ -0,0 +1,1208 @@ +37 +21 +00 +00 +1b +01 +11 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b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/ws-shift-edges/simulation/tb_cpu.sv new file mode 100644 index 0000000..6a5e8de --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/ws-shift-edges/simulation/tb_cpu.sv @@ -0,0 +1,153 @@ +`timescale 1ns/1ps +module tb; + reg clock=0; + reg reset=0; + reg interrupt=0; + wire memory_aw_ready; + wire memory_aw_valid; + wire [3:0] memory_aw_bits_id; + wire [31:0] memory_aw_bits_addr; + wire [7:0] memory_aw_bits_len; + wire [2:0] memory_aw_bits_size; + wire [1:0] memory_aw_bits_burst; + wire memory_aw_bits_lock; + wire [3:0] memory_aw_bits_cache; + wire [2:0] memory_aw_bits_prot; + wire [3:0] memory_aw_bits_qos; + wire memory_w_ready; + wire memory_w_valid; + wire [127:0] memory_w_bits_data; + wire [15:0] memory_w_bits_strb; + wire memory_w_bits_last; + wire memory_b_ready; + wire memory_b_valid; + wire [3:0] memory_b_bits_id; + wire [1:0] memory_b_bits_resp; + wire memory_ar_ready; + wire memory_ar_valid; + wire [3:0] memory_ar_bits_id; + wire [31:0] memory_ar_bits_addr; + wire [7:0] memory_ar_bits_len; + wire [2:0] memory_ar_bits_size; + wire [1:0] memory_ar_bits_burst; + wire memory_ar_bits_lock; + wire [3:0] memory_ar_bits_cache; + wire [2:0] memory_ar_bits_prot; + wire [3:0] memory_ar_bits_qos; + wire memory_r_ready; + wire memory_r_valid; + wire [3:0] memory_r_bits_id; + wire [127:0] memory_r_bits_data; + wire [1:0] memory_r_bits_resp; + wire memory_r_bits_last; + wire peripherals_aw_ready; + wire peripherals_aw_valid; + wire [1:0] peripherals_aw_bits_id; + wire [30:0] peripherals_aw_bits_addr; + wire [7:0] peripherals_aw_bits_len; + wire [2:0] peripherals_aw_bits_size; + wire [1:0] peripherals_aw_bits_burst; + wire peripherals_aw_bits_lock; + wire [3:0] peripherals_aw_bits_cache; + wire [2:0] peripherals_aw_bits_prot; + wire [3:0] peripherals_aw_bits_qos; + wire peripherals_w_ready; + wire peripherals_w_valid; + wire [63:0] peripherals_w_bits_data; + wire [7:0] peripherals_w_bits_strb; + wire peripherals_w_bits_last; + wire peripherals_b_ready; + wire peripherals_b_valid; + wire [1:0] peripherals_b_bits_id; + wire [1:0] peripherals_b_bits_resp; + wire peripherals_ar_ready; + wire peripherals_ar_valid; + wire [1:0] peripherals_ar_bits_id; + wire [30:0] peripherals_ar_bits_addr; + wire [7:0] peripherals_ar_bits_len; + wire [2:0] peripherals_ar_bits_size; + wire [1:0] peripherals_ar_bits_burst; + wire peripherals_ar_bits_lock; + wire [3:0] peripherals_ar_bits_cache; + wire [2:0] peripherals_ar_bits_prot; + wire [3:0] peripherals_ar_bits_qos; + wire peripherals_r_ready; + wire peripherals_r_valid; + wire [1:0] peripherals_r_bits_id; + wire [63:0] peripherals_r_bits_data; + wire [1:0] peripherals_r_bits_resp; + wire peripherals_r_bits_last; + ToyLinuxChip dut(.*); + integer cycle_count=0; + always @(posedge clock) if (!reset) cycle_count<=cycle_count+1; + always #5 clock=~clock; + initial begin reset=1; repeat(20) @(negedge clock); reset=0; end + initial begin repeat(5000000) @(posedge clock); $fatal(1,"CPU timeout"); end + axi_smoke_memory #(.DATA_BITS(128), .ID_BITS(4), .ADDR_BITS(32), .BASE(32'h80000000), .CAPACITY(262144), .IMAGE("smoke.hex")) memory_model ( + .clock(clock), + .reset(reset), + .aw_ready(memory_aw_ready), + .aw_valid(memory_aw_valid), + .aw_bits_id(memory_aw_bits_id), + .aw_bits_addr(memory_aw_bits_addr), + .aw_bits_len(memory_aw_bits_len), + .aw_bits_size(memory_aw_bits_size), + .aw_bits_burst(memory_aw_bits_burst), + .w_ready(memory_w_ready), + .w_valid(memory_w_valid), + .w_bits_data(memory_w_bits_data), + .w_bits_strb(memory_w_bits_strb), + .w_bits_last(memory_w_bits_last), + .b_ready(memory_b_ready), + .b_valid(memory_b_valid), + .b_bits_id(memory_b_bits_id), + .b_bits_resp(memory_b_bits_resp), + .ar_ready(memory_ar_ready), + .ar_valid(memory_ar_valid), + .ar_bits_id(memory_ar_bits_id), + .ar_bits_addr(memory_ar_bits_addr), + .ar_bits_len(memory_ar_bits_len), + .ar_bits_size(memory_ar_bits_size), + .ar_bits_burst(memory_ar_bits_burst), + .r_ready(memory_r_ready), + .r_valid(memory_r_valid), + .r_bits_id(memory_r_bits_id), + .r_bits_data(memory_r_bits_data), + .r_bits_resp(memory_r_bits_resp), + .r_bits_last(memory_r_bits_last) + ); + axi_smoke_memory #(.DATA_BITS(64), .ID_BITS(2), .ADDR_BITS(31), .BASE(32'h60000000), .CAPACITY(4096), .MONITOR(1), .TEST_LABEL("whole Toy 64 OS WS RNE edge cases 4096 results")) peripherals_model ( + .clock(clock), + .reset(reset), + .aw_ready(peripherals_aw_ready), + .aw_valid(peripherals_aw_valid), + .aw_bits_id(peripherals_aw_bits_id), + .aw_bits_addr(peripherals_aw_bits_addr), + .aw_bits_len(peripherals_aw_bits_len), + .aw_bits_size(peripherals_aw_bits_size), + .aw_bits_burst(peripherals_aw_bits_burst), + .w_ready(peripherals_w_ready), + .w_valid(peripherals_w_valid), + .w_bits_data(peripherals_w_bits_data), + .w_bits_strb(peripherals_w_bits_strb), + .w_bits_last(peripherals_w_bits_last), + .b_ready(peripherals_b_ready), + .b_valid(peripherals_b_valid), + .b_bits_id(peripherals_b_bits_id), + .b_bits_resp(peripherals_b_bits_resp), + .ar_ready(peripherals_ar_ready), + .ar_valid(peripherals_ar_valid), + .ar_bits_id(peripherals_ar_bits_id), + .ar_bits_addr(peripherals_ar_bits_addr), + .ar_bits_len(peripherals_ar_bits_len), + .ar_bits_size(peripherals_ar_bits_size), + .ar_bits_burst(peripherals_ar_bits_burst), + .r_ready(peripherals_r_ready), + .r_valid(peripherals_r_valid), + .r_bits_id(peripherals_r_bits_id), + .r_bits_data(peripherals_r_bits_data), + .r_bits_resp(peripherals_r_bits_resp), + .r_bits_last(peripherals_r_bits_last) + ); + final $display("MEASURE cycles=%0d memory_reads=%0d memory_writes=%0d", cycle_count, memory_model.read_bursts, memory_model.write_bursts); +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/ws-shift-edges/simulation/verilator-build.log b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/ws-shift-edges/simulation/verilator-build.log new file mode 100644 index 0000000..060b997 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/tests/ws-shift-edges/simulation/verilator-build.log @@ -0,0 +1,2123 @@ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 31 | module NonSyncResetSynchronizerPrimitiveShiftReg_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ + ... For warning description see https://verilator.org/warn/TIMESCALEMOD?v=5.050 + ... Use "/* verilator lint_off TIMESCALEMOD */" and lint_on around source to disable this message. +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:48:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 48 | module SynchronizerShiftReg_w1_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:61:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 61 | module IntSyncAsyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:74:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 74 | module AsyncResetRegVec_w1_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 103 | module IntSyncCrossingSource_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:118:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 118 | module FixedClockBroadcast_3( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:139:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 139 | module TLMonitor( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:987:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 987 | module TLMonitor_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:2434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 2434 | module TLXbar_sbus_i2_o3_a32d128s3k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:3195:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3195 | module TLMonitor_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4151 | module Repeater_TLBundleA_a28d128s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4218 | module TLWidthWidget16( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4386 | module TLInterconnectCoupler_sbus_to_bus_named_cbus( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4478:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4478 | module ram_2x58( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4497:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4497 | module Queue2_AXI4BundleAW( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4581:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4581 | module ram_2x73( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4600:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4600 | module Queue2_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4657:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4657 | module ram_2x4( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4676:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4676 | module Queue2_AXI4BundleB( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4729:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4729 | module Queue2_AXI4BundleAR( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4813:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4813 | module ram_2x69( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4832:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4832 | module Queue2_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:4891:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4891 | module AXI4Buffer( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5067:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5067 | module ram_2x8( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5086:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5086 | module Queue2_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5143:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5143 | module Queue1_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5178 | module AXI4UserYanker( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5540:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5540 | module ram_8x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5559:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5559 | module Queue8_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:5631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5631 | module AXI4Deinterleaver( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:6073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6073 | module AXI4IdIndexer( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:6219:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6219 | module TLMonitor_3( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7048:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7048 | module Queue1_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7082:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7082 | module Queue1_AXI4BundleARW( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7148:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7148 | module TLToAXI4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:7529:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7529 | module TLMonitor_4( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8396:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8396 | module Repeater_TLBundleA_a31d128s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8463 | module TLWidthWidget16_2( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:8623:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8623 | module TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:9400:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 9400 | module SystemBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10050 | module FixedClockBroadcast_4( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10073 | module TLMonitor_5( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:10975:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10975 | module TLXbar_cbus_out_i1_o4_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:11288:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +11288 | module TLMonitor_6( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12202:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12202 | module ram_2x114( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12221 | module Queue2_TLBundleA_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12301 | module ram_2x79( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12320:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12320 | module Queue2_TLBundleD_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12399:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12399 | module TLBuffer_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:12534:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12534 | module TLMonitor_7( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:13449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13449 | module TLAtomicAutomata_cbus( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:13973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13973 | module TLMonitor_8( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14799 | module Queue1_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14846:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14846 | module TLError( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:14953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14953 | module TLMonitor_9( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15857 | module ram_2x100( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15876:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15876 | module Queue2_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:15955:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15955 | module Queue2_TLBundleD_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16028 | module TLBuffer_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16155 | module ErrorDeviceWrapper( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:16258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16258 | module TLMonitor_10( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17017:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17017 | module Repeater_TLBundleA_a26d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17081:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17081 | module TLFragmenter_CLINT( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17261:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17261 | module TLInterconnectCoupler_cbus_to_clint( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:17336:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17336 | module TLMonitor_11( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18106:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18106 | module Repeater_TLBundleA_a28d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18170:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18170 | module TLFragmenter_PLIC( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18350 | module TLInterconnectCoupler_cbus_to_plic( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:18425:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18425 | module TLMonitor_12( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19040 | module Repeater_TLBundleA_a17d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19104:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19104 | module TLFragmenter_bootrom( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19263:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19263 | module TLInterconnectCoupler_cbus_to_bootrom( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19330:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19330 | module PeripheryBus_cbus( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:19882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19882 | module TLMonitor_13( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20610:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20610 | module ProbePicker( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20688:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20688 | module ram_2x10( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20707:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20707 | module Queue2_BundleMap_6( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:20764:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20764 | module AXI4UserYanker_1( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:21713:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21713 | module AXI4IdIndexer_1( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:21859:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21859 | module TLMonitor_14( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22587:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22587 | module Queue1_AXI4BundleW_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22621 | module Queue1_AXI4BundleARW_1( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:22687:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22687 | module TLToAXI4_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:23555:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +23555 | module TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:24031:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24031 | module MemoryBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:24349:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24349 | module TLMonitor_15( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25732:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25732 | module BroadcastFilter( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25756:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25756 | module ram_4x144( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25775:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25775 | module Queue4_TLBroadcastData( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25828:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25828 | module TLBroadcastTracker( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:25964:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25964 | module TLBroadcastTracker_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:26100:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26100 | module TLBroadcast( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:26686:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26686 | module TLMonitor_16( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27414 | module BankBinder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27491:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27491 | module CoherenceManagerWrapper( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:27669:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27669 | module TLMonitor_17( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29229:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29229 | module TLMonitor_18( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29635:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29635 | module TLXbar_MasterXbar_BBTile_i2_o1_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29898 | module IntXbar_i4_o1( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:29918:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29918 | module WritebackUnit( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30014:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30014 | module ProbeUnit( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30154:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30154 | module Arbiter1_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30168:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30168 | module Arbiter1_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30191 | module Arbiter1_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30214 | module Arbiter1_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30249:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30249 | module Arbiter1_Bool( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30258 | module ram_16x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30277:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30277 | module Queue16_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30360:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30360 | module Queue1_TLBundleE_a32d128s1k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30388:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30388 | module MSHR( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30835:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30835 | module Arbiter1_HellaCacheResp( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:30879:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30879 | module IOMSHR( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31790:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31790 | module sdq_17x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:31809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31809 | module MSHRFile( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32350 | module OptimizationBarrier_TLBEntryData( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32406:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32406 | module PMPChecker_s3( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32691:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32691 | module PMAChecker( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:32731:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32731 | module DTLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:35923:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35923 | module L1MetadataArray( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:35990:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35990 | module Arbiter5_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36023:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36023 | module Arbiter2_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36055 | module DataArray( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36151 | module Arbiter4_L1DataReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36180:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36180 | module Arbiter2_L1DataWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36206:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36206 | module AMOALU( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36248:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36248 | module MaxPeriodFibonacciLFSR( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36342:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36342 | module Arbiter2_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:36377:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36377 | module NonBlockingDCache( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:37660:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37660 | module ICache( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:37914:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37914 | module ShiftQueue( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:38054:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38054 | module PMPChecker_s2( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:38215:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38215 | module ITLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:41129:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41129 | module Frontend( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:41494:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41494 | module TLMonitor_19( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:42301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +42301 | module TLMonitor_20( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43108:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43108 | module TLXbar_i2_o1_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43343 | module TLMonitor_21( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43851:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43851 | module ram_2x116( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43870:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43870 | module Queue2_TLBundleA_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43947:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43947 | module ram_2x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:43966:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43966 | module Queue2_TLBundleD_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44045:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44045 | module TLBuffer_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44158:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44158 | module TLMonitor_22( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44783 | module TLBuffer_a32d64s1k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:44892:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44892 | module TLMonitor_23( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:45699:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45699 | module Repeater_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:45766:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45766 | module TLWidthWidget8_4( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46074:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46074 | module TLMonitor_24( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46882 | module ram_2x117( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46901:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46901 | module Queue2_TLBundleA_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:46981:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46981 | module ram_2x78( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47000:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47000 | module Queue2_TLBundleD_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47079:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47079 | module TLBuffer_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47214 | module HellaCacheArbiter( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47381 | module Arbiter3_Valid_PTWReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47419:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47419 | module OptimizationBarrier_UInt( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47427 | module OptimizationBarrier_PTE( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:47459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47459 | module PTW( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:48434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +48434 | module FPUDecoder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49794:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49794 | module CompareRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49824:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49824 | module RecFNToIN_e11_s53_i64( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49873:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49873 | module RecFNToIN_e11_s53_i32( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:49912:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49912 | module FPToInt( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50375:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50375 | module RoundAnyRawFNToRecFN_ie7_is64_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50410:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50410 | module PipelinedINToRecFN( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50513:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50513 | module RoundAnyRawFNToRecFN_ie7_is64_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50539 | module PipelinedINToRecFN_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50614 | module RoundAnyRawFNToRecFN_ie7_is64_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50642:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50642 | module PipelinedINToRecFN_2( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:50717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50717 | module IntToFP( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51072:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51072 | module RoundAnyRawFNToRecFN_ie11_is53_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51199:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51199 | module RecFNToRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51221 | module RoundAnyRawFNToRecFN_ie11_is53_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51321:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51321 | module RecFNToRecFN_1( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51343 | module FPToFP( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51469:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51469 | module MulAddRecFNToRaw_preMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51569 | module MulAddRecFNToRaw_postMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51822:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51822 | module RoundAnyRawFNToRecFN_ie11_is55_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:51953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51953 | module RoundAnyRawFNToRecFN_ie11_is55_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52060:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52060 | module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52194:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52194 | module SharedMulAddRecFNPipe( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52551:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52551 | module FPUSharedFMAPipe( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52682:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52682 | module DivSqrtRawFN_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52852:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52852 | module DivSqrtRecFMToRaw_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:52907:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52907 | module RoundAnyRawFNToRecFN_ie5_is13_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53039:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53039 | module RoundRawFNToRecFN_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53068:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53068 | module DivSqrtRecFM_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53128:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53128 | module DivSqrtRawFN_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53297:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53297 | module DivSqrtRecFMToRaw_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53352:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53352 | module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53456:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53456 | module RoundRawFNToRecFN_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53485:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53485 | module DivSqrtRecFM_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53545:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53545 | module DivSqrtRawFN_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53715:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53715 | module DivSqrtRecFMToRaw_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53770:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53770 | module RoundRawFNToRecFN_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53799 | module DivSqrtRecFM_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53860:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53860 | module regfile_32x65( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:53905:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53905 | module FPU( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:54820:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +54820 | module RVCExpander( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:55183:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55183 | module IBuf( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:55307:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55307 | module CSRFile( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:57223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57223 | module RocketALU( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:57809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57809 | module MulDiv( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:58107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58107 | module Arbiter3_LLWB( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:58125:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58125 | module rf_31x64( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:58149:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58149 | module RocketBB( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62838:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62838 | module GlobalDecoder( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:62928:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62928 | module BankAliasTable( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:64252:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64252 | module BankScoreboard( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:64627:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64627 | module GlobalROB( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68674:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68674 | module Arbiter3_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68717 | module ram_16x4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68736:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68736 | module Queue16_UInt4( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:68782:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68782 | module SubROB( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:69357:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69357 | module Arbiter1_SubRobRow( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:69722:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69722 | module GlobalScheduler( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:70973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +70973 | module BootRom( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:71013:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71013 | module Frontend_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:71637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71637 | module PE( + | ^~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:71656:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71656 | module AlwaysOutTransposer( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72411:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72411 | module MacUnit( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72426:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72426 | module PE_64( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72524:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72524 | module Tile( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:72571:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72571 | module Mesh( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76050 | module TagQueue( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76191 | module ram_6x7( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76210:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76210 | module Queue6_TagWithIdAndTotalRows( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:76271:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76271 | module MeshWithDelays( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77318:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77318 | module ram_data_8x64( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77337 | module Queue8_SramReadResp( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:77385:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77385 | module GemminiExCtrl( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79354:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79354 | module LoopMatmulUnroller( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79637 | module LoopConvAddrGen( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:79690:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79690 | module LoopConvUnroller( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:80113:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80113 | module LoopCmdEncoder( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:80402:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80402 | module Arbiter2_LoopCmd( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:80598:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80598 | module GemminiBall( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:81783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81783 | module RRArbiter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:81857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81857 | module CmdRouter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:81985:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81985 | module BallCyclePMC( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:82095:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82095 | module BBus( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:82898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82898 | module BallDomainDecoder( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83028 | module ram_4x281( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83047:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83047 | module Queue4_BallReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83178 | module Arbiter1_BallRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83198:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83198 | module BallReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:83328:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83328 | module BallDomain( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84141:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84141 | module MemDomainDecoder( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84300:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84300 | module ram_4x158( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84319:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84319 | module Queue4_MemReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84421:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84421 | module Arbiter3_MemRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84463 | module MemReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84631 | module MemLoader( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:84869:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84869 | module MemStorer( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85122:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85122 | module MemCyclePMC( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85241:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85241 | module TLB( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85621 | module RRArbiter_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85649:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85649 | module BBTLBCluster( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:85777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85777 | module StreamReader( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86142:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86142 | module StreamWriter( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86223 | module ZeroLineGenerator( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86264:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86264 | module MemConfiger( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86433:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86433 | module RRArbiter_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86465:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86465 | module MemGroupQueryArbiter( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:86543:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86543 | module MemFrontend( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87160 | module MemMidend( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87621 | module SramBank( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87672:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87672 | module AccPipe( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:87781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87781 | module PrivateMemBackend( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:90777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +90777 | module MemBackend( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:91055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91055 | module MemDomain( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:91973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91973 | module Queue1_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92008:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92008 | module GpDomain( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92040 | module ram_8x21( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92059 | module Queue8_BuckyballAccelerator_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:92123:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92123 | module BuckyballAccelerator( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93569 | module Queue3_UInt2( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93614 | module SimpleHellaCacheIFReplayQueue( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93667:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93667 | module Arbiter2_HellaCacheReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93678:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93678 | module SimpleHellaCacheIF( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93768:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93768 | module BarrierUnit( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:93785:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93785 | module BBTile( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:95579:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +95579 | module TLMonitor_25( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:96427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +96427 | module TLMonitor_26( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98184:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98184 | module ram_2x189( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98203:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98203 | module Queue2_TLBundleA_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98283:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98283 | module ram_2x142( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98302:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98302 | module Queue2_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98381 | module Queue2_TLBundleA_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98459 | module Queue2_TLBundleD_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98539 | module ram_2x60( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98558:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98558 | module Queue2_TLBundleB_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98622:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98622 | module ram_2x173( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98641:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98641 | module Queue2_TLBundleC_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98716:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98716 | module ram_sink_2x1( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98735:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98735 | module Queue2_TLBundleE_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:98781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98781 | module TLBuffer_a32d128s2k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99162:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99162 | module IntSyncSyncCrossingSink_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99173:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99173 | module IntSyncSyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99181:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99181 | module TilePRCIDomain( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99589:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99589 | module BundleBridgeNexus_UInt1_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:99597:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99597 | module TLMonitor_27( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100216:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100216 | module CLINT( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100337 | module AsyncResetRegVec_w2_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100366:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100366 | module IntSyncCrossingSource_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100386 | module CLINTClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:100449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100449 | module TLMonitor_28( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101080:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101080 | module LevelGateway( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101099:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101099 | module PLICFanIn( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101111:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101111 | module Queue1_RegMapperInput_i23_m8( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101160 | module TLPLIC( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101389:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101389 | module PLICClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101452:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101452 | module TLMonitor_29( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:101973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101973 | module TLROM( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:102530:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102530 | module bootromClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:102569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102569 | module ToyLinuxSystem( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103817:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103817 | module ToyLinuxChip( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:103984:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103984 | module tag_array( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104007:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104007 | module array_0_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104034:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104034 | module array_0_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104059 | module array_2_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104084:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104084 | module array_2_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104109:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104109 | module bbtile_icache_tag_array( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104132:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104132 | module bbtile_icache_data_arrays_0( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104155 | module bbtile_icache_data_arrays_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104176:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104176 | module bbtile_icache_data_arrays_2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104197:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104197 | module bbtile_icache_data_arrays_3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104218 | module robOperands( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104243:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104243 | module sram( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104268:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104268 | module mem( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104301 | module plusarg_reader #( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104326:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104326 | module ITraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104404:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104404 | module FpgaDspMac(input [7:0] a, b, input [19:0] c, output [19:0] y); + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104414 | module PMCTraceDPI( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104464:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104464 | module MemPMCTraceDPI( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/ToyLinuxChip.sv:104514:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104514 | module MTraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:1:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 1 | module tag_array_ext( input [4:0] RW0_addr, + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 19 | module array_0_0_ext( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:37:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 37 | module bbtile_icache_tag_array_ext( input [5:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:55:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 55 | module bbtile_icache_data_arrays_0_ext( input [7:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:73:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 73 | module robOperands_ext( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:90:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 90 | module sram_ext( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/serial-bound/FpgaMemories.sv:107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 107 | module mem_ext( input [9:0] RW0_addr, + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:3:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3 | module axi_smoke_memory #( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/tb_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:52:20: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'addr' generates 31 bits. + : ... note: In instance 'tb.peripherals_model' + 52 | offset=(addr & ~(LANES-1))-BASE; + | ^ + ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=5.050 + ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:78:28: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'write_addr' generates 31 bits. + : ... note: In instance 'tb.peripherals_model' + 78 | offset=(write_addr & ~(LANES-1))-BASE; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:86:26: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'h600d600d' generates 64 bits. + : ... note: In instance 'tb.memory_model' + 86 | if (w_bits_data==64'h600d600d) begin + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:91:66: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff' generates 64 bits. + : ... note: In instance 'tb.memory_model' + 91 | $fatal(1,"CPU smoke failed at stage %0d",w_bits_data & 64'hffff); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:90:28: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff0000' generates 64 bits. + : ... note: In instance 'tb.memory_model' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/tests/axi_smoke_memory.sv:90:43: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'hbad00000' generates 64 bits. + : ... note: In instance 'tb.memory_model' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^~ +make: Entering directory '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/obj' +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_timing.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_timing.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_threads.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_threads.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb__pch.h -o Vtb__pch.h.fast.gch +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb__pch.h -o Vtb__pch.h.slow.gch +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb__ConstPool__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__1__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__2__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__3__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb__Syms__Slow.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__0.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__1.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__2.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__3.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__4.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__5.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__6.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__7.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__8.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__9.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb__main.cpp +g++ verilated.o verilated_timing.o verilated_threads.o Vtb__ALL.a -pthread -lpthread -latomic -o Vtb +rm Vtb__ALL.verilator_deplist.tmp +make: Leaving directory '/home/yys/codex-builds/toy-a7-rob-pr10-20261013-c0881ec8/platform/build/ws-shift-edges/simulation/obj' +- V e r i l a t i o n R e p o r t: Verilator 5.050 2026-07-01 rev v5.050 +- Verilator: Built from 15.468 MB sources in 346 modules, into 23.746 MB in 19 C++ files needing 0.019 MB +- Verilator: Walltime 14.167 s (elab=0.604, cvt=3.423, bld=9.465); cpu 4.984 s on 8 threads; allocated 561.754 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/toolchain.sh b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/toolchain.sh new file mode 100644 index 0000000..92d5f8a --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-13/rob-pr10-full/toolchain.sh @@ -0,0 +1,5 @@ +#!/usr/bin/env bash +# Pinned installed tools from the preceding accepted run. +export JAVA_HOME=/nix/store/2y0qz1r84ckgmmrnfvx9bbysnyn1zb61-openjdk-17.0.20+8 +export CHISEL_FIRTOOL_PATH=/home/yys/.cache/llvm-firtool/1.62.1/bin +export PATH="$JAVA_HOME/bin:/nix/store/ahvmb4byixykslwcxiay7c4ivhgpf8vg-sbt-1.8.2/bin:/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/bin:/nix/store/y8vkcyc8frd7ipcq0a6jix4xilgm93j7-riscv64-unknown-elf-gcc/bin:/nix/store/ywdz7hiyhb7hkp0vyzqfdx3fmrf1v8pa-yosys-0.67/bin:/home/yys/bin:$PATH" diff --git a/platforms/arty-a7-toy/host/flash.py b/platforms/arty-a7-toy/host/flash.py index 421e163..6c518ab 100644 --- a/platforms/arty-a7-toy/host/flash.py +++ b/platforms/arty-a7-toy/host/flash.py @@ -82,10 +82,14 @@ def main(): packed_record = json.loads( args.mcs.with_suffix(args.mcs.suffix + ".json").read_text() ) - assert packed_record["result"] == "PASS_VIVADO_FLASH_PACK" - assert packed_record["bitstream_sha256"] == sha(bit) - assert packed_record["packed_payload_sha256"] == sha(payload) - assert packed_record["flash_image_sha256"] == sha(args.mcs) + if packed_record["result"] != "PASS_VIVADO_FLASH_PACK": + raise ValueError("Prepacked flash image record did not pass packing") + if packed_record["bitstream_sha256"] != sha(bit): + raise ValueError("Prepacked flash image bitstream hash mismatch") + if packed_record["packed_payload_sha256"] != sha(payload): + raise ValueError("Prepacked flash image payload hash mismatch") + if packed_record["flash_image_sha256"] != sha(args.mcs): + raise ValueError("Prepacked flash image MCS hash mismatch") shutil.copy2(args.mcs.resolve(), image) commands[0] = None record = dict( diff --git a/platforms/arty-a7-toy/host/requirements-hardware.txt b/platforms/arty-a7-toy/host/requirements-hardware.txt new file mode 100644 index 0000000..d0dfd58 --- /dev/null +++ b/platforms/arty-a7-toy/host/requirements-hardware.txt @@ -0,0 +1 @@ +pyserial==3.5 diff --git a/platforms/arty-a7-toy/patches/framework/GlobalROB.scala b/platforms/arty-a7-toy/patches/framework/GlobalROB.scala new file mode 100644 index 0000000..2cd7e8d --- /dev/null +++ b/platforms/arty-a7-toy/patches/framework/GlobalROB.scala @@ -0,0 +1,603 @@ +package framework.frontend.globalrs + +import chisel3._ +import chisel3.util._ +import chisel3.experimental._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import framework.top.GlobalConfig +import framework.frontend.decoder.{DomainId, PostGDCmd} +import framework.frontend.scoreboard.{BankAccessInfo, BankAliasTable, BankScoreboard} +import framework.memdomain.frontend.cmd.decoder.DISA.MSET_BITPAT +import framework.memdomain.backend.shared.SharedMemLayout +import framework.memdomain.backend.banks.btrace.{BTraceDPI, PhysicalBankHash} + +@instantiable +class GlobalROB(val b: GlobalConfig, useOperandRam: Boolean = GlobalROB.operandRamEnabled) extends Module { + + val robDepth = b.frontend.rob_entries + val idWidth = log2Up(robDepth) + val scoreBankNum = b.memDomain.virtualBankCount + robDepth + val sharedHashCount = if (b.memDomain.sharedEnable) SharedMemLayout.totalBank(b) else 0 + val physicalBankCount = b.memDomain.bankNum + sharedHashCount + + require( + b.frontend.vbank_id_upper_bound < b.memDomain.virtualBankCount, + s"vbank_id_upper_bound(${b.frontend.vbank_id_upper_bound}) must be < virtualBankCount(${b.memDomain.virtualBankCount})" + ) + + @public + val io = IO(new Bundle { + val hart_id = Input(UInt(b.tile.xLen.W)) + val alloc = Flipped(new DecoupledIO(new PostGDCmd(b))) + val issue = new DecoupledIO(new GlobalRobEntry(b)) + val complete = Flipped(new DecoupledIO(UInt(idWidth.W))) + + val empty = Output(Bool()) + val full = Output(Bool()) + val head_ptr = Output(UInt(idWidth.W)) + val issued_count = Output(UInt(log2Up(robDepth + 1).W)) + val entry_valid = Output(Vec(robDepth, Bool())) + val entry_complete = Output(Vec(robDepth, Bool())) + + val subRobActive = Input(Bool()) + val inst_ids = Output(Vec(robDepth, UInt(64.W))) + + val bank_hashes = + if (b.sim.diffTest) { + Some(Input(Vec(physicalBankCount, new PhysicalBankHash(b)))) + } else { + None + } + + }) + + // --------------------------------------------------------------------------- + // BAT + Bank Scoreboard + // --------------------------------------------------------------------------- + val bat: Instance[BankAliasTable] = Instantiate( + new BankAliasTable( + bankIdLen = b.frontend.bank_id_len, + vbankUpper = b.memDomain.virtualBankCount - 1, + robEntries = robDepth + ) + ) + + val scoreboard: Instance[BankScoreboard] = + Instantiate(new BankScoreboard(b.frontend.bank_id_len, scoreBankNum, robDepth)) + + // --------------------------------------------------------------------------- + // Instruction trace (DPI-C, defined in ITraceDPI.scala) + // --------------------------------------------------------------------------- + val itraceAlloc = Module(new ITraceDPI) + val itraceIssue = Module(new ITraceDPI) + val itraceComp = Module(new ITraceDPI) + + for (t <- Seq(itraceAlloc, itraceIssue, itraceComp)) { + t.io.clock := clock + t.io.reset := reset.asBool + t.io.is_issue := 0.U + t.io.hart_id := io.hart_id + t.io.rob_id := 0.U + t.io.inst_id := 0.U + t.io.domain_id := 0.U + t.io.funct := 0.U + t.io.pc := 0.U + t.io.rs1_data := 0.U + t.io.rs2_data := 0.U + t.io.enable := false.B + } + + // --------------------------------------------------------------------------- + // Storage + // --------------------------------------------------------------------------- + val robEntries = RegInit(VecInit(Seq.fill(robDepth)(0.U.asTypeOf(new GlobalRobEntry(b))))) + // Only the issued payload needs the full operands. Keep existing copies for + // trace/commit observation; Vivado removes trace-only bits with DPI disabled. + // MSET's low rs2 bits stay in registers for the parallel commit scan. + private val operandWidth = b.tile.xLen + private val operandRam = if (useOperandRam) { + Some(SyncReadMem(robDepth, UInt((2 * operandWidth).W)).suggestName("robOperands")) + } else None + val robValid = RegInit(VecInit(Seq.fill(robDepth)(false.B))) + val robIssued = RegInit(VecInit(Seq.fill(robDepth)(false.B))) + val robComplete = RegInit(VecInit(Seq.fill(robDepth)(false.B))) + val instIds = RegInit(VecInit(Seq.fill(robDepth)(0.U(64.W)))) + val nextInstId = RegInit(1.U(64.W)) + + val statusHashes = + if (b.sim.diffTest) { + Some(RegInit(VecInit(Seq.fill(robDepth)(VecInit(Seq.fill(3)(0.U(32.W))))))) + } else { + None + } + + io.inst_ids := instIds + + val headPtr = RegInit(0.U(idWidth.W)) + val tailPtr = RegInit(0.U(idWidth.W)) + val issuedCount = RegInit(0.U(log2Up(robDepth + 1).W)) + private val bankColWidth = b.memDomain.groupCountWidth + val bankCols = RegInit(VecInit(Seq.fill(b.memDomain.virtualBankCount)(0.U(bankColWidth.W)))) + // In-flight ownership is tracked in the architectural vbank namespace. + private val vbankMaskWidth = b.memDomain.virtualBankCount + val vbankBusy = RegInit(0.U(vbankMaskWidth.W)) + + // Dependency state is maintained incrementally instead of rebuilding all + // older-entry comparisons every cycle. A bit in slot k names the ROB slot + // that currently blocks k. Ordinary RAW dependencies disappear at complete; + // dependencies involving a mapping/config instruction disappear at commit. + // Keeping one union mask is sufficient because a config dependency is never + // allowed to clear earlier than commit, even when it also looks like a RAW. + val dependencyMask = RegInit(VecInit(Seq.fill(robDepth)(0.U(robDepth.W)))) + + val isEmpty = headPtr === tailPtr && !robValid(headPtr) + val isFull = headPtr === tailPtr && robValid(headPtr) + + def nextPtr(p: UInt): UInt = Mux(p === (robDepth - 1).U, 0.U, p + 1.U) + def wrapPtr(v: UInt): UInt = Mux(v >= robDepth.U, v - robDepth.U, v) + def robIdx(v: UInt): UInt = v(idWidth - 1, 0) + + def isMappingConfig(entry: GlobalRobEntry): Bool = + entry.cmd.domain_id === DomainId.MEM && + (entry.cmd.cmd.funct === MSET_BITPAT) + + def accessUsesBank(access: BankAccessInfo, bank: UInt): Bool = + (access.rd_bank_0_valid && access.rd_bank_0_id === bank) || + (access.rd_bank_1_valid && access.rd_bank_1_id === bank) || + (access.wr_bank_valid && access.wr_bank_id === bank) + + // Build one architectural-vbank mask per ROB slot once, then hazard checks + // become mask intersections instead of repeating ID comparisons. + private val hazardBankCount = b.memDomain.virtualBankCount + + def rawReadMask(access: BankAccessInfo): UInt = { + val rd0 = Mux( + access.rd_bank_0_valid && access.rd_bank_0_id < hazardBankCount.U, + UIntToOH(access.rd_bank_0_id, hazardBankCount), + 0.U(hazardBankCount.W) + ) + val rd1 = Mux( + access.rd_bank_1_valid && access.rd_bank_1_id < hazardBankCount.U, + UIntToOH(access.rd_bank_1_id, hazardBankCount), + 0.U(hazardBankCount.W) + ) + rd0 | rd1 + } + + def rawWriteMask(access: BankAccessInfo): UInt = Mux( + access.wr_bank_valid && access.wr_bank_id < hazardBankCount.U, + UIntToOH(access.wr_bank_id, hazardBankCount), + 0.U(hazardBankCount.W) + ) + + def rawUseMask(access: BankAccessInfo): UInt = + rawReadMask(access) | rawWriteMask(access) + + // --------------------------------------------------------------------------- + // Allocate: enqueue decoded instruction into ROB + // rob_id == tailPtr at allocation time (no separate counter needed) + // --------------------------------------------------------------------------- + val commitMask = Wire(Vec(robDepth, Bool())) + for (i <- 0 until robDepth) { + commitMask(i) := false.B + } + bat.io.free.valid := commitMask.asUInt.orR + bat.io.free.mask := commitMask + + val commitScan = Wire(Vec(robDepth, Bool())) + val commitKeep = Wire(Vec(robDepth + 1, Bool())) + commitKeep(0) := true.B + for (i <- 0 until robDepth) { + val ptr = robIdx(wrapPtr(headPtr + i.U)) + commitScan(i) := commitKeep(i) && robValid(ptr) && robComplete(ptr) + commitKeep(i + 1) := (if (b.sim.diffTest) false.B else commitScan(i)) + } + val hasCommit = commitScan.asUInt.orR + val tailAlias = Wire(UInt(b.frontend.bank_id_len.W)) + tailAlias := + b.memDomain.virtualBankCount.U(b.frontend.bank_id_len.W) + tailPtr + + val tailAliasLive = WireDefault(false.B) + for (i <- 0 until robDepth) { + when(robValid(i) && !robComplete(i) && accessUsesBank(robEntries(i).renamedBankAccess, tailAlias)) { + tailAliasLive := true.B + } + } + + io.alloc.ready := !isFull && !hasCommit && !tailAliasLive + bat.io.alloc.valid := io.alloc.fire + bat.io.alloc.rob_id := tailPtr + bat.io.alloc.raw := io.alloc.bits.bankAccess + + // Mark write alias as busy in scoreboard at alloc time (not issue time). + scoreboard.alloc.valid := io.alloc.fire && io.alloc.bits.bankAccess.wr_bank_valid + scoreboard.alloc.bits := bat.io.alloc_renamed + + // Bank masks are shared by allocation and issue. This avoids rebuilding the + // UIntToOH decoders once for every older-entry comparison at allocation. + val entryRawReads = Wire(Vec(robDepth, UInt(hazardBankCount.W))) + val entryRawWrites = Wire(Vec(robDepth, UInt(hazardBankCount.W))) + val entryIsConfig = Wire(Vec(robDepth, Bool())) + for (slot <- 0 until robDepth) { + entryRawReads(slot) := rawReadMask(robEntries(slot).cmd.bankAccess) + entryRawWrites(slot) := rawWriteMask(robEntries(slot).cmd.bankAccess) + entryIsConfig(slot) := isMappingConfig(robEntries(slot)) + } + + // A newly allocated entry is always younger than all currently valid ROB + // entries (tailPtr points at the first free slot). Capture its older-entry + // dependencies once here; issue no longer repeats pairwise comparisons. + val allocReadMask = rawReadMask(io.alloc.bits.bankAccess) + val allocWriteMask = rawWriteMask(io.alloc.bits.bankAccess) + val allocIsConfig = io.alloc.bits.domain_id === DomainId.MEM && + (io.alloc.bits.cmd.funct === MSET_BITPAT) + val allocIsBall = io.alloc.bits.domain_id === DomainId.BALL + val allocDependencyBits = Wire(Vec(robDepth, Bool())) + for (older <- 0 until robDepth) { + val olderUseMask = entryRawReads(older) | entryRawWrites(older) + val rawConflict = ((allocReadMask & entryRawWrites(older)) | + (allocWriteMask & olderUseMask)).orR + val configConflict = (allocIsConfig && entryIsConfig(older)) || + ((allocIsConfig || entryIsConfig(older)) && ((allocReadMask | allocWriteMask) & olderUseMask).orR) + val sameBall = allocIsBall && + robEntries(older).cmd.domain_id === DomainId.BALL && + robEntries(older).cmd.ball_bid === io.alloc.bits.ball_bid + // Config conflicts include entries that have completed but are waiting to + // commit. RAW conflicts and same-Ball commands release at completion. + allocDependencyBits(older) := + (robValid(older) && !robComplete(older) && (rawConflict || sameBall)) || + (robValid(older) && configConflict) + } + val allocDependencies = allocDependencyBits.asUInt + val allocUsesInstId = io.alloc.bits.cmd.pc =/= 0.U + + when(io.alloc.fire) { + operandRam.foreach(_.write(tailPtr, Cat(io.alloc.bits.cmd.rs1Data, io.alloc.bits.cmd.rs2Data))) + itraceAlloc.io.is_issue := 2.U + itraceAlloc.io.rob_id := tailPtr + itraceAlloc.io.inst_id := Mux(allocUsesInstId, nextInstId, 0.U) + itraceAlloc.io.domain_id := io.alloc.bits.domain_id + itraceAlloc.io.funct := io.alloc.bits.cmd.funct + itraceAlloc.io.pc := io.alloc.bits.cmd.pc + itraceAlloc.io.rs1_data := io.alloc.bits.cmd.rs1Data + itraceAlloc.io.rs2_data := io.alloc.bits.cmd.rs2Data + itraceAlloc.io.enable := true.B + + robEntries(tailPtr).cmd := io.alloc.bits + robEntries(tailPtr).renamedBankAccess := bat.io.alloc_renamed + robEntries(tailPtr).rob_id := tailPtr + instIds(tailPtr) := Mux(allocUsesInstId, nextInstId, 0.U) + robValid(tailPtr) := true.B + robIssued(tailPtr) := false.B + robComplete(tailPtr) := false.B + statusHashes.foreach { hashes => + for (slot <- 0 until 3) { + hashes(tailPtr)(slot) := 0.U + } + } + tailPtr := nextPtr(tailPtr) + when(allocUsesInstId) { + nextInstId := nextInstId + 1.U + } + } + + // --------------------------------------------------------------------------- + // Complete: mark entry as completed, release scoreboard resources + // --------------------------------------------------------------------------- + if (b.sim.diffTest) { + val collecting = RegInit(false.B) + val collectCid = Reg(UInt(idWidth.W)) + val collectSlot = Reg(UInt(2.W)) + val collectGroup = Reg(UInt(32.W)) + val currentHash = Reg(UInt(32.W)) + val hashReady = RegInit(false.B) + val hashCid = Reg(UInt(idWidth.W)) + + val incomingAccess = robEntries(io.complete.bits).cmd.bankAccess + val incomingNeedsHash = instIds(io.complete.bits) =/= 0.U && !isMappingConfig(robEntries(io.complete.bits)) && + (incomingAccess.rd_bank_0_valid || incomingAccess.rd_bank_1_valid || incomingAccess.wr_bank_valid) + io.complete.ready := !incomingNeedsHash || (hashReady && hashCid === io.complete.bits) + + when(!collecting && !hashReady && io.complete.valid && incomingNeedsHash) { + collecting := true.B + collectCid := io.complete.bits + collectSlot := Mux(incomingAccess.rd_bank_0_valid, 0.U, Mux(incomingAccess.rd_bank_1_valid, 1.U, 2.U)) + collectGroup := 0.U + currentHash := 0.U + } + + val access = robEntries(collectCid).cmd.bankAccess + val vbank = MuxLookup(collectSlot, access.wr_bank_id)(Seq( + 0.U -> access.rd_bank_0_id, + 1.U -> access.rd_bank_1_id, + 2.U -> access.wr_bank_id + )) + val hasNextSlot = MuxLookup(collectSlot, false.B)(Seq( + 0.U -> (access.rd_bank_1_valid || access.wr_bank_valid), + 1.U -> access.wr_bank_valid + )) + val nextSlot = Mux(collectSlot === 0.U && access.rd_bank_1_valid, 1.U, 2.U) + val matches = VecInit(io.bank_hashes.get.map { state => + state.valid && state.hartId === io.hart_id && state.vbankId === vbank && state.groupId === collectGroup + }) + val nextMatches = VecInit(io.bank_hashes.get.map { state => + state.valid && state.hartId === io.hart_id && state.vbankId === vbank && state.groupId === collectGroup + 1.U + }) + val physical = Mux1H(matches, io.bank_hashes.get) + def rotateLeft(value: UInt, amount: Int): UInt = Cat(value(31 - amount, 0), value(31, 32 - amount)) + + val mixed = physical.statusHash ^ rotateLeft(physical.groupId, 7) ^ "h9e3779b9".U + val nextHash = rotateLeft(currentHash, 5) ^ mixed ^ rotateLeft(mixed, 13) + + when(collecting) { + assert(PopCount(matches) === 1.U, "BTrace requires exactly one physical bank per vbank group") + when(nextMatches.asUInt.orR) { + currentHash := nextHash + collectGroup := collectGroup + 1.U + }.otherwise { + statusHashes.get(collectCid)(collectSlot) := nextHash + when(hasNextSlot) { + collectSlot := nextSlot + collectGroup := 0.U + currentHash := 0.U + }.otherwise { + collecting := false.B + hashReady := true.B + hashCid := collectCid + } + } + } + + when(io.complete.fire) { + hashReady := false.B + } + } else { + io.complete.ready := true.B + } + + scoreboard.complete.valid := false.B + scoreboard.complete.bits := 0.U.asTypeOf(scoreboard.complete.bits) + + val issueFired = WireDefault(false.B) + val completeIssuedEntry = io.complete.fire && robIssued(io.complete.bits) + + when(io.complete.fire) { + val cid = io.complete.bits + robComplete(cid) := true.B + scoreboard.complete.valid := true.B + scoreboard.complete.bits := robEntries(cid).renamedBankAccess + + itraceComp.io.is_issue := 0.U + itraceComp.io.rob_id := cid + itraceComp.io.inst_id := instIds(cid) + itraceComp.io.domain_id := robEntries(cid).cmd.domain_id + itraceComp.io.funct := robEntries(cid).cmd.cmd.funct + itraceComp.io.pc := robEntries(cid).cmd.cmd.pc + itraceComp.io.rs1_data := robEntries(cid).cmd.cmd.rs1Data + itraceComp.io.rs2_data := robEntries(cid).cmd.cmd.rs2Data + itraceComp.io.enable := true.B + } + + val completedBitMask = Mux( + io.complete.fire, + UIntToOH(io.complete.bits, robDepth), + 0.U(robDepth.W) + ) + + // --------------------------------------------------------------------------- + // Issue: scan from head for first issuable entry (valid && !issued && !complete) + // --------------------------------------------------------------------------- + val scanValid = Wire(Vec(robDepth, Bool())) + val scanReady = Wire(Vec(robDepth, Bool())) + val vbankMasks = Wire(Vec(robDepth, UInt(vbankMaskWidth.W))) + for (slot <- 0 until robDepth) { + // Reuse the raw hazard mask for active-command ownership. + vbankMasks(slot) := entryRawReads(slot) | entryRawWrites(slot) + } + + // Check each candidate against older ROB entries using mask intersections. + // The masks are precomputed once per slot, so this retains the original + // age-sensitive RAW/WAR/WAW semantics without replicating three equality + // comparators for every bank access pair. + for (i <- 0 until robDepth) { + val ptr = robIdx(wrapPtr(headPtr + i.U)) + scanValid(i) := robValid(ptr) && !robIssued(ptr) && !robComplete(ptr) + scoreboard.queryVec(i) := robEntries(ptr).renamedBankAccess + scanReady(i) := scanValid(i) && !scoreboard.hazardVec(i) && + !dependencyMask(ptr).orR && + !(vbankMasks(ptr) & vbankBusy).orR + } + + val hasReady = scanReady.asUInt.orR + val firstReady = PriorityEncoder(scanReady.asUInt) + val actualIssuePtr = robIdx(wrapPtr(headPtr + firstReady)) + + scoreboard.query := robEntries(actualIssuePtr).renamedBankAccess + val canIssue = hasReady + + val issueStageValid = RegInit(false.B) + val issueStageEntry = Reg(new GlobalRobEntry(b)) + val issueStageFire = issueStageValid && !io.subRobActive && io.issue.ready + val issueStageReady = !issueStageValid || issueStageFire + + // Keep the wide ROB entry and bank-column mux one register boundary away + // from the age/scoreboard scan. The pointer stage can accept one candidate + // per cycle; the payload stage drains at one per cycle, so steady-state II + // remains one while the extra latency is hidden by in-flight commands. + val issuePtrValid = RegInit(false.B) + val issuePtr = Reg(UInt(idWidth.W)) + val issuePtrFire = issuePtrValid && issueStageReady + val issuePtrReady = !issuePtrValid || issuePtrFire + val issueLoad = canIssue && !io.subRobActive && issuePtrReady + val issuePayload = Wire(new GlobalRobEntry(b)) + issuePayload := robEntries(issuePtr) + operandRam.foreach { memory => + // Read at pointer selection, then re-read while that pointer is stalled. + // Replacement selects the new pointer; the current response is consumed + // before the next edge. This preserves the existing two-stage issue timing. + val readAddress = Mux(issueLoad, actualIssuePtr, issuePtr) + val readEnable = issueLoad || issuePtrValid + val operands = memory.read(readAddress, readEnable) + issuePayload.cmd.cmd.rs1Data := operands(2 * operandWidth - 1, operandWidth) + issuePayload.cmd.cmd.rs2Data := operands(operandWidth - 1, 0) + when(io.alloc.fire && readEnable) { + assert(tailPtr =/= readAddress, "ROB operand RAM read/write collision") + } + } + issuePayload.cmd.op1_col := Mux( + issuePayload.cmd.bankAccess.rd_bank_0_valid, + bankCols(issuePayload.cmd.bankAccess.rd_bank_0_id(b.memDomain.vbankIdWidth - 1, 0)), + 0.U + ) + issuePayload.cmd.op2_col := Mux( + issuePayload.cmd.bankAccess.rd_bank_1_valid, + bankCols(issuePayload.cmd.bankAccess.rd_bank_1_id(b.memDomain.vbankIdWidth - 1, 0)), + 0.U + ) + issuePayload.cmd.wr_col := Mux( + issuePayload.cmd.bankAccess.wr_bank_valid, + bankCols(issuePayload.cmd.bankAccess.wr_bank_id(b.memDomain.vbankIdWidth - 1, 0)), + 0.U + ) + + io.issue.valid := issueStageValid && !io.subRobActive + io.issue.bits := issueStageEntry + + when(issuePtrReady) { + issuePtrValid := issueLoad + when(issueLoad) { + issuePtr := actualIssuePtr + } + } + when(issueStageReady) { + issueStageValid := issuePtrValid + when(issuePtrFire) { + issueStageEntry := issuePayload + } + } + + scoreboard.issue.valid := false.B + scoreboard.issue.bits := 0.U.asTypeOf(scoreboard.issue.bits) + + when(issueLoad) { + robIssued(actualIssuePtr) := true.B + issueFired := true.B + scoreboard.issue.valid := true.B + scoreboard.issue.bits := robEntries(actualIssuePtr).renamedBankAccess + + itraceIssue.io.is_issue := 1.U + itraceIssue.io.rob_id := robEntries(actualIssuePtr).rob_id + itraceIssue.io.inst_id := instIds(actualIssuePtr) + itraceIssue.io.domain_id := robEntries(actualIssuePtr).cmd.domain_id + itraceIssue.io.funct := robEntries(actualIssuePtr).cmd.cmd.funct + itraceIssue.io.pc := robEntries(actualIssuePtr).cmd.cmd.pc + itraceIssue.io.rs1_data := robEntries(actualIssuePtr).cmd.cmd.rs1Data + itraceIssue.io.rs2_data := robEntries(actualIssuePtr).cmd.cmd.rs2Data + itraceIssue.io.enable := true.B + } + + // Preserve the original update ordering when issue and complete coincide: + // a completion clears ownership after the newly issued transaction marks + // its banks busy. + val issuedVbankMask = Mux(issueLoad, vbankMasks(actualIssuePtr), 0.U) + val completedVbankMask = Mux(io.complete.fire, vbankMasks(io.complete.bits), 0.U) + when(issueLoad || io.complete.fire) { + vbankBusy := + (vbankBusy & ~completedVbankMask) | issuedVbankMask + } + + issuedCount := issuedCount + issueFired.asUInt - completeIssuedEntry.asUInt + + // --------------------------------------------------------------------------- + // Commit: clear completed entries. + // Explicitly skip entries being allocated or completed this cycle. + // --------------------------------------------------------------------------- + for (i <- 0 until robDepth) { + val hits = (0 until robDepth).map { off => + val ptr = robIdx(wrapPtr(headPtr + off.U)) + commitScan(off) && ptr === i.U + } + commitMask(i) := hits.reduce(_ || _) + when(commitMask(i)) { + when(robEntries(i).cmd.domain_id === DomainId.MEM && robEntries(i).cmd.cmd.funct === MSET_BITPAT) { + val bankId = robEntries(i).cmd.bankAccess.wr_bank_id + val bank = bankId(b.memDomain.vbankIdWidth - 1, 0) + val col = robEntries(i).cmd.cmd.rs2Data(9, 5) + when(robEntries(i).cmd.cmd.rs2Data(10)) { + val fullCol = + if (b.memDomain.sharedEnable) { + Mux( + bankId >= b.frontend.shared_bank_id_base.U && bankId < b.memDomain.virtualBankCount.U, + SharedMemLayout.totalBank(b).U(bankColWidth.W), + b.memDomain.bankNum.U(bankColWidth.W) + ) + } else { + b.memDomain.bankNum.U(bankColWidth.W) + } + bankCols(bank) := Mux(col === 0.U, fullCol, col) + }.otherwise { + bankCols(bank) := 0.U + } + } + robValid(i) := false.B + robIssued(i) := false.B + robComplete(i) := false.B + } + } + + if (b.sim.diffTest) { + val commitIndex = PriorityEncoder(commitMask.asUInt) + val commitAccess = robEntries(commitIndex).cmd.bankAccess + val invalidVbank = "hffffffff".U(32.W) + val btrace = Module(new BTraceDPI) + btrace.io.clock := clock + btrace.io.reset := reset.asBool + btrace.io.instId := instIds(commitIndex) + btrace.io.hartId := io.hart_id + btrace.io.r0Vbank := Mux(commitAccess.rd_bank_0_valid, commitAccess.rd_bank_0_id, invalidVbank) + btrace.io.r0Hash := Mux(commitAccess.rd_bank_0_valid, statusHashes.get(commitIndex)(0), 0.U) + btrace.io.r1Vbank := Mux(commitAccess.rd_bank_1_valid, commitAccess.rd_bank_1_id, invalidVbank) + btrace.io.r1Hash := Mux(commitAccess.rd_bank_1_valid, statusHashes.get(commitIndex)(1), 0.U) + btrace.io.w0Vbank := Mux(commitAccess.wr_bank_valid, commitAccess.wr_bank_id, invalidVbank) + btrace.io.w0Hash := Mux(commitAccess.wr_bank_valid, statusHashes.get(commitIndex)(2), 0.U) + btrace.io.fire := hasCommit && instIds(commitIndex) =/= 0.U && !isMappingConfig(robEntries(commitIndex)) && + (commitAccess.rd_bank_0_valid || commitAccess.rd_bank_1_valid || commitAccess.wr_bank_valid) + } + + // Maintain dependency masks at the same architectural events that gate the + // issue scan. A dependency involving a config entry (on either side) clears + // only at commit; all other dependencies clear at complete. This is the + // union-mask form of the former separate RAW/config masks. + val configEntryMask = entryIsConfig.asUInt + for (slot <- 0 until robDepth) { + val isAllocatedSlot = io.alloc.fire && tailPtr === slot.U + val slotIsConfig = Mux(isAllocatedSlot, allocIsConfig, entryIsConfig(slot)) + // Each dependency bit names the older entry that blocks this slot. Keep a + // config-related edge through completion when either endpoint is config. + val configRelated = configEntryMask | Fill(robDepth, slotIsConfig) + val clearMask = commitMask.asUInt | (completedBitMask & ~configRelated) + when(isAllocatedSlot) { + dependencyMask(slot) := allocDependencies & ~clearMask + }.otherwise { + dependencyMask(slot) := dependencyMask(slot) & ~clearMask + } + } + + val commitCount = PopCount(commitScan) + headPtr := wrapPtr(headPtr + commitCount) + + // --------------------------------------------------------------------------- + // Status outputs + // --------------------------------------------------------------------------- + io.empty := isEmpty + io.full := isFull + io.head_ptr := headPtr + io.issued_count := issuedCount + io.entry_valid := robValid + io.entry_complete := robComplete + +} + +object GlobalROB { + def operandRamEnabled: Boolean = java.lang.Boolean.getBoolean("fpga.robOperandRam") +} diff --git a/platforms/arty-a7-toy/run_hardware.ps1 b/platforms/arty-a7-toy/run_hardware.ps1 new file mode 100644 index 0000000..763582a --- /dev/null +++ b/platforms/arty-a7-toy/run_hardware.ps1 @@ -0,0 +1,17 @@ +# Prepare the pinned UART release and reuse the Linux/Gemmini verifier. +param( + [string]$Port, + [string]$Vivado, + [string]$Python = 'python', + [string]$BundleZip, + [switch]$PrepareOnly +) +$ErrorActionPreference = 'Stop' +$entry = Join-Path $PSScriptRoot 'scripts/run_hardware.py' +$entryArgs = @('-X', 'utf8', $entry) +if ($PrepareOnly) { $entryArgs += '--prepare-only' } +if ($Port) { $entryArgs += @('--port', $Port) } +if ($Vivado) { $entryArgs += @('--vivado', $Vivado) } +if ($BundleZip) { $entryArgs += @('--bundle-zip', $BundleZip) } +& $Python @entryArgs +if ($LASTEXITCODE -ne 0) { throw "Hardware verification failed (exit code $LASTEXITCODE); see the error and RUN.json above." } diff --git a/platforms/arty-a7-toy/scripts/check_board.py b/platforms/arty-a7-toy/scripts/check_board.py index 5f711c2..1d064ba 100644 --- a/platforms/arty-a7-toy/scripts/check_board.py +++ b/platforms/arty-a7-toy/scripts/check_board.py @@ -3,6 +3,7 @@ import json from pathlib import Path import subprocess +from offline_check import run_check ROOT=Path(__file__).resolve().parents[1] OUT=ROOT/"build/board-unit" @@ -22,9 +23,17 @@ def run(name, files, marker): def main(): + fixture=json.loads((ROOT/"tests/PLATFORM_PORTS_MANIFEST.json").read_text()) + if hashlib.sha256((ROOT/"tests/ToyLinuxChipPorts.sv").read_bytes()).hexdigest()!=fixture["stub_sha256"]: + raise ValueError("CPU port fixture differs from its manifest") OUT.mkdir(parents=True,exist_ok=True) run("tb_axi_fullwidth",[ROOT/"board/axi_fullwidth.sv",ROOT/"tests/axi_smoke_memory.sv",ROOT/"tests/tb_axi_fullwidth.sv"],"PASS fullwidth AXI") run("tb_axi_scu",[ROOT/"board/axi_scu.sv",ROOT/"tests/tb_axi_scu.sv"],"PASS SCU") + platform_files=[ROOT/"board"/name for name in + ("toy_a7_platform.sv","axi_fullwidth.sv","axi_scu.sv","ddr_uart_loader.sv", + "loader_axi.sv","uart_rx.sv","uart_tx.sv","flash_spi_byte.sv")] + run("tb_platform_bresp",platform_files+[ROOT/"tests/ToyLinuxChipPorts.sv",ROOT/"tests/tb_platform_bresp.sv"], + "PASS platform AXI B response") # Retain the CRC/range/timeout/rejected RUN oracle from the earlier loader, # but connect its new acknowledgement boundary to AXI, not zero-latency RAM. template=(ROOT/"tests/board_loader_template.sv").read_text() @@ -38,7 +47,8 @@ def main(): (OUT/"tb_ddr_loader.sv").write_text(template) run("tb_ddr_loader",[ROOT/"board/ddr_uart_loader.sv",ROOT/"board/loader_axi.sv",ROOT/"tests/axi_smoke_memory.sv",OUT/"tb_ddr_loader.sv"],"PASS: DDR UART loader") files=[p for p in (ROOT/"board").glob("*.sv")]+[ROOT/"tests/tb_axi_fullwidth.sv",ROOT/"tests/tb_axi_scu.sv"] - record=dict(result="PASS",tests=3,physical_mig_simulated=False, + files += [ROOT/"tests/ToyLinuxChipPorts.sv",ROOT/"tests/tb_platform_bresp.sv"] + record=dict(result="PASS",tests=4,physical_mig_simulated=False, sources={str(p.relative_to(ROOT)):hashlib.sha256(p.read_bytes()).hexdigest() for p in files}) (OUT/"RESULT.json").write_text(json.dumps(record,indent=2)+"\n") @@ -64,4 +74,4 @@ def main(): if __name__=="__main__": - main() + run_check(main, OUT) diff --git a/platforms/arty-a7-toy/scripts/check_board_mmio_error.py b/platforms/arty-a7-toy/scripts/check_board_mmio_error.py new file mode 100644 index 0000000..c354ba1 --- /dev/null +++ b/platforms/arty-a7-toy/scripts/check_board_mmio_error.py @@ -0,0 +1,81 @@ +"""真实 CPU→SCU 错误响应回归；记录异常行为，不把总线错误等同于同步 trap。""" + +import argparse +import hashlib +import json +from pathlib import Path +import subprocess +import re +from offline_check import run_check + +ROOT = Path(__file__).resolve().parents[1] +OUT = ROOT / "build/board-mmio-error" + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--platform-file", type=Path, default=ROOT / "board/toy_a7_platform.sv") + args = parser.parse_args() + elf = OUT / "fault.elf" + subprocess.run(["riscv64-unknown-elf-gcc", "-nostdlib", "-nostartfiles", "-mcmodel=medany", + "-march=rv64imafdc_zicsr_zifencei", "-mabi=lp64d", "-Wl,--no-relax", + "-T", str(ROOT / "tests/cpu_smoke.ld"), str(ROOT / "tests/mmio_error.S"), "-o", str(elf)], check=True) + binary = OUT / "fault.bin" + subprocess.run(["riscv64-unknown-elf-objcopy", "-O", "binary", str(elf), str(binary)], check=True) + (OUT / "fault.hex").write_text("\n".join(f"{value:02x}" for value in binary.read_bytes()) + "\n") + bench = (ROOT / "build/board-cpu/tb_board_cpu.sv").read_text().replace("tb_board_cpu", "tb_mmio_error") + bench = bench.replace('"smoke.hex"', '"fault.hex"') + bench = bench.replace('$display("PASS CPU', 'if(bad_b!=1 || bad_r!=1) $fatal(1,"Fault did not traverse AXI/SCU");\n $display("PASS MMIO_ERROR CPU') + bench = bench.replace("PASS MMIO_ERROR CPU Sv39/FPU/AMO/cache/interrupt through board AXI/SCU", + "PASS MMIO_ERROR CPU AXI/SCU response delivery") + monitors = ''' + reg bad_write=0,bad_read=0; + integer bad_b=0,bad_r=0; + integer traps=-1; + always @(posedge clk) if(!reset) begin + if(exited && exit_code[31:16]==16'h7400 && traps<0) begin + traps=exit_code[15:0];$display("MMIO_SYNCHRONOUS_TRAPS %0d",traps); + end + if(platform.peripherals_aw_valid && platform.peripherals_aw_ready) + bad_write<=platform.peripherals_aw_bits_addr==31'h60030000; + if(platform.peripherals_ar_valid && platform.peripherals_ar_ready) + bad_read<=platform.peripherals_ar_bits_addr==31'h60030000; + if(platform.peripherals_b_valid && platform.peripherals_b_ready && bad_write) begin + if(platform.chip.peripherals_b_bits_resp!==2'b10) $fatal(1,"CPU did not receive SLVERR"); + bad_b<=bad_b+1;bad_write<=0; + end + if(platform.peripherals_r_valid && platform.peripherals_r_ready && bad_read) begin + if(platform.chip.peripherals_r_bits_resp!==2'b10) $fatal(1,"CPU did not receive read error"); + bad_r<=bad_r+1;bad_read<=0; + end + end +''' + bench = bench.replace("endmodule", monitors + "\nendmodule") + path = OUT / "tb_mmio_error.sv" + path.write_text(bench) + sources = [ROOT / "build/serial-bound/ToyLinuxChip.sv", ROOT / "build/serial-bound/FpgaMemories.sv", + ROOT / "tests/axi_smoke_memory.sv", path] + sources += [args.platform_file if p.name=="toy_a7_platform.sv" else p + for p in (ROOT / "board").glob("*.sv") if p.name != "toy_a7_top.sv"] + with (OUT / "compile.log").open("w") as log: + subprocess.run(["verilator", "--binary", "--timing", "-j", "4", "-Wno-fatal", "-DSYNTHESIS", + "-DBUCKYBALL_DISABLE_DPI", "--top-module", "tb_mmio_error", "--Mdir", str(OUT / "obj")] + + [str(p) for p in sources], stdout=log, stderr=log, check=True, timeout=900) + result = subprocess.run([str(OUT / "obj/Vtb_mmio_error")], cwd=OUT, capture_output=True, text=True, timeout=180) + (OUT / "simulation.log").write_text(result.stdout + result.stderr) + result.check_returncode() + if "PASS MMIO_ERROR CPU" not in result.stdout: + raise ValueError("Missing CPU fault oracle") + matches = re.findall(r"MMIO_SYNCHRONOUS_TRAPS (\d+)", result.stdout) + if len(matches) != 1: + raise ValueError("Missing synchronous-trap observation") + record = {"result": "PASS_CPU_MMIO_SLVERR", "physical_hardware_tested": False, + "synchronous_traps_observed": int(matches[0]), "synchronous_trap_guaranteed": False, + "invalid_address": "0x60030000", "required_read_write_response": "10", + "binary_sha256": hashlib.sha256(binary.read_bytes()).hexdigest()} + (OUT / "RESULT.json").write_text(json.dumps(record, indent=2) + "\n") + print(result.stdout) + + +if __name__ == "__main__": + run_check(main, OUT) diff --git a/platforms/arty-a7-toy/scripts/check_core_units.py b/platforms/arty-a7-toy/scripts/check_core_units.py new file mode 100644 index 0000000..cb08165 --- /dev/null +++ b/platforms/arty-a7-toy/scripts/check_core_units.py @@ -0,0 +1,73 @@ +"""重新生成并验证 PE、FMA、移位、RF、查询与 SubROB 单元；不连接硬件。""" + +import hashlib +import json +from pathlib import Path +import re +import subprocess +import sys +from offline_check import run_check + +ROOT = Path(__file__).resolve().parents[1] +OUT = ROOT / "build/core-unit-regressions" + + +def execute(name, command, marker=None, cwd=ROOT, timeout=900): + result = subprocess.run(command, cwd=cwd, capture_output=True, text=True, timeout=timeout) + (OUT / (name + ".log")).write_text(result.stdout + result.stderr) + result.check_returncode() + if marker and marker not in result.stdout: + raise ValueError(f"Missing passing marker: {name}") + return result.stdout + + +def unpack(path): + pieces = re.split(r'// ----- 8< ----- FILE "([^"]+)" ----- 8< -----', path.read_text()) + modules = [pieces[0]] + for name, body in zip(pieces[1::2], pieces[2::2]): + if name.endswith((".sv", ".v")): + modules.append(body) + elif name != "firrtl_black_box_resource_files.f": + raise ValueError("Unexpected emitted resource: " + name) + output = OUT / (path.stem + ".sv") + output.write_text("\n".join(modules)) + return output + + +def main(): + emitters = ["EmitPeChecks", "EmitFmaChecks", "EmitRoundShiftChecks", "EmitGroupQueryCheck", "EmitSubRobCheck"] + execute("elaboration", ["sbt", "-batch"] + ["runMain fpga.arty.linux." + name for name in emitters]) + records = {} + for label, raw, bench, marker in [ + ("round", "round-check/RoundShiftChecks.sv", "tb_round_shift.sv", "PASS ROUND_SHIFT"), + ("group", "group-query-check/GroupQueryCheck.sv", "tb_group_query.sv", "PASS: 256 concurrent group queries"), + ("subrob", "subrob-check/SubRobCheck.sv", "tb_subrob.sv", "PASS SUBROB")]: + rtl = unpack(ROOT / "build" / raw) + obj = OUT / (label + "-obj") + execute(label + "-compile", ["verilator", "--binary", "--timing", "--assert", "-j", "4", + "-Wno-fatal", "-DBUCKYBALL_DISABLE_DPI", "--top-module", "tb", "--Mdir", str(obj), + str(rtl), str(ROOT / "tests" / bench)]) + execute(label, [str(obj / "Vtb")], marker, timeout=120) + records[label] = "PASS" + fma = unpack(ROOT / "build/fma-check/FmaPrecisionCheck.sv") + obj = OUT / "fma-obj" + execute("fma-compile", ["verilator", "--cc", "--exe", "--build", "-j", "4", "-Wno-fatal", + "--top-module", "FmaPrecisionCheck", "--Mdir", str(obj), str(fma), + str(ROOT / "tests/fma_differential.cpp")]) + execute("fma", [str(obj / "VFmaPrecisionCheck")], "PASS FMA_SHARED", ROOT / "build/fma-check", 120) + records["fma"] = "PASS" + rf = OUT / "fpu-rf.vvp" + execute("rf-compile", ["iverilog", "-g2012", "-s", "tb", "-o", str(rf), + str(ROOT / "rtl/FpuRfOriginal.sv"), str(ROOT / "rtl/FpuRfLvt.sv"), str(ROOT / "tests/tb_fpu_rf.sv")]) + execute("rf", ["vvp", str(rf)], "PASS FPU_RF_LVT", timeout=120) + records["rf"] = "PASS" + execute("pe", [sys.executable, str(ROOT / "tests/check_pe.py")], "PASS original/LUT/DSP PE") + records["pe"] = "PASS" + record = {"result": "PASS_UNIT_REGRESSIONS", "physical_hardware_tested": False, "tests": records, + "generated_rtl": {path.name: hashlib.sha256(path.read_bytes()).hexdigest() for path in OUT.glob("*.sv")}} + (OUT / "RESULT.json").write_text(json.dumps(record, indent=2) + "\n") + print("PASS core units: PE/formal quantizer, FMA, round shift, FPU RF, group query and SubROB") + + +if __name__ == "__main__": + run_check(main, OUT) diff --git a/platforms/arty-a7-toy/scripts/check_flash_guards.py b/platforms/arty-a7-toy/scripts/check_flash_guards.py new file mode 100644 index 0000000..ce63561 --- /dev/null +++ b/platforms/arty-a7-toy/scripts/check_flash_guards.py @@ -0,0 +1,48 @@ +"""验证普通模式与 python -O 下四项预打包镜像校验均有效。""" + +import hashlib +import json +from pathlib import Path +import subprocess +import sys +import tempfile +from offline_check import run_check + +ROOT = Path(__file__).resolve().parents[1] + + +def main(): + out = ROOT / "build/flash-guard-check" + out.mkdir(parents=True, exist_ok=True) + cases = [] + for optimized in [False, True]: + for field in [None, "result", "bitstream_sha256", "packed_payload_sha256", "flash_image_sha256"]: + with tempfile.TemporaryDirectory(dir=out) as directory: + work = Path(directory) + bit, payload, mcs = [work / name for name in ["chip.bit", "payload.bin", "image.mcs"]] + for path in [bit, payload, mcs]: + path.write_bytes(path.name.encode()) + sha = lambda path: hashlib.sha256(path.read_bytes()).hexdigest() + record = {"result": "PASS_VIVADO_FLASH_PACK", "bitstream_sha256": sha(bit), + "packed_payload_sha256": sha(payload), "flash_image_sha256": sha(mcs)} + if field: + record[field] = "FAILED" if field == "result" else "0" * 64 + mcs.with_suffix(".mcs.json").write_text(json.dumps(record)) + expected = "reject" if field else "accept" + command = [sys.executable] + (["-O"] if optimized else []) + command += [str(ROOT / "tests/flash_guard_probe.py"), str(ROOT / "host/flash.py"), + str(bit), str(payload), str(mcs), str(work / "run"), expected] + result = subprocess.run(command, capture_output=True, text=True, timeout=20) + name = f"{'optimized' if optimized else 'normal'}-{field or 'valid'}" + (out / f"{name}.log").write_text(result.stdout + result.stderr, encoding="utf-8") + result.check_returncode() + if ("PASS INVALID_IMAGE_BLOCKED" if field else "PASS VALID_IMAGE_REACHED_OFFLINE_BOUNDARY") not in result.stdout: + raise ValueError("Missing guard oracle") + cases.append({"optimized": optimized, "field": field or "valid", "result": "PASS"}) + (out / "RESULT.json").write_text(json.dumps({"result": "PASS_FLASH_GUARDS_NORMAL_AND_OPTIMIZED", + "physical_hardware_tested": False, "cases": cases}, indent=2) + "\n") + print(f"PASS Flash image guards: {len(cases)} normal/-O tamper/control cases; no hardware") + + +if __name__ == "__main__": + run_check(main, ROOT / "build/flash-guard-check") diff --git a/platforms/arty-a7-toy/scripts/check_globalrob.py b/platforms/arty-a7-toy/scripts/check_globalrob.py new file mode 100644 index 0000000..d563932 --- /dev/null +++ b/platforms/arty-a7-toy/scripts/check_globalrob.py @@ -0,0 +1,64 @@ +"""核验同步 RAM 与原寄存器路径逐周期等价，包括背压、绕回和中途复位。""" + +import argparse +import hashlib +import json +from pathlib import Path +import re +import subprocess + +ROOT = Path(__file__).resolve().parents[1] + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--skip-elaboration", action="store_true") + args = parser.parse_args() + out = ROOT / "build/globalrob-check" + out.mkdir(parents=True, exist_ok=True) + commands = [] + if not args.skip_elaboration: + commands.append((["sbt", "-batch", "runMain fpga.arty.linux.EmitGlobalRobCheck"], + "elaboration.log", 900)) + for command, name, timeout in commands: + with (out / name).open("w") as log: + subprocess.run(command, cwd=ROOT, stdout=log, stderr=subprocess.STDOUT, + timeout=timeout, check=True) + # CIRCT appends named inline resources and the .f index to one emission. + # Keep the untouched emission, compile only Verilog sections. + parts = re.split(r'// ----- 8< ----- FILE "([^"]+)" ----- 8< -----', + (out / "GlobalRobCheck.sv").read_text()) + modules = [parts[0]] + for name, body in zip(parts[1::2], parts[2::2]): + if name.endswith((".sv", ".v")): + modules.append(body) + elif name == "firrtl_black_box_resource_files.f": + if not all(line.strip().endswith(".v") for line in body.splitlines() if line.strip()): + raise ValueError("Unexpected inline resource index") + else: + raise ValueError("Unexpected emitted resource: " + name) + rtl = out / "GlobalRobCheck.sim.sv" + rtl.write_text("\n".join(modules)) + commands = [(["verilator", "--binary", "--timing", "--assert", "-j", "4", "-Wno-fatal", + "-DBUCKYBALL_DISABLE_DPI", "--top-module", "tb", "--Mdir", str(out / "obj"), + str(rtl), str(ROOT / "tests/tb_globalrob.sv")], + "compile.log", 600), + ([str(out / "obj/Vtb")], "simulation.log", 60)] + for command, name, timeout in commands: + with (out / name).open("w") as log: + subprocess.run(command, cwd=ROOT, stdout=log, stderr=subprocess.STDOUT, + timeout=timeout, check=True) + transcript = (out / "simulation.log").read_text() + if "PASS GLOBALROB RAM/register cycle comparison" not in transcript: + raise ValueError("GlobalROB passing marker missing") + record = {"result": "PASS", "cycle_equivalence": True, + "coverage": ["accepted operand integrity", "ROB full", "pointer wrap", + "issue backpressure", "SubROB ownership stall", "mid-flight resets", + "concurrent allocation/issue/completion", "complete drain"], + "rtl_sha256": hashlib.sha256((out / "GlobalRobCheck.sv").read_bytes()).hexdigest()} + (out / "RESULT.json").write_text(json.dumps(record, indent=2) + "\n") + print(transcript) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/scripts/check_platform_mutations.py b/platforms/arty-a7-toy/scripts/check_platform_mutations.py new file mode 100644 index 0000000..203194c --- /dev/null +++ b/platforms/arty-a7-toy/scripts/check_platform_mutations.py @@ -0,0 +1,56 @@ +"""只在 build 中注入 RTL 错误，核验 AXI 用例的检错能力；不改生产源码。""" + +import hashlib +import json +from pathlib import Path +import subprocess +from offline_check import run_check + +ROOT = Path(__file__).resolve().parents[1] +OUT = ROOT / "build/backpressure-mutation" +OLD = ROOT / "evidence/2026-10-12/pr10-review" + + +def main(): + original = (ROOT / "board/axi_scu.sv").read_text() + condition = "if(bvalid && bready) bvalid<=0;" + if original.count(condition) != 1: + raise ValueError("SCU mutation target changed; review this oracle") + mutant = OUT / "scu-mutant.sv" + mutant.write_text(original.replace(condition, "if(bvalid) bvalid<=0;")) + common = [ROOT / "board" / name for name in + ["axi_fullwidth.sv", "ddr_uart_loader.sv", "loader_axi.sv", + "uart_rx.sv", "uart_tx.sv", "flash_spi_byte.sv"]] + common += [ROOT / "tests/ToyLinuxChipPorts.sv"] + cases = [] + inputs = [("old-test", ROOT / "board/toy_a7_platform.sv", mutant, + OLD / "sources/tests/tb_platform_bresp.sv", 0), + ("new-test", ROOT / "board/toy_a7_platform.sv", mutant, + ROOT / "tests/tb_platform_bresp.sv", 1), + ("old-response", OLD / "old-platform.sv", ROOT / "board/axi_scu.sv", + ROOT / "tests/tb_platform_bresp.sv", 1)] + for label, platform, scu, bench, expected in inputs: + executable = OUT / label + sources = [platform, scu, bench] + common + compiled = subprocess.run(["iverilog", "-g2012", "-s", "tb_platform_bresp", "-o", + str(executable)] + [str(path) for path in sources], + capture_output=True, text=True, timeout=60) + (OUT / (label + "-compile.log")).write_text(compiled.stdout + compiled.stderr) + compiled.check_returncode() + result = subprocess.run(["vvp", str(executable)], capture_output=True, text=True, timeout=60) + log = result.stdout + result.stderr + (OUT / (label + ".log")).write_text(log) + marker = {"old-test": "PASS platform AXI B response", "new-test": "valid=0", + "old-response": "actual=01 expected=10"}[label] + if result.returncode != expected or marker not in log: + raise ValueError(f"Mutation oracle failed: {label}: {log}") + cases.append({"case": label, "exit_code": result.returncode, "expected_exit_code": expected, + "result": "PASS", "sources": {path.relative_to(ROOT).as_posix(): + hashlib.sha256(path.read_bytes()).hexdigest() for path in sources}}) + record = {"result": "PASS_MUTATION_ORACLES", "physical_hardware_tested": False, "cases": cases} + (OUT / "RESULT.json").write_text(json.dumps(record, indent=2) + "\n") + print("PASS mutation oracles: old test misses premature BVALID drop; new test rejects it and old response bug") + + +if __name__ == "__main__": + run_check(main, OUT) diff --git a/platforms/arty-a7-toy/scripts/check_programming_scripts.py b/platforms/arty-a7-toy/scripts/check_programming_scripts.py new file mode 100644 index 0000000..9e248c0 --- /dev/null +++ b/platforms/arty-a7-toy/scripts/check_programming_scripts.py @@ -0,0 +1,57 @@ +"""离线注入 Vivado API 返回值、异常与配置状态，检查实际 Tcl 入口。""" + +import argparse +import json +from pathlib import Path +import shutil +import subprocess +import tempfile +from offline_check import run_check + +ROOT = Path(__file__).resolve().parents[1] + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--tclsh", default=shutil.which("tclsh")) + args = parser.parse_args() + if not args.tclsh: + raise RuntimeError("Install Tcl or supply --tclsh") + out = ROOT / "build/programming-check" + out.mkdir(parents=True, exist_ok=True) + cases = [] + for script in ["program_arty.tcl", "backup_flash.tcl", "program_flash.tcl"]: + faults = ["none", "device_error", "done_low", "eos_low", "crc_error"] + if script != "program_arty.tcl": + faults += ["readback_error", "short_backup"] + if script == "program_flash.tcl": + faults += ["cfgmem_error"] + for fault in faults: + with tempfile.TemporaryDirectory(dir=out) as directory: + work = Path(directory) + bit = work / "input.bit" + bit.write_bytes(b"offline fixture") + command = [args.tclsh, str(ROOT / "tests/mock_programming.tcl"), + str(ROOT / "board" / script), fault, str(bit), str(work / "backup.bin")] + result = subprocess.run(command, capture_output=True, text=True, timeout=20) + transcript = result.stdout + result.stderr + (out / f"{script}-{fault}.log").write_text(transcript, encoding="utf-8") + if fault == "none": + if result.returncode or "MOCK_SUCCESS" not in transcript: + raise ValueError(f"Documented success return rejected: {script}: {transcript}") + else: + if result.returncode == 0 or "MOCK_FAILURE" not in transcript: + raise ValueError(f"Injected failure accepted: {script}/{fault}") + if "PASS FLASH_PROGRAM_VERIFY" in transcript or "ARTY_JTAG_PROGRAMMED:" in transcript: + raise ValueError("False success marker") + if fault != "cfgmem_error" and "program_flash" in transcript.split("MOCK_EVENTS", 1)[1].splitlines()[0]: + raise ValueError("Flash programming reached after an earlier failure") + cases.append({"script": script, "fault": fault, "result": "PASS"}) + record = {"result": "PASS_OFFLINE_TCL_CONTRACTS", "physical_hardware_tested": False, + "cases": cases} + (out / "RESULT.json").write_text(json.dumps(record, indent=2) + "\n") + print(f"PASS programming scripts: {len(cases)} documented-return/status/error cases; no hardware") + + +if __name__ == "__main__": + run_check(main, ROOT / "build/programming-check") diff --git a/platforms/arty-a7-toy/scripts/check_runner_status.py b/platforms/arty-a7-toy/scripts/check_runner_status.py new file mode 100644 index 0000000..14846cb --- /dev/null +++ b/platforms/arty-a7-toy/scripts/check_runner_status.py @@ -0,0 +1,71 @@ +"""注入检查失败，验证三种实际入口不会遗留上次 PASS；不连接硬件。""" + +import argparse +import hashlib +import json +from pathlib import Path +import shutil +import subprocess +import sys +import tempfile +from offline_check import run_check + +ROOT = Path(__file__).resolve().parents[1] +OUT = ROOT / "build/runner-status-check" + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--baseline-ref", help="仅用旧源码反测，预期复现遗留 PASS") + args = parser.parse_args() + OUT.mkdir(parents=True, exist_ok=True) + cases = [] + runners = [("check_board.py", "board-unit", "PASS"), + ("check_programming_scripts.py", "programming-check", "PASS_OFFLINE_TCL_CONTRACTS"), + ("check_flash_guards.py", "flash-guard-check", "PASS_FLASH_GUARDS_NORMAL_AND_OPTIMIZED")] + for script, directory, old_pass in runners: + source = ROOT / "scripts" / script + data = source.read_bytes() if not args.baseline_ref else subprocess.check_output( + ["git", "show", f"{args.baseline_ref}:platforms/arty-a7-toy/scripts/{script}"], cwd=ROOT) + with tempfile.TemporaryDirectory(dir=OUT) as temporary: + work = Path(temporary) + (work / "scripts").mkdir() + (work / "tests").mkdir() + (work / "scripts" / script).write_bytes(data) + helper = ROOT / "scripts/offline_check.py" + if helper.exists(): + shutil.copy2(helper, work / "scripts/offline_check.py") + result_file = work / "build" / directory / "RESULT.json" + result_file.parent.mkdir(parents=True) + result_file.write_text(json.dumps({"result": old_pass})) + if script == "check_board.py": + (work / "tests/PLATFORM_PORTS_MANIFEST.json").write_text(json.dumps({"stub_sha256": "0" * 64})) + (work / "tests/ToyLinuxChipPorts.sv").write_text("// injected fixture mismatch\n") + extra = [] + elif script == "check_programming_scripts.py": + # A child fails before any hardware operation; Python is the injected interpreter. + (work / "tests/mock_programming.tcl").write_text("raise RuntimeError('INJECTED_CHECK_FAILURE')\n") + extra = ["--tclsh", sys.executable] + else: + (work / "tests/flash_guard_probe.py").write_text("raise RuntimeError('INJECTED_CHECK_FAILURE')\n") + extra = [] + process = subprocess.run([sys.executable, str(work / "scripts" / script)] + extra, + capture_output=True, text=True, timeout=30) + status = json.loads(result_file.read_text()) + log = process.stdout + process.stderr + "\nOBSERVED_RESULT " + json.dumps(status) + "\n" + (OUT / (script + ".log")).write_text(log, encoding="utf-8") + if process.returncode == 0: + raise ValueError("Failure injection did not reach the actual runner") + expected = old_pass if args.baseline_ref else "FAILED" + if status["result"] != expected: + raise ValueError(f"{script}: expected {expected}, got {status}") + cases.append({"script": script, "source_sha256": hashlib.sha256(data).hexdigest(), + "exit_code": process.returncode, "observed_result": status["result"], "result": "PASS"}) + record = {"result": "PASS_EXPECTED_STALE_BASELINE" if args.baseline_ref else "PASS_RUNNER_FAILURE_STATUS", + "baseline_ref": args.baseline_ref, "physical_hardware_tested": False, "cases": cases} + (OUT / "RESULT.json").write_text(json.dumps(record, indent=2) + "\n") + print(f"PASS runner failure status: {len(cases)} actual entrypoints; baseline={args.baseline_ref or 'current'}") + + +if __name__ == "__main__": + run_check(main, OUT) diff --git a/platforms/arty-a7-toy/scripts/elaborate_rob_candidate.sh b/platforms/arty-a7-toy/scripts/elaborate_rob_candidate.sh new file mode 100644 index 0000000..f89674c --- /dev/null +++ b/platforms/arty-a7-toy/scripts/elaborate_rob_candidate.sh @@ -0,0 +1,13 @@ +#!/usr/bin/env bash +set -euo pipefail +cd "$(dirname "$0")/.." +python3 scripts/prepare_sources.py "$@" +python3 scripts/resolve_config.py +python3 scripts/check_globalrob.py +sbt -Dfpga.robOperandRam=true -batch \ + 'runMain fpga.arty.linux.EmitToyLinux build/serial-raw --fpga-memories --serial-fpga' \ + 'runMain fpga.arty.linux.EmitToyLinux build/serial-reference --serial-fpga' \ + 'runMain fpga.arty.linux.EmitRoutingCheck build/routing-check' +python3 scripts/prepare_rob_candidate.py \ + --baseline-memory-manifest evidence/2026-10-11/MEMORY_MANIFEST.json +python3 scripts/export_capabilities.py diff --git a/platforms/arty-a7-toy/scripts/offline_check.py b/platforms/arty-a7-toy/scripts/offline_check.py new file mode 100644 index 0000000..2b02125 --- /dev/null +++ b/platforms/arty-a7-toy/scripts/offline_check.py @@ -0,0 +1,23 @@ +"""离线检查启动时撤销旧 PASS，失败时保存本轮状态。""" + +import json +from pathlib import Path + + +def run_check(main, directory): + directory = Path(directory) + directory.mkdir(parents=True, exist_ok=True) + result = directory / "RESULT.json" + + def publish(record): + temporary = result.with_suffix(".tmp") + temporary.write_text(json.dumps(record, indent=2) + "\n", encoding="utf-8") + temporary.replace(result) + + publish({"result": "RUNNING", "physical_hardware_tested": False}) + try: + main() + except (Exception, KeyboardInterrupt) as error: + publish({"result": "FAILED", "physical_hardware_tested": False, + "error_type": type(error).__name__, "error": str(error)}) + raise diff --git a/platforms/arty-a7-toy/scripts/package_rob_release.py b/platforms/arty-a7-toy/scripts/package_rob_release.py new file mode 100644 index 0000000..f53322f --- /dev/null +++ b/platforms/arty-a7-toy/scripts/package_rob_release.py @@ -0,0 +1,135 @@ +"""只打包已通过完整实现/RTL 核验的 ROB/PR10 UART 工程预发布，不访问板卡。""" + +import argparse +import hashlib +import json +from pathlib import Path +import shutil +import subprocess +import zipfile + +ROOT = Path(__file__).resolve().parents[1] + + +def digest(path): + result = hashlib.sha256() + with path.open("rb") as source: + while block := source.read(1024 * 1024): + result.update(block) + return result.hexdigest() + + +def require(value, message): + if not value: + raise ValueError(message) + + +def copy(source, root, name): + destination = root / name + destination.parent.mkdir(parents=True, exist_ok=True) + shutil.copy2(source, destination) + + +def bind(root, kind, commit): + record = {"flow": kind, "source_commit": commit, "target": "xc7a100tcsg324-1", + "engineering_prerelease": True, "physical_hardware_tested_this_release": False, + "files": {p.relative_to(root).as_posix(): {"sha256": digest(p), "bytes": p.stat().st_size} + for p in sorted(root.rglob("*")) if p.is_file()}} + (root / "MANIFEST.json").write_text(json.dumps(record, indent=2, ensure_ascii=False) + "\n", encoding="utf-8") + + +def compress(root, output): + with zipfile.ZipFile(output, "w", compression=zipfile.ZIP_DEFLATED, compresslevel=6) as archive: + for path in sorted(root.rglob("*")): + if path.is_file(): + method = zipfile.ZIP_STORED if path.name.endswith(".tar.gz") else zipfile.ZIP_DEFLATED + archive.write(path, path.relative_to(root).as_posix(), compress_type=method) + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + for name in ["bitstream", "payload", "core-dir", "validation", "os-inputs", "output"]: + parser.add_argument("--" + name, type=Path, required=True) + parser.add_argument("--baseline-core", type=Path, required=True) + args = parser.parse_args() + record = json.loads(args.validation.read_text()) + require(record["result"] == "PASS_ROB_PR10_FULL_VALIDATION", "完整验证尚未通过") + require(not record["physical_hardware_tested"], "此入口只发布尚未实板测试的工程预发布") + require(record["timing"]["wns_ns"] >= 0 and record["timing"]["whs_ns"] >= 0, "时序未通过") + require(record["route_errors"] == record["critical_drc"] == record["critical_cdc"] == 0, "实现存在严重错误") + for name, expected in [(args.bitstream, record["bitstream_sha256"]), (args.payload, record["payload_sha256"]), + (args.core_dir / "ToyLinuxChip.sv", record["core_rtl_sha256"]), + (args.core_dir / "FpgaMemories.sv", record["memory_rtl_sha256"])]: + require(digest(name) == expected, "验证输入摘要不匹配：" + name.name) + for name, expected in record["board_sources"].items(): + require(digest(ROOT / name) == expected, "板级源码已变：" + name) + software = json.loads((ROOT / "evidence/2026-10-12/linux-gemmini/build/LINUX_GEMMINI_BUILD.json").read_text()) + require(software["payload_sha256"] == record["payload_sha256"] and + args.payload.stat().st_size == software["payload_bytes"], "软件镜像未匹配标准构建记录") + inputs = json.loads((args.os_inputs / "INPUTS.json").read_text()) + for name, item in inputs.items(): + require(digest(args.os_inputs / name) == item["sha256"] and + (args.os_inputs / name).stat().st_size == item["bytes"], "软件输入档案已变：" + name) + for name, expected in record["fpu_baseline_rtl"].items(): + require(digest(args.baseline_core / name) == expected, "FPU 基线输入已变：" + name) + repo = Path(subprocess.check_output(["git", "rev-parse", "--show-toplevel"], cwd=ROOT, text=True).strip()) + require(not subprocess.check_output(["git", "status", "--porcelain"], cwd=repo), "先提交全部公开文件，再打包") + commit = subprocess.check_output(["git", "rev-parse", "HEAD"], cwd=repo, text=True).strip() + out = args.output.resolve() + out.mkdir(parents=True, exist_ok=False) + uart, sources = out / "uart", out / "sources" + uart.mkdir(); sources.mkdir() + copy(args.bitstream, uart, "toy_a7_uart.bit") + copy(args.payload, uart, "fw_payload.bin") + copy(args.validation, uart, "VALIDATION_RESULT.json") + copy(ROOT / "evidence/2026-10-12/linux-gemmini/build/LINUX_GEMMINI_BUILD.json", uart, "LINUX_GEMMINI_BUILD.json") + for name in ["README.md", "run_uart.ps1", "verify_bundle.py"]: + copy(ROOT / "distribution-rob" / name, uart, name) + copy(repo / "LICENSE", uart, "LICENSE") + copy(ROOT / "program.tcl", uart, "program.tcl") + for path in (ROOT / "host").glob("*.py"): + copy(path, uart, path.relative_to(ROOT)) + for path in (ROOT / "board").rglob("*"): + if path.is_file() and (path.suffix in [".sv", ".tcl", ".xdc", ".xml", ".prj"] or "vendor" in path.parts): + copy(path, uart, path.relative_to(ROOT)) + for name in ["ToyLinuxChip.sv", "FpgaMemories.sv", "MEMORY_MANIFEST.json"]: + copy(args.core_dir / name, uart, "build/serial-bound/" + name) + shutil.copytree(args.os_inputs / "notices", uart / "notices") + (uart / "requirements.txt").write_text("pyserial==3.5\n") + bind(uart, "ROB_PR10_UART", commit) + tracked = subprocess.check_output(["git", "ls-files", "--stage", "-z"], cwd=repo).decode().split("\0") + submodules = {} + for entry in tracked: + if entry: + metadata, name = entry.split("\t", 1) + mode, object_id, _ = metadata.split() + if mode == "160000": + submodules[name] = object_id + else: + copy(repo / name, sources, "repository/" + name) + (sources / "SUBMODULES.json").write_text(json.dumps(submodules, indent=2) + "\n") + copy(args.validation, sources, "VALIDATION_RESULT.json") + shutil.copytree(args.os_inputs / "build", sources / "software-inputs/build") + copy(args.os_inputs / "INPUTS.json", sources, "software-inputs/INPUTS.json") + shutil.copytree(args.os_inputs / "notices", sources / "notices") + for name in ["ToyLinuxChip.sv", "FpgaMemories.sv", "MEMORY_MANIFEST.json"]: + copy(args.core_dir / name, sources, "generated/" + name) + for name in record["fpu_baseline_rtl"]: + copy(args.baseline_core / name, sources, "reference-fpu/" + name) + bind(sources, "ROB_PR10_SOURCES", commit) + for kind, directory in [("uart", uart), ("sources", sources)]: + compress(directory, out / ("arty-a7-rob-pr10-" + kind + ".zip")) + for path, name in [(args.bitstream, "toy_a7_rob_pr10_uart.bit"), + (ROOT / "board/program_arty.tcl", "program_arty.tcl"), + (ROOT / "board/build_board.tcl", "build_board.tcl")]: + copy(path, out, name) + assets = {path.name: {"sha256": digest(path), "bytes": path.stat().st_size} for path in sorted(out.iterdir()) if path.is_file()} + (out / "SHA256SUMS.txt").write_text("".join(item["sha256"] + " " + name + "\n" for name, item in assets.items())) + (out / "RELEASE_MANIFEST.json").write_text(json.dumps({"source_commit": commit, + "validation_input_commit": record["source_commit"], "engineering_prerelease": True, + "physical_hardware_tested": False, "assets": assets}, indent=2) + "\n") + print("PASS packaged ROB/PR10 prerelease:", out) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/scripts/prepare_fpga_memories.py b/platforms/arty-a7-toy/scripts/prepare_fpga_memories.py index 6c2b253..049f434 100644 --- a/platforms/arty-a7-toy/scripts/prepare_fpga_memories.py +++ b/platforms/arty-a7-toy/scripts/prepare_fpga_memories.py @@ -93,14 +93,14 @@ def emit_dual_memory(mem, style): return "\n".join(lines), style -def emit_memory(mem): +def emit_memory(mem, force_block=False): name, depth, width = (mem[k] for k in ("module_name", "depth", "width")) gran = mem.get("mask_granularity", width) lanes = width // gran addr = (depth - 1).bit_length() # A 64-row bank fits one LUT RAM per bit. Avoid wasting deep BRAM blocks # on shallow tags, MMIO banks and SubROB; keep 1024-row data banks in BRAM. - style = "distributed" if depth <= 64 else "block" + style = "block" if force_block else "distributed" if depth <= 64 else "block" if mem["read"] == 1: return emit_dual_memory(mem, style) ports = [ @@ -156,13 +156,19 @@ def main(): parser = argparse.ArgumentParser(description=__doc__) parser.add_argument("emission", type=Path) parser.add_argument("--output-dir", type=Path, required=True) + parser.add_argument("--block-memory", action="append", default=[], + help="明确将指定宏映射到 BRAM，包括 ROB 的浅层宽操作数 RAM") args = parser.parse_args() raw = args.emission.read_bytes() rtl, metadata, config = unpack_emission(raw.decode()) validate(metadata, config) + requested = set(args.block_memory) + available = {mem["module_name"] for mem in metadata} + if not requested <= available: + raise ValueError("Unknown block memory: " + ", ".join(sorted(requested - available))) modules, mappings = [], [] for mem in metadata: - module, style = emit_memory(mem) + module, style = emit_memory(mem, mem["module_name"] in requested) modules.append(module) mappings.append({**mem, "ram_style": style}) macros = "\n".join(modules) diff --git a/platforms/arty-a7-toy/scripts/prepare_rob_candidate.py b/platforms/arty-a7-toy/scripts/prepare_rob_candidate.py new file mode 100644 index 0000000..615b19d --- /dev/null +++ b/platforms/arty-a7-toy/scripts/prepare_rob_candidate.py @@ -0,0 +1,60 @@ +"""为 ROB 操作数候选显式绑定 BRAM，核对 profile 与已有存储器几何参数。""" + +import argparse +import hashlib +import json +from pathlib import Path +import subprocess +import sys + +from prepare_fpga_memories import unpack_emission, validate + +ROOT = Path(__file__).resolve().parents[1] + + +def digest(path): + return hashlib.sha256(path.read_bytes()).hexdigest() + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--baseline-memory-manifest", type=Path, required=True) + args = parser.parse_args() + raw = ROOT / "build/serial-raw/ToyLinuxChip.sv" + profile = json.loads((ROOT / "build/serial-raw/ToyLinuxChip.profile.json").read_text()) + expected = json.loads((ROOT / "evidence/2026-10-11/ToyLinuxChip.profile.json").read_text()) + if profile != expected: + raise ValueError("Optimization changed the architectural hardware profile") + _, memories, config = unpack_emission(raw.read_text()) + validate(memories, config) + operands = [m for m in memories if any("robOperands" in h for h in m["hierarchy"])] + if len(operands) != 1: + raise ValueError("Expected one ROB operand memory type") + operand = operands[0] + if (operand["depth"], operand["width"], operand["read"], operand["write"], + operand["readwrite"], operand["masked"], len(operand["hierarchy"])) != (16, 128, 1, 1, 0, False, 1): + raise ValueError("Unexpected ROB memory geometry or topology") + baseline = json.loads(args.baseline_memory_manifest.read_text()) + if baseline["core_rtl_sha256"] != "4c6aacf64660bbbf14b1114e8d5e4439d6a4e1427aaf1f681c6a4f618f2d2779": + raise ValueError("Wrong baseline memory manifest") + def signature(memory): + return tuple(memory.get(k) for k in + ("depth", "width", "read", "write", "readwrite", "masked", "mask_granularity")) + before = sorted((signature(m), len(m["hierarchy"])) for m in baseline["memories"]) + after = sorted((signature(m), len(m["hierarchy"])) for m in memories if m != operand) + if before != after: + raise ValueError("An existing memory geometry/topology changed") + subprocess.run([sys.executable, str(ROOT / "scripts/prepare_fpga_memories.py"), str(raw), + "--output-dir", str(ROOT / "build/serial-bound"), + "--block-memory", operand["module_name"]], check=True, timeout=60) + subprocess.run([sys.executable, str(ROOT / "scripts/bind_fpu_rf.py")], check=True, timeout=60) + record = {"result": "PREPARED_NOT_VALIDATED", "architectural_profile_unchanged": True, + "existing_memory_geometry_unchanged": True, "rob_operand_memory": operand, + "rob_operand_ram_style": "block", "core_rtl_sha256": digest(ROOT / "build/serial-bound/ToyLinuxChip.sv"), + "memory_rtl_sha256": digest(ROOT / "build/serial-bound/FpgaMemories.sv")} + (ROOT / "build/ROB_RAM_PREPARED.json").write_text(json.dumps(record, indent=2) + "\n") + print(json.dumps(record, indent=2)) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/scripts/run_hardware.py b/platforms/arty-a7-toy/scripts/run_hardware.py new file mode 100644 index 0000000..cae3f89 --- /dev/null +++ b/platforms/arty-a7-toy/scripts/run_hardware.py @@ -0,0 +1,211 @@ +"""从仓库准备固定 UART 发布包，复用原实板验证器；--prepare-only 不访问硬件。""" + +import argparse +import hashlib +import importlib.util +import json +import os +from pathlib import Path, PurePosixPath +import shutil +import stat +import struct +import subprocess +import sys +import time +import urllib.request +import uuid +import zipfile + +ROOT = Path(__file__).resolve().parents[1] + + +def require(value, message): + if not value: + raise ValueError(message) + + +def read_json(path): + return json.loads(path.read_text(encoding="utf-8")) + + +def digest(path): + result = hashlib.sha256() + with path.open("rb") as stream: + for block in iter(lambda: stream.read(1024 * 1024), b""): + result.update(block) + return result.hexdigest() + + +def check_archive(path, release): + require(path.stat().st_size == release["archive_bytes"] and + digest(path) == release["archive_sha256"], "UART 包与固定发布摘要不匹配：" + str(path)) + + +def unpack(archive, destination): + # Validate all names before writing anything, including Windows aliases/ADS. + destination = destination.resolve() + with zipfile.ZipFile(archive) as package: + names = set() + total = 0 + for item in package.infolist(): + name = item.filename + parts = PurePosixPath(name).parts + require(parts and not name.startswith("/") and "\\" not in name and + all(part not in [".", ".."] and ":" not in part and + not part.endswith((".", " ")) for part in parts), "ZIP 路径无效：" + name) + require(stat.S_IFMT(item.external_attr >> 16) != stat.S_IFLNK, "ZIP 不允许符号链接") + require(name.casefold() not in names, "ZIP 文件名重复：" + name) + names.add(name.casefold()) + require((destination / name).resolve().is_relative_to(destination), "ZIP 路径越界") + total += item.file_size + require(total <= 256 * 1024 * 1024, "UART 包解压大小异常") + package.extractall(destination) + + +def check_bundle(directory, release): + require(digest(directory / "MANIFEST.json") == release["manifest_sha256"], "缓存清单与固定发布不匹配") + spec = importlib.util.spec_from_file_location("hardware_bundle_verifier", ROOT / "distribution-rob/verify_bundle.py") + verifier = importlib.util.module_from_spec(spec) + spec.loader.exec_module(verifier) + manifest = verifier.verify(directory) + for field in ["flow", "target", "source_commit"]: + require(manifest[field] == release[field], "发布包配置不匹配：" + field) + validation = read_json(directory / "VALIDATION_RESULT.json") + require(validation["result"] == "PASS_ROB_PR10_FULL_VALIDATION" and + validation["source_commit"] == release["validation_input_commit"] and + validation["profile"] == release["profile"], "发布包缺少对应实现/RTL 验证") + for name, field in [("toy_a7_uart.bit", "bitstream_sha256"), ("fw_payload.bin", "payload_sha256")]: + require(manifest["files"][name]["sha256"] == validation[field] == release[field], "位流/软件版本不匹配") + software = read_json(directory / "LINUX_GEMMINI_BUILD.json") + require(software["payload_sha256"] == release["payload_sha256"] and + software["payload_bytes"] == release["payload_bytes"] and + len(software["workloads"]) == release["test_count"], "软件测试清单不匹配") + return directory + + +def prepare(release, cache, supplied_archive=None): + cache = cache.resolve() + cache.mkdir(parents=True, exist_ok=True) + archive = cache / "uart.zip" + if supplied_archive: + supplied_archive = supplied_archive.resolve() + check_archive(supplied_archive, release) + if archive.exists(): + check_archive(archive, release) + else: + partial = cache / ("uart-" + uuid.uuid4().hex + ".part") + try: + if supplied_archive: + shutil.copyfile(supplied_archive, partial) + else: + print("下载固定 UART 发布包：" + release["tag"], flush=True) + request = urllib.request.Request(release["url"], headers={"User-Agent": "DangoSys-FPGA-hardware-check"}) + with urllib.request.urlopen(request, timeout=60) as response, partial.open("wb") as stream: + received = 0 + started = time.monotonic() + while block := response.read(1024 * 1024): + received += len(block) + require(received <= release["archive_bytes"], "下载文件超过固定大小") + if time.monotonic() - started > 300: + raise TimeoutError("下载超过 300 秒；可用 --bundle-zip 指定本地发布包") + stream.write(block) + check_archive(partial, release) + partial.rename(archive) + finally: + if partial.exists(): + partial.unlink() + bundle = cache / "bundle" + if not bundle.exists(): + staging = cache / ("staging-" + uuid.uuid4().hex) + staging.mkdir() + unpack(archive, staging) + check_bundle(staging, release) + require(staging.resolve().is_relative_to(cache) and bundle.resolve().is_relative_to(cache), "缓存路径越界") + staging.rename(bundle) + return check_bundle(bundle, release) + + +def check_host(port, vivado): + require(os.name == "nt" and struct.calcsize("P") == 8, "实板入口需要 Windows 与 64 位 Python 3.10+；其他环境可使用 --prepare-only") + require(vivado.is_file(), "未找到 Vivado：" + str(vivado)) + require(Path("C:/Windows/System32/ftd2xx.dll").is_file(), "未找到 64 位 FTDI D2XX 驱动，请先安装板卡驱动") + try: + import serial.tools.list_ports + except ImportError as error: + raise RuntimeError("请先运行 python -m pip install -r host/requirements-hardware.txt") from error + matches = [item for item in serial.tools.list_ports.comports() if item.device.casefold() == port.casefold()] + require(len(matches) == 1, "没有找到指定串口 " + port + "；请连接 PROG/UART USB 并检查设备管理器") + device = matches[0] + require((device.vid, device.pid) == (0x0403, 0x6010) and + (device.serial_number or "").endswith("B"), "指定端口不是 FT2232 UART B；请勿选择 JTAG A") + return device.device + + +def verify_hardware(bundle, release, port, vivado): + before = set((bundle / "build").glob("hardware-gemmini-*/RESULT.json")) + command = [sys.executable, "-X", "utf8", "-u", str(bundle / "host/check_linux_gemmini.py"), + "--payload", str(bundle / "fw_payload.bin"), "--build-result", str(bundle / "LINUX_GEMMINI_BUILD.json"), + "--bitstream", str(bundle / "toy_a7_uart.bit"), "--expected-bit-sha256", release["bitstream_sha256"], + "--port", port, "--vivado", str(vivado)] + print("开始临时 JTAG 配置、DDR 完整读回与 Linux/Gemmini 验证，硬超时 3600 秒。", flush=True) + process = subprocess.Popen(command, cwd=bundle) + try: + code = process.wait(timeout=release["timeout_seconds"]) + except BaseException: + # Terminate only this launched process tree, including its Vivado child. + if process.poll() is None: + subprocess.run(["taskkill", "/PID", str(process.pid), "/T", "/F"], timeout=15, check=False) + process.wait(timeout=15) + raise + require(code == 0, "原实板验证器失败，退出码 " + str(code) + "；日志位于 " + str(bundle / "build")) + created = set((bundle / "build").glob("hardware-gemmini-*/RESULT.json")) - before + require(len(created) == 1, "没有取得本轮唯一实板结果，不能沿用旧 PASS") + result_path = created.pop() + result = read_json(result_path) + require(result["result"] == "PASS_LINUX_AND_GEMMINI_HARDWARE" and not result["flash_written"] and + result["bitstream_sha256"] == release["bitstream_sha256"] and + result["payload_sha256"] == release["payload_sha256"] and + result["ddr_readback_bytes"] == release["payload_bytes"] and + result["test_count"] == len(result["tests"]) == release["test_count"] and + all(item["exit_code"] == 0 for item in result["tests"]), "本轮实板结果不完整或版本不匹配") + return result_path + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--port", help="Windows 的 FT2232 UART B 串口，例如 COM5") + parser.add_argument("--vivado", type=Path, help="vivado.bat 的完整路径") + parser.add_argument("--bundle-zip", type=Path, help="已下载的固定 UART ZIP；省略则自动下载") + parser.add_argument("--prepare-only", action="store_true", help="只下载/校验/解压，不连接串口或调用 Vivado") + args = parser.parse_args() + if not args.prepare_only and (not args.port or not args.vivado): + parser.error("实板验证需要 --port 和 --vivado；离线准备请使用 --prepare-only") + release = read_json(ROOT / "HARDWARE_RELEASE.json") + require(release["tag"] and all(c.isalnum() or c in "-_" for c in release["tag"]), "发布标签无效") + output = ROOT / "build/hardware-entry" / (time.strftime("%Y%m%d-%H%M%S") + "-" + uuid.uuid4().hex[:8]) + output.mkdir(parents=True, exist_ok=False) + result = {"status": "RUNNING", "release": release, "physical_hardware_tested": False, "flash_written": False} + started = time.monotonic() + try: + port = check_host(args.port, args.vivado.resolve()) if not args.prepare_only else None + bundle = prepare(release, ROOT / "build/hardware-release" / release["tag"], args.bundle_zip) + result["bundle_directory"] = str(bundle) + if args.prepare_only: + result["status"] = "PREPARED_NOT_HARDWARE_TESTED" + print("产物准备完成；未访问硬件：" + str(bundle), flush=True) + else: + hardware_result = verify_hardware(bundle, release, port, args.vivado.resolve()) + result.update(status="PASS_LINUX_AND_GEMMINI_HARDWARE", physical_hardware_tested=True, + hardware_result=str(hardware_result)) + print("PASS 本轮实板验证；原始日志：" + str(hardware_result.parent), flush=True) + except BaseException as error: + result.update(status="FAILED", error=str(error)) + raise + finally: + result["elapsed_seconds"] = round(time.monotonic() - started, 3) + (output / "RUN.json").write_text(json.dumps(result, indent=2, ensure_ascii=False) + "\n", encoding="utf-8") + print("入口记录：" + str(output / "RUN.json"), flush=True) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/scripts/start_rob_board_build.py b/platforms/arty-a7-toy/scripts/start_rob_board_build.py new file mode 100644 index 0000000..de57b6d --- /dev/null +++ b/platforms/arty-a7-toy/scripts/start_rob_board_build.py @@ -0,0 +1,63 @@ +"""以独立候选记录执行同一整板流程；不继承旧位流的资格结论。""" + +import argparse +from datetime import datetime +import json +import os +from pathlib import Path +import shutil +import subprocess +import sys + +from start_board_build import ROOT, TZ, save, sha, worker + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--worker", type=Path) + args = parser.parse_args() + if args.worker: + out = args.worker.resolve() + worker(out) + record = json.loads((out / "RUN.json").read_text()) + record["candidate_core_unchanged"] = sha(ROOT / "build/serial-bound/ToyLinuxChip.sv") == record["core_sha256"] + record["candidate_memory_unchanged"] = sha(ROOT / "build/serial-bound/FpgaMemories.sv") == record["memory_sha256"] + if not record["candidate_core_unchanged"] or not record["candidate_memory_unchanged"]: + record["status"] = "INPUT_CHANGED_REJECTED" + save(out / "RUN.json", record) + return + prepared = json.loads((ROOT / "build/ROB_RAM_PREPARED.json").read_text()) + for path in ["build/globalrob-check/RESULT.json", "build/BOARD_REGRESSION.json"]: + if json.loads((ROOT / path).read_text())["result"] != "PASS": + raise ValueError("Candidate regression has not passed: " + path) + core = ROOT / "build/serial-bound/ToyLinuxChip.sv" + memories = ROOT / "build/serial-bound/FpgaMemories.sv" + if sha(core) != prepared["core_rtl_sha256"] or sha(memories) != prepared["memory_rtl_sha256"]: + raise ValueError("Candidate inputs changed after preparation") + for path in (ROOT / "build").glob("board-*/RUN.json"): + if json.loads(path.read_text())["status"] in ("CREATED", "RUNNING"): + raise ValueError("An isolated board build is already active") + out = ROOT / "build" / ("board-rob-ram-" + datetime.now(TZ).strftime("%Y%m%d-%H%M%S")) + out.mkdir() + shutil.copytree(ROOT / "board", out / "inputs/board") + files = {str(p.relative_to(ROOT)): sha(p) for p in (ROOT / "board").rglob("*") if p.is_file()} + script = out / "inputs/board/build_board.tcl" + # Keep the input snapshot for audit, execute the identical script at its + # normal root so relative HDL/IP paths resolve without rewriting Tcl. + record = {"status": "CREATED", "optimization": "ROB_OPERAND_BRAM", "timeout_seconds": 3600, + "termination_grace_seconds": 15, "part": "xc7a100tcsg324-1", + "core_sha256": sha(core), "memory_sha256": sha(memories), "board_sources": files, + "execution_script": str(ROOT / "board/build_board.tcl"), "execution_script_sha256": sha(script), + "core_clock_hz": 25000000, "uart_baud": 1000000, + "architectural_profile_unchanged": True, "flash_boot": False, + "physical_boot_tested": False, "inherits_baseline_hardware_qualification": False} + save(out / "RUN.json", record) + with (out / "launcher.log").open("w") as log: + process = subprocess.Popen([sys.executable, str(Path(__file__).resolve()), "--worker", str(out)], + cwd=ROOT, stdout=log, stderr=subprocess.STDOUT, stdin=subprocess.DEVNULL, + start_new_session=True, close_fds=True) + print(json.dumps({"output_directory": str(out), "worker_pid": process.pid, "timeout_seconds": 3600})) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/scripts/verify_hardware_evidence.py b/platforms/arty-a7-toy/scripts/verify_hardware_evidence.py index d674054..c8900a1 100644 --- a/platforms/arty-a7-toy/scripts/verify_hardware_evidence.py +++ b/platforms/arty-a7-toy/scripts/verify_hardware_evidence.py @@ -22,7 +22,9 @@ def verify(): assert manifest["time_zone"] == "Asia/Shanghai" for name, metadata in manifest["files"].items(): assert sha(ARCHIVE / name) == metadata["sha256"], name - assert sha(ROOT / "board/program_arty.tcl") == sha(ARCHIVE / "program_arty.tcl") + # Historical programming evidence binds the archived script, not later + # revised entry points. Current sources have their own SOURCE_LOCK/tests. + assert sha(ARCHIVE / "program_arty.tcl") == manifest["files"]["program_arty.tcl"]["sha256"] assert sha(ROOT / "host/load.py") == manifest["host_loader_sha256"] hardware = read(ARCHIVE / "HARDWARE_RESULT.json") implementation = read(ROOT / "evidence/2026-10-11/BOARD_RESULT.json") diff --git a/platforms/arty-a7-toy/scripts/verify_pr10_evidence.py b/platforms/arty-a7-toy/scripts/verify_pr10_evidence.py new file mode 100644 index 0000000..c55cb2e --- /dev/null +++ b/platforms/arty-a7-toy/scripts/verify_pr10_evidence.py @@ -0,0 +1,87 @@ +"""离线核验 PR #10 的不可变测试档案，不继承历史实物资格。""" + +import hashlib +import json +from pathlib import Path + +ARCHIVE = Path(__file__).resolve().parents[1] / "evidence/2026-10-12/pr10-review" + + +def read(name): + return json.loads((ARCHIVE / name).read_text(encoding="utf-8")) + + +def require(condition, message): + if not condition: + raise ValueError(message) + + +def main(): + manifest = read("MANIFEST.json") + for name, item in manifest["files"].items(): + data = (ARCHIVE / name).read_bytes() + require(hashlib.sha256(data).hexdigest() == item["sha256"], name) + require(len(data) == item["bytes"], name) + record = read("RESULT.json") + require(record["result"] == "PASS_PR10_EVALUATION_AND_OFFLINE_REGRESSIONS", "review result") + require(not any(record[key] for key in ["physical_hardware_tested", "new_bitstream_generated", + "cpu_behavior_simulated", "physical_mig_simulated"]), "test scope") + require(record["focused_patch_apply_check_exit_code"] == 0, "patch compatibility") + require(len(record["comparison"]) == 5, "compared files") + require(all(item["byte_identical"] and item["base_sha256"] == item["current_sha256"] + for item in record["comparison"].values()), "old/current comparison") + for name, expected in record["sources"].items(): + require(manifest["files"]["sources/" + name]["sha256"] == expected, name) + require(manifest["files"]["old-platform.sv"]["sha256"] == + record["old_platform_expected_negative"]["source_sha256"], "old platform") + board = read("board-unit/RESULT.json") + require(board["result"] == "PASS" and board["tests"] == 4, "interface groups") + ports = read("sources/tests/PLATFORM_PORTS_MANIFEST.json") + require(not ports["cpu_behavior_included"], "CPU fixture scope") + require(ports["stub_sha256"] == record["sources"]["tests/ToyLinuxChipPorts.sv"], "port fixture bytes") + for directory, count in [("programming-check", 20), ("flash-guard-check", 10)]: + cases = read(directory + "/RESULT.json")["cases"] + require(len(cases) == count and all(case["result"] == "PASS" for case in cases), directory) + negative = (ARCHIVE / "old-platform-negative.log").read_text() + require("addr=60030000 actual=01 expected=10" in negative, "old RTL negative oracle") + for name in ["program_arty.tcl", "backup_flash.tcl", "program_flash.tcl"]: + log = (ARCHIVE / "original-pr" / (name + ".log")).read_text() + require("MOCK_FAILURE expected boolean value" in log, name) + print(f"PASS PR10 archive: {len(manifest['files'])} artifacts; 4/20/10 offline checks and expected negatives") + verify_selfcheck() + + +def verify_selfcheck(): + archive = ARCHIVE.parents[1] / "2026-10-13/pr10-selfcheck" + + def load(name): + return json.loads((archive / name).read_text(encoding="utf-8")) + + manifest = load("MANIFEST.json") + for name, item in manifest["files"].items(): + data = (archive / name).read_bytes() + require(hashlib.sha256(data).hexdigest() == item["sha256"] and len(data) == item["bytes"], name) + record = load("RESULT.json") + require(record["result"] == "PASS_PR10_SELFCHECK", "selfcheck result") + require(not record["physical_hardware_tested"] and not record["new_bitstream_generated"], "selfcheck scope") + for name, expected in record["sources"].items(): + require(manifest["files"]["sources/" + name]["sha256"] == expected, name) + require(load("board-unit/RESULT.json")["tests"] == 4, "selfcheck interface groups") + for directory, count in [("programming-check", 20), ("flash-guard-check", 10), + ("runner-status-check", 3), ("backpressure-mutation", 3)]: + cases = load(directory + "/RESULT.json")["cases"] + require(len(cases) == count and all(case["result"] == "PASS" for case in cases), directory) + current = load("runner-status-check/RESULT.json")["cases"] + require(all(case["exit_code"] != 0 and case["observed_result"] == "FAILED" for case in current), "fresh failures") + old = load("stale-baseline/RESULT.json")["cases"] + require(len(old) == 3 and all(case["exit_code"] != 0 and case["observed_result"].startswith("PASS") + for case in old), "stale baseline counterexamples") + mutations = {case["case"]: case for case in load("backpressure-mutation/RESULT.json")["cases"]} + require({name: case["exit_code"] for name, case in mutations.items()} == + {"old-test": 0, "new-test": 1, "old-response": 1}, "mutation outcomes") + require("valid=0" in (archive / "backpressure-mutation/new-test.log").read_text(), "BVALID oracle") + print(f"PASS PR10 selfcheck archive: {len(manifest['files'])} artifacts; fresh failure status and BVALID oracles") + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/scripts/verify_rob_evidence.py b/platforms/arty-a7-toy/scripts/verify_rob_evidence.py new file mode 100644 index 0000000..bbd395a --- /dev/null +++ b/platforms/arty-a7-toy/scripts/verify_rob_evidence.py @@ -0,0 +1,94 @@ +"""核验 ROB RAM 候选档案；实物资格不从旧版本继承。""" + +import argparse +import hashlib +import json +from pathlib import Path +import re + +ROOT = Path(__file__).resolve().parents[1] +ARCHIVE = ROOT / "evidence/2026-10-12/rob-ram" + + +def read(path): + return json.loads(path.read_text(encoding="utf-8")) + + +def sha(path): + return hashlib.sha256(path.read_bytes()).hexdigest() + + +def resources(path): + labels = {"Slice LUTs": "LUT", "Slice Registers": "FF", "Slice": "Slice", + "Block RAM Tile": "BRAM_tiles", "DSPs": "DSP"} + values = {} + for line in path.read_text().splitlines(): + fields = [field.strip() for field in line.split("|")] + if len(fields) > 3 and fields[1] in labels: + values[labels[fields[1]]] = float(fields[2]) + assert set(values) == set(labels.values()) + return values + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--core", action="store_true") + args = parser.parse_args() + manifest = read(ARCHIVE / "MANIFEST.json") + for name, expected in manifest["files"].items(): + assert sha(ARCHIVE / name) == expected, name + record = read(ARCHIVE / "RESULT.json") + assert record["result"] == "PASS_ROB_RAM_RTL_AND_BOARD_IMPLEMENTATION" + assert record["physical_board_tested"] is False + assert record["flash_boot_tested"] is False + run = read(ARCHIVE / "implementation/RUN.json") + assert run["status"] == "COMPLETED" and run["exit_code"] == 0 + assert run["bitstream_generated"] and run["timeout_seconds"] == 3600 + assert run["candidate_core_unchanged"] and run["candidate_memory_unchanged"] + assert resources(ARCHIVE / "implementation/routed-utilization.rpt") == record["routed_resources"] + before = read(ROOT / "evidence/2026-10-11/BOARD_RESULT.json")["routed_resources"] + for name, value in record["routed_resources"].items(): + assert value - before[name] == record["resource_delta"][name], name + assert read(ARCHIVE / "ToyLinuxChip.profile.json") == read( + ROOT / "evidence/2026-10-11/ToyLinuxChip.profile.json") + assert read(ARCHIVE / "tests/globalrob/RESULT.json")["result"] == "PASS" + assert "PASS all memory bindings" in (ARCHIVE / "tests/rob-memory-regression.log").read_text() + regressions = read(ARCHIVE / "tests/BOARD_REGRESSION.json") + baseline = read(ROOT / "evidence/2026-10-11/tests/BOARD_REGRESSION.json") + assert regressions["result"] == "PASS" + for name, case in regressions["tests"].items(): + assert case["result"] == "PASS" + assert case["cycles"] == baseline["tests"][name]["cycles"] + assert case["binary_sha256"] == baseline["tests"][name]["binary_sha256"] + linux = read(ARCHIVE / "tests/linux-final/RESULT.json") + assert linux["result"] == "PASS_RTL_LINUX_USERSPACE" and not linux["physical_board_tested"] + transcript = (ARCHIVE / "tests/linux-final/simulation.log").read_text() + for marker in linux["checks"]: + assert marker in transcript, marker + assert "PASS BOARD_LINUX_USERSPACE cycles=273506752" in transcript + timing = (ARCHIVE / "implementation/routed-timing.rpt").read_text() + assert "All user specified timing constraints are met." in timing + rows = timing.split("WNS(ns)", 1)[1].splitlines() + values = next(line.split() for line in rows if re.match(r"\s+-?\d+\.\d+", line)) + assert float(values[0]) == record["timing"]["wns_ns"] >= 0 + assert float(values[4]) == record["timing"]["whs_ns"] >= 0 + assert all(float(values[n]) == 0 for n in [1, 2, 5, 6, 9, 10]) + route = (ARCHIVE / "implementation/route-status.rpt").read_text() + assert re.search(r"nets with routing errors\.+\s*:\s*0\s*:", route) + for name in ["drc.rpt", "cdc.rpt"]: + assert not re.search(r"\b(?:Critical|Error)\b", (ARCHIVE / "implementation" / name).read_text()) + assert read(ARCHIVE / "OPTIN_RESULT.json")["result"] == "PASS_DEFAULT_AND_CANDIDATE_BYTE_IDENTITY" + memory = read(ARCHIVE / "MEMORY_MANIFEST.json") + assert memory["core_rtl_sha256"] == record["core_rtl_sha256"] == run["core_sha256"] + assert memory["memory_rtl_sha256"] == record["memory_rtl_sha256"] == run["memory_sha256"] + for name, expected in record["integration_sources"].items(): + assert sha(ROOT / name) == expected, name + if args.core: + assert sha(ROOT / "build/serial-bound/ToyLinuxChip.sv") == record["core_rtl_sha256"] + assert sha(ROOT / "build/serial-bound/FpgaMemories.sv") == record["memory_rtl_sha256"] + print(f"PASS ROB RAM archive: {len(manifest['files'])} files; unchanged regression cycles; routed candidate") + print("This initial archive predates physical tests; later hardware evidence is in PR #9") + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/scripts/verify_rob_pr10_full.py b/platforms/arty-a7-toy/scripts/verify_rob_pr10_full.py new file mode 100644 index 0000000..0db9638 --- /dev/null +++ b/platforms/arty-a7-toy/scripts/verify_rob_pr10_full.py @@ -0,0 +1,83 @@ +"""离线核验本轮完整实现/RTL 档案，可另传位流检查实际摘要；不访问硬件。""" + +import argparse +import hashlib +import json +from pathlib import Path +import re + +ROOT = Path(__file__).resolve().parents[1] +ARCHIVE = ROOT / "evidence/2026-10-13/rob-pr10-full" + + +def read(name): + return json.loads((ARCHIVE / name).read_text(encoding="utf-8")) + + +def require(condition, message): + if not condition: + raise ValueError(message) + + +def sha(path): + return hashlib.sha256(path.read_bytes()).hexdigest() + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--bitstream", type=Path) + args = parser.parse_args() + manifest = read("MANIFEST.json") + for name, metadata in manifest["files"].items(): + path = ARCHIVE / name + require(sha(path) == metadata["sha256"] and path.stat().st_size == metadata["bytes"], name) + result = read("RESULT.json") + require(result["result"] == "PASS_ROB_PR10_FULL_VALIDATION", "full result") + require(result["engineering_prerelease"] and not result["physical_hardware_tested"], "physical qualification") + require(not result["physical_mig_simulated"] and not result["flash_boot_tested"], "simulation scope") + run = read("implementation/RUN.json") + require(run["status"] == "COMPLETED" and run["exit_code"] == 0 and run["bitstream_generated"], "implementation") + require(run["candidate_core_unchanged"] and run["candidate_memory_unchanged"], "generated inputs") + require(run["timeout_seconds"] == 3600 and run["elapsed_seconds"] < 3600, "timeout") + require(run["part"] == result["part"] == "xc7a100tcsg324-1", "target") + for name, expected in run["board_sources"].items(): + require(sha(ARCHIVE / "sources" / name) == expected, name) + inputs = read("INPUTS.json") + for name, expected in inputs["files"].items(): + require(sha(ARCHIVE / "sources" / name) == expected, name) + timing = (ARCHIVE / "implementation/routed-timing.rpt").read_text() + require("All user specified timing constraints are met." in timing, "timing summary") + rows = timing.split("WNS(ns)", 1)[1].splitlines() + values = next(line.split() for line in rows if re.match(r"\s+-?\d+\.\d+", line)) + require(float(values[0]) == result["timing"]["wns_ns"] >= 0 and + float(values[4]) == result["timing"]["whs_ns"] >= 0, "slack") + require(all(float(values[i]) == 0 for i in [1, 2, 5, 6]), "violating endpoints") + for name in ["drc.rpt", "cdc.rpt"]: + require(not re.search(r"\b(?:Critical|Error)\b", (ARCHIVE / "implementation" / name).read_text()), name) + route = (ARCHIVE / "implementation/route-status.rpt").read_text() + require(bool(re.search(r"nets with routing errors\.+\s*:\s*0\s*:", route)), "route errors") + linux = read("tests/board-linux-final/RESULT.json") + require(linux["result"] == "PASS_RTL_LINUX_USERSPACE" and not linux["physical_board_tested"], "Linux scope") + log = (ARCHIVE / "tests/board-linux-final/simulation.log").read_text() + require(all(marker in log for marker in linux["checks"]), "Linux markers") + require(linux["payload_sha256"] == result["payload_sha256"], "Linux input") + regressions = read("BOARD_REGRESSION.json")["tests"] + require(len(regressions) == 4 and all(case["result"] == "PASS" for case in regressions.values()), "board cases") + baseline = json.loads((ROOT / "evidence/2026-10-12/rob-ram/tests/BOARD_REGRESSION.json").read_text()) + require(all(case["cycles"] == baseline["tests"][name]["cycles"] for name, case in regressions.items()), "same cycles") + require(read("tests/core-unit-regressions/RESULT.json")["result"] == "PASS_UNIT_REGRESSIONS", "units") + require(read("tests/fpu-shared/RESULT.json")["vector_count"] == 1536, "floating vectors") + require(read("tests/board-cdc/RESULT.json")["result"] == "PASS_BOARD_CDC", "actual CDC IP") + uart = read("tests/board-uart-boot/RESULT.json") + require(uart["result"] == "PASS_UART_LOAD_VERIFY_BOOT" and uart["bytes_verified"] == 110592, "UART boot") + require(not uart["testbench_cpu_release_override"] and not uart["preloaded_ddr_image"], "UART loader boundary") + mmio = read("tests/board-mmio-error/RESULT.json") + require(mmio["result"] == "PASS_CPU_MMIO_SLVERR" and mmio["synchronous_traps_observed"] == 0, "MMIO scope") + require("CPU did not receive SLVERR" in (ARCHIVE / "tests/mmio-old-counterexample/simulation.log").read_text(), "old negative") + if args.bitstream: + require(sha(args.bitstream) == result["bitstream_sha256"], "actual bitstream") + print(f"PASS ROB/PR10 full archive: {len(manifest['files'])} artifacts; implementation, units, CPU/Gemmini/Linux and actual CDC") + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/src/main/scala/EmitGlobalRobCheck.scala b/platforms/arty-a7-toy/src/main/scala/EmitGlobalRobCheck.scala new file mode 100644 index 0000000..859e462 --- /dev/null +++ b/platforms/arty-a7-toy/src/main/scala/EmitGlobalRobCheck.scala @@ -0,0 +1,110 @@ +package fpga.arty.linux + +import chisel3._ +import chisel3.util._ +import _root_.circt.stage.ChiselStage +import framework.frontend.globalrs.GlobalROB +import framework.frontend.decoder.{DomainId, PostGDCmd} +import framework.memdomain.frontend.cmd.decoder.DISA.MSET_BITPAT + +/** Cycle comparison of register and synchronous-RAM operand storage. */ +class GlobalRobCheck extends Module { + val seed = IO(Input(UInt(32.W))) + val passed = IO(Output(Bool())) + private val b = OriginalToy.serial + val dut = Module(new GlobalROB(b, useOperandRam = true)) + val reference = Module(new GlobalROB(b, useOperandRam = false)) + val cycle = RegInit(0.U(16.W)) + val random = RegInit(seed) + cycle := cycle + 1.U + random := Cat(random(30, 0), random(31) ^ random(21) ^ random(1) ^ random(0)) + assert(cycle < 9000.U, "GlobalROB drain timeout") + + val source = Module(new Queue(new PostGDCmd(b), 2)) + val generated = Wire(new PostGDCmd(b)) + generated := 0.U.asTypeOf(generated) + val config = random(5, 2) === 0.U + generated.domain_id := Mux(config || random(2), DomainId.MEM, DomainId.BALL) + generated.ball_bid := 0.U + generated.cmd.funct := Mux(config, MSET_BITPAT.value.U(7.W), Mux(random(3), 53.U, 66.U)) + generated.cmd.raw_inst := random + generated.cmd.pc := Cat(random, ~random) + generated.cmd.rs1Data := Cat(random, random ^ "h597bdf03".U) + generated.cmd.rs2Data := Mux(config, + Cat(random, 0.U(21.W), 1.U(1.W), 0.U(3.W), random(1, 0), 0.U(5.W)), + Cat(~random, random ^ "h26ac048e".U)) + generated.bankAccess.rd_bank_0_valid := !config && random(8) + generated.bankAccess.rd_bank_1_valid := !config && random(9) + generated.bankAccess.wr_bank_valid := config || random(10) + generated.bankAccess.rd_bank_0_id := random(14, 11) + generated.bankAccess.rd_bank_1_id := random(18, 15) + generated.bankAccess.wr_bank_id := random(22, 19) + source.io.enq.valid := cycle < 5000.U && random(0) + source.io.enq.bits := generated + dut.io.alloc <> source.io.deq + reference.io.alloc.valid := dut.io.alloc.valid + reference.io.alloc.bits := dut.io.alloc.bits + + val completions = Module(new Queue(UInt(log2Ceil(b.frontend.rob_entries).W), 16)) + val active = cycle(9, 6) === 13.U + val ready = completions.io.enq.ready && random(7) && cycle(8, 5) =/= 7.U + dut.io.issue.ready := ready + reference.io.issue.ready := ready + completions.io.enq.valid := dut.io.issue.fire + completions.io.enq.bits := dut.io.issue.bits.rob_id + dut.io.complete.valid := completions.io.deq.valid && random(4) + dut.io.complete.bits := completions.io.deq.bits + reference.io.complete.valid := dut.io.complete.valid + reference.io.complete.bits := dut.io.complete.bits + completions.io.deq.ready := dut.io.complete.ready && random(4) + dut.io.hart_id := 0.U + reference.io.hart_id := 0.U + dut.io.subRobActive := active + reference.io.subRobActive := active + + assert(dut.io.alloc.ready === reference.io.alloc.ready, "ROB allocation timing mismatch") + assert(dut.io.complete.ready === reference.io.complete.ready, "ROB completion timing mismatch") + assert(dut.io.issue.valid === reference.io.issue.valid, "ROB issue timing mismatch") + when(dut.io.issue.valid) { + assert(dut.io.issue.bits.asUInt === reference.io.issue.bits.asUInt, "ROB issue payload mismatch") + } + assert(dut.io.empty === reference.io.empty && dut.io.full === reference.io.full) + assert(dut.io.head_ptr === reference.io.head_ptr) + assert(dut.io.issued_count === reference.io.issued_count) + assert(dut.io.entry_valid.asUInt === reference.io.entry_valid.asUInt) + assert(dut.io.entry_complete.asUInt === reference.io.entry_complete.asUInt) + assert(dut.io.inst_ids.asUInt === reference.io.inst_ids.asUInt) + + val allocated = RegInit(0.U(16.W)) + val issued = RegInit(0.U(16.W)) + val completed = RegInit(0.U(16.W)) + val sawFull = RegInit(false.B) + val sawStall = RegInit(false.B) + val expected = Reg(Vec(b.frontend.rob_entries, chiselTypeOf(generated.cmd))) + val allocationSlot = RegInit(0.U(log2Ceil(b.frontend.rob_entries).W)) + when(dut.io.alloc.fire) { + allocated := allocated + 1.U + expected(allocationSlot) := dut.io.alloc.bits.cmd + allocationSlot := Mux(allocationSlot === (b.frontend.rob_entries - 1).U, + 0.U, allocationSlot + 1.U) + } + when(dut.io.issue.fire) { + issued := issued + 1.U + assert(dut.io.issue.bits.cmd.cmd.asUInt === expected(dut.io.issue.bits.rob_id).asUInt, + "ROB changed accepted command operands") + } + when(dut.io.complete.fire) { completed := completed + 1.U } + when(dut.io.full) { sawFull := true.B } + when(dut.io.issue.valid && !ready) { sawStall := true.B } + passed := cycle > 5005.U && !source.io.deq.valid && dut.io.empty && !completions.io.deq.valid + when(passed) { + assert(allocated === issued && issued === completed && allocated > 64.U) + assert(sawFull && sawStall, "Missing ROB full/stall coverage") + } +} + +object EmitGlobalRobCheck extends App { + ChiselStage.emitSystemVerilogFile(new GlobalRobCheck, + Array("--target-dir", args.headOption.getOrElse("build/globalrob-check")), + Array("-disable-all-randomization", "-strip-debug-info")) +} diff --git a/platforms/arty-a7-toy/tests/PLATFORM_PORTS_MANIFEST.json b/platforms/arty-a7-toy/tests/PLATFORM_PORTS_MANIFEST.json new file mode 100644 index 0000000..3c892d5 --- /dev/null +++ b/platforms/arty-a7-toy/tests/PLATFORM_PORTS_MANIFEST.json @@ -0,0 +1,7 @@ +{ + "source_core_sha256": "31e7e07f94d08208dbb564edf9546240df26ff834935bfb646b71b541d875fb9", + "port_header_sha256": "3329804932f5a7632f78bbe56797f9bff35fb6f94910f0a474c59a9a0a90bf5d", + "stub_sha256": "e4c06220cd7025972d432b06c452e85c62bd2cfccad618b2b993499b62e6621a", + "cpu_behavior_included": false, + "port_header_hash_encoding": "UTF-8 with LF newlines" +} diff --git a/platforms/arty-a7-toy/tests/ToyLinuxChipPorts.sv b/platforms/arty-a7-toy/tests/ToyLinuxChipPorts.sv new file mode 100644 index 0000000..6e07c67 --- /dev/null +++ b/platforms/arty-a7-toy/tests/ToyLinuxChipPorts.sv @@ -0,0 +1,134 @@ +// Port-only fixture from the Chisel-generated core; no CPU behavior. +// Outputs idle at zero. The testbench drives the real platform AXI port. +module ToyLinuxChip( + input clock, + reset, + interrupt, + memory_aw_ready, + output memory_aw_valid, + output [3:0] memory_aw_bits_id, + output [31:0] memory_aw_bits_addr, + output [7:0] memory_aw_bits_len, + output [2:0] memory_aw_bits_size, + output [1:0] memory_aw_bits_burst, + output memory_aw_bits_lock, + output [3:0] memory_aw_bits_cache, + output [2:0] memory_aw_bits_prot, + output [3:0] memory_aw_bits_qos, + input memory_w_ready, + output memory_w_valid, + output [127:0] memory_w_bits_data, + output [15:0] memory_w_bits_strb, + output memory_w_bits_last, + memory_b_ready, + input memory_b_valid, + input [3:0] memory_b_bits_id, + input [1:0] memory_b_bits_resp, + input memory_ar_ready, + output memory_ar_valid, + output [3:0] memory_ar_bits_id, + output [31:0] memory_ar_bits_addr, + output [7:0] memory_ar_bits_len, + output [2:0] memory_ar_bits_size, + output [1:0] memory_ar_bits_burst, + output memory_ar_bits_lock, + output [3:0] memory_ar_bits_cache, + output [2:0] memory_ar_bits_prot, + output [3:0] memory_ar_bits_qos, + output memory_r_ready, + input memory_r_valid, + input [3:0] memory_r_bits_id, + input [127:0] memory_r_bits_data, + input [1:0] memory_r_bits_resp, + input memory_r_bits_last, + peripherals_aw_ready, + output peripherals_aw_valid, + output [1:0] peripherals_aw_bits_id, + output [30:0] peripherals_aw_bits_addr, + output [7:0] peripherals_aw_bits_len, + output [2:0] peripherals_aw_bits_size, + output [1:0] peripherals_aw_bits_burst, + output peripherals_aw_bits_lock, + output [3:0] peripherals_aw_bits_cache, + output [2:0] peripherals_aw_bits_prot, + output [3:0] peripherals_aw_bits_qos, + input peripherals_w_ready, + output peripherals_w_valid, + output [63:0] peripherals_w_bits_data, + output [7:0] peripherals_w_bits_strb, + output peripherals_w_bits_last, + peripherals_b_ready, + input peripherals_b_valid, + input [1:0] peripherals_b_bits_id, + peripherals_b_bits_resp, + input peripherals_ar_ready, + output peripherals_ar_valid, + output [1:0] peripherals_ar_bits_id, + output [30:0] peripherals_ar_bits_addr, + output [7:0] peripherals_ar_bits_len, + output [2:0] peripherals_ar_bits_size, + output [1:0] peripherals_ar_bits_burst, + output peripherals_ar_bits_lock, + output [3:0] peripherals_ar_bits_cache, + output [2:0] peripherals_ar_bits_prot, + output [3:0] peripherals_ar_bits_qos, + output peripherals_r_ready, + input peripherals_r_valid, + input [1:0] peripherals_r_bits_id, + input [63:0] peripherals_r_bits_data, + input [1:0] peripherals_r_bits_resp, + input peripherals_r_bits_last +); + assign memory_aw_valid = '0; + assign memory_aw_bits_id = '0; + assign memory_aw_bits_addr = '0; + assign memory_aw_bits_len = '0; + assign memory_aw_bits_size = '0; + assign memory_aw_bits_burst = '0; + assign memory_aw_bits_lock = '0; + assign memory_aw_bits_cache = '0; + assign memory_aw_bits_prot = '0; + assign memory_aw_bits_qos = '0; + assign memory_w_valid = '0; + assign memory_w_bits_data = '0; + assign memory_w_bits_strb = '0; + assign memory_w_bits_last = '0; + assign memory_b_ready = '0; + assign memory_ar_valid = '0; + assign memory_ar_bits_id = '0; + assign memory_ar_bits_addr = '0; + assign memory_ar_bits_len = '0; + assign memory_ar_bits_size = '0; + assign memory_ar_bits_burst = '0; + assign memory_ar_bits_lock = '0; + assign memory_ar_bits_cache = '0; + assign memory_ar_bits_prot = '0; + assign memory_ar_bits_qos = '0; + assign memory_r_ready = '0; + assign peripherals_aw_valid = '0; + assign peripherals_aw_bits_id = '0; + assign peripherals_aw_bits_addr = '0; + assign peripherals_aw_bits_len = '0; + assign peripherals_aw_bits_size = '0; + assign peripherals_aw_bits_burst = '0; + assign peripherals_aw_bits_lock = '0; + assign peripherals_aw_bits_cache = '0; + assign peripherals_aw_bits_prot = '0; + assign peripherals_aw_bits_qos = '0; + assign peripherals_w_valid = '0; + assign peripherals_w_bits_data = '0; + assign peripherals_w_bits_strb = '0; + assign peripherals_w_bits_last = '0; + assign peripherals_b_ready = '0; + assign peripherals_ar_valid = '0; + assign peripherals_ar_bits_id = '0; + assign peripherals_ar_bits_addr = '0; + assign peripherals_ar_bits_len = '0; + assign peripherals_ar_bits_size = '0; + assign peripherals_ar_bits_burst = '0; + assign peripherals_ar_bits_lock = '0; + assign peripherals_ar_bits_cache = '0; + assign peripherals_ar_bits_prot = '0; + assign peripherals_ar_bits_qos = '0; + assign peripherals_r_ready = '0; +endmodule diff --git a/platforms/arty-a7-toy/tests/check_fpu_shared.py b/platforms/arty-a7-toy/tests/check_fpu_shared.py index 130245f..3342ecb 100644 --- a/platforms/arty-a7-toy/tests/check_fpu_shared.py +++ b/platforms/arty-a7-toy/tests/check_fpu_shared.py @@ -1,5 +1,6 @@ """Execute original-FMA oracle vectors as real H/S/D Rocket instructions.""" +import argparse import hashlib import json from pathlib import Path @@ -8,6 +9,11 @@ import re ROOT = Path(__file__).resolve().parents[1] +parser = argparse.ArgumentParser(description=__doc__) +parser.add_argument("--baseline-core", type=Path, + default=ROOT.parent / "toy-a7-all-dsp-20261010/build/serial-bound", + help="含 ToyLinuxChip.sv 和 FpgaMemories.sv 的原独立 FMA 核心目录") +args = parser.parse_args() out = ROOT / "build/fpu-shared" out.mkdir(parents=True, exist_ok=True) vectors = ROOT / "build/fma-check/vectors.csv" @@ -78,7 +84,7 @@ "--output-dir", str(out / "simulation"), "--label", "whole Toy shared FPU 1536 oracle vectors"], check=True) baseline_output = out / "baseline-simulation" subprocess.run([sys.executable, str(ROOT / "tests/check_cpu_smoke.py"), "--program-elf", str(elf), - "--core-dir", str(ROOT.parent / "toy-a7-all-dsp-20261010/build/serial-bound"), + "--core-dir", str(args.baseline_core), "--output-dir", str(baseline_output), "--label", "whole Toy baseline FPU 1536 oracle vectors"], check=True) def measures(path): log = (path / "simulation.log").read_text() diff --git a/platforms/arty-a7-toy/tests/flash_guard_probe.py b/platforms/arty-a7-toy/tests/flash_guard_probe.py new file mode 100644 index 0000000..7931bfb --- /dev/null +++ b/platforms/arty-a7-toy/tests/flash_guard_probe.py @@ -0,0 +1,37 @@ +"""隔离进程内替代编程边界，确保测试永不访问串口或启动 Vivado。""" + +import json +from pathlib import Path +import runpy +import sys +import types + + +class ProgrammingBoundary(Exception): + pass + + +class OfflineObserver: + def __init__(self, *args, **kwargs): + raise ProgrammingBoundary("Guard accepted the valid image") + + +fake = types.ModuleType("observe_flash_boot") +fake.Observer = OfflineObserver +sys.modules["observe_flash_boot"] = fake +script, bit, payload, mcs, out, expected = sys.argv[1:] +sys.argv = [script, "--bitstream", bit, "--payload", payload, "--mcs", mcs, + "--part", "mt25ql128-spi-x1_x2_x4", "--port", "OFFLINE_NO_DEVICE", + "--vivado", "OFFLINE_NO_VIVADO", "--out", out] +try: + runpy.run_path(script, run_name="__main__") +except ValueError as error: + if expected != "reject": + raise + print("PASS INVALID_IMAGE_BLOCKED", str(error)) +except ProgrammingBoundary: + if expected != "accept": + raise + print("PASS VALID_IMAGE_REACHED_OFFLINE_BOUNDARY") +else: + raise RuntimeError("Missing verification boundary") diff --git a/platforms/arty-a7-toy/tests/mmio_error.S b/platforms/arty-a7-toy/tests/mmio_error.S new file mode 100644 index 0000000..43d197e --- /dev/null +++ b/platforms/arty-a7-toy/tests/mmio_error.S @@ -0,0 +1,49 @@ +.option norvc +.option norelax +.section .text.init,"ax",@progbits +.globl _start +_start: + la t0, trap_handler + csrw mtvec, t0 + csrw medeleg, zero + csrw mie, zero + li s1, 0 + li t0, 0x60030000 + sd zero, 0(t0) + fence iorw, iorw + ld t1, 0(t0) + fence iorw, iorw + # Record synchronous traps without assuming the cache supplies them. + li t0, 0x60000000 + li t1, 0x74000000 + or t1, t1, s1 + sd t1, 0(t0) + li t0, 0x60000000 + li t1, 0x600d600d + sd t1, 0(t0) +1: j 1b + +.balign 4 +trap_handler: + csrr a0, mcause + li a2, 5 + beq a0, a2, check_address + li a2, 7 + bne a0, a2, fail +check_address: + csrr a1, mtval + beqz a1, resume + li a2, 0x60030000 + bne a1, a2, fail +resume: + addi s1, s1, 1 + csrr a0, mepc + addi a0, a0, 4 + csrw mepc, a0 + mret + +fail: + li t0, 0x60000000 + li t1, 0xbad00007 + sd t1, 0(t0) +2: j 2b diff --git a/platforms/arty-a7-toy/tests/mock_programming.tcl b/platforms/arty-a7-toy/tests/mock_programming.tcl new file mode 100644 index 0000000..7efa6f7 --- /dev/null +++ b/platforms/arty-a7-toy/tests/mock_programming.tcl @@ -0,0 +1,71 @@ +# Offline API contract fixture. Never load Vivado or connect to hardware. +lassign $argv script fault bitfile backup +set events {} +proc event {name} {lappend ::events $name} +proc open_hw_manager {} {} +proc connect_hw_server {args} {} +proc get_hw_targets {args} {return target_0} +proc open_hw_target {args} {} +proc get_hw_devices {args} {return xc7a100t_0} +proc current_hw_device {args} {} +proc get_cfgmem_parts {args} {return mt25ql128-spi-x1_x2_x4} +proc create_hw_cfgmem {args} {} +proc create_hw_bitstream {args} {} +proc set_property {args} {} +proc refresh_hw_device {args} {} +proc close_hw_target {} {} +proc disconnect_hw_server {} {} +proc close_hw_manager {} {} +proc program_hw_devices {args} { + event program_device + if {$::fault eq "device_error"} {error "injected programming exception"} + return xc7a100t_0 +} +proc get_property {name device} { + switch -- $name { + PROGRAM.HW_CFGMEM {return cfgmem_0} + PROGRAM.HW_CFGMEM_BITFILE {return bridge.bit} + REGISTER.CONFIG_STATUS.BIT14_DONE_PIN {return [expr {$::fault ne "done_low"}]} + REGISTER.CONFIG_STATUS.BIT04_END_OF_STARTUP_(EOS)_STATUS {return [expr {$::fault ne "eos_low"}]} + REGISTER.CONFIG_STATUS.BIT00_CRC_ERROR {return [expr {$::fault eq "crc_error"}]} + REGISTER.CONFIG_STATUS {return {DONE=1 EOS=1 CRC=0}} + default {error "Unexpected property: $name"} + } +} +proc readback_hw_cfgmem {args} { + event readback + if {$::fault eq "readback_error"} {error "injected readback exception"} + set path [lindex $args [expr {[lsearch -exact $args -file]+1}]] + set f [open $path wb] + set bytes [expr {$::fault eq "short_backup" ? 127 : 16777216}] + seek $f [expr {$bytes-1}] + puts -nonewline $f "\0" + close $f + return "" +} +proc program_hw_cfgmem {args} { + event program_flash + if {$::fault eq "cfgmem_error"} {error "injected Flash verify exception"} + return "Program and verification completed" +} +proc boot_hw_device {args} {event boot; return 1} + +# Replace exit so source can report its result without killing this fixture. +rename exit fixture_exit +proc exit {args} {return} +set part mt25ql128-spi-x1_x2_x4 +switch -- [file tail $script] { + program_arty.tcl {set argv [list $bitfile]} + backup_flash.tcl {set argv [list $part $backup]} + program_flash.tcl {set argv [list $bitfile $part $backup]} + default {error "Unexpected script"} +} +set argc [llength $argv] +set code [catch {source $script} message] +puts "MOCK_EVENTS $events" +if {$code} { + puts "MOCK_FAILURE $message" + fixture_exit 1 +} +puts "MOCK_SUCCESS" +fixture_exit 0 diff --git a/platforms/arty-a7-toy/tests/tb_globalrob.sv b/platforms/arty-a7-toy/tests/tb_globalrob.sv new file mode 100644 index 0000000..8213b7d --- /dev/null +++ b/platforms/arty-a7-toy/tests/tb_globalrob.sv @@ -0,0 +1,29 @@ +`timescale 1ns/1ps +module tb; + reg clock = 0, reset = 1; + reg [31:0] seed = 32'h12345678; + wire passed; + integer cycles = 0; + GlobalRobCheck dut(.*); + always #5 clock = ~clock; + initial begin + repeat (5) @(negedge clock); + reset = 0; + repeat (1200) @(negedge clock); + reset = 1; seed = 32'hda7a0319; + repeat (5) @(negedge clock); + reset = 0; + repeat (1800) @(negedge clock); + reset = 1; seed = 32'habcdef01; + repeat (5) @(negedge clock); + reset = 0; + end + always @(posedge clock) begin + cycles <= cycles + 1; + if (!reset && passed) begin + $display("PASS GLOBALROB RAM/register cycle comparison, payloads, wrap, stalls, resets cycles=%0d", cycles); + $finish; + end + if (cycles > 15000) $fatal(1, "GlobalROB test timeout"); + end +endmodule diff --git a/platforms/arty-a7-toy/tests/tb_platform_bresp.sv b/platforms/arty-a7-toy/tests/tb_platform_bresp.sv new file mode 100644 index 0000000..f3c0490 --- /dev/null +++ b/platforms/arty-a7-toy/tests/tb_platform_bresp.sv @@ -0,0 +1,58 @@ +`timescale 1ns/1ps +module tb_platform_bresp; + reg clk=0; + always #5 clk=~clk; + reg reset=1; + reg [30:0] address=0; + reg [2:0] size=2; + reg [7:0] length=0; + reg awvalid=0,wvalid=0,last=1,bready=0; + toy_a7_platform dut(.clk(clk),.reset(reset),.uart_rx_in(1'b1), + .ddr_awready(1'b1),.ddr_wready(1'b1),.ddr_bid(4'd0),.ddr_bresp(2'd0),.ddr_bvalid(1'b0), + .ddr_arready(1'b1),.ddr_rid(4'd0),.ddr_rdata(128'd0),.ddr_rresp(2'd0),.ddr_rlast(1'b1),.ddr_rvalid(1'b0), + .flash_miso(1'b0),.flash_recovery(1'b0)); + task automatic write_case(input [30:0] addr,input [2:0] width,input [7:0] len,input [1:0] expected); + @(negedge clk);address=addr;size=width;length=len;awvalid=1; + do @(posedge clk);while(!dut.peripherals_aw_ready); + @(negedge clk);awvalid=0; + for(integer beat=0;beat<=len;beat=beat+1) begin + wvalid=1;last=beat==len; + do @(posedge clk);while(!dut.peripherals_w_ready); + @(negedge clk);wvalid=0; + end + while(!dut.peripherals_b_valid) @(negedge clk); + repeat(5) begin + // Observe the CPU input, through actual platform wiring and real SCU. + if(dut.chip.peripherals_b_valid!==1 || dut.chip.peripherals_b_bits_resp!==expected || + dut.chip.peripherals_b_bits_id!==2) + $fatal(1,"Platform B response addr=%h valid=%b id=%b actual=%b expected=%b",addr, + dut.chip.peripherals_b_valid,dut.chip.peripherals_b_bits_id,dut.chip.peripherals_b_bits_resp,expected); + @(negedge clk); + end + bready=1;@(negedge clk);bready=0; + if(dut.chip.peripherals_b_valid!==0) $fatal(1,"BVALID not cleared after handshake"); + endtask + initial begin + force dut.cpu_run=1; + force dut.peripherals_aw_valid=awvalid; + force dut.peripherals_aw_bits_addr=address; + force dut.peripherals_aw_bits_size=size; + force dut.peripherals_aw_bits_len=length; + force dut.peripherals_aw_bits_id=2; + force dut.peripherals_aw_bits_burst=1; + force dut.peripherals_w_valid=wvalid; + force dut.peripherals_w_bits_last=last; + force dut.peripherals_w_bits_data=64'h13572468; + force dut.peripherals_w_bits_strb=8'h0f; + force dut.peripherals_b_ready=bready; + repeat(5) @(negedge clk);reset=0; + write_case(31'h60000000,2,0,0); + if(!dut.exited || dut.exit_code!==32'h13572468) $fatal(1,"Valid MMIO changed"); + write_case(31'h60030000,2,0,2); + write_case(31'h60000002,2,0,2); + write_case(31'h60000000,2,1,2); + $display("PASS platform AXI B response: valid, invalid address, unaligned, burst, ID and backpressure"); + $finish; + end + initial begin #100000;$fatal(1,"Platform response watchdog");end +endmodule